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[83.57.172.194]) by smtp.gmail.com with ESMTPSA id x25sm27360980wmc.3.2021.01.03.05.04.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 03 Jan 2021 05:04:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 0/5] hw: Use PCI macros from 'hw/pci/pci.h' To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-ppc@nongnu.org, qemu-trivial@nongnu.org, Paul Durrant , Aurelien Jarno , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Jiaxun Yang , Yoshinori Sato , =?UTF-8?Q?C=c3=a9dric_Le_Goate?= =?UTF-8?Q?r?= , David Gibson , Stefano Stabellini , Helge Deller , Anthony Perard , Richard Henderson , Aleksandar Markovic , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Marcel Apfelbaum , Mark Cave-Ayland , Paolo Bonzini , Huacai Chen , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20201012124506.3406909-1-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <04b12adf-39ad-dc19-0458-74b0db809a95@amsat.org> Date: Sun, 3 Jan 2021 14:04:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20201012124506.3406909-1-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.262, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Jan 2021 13:05:01 -0000 On 10/12/20 2:45 PM, Philippe Mathieu-Daudé wrote: > Trivial patches using the generic PCI macros from "hw/pci/pci.h". > > Philippe Mathieu-Daudé (5): > hw/pci-host/bonito: Make PCI_ADDR() macro more readable > hw/pci-host: Use the PCI_BUILD_BDF() macro from 'hw/pci/pci.h' > hw/pci-host/uninorth: Use the PCI_FUNC() macro from 'hw/pci/pci.h' > hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h' > hw: Use the PCI_DEVFN() macro from 'hw/pci/pci.h' As this series are trivial and Acked, I'm going to queue it via the mips-tree, as other reviewed patches depend on it. Thanks, Phil. From MAILER-DAEMON Mon Jan 04 04:32:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwMEA-0008B8-Ve for mharc-qemu-arm@gnu.org; Mon, 04 Jan 2021 04:32:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwME9-00088N-Et for qemu-arm@nongnu.org; Mon, 04 Jan 2021 04:32:37 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:36752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kwME6-0000cr-Bq for qemu-arm@nongnu.org; Mon, 04 Jan 2021 04:32:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1609752752; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HxTr71QZaT90y8c2vL2GVs5Sp2A5X0ewvCwxjpolVVQ=; b=NHK+gnlrU8EKoI41UYBKe5QrUiHgBVPTSxUAMMVwelG/Epygvbi5U8ydwZDREQ1zhqsqt3 RFyp/aeUkxc2v7O2L0/pFWJi+LHkovUbSJwLoqdHcPaOGlzp+bPf5FOVotu7f44w7Y+sja h7fJcE/iQvKfwFJ1c81LMPKp2n4U1EM= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-218-qY9vbJxBN5GUS_CwYm35vQ-1; Mon, 04 Jan 2021 04:32:31 -0500 X-MC-Unique: qY9vbJxBN5GUS_CwYm35vQ-1 Received: by mail-wm1-f71.google.com with SMTP id w204so10290148wmb.1 for ; Mon, 04 Jan 2021 01:32:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=tn7hDzxpKrM1swuwnw3aSgEMZIORK6hhOk9QF/UxR54=; b=CO38DOVo3tTDRPVktUB/GVFZqwDwqS4q0OlXHuSzBcDEoZZm61JWcXB2fa3C2bsyBv 6D8ouzkgJdgiHo1LwT03Qj9K2iWlh0d0i8gAnq2xJUazlBXc6YFEsDqDYtnfdutNCxtb OfSq6E6vxGmEYIfjwAWBh3h/P4dqhFYMmOyq+lYxUnz2DrwAlXmdplHSUI5MEqx5BV4O tQEzTJRTV3ht/7dOBxWn/l6hUzEbwc4eeg65j+mzSNO0ciP9RPRafQKDX6+/3m1Htrge L3DHnMzmXstHlVMtMPgcXItrUTfjo1mjjbZuV5X6rZqQ/8LP+VPvdOx1pV3ExA1h4HQU URsg== X-Gm-Message-State: AOAM533uWJYpQP8sx7K7OezKh8XAtB8sO6eXKllY62j1uJgZ64rkdXF8 On9oL/wslsUSrZVSppRxCabKsgTzybx7vYpLsSiuemmQcuhMKIHUPZJEF+Y1DA+VplcwW66Q098 R8s4z8AEVjo2v X-Received: by 2002:a05:6000:10c4:: with SMTP id b4mr80539874wrx.170.1609752750033; Mon, 04 Jan 2021 01:32:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJx4JuLN6jtROkA0DcLhevcSrtv/oKG8Fo13+2fbLpVuH3BNDwBHHvd1SgSdxKPaKWu9HdWnpw== X-Received: by 2002:a05:6000:10c4:: with SMTP id b4mr80539832wrx.170.1609752749696; Mon, 04 Jan 2021 01:32:29 -0800 (PST) Received: from redhat.com (bzq-79-178-32-166.red.bezeqint.net. [79.178.32.166]) by smtp.gmail.com with ESMTPSA id n9sm88912868wrq.41.2021.01.04.01.32.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 01:32:28 -0800 (PST) Date: Mon, 4 Jan 2021 04:32:25 -0500 From: "Michael S. Tsirkin" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, qemu-trivial@nongnu.org, Paul Durrant , Aurelien Jarno , qemu-arm@nongnu.org, Eduardo Habkost , Jiaxun Yang , Yoshinori Sato , =?iso-8859-1?Q?C=E9dric?= Le Goater , David Gibson , Stefano Stabellini , Helge Deller , Anthony Perard , Richard Henderson , Aleksandar Markovic , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Marcel Apfelbaum , Mark Cave-Ayland , Paolo Bonzini , Huacai Chen , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 0/5] hw: Use PCI macros from 'hw/pci/pci.h' Message-ID: <20210104043218-mutt-send-email-mst@kernel.org> References: <20201012124506.3406909-1-philmd@redhat.com> <04b12adf-39ad-dc19-0458-74b0db809a95@amsat.org> MIME-Version: 1.0 In-Reply-To: <04b12adf-39ad-dc19-0458-74b0db809a95@amsat.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jan 2021 09:32:37 -0000 On Sun, Jan 03, 2021 at 02:04:53PM +0100, Philippe Mathieu-Daudé wrote: > On 10/12/20 2:45 PM, Philippe Mathieu-Daudé wrote: > > Trivial patches using the generic PCI macros from "hw/pci/pci.h". > > > > Philippe Mathieu-Daudé (5): > > hw/pci-host/bonito: Make PCI_ADDR() macro more readable > > hw/pci-host: Use the PCI_BUILD_BDF() macro from 'hw/pci/pci.h' > > hw/pci-host/uninorth: Use the PCI_FUNC() macro from 'hw/pci/pci.h' > > hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h' > > hw: Use the PCI_DEVFN() macro from 'hw/pci/pci.h' > > As this series are trivial and Acked, I'm going to queue > it via the mips-tree, as other reviewed patches depend > on it. > > Thanks, > > Phil. Fine. Acked-by: Michael S. Tsirkin From MAILER-DAEMON Mon Jan 04 07:08:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwOfE-0003Gs-UW for mharc-qemu-arm@gnu.org; Mon, 04 Jan 2021 07:08:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwOfD-0003Gi-A8; Mon, 04 Jan 2021 07:08:43 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:60554 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kwOf9-0002xT-Mq; Mon, 04 Jan 2021 07:08:43 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id 591405FC99; Mon, 4 Jan 2021 13:08:34 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 03/18] target/arm: use arm_is_el2_enabled() where applicable Date: Mon, 04 Jan 2021 14:08:31 +0200 Message-ID: <5669299.lOV4Wx5bFT@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: <6f114b65-e6e8-e9a2-41f0-c3fda14680d0@linaro.org> References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-3-remi.denis.courmont@huawei.com> <6f114b65-e6e8-e9a2-41f0-c3fda14680d0@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jan 2021 12:08:43 -0000 Le maanantaina 21. joulukuuta 2020, 22.54.08 EET Richard Henderson a =C3=A9= crit : > On 12/18/20 2:37 AM, remi.denis.courmont@huawei.com wrote: > > From: R=C3=A9mi Denis-Courmont > >=20 > > Do not assume that EL2 is available in non-secure context. >=20 > Just noticed this wording is off. Should be > "Do not assume that EL2 is unavailable in a secure context" It would be clearer, but I'd hate to rereresend the patchset just for this. Indeed, the second sentence clarifies that this was meant reciprocally, i.e= =2E=20 that it should not be assumed that EL2 is always and only available in non- secure context: > > That equivalence is broken by ARMv8.4-SEL2. > >=20 > > Signed-off-by: R=C3=A9mi Denis-Courmont > > Reviewed-by: Richard Henderson > > --- > >=20 > > target/arm/cpu.h | 4 ++-- > > target/arm/helper-a64.c | 8 +------- > > target/arm/helper.c | 33 +++++++++++++-------------------- > > 3 files changed, 16 insertions(+), 29 deletions(-) =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Mon Jan 04 17:10:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwY3Y-0005OX-MO for mharc-qemu-arm@gnu.org; Mon, 04 Jan 2021 17:10:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwY3X-0005OM-Os for qemu-arm@nongnu.org; Mon, 04 Jan 2021 17:10:27 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:31865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kwY3W-0007DE-6p for qemu-arm@nongnu.org; Mon, 04 Jan 2021 17:10:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1609798225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+B+r0+4aZaYYBaD8upICaTg7dnMjcQT09LwD9q+xk6I=; b=UBxhZG45TMF/96x06er/EcEMxqSNh5o/Z8gejbhAO0Hyw8lfk/0e3JbKMH0GrKHSwWKJ94 lFRYO3iT4RDddR591qYqj8alTQrX6gBUzh+7Z9SIsF5B/DSMmohQbwr+/JsvvpqBT57Lho a+xo1jPo9xf4tFQKjP+enNtzWJ1MMTw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-417-ycQTF7KoNlGtDn5EJgAHLQ-1; Mon, 04 Jan 2021 17:10:19 -0500 X-MC-Unique: ycQTF7KoNlGtDn5EJgAHLQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E9B7A107B45F; Mon, 4 Jan 2021 22:10:17 +0000 (UTC) Received: from localhost (ovpn-116-153.rdu2.redhat.com [10.10.116.153]) by smtp.corp.redhat.com (Postfix) with ESMTP id 28D2E5D9D5; Mon, 4 Jan 2021 22:10:14 +0000 (UTC) Date: Mon, 4 Jan 2021 17:10:13 -0500 From: Eduardo Habkost To: Igor Mammedov Cc: qemu-devel@nongnu.org, Peter Maydell , "Daniel P. Berrange" , "Michael S. Tsirkin" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson , Michael Roth , Markus Armbruster , qemu-arm@nongnu.org, Paolo Bonzini , Laszlo Ersek Subject: Re: [PATCH v2 0/3] pc: Support configuration of SMBIOS entry point type Message-ID: <20210104221013.GK18467@habkost.net> References: <20201214205029.2991222-1-ehabkost@redhat.com> <20201229142001.3b28fdf2@redhat.com> MIME-Version: 1.0 In-Reply-To: <20201229142001.3b28fdf2@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.243, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jan 2021 22:10:28 -0000 On Tue, Dec 29, 2020 at 02:20:01PM +0100, Igor Mammedov wrote: > On Mon, 14 Dec 2020 15:50:26 -0500 > Eduardo Habkost wrote: > > > This includes code previously submitted[1] by Daniel P. Berrangé > > to add a "smbios-ep" machine property on PC. > > > > SMBIOS 3.0 is necessary to support more than ~720 VCPUs, as a > > large number of VCPUs can easily hit the table size limit of > > SMBIOS 2.1 entry points. > > Eduardo, > do you plan to submit Seabios patches for SMBIOS 3.0? > will OVMF pick up new tables automatically? OVMF will pick the new tables automatically. SeaBIOS patches are at: https://www.mail-archive.com/search?l=mid&q=20201210212640.2023885-1-ehabkost@redhat.com -- Eduardo From MAILER-DAEMON Mon Jan 04 17:45:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwYaz-0007OS-V0 for mharc-qemu-arm@gnu.org; Mon, 04 Jan 2021 17:45:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwYaw-0007Lp-QR for qemu-arm@nongnu.org; Mon, 04 Jan 2021 17:44:58 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:54030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kwYas-0002ua-Th for qemu-arm@nongnu.org; Mon, 04 Jan 2021 17:44:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1609800293; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DPSU4RfLlMfVmTuHkZt3krQO84SIfrjmyUkgiA27jE8=; b=X/uJ8EkiP3tJgWJk+7Fz0JwEqudg8wjyP4uXsn3ufTfuopuj4X2irznhF8yTN7voKoF6H9 vLt+KuxCerHsqn9ufBrMgx2YzxFYkTpolkkYMtzuEJOiY/K7uiomfYvAF7ufxQtBkf02W5 X3bTBeqJ7152m9XFtw8DDaNs7RR9ymw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-377-50gZDxyPOpC1L-ahRxkO0Q-1; Mon, 04 Jan 2021 17:44:50 -0500 X-MC-Unique: 50gZDxyPOpC1L-ahRxkO0Q-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A208D801A9D; Mon, 4 Jan 2021 22:44:48 +0000 (UTC) Received: from localhost (unknown [10.40.208.13]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9438610027A5; Mon, 4 Jan 2021 22:44:42 +0000 (UTC) Date: Mon, 4 Jan 2021 23:44:40 +0100 From: Igor Mammedov To: Eduardo Habkost Cc: qemu-devel@nongnu.org, Peter Maydell , "Daniel P. Berrange" , "Michael S. Tsirkin" , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= , Richard Henderson , Michael Roth , Markus Armbruster , qemu-arm@nongnu.org, Paolo Bonzini , Laszlo Ersek Subject: Re: [PATCH v2 3/3] hw/i386: expose a "smbios-ep" PC machine property Message-ID: <20210104234440.2da6c503@redhat.com> In-Reply-To: <20201214205029.2991222-4-ehabkost@redhat.com> References: <20201214205029.2991222-1-ehabkost@redhat.com> <20201214205029.2991222-4-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.243, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jan 2021 22:44:59 -0000 On Mon, 14 Dec 2020 15:50:29 -0500 Eduardo Habkost wrote: > From: Daniel P. Berrang=C3=A9 >=20 > The i440fx and Q35 machine types are both hardcoded to use the legacy > SMBIOS 2.1 entry point. This is a sensible conservative choice because > SeaBIOS only supports SMBIOS 2.1 >=20 > EDK2, however, can also support SMBIOS 3.0 and QEMU already uses this on > the ARM virt machine type. >=20 > This adds a property to allow the choice of SMBIOS entry point versions > For example to opt in to version 3.0 >=20 > $QEMU -machine q35,smbios-ep=3D3_0 >=20 > Signed-off-by: Daniel P. Berrang=C3=A9 > Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov > --- > This is patch was previously submitted at: > https://lore.kernel.org/qemu-devel/20200908165438.1008942-6-berrange@redh= at.com >=20 > Changes from v1: > * Include qapi-visit-smbios.h instead of qapi-visit-machine.h > * Commit message fix: s/smbios_ep/smbios-ep/ > --- > include/hw/i386/pc.h | 3 +++ > hw/i386/pc.c | 26 ++++++++++++++++++++++++++ > hw/i386/pc_piix.c | 2 +- > hw/i386/pc_q35.c | 2 +- > 4 files changed, 31 insertions(+), 2 deletions(-) >=20 > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index 2aa8797c6e..2075093b32 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -11,6 +11,7 @@ > #include "hw/acpi/acpi_dev_interface.h" > #include "hw/hotplug.h" > #include "qom/object.h" > +#include "hw/firmware/smbios.h" > =20 > #define HPET_INTCAP "hpet-intcap" > =20 > @@ -38,6 +39,7 @@ typedef struct PCMachineState { > /* Configuration options: */ > uint64_t max_ram_below_4g; > OnOffAuto vmport; > + SmbiosEntryPointType smbios_ep; > =20 > bool acpi_build_enabled; > bool smbus_enabled; > @@ -62,6 +64,7 @@ typedef struct PCMachineState { > #define PC_MACHINE_SATA "sata" > #define PC_MACHINE_PIT "pit" > #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" > +#define PC_MACHINE_SMBIOS_EP "smbios-ep" > =20 > /** > * PCMachineClass: > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 640fb5b0b7..3cc559e0d9 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -81,6 +81,7 @@ > #include "hw/mem/nvdimm.h" > #include "qapi/error.h" > #include "qapi/qapi-visit-common.h" > +#include "qapi/qapi-visit-smbios.h" > #include "qapi/visitor.h" > #include "hw/core/cpu.h" > #include "hw/usb.h" > @@ -1532,6 +1533,23 @@ static void pc_machine_set_hpet(Object *obj, bool = value, Error **errp) > pcms->hpet_enabled =3D value; > } > =20 > +static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char= *name, > + void *opaque, Error **errp) > +{ > + PCMachineState *pcms =3D PC_MACHINE(obj); > + SmbiosEntryPointType smbios_ep =3D pcms->smbios_ep; > + > + visit_type_SmbiosEntryPointType(v, name, &smbios_ep, errp); > +} > + > +static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char= *name, > + void *opaque, Error **errp) > +{ > + PCMachineState *pcms =3D PC_MACHINE(obj); > + > + visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_ep, errp); > +} > + > static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, > const char *name, void *opaq= ue, > Error **errp) > @@ -1621,6 +1639,8 @@ static void pc_machine_initfn(Object *obj) > pcms->vmport =3D ON_OFF_AUTO_OFF; > #endif /* CONFIG_VMPORT */ > pcms->max_ram_below_4g =3D 0; /* use default */ > + pcms->smbios_ep =3D SMBIOS_ENTRY_POINT_TYPE_2_1; > + > /* acpi build is enabled by default if machine supports it */ > pcms->acpi_build_enabled =3D PC_MACHINE_GET_CLASS(pcms)->has_acpi_bu= ild; > pcms->smbus_enabled =3D true; > @@ -1759,6 +1779,12 @@ static void pc_machine_class_init(ObjectClass *oc,= void *data) > NULL, NULL); > object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, > "Maximum combined firmware size"); > + > + object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", > + pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, > + NULL, NULL); > + object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, > + "SMBIOS Entry Point version [v2_1, v3_0]"); > } > =20 > static const TypeInfo pc_machine_info =3D { > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 08b82df4d1..30ae7f27af 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -179,7 +179,7 @@ static void pc_init1(MachineState *machine, > smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)", > mc->name, pcmc->smbios_legacy_mode, > pcmc->smbios_uuid_encoded, > - SMBIOS_ENTRY_POINT_TYPE_2_1); > + pcms->smbios_ep); > } > =20 > /* allocate ram and load rom/bios */ > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index f71b1e2dcf..9974426806 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -198,7 +198,7 @@ static void pc_q35_init(MachineState *machine) > smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", > mc->name, pcmc->smbios_legacy_mode, > pcmc->smbios_uuid_encoded, > - SMBIOS_ENTRY_POINT_TYPE_2_1); > + pcms->smbios_ep); > } > =20 > /* allocate ram and load rom/bios */ From MAILER-DAEMON Mon Jan 04 22:51:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwdNt-0001E0-V7 for mharc-qemu-arm@gnu.org; Mon, 04 Jan 2021 22:51:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwdNs-0001Bn-L9; Mon, 04 Jan 2021 22:51:48 -0500 Received: from mail-yb1-xb35.google.com ([2607:f8b0:4864:20::b35]:41116) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwdNr-0006Jb-1b; Mon, 04 Jan 2021 22:51:48 -0500 Received: by mail-yb1-xb35.google.com with SMTP id w127so28046841ybw.8; Mon, 04 Jan 2021 19:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7nz4pSBdnZxedE+I2ZOXRhBAJyTs41Fb/2bnB3jz19g=; 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Mon, 04 Jan 2021 19:51:45 -0800 (PST) MIME-Version: 1.0 References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> From: Bin Meng Date: Tue, 5 Jan 2021 11:51:34 +0800 Message-ID: Subject: Re: [PATCH v2 1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value To: Jean-Christophe Dubois , Peter Maydell , =?UTF-8?B?QWxleCBCZW5uw6ll?= , qemu-arm , "qemu-devel@nongnu.org Developers" Cc: Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 03:51:48 -0000 On Wed, Dec 23, 2020 at 2:26 PM Bin Meng wrote: > > From: Bin Meng > > U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap() > in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the > bandgap has stabilized. > > With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6 > sabrelite board (mx6qsabrelite_defconfig), with a slight change made > by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot > shell on QEMU with the following command: > > $ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \ > -display none -serial null -serial stdio > > Boot log below: > > U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800) > > CPU: Freescale i.MX?? rev1.0 at 792 MHz > Reset cause: POR > Model: Freescale i.MX6 Quad SABRE Lite Board > Board: SABRE Lite > I2C: ready > DRAM: 1 GiB > force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55 > force_idle_bus: failed to clear bus, sda=0 scl=0 > force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c > force_idle_bus: failed to clear bus, sda=0 scl=0 > force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5 > force_idle_bus: failed to clear bus, sda=0 scl=0 > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > Loading Environment from MMC... *** Warning - No block device, using default environment > > In: serial > Out: serial > Err: serial > Net: Board Net Initialization Failed > No ethernet found. > starting USB... > Bus usb@2184000: usb dr_mode not found > USB EHCI 1.00 > Bus usb@2184200: USB EHCI 1.00 > scanning bus usb@2184000 for devices... 1 USB Device(s) found > scanning bus usb@2184200 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found > scanning usb for ethernet devices... 0 Ethernet Device(s) found > Hit any key to stop autoboot: 0 > => > > Signed-off-by: Bin Meng > --- > > (no changes since v1) > > hw/misc/imx6_ccm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Ping? 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Tue, 05 Jan 2021 01:22:08 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j2sm94386754wrt.35.2021.01.05.01.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 01:22:07 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7AD761FF7E; Tue, 5 Jan 2021 09:22:06 +0000 (GMT) References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-5-git-send-email-bmeng.cn@gmail.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Bin Meng Cc: Jean-Christophe Dubois , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Bin Meng Subject: Re: [PATCH v2 4/4] docs/system: arm: Add sabrelite board description Date: Tue, 05 Jan 2021 09:21:38 +0000 In-reply-to: <1608704767-9317-5-git-send-email-bmeng.cn@gmail.com> Message-ID: <87turv3fi9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 09:22:12 -0000 Bin Meng writes: > From: Bin Meng > > This adds the target guide for SABRE Lite board, and documents how > to boot a Linux kernel and U-Boot bootloader. > > Signed-off-by: Bin Meng Awesome documentation =F0=9F=91=8F Reviewed-by: Alex Benn=C3=A9e > > --- > > Changes in v2: > - new patch: add sabrelite target guide > > docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++++= ++++++ > docs/system/target-arm.rst | 1 + > 2 files changed, 120 insertions(+) > create mode 100644 docs/system/arm/sabrelite.rst > > diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst > new file mode 100644 > index 0000000..4c5d101 > --- /dev/null > +++ b/docs/system/arm/sabrelite.rst > @@ -0,0 +1,119 @@ > +Boundary Devices SABRE Lite (``sabrelite``) > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost develo= pment > +platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Q= uad > +Applications Processor. > + > +Supported devices > +----------------- > + > +The SABRE Lite machine supports the following devices: > + > + * Up to 4 Cortex A9 cores > + * Generic Interrupt Controller > + * 1 Clock Controller Module > + * 1 System Reset Controller > + * 5 UARTs > + * 2 EPIC timers > + * 1 GPT timer > + * 2 Watchdog timers > + * 1 FEC ethernet controller > + * 3 I2C controllers > + * 7 GPIO controllers > + * 4 SDHC storage controllers > + * 4 USB 2.0 host controllers > + * 5 ECSPI controllers > + * 1 SST 25VF016B flash > + > +Please note above list is a complete superset the QEMU SABRE Lite machin= e can > +support. For a normal use case, a device tree blob that reprents a real = world > +SABRE Lite board, only exposes a subset of devices to the guest software. > + > +Boot options > +------------ > + > +The SABRE Lite machine can start using the standard -kernel functionality > +for loading a Linux kernel, U-Boot bootloader or ELF executable. > + > +Running Linux kernel > +-------------------- > + > +Linux mainline v5.10 release is tested at the time of writing. To build = a Linux > +mainline kernel that can be booted by the SABRE Lite machine, simply con= figure > +the kernel using the imx_v6_v7_defconfig configuration: > + > +.. code-block:: bash > + > + $ export ARCH=3Darm > + $ export CROSS_COMPILE=3Darm-linux-gnueabihf- > + $ make imx_v6_v7_defconfig > + $ make > + > +To boot the newly built Linux kernel in QEMU with the SABRE Lite machine= , use: > + > +.. code-block:: bash > + > + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ > + -display none -serial null -serial stdio \ > + -kernel arch/arm/boot/zImage \ > + -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \ > + -initrd /path/to/rootfs.ext4 \ > + -append "root=3D/dev/ram" > + > +Running U-Boot > +-------------- > + > +U-Boot mainline v2020.10 release is tested at the time of writing. To bu= ild a > +U-Boot mainline bootloader that can be booted by the SABRE Lite machine,= use > +the mx6qsabrelite_defconfig with similar commands as described above for= Linux: > + > +.. code-block:: bash > + > + $ export CROSS_COMPILE=3Darm-linux-gnueabihf- > + $ make mx6qsabrelite_defconfig > + > +Note we need to adjust settings by: > + > +.. code-block:: bash > + > + $ make menuconfig > + > +then manually select the following configuration in U-Boot: > + > + Device Tree Control > Provider of DTB for DT Control > Embedded DTB > + > +To start U-Boot using the SABRE Lite machine, provide the u-boot binary = to > +the -kernel argument, along with an SD card image with rootfs: > + > +.. code-block:: bash > + > + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ > + -display none -serial null -serial stdio \ > + -kernel u-boot > + > +The following example shows booting Linux kernel from dhcp, and uses the > +rootfs on an SD card. This requies some additional command line paramete= rs > +for QEMU: > + > +.. code-block:: none > + > + -nic user,tftp=3D/path/to/kernel/zImage \ > + -drive file=3Dsdcard.img,id=3Drootfs -device sd-card,drive=3Drootfs > + > +The directory for the built-in TFTP server should also contain the devic= e tree > +blob of the SABRE Lite board. The sample SD card image was populated wit= h the > +root file system with one single partition. You may adjust the kernel "r= oot=3D" > +boot parameter accordingly. > + > +After U-Boot boots, type the following commands in the U-Boot command sh= ell to > +boot the Linux kernel: > + > +.. code-block:: none > + > + =3D> setenv ethaddr 00:11:22:33:44:55 > + =3D> setenv bootfile zImage > + =3D> dhcp > + =3D> tftpboot 14000000 imx6q-sabrelite.dtb > + =3D> setenv bootargs root=3D/dev/mmcblk3p1 > + =3D> bootz 12000000 - 14000000 > diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst > index bde4b8e..edd013c 100644 > --- a/docs/system/target-arm.rst > +++ b/docs/system/target-arm.rst > @@ -83,6 +83,7 @@ undocumented; you can get a complete list by running > arm/versatile > arm/vexpress > arm/aspeed > + arm/sabrelite > arm/digic > arm/musicpal > arm/gumstix --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 05 04:23:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwiYV-0007EF-AL for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 04:23:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwiYR-0007D0-Hj for qemu-arm@nongnu.org; Tue, 05 Jan 2021 04:23:03 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:40888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwiYL-0008Nt-8T for qemu-arm@nongnu.org; Tue, 05 Jan 2021 04:23:03 -0500 Received: by mail-wm1-x329.google.com with SMTP id r4so2328539wmh.5 for ; Tue, 05 Jan 2021 01:22:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=BLgGujq8rqc7XcBFJuzNFY3EMhBseweZFBP6CpXMw4Y=; b=f6zxBgLM6gzV63gV4jzaK8mLLb50x9PB9Ac5v3046ZpyXHoj7ZbhbZs2jOmaleT7DI nOZvWQdAZI52qlNs4d9y15XCX7raVxLYxzLA2453Mra859R+9SpD8q2DfvntLTSZi1uT bRlNzxId7MR0Qc6gkvLBv9XndAl6WGJRP8VaKazaPredgCFEKzFH8XGbIip21dCaGGuC Sz/r+jTYm2ChFzkhm61Sps20gg1H7fb/aCGfEdFxbB3EkPv/cN10NX0BqYu89LFK3gNs LW3UXlpMGRDFJ5HP88xi3bO9NSpNWS17U1rIm/oOHaA12heotM6NmSRqKZEqKMIH4nIV J6kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=BLgGujq8rqc7XcBFJuzNFY3EMhBseweZFBP6CpXMw4Y=; b=lpnLzmpL4XFzzPxGLVqf6xYS0/ELW5s4tOYNv8eVoNGoq7aeKDGQsfNaWkjoamLfEM 0JTMCtLIsCahgKi7F2tHh6HOf8+//rQh1SIHnPTl+wUj225Pm4+5I+Tlf4aYeBVtpzkz 0UPzuoBpTAyBXphd1P10KhUvFiPsv28NhgYWlY7MFTOYxISH+Vyf4aPscQOalsdxJJuw Q8rDkF/GMZk0rjK2NoQlPw4vZMb0mYdgt9sRuGj+RAbmJdv1hmtjfmEQUdl36Bm13iwq /eVsFx+vs2NetemXVvq3YnQqZliZRXhcQauQQhkbwvthXTscCZaUW421NwFL+PimKHcO 12Tw== X-Gm-Message-State: AOAM530mxCXVhBfKATOm27l97iRLkgcAPt457/oe2Arko3QyzNdG6rBW 3WCD1o/ZYCQmbXN8QFlMYl7Vvw== X-Google-Smtp-Source: ABdhPJwwT/YWJkqHr9XACTrhC+zHYTbTE0HzYlwApDjgl7uzpTK2EoAUcY8qUMTMcZPFFJ7YxLo8qw== X-Received: by 2002:a1c:6144:: with SMTP id v65mr2552933wmb.125.1609838575593; Tue, 05 Jan 2021 01:22:55 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id i18sm97400899wrp.74.2021.01.05.01.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 01:22:53 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1EB201FF7E; Tue, 5 Jan 2021 09:22:53 +0000 (GMT) References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-3-git-send-email-bmeng.cn@gmail.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Bin Meng Cc: Jean-Christophe Dubois , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Bin Meng Subject: Re: [PATCH v2 2/4] hw/msic: imx6_ccm: Correct register value for silicon type Date: Tue, 05 Jan 2021 09:22:47 +0000 In-reply-to: <1608704767-9317-3-git-send-email-bmeng.cn@gmail.com> Message-ID: <87r1mz3fgy.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 09:23:05 -0000 Bin Meng writes: > From: Bin Meng > > Currently when U-Boot boots, it prints "??" for i.MX processor: > > CPU: Freescale i.MX?? rev1.0 at 792 MHz > > The register that was used to determine the silicon type is > undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we > can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in > the U-Boot source codes that USB_ANALOG_DIGPROG is used. > > Update its reset value to indicate i.MX6Q. > > Signed-off-by: Bin Meng Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 05 04:23:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwiZ4-0007Ub-AW for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 04:23:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwiYx-0007TR-T2 for qemu-arm@nongnu.org; Tue, 05 Jan 2021 04:23:37 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:41706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwiYu-00009A-SW for qemu-arm@nongnu.org; Tue, 05 Jan 2021 04:23:35 -0500 Received: by mail-wr1-x42c.google.com with SMTP id a12so35411075wrv.8 for ; Tue, 05 Jan 2021 01:23:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=l+lUEQuZFIcc0NWF7nlafJJcRfNM4V3YFWuroiahE3M=; b=uatrzF6NqStRIz07y+fxWdQ4YvH/lkpj5pQNAHnHPMRjcZzZr1xyALExT/YwuDFjFE yF9dClfLYtkvNqiXRLfeV+rxNvW8/p/6oAvpOc9wsdFd/ZcSvsraB8Vny4U1b2QILtkm PsKKFgOs5agDosKY6eBAb7m/3oYJUkDR9oeqj3q/e44ZBT07YWbLNZm9dSOoFw/SP+Oc 2a+yZ4re1zZvaf/ooMhoPy9uPrLX0X3V7afC5hUAjPCD2vzk+LwPS3o6jCuKyqLjLBxJ 7xD+4Tvlzh4u1JZuBeOZNmOXT3GdSTmgJZCsxLzMEknSn0XVLkKCjKOXhx9HYQO2pGJC H03Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=l+lUEQuZFIcc0NWF7nlafJJcRfNM4V3YFWuroiahE3M=; b=kU6cYdB5Qppxf4mJ9w4SL7juzV6ELs91MgamVq+RM94Yi7N8hYdiYVEkajUJQoi8bj KlXQCmWQtlKoCsjMsMas8VdZ3/n3PQQZSD0m05O3J05ltyjbCyP+wVAKQ+GLZR3UdHFr +jfALkmE7roIU9085kT395D+Ik5qIH2p6QGGmTnwOBgFdygu/rnKVZQn/dWSCuPGY1+Z vF1lxOd1bfKGp6Efbd2dXBJ7EdE5yLdmMwdxUxYsaX/m3XBr6W7O2WhgBOljalIcfVt1 Sswbcr0c+TEsrE9Zk20rA2X61FR/fVfiFLdvvFcRb+wEr8Jm+RsqWkrb0xzbrzfAN3t0 mXSQ== X-Gm-Message-State: AOAM5314J55MZCjrkONG/d/rYf0dAFcZqn6z061K87MvTvznvNGWHuDa UPL4mFeU0PA9fy//uqetnqXZYLXXjsi5bQ== X-Google-Smtp-Source: ABdhPJyTzgFMPXFI4iPff1fqZCmWelpCK/aB5/A+h3FO8f+1GS3J94BK5lnulVAiensBa8hRC9SK/w== X-Received: by 2002:adf:90e3:: with SMTP id i90mr59318858wri.248.1609838611543; Tue, 05 Jan 2021 01:23:31 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z63sm3565187wme.8.2021.01.05.01.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 01:23:30 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A9E9C1FF7E; Tue, 5 Jan 2021 09:23:29 +0000 (GMT) References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Bin Meng Cc: Jean-Christophe Dubois , Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Bin Meng Subject: Re: [PATCH v2 1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value Date: Tue, 05 Jan 2021 09:23:21 +0000 In-reply-to: <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> Message-ID: <87o8i33ffy.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 09:23:37 -0000 Bin Meng writes: > From: Bin Meng > > U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap() > in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the > bandgap has stabilized. > > With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6 > sabrelite board (mx6qsabrelite_defconfig), with a slight change made > by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot > shell on QEMU with the following command: > > $ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \ > -display none -serial null -serial stdio > > Boot log below: > > U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800) > > CPU: Freescale i.MX?? rev1.0 at 792 MHz > Reset cause: POR > Model: Freescale i.MX6 Quad SABRE Lite Board > Board: SABRE Lite > I2C: ready > DRAM: 1 GiB > force_idle_bus: sda=3D0 scl=3D0 sda.gp=3D0x5c scl.gp=3D0x55 > force_idle_bus: failed to clear bus, sda=3D0 scl=3D0 > force_idle_bus: sda=3D0 scl=3D0 sda.gp=3D0x6d scl.gp=3D0x6c > force_idle_bus: failed to clear bus, sda=3D0 scl=3D0 > force_idle_bus: sda=3D0 scl=3D0 sda.gp=3D0xcb scl.gp=3D0x5 > force_idle_bus: failed to clear bus, sda=3D0 scl=3D0 > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > Loading Environment from MMC... *** Warning - No block device, using de= fault environment > > In: serial > Out: serial > Err: serial > Net: Board Net Initialization Failed > No ethernet found. > starting USB... > Bus usb@2184000: usb dr_mode not found > USB EHCI 1.00 > Bus usb@2184200: USB EHCI 1.00 > scanning bus usb@2184000 for devices... 1 USB Device(s) found > scanning bus usb@2184200 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found > scanning usb for ethernet devices... 0 Ethernet Device(s) found > Hit any key to stop autoboot: 0 > =3D> > > Signed-off-by: Bin Meng Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 05 04:25:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwiat-0000eJ-NH for mharc-qemu-arm@gnu.org; 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Tue, 05 Jan 2021 01:25:25 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C2B0D1FF7E; Tue, 5 Jan 2021 09:25:24 +0000 (GMT) References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Bin Meng Cc: Jean-Christophe Dubois , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Subject: Re: [PATCH v2 1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value Date: Tue, 05 Jan 2021 09:23:41 +0000 In-reply-to: Message-ID: <87lfd73fcr.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 09:25:34 -0000 Bin Meng writes: > On Wed, Dec 23, 2020 at 2:26 PM Bin Meng wrote: >> >> From: Bin Meng >> >> >> (no changes since v1) >> >> hw/misc/imx6_ccm.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> > > Ping? Looks good to me - Peter should be able to pull it into his tree soon. --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 05 04:27:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwid8-0002Kp-8v for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 04:27:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwid4-0002Ir-1g; Tue, 05 Jan 2021 04:27:51 -0500 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]:46899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwid2-0001ub-EY; Tue, 05 Jan 2021 04:27:49 -0500 Received: by mail-yb1-xb2c.google.com with SMTP id f6so28631487ybq.13; Tue, 05 Jan 2021 01:27:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=byKgXZAveVpGlvN1y8RqU8Pv1Mo+mr9U+5WKhQwPZDo=; b=exqvpJ4ZWZtlhHMGufQsm34Nbj3EtqAMfX/YnHuaJI0iPOu+LzpymD7XzKHdOumP0U k+Zq9CTPOkshgZBKaJPh8bYN84hymhWcGJEddVrUHF43uNzOlPdDq957blhqkp/HzuVk Qo/CcUUx8WQNGVqv5oD3ig6yjO2otHEtawnX22ZVzClORJyXEidcYTMaiNNXQ3Ofc6Ak JQd7p1a/Ut3V0PL5cL3N2key0zIpfUOtpjNvjezQc902NhEW8f7PoUL/wnRADaAyBavB qFZTiSoWbM7L4FNAqb4i/q0DCm9JyJRUfmSXsIjZmklB0M9zqxasRART3WYcMH2dCoHD cFHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=byKgXZAveVpGlvN1y8RqU8Pv1Mo+mr9U+5WKhQwPZDo=; b=jWoCPoi3oFI6snj/eJ61X+i+fq6cRYkiL3vuMkZscBSjzyKx6Q+BXcuNtP3ySKyDCl g12pkhPHPCMgN8oxOyrleZnFBHR6D1yCsLYYIX4azlxTBxImu45/x2P5JXpTk//NLKuL z9oAiDpxd7uzNnWCbZehfTq0swkhXYO6MerLZGsVymaNzmu2G4kNr1ChtDrZN0rCAhWY CQP0EkppDmuxYQNcMH9nH5TuygK4kWNPD3ct9njOiQoJCJ1ePrD9P9fhTHOrWIgeQx5+ OItmMGxNsqim/OnOiGS4dWlb+YSyPce+JpoUDfmR974FO/oFJiNUd1gqZh4APqswFd2Y fOxg== X-Gm-Message-State: AOAM5332KnkiHz9PVYMnumNqspAtZu0+cGkQRB+3zufTMb7BZvWXSiBt alBWNFs5CNCvJcb1g71JFnEomUzTzd2E624AUuQ= X-Google-Smtp-Source: ABdhPJypCQEtYsxgj+yQ61ZOb1oC0D/z1+2/ALfbrTbG1TCYRNyxQ0RJWdd5nZiBWEXOlaW+iAR/Akr0sfTnsS9Mang= X-Received: by 2002:a25:aaee:: with SMTP id t101mr105435222ybi.517.1609838866984; Tue, 05 Jan 2021 01:27:46 -0800 (PST) MIME-Version: 1.0 References: <1608704767-9317-1-git-send-email-bmeng.cn@gmail.com> <1608704767-9317-2-git-send-email-bmeng.cn@gmail.com> <87lfd73fcr.fsf@linaro.org> In-Reply-To: <87lfd73fcr.fsf@linaro.org> From: Bin Meng Date: Tue, 5 Jan 2021 17:27:35 +0800 Message-ID: Subject: Re: [PATCH v2 1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: Jean-Christophe Dubois , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 09:27:51 -0000 Hi Alex, On Tue, Jan 5, 2021 at 5:25 PM Alex Benn=C3=A9e wr= ote: > > > Bin Meng writes: > > > On Wed, Dec 23, 2020 at 2:26 PM Bin Meng wrote: > >> > >> From: Bin Meng > >> > > >> > >> (no changes since v1) > >> > >> hw/misc/imx6_ccm.c | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > > > > Ping? > > Looks good to me - Peter should be able to pull it into his tree soon. Thank you for the review. Regards, Bin From MAILER-DAEMON Tue Jan 05 05:21:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwjSg-0006wX-Ce for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 05:21:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwjSd-0006uZ-RG; Tue, 05 Jan 2021 05:21:07 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:38841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwjSZ-0006CE-3T; Tue, 05 Jan 2021 05:21:07 -0500 Received: by mail-wm1-x32f.google.com with SMTP id g185so2517846wmf.3; Tue, 05 Jan 2021 02:21:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=wcyrXJyV8vkXYpF1Gj7teAMTTTs3GqXdlTK0DB40QuM=; b=fZAESk28FY86MP2pfU2qVWx0kftV3kXrAHiyOj2P0Djgl+uxMpp6FhUQUR20V7A87y p/izchjfhwi8wks5lBCNir7O2GBbEblzOxtQ7CiHSij0sGTAvXfEJSPCr833LwGK3ZA8 Vdy48MZGAZUDY0bBxeaoKF5lB1dSuO0OOPPs2JXSIPJjFKF5TGUY6buSxb2JP/jJUkdA FA6KLkIiu67xepzvSidxOBQNe0ZvlcXn2qQ8DBfFF4e7L/uLShvHvV5WNHQZFFBpCYjP NEyM+56YrUsrIYsWxaBTPxcu+47Rhg7DBjE7sJ7mlQNi66P59GxqTi2N6XjmluQLlaCx wD+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=wcyrXJyV8vkXYpF1Gj7teAMTTTs3GqXdlTK0DB40QuM=; b=Fcn7SIoZhjuIVcc2yRw6l1qRHWlepuubq1M9XPVeMcytz25ZruyO5gqrVqcmGPduBu d7bnYYtre6De0Bci/FhRpdx2Fz08Wnr/pGfpfZ/ZnNzPT3gWrnnh23GP1ER2tBKFRkMq fk3IzK9QtYjtxAr8aFU1zDKW6w0SuIhU6vYYGiSnxnKZec6IglLCI2PqjSiRRZ/QUHh9 3q8fR4U2xtJV+cKC4AkH/ZnyPBfo/nU+aQfdCO2YeFXaAOZZyHznwKW3PjKcszl0BfUm czoaAA/cZwVmASBHQRUMWogrMLhoNrZLQtz/XTjzHlN1fzsc5U7KhoWPhoZe+7yps7Po S3Zw== X-Gm-Message-State: AOAM53234IzW/31Cz+Zhwv9yF9A6WFKR5DtEUGReNIRmXE5NN00oBo9K 5HA5mssMaSUWjldT3jayrhw= X-Google-Smtp-Source: ABdhPJwddyjDxJ9HKbGqaGortZ+0dvv4r7rvL8MHZw8YESMiQHIRZUqSHkfbnBtkEsbIVJQw1it38A== X-Received: by 2002:a1c:2785:: with SMTP id n127mr2844010wmn.148.1609842060737; Tue, 05 Jan 2021 02:21:00 -0800 (PST) Received: from [192.168.1.36] (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id a62sm3599259wmh.40.2021.01.05.02.20.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Jan 2021 02:20:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, francois.ozog@linaro.org, Jose.Marinho@arm.com, tf-a@lists.trustedfirmware.org References: <20201217135713.9715-1-maxim.uvarov@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <72254ba5-368e-e179-cce0-75510ff8028b@amsat.org> Date: Tue, 5 Jan 2021 11:20:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20201217135713.9715-1-maxim.uvarov@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 10:21:08 -0000 On 12/17/20 2:57 PM, Maxim Uvarov wrote: > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). > Use the same gpio 3 and gpio 4 which were used by > non acpi variant of linux power control gpios. > > Signed-off-by: Maxim Uvarov > --- > This patch works together with ATF patch: > https://github.com/muvarov/arm-trusted-firmware/commit/dd4401d8eb8e0f3018b335b81ce7a96d6cb16d0f > > Previus discussion for reboot issue was here: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html > > Regards, > Maxim. > > > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 24 +++++++++++++ > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 83 +++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > include/hw/arm/virt.h | 1 + > 6 files changed, 113 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c ... > +static void gpio_pwr_set_irq(void *opaque, int irq, int level) > +{ > + GPIO_PWR_State *s = (GPIO_PWR_State *)opaque; > + > + qemu_set_irq(s->irq, 1); > + > + if (level) { > + return; > + } > + > + switch (irq) { > + case 3: > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); > + break; > + case 4: > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); > + break; > + default: > + printf("qemu; gpio_pwr: unknown interrupt %d lvl %d\n", > + irq, level); Please use qemu_log_mask(LOG_GUEST_ERROR) (or UNIMP?). Otherwise patch is good, thanks! Phil. From MAILER-DAEMON Tue Jan 05 05:55:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwjzv-00071Q-S4 for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 05:55:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwjzh-0006tk-Id; Tue, 05 Jan 2021 05:55:18 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwjzf-0003li-K6; Tue, 05 Jan 2021 05:55:16 -0500 Received: by mail-wr1-x42a.google.com with SMTP id 91so35699786wrj.7; Tue, 05 Jan 2021 02:55:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=N4eE/I/iYxVLEloIym09b1kOSFCaCgrJ67UK8teDUkc=; b=UmrLFKIo8Y1/qfrOghBLEPVLcJMTVF3Qm+D+LZ7X92PQ1AmCr9/E8TkHVLWLHAj/XQ K/uO66gCzVsutXDwen0ZvvTlUqybKRxqDUnf+kHX83Q+jhYzhUkI3744DwMnXqO1XgI3 bWNyEdq7gIOxMtzpXyYJl0kUWfwk04dlNUGjizEHwpeUvq94PSGFxA+mD2gJEIr+6wYl wlQCMB32Kn4I1HAZ3QiLcE7pIU4byY1KAm5iVom5WRC14XEbv1Dxyeh1uFON4V5kDJuB DZh+tEAYHoRaHJh5ZYWRzzKSyqlApu35/L4ED/2VR2tpT+Vv4Ii/kzdhrVSl+VjngDRm ph9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=N4eE/I/iYxVLEloIym09b1kOSFCaCgrJ67UK8teDUkc=; b=fJJ1t5LUgi6IoyiJJwpejf5PpwAb6IXOb9YWH02Lu6bI2CTDHqywD0e0C+Y/ybrTlv +2aYt9YxGoGIvVi5WWBBabe3EFasCtCTUEQoWcEvJ2277mgqU7QtJ02LD0cmSJuTWrGT xHFj3oUaSH7RvnzSilfuMQQWpe39hoNzhLTwp8Bt33m5Gj6qE0SMXJH04ExXmxtzeuTi d8QL8z2dHJYQMfabQuByr12St3uHqMuSvmJHas+SWL2ivf08hzLofIrU+2YRF7NyAIn+ iVq/pyL9MniKyAQ6ncMiMPvueGlw9x+iyrmA5w3qKPfCYzHPHCfA8Y8x+/fFp2hDjO+k ACBQ== X-Gm-Message-State: AOAM533Z40QD8AU9zj/YFldMdMLy3avVNoNaeh41nMqwobdKPJdLVMGi jSE8rokqv8JF4H3BdJTXJgI= X-Google-Smtp-Source: ABdhPJyjJlklv0rg/zcH1KaBMhmdy8dCh+LFh1q9Qc2G9HBBTjP/3xsiPqGxaL0a9g4Sw48E3Swv1g== X-Received: by 2002:adf:ba8b:: with SMTP id p11mr81031556wrg.328.1609844112836; Tue, 05 Jan 2021 02:55:12 -0800 (PST) Received: from [192.168.1.36] (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id w8sm95858067wrl.91.2021.01.05.02.55.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Jan 2021 02:55:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH] hw/arm/highbank: Drop dead KVM support code To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Rob Herring References: <20201215144215.28482-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <24e9f6e5-4700-7e31-bd04-8aead370415c@amsat.org> Date: Tue, 5 Jan 2021 11:55:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20201215144215.28482-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 10:55:25 -0000 On 12/15/20 3:42 PM, Peter Maydell wrote: > Support for running KVM on 32-bit Arm hosts was removed in commit > 82bf7ae84ce739e. You can still run a 32-bit guest on a 64-bit Arm > host CPU, but because Arm KVM requires the host and guest CPU types > to match, it is not possible to run a guest that requires a Cortex-A9 > or Cortex-A15 CPU there. That means that the code in the > highbank/midway board models to support KVM is no longer used, and we > can delete it. > > Signed-off-by: Peter Maydell > --- > hw/arm/highbank.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Tue Jan 05 06:02:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwk74-0003J2-SX for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 06:02:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwk72-0003HI-AK for qemu-arm@nongnu.org; Tue, 05 Jan 2021 06:02:52 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:46892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kwk6z-00076c-Ir for qemu-arm@nongnu.org; Tue, 05 Jan 2021 06:02:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1609844568; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8cu6HkCB5CpxmqJ03sR67WS1+WODTfgIc3D+gNm2MqU=; b=GdlseIO5+by6Y1DM04m8GNhJmEQabEZEFK5TZOpKUMmc/XWpnycRxWW+9WFdqZHcuiVOtt +mDHvAPJLmS+oxlKJTs7+vVDIe85Niy0HqjrDKneuLdgJihdvZbzmFDraywSiczdnaozyY KJTgUUnlY7j/fOWf9I0/LJg5DuNGfNs= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-487-6n4ElkjYN1-n9V1Oa3Lp5A-1; Tue, 05 Jan 2021 06:02:47 -0500 X-MC-Unique: 6n4ElkjYN1-n9V1Oa3Lp5A-1 Received: by mail-wr1-f69.google.com with SMTP id q18so14673618wrc.20 for ; Tue, 05 Jan 2021 03:02:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=mbl5QmC5aHI8ZfdwVbKvx4Xv3Z0CQD3R2rpo6FmAyfQ=; b=Mr/nfy5keRyWb45nEa+2pUwLhxPHew8HtSWmJoa+jbnXdVXSgB68i3vzgwX//Psl1k +KCaEsf88U4oJ42XR/03b5WKACAPv3aBnWuj43XW1R+KpAjiHRcsugbihSGioMjXHC0h lTqWBqdwEsl3PJqCaJ3kf0QBkyy4WgW8KdRrQ3WP/dbVw7s6YtlvM48W9e99a851miFU 9oNpfIpA6Uc8fO+u/7Q/kKot63us55O2j1bDlx4JMbTtWn/raKJgPg3L2cSRxI+6rVD5 QyluyOyN8o3j5TeQKtIqhDlNlJP95JVe90ZpuZzAma1E72KF89uLCiZmetmst45irkMQ S1qA== X-Gm-Message-State: AOAM531TkJ8aQPaiwKfGfgmjlRv71Hnx37JOQ6AkMhwQTUQ0tpoRbw1E m4jEBb5+2G6LfXPC1iY7AbGPLt0I7TWrVkTg65lH+rfeQkGTBUhLgY17CTYJFuQGFToObm4vpK7 y2ZxRi7vKk5K7 X-Received: by 2002:a05:6000:1d1:: with SMTP id t17mr86763568wrx.164.1609844563962; Tue, 05 Jan 2021 03:02:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJz4hnw0cXfyXJO/q1XhDtqdY2vnBX0lFQZoDAbJmZgLdBPxSaHYmrKIJ6h9H7/q0eBZVqcyZw== X-Received: by 2002:a05:6000:1d1:: with SMTP id t17mr86763531wrx.164.1609844563667; Tue, 05 Jan 2021 03:02:43 -0800 (PST) Received: from redhat.com (bzq-79-178-32-166.red.bezeqint.net. [79.178.32.166]) by smtp.gmail.com with ESMTPSA id j2sm61399868wrh.78.2021.01.05.03.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 03:02:42 -0800 (PST) Date: Tue, 5 Jan 2021 06:02:39 -0500 From: "Michael S. Tsirkin" To: Eduardo Habkost Cc: qemu-devel@nongnu.org, Michael Roth , "Daniel P. Berrange" , Igor Mammedov , qemu-arm@nongnu.org, Markus Armbruster , Laszlo Ersek , Paolo Bonzini , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Richard Henderson , Marcel Apfelbaum , Eric Blake Subject: Re: [PATCH v2 3/3] hw/i386: expose a "smbios-ep" PC machine property Message-ID: <20210105055815-mutt-send-email-mst@kernel.org> References: <20201214205029.2991222-1-ehabkost@redhat.com> <20201214205029.2991222-4-ehabkost@redhat.com> MIME-Version: 1.0 In-Reply-To: <20201214205029.2991222-4-ehabkost@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.243, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 11:02:52 -0000 On Mon, Dec 14, 2020 at 03:50:29PM -0500, Eduardo Habkost wrote: > From: Daniel P. Berrangé > > The i440fx and Q35 machine types are both hardcoded to use the legacy > SMBIOS 2.1 entry point. This is a sensible conservative choice because > SeaBIOS only supports SMBIOS 2.1 > > EDK2, however, can also support SMBIOS 3.0 and QEMU already uses this on > the ARM virt machine type. > > This adds a property to allow the choice of SMBIOS entry point versions > For example to opt in to version 3.0 > > $QEMU -machine q35,smbios-ep=3_0 > > Signed-off-by: Daniel P. Berrangé > Signed-off-by: Eduardo Habkost Just one small point: wouldn't it be a good idea to eschew abbreviation here, and call the property smbios-entry-point or even smbios-entry-point-type or smbios-entry-point-version? > --- > This is patch was previously submitted at: > https://lore.kernel.org/qemu-devel/20200908165438.1008942-6-berrange@redhat.com > > Changes from v1: > * Include qapi-visit-smbios.h instead of qapi-visit-machine.h > * Commit message fix: s/smbios_ep/smbios-ep/ > --- > include/hw/i386/pc.h | 3 +++ > hw/i386/pc.c | 26 ++++++++++++++++++++++++++ > hw/i386/pc_piix.c | 2 +- > hw/i386/pc_q35.c | 2 +- > 4 files changed, 31 insertions(+), 2 deletions(-) > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index 2aa8797c6e..2075093b32 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -11,6 +11,7 @@ > #include "hw/acpi/acpi_dev_interface.h" > #include "hw/hotplug.h" > #include "qom/object.h" > +#include "hw/firmware/smbios.h" > > #define HPET_INTCAP "hpet-intcap" > > @@ -38,6 +39,7 @@ typedef struct PCMachineState { > /* Configuration options: */ > uint64_t max_ram_below_4g; > OnOffAuto vmport; > + SmbiosEntryPointType smbios_ep; > > bool acpi_build_enabled; > bool smbus_enabled; > @@ -62,6 +64,7 @@ typedef struct PCMachineState { > #define PC_MACHINE_SATA "sata" > #define PC_MACHINE_PIT "pit" > #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" > +#define PC_MACHINE_SMBIOS_EP "smbios-ep" > > /** > * PCMachineClass: > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 640fb5b0b7..3cc559e0d9 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -81,6 +81,7 @@ > #include "hw/mem/nvdimm.h" > #include "qapi/error.h" > #include "qapi/qapi-visit-common.h" > +#include "qapi/qapi-visit-smbios.h" > #include "qapi/visitor.h" > #include "hw/core/cpu.h" > #include "hw/usb.h" > @@ -1532,6 +1533,23 @@ static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) > pcms->hpet_enabled = value; > } > > +static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + PCMachineState *pcms = PC_MACHINE(obj); > + SmbiosEntryPointType smbios_ep = pcms->smbios_ep; > + > + visit_type_SmbiosEntryPointType(v, name, &smbios_ep, errp); > +} > + > +static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + PCMachineState *pcms = PC_MACHINE(obj); > + > + visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_ep, errp); > +} > + > static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, > const char *name, void *opaque, > Error **errp) > @@ -1621,6 +1639,8 @@ static void pc_machine_initfn(Object *obj) > pcms->vmport = ON_OFF_AUTO_OFF; > #endif /* CONFIG_VMPORT */ > pcms->max_ram_below_4g = 0; /* use default */ > + pcms->smbios_ep = SMBIOS_ENTRY_POINT_TYPE_2_1; > + > /* acpi build is enabled by default if machine supports it */ > pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; > pcms->smbus_enabled = true; > @@ -1759,6 +1779,12 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) > NULL, NULL); > object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, > "Maximum combined firmware size"); > + > + object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", > + pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, > + NULL, NULL); > + object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, > + "SMBIOS Entry Point version [v2_1, v3_0]"); To me this reads like the legal values are v2_1 and v3_0, in fact they are 2_1 and 3_0. > } > > static const TypeInfo pc_machine_info = { > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index 08b82df4d1..30ae7f27af 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -179,7 +179,7 @@ static void pc_init1(MachineState *machine, > smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)", > mc->name, pcmc->smbios_legacy_mode, > pcmc->smbios_uuid_encoded, > - SMBIOS_ENTRY_POINT_TYPE_2_1); > + pcms->smbios_ep); > } > > /* allocate ram and load rom/bios */ > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index f71b1e2dcf..9974426806 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -198,7 +198,7 @@ static void pc_q35_init(MachineState *machine) > smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", > mc->name, pcmc->smbios_legacy_mode, > pcmc->smbios_uuid_encoded, > - SMBIOS_ENTRY_POINT_TYPE_2_1); > + pcms->smbios_ep); > } > > /* allocate ram and load rom/bios */ > -- > 2.28.0 From MAILER-DAEMON Tue Jan 05 16:09:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwtZm-0002w9-VZ for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 16:09:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwtZl-0002uc-VL; Tue, 05 Jan 2021 16:09:09 -0500 Received: from mail-il1-x132.google.com ([2607:f8b0:4864:20::132]:36819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwtZk-0004a1-FD; Tue, 05 Jan 2021 16:09:09 -0500 Received: by mail-il1-x132.google.com with SMTP id u12so1067095ilv.3; Tue, 05 Jan 2021 13:09:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+YbBYxs4hsW5m93VHJs6o1NpJlsMUpCdZX8aI/aak+U=; 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Tue, 05 Jan 2021 13:09:06 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> In-Reply-To: From: Alistair Francis Date: Tue, 5 Jan 2021 13:08:40 -0800 Message-ID: Subject: Re: [PATCH v2 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Bin Meng Cc: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=alistair23@gmail.com; helo=mail-il1-x132.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 21:09:10 -0000 On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote: > > Hi Alistair, Peter, > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote: > > > > From: Bin Meng > > > > Avoid using a magic number (4) everywhere for the number of chip > > selects supported. > > > > Signed-off-by: Bin Meng > > Reviewed-by: Alistair Francis > > --- > > > > (no changes since v1) > > > > hw/ssi/imx_spi.c | 4 ++-- > > include/hw/ssi/imx_spi.h | 5 ++++- > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > Ping, not sure who is going to pick up this series? It should be reviewed by Jean-Christophe and then probably go via the ARM tree. Alistair > > Regards, > Bin > From MAILER-DAEMON Tue Jan 05 16:11:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwtbm-00048c-Gq for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 16:11:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwtbl-00048U-KC for qemu-arm@nongnu.org; Tue, 05 Jan 2021 16:11:13 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:40228) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwtbj-0005Pl-Io for qemu-arm@nongnu.org; Tue, 05 Jan 2021 16:11:13 -0500 Received: by mail-ej1-x62d.google.com with SMTP id x16so2363522ejj.7 for ; Tue, 05 Jan 2021 13:11:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=U5FDRc64gS4Z/qmb6HEXGmEPLYosVqTsAov7RGKQL4I=; b=Oj6E3u9O3Jrt7LKPLG6Nq8/J+shdNd6V+xZ7v2hHYmNqU+a6+yrn8dKqJ1KI/7b/ee e0ZiBdBNNSNKOABV2VMicEKtefSHcvd0yl/ylpVsLkz1ckyjmc7nZRUluQ1AindEXSFd YpKYUOhcmoNE/FG6EZaXIP8oEn9PFCf7cK60xuhMbDA3iflP6bgnAt6S+CcZ5ijPwkyX LkIQfRAD5n1V+FjQTVj4Wan1d5sU29cRXdrocDyUV1rfrG0rJj7A4Z38mcyldiEFVzf3 RavfAdjFn+TeIFSdXyANMaky8XnKSRBw/aI2IcoGqXtKwtLhC92M80gMY1EZIDHl5TGJ H4Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=U5FDRc64gS4Z/qmb6HEXGmEPLYosVqTsAov7RGKQL4I=; b=pXqWSPd4pARw3edl6YnrNS3cSCiYA6NoB3OpT1TpOrlCiiecihdX55ltS0G1rvP8CC z4+cmpRp9NBS/JL+NaPwZ/snKvbcfefDiUSSwvfBj5KUjZy4DqbFbthy3y5R0NvCZ/QV iYeCGflIRGnJ6rjCmNefLJamh3RUdbJBBFep/UHMAe7N25f8rpxEPDFZsHlAA50X8jzx qUqu45DyDcQ0JvIPQ34sR0kuh2X5jt+GGCjbxfRLJZ3Y5XyepDvWj+tTLhu7QweKnjqv A4lBhTEUKgaVsAE2nDGjUzdBrPmisDpXBWfWRgqr3dbxkHzWdtbj/ON9RcHlwn/mhBOW wJ5w== X-Gm-Message-State: AOAM532G+0GjNHjqZCdtKkDV7nRqunpjk5i5uYHtvGjrL3frM1i2MM5i 9zeHsqLITDdT+o1zkp4RyVZvRG5HYcnflgK832ibZg== X-Google-Smtp-Source: ABdhPJylU9HTgLd+oOTuohzTfMilSVXXRhhEzVgxd7WT9T/+qXEnD63ENVhcb/Zh54fn7ngrB6uojFBGBpbCWHhvCC4= X-Received: by 2002:a17:906:31d2:: with SMTP id f18mr808600ejf.407.1609881070185; Tue, 05 Jan 2021 13:11:10 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> In-Reply-To: From: Peter Maydell Date: Tue, 5 Jan 2021 21:10:59 +0000 Message-ID: Subject: Re: [PATCH v2 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Alistair Francis Cc: Bin Meng , Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 21:11:13 -0000 On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote: > > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote: > > > > Hi Alistair, Peter, > > > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > Avoid using a magic number (4) everywhere for the number of chip > > > selects supported. > > > > > > Signed-off-by: Bin Meng > > > Reviewed-by: Alistair Francis > > > --- > > > > > > (no changes since v1) > > > > > > hw/ssi/imx_spi.c | 4 ++-- > > > include/hw/ssi/imx_spi.h | 5 ++++- > > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > > > > Ping, not sure who is going to pick up this series? > > It should be reviewed by Jean-Christophe and then probably go via the ARM tree. It doesn't seem to have been sent with a cover letter. Multi-patch patchsets without a cover letter tend to get missed because when I scan through my email looking for patches I should review or pick up I'm looking for either (a) single patches or (b) the 00/nn cover letter email... thanks -- PMM From MAILER-DAEMON Tue Jan 05 16:12:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwtdK-00059F-Qw for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 16:12:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwtdJ-00057q-EE; Tue, 05 Jan 2021 16:12:49 -0500 Received: from mail-il1-x132.google.com ([2607:f8b0:4864:20::132]:37334) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwtdH-0005vM-QO; Tue, 05 Jan 2021 16:12:49 -0500 Received: by mail-il1-x132.google.com with SMTP id k8so1070622ilr.4; Tue, 05 Jan 2021 13:12:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CJzM8vGuJJ7uphomVoIK3FvyeywCzrMEff/uX/RUGhQ=; b=nQoLdb9HSjZeeEmET9F+xZE56nPZqliJIuRKKXgFOdKhGagTfNZ0qEN+AtOWa48GzE T7c+xuq6FfNPxyJ1WeonzqRCIJDY9Qiwjb9aV11C5bY8YM1ALCb95amsyED28LAt8rjY FxHQ66FEzKu2fmhEb2g8LhFyx+pTSJf6U1JJUAebc+mv+0h4fSmk4bX4N9WBi0NJKgGJ 2SJjVBosLF1XejAKXA9oNPTf6Jhx1V9vPyOA5dY/MvRuak1igQbxBLlWTh12qs3UkFnK o56Wdsv6WEJi7td88Ym4aAzwpmqgieiSe2ZK5p1tDVH4SHLflCmWoIMpqv3Kmf/ntBa6 o44w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CJzM8vGuJJ7uphomVoIK3FvyeywCzrMEff/uX/RUGhQ=; b=Wn0nZBS1ExFgINeFwwdUZKgLX9S4916cD/zwGCEt2PBf2bLXegft5qaMf8rHPmcOsh a8kVPaKEZpmo1ArsKDvebwTCmXCSmXjPPc9UPvfmheM2iwPBQT4H1pd3cwT3IkNYJRDg KjrO+O5tOImah8s4DnIAcOZYh/2RTift1uGFlZi+wJiOkZLXo+Qsnbs+1bGEAbpHLU5Y BQELvfihQYOG0QHWsVjdvI6i2v4g/t+f+Y3VNYkUwkly1FGxSaTHBmKGtQtNgaM686d8 qTWKt4KMUSvoilqzsoRK8Hf90ZNN3RImqfnXHd+TPFCgbA/E0RyFWtjC4pxY8gvYtrf8 vLxg== X-Gm-Message-State: AOAM531h8fUSgZ9QEqccm/7gM1KTVlILtIB6KzL4iseIssNz7TC2vVSg Pu0m0arV89dmQdX0JPKoQmDh8f5IfgoWkNV9bouCGVasp0Q= X-Google-Smtp-Source: ABdhPJyV//J91oUbSy46/5/647p/q40XVfqntZEWZZNiqAeoBgj1nhnyYGvhL38IHUi/i9ofPpYBbf9Wo34Aq1er4CM= X-Received: by 2002:a05:6e02:ca5:: with SMTP id 5mr1471370ilg.40.1609881166022; Tue, 05 Jan 2021 13:12:46 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> In-Reply-To: From: Alistair Francis Date: Tue, 5 Jan 2021 13:12:19 -0800 Message-ID: Subject: Re: [PATCH v2 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Bin Meng Cc: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , Peter Maydell , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=alistair23@gmail.com; helo=mail-il1-x132.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 21:12:49 -0000 On Tue, Jan 5, 2021 at 1:08 PM Alistair Francis wrote: > > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote: > > > > Hi Alistair, Peter, > > > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > Avoid using a magic number (4) everywhere for the number of chip > > > selects supported. > > > > > > Signed-off-by: Bin Meng > > > Reviewed-by: Alistair Francis > > > --- > > > > > > (no changes since v1) > > > > > > hw/ssi/imx_spi.c | 4 ++-- > > > include/hw/ssi/imx_spi.h | 5 ++++- > > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > > > > Ping, not sure who is going to pick up this series? > > It should be reviewed by Jean-Christophe and then probably go via the ARM tree. Ah, I just realised I apparently have `hw/ssi/*` listed in MAINTAINERS. As this file is specifically mentioned somewhere else in MAINTAINERS and I know very little about IMX I'm going to leave this alone still. Alistair > > Alistair > > > > > Regards, > > Bin > > From MAILER-DAEMON Tue Jan 05 16:56:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwuJp-0002dX-2K for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 16:56:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwuJn-0002dA-Ku for qemu-arm@nongnu.org; Tue, 05 Jan 2021 16:56:43 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:44489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwuJl-0004zZ-0e for qemu-arm@nongnu.org; Tue, 05 Jan 2021 16:56:43 -0500 Received: by mail-lf1-x131.google.com with SMTP id m25so1937725lfc.11 for ; Tue, 05 Jan 2021 13:56:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CJTR5P+O1pAD9ZwARwSZ/K8/6oUZwdn6dUQpE4KreUU=; b=X3nJsZLrGDkre0IxhwB9gU76MRmgh7NQQkgtmp+2qgfMN2myC1CqKbyupf/g2JGSKB ePT96owqK6R0bUltPu1FuQg5iF09pnelWWk46QC8eHo1iOdCnVN11L6zkHbmabV+v/vu o5uQ9VJs/ggBrzXEHevTQMOLE8m8l6/Z2UVqtsWHeN6Xl0WoczwVZn+MKfKNEO2aCCaN AEdihsmfHRofpW/EEzwAxde7+/D9BhED9pdFBZpgbdQZbPbDsHSh/v/LHum5/Mcs2YpY dA7kpcBmfs7Oa9yvL5p4Yz5UEUP9AfWXPt39D4KbcBeOtQV4Zj5zMKY2DhtvZ83v/BEX qcEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CJTR5P+O1pAD9ZwARwSZ/K8/6oUZwdn6dUQpE4KreUU=; b=YKCY5TrQ8wGZT3sE4RwiBfCNPfxX2KUHij9vJPbfwLXZ4z8Eqz/kZm8B1AKNHexh8E SyvzpV8yzXVJOpn88YdDel0iu9CjJFFNIwoOITzVwB+tF2BngAGG/BjWPyuJchd1QW2S gA//6q9szZifV0ceozgzRPS8+Ab1XkFAg767Dn6XFeVcQZqQt9RUZNJT7kYFf05EWtc7 4zbNlj3qFZMNgZRPzu1IQtjkjDs2yGCDc+YzBO6ORfFFPIk9L+vXiw9mfQUcnxVFz3Zb yIYkj3D5qCicZLziF9cgD23nMoLLOlOfA2QHjRa3uadvgQbiL/+sjHc9Q0RZHp+0QlIg 619w== X-Gm-Message-State: AOAM530Am55pBO2EMQVt9cugaslqL4WRAIYU3iaC4fmljT/+MO7JnQs3 0jEU9uMHSRj1VFF92i47gs/88xZu/3pEqLYvwQ24nw== X-Google-Smtp-Source: ABdhPJxffchFhmbHgephTF5b7gfCY6BL6aQlHOAEktndKsAUg0Hy3o5GayMBhJkuWUGHuaDX9gKLuRni5Kd2+We6SRY= X-Received: by 2002:ac2:4d14:: with SMTP id r20mr576847lfi.410.1609883793668; Tue, 05 Jan 2021 13:56:33 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-1-wuhaotsh@google.com> From: Hao Wu Date: Tue, 5 Jan 2021 13:56:22 -0800 Message-ID: Subject: Re: [PATCH v4 0/6] Additional NPCM7xx devices To: Peter Maydell Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000a7214905b82e4742" Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -179 X-Spam_score: -18.0 X-Spam_bar: ------------------ X-Spam_report: (-18.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.369, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Jan 2021 21:56:43 -0000 --000000000000a7214905b82e4742 Content-Type: text/plain; charset="UTF-8" Ping? On Wed, Dec 16, 2020 at 4:45 PM Hao Wu wrote: > This patch series include a few more NPCM7XX devices including > > - Analog Digital Converter (ADC) > - Pulse Width Modulation (PWM) > > We also modified the CLK module to generate clock values using qdev_clock. > These clocks are used to determine various clocks in NPCM7XX devices. > > Thank you for your review. > > Changes since v3: > - Use type casting instead of accessing parent object in all devices. > > Changes since v2: > - Split PWM test into a separate patch in the patch set > - Add trace events for PWM's update_freq/update_duty > - Add trace events for ioread/iowrite in ADC and PWM > - Use timer_get_ns in hw/timer/npcm7xx_timer.c > - Update commit message in ADC/PWM to mention qom-get/set method for usage > - Fix typos > > Changes since v1: > - We removed the IPMI and KCS related code from this patch set. > > Hao Wu (6): > hw/misc: Add clock converter in NPCM7XX CLK module > hw/timer: Refactor NPCM7XX Timer to use CLK clock > hw/adc: Add an ADC module for NPCM7XX > hw/misc: Add a PWM module for NPCM7XX > hw/misc: Add QTest for NPCM7XX PWM Module > hw/*: Use type casting for SysBusDevice in NPCM7XX > > docs/system/arm/nuvoton.rst | 4 +- > hw/adc/meson.build | 1 + > hw/adc/npcm7xx_adc.c | 321 +++++++++++++ > hw/adc/trace-events | 5 + > hw/arm/npcm7xx.c | 55 ++- > hw/arm/npcm7xx_boards.c | 2 +- > hw/mem/npcm7xx_mc.c | 2 +- > hw/misc/meson.build | 1 + > hw/misc/npcm7xx_clk.c | 797 ++++++++++++++++++++++++++++++- > hw/misc/npcm7xx_gcr.c | 2 +- > hw/misc/npcm7xx_pwm.c | 559 ++++++++++++++++++++++ > hw/misc/npcm7xx_rng.c | 2 +- > hw/misc/trace-events | 6 + > hw/nvram/npcm7xx_otp.c | 2 +- > hw/ssi/npcm7xx_fiu.c | 2 +- > hw/timer/npcm7xx_timer.c | 25 +- > include/hw/adc/npcm7xx_adc.h | 72 +++ > include/hw/arm/npcm7xx.h | 4 + > include/hw/misc/npcm7xx_clk.h | 146 +++++- > include/hw/misc/npcm7xx_pwm.h | 106 ++++ > include/hw/timer/npcm7xx_timer.h | 1 + > meson.build | 1 + > tests/qtest/meson.build | 4 +- > tests/qtest/npcm7xx_adc-test.c | 400 ++++++++++++++++ > tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++ > 25 files changed, 2972 insertions(+), 38 deletions(-) > create mode 100644 hw/adc/npcm7xx_adc.c > create mode 100644 hw/adc/trace-events > create mode 100644 hw/misc/npcm7xx_pwm.c > create mode 100644 include/hw/adc/npcm7xx_adc.h > create mode 100644 include/hw/misc/npcm7xx_pwm.h > create mode 100644 tests/qtest/npcm7xx_adc-test.c > create mode 100644 tests/qtest/npcm7xx_pwm-test.c > > -- > 2.29.2.684.gfbc64c5ab5-goog > > --000000000000a7214905b82e4742 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Ping?

On Wed, Dec 16, 2020 at 4:45 PM Hao Wu <wuhaotsh@google.com> wrote:
This patch series include a= few more NPCM7XX devices including

- Analog Digital Converter (ADC)
- Pulse Width Modulation (PWM)

We also modified the CLK module to generate clock values using qdev_clock.<= br> These clocks are used to determine various clocks in NPCM7XX devices.

Thank you for your review.

Changes since v3:
- Use type casting instead of accessing parent object in all devices.

Changes since v2:
- Split PWM test into a separate patch in the patch set
- Add trace events for PWM's update_freq/update_duty
- Add trace events for ioread/iowrite in ADC and PWM
- Use timer_get_ns in hw/timer/npcm7xx_timer.c
- Update commit message in ADC/PWM to mention qom-get/set method for usage<= br> - Fix typos

Changes since v1:
- We removed the IPMI and KCS related code from this patch set.

Hao Wu (6):
=C2=A0 hw/misc: Add clock converter in NPCM7XX CLK module
=C2=A0 hw/timer: Refactor NPCM7XX Timer to use CLK clock
=C2=A0 hw/adc: Add an ADC module for NPCM7XX
=C2=A0 hw/misc: Add a PWM module for NPCM7XX
=C2=A0 hw/misc: Add QTest for NPCM7XX PWM Module
=C2=A0 hw/*: Use type casting for SysBusDevice in NPCM7XX

=C2=A0docs/system/arm/nuvoton.rst=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A04 +- =C2=A0hw/adc/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A01 +
=C2=A0hw/adc/npcm7xx_adc.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= 321 +++++++++++++
=C2=A0hw/adc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A05 +
=C2=A0hw/arm/npcm7xx.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0|=C2=A0 55 ++-
=C2=A0hw/arm/npcm7xx_boards.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A02 +-
=C2=A0hw/mem/npcm7xx_mc.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A02 +-
=C2=A0hw/misc/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A01 +
=C2=A0hw/misc/npcm7xx_clk.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 797 = ++++++++++++++++++++++++++++++-
=C2=A0hw/misc/npcm7xx_gcr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A02 +-
=C2=A0hw/misc/npcm7xx_pwm.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 559 = ++++++++++++++++++++++
=C2=A0hw/misc/npcm7xx_rng.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A02 +-
=C2=A0hw/misc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A06 +
=C2=A0hw/nvram/npcm7xx_otp.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 =C2=A02 +-
=C2=A0hw/ssi/npcm7xx_fiu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A02 +-
=C2=A0hw/timer/npcm7xx_timer.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 25 = +-
=C2=A0include/hw/adc/npcm7xx_adc.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 72 +++
=C2=A0include/hw/arm/npcm7xx.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A04 +
=C2=A0include/hw/misc/npcm7xx_clk.h=C2=A0 =C2=A0 | 146 +++++-
=C2=A0include/hw/misc/npcm7xx_pwm.h=C2=A0 =C2=A0 | 106 ++++
=C2=A0include/hw/timer/npcm7xx_timer.h |=C2=A0 =C2=A01 +
=C2=A0meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
=C2=A0tests/qtest/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A04 +-
=C2=A0tests/qtest/npcm7xx_adc-test.c=C2=A0 =C2=A0| 400 ++++++++++++++++
=C2=A0tests/qtest/npcm7xx_pwm-test.c=C2=A0 =C2=A0| 490 +++++++++++++++++++<= br> =C2=A025 files changed, 2972 insertions(+), 38 deletions(-)
=C2=A0create mode 100644 hw/adc/npcm7xx_adc.c
=C2=A0create mode 100644 hw/adc/trace-events
=C2=A0create mode 100644 hw/misc/npcm7xx_pwm.c
=C2=A0create mode 100644 include/hw/adc/npcm7xx_adc.h
=C2=A0create mode 100644 include/hw/misc/npcm7xx_pwm.h
=C2=A0create mode 100644 tests/qtest/npcm7xx_adc-test.c
=C2=A0create mode 100644 tests/qtest/npcm7xx_pwm-test.c

--
2.29.2.684.gfbc64c5ab5-goog

--000000000000a7214905b82e4742-- From MAILER-DAEMON Tue Jan 05 19:22:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kwwar-00040k-4n for mharc-qemu-arm@gnu.org; Tue, 05 Jan 2021 19:22:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kwwap-00040X-23; Tue, 05 Jan 2021 19:22:27 -0500 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]:45945) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kwwan-0006bK-Hc; Tue, 05 Jan 2021 19:22:26 -0500 Received: by mail-yb1-xb32.google.com with SMTP id k78so1184396ybf.12; Tue, 05 Jan 2021 16:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7ugd7YDudYddqLGIcukv+gM9J30wg5E9OZ3wbdwxrsY=; b=FfKeffQDpZPWbJfr0KuqD1NithrQo/98z99aZesAW9ufKAGlxSWT5LRVSR7NEITGLJ J6SlIOgw9eaAHSrmsHvR0SsIStaFOlZwN6m+mEqZaIvUp8cXxHvxeOR2XiPFL7GbdMDA 5G20xwWdDSl6eqSFl7sRhdhs24Uhnv4iGc4dyO64ExtW8xHPknSMxCGTqXgN3tjGaI5i 62JwwajDpYcRD5mu+B2oiDFA/AUEu1JwKp/+9XJdAURBQ72uBWAc5V/RJMQtZH1YZFTr cAxfruD5MGY9NCgMg/n4aIDppRiTuviSL7bhTG4j5zML0JYUDBbIaB7wzlRfM+Ylx/ot saAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7ugd7YDudYddqLGIcukv+gM9J30wg5E9OZ3wbdwxrsY=; b=eS9l4uxrDVU/t6z6XU8CReaQdhlUJsRT44x9q4vzZ20EOoUjY4QPuZDZyz5xPXJVsY Tj8qyVuAX/+Ig9j0N5yGv4BtkgaiS2kMTauL3N3Jusj70qJAjiEmMIHP6mnfmcLlV++w v5BKy+Xeo8FJrxVcBY9Y6VUGaZ31ErbzV18FVE9OK/P2OetRJFy5SGfuJ0xL+ZgB2JSQ MDruJ7qmF+hLgJecPz7Uxugi1s0KkTHW1qZkQfcE5rxwuIyZdIF5OH4OqyVUqJ+A8gG3 HJXPZzmiSw5MSnLkFdo773GFBTxYrTsgABHsJLZHFYVgRgto4YKhaLo63pAuYGk8cJEK lDDA== X-Gm-Message-State: AOAM5330jCS6U5vYqZWx9oRP4mQ+KyHxgDlMW4shuYQ3by8qJhMQ/gqe h98lu/O4OMptXF120ZkSSSkk+yTPU0sGG/d0QlA= X-Google-Smtp-Source: ABdhPJxO1V7jYiD1y83kIiSLO0S0DpaEIjmmzIhiOYFQOg7P841IEZAzxG+rxVNKu7uEoNc8VHQSiYwOP2Fo+HU1mLU= X-Received: by 2002:a25:4d7:: with SMTP id 206mr2970167ybe.306.1609892544235; Tue, 05 Jan 2021 16:22:24 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Wed, 6 Jan 2021 08:22:13 +0800 Message-ID: Subject: Re: [PATCH v2 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Peter Maydell Cc: Alistair Francis , Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 00:22:27 -0000 On Wed, Jan 6, 2021 at 5:11 AM Peter Maydell wrote: > > On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote: > > > > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote: > > > > > > Hi Alistair, Peter, > > > > > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote: > > > > > > > > From: Bin Meng > > > > > > > > Avoid using a magic number (4) everywhere for the number of chip > > > > selects supported. > > > > > > > > Signed-off-by: Bin Meng > > > > Reviewed-by: Alistair Francis > > > > --- > > > > > > > > (no changes since v1) > > > > > > > > hw/ssi/imx_spi.c | 4 ++-- > > > > include/hw/ssi/imx_spi.h | 5 ++++- > > > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > > > > > > > Ping, not sure who is going to pick up this series? > > > > It should be reviewed by Jean-Christophe and then probably go via the ARM tree. > > It doesn't seem to have been sent with a cover letter. Multi-patch > patchsets without a cover letter tend to get missed because when > I scan through my email looking for patches I should review or > pick up I'm looking for either (a) single patches or (b) the 00/nn > cover letter email... Thanks. I will resend it with a cover-letter. Regards, Bin From MAILER-DAEMON Wed Jan 06 00:55:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1nH-0004ok-3a for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 00:55:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1nF-0004oV-GQ; Wed, 06 Jan 2021 00:55:37 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:41231) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1nD-0004ux-Ta; Wed, 06 Jan 2021 00:55:37 -0500 Received: by mail-pf1-x429.google.com with SMTP id t8so1093201pfg.8; Tue, 05 Jan 2021 21:55:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GoRyg9SHz3SU7GVb6+KfUus8j+YhS4cNFNlNjHUUGco=; b=B/jW2r+pLXwu8clwVwOHii8sZ2Qg/M2UMn+Dssj+MxQJOJpKfJ3AsQr1An5TwG+Ddf ip5Xidu9OX/9pTRlmLBkKaNkRnb2/cLMQZiVZ6/M19toahn81p9rLxhZ7DTzwua6otSm 6TsB2xL5DhUNMV9A69cLlbtYIMRTKwMOz9fXTlH+Z1JbHyY461XqutuM+oxf8b48NxDM UbI54xXMX/gwqPSvHtMhUWdB/E/+1QYi+Nz54YkQGAM80V6sIWHP/Kb3NJsSVpFZB01o R5S1yuiYFL07xKMZ/aoQnnbOszyDHJHBJP+/rrCPe0pEu01CDOU4tM3yL8DTH4rpsuPQ 59Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GoRyg9SHz3SU7GVb6+KfUus8j+YhS4cNFNlNjHUUGco=; b=bSOhuMfhMjfB/boylPSgmpO46Zn5nP7CyV9nNYmE98e3K9lQaObMpUGr7wQvNSUbYD Oy7MvuTqgEdzomSaFWc5H1ZFYPB3NGtUDRpGg9zEvw/o/swy9prGky5aClMhYVJSPKU8 AlSUMFJXuuc0ebv3Skyn/OBqs5wLpvskoq7t/TObhFIxqCdL+I+Wt2u4RHkA2rNBCG31 plfgYO5kfaU2AUc8y22nEicYNN1YwkhkRvXKrXEIFpDLFDO0HJMBbBqRut7alaubTWbo Zd/VRAdYFPsYLKw8T4jHvz1eOL3UbE5FAVGIG6qXxR6sYrDiUpiO26SkIoIJEcP6fSWC Pt3w== X-Gm-Message-State: AOAM530zhUZc7/mEzzDbEyB6JXQUxuVXkh6zEyKs1ESosCEMc5AJJq9W gGqkU9fAhfBvi6BrfzreKeo= X-Google-Smtp-Source: ABdhPJwCkNzyz84eenQKejGpATQyx7D7zQlRZLKh84ND8uO9Dgt2cJk09jacCJOl+XXOV+Xou5r3ZA== X-Received: by 2002:a65:6382:: with SMTP id h2mr2793618pgv.365.1609912533635; Tue, 05 Jan 2021 21:55:33 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:33 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v2 0/4] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Wed, 6 Jan 2021 13:55:18 +0800 Message-Id: <20210106055522.2031-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 05:55:37 -0000 From: Bin Meng This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is reset - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (3): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 27 ++++++++++++++++++++------- 2 files changed, 24 insertions(+), 8 deletions(-) -- 2.25.1 From MAILER-DAEMON Wed Jan 06 00:55:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1nK-0004sA-5h for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 00:55:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1nJ-0004qr-1q; Wed, 06 Jan 2021 00:55:41 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:33692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1nH-0004wr-G7; Wed, 06 Jan 2021 00:55:40 -0500 Received: by mail-pj1-x102f.google.com with SMTP id w1so2079345pjc.0; Tue, 05 Jan 2021 21:55:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=co4+01plcMDklfphwAUe6tgXN/qjYqocNNI7W6fX0o0=; b=IW8lIzrWPDZ/GaEqerBofB4OlYuHwNBcjR8scFo3+QL+1R2ruSMIM06DhthcCQj7q4 M8NUtadAefO1Ncsvq5KVizMWjJ8StnvGsItRmpLQwjpO3pvk03XtebOdyfpw33c1RXOm D4PU98TgI3ztsmVoSFpnRoTTTzs39JkXPy2ZvVp9h6P8zLRmRFtNWTyLZAgWWlct5Dtb hsRR2pfIqe+HYlOm75xi2XA4LjlSOK5mMoYyB9k+swBANwUQrRtnpX2JZaK2jeKzhtCf QCVXzAt9Dlpc/sSWrO8BMwbbchCFzsmTqKvngFk03zvubiT1pRPT9M5u4SX4DoFsmzs/ E6zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=co4+01plcMDklfphwAUe6tgXN/qjYqocNNI7W6fX0o0=; b=iQzFtmc4sAkBnv/15vGYPFnqV+06cA3g+B6c5G2lJ72Q/O51PHXz9bUxDnIdHgJpjf Nz7/vUjOwu7c2GncJmxVGVavOxPa7PLRxck0Pz41qsVJXuyn2+UYD9z2ZNCNhuSy4Jw/ 05yvg0Yp7j4t4lPyr7Vx9l1O1hn5x7UBA4RUg6rUcVEBjFFo8cXOsG/8Pgxg5PUuId70 inCGIR/X9Wue/w/+7gsGKK+mxNad37qBcVEhjWBCdzr9OvMwIK5Uak2ANMq/mMOb/1BC Jb+eXvtSWOF/yxzB+21snXXVNTuqN0LhMQrsB3Y9ptCRAh19HP532ci7mllm6na+GfQM rgYw== X-Gm-Message-State: AOAM532ngqePDlPP63d61j9PwAGDozi1DTZYELmCC8s597LuxcL3LUgA MVBXdStMhKUQ5otsnDiFULc= X-Google-Smtp-Source: ABdhPJw6F9VXUvAHFJqJTUcvRG6mBlP0+eiaH4PtqPZRNLoEVfIrc29rFlZFQkldFg8iW5wQayYq6A== X-Received: by 2002:a17:902:521:b029:dc:2836:ec17 with SMTP id 30-20020a1709020521b02900dc2836ec17mr2604978plf.47.1609912537840; Tue, 05 Jan 2021 21:55:37 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:37 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v2 1/4] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Wed, 6 Jan 2021 13:55:19 +0800 Message-Id: <20210106055522.2031-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106055522.2031-1-bmeng.cn@gmail.com> References: <20210106055522.2031-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 05:55:41 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.25.1 From MAILER-DAEMON Wed Jan 06 00:55:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1nN-0004zI-Gq for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 00:55:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37064) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1nM-0004wo-FO; Wed, 06 Jan 2021 00:55:44 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:36182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1nK-0004yK-VT; Wed, 06 Jan 2021 00:55:44 -0500 Received: by mail-pl1-x62d.google.com with SMTP id j1so1027563pld.3; Tue, 05 Jan 2021 21:55:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fkbY38y+uyqMVcJivAUjLwtmcJVovS8vLBnCWge6hes=; b=eVrb6lgnNaInpxjmsSVwlQNsZ1o2CtyuAf/BCDootbP+PO2/JTMNeCwjwxLrhF+MZ2 9qGpEiZFNAkHDYrTiV/uCTenkQfS7xhi8f/NUIIFhWHKyEbMj2NUOvImD1cWKF8Pi9OM S8ffDi8cVcUpFbksaW4WAnQuFwTBugVHUtCi4vQqyaq6GsoUbxQnqnSbLYWEXS0tP1SM N0j13l6oTrQwKoeZUFyzDPl3km5nLeBX7wY1zPsMefXpKJUIfpqWkAqDHK2f3YDkKjTv feCM24AWhvF19W8xI868fIt4ssmkEnJBGXYbCQ7mFkeXWaI2eyx9HjeFD55sZmGuiGg6 PppA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fkbY38y+uyqMVcJivAUjLwtmcJVovS8vLBnCWge6hes=; b=dx/Tkgp281audj/2mQvecy15IBp+YIfbED1NBcdkvj/w1lYo4Uw277YuvYrYuxyOpF qb5GBlteHUpu1ZDf8rd3YtKnLWH1m5UWgUluRhUb1Biul6b397uA6EbV+L4I9SuRVN9b ggePiUm+tmWr1JcSmnDfeGpdNKqPzaIIiXYSfxZpYrzuZlOmmH1a3ULatLDvUL4GavP8 3+1RSgSYlC/6zAei9YJPwfFygCEqMW1Umv3Sj/JfbRZdjz2Lecf6IAkiPeYcVbzEHzGk iYWLZ0KMoa6hnsYhMp6FuJhz4Y0UH52dgkNo1JpbPopjOhg/+9piQbLWnD46IC1R1BVq K3vQ== X-Gm-Message-State: AOAM530Qy1FfuYM0FHqfwVm38Oo7dpa+PApYnc2uRzYp6mhNlj5uiCCE tYiNrvQBJn+/1Tv5dvLDWVo= X-Google-Smtp-Source: ABdhPJxYZnj7tVNylIrzYeSHjUiFJZnK+UTbLh7NPCH3VUxkf2D315TaE29yhnE0ywsVyME68o6sAg== X-Received: by 2002:a17:902:16b:b029:dc:4ca1:f5fc with SMTP id 98-20020a170902016bb02900dc4ca1f5fcmr2758401plb.26.1609912541328; Tue, 05 Jan 2021 21:55:41 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:40 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng Subject: [PATCH v2 2/4] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() Date: Wed, 6 Jan 2021 13:55:20 +0800 Message-Id: <20210106055522.2031-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106055522.2031-1-bmeng.cn@gmail.com> References: <20210106055522.2031-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 05:55:44 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, during which CS lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Acked-by: Alistair Francis --- Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..85c172e815 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + int i; DPRINTF("\n"); @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; } -- 2.25.1 From MAILER-DAEMON Wed Jan 06 00:55:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1nS-0005Fa-MU for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 00:55:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1nR-0005CA-Gt; Wed, 06 Jan 2021 00:55:49 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:43465) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1nP-00050O-Rz; Wed, 06 Jan 2021 00:55:49 -0500 Received: by mail-pl1-x62c.google.com with SMTP id x12so1006426plr.10; Tue, 05 Jan 2021 21:55:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ctjrb0wLEu8UMxmCsMBYWKVGQJNBDXEyUZiU0DSOVTU=; b=saG65mL/nb4ayK6cIqYmLIkPX9wzVH23XMeJpwM0Nehd8UjnofpivGvFIKf+CUgJae iBVIaQfl1svNtAh1aiSm/7jX3PVcUZnIe7rHZD0IB7v6WcRnCWTVUGKNkqkCZcKDdLhO 8X395mpswr9uFl2UoIgtkXxn7v3JBIc9vBSycbtKOGLdYfMAT0sESdi+/nyi7PFnm/MH UM2qWtGztKfSpvCYxS3MZT5DsN1HC3z6CMo3KxihEChFOsK3b6ZjxTjZk7xqjbyEGj96 Gk6VlEO4bYMtOeBE1ZV29CP9Jv3Arfc/4hVkWFCrDgm+ibe8VKfpFJYWdgoUTUmeVHuE kt0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ctjrb0wLEu8UMxmCsMBYWKVGQJNBDXEyUZiU0DSOVTU=; b=CiYddmx0bhNhl2hjf0c2roz4w7oppeKYCKKUuiCZHAJTt+3nM+65qx3yfd3FZxkcuI f40UvqxJ1jRFOHsdbPlS9G1WJ45e6jouxtikzTY9fuQVVY7+4YdAEiNkhDbOieMO41jj 0y5zFriuMfJHJ9QAq9ku7EBs0p5JVE+kvLEJzY03T6xXtNGvth/3ZIo4jck6m9821Pho ezB4azwHJzm9NRjBr72vUNkhLyrIp6PjYlkL3gKVI7tRoU2tB/EG0yYk+YnHX/trOes6 EiWJUagnaOVPAdRfVGRYYg7lBSQH49vm409hX6jdtgIlsomeGT55LO3GhFgXbGzXaOOY AQDg== X-Gm-Message-State: AOAM5328YPMHOCYANaJUqGvUBQ4qC3NYJRrk9eJUn+HSjhqUMNJA7aeX 0H83VNXRl3zbTb0D+XPapKA= X-Google-Smtp-Source: ABdhPJzFxVAYYOoHU9vY3vEH5J2xSk+CSIMUWoQ1JOwMUl8lD0zihjvpQsytf5QWOrmNh1c5aEvd3w== X-Received: by 2002:a17:90a:68ca:: with SMTP id q10mr2795801pjj.15.1609912546272; Tue, 05 Jan 2021 21:55:46 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:45 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v2 3/4] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Wed, 6 Jan 2021 13:55:21 +0800 Message-Id: <20210106055522.2031-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106055522.2031-1-bmeng.cn@gmail.com> References: <20210106055522.2031-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 05:55:49 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 85c172e815..0cf07d295c 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -178,7 +178,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.25.1 From MAILER-DAEMON Wed Jan 06 00:55:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1nV-0005PL-TY for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 00:55:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1nV-0005Me-2f; Wed, 06 Jan 2021 00:55:53 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:42495) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1nT-00051s-Ds; Wed, 06 Jan 2021 00:55:52 -0500 Received: by mail-pl1-x62d.google.com with SMTP id s15so1009188plr.9; Tue, 05 Jan 2021 21:55:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1pk+YIujJUj7e3iQ8JqgaH4k0EIfTRLkfSX45O6GJA0=; b=qXNJ6YJcFKp7BJQL0ktxtvk4OqQOR5Rr3OUNVrABhXKnaNWOvOE0b9XONhahlG6GG5 c81HQSkxuZXkhwgLmFjcHsDWIeBk7d4L5PqSMvYz+JkBDYN5ujBiipoLZ/QA4JWsJhkW h+WMMV9zwiPdsynOkBLFd7Flhw3PU0d32nA+xs6LDjpWPoastlAKqgOMXBxjfq+A5CeO DR3br5j606Wp9eHm24CBZ456ISImtVWKFpKM5GIWjKmvs4tGmC3WZcISyGymOlKLTUlw QF/iJVAktYVo2zs7gfIbwUiJD+kLXltH9emeBLoEo6r7iPLTDHZHjsISre9QyuCRsrVA kfPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1pk+YIujJUj7e3iQ8JqgaH4k0EIfTRLkfSX45O6GJA0=; b=s1ZnqQMnIdWBD8cuHYBYHtSwcY39gYZ613qDfAmJUoZp2JhCCWMLpNKkDb9wa2pAHs aA8MgpD01GEtN+DkLJhiLoWj3WuMz+eYj0au5yvRm2otZcWeBDhI09FnENYLJCAbH7C4 jW0kmhlWibZFaNDQCd4dURQNi8E5FoMIAV4shfJ49G0lc4tG/5+jhv9pk46FY3y4ziq2 YE1nlBeYp1STlinKJlxg3eqRb6r5G1b1R2zopZMSUvSEwN+N62BcgKRPDUDeGDhr7Dc2 dXapMYJ3FPXo75tRsz7Z39F90yccazGQ6enadSXFsOwTRP2wqZzNe77WAPOvBGBiNhl8 KBsA== X-Gm-Message-State: AOAM531xv5EeO4qqxutnn8tYszuwIcrYM9G4QQ0eCdYPouu1DqVCidVl E7jOCE180qBPX7SAWq7/IqY= X-Google-Smtp-Source: ABdhPJye3OJK+6nEyJ04D/uPedW+PYEbbQRMwjg94QusDcdV4yDUrERF6bW1B2uVpSElDAsTaN69lA== X-Received: by 2002:a17:90a:d70e:: with SMTP id y14mr2675871pju.9.1609912549894; Tue, 05 Jan 2021 21:55:49 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:49 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v2 4/4] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Wed, 6 Jan 2021 13:55:22 +0800 Message-Id: <20210106055522.2031-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106055522.2031-1-bmeng.cn@gmail.com> References: <20210106055522.2031-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 05:55:53 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng --- (no changes since v1) hw/ssi/imx_spi.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 0cf07d295c..d45aaae320 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -156,13 +156,14 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) { uint32_t tx; uint32_t rx; + uint32_t data; + uint8_t byte; DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n", fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -180,10 +181,18 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) tx_burst = (s->burst_length % 32) ? : 32; + data = 0; + for (int i = 0; i < tx_burst / 8; i++) { + byte = tx & 0xff; + tx = tx >> 8; + data = (data << 8) | byte; + } + tx = data; + rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + byte = tx & 0xff; DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -193,12 +202,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.25.1 From MAILER-DAEMON Wed Jan 06 01:05:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1wx-00021F-Bx for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:05:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1wq-0001zU-FS; Wed, 06 Jan 2021 01:05:33 -0500 Received: from mail-yb1-xb2c.google.com ([2607:f8b0:4864:20::b2c]:42425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1wo-00019P-1V; Wed, 06 Jan 2021 01:05:31 -0500 Received: by mail-yb1-xb2c.google.com with SMTP id j17so1813967ybt.9; Tue, 05 Jan 2021 22:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ev+EbpEFLmVZe+5Epsyt5KsNPBDTv3jc41WhF2HPQOM=; b=tLfwfw3+uJadhD2f3jjZgh+w4cmrvhxkGhZeesxQFjK7UwbpsVASoVlBS2rtbu+sjX 8Yu5lWOOADC8irh7+zm5G0fIPxwlSt0oz5vGvqvZPSenM5lHzLSbnfl1Tps2pCasF/ND N6sU3eBdSzrLpk7n/0a3SF+zkTY/nRibHuW8DmTvJSzpb23++AYf+DWOmO2dsUbPYzkV sSK9AIUGc1i6OeKNO4HXqWnt0P1QGUpUowQuSvv7uYbn7ys0dyJ4MF8wLR1TiLJ8GjP+ tffTt6gijvyV4OLTqRtBQSxxJsfrCqAvXyC4pEABv25GY1iMyTG06rHnxC1OQ3axqwRm Ukfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ev+EbpEFLmVZe+5Epsyt5KsNPBDTv3jc41WhF2HPQOM=; b=Pw3H3RVDj7FEUpqEpa4N1R4nVRtMF1mLhpAnjdrJof1o6qL1ChjxQm1GKOQcHTIG9T 7zSb+urnsTdCUt15AHxrhBr332TN/da1IX2Cxa79OLBakELpXvisbSMKFDV2DILwdq3L 0AmnvBSlhPCTPwq7+3j6Ez+O5N+VyUH3Xlj/AUb/YEceekQHcDplE5zlS3E9AW3VBkF+ Ksm5si8R4i8nj9P0c7OJjZCLFpmrOpp04tMeLkt8w6Yl/fLkI0mAel81BnJND3mLXppI 6h+dEsPFOw1SxtAWyx3HDTL86NdQpsK/jHMQ9mBefP2C+/w4ePE3hBb3nr51DwteJ47u K1/w== X-Gm-Message-State: AOAM5314mXQsGAfkEN7YDMahIirdNuzwGPR25QbOofHgBC7nz4fm6Dvj mZ1EX+4hNIabu8WaedHQgEEsvbb5vFdMgkHPkSI= X-Google-Smtp-Source: ABdhPJymYw2bgwX9dPDVQii9NifEoR2jIp5hIv6TmO4tUlSnsqrnGkJRSBmYhYRW5Xq5pge9iQVXTTW/Vq0kNfTMI9I= X-Received: by 2002:a25:aaee:: with SMTP id t101mr3764854ybi.517.1609913128766; Tue, 05 Jan 2021 22:05:28 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Wed, 6 Jan 2021 14:05:17 +0800 Message-ID: Subject: Re: [PATCH v2 1/2] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Peter Maydell Cc: Alistair Francis , Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:05:34 -0000 On Wed, Jan 6, 2021 at 8:22 AM Bin Meng wrote: > > On Wed, Jan 6, 2021 at 5:11 AM Peter Maydell wrote: > > > > On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote: > > > > > > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote: > > > > > > > > Hi Alistair, Peter, > > > > > > > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote: > > > > > > > > > > From: Bin Meng > > > > > > > > > > Avoid using a magic number (4) everywhere for the number of chip > > > > > selects supported. > > > > > > > > > > Signed-off-by: Bin Meng > > > > > Reviewed-by: Alistair Francis > > > > > --- > > > > > > > > > > (no changes since v1) > > > > > > > > > > hw/ssi/imx_spi.c | 4 ++-- > > > > > include/hw/ssi/imx_spi.h | 5 ++++- > > > > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > > > > > > > > > > Ping, not sure who is going to pick up this series? > > > > > > It should be reviewed by Jean-Christophe and then probably go via the ARM tree. > > > > It doesn't seem to have been sent with a cover letter. Multi-patch > > patchsets without a cover letter tend to get missed because when > > I scan through my email looking for patches I should review or > > pick up I'm looking for either (a) single patches or (b) the 00/nn > > cover letter email... > > Thanks. I will resend it with a cover-letter. This series is resent and included in the following series with a cover letter: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=222931 Regards, Bin From MAILER-DAEMON Wed Jan 06 01:07:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx1yP-0002zI-Oi for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:07:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx1yJ-0002xS-93; Wed, 06 Jan 2021 01:07:07 -0500 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]:47023) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx1yG-0001sp-4z; Wed, 06 Jan 2021 01:07:03 -0500 Received: by mail-yb1-xb32.google.com with SMTP id f6so1795244ybq.13; Tue, 05 Jan 2021 22:06:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=7y0hhbvZTznMMzCHGJlFZj/YuRRiB2TedVaDCsTT4PY=; b=gmo6TMLNjkZ+LXD9KNQ6joWIfjYt/yxzKe1zk2Sq9lOqGuVaNVVU7uVHReXflEvL+E 3LytJUIN2gUn/rEn5JNaV9hQJsJdBC4m3Fkt4Nq70jdQt9RANyk1fgfAa7gM/cyKJg6j b8Vf8/Pst+iTe6EhdLCzEAqiRdeT6+jfyrkZgjgpc6Uxwm15jdW+lTw+w2nx9ONJfBz5 MEKja0MXw3EHK8WPivgHXJ73Oq4wLHqQcolZXhD/dJ1w7Kfz5swReX/gXYGNFymP9emf VzSockhQgeGvRJl0PurMUwvjXGdD9EfifReIVr0aU0KilJvmIg6bygCgMSob+IdGzDhS Qr2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=7y0hhbvZTznMMzCHGJlFZj/YuRRiB2TedVaDCsTT4PY=; b=LQFCjF+AY41RtPbhXQAaiMDppKNFhB6WNleBnxN477hlRYYdUoTyFQraX5o2uH15gz sFPEYJLTvL3BbukEKTDpakhriFDTMAgf5BhGzUfwt0lREIBI+B+F7v0uMVmsMTITx58p L9uUsZ9WxZA65c1O4LGEl1QDhXlQ3YCJuBuetOnPXoCeV9d/TL1WAv635WgQI+m8B4V3 0Txakknl15R2k0qQerUNwuuFrCVkMJQ+81Infz6+YssDjh9K8OxgwuAPuYZ3XE6GGZPI xU1K56yP6BRtF4CxAFYpCbVdGEKD8emPZ4fmioh1LGxVGVydk0wAvKwauDZKooyYgbfK OGdA== X-Gm-Message-State: AOAM531NiRUPPDz1CvZZ8ItJGF7M30l1tmBcSiAxheLh2aZ4Qk3GgjAp R3gshLMLb1iBEBu9B/8WaNLtVWGmBB1turQvdr8= X-Google-Smtp-Source: ABdhPJxgm3Tqb6yigalIvoRLJHxDyKUSdTWUPB7s7RQp3FJpIv8R4P1yNhsLo8AgxnuT+HetG8Q9O3VKGG2AnB54dDc= X-Received: by 2002:a05:6902:210:: with SMTP id j16mr4193590ybs.122.1609913218717; Tue, 05 Jan 2021 22:06:58 -0800 (PST) MIME-Version: 1.0 References: <1608182913-54603-1-git-send-email-bmeng.cn@gmail.com> <54a57f94-e0e5-6dfd-2813-a38e374f221c@amsat.org> In-Reply-To: <54a57f94-e0e5-6dfd-2813-a38e374f221c@amsat.org> From: Bin Meng Date: Wed, 6 Jan 2021 14:06:47 +0800 Message-ID: Subject: Re: [PATCH 1/2] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:07:07 -0000 On Thu, Dec 31, 2020 at 6:31 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 12/17/20 6:28 AM, Bin Meng wrote: > > From: Bin Meng > > > > For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: > > > > 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in s= econd word. > > 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in s= econd word. > > > > Current logic uses either s->burst_length or 32, whichever smaller, > > to determine how many bits it should read from the tx fifo each time. > > For example, for a 48 bit burst length, current logic transfers the > > first 32 bit from the first word in the tx fifo, followed by a 16 > > bit from the second word in the tx fifo, which is wrong. The correct > > logic should be: transfer the first 16 bit from the first word in > > the tx fifo, followed by a 32 bit from the second word in the tx fifo. > > > > With this change, SPI flash can be successfully probed by U-Boot on > > imx6 sabrelite board. > > > > =3D> sf probe > > SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, = total 2 MiB > > > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > > Signed-off-by: Bin Meng > > --- > > > > hw/ssi/imx_spi.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index 85c172e..509fb9f 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -178,7 +178,10 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > > > DPRINTF("data tx:0x%08x\n", tx); > > > > - tx_burst =3D MIN(s->burst_length, 32); > > + tx_burst =3D s->burst_length % 32; > > + if (tx_burst =3D=3D 0) { > > + tx_burst =3D 32; > > + } > > Or alternatively using ternary operator: > > tx_burst =3D (s->burst_length % 32) ?: 32; Updated this in v2 series: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D222931 > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Regards, Bin From MAILER-DAEMON Wed Jan 06 01:35:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2Ph-0000O3-LY for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:35:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2Pg-0000Np-5p; Wed, 06 Jan 2021 01:35:20 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:43585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx2Pd-0006Dc-8Z; Wed, 06 Jan 2021 01:35:19 -0500 Received: by mail-pl1-x630.google.com with SMTP id x12so1052020plr.10; Tue, 05 Jan 2021 22:35:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rLgYDF/7oFhtxXtNL3KpSkY7bc4IwwkgKlQx9pF1SDA=; b=Jtx43lVg2e+9H9KQvq/4g+s6bHrXknYf4lXNZgvYuitJKxVLUXCKl8IoVCJ0sU9TT9 YFGI93mE6u6uT2ngnJaUGoE9r6Eyz80vZNQSXjOPJ7ehRj/7pquOk2cz801p11Z+x9HC 54e7Ej4ShwNGFPburn76ot83xPCCew3Ls5gkNySwYDJzXYcYliku14NNTUfE3rOVraYH Ai1bgRIoanwwqmi/HLsHyaasMLmqoW4NHekFPOUDlLLKM0tvH/otX0hIMs0yc6sk0AlQ OJ3ZQ/4DwWuWSiaU4QJGrcUgnLaxIQKDgqg1YC6ogKYqb/B3OKhJwNUOtW9iGz71nDmV t4MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rLgYDF/7oFhtxXtNL3KpSkY7bc4IwwkgKlQx9pF1SDA=; b=LVblMKzGUajL5Up2JQ4FjsB9EsrIUPHEyvwGuOIV/TotMaK3Wbc2go8VZY6uFpDOIn oPfF92kzBZMUC9vhEMv162ci+JYji5yIQNiTM06QdLOVMQjGzwuzPi7XVDHrvMcupalZ YXmoM1IYyRaCKIvpOEkuCUIY+fGnfiwJOJWNtueRaBiyw6EaJ3p7PHDqbj8Jj7i77eIc cBQ0nfqfEYFqJcIiYlrwdPXacb3sXAfMnAYtzXluKu81UwLjvzT0Ljb9Iy7x4kQXgsUC 4H0dDCem+00/gp2Fu96BOxVI1hkyFeLqZ5tu0Qzlyarwm5ydR1/0JXWNpVpHWe//LU7X QKbw== X-Gm-Message-State: AOAM532h7JAntA+5absVre6StUXxvqxOYVRJxU1cUci5v0M0HGDTD8ez L2eZ+Av6zuLWV0v+J7e509A= X-Google-Smtp-Source: ABdhPJwU6wVXN0TfF7oZcQvpiDBg7zVbYfp/0RIEUzC2GPfoChodKmvnGCr4dLtn+WAU+uGK/043iA== X-Received: by 2002:a17:90a:eacf:: with SMTP id ev15mr2941548pjb.174.1609914915478; Tue, 05 Jan 2021 22:35:15 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id cu4sm1132976pjb.18.2021.01.05.22.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 22:35:15 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 0/4] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot Date: Wed, 6 Jan 2021 14:35:00 +0800 Message-Id: <20210106063504.10841-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:35:20 -0000 From: Bin Meng At present the upstream U-Boot (as of today, v2021.01-rc3) does not boot on QEMU sabrelite machine. This fixes several issues to improve emulation fidelity of the i.MX6 sabrelite board. With this series, upstream U-Boot can boot to U-Boot command shell. While we are here, add a target guide for this board to help people run Linux kernel and U-Boot on QEMU. Changes in v3: - correct 2 typos in sabrelite.rst Changes in v2: - new patch: add sabrelite target guide Bin Meng (4): hw/misc: imx6_ccm: Update PMU_MISC0 reset value hw/msic: imx6_ccm: Correct register value for silicon type hw/arm: sabrelite: Connect the Ethernet PHY at address 6 docs/system: arm: Add sabrelite board description docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + hw/arm/sabrelite.c | 4 ++ hw/misc/imx6_ccm.c | 4 +- 4 files changed, 126 insertions(+), 2 deletions(-) create mode 100644 docs/system/arm/sabrelite.rst -- 2.25.1 From MAILER-DAEMON Wed Jan 06 01:35:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2Pn-0000RN-Rd for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:35:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2Pi-0000OX-4z; Wed, 06 Jan 2021 01:35:22 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:38001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx2Pg-0006HW-DX; Wed, 06 Jan 2021 01:35:21 -0500 Received: by mail-pj1-x102a.google.com with SMTP id j13so1084388pjz.3; Tue, 05 Jan 2021 22:35:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hI10iUcIAI/iQ1m4mauQ5SNhBSk9eoPehRL5woqTjh0=; b=Cirqna35dtXcLZQD2EsT66GQGcUbjHQdzG1rkJ09VrqTojHqqeycKV+wyMbMlX563Z cM3Nq9hpiyxcj4CYwa8s4c5esP/zfFUnMfQlMG95fEYbhDzkXxKH5y6dogE3gslqu3OY j8ITonjQ5IL1gkYMp3ANDwNcLlMgnAGEuOPp68yHz7DHPJytWTASupvQperkEBdk+aDa zLbYac4QlUUySnqG4cAgOUYNAjvuIjGgOO94O/CmxY6VlzaOYwanB8VyOQXZ6wfN3mNq 6KHn3LdMwEnNch3+lRLruN8Ekig/FUpbAv9HfsgsRd1PUyYVH8yAdXJvDDsqGG7jHmIU VIzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hI10iUcIAI/iQ1m4mauQ5SNhBSk9eoPehRL5woqTjh0=; b=i9bCiRPRtLeV80twdGlAvKJWUF57rzfcORv/WwWFujnTMjH/+hLZGSac7pufwg0pHK IL4iSwA5klsQaY14J6i06NlgUbDC8fIA1AeCE1EJaNSYc6g2gPta47DDK+LFLfc7l084 tmyHSLubUrhsyvbCbxOlLbJlMSUjp5UssIz/IEY0+Di/qZfu1RHPjfvdZ4Vjk+GokRxL 4ET+Fzj1Ygm3xjT2Ahr3aIoiDlA8ckPQRlP+g7m2lILuynk0NtUt7q7OQ9NsQY+QDokf 8WjPPjB/0Gbi5PXT8tLAAp9CLCidIn5sUB2tRw7iNAB3nmzBTCaRVFJWYkE4ogoSL3e3 nasA== X-Gm-Message-State: AOAM5317QiiaP3DKH/x1KYQzIYg5vvaHA8EFuClaLV6Ww49lwDxqQY2o wC7kLHn8ZE6ZGcUtOzuxghc= X-Google-Smtp-Source: ABdhPJwGl7aSlb4N5qQUKOqbhaQy/7mo+ogiUeTv28yqfxJdN96xOBYNX+F7U2vNubF0yR3Exi3TNA== X-Received: by 2002:a17:902:bf4a:b029:da:d0b8:6489 with SMTP id u10-20020a170902bf4ab02900dad0b86489mr3170171pls.58.1609914918392; Tue, 05 Jan 2021 22:35:18 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id cu4sm1132976pjb.18.2021.01.05.22.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 22:35:17 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 1/4] hw/misc: imx6_ccm: Update PMU_MISC0 reset value Date: Wed, 6 Jan 2021 14:35:01 +0800 Message-Id: <20210106063504.10841-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106063504.10841-1-bmeng.cn@gmail.com> References: <20210106063504.10841-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:35:22 -0000 From: Bin Meng U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap() in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the bandgap has stabilized. With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6 sabrelite board (mx6qsabrelite_defconfig), with a slight change made by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot shell on QEMU with the following command: $ qemu-system-arm -M sabrelite -smp 4 -m 1G -kernel u-boot \ -display none -serial null -serial stdio Boot log below: U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800) CPU: Freescale i.MX?? rev1.0 at 792 MHz Reset cause: POR Model: Freescale i.MX6 Quad SABRE Lite Board Board: SABRE Lite I2C: ready DRAM: 1 GiB force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55 force_idle_bus: failed to clear bus, sda=0 scl=0 force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c force_idle_bus: failed to clear bus, sda=0 scl=0 force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5 force_idle_bus: failed to clear bus, sda=0 scl=0 MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - No block device, using default environment In: serial Out: serial Err: serial Net: Board Net Initialization Failed No ethernet found. starting USB... Bus usb@2184000: usb dr_mode not found USB EHCI 1.00 Bus usb@2184200: USB EHCI 1.00 scanning bus usb@2184000 for devices... 1 USB Device(s) found scanning bus usb@2184200 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found Hit any key to stop autoboot: 0 => Signed-off-by: Bin Meng Reviewed-by: Alex Bennée --- (no changes since v1) hw/misc/imx6_ccm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index cb740427ec..7e031b6775 100644 --- a/hw/misc/imx6_ccm.c +++ b/hw/misc/imx6_ccm.c @@ -450,7 +450,7 @@ static void imx6_ccm_reset(DeviceState *dev) s->analog[PMU_REG_3P0] = 0x00000F74; s->analog[PMU_REG_2P5] = 0x00005071; s->analog[PMU_REG_CORE] = 0x00402010; - s->analog[PMU_MISC0] = 0x04000000; + s->analog[PMU_MISC0] = 0x04000080; s->analog[PMU_MISC1] = 0x00000000; s->analog[PMU_MISC2] = 0x00272727; -- 2.25.1 From MAILER-DAEMON Wed Jan 06 01:35:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2Pp-0000Uz-EG for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:35:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2Pn-0000Ql-Cc; Wed, 06 Jan 2021 01:35:27 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:43070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx2Pi-0006Km-Ty; Wed, 06 Jan 2021 01:35:27 -0500 Received: by mail-pg1-x52f.google.com with SMTP id n10so1544284pgl.10; Tue, 05 Jan 2021 22:35:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vUQGbC64bDqMXxpl/W2K5oV7pP0S99JpmeJuH9H8/cc=; b=kYw4/eTB1G6lMgphoYcEdTkE6Y3XhuX7y2Gv1Z79nxdeYmFTIvUx208b6pzhS/G4bM K04OygNhrCQ2C6yl/tMkHS5JJVpYjAlP1WmcGP1SSRb0uiGyZi1lS9KtnXMDWQUzC4/p xd5ThvHyjBDpLuQALbQdmF2M97VmVQ1HRQz+UmA0oHlLNh7ExzsiNbcSoe4RjN9Kbx7H BEUm8sahraxA0dYKZkr+qKxMous7CkYtur+it0qG4PxNQKq3Zi759JkV+426ihXaVvf9 53J0AaGH7GF1APxwJoQKDV+z4NrI7RrYvBhTsnI2vIAn4v79XvzdJQd1CZa0+lnT56QO j10A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vUQGbC64bDqMXxpl/W2K5oV7pP0S99JpmeJuH9H8/cc=; b=PN4q4rYEHrq08G6mkrUOJS2+Amn3s7NjVoIsOg07XInMNTAKmRSznYpE7GeXMyvAlK +Gllip20J95oqVp+IbHwwLkF60zTuBMJRkauKoBMsEs6r/+MCjGqvsXJrMQEayuMh4YZ DaLaTy+rD4qWjakIvIEeUjmlwHiTXwfaSWW/m3imhX4T2Sv6lqHO2SON4DW6Xk0Az4SD HAuz5WVBGxf0KpJuYsVeZ/CvYypGJKmRQvM7BfltuvGXtNQZF1T62GjktXhAwKryOQvs yQYMvmL+mYKQSrLVsBZbKU+mt9VIEZmk5jBrWxa/nf9/WxkLGsmFuIgheDD6OLbLBgfp 2fng== X-Gm-Message-State: AOAM530OBE9kHXxa/tOzkzn17EU4duvRhFFzwuHmCdFJUvM/F+vqdKcH MvQgmJlxHOaEBICfxY3ewFs= X-Google-Smtp-Source: ABdhPJzor6mekBld2kLIpXbxd8gS8ZKt2oH2WYSIzudsMYA3FcnH49deBSZ2z2x5vGQH1RzhRWQL0w== X-Received: by 2002:a05:6a00:14d1:b029:19d:d135:bacf with SMTP id w17-20020a056a0014d1b029019dd135bacfmr2459792pfu.12.1609914921290; Tue, 05 Jan 2021 22:35:21 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id cu4sm1132976pjb.18.2021.01.05.22.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 22:35:20 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 2/4] hw/msic: imx6_ccm: Correct register value for silicon type Date: Wed, 6 Jan 2021 14:35:02 +0800 Message-Id: <20210106063504.10841-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106063504.10841-1-bmeng.cn@gmail.com> References: <20210106063504.10841-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:35:27 -0000 From: Bin Meng Currently when U-Boot boots, it prints "??" for i.MX processor: CPU: Freescale i.MX?? rev1.0 at 792 MHz The register that was used to determine the silicon type is undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we can refer to get_cpu_rev() in arch/arm/mach-imx/mx6/soc.c in the U-Boot source codes that USB_ANALOG_DIGPROG is used. Update its reset value to indicate i.MX6Q. Signed-off-by: Bin Meng Reviewed-by: Alex Bennée --- (no changes since v1) hw/misc/imx6_ccm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index 7e031b6775..4c830fd89a 100644 --- a/hw/misc/imx6_ccm.c +++ b/hw/misc/imx6_ccm.c @@ -462,7 +462,7 @@ static void imx6_ccm_reset(DeviceState *dev) s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x00000004; s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000; s->analog[USB_ANALOG_USB2_MISC] = 0x00000002; - s->analog[USB_ANALOG_DIGPROG] = 0x00000000; + s->analog[USB_ANALOG_DIGPROG] = 0x00630000; /* all PLLs need to be locked */ s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK; -- 2.25.1 From MAILER-DAEMON Wed Jan 06 01:35:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2Pq-0000Xi-SC for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:35:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2Po-0000TB-UK; Wed, 06 Jan 2021 01:35:28 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:41429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx2Pn-0006Nn-ES; Wed, 06 Jan 2021 01:35:28 -0500 Received: by mail-pl1-x632.google.com with SMTP id y8so1058956plp.8; Tue, 05 Jan 2021 22:35:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CXG7bK3DGo/swZLf3xUG4CksXWWUngcawbrNPY8Gm1o=; b=LHZ6mdL7ECrIk0DSUNHKlIRmiWe71383NBHMeAggswZHKZiSZ3xctUiFSL9YSrgbgx Q+WZ0tYqT5D6NeaQObm5XZNuXcTtMqOFTlAf+YOXOgP9bqApsTc3YebU/JHTe48+m6B3 gl5iHUT1wP+QXYvjXgijBittEE3MjeOGqGnHM/8bnMlDuvaL4Rvr5D1xI5hwZGOZ47Kk S6wDqynDhzewulPPGEh1nTDcgj7s9MqTquzZD4js6IAkaZOESylDF7RtBXkKEzXoBBNu O89e4CPHMv7FPkMtc4lZIWzO9jptOrgtF4xabbZG49+NB1T9pBXDRndXDQzDdidQDjy5 UiVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXG7bK3DGo/swZLf3xUG4CksXWWUngcawbrNPY8Gm1o=; b=GSHUQB3M+UtTaLIMELKaxFLP2KAUNJWbaHPD+rQUCXYTpZJgdP2udXwcQWFoSnUhCE orKCbYLyhhdKnvI/DJ5EjqLHtLEW3EPP1MmNKx1cdZHvbabBvYHEHTZ32mKjKsTK0EXu 9kxsQO1MYyN6178nkVu/ZA5dwJnqB+L2hhv/0+SePYtdQ+RMFAyVsXZbmFZPcxn1XwfO cmXzzoXF/RugwCxusdsrJj5w5qXoHdTiRyiQhtzzyObYSgMQvuIwXJlgqdAsdr/R1dvw 7qbvN//K4lAPlCpBKayNnl076l8SlriN9M9Tbvf88YnRbxYQN4moaCGqx/KD8Tv2EJSO oYhA== X-Gm-Message-State: AOAM531uQyK7Am+3t5hRvd2aveLyWjv3+bHAmspOB/mlN9/0OI8o4fL8 jy3XDEG7bgdE2y36/Q3FEw7gJOqFxi4= X-Google-Smtp-Source: ABdhPJyOtT/Dzea5HsTFMD2HJVEVlpVqcOS2hxl0kKuEjQyj7KLnuly37ZqQkh1gQxB5lisfFE3RYg== X-Received: by 2002:a17:902:6b87:b029:dc:3402:18af with SMTP id p7-20020a1709026b87b02900dc340218afmr3126456plk.29.1609914924141; Tue, 05 Jan 2021 22:35:24 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id cu4sm1132976pjb.18.2021.01.05.22.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 22:35:23 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6 Date: Wed, 6 Jan 2021 14:35:03 +0800 Message-Id: <20210106063504.10841-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106063504.10841-1-bmeng.cn@gmail.com> References: <20210106063504.10841-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:35:29 -0000 From: Bin Meng At present, when booting U-Boot on QEMU sabrelite, we see: Net: Board Net Initialization Failed No ethernet found. U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real board, the Ethernet PHY is at address 6. Adjust this by updating the "fec-phy-num" property of the fsl_imx6 SoC object. With this change, U-Boot sees the PHY but complains MAC address: Net: using phy at 6 FEC [PRIME] Error: FEC address not set. This is due to U-Boot tries to read the MAC address from the fuse, which QEMU does not have any valid content filled in. However this does not prevent the Ethernet from working in QEMU. We just need to set up the MAC address later in the U-Boot command shell, by: => setenv ethaddr 00:11:22:33:44:55 Signed-off-by: Bin Meng Reviewed-by: Alex Bennée --- (no changes since v1) hw/arm/sabrelite.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 91d8c43a7e..a3dbf85e0e 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -51,6 +51,10 @@ static void sabrelite_init(MachineState *machine) s = FSL_IMX6(object_new(TYPE_FSL_IMX6)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + + /* Ethernet PHY address is 6 */ + object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); + qdev_realize(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, -- 2.25.1 From MAILER-DAEMON Wed Jan 06 01:35:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2Pt-0000dB-2B for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 01:35:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42300) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2Pq-0000Xo-S3; Wed, 06 Jan 2021 01:35:30 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:41399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx2Po-0006QT-MS; Wed, 06 Jan 2021 01:35:30 -0500 Received: by mail-pf1-x429.google.com with SMTP id t8so1144491pfg.8; Tue, 05 Jan 2021 22:35:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zirkRo36lTO4K/qI+C44rWOQIVLw5skxXSXDCk/pUuk=; b=EKu+6UpcBy1Tv9H8dQ/07rW4qzuces4VX5DmsfSS/aQ5+lztA9W1QbWL83suPklalP cfFTwnMQtNkctSyasKiX9WRrSJst3U/W19PSC3YousmrA1xXkEg9s6pdX/EzgGmkNqMi o/4fNoT3SZf+jztYOIthh4GRTuf8uxUHAZIsAPA/wBPeggHiIuKLC5hA5zP8iuGU/aH0 8WtXFYO28Jm+lqxzTQUaAViWW1h9xaCxiEg3nuJBfVZI6MKFbXp4SnmaRhQsUpq2p4Gm CPxKykRT+JcXq8vC4AeUs3pvJ/TGypSCbGP1QrH/zT/pjnGXGdE6aTyzkiHJhRw9HCqK UrIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zirkRo36lTO4K/qI+C44rWOQIVLw5skxXSXDCk/pUuk=; b=co9F07M6cADR0XOTbaICXLb4IEY5I+WihKIwNxiXKPzTncZeEYsUhAK5vt0mnzgi2q O3QfEBaLPiGg98mSeenwl59I+I2IzgpV1nSr/Ob6lkaYDT82ZmQfOmZcHX1lTxh2VlQU jKSjBcsw2N0/ufYTnKh17DDXnAnwAkS0/nXKsnz1CUxPwgcgmHaYe/qTIyHlZoVqztXQ H493grx4GA99vYtrcgH1rWEItSw+jJLziOklkKukRCPzwaFRglyYNsMWBq/fs5e+JU2Y iCfTVbMTZcvc2zFTApAcCFrGr8ImYOYRpagxCfN7kZ4Fl3E1Go4yj5Xx/XA9tONDEdZf Z0/w== X-Gm-Message-State: AOAM530OaKUU/jt+ti/zp3/wH3YhIPk/KUtewXSYRNu+3nw5I/vwDe1L b3w3lAbGWgLp5YqKWLYQ/hrqTi4v9aQ= X-Google-Smtp-Source: ABdhPJwDtFD+iIX78m2ia0TKjGvnyCfpqy/giSENGmC5vcQFgoS/JJ5oHvP/iN7Q7sFXaEUW2CdNqw== X-Received: by 2002:a63:d141:: with SMTP id c1mr2939779pgj.75.1609914927117; Tue, 05 Jan 2021 22:35:27 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id cu4sm1132976pjb.18.2021.01.05.22.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 22:35:26 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jean-Christophe Dubois , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 4/4] docs/system: arm: Add sabrelite board description Date: Wed, 6 Jan 2021 14:35:04 +0800 Message-Id: <20210106063504.10841-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106063504.10841-1-bmeng.cn@gmail.com> References: <20210106063504.10841-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 06:35:31 -0000 From: Bin Meng This adds the target guide for SABRE Lite board, and documents how to boot a Linux kernel and U-Boot bootloader. Signed-off-by: Bin Meng Reviewed-by: Alex Bennée --- Changes in v3: - correct 2 typos in sabrelite.rst Changes in v2: - new patch: add sabrelite target guide docs/system/arm/sabrelite.rst | 119 ++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 120 insertions(+) create mode 100644 docs/system/arm/sabrelite.rst diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst new file mode 100644 index 0000000000..71713310e3 --- /dev/null +++ b/docs/system/arm/sabrelite.rst @@ -0,0 +1,119 @@ +Boundary Devices SABRE Lite (``sabrelite``) +=========================================== + +Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development +platform featuring the powerful Freescale / NXP Semiconductor's i.MX 6 Quad +Applications Processor. + +Supported devices +----------------- + +The SABRE Lite machine supports the following devices: + + * Up to 4 Cortex A9 cores + * Generic Interrupt Controller + * 1 Clock Controller Module + * 1 System Reset Controller + * 5 UARTs + * 2 EPIC timers + * 1 GPT timer + * 2 Watchdog timers + * 1 FEC Ethernet controller + * 3 I2C controllers + * 7 GPIO controllers + * 4 SDHC storage controllers + * 4 USB 2.0 host controllers + * 5 ECSPI controllers + * 1 SST 25VF016B flash + +Please note above list is a complete superset the QEMU SABRE Lite machine can +support. For a normal use case, a device tree blob that represents a real world +SABRE Lite board, only exposes a subset of devices to the guest software. + +Boot options +------------ + +The SABRE Lite machine can start using the standard -kernel functionality +for loading a Linux kernel, U-Boot bootloader or ELF executable. + +Running Linux kernel +-------------------- + +Linux mainline v5.10 release is tested at the time of writing. To build a Linux +mainline kernel that can be booted by the SABRE Lite machine, simply configure +the kernel using the imx_v6_v7_defconfig configuration: + +.. code-block:: bash + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-linux-gnueabihf- + $ make imx_v6_v7_defconfig + $ make + +To boot the newly built Linux kernel in QEMU with the SABRE Lite machine, use: + +.. code-block:: bash + + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ + -display none -serial null -serial stdio \ + -kernel arch/arm/boot/zImage \ + -dtb arch/arm/boot/dts/imx6q-sabrelite.dtb \ + -initrd /path/to/rootfs.ext4 \ + -append "root=/dev/ram" + +Running U-Boot +-------------- + +U-Boot mainline v2020.10 release is tested at the time of writing. To build a +U-Boot mainline bootloader that can be booted by the SABRE Lite machine, use +the mx6qsabrelite_defconfig with similar commands as described above for Linux: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-linux-gnueabihf- + $ make mx6qsabrelite_defconfig + +Note we need to adjust settings by: + +.. code-block:: bash + + $ make menuconfig + +then manually select the following configuration in U-Boot: + + Device Tree Control > Provider of DTB for DT Control > Embedded DTB + +To start U-Boot using the SABRE Lite machine, provide the u-boot binary to +the -kernel argument, along with an SD card image with rootfs: + +.. code-block:: bash + + $ qemu-system-arm -M sabrelite -smp 4 -m 1G \ + -display none -serial null -serial stdio \ + -kernel u-boot + +The following example shows booting Linux kernel from dhcp, and uses the +rootfs on an SD card. This requires some additional command line parameters +for QEMU: + +.. code-block:: none + + -nic user,tftp=/path/to/kernel/zImage \ + -drive file=sdcard.img,id=rootfs -device sd-card,drive=rootfs + +The directory for the built-in TFTP server should also contain the device tree +blob of the SABRE Lite board. The sample SD card image was populated with the +root file system with one single partition. You may adjust the kernel "root=" +boot parameter accordingly. + +After U-Boot boots, type the following commands in the U-Boot command shell to +boot the Linux kernel: + +.. code-block:: none + + => setenv ethaddr 00:11:22:33:44:55 + => setenv bootfile zImage + => dhcp + => tftpboot 14000000 imx6q-sabrelite.dtb + => setenv bootargs root=/dev/mmcblk3p1 + => bootz 12000000 - 14000000 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index bde4b8e044..edd013c7bb 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -83,6 +83,7 @@ undocumented; you can get a complete list by running arm/versatile arm/vexpress arm/aspeed + arm/sabrelite arm/digic arm/musicpal arm/gumstix -- 2.25.1 From MAILER-DAEMON Wed Jan 06 02:07:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx2v5-0004fB-H7 for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 02:07:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2v3-0004f0-HY; Wed, 06 Jan 2021 02:07:45 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3020) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx2uy-0004F3-13; Wed, 06 Jan 2021 02:07:45 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D9gQD5RSpzj392; Wed, 6 Jan 2021 15:06:28 +0800 (CST) Received: from [10.174.184.42] (10.174.184.42) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Jan 2021 15:07:13 +0800 Subject: Re: [PATCH v2 0/2] accel: kvm: Some bugfixes for kvm dirty log To: Peter Maydell , Paolo Bonzini , "Dr . David Alan Gilbert" References: <20201217014941.22872-1-zhukeqian1@huawei.com> CC: Andrew Jones , Peter Xu , , , , Zenghui Yu , From: Keqian Zhu Message-ID: <6c1a62af-1aa7-cc7f-28de-9761d88faa8f@huawei.com> Date: Wed, 6 Jan 2021 15:07:12 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <20201217014941.22872-1-zhukeqian1@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhukeqian1@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.249, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 07:07:45 -0000 Friendly ping ... Hi, please queue this well reviewed series, Thanks :-) Keqian On 2020/12/17 9:49, Keqian Zhu wrote: > Hi all, > > This series fixes memory waste and adds alignment check for unmatched > qemu_real_host_page_size and TARGET_PAGE_SIZE. > > Thanks. > > Keqian Zhu (2): > accel: kvm: Fix memory waste under mismatch page size > accel: kvm: Add aligment assert for kvm_log_clear_one_slot > > accel/kvm/kvm-all.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > From MAILER-DAEMON Wed Jan 06 02:17:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx34c-0006EZ-4j for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 02:17:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx34Z-0006Dk-VI; Wed, 06 Jan 2021 02:17:35 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2925) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx34Y-0000Xm-BJ; Wed, 06 Jan 2021 02:17:35 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D9gdW66kzzMG23; Wed, 6 Jan 2021 15:16:15 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.184.42) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Jan 2021 15:17:18 +0800 From: Keqian Zhu To: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Stefan Hajnoczi" CC: Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , , , , Keqian Zhu , Subject: [PATCH v2] Docs/RCU: Correct sample code of qatomic_rcu_set Date: Wed, 6 Jan 2021 15:17:10 +0800 Message-ID: <20210106071710.15836-1-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhukeqian1@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 07:17:36 -0000 Correct sample code to avoid confusing readers. Signed-off-by: Keqian Zhu Cc: qemu-trivial@nongnu.org Reviewed-by: Paolo Bonzini Reviewed-by: Peter Xu --- v2: - Add Cc and R-b. --- docs/devel/rcu.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/rcu.txt b/docs/devel/rcu.txt index cdf002edd8..2e6cc607a1 100644 --- a/docs/devel/rcu.txt +++ b/docs/devel/rcu.txt @@ -392,7 +392,7 @@ Instead, we store the size of the array with the array itself: /* Removal phase. */ old_array = global_array; - qatomic_rcu_set(&new_array->data, new_array); + qatomic_rcu_set(&global_array, new_array); synchronize_rcu(); /* Reclamation phase. */ -- 2.19.1 From MAILER-DAEMON Wed Jan 06 07:13:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kx7hB-0002iU-Mb for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 07:13:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kx4PZ-0001o0-6A for qemu-arm@nongnu.org; Wed, 06 Jan 2021 03:43:21 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:36651) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kx4PW-0007OX-M8 for qemu-arm@nongnu.org; Wed, 06 Jan 2021 03:43:20 -0500 Received: by mail-ej1-x62e.google.com with SMTP id lt17so4064297ejb.3 for ; Wed, 06 Jan 2021 00:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=c+EzoNODPzaBLH17xv1nNpILReIYs1e3B66+EmkgoMM=; b=SOaUizf7Moe+GVf2RJ/oAuNWu5tiZdf9MsA79cizt5BczfuH/4Z3rfDKXRuxoZsi6y 07KdWbt7mCF7LatGNvfNH77Ow9OK7Rcx0spmOBEy4KkoExUfV6IOfuP1xA4AGzbFUbFS SB+Hch4kVMs0vkF2yrTNJx1vabi6Of7mcnL2/VR0HxTXW5BiaPjDITHDxoJzoHQGqNLA PmtugTYuBe0+FP/9CdbM//e9zAzt3EDd7BLRbo3Q5SUlV/poWL4Bzxs6BSM8nb0YALAN Byp49QNjU6yKqJExInQ56wjNoPAnmsD7aoZ2COujcU3DCkgj1gRmjy4D+phyJIvekkM/ 57ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=c+EzoNODPzaBLH17xv1nNpILReIYs1e3B66+EmkgoMM=; b=sXXfyPHxSh6VqyXvF2TJUPen+CbJ1vA/VHX3mUxY0TQo/UqSHEhBcp98zX2TctS1g3 ct/w/FshW5g/z62H7QxPMoEnmUTGNNlk4E/ScdXrqtzpn1Tb0bvAV5zWnXWhfIWNqlGT ooFPr7YM6VWnrBX4DAvd5cGKvOpefNjOstAKw4AcyA0Lgcwm+cCTgoOeQ3JsVStP7A+/ siA+55hF99NhXdpVo+La4W+9UoXazYO6bpvEcivHBIyfnTBekYlW0zp3aauXltgOihTx mMIQGDXJmBtM49hHlHlKgxvt1qGd0qxMGsKup4sdHa1on7IHmSRARUrNVapdukHsfggf Vsaw== X-Gm-Message-State: AOAM533TUChXyC/GzBVI1BZvUeKOkGEu+UNENUnzFuMgDlTRt1/EQRiX mD9OvehN2UYVIhaf99/50In8MV7nIJlFiCCyk5hcAYbhMRzKig== X-Google-Smtp-Source: ABdhPJy9IM/r8g4BHTEQMcN0KK6oCQE7tYPrQ+QqShLOHCLNapWhf7/IWcs8tuUxa0NWqgxGhlqFwzqm/YZVyr6nPJg= X-Received: by 2002:a17:906:1f07:: with SMTP id w7mr2117055ejj.519.1609922596661; Wed, 06 Jan 2021 00:43:16 -0800 (PST) MIME-Version: 1.0 From: Yu Nexus Date: Wed, 6 Jan 2021 09:43:06 +0100 Message-ID: Subject: MTE support inside QEMU? To: qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="0000000000007d700e05b8375073" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=yunextus@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 06 Jan 2021 07:13:44 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 08:43:21 -0000 --0000000000007d700e05b8375073 Content-Type: text/plain; charset="UTF-8" Is there full support for ARMv8.5 Memory Tagging Extensions (MTE) inside QEMU? So is this MTE example code supposed to work inside QEMU? https://www.kernel.org/doc/html/latest/arm64/memory-tagging-extension.html --0000000000007d700e05b8375073 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Is there full support fo= r ARMv8.5 Memory Tagging Extensions (MTE) inside QEMU?
So is this MTE example code supposed to work inside QEMU?=C2=A0https://www.kernel.org/doc/html/latest/arm64/memory= -tagging-extension.html
--0000000000007d700e05b8375073-- From MAILER-DAEMON Wed Jan 06 11:04:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxBIE-0008Jn-2Q for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 11:04:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxBID-0008JZ-25; Wed, 06 Jan 2021 11:04:13 -0500 Received: from mta-02.yadro.com ([89.207.88.252]:46288 helo=mta-01.yadro.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxBIA-0001bL-PC; Wed, 06 Jan 2021 11:04:12 -0500 Received: from localhost (unknown [127.0.0.1]) by mta-01.yadro.com (Postfix) with ESMTP id 3DEFE412D6; Wed, 6 Jan 2021 16:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=yadro.com; h= in-reply-to:content-disposition:content-type:content-type :mime-version:references:message-id:subject:subject:from:from :date:date:received:received:received; s=mta-01; t=1609949046; x=1611763447; bh=4kxhXyFP2O5PFcbvvlJD21aFOWi3oLeDiYHrHgCqs/U=; b= VYmJgxsHjf11/fdrkDpxdOr0o9cvRSGRPnF4HCUsSVYm/g+FDUmLmVe0l0G5AM2M e+IiF2Dm+DK1yvu9L11CW+lCw5Lkkre0YmsVarMq2ZIHnMjjNWJYjB4lKuDfEf9N uB/kJttp0Uv7sjbL5x3Fq8vMu5G+3auWvk9vjnspirM= X-Virus-Scanned: amavisd-new at yadro.com Received: from mta-01.yadro.com ([127.0.0.1]) by localhost (mta-01.yadro.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JwWgguZxB6SH; Wed, 6 Jan 2021 19:04:06 +0300 (MSK) Received: from T-EXCH-03.corp.yadro.com (t-exch-03.corp.yadro.com [172.17.100.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mta-01.yadro.com (Postfix) with ESMTPS id 6096541268; Wed, 6 Jan 2021 19:04:06 +0300 (MSK) Received: from localhost (172.17.204.212) by T-EXCH-03.corp.yadro.com (172.17.100.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.32; Wed, 6 Jan 2021 19:04:06 +0300 Date: Wed, 6 Jan 2021 19:04:20 +0300 From: Roman Bolshakov To: Alexander Graf CC: , , Cameron Esfahani , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: Re: [PATCH v5 00/11] hvf: Implement Apple Silicon Support Message-ID: References: <20201211151300.85322-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20201211151300.85322-1-agraf@csgraf.de> X-Originating-IP: [172.17.204.212] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-03.corp.yadro.com (172.17.100.103) Received-SPF: pass client-ip=89.207.88.252; envelope-from=r.bolshakov@yadro.com; helo=mta-01.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 16:04:13 -0000 On Fri, Dec 11, 2020 at 04:12:49PM +0100, Alexander Graf wrote: > Now that Apple Silicon is widely available, people are obviously excited > to try and run virtualized workloads on them, such as Linux and Windows. > > This patch set implements a fully functional version to get the ball > going on that. With this applied, I can successfully run both Linux and > Windows as guests. I am not aware of any limitations specific to > Hypervisor.framework apart from: > > - Live migration / savevm > - gdbstub debugging (SP register) > > > Enjoy! > Hi Alex, For the ARM part: Tested-by: Roman Bolshakov Note, that it doesn't apply to current master. So I applied it over tagged v5.2.0. Are there any outstanding issues that blocking merge apart from the rebase? Thanks, Roman > Alex > > v1 -> v2: > > - New patch: hvf: Actually set SIG_IPI mask > - New patch: hvf: Introduce hvf vcpu struct > - New patch: hvf: arm: Mark CPU as dirty on reset > - Removed patch: hw/arm/virt: Disable highmem when on hypervisor.framework > - Removed patch: arm: Synchronize CPU on PSCI on > - Fix build on 32bit arm > - Merge vcpu kick function patch into ARM enablement > - Implement WFI handling (allows vCPUs to sleep) > - Synchronize system registers (fixes OVMF crashes and reboot) > - Don't always call cpu_synchronize_state() > - Use more fine grained iothread locking > - Populate aa64mmfr0 from hardware > - Make safe to ctrl-C entitlement application > > v2 -> v3: > > - Removed patch: hvf: Actually set SIG_IPI mask > - New patch: hvf: arm: Add support for GICv3 > - New patch: hvf: arm: Implement -cpu host > - Advance PC on SMC > - Use cp list interface for sysreg syncs > - Do not set current_cpu > - Fix sysreg isread mask > - Move sysreg handling to functions > - Remove WFI logic again > - Revert to global iothread locking > > v3 -> v4: > > - Removed patch: hvf: arm: Mark CPU as dirty on reset > - New patch: hvf: Simplify post reset/init/loadvm hooks > - Remove i386-softmmu target (meson.build for hvf target) > - Combine both if statements (PSCI) > - Use hv.h instead of Hypervisor.h for 10.15 compat > - Remove manual inclusion of Hypervisor.h in common .c files > - No longer include Hypervisor.h in arm hvf .c files > - Remove unused exe_full variable > - Reuse exe_name variable > > v4 -> v5: > > - Use g_free() on destroy > > Alexander Graf (10): > hvf: Add hypervisor entitlement to output binaries > hvf: x86: Remove unused definitions > hvf: Move common code out > hvf: Introduce hvf vcpu struct > arm: Set PSCI to 0.2 for HVF > hvf: Simplify post reset/init/loadvm hooks > hvf: Add Apple Silicon support > arm: Add Hypervisor.framework build target > hvf: arm: Add support for GICv3 > hvf: arm: Implement -cpu host > > Peter Collingbourne (1): > arm/hvf: Add a WFI handler > > MAINTAINERS | 14 +- > accel/hvf/entitlements.plist | 8 + > accel/hvf/hvf-all.c | 54 +++ > accel/hvf/hvf-cpus.c | 466 +++++++++++++++++++ > accel/hvf/meson.build | 7 + > accel/meson.build | 1 + > include/hw/core/cpu.h | 3 +- > include/sysemu/hvf.h | 2 + > include/sysemu/hvf_int.h | 66 +++ > meson.build | 40 +- > scripts/entitlement.sh | 13 + > target/arm/cpu.c | 13 +- > target/arm/cpu.h | 2 + > target/arm/hvf/hvf.c | 856 +++++++++++++++++++++++++++++++++++ > target/arm/hvf/meson.build | 3 + > target/arm/kvm_arm.h | 2 - > target/arm/meson.build | 2 + > target/i386/hvf/hvf-cpus.c | 131 ------ > target/i386/hvf/hvf-cpus.h | 25 - > target/i386/hvf/hvf-i386.h | 49 +- > target/i386/hvf/hvf.c | 462 +++---------------- > target/i386/hvf/meson.build | 1 - > target/i386/hvf/vmx.h | 24 +- > target/i386/hvf/x86.c | 28 +- > target/i386/hvf/x86_descr.c | 26 +- > target/i386/hvf/x86_emu.c | 62 +-- > target/i386/hvf/x86_mmu.c | 4 +- > target/i386/hvf/x86_task.c | 12 +- > target/i386/hvf/x86hvf.c | 224 ++++----- > target/i386/hvf/x86hvf.h | 2 - > 30 files changed, 1786 insertions(+), 816 deletions(-) > create mode 100644 accel/hvf/entitlements.plist > create mode 100644 accel/hvf/hvf-all.c > create mode 100644 accel/hvf/hvf-cpus.c > create mode 100644 accel/hvf/meson.build > create mode 100644 include/sysemu/hvf_int.h > create mode 100755 scripts/entitlement.sh > create mode 100644 target/arm/hvf/hvf.c > create mode 100644 target/arm/hvf/meson.build > delete mode 100644 target/i386/hvf/hvf-cpus.c > delete mode 100644 target/i386/hvf/hvf-cpus.h > > -- > 2.24.3 (Apple Git-128) > From MAILER-DAEMON Wed Jan 06 11:21:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxBYv-0007yv-Qk for mharc-qemu-arm@gnu.org; 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Wed, 06 Jan 2021 08:21:22 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, Maxim Uvarov Subject: [PATCHv2] arm-virt: add secure pl061 for reset/power down Date: Wed, 6 Jan 2021 19:21:18 +0300 Message-Id: <20210106162118.8869-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 16:21:27 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Use the same gpio 3 and gpio 4 which were used by non acpi variant of linux power control gpios. Signed-off-by: Maxim Uvarov --- v2: replace printf with qemu_log (Philippe Mathieu-Daudé) hw/arm/Kconfig | 1 + hw/arm/virt.c | 24 +++++++++++++ hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 84 +++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 1 + 6 files changed, 114 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..eff0345303 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, + [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, @@ -189,6 +190,7 @@ static const int a15irqmap[] = { [VIRT_GPIO] = 7, [VIRT_SECURE_UART] = 8, [VIRT_ACPI_GED] = 9, + [VIRT_SECURE_GPIO] = 10, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ @@ -864,6 +866,24 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } +static void create_gpio_secure(const VirtMachineState *vms) +{ + DeviceState *pl061_dev; + static DeviceState *gpio_pwr_dev; + + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; + int irq = vms->irqmap[VIRT_SECURE_GPIO]; + + pl061_dev = sysbus_create_simple("pl061", base, + qdev_get_gpio_in(vms->gic, irq)); + + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + qdev_connect_gpio_out(pl061_dev, 3, qdev_get_gpio_in(gpio_pwr_dev, 3)); + qdev_connect_gpio_out(pl061_dev, 4, qdev_get_gpio_in(gpio_pwr_dev, 4)); +} + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -1993,6 +2013,10 @@ static void machvirt_init(MachineState *machine) create_gpio(vms); } + if (vms->secure) { + create_gpio_secure(vms); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..f5868653b3 --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,84 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; + qemu_irq irq; +}; + +static void gpio_pwr_set_irq(void *opaque, int irq, int level) +{ + GPIO_PWR_State *s = (GPIO_PWR_State *)opaque; + + qemu_set_irq(s->irq, 1); + + if (level) { + return; + } + + switch (irq) { + case 3: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + break; + case 4: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "qemu; gpio_pwr: unknown interrupt %d lvl %d\n", + irq, level); + } +} + + +static void gpio_pwr_realize(DeviceState *dev, Error **errp) +{ + GPIO_PWR_State *s = GPIOPWR(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + qdev_init_gpio_in(dev, gpio_pwr_set_irq, 8); +} + +static void gpio_pwr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = gpio_pwr_realize; +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .class_init = gpio_pwr_class_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..77a4523cc7 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, -- 2.17.1 From MAILER-DAEMON Wed Jan 06 11:34:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxBlg-0004k2-9k for mharc-qemu-arm@gnu.org; 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Wed, 06 Jan 2021 08:34:29 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, Maxim Uvarov Subject: [PATCHv3] arm-virt: add secure pl061 for reset/power down Date: Wed, 6 Jan 2021 19:34:26 +0300 Message-Id: <20210106163426.9971-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 16:34:38 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Use the same gpio 3 and gpio 4 which were used by non acpi variant of linux power control gpios. Signed-off-by: Maxim Uvarov --- v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) hw/arm/Kconfig | 1 + hw/arm/virt.c | 24 ++++++++++++ hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 85 +++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 1 + 6 files changed, 115 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..eff0345303 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, + [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, @@ -189,6 +190,7 @@ static const int a15irqmap[] = { [VIRT_GPIO] = 7, [VIRT_SECURE_UART] = 8, [VIRT_ACPI_GED] = 9, + [VIRT_SECURE_GPIO] = 10, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ @@ -864,6 +866,24 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } +static void create_gpio_secure(const VirtMachineState *vms) +{ + DeviceState *pl061_dev; + static DeviceState *gpio_pwr_dev; + + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; + int irq = vms->irqmap[VIRT_SECURE_GPIO]; + + pl061_dev = sysbus_create_simple("pl061", base, + qdev_get_gpio_in(vms->gic, irq)); + + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + qdev_connect_gpio_out(pl061_dev, 3, qdev_get_gpio_in(gpio_pwr_dev, 3)); + qdev_connect_gpio_out(pl061_dev, 4, qdev_get_gpio_in(gpio_pwr_dev, 4)); +} + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -1993,6 +2013,10 @@ static void machvirt_init(MachineState *machine) create_gpio(vms); } + if (vms->secure) { + create_gpio_secure(vms); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..0d0680c9f7 --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,85 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; + qemu_irq irq; +}; + +static void gpio_pwr_set_irq(void *opaque, int irq, int level) +{ + GPIO_PWR_State *s = (GPIO_PWR_State *)opaque; + + qemu_set_irq(s->irq, 1); + + if (level) { + return; + } + + switch (irq) { + case 3: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + break; + case 4: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "qemu; gpio_pwr: unknown interrupt %d lvl %d\n", + irq, level); + } +} + + +static void gpio_pwr_realize(DeviceState *dev, Error **errp) +{ + GPIO_PWR_State *s = GPIOPWR(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + qdev_init_gpio_in(dev, gpio_pwr_set_irq, 8); +} + +static void gpio_pwr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = gpio_pwr_realize; +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .class_init = gpio_pwr_class_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..77a4523cc7 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, -- 2.17.1 From MAILER-DAEMON Wed Jan 06 11:36:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxBnu-0006bg-Pb for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 11:36:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxBnr-0006Zm-Gw for qemu-arm@nongnu.org; Wed, 06 Jan 2021 11:36:56 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:42600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxBnp-00019y-H9 for qemu-arm@nongnu.org; Wed, 06 Jan 2021 11:36:55 -0500 Received: by mail-pl1-x629.google.com with SMTP id s15so1791703plr.9 for ; Wed, 06 Jan 2021 08:36:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=ffb+X+NHgNBHv5+5luuXnUQ32C/ziSJZje4HKbF1kak=; b=nXfTIrqhq6U1SAxi6oQJEomojGkBpWceWsv6WwOhR6FakHmHAMj02yhs7IAwxXa/O5 3ZR0B0RyDGD2XT+O/J2YenLgW8qVCn03gxJ8L7DYob/VDIm7ySl8oxrZwCkaWQBv4nSX LswudI1/h039UEkFleqFTgWjzeWFaZKPc3QzUhV4HY7tjYXbzResNjVHICOknTx0BCtX Bq7r/Xm5b14NX1y42VTFO9qOOehcd//X4Wk6jFc8siSfQtyIcdIKrBTAHzXAVL0Pz3QX WvxtP6+GElwn5U/4QHP/zR6HYj/8onVetPZqrIKSUGkstswur5EC+eRlUKQVRpZ6s2Yk 5V9Q== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=maxim.uvarov@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 16:36:56 -0000 Please skip v2 and use v3. I had to check that one line change code compiles. qemu_log() requires include header for that function. Best regards, Maxim. On Wed, 6 Jan 2021 at 19:34, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). > Use the same gpio 3 and gpio 4 which were used by > non acpi variant of linux power control gpios. > > Signed-off-by: Maxim Uvarov > --- > v3: added missed include qemu/log.h for qemu_log(.. > v2: replace printf with qemu_log (Philippe Mathieu-Daud=C3=A9) > > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 24 ++++++++++++ > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 85 +++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > include/hw/arm/virt.h | 1 + > 6 files changed, 115 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 0a242e4c5d..13cc42dcc8 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -17,6 +17,7 @@ config ARM_VIRT > select PL011 # UART > select PL031 # RTC > select PL061 # GPIO > + select GPIO_PWR > select PLATFORM_BUS > select SMBIOS > select VIRTIO_MMIO > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 96985917d3..eff0345303 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] =3D { > [VIRT_RTC] =3D { 0x09010000, 0x00001000 }, > [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, > [VIRT_GPIO] =3D { 0x09030000, 0x00001000 }, > + [VIRT_SECURE_GPIO] =3D { 0x09031000, 0x00001000 }, > [VIRT_SECURE_UART] =3D { 0x09040000, 0x00001000 }, > [VIRT_SMMU] =3D { 0x09050000, 0x00020000 }, > [VIRT_PCDIMM_ACPI] =3D { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, > @@ -189,6 +190,7 @@ static const int a15irqmap[] =3D { > [VIRT_GPIO] =3D 7, > [VIRT_SECURE_UART] =3D 8, > [VIRT_ACPI_GED] =3D 9, > + [VIRT_SECURE_GPIO] =3D 10, > [VIRT_MMIO] =3D 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ > [VIRT_GIC_V2M] =3D 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ > [VIRT_SMMU] =3D 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ > @@ -864,6 +866,24 @@ static void create_gpio(const VirtMachineState *vms) > g_free(nodename); > } > > +static void create_gpio_secure(const VirtMachineState *vms) > +{ > + DeviceState *pl061_dev; > + static DeviceState *gpio_pwr_dev; > + > + hwaddr base =3D vms->memmap[VIRT_SECURE_GPIO].base; > + int irq =3D vms->irqmap[VIRT_SECURE_GPIO]; > + > + pl061_dev =3D sysbus_create_simple("pl061", base, > + qdev_get_gpio_in(vms->gic, irq)); > + > + gpio_pwr_dev =3D sysbus_create_simple("gpio-pwr", -1, > + qdev_get_gpio_in(pl061_dev, 3)); > + > + qdev_connect_gpio_out(pl061_dev, 3, qdev_get_gpio_in(gpio_pwr_dev, 3= )); > + qdev_connect_gpio_out(pl061_dev, 4, qdev_get_gpio_in(gpio_pwr_dev, 4= )); > +} > + > static void create_virtio_devices(const VirtMachineState *vms) > { > int i; > @@ -1993,6 +2013,10 @@ static void machvirt_init(MachineState *machine) > create_gpio(vms); > } > > + if (vms->secure) { > + create_gpio_secure(vms); > + } > + > /* connect powerdown request */ > vms->powerdown_notifier.notify =3D virt_powerdown_req; > qemu_register_powerdown_notifier(&vms->powerdown_notifier); > diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig > index b6fdaa2586..f0e7405f6e 100644 > --- a/hw/gpio/Kconfig > +++ b/hw/gpio/Kconfig > @@ -8,5 +8,8 @@ config PL061 > config GPIO_KEY > bool > > +config GPIO_PWR > + bool > + > config SIFIVE_GPIO > bool > diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c > new file mode 100644 > index 0000000000..0d0680c9f7 > --- /dev/null > +++ b/hw/gpio/gpio_pwr.c > @@ -0,0 +1,85 @@ > +/* > + * GPIO qemu power controller > + * > + * Copyright (c) 2020 Linaro Limited > + * > + * Author: Maxim Uvarov > + * > + * Virtual gpio driver which can be used on top of pl061 > + * to reboot and shutdown qemu virtual machine. One of use > + * case is gpio driver for secure world application (ARM > + * Trusted Firmware.). > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or la= ter. > + * See the COPYING file in the top-level directory. > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "hw/irq.h" > +#include "hw/sysbus.h" > +#include "sysemu/runstate.h" > + > +#define TYPE_GPIOPWR "gpio-pwr" > +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) > + > +struct GPIO_PWR_State { > + SysBusDevice parent_obj; > + qemu_irq irq; > +}; > + > +static void gpio_pwr_set_irq(void *opaque, int irq, int level) > +{ > + GPIO_PWR_State *s =3D (GPIO_PWR_State *)opaque; > + > + qemu_set_irq(s->irq, 1); > + > + if (level) { > + return; > + } > + > + switch (irq) { > + case 3: > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); > + break; > + case 4: > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "qemu; gpio_pwr: unknown interrupt %d lvl %d\n", > + irq, level); > + } > +} > + > + > +static void gpio_pwr_realize(DeviceState *dev, Error **errp) > +{ > + GPIO_PWR_State *s =3D GPIOPWR(dev); > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > + > + sysbus_init_irq(sbd, &s->irq); > + qdev_init_gpio_in(dev, gpio_pwr_set_irq, 8); > +} > + > +static void gpio_pwr_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + > + dc->realize =3D gpio_pwr_realize; > +} > + > +static const TypeInfo gpio_pwr_info =3D { > + .name =3D TYPE_GPIOPWR, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(GPIO_PWR_State), > + .class_init =3D gpio_pwr_class_init, > +}; > + > +static void gpio_pwr_register_types(void) > +{ > + type_register_static(&gpio_pwr_info); > +} > + > +type_init(gpio_pwr_register_types) > diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build > index 5c0a7d7b95..79568f00ce 100644 > --- a/hw/gpio/meson.build > +++ b/hw/gpio/meson.build > @@ -1,5 +1,6 @@ > softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) > softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) > +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) > softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) > softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) > softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index abf54fab49..77a4523cc7 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -81,6 +81,7 @@ enum { > VIRT_GPIO, > VIRT_SECURE_UART, > VIRT_SECURE_MEM, > + VIRT_SECURE_GPIO, > VIRT_PCDIMM_ACPI, > VIRT_ACPI_GED, > VIRT_NVDIMM_ACPI, > -- > 2.17.1 > From MAILER-DAEMON Wed Jan 06 11:47:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxByH-0003vg-MM for mharc-qemu-arm@gnu.org; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w189sm3693625wmg.31.2021.01.06.08.47.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Jan 2021 08:47:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCHv3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Jose.Marinho@arm.com, tf-a@lists.trustedfirmware.org References: <20210106163426.9971-1-maxim.uvarov@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7c639f40-e42a-44a0-3a1f-a0ddc8413e83@amsat.org> Date: Wed, 6 Jan 2021 17:47:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210106163426.9971-1-maxim.uvarov@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 16:47:39 -0000 On 1/6/21 5:34 PM, Maxim Uvarov wrote: > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). > Use the same gpio 3 and gpio 4 which were used by > non acpi variant of linux power control gpios. > > Signed-off-by: Maxim Uvarov > --- > v3: added missed include qemu/log.h for qemu_log(.. > v2: replace printf with qemu_log (Philippe Mathieu-Daudé) Thanks! Reviewed-by: Philippe Mathieu-Daudé > > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 24 ++++++++++++ > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 85 +++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > include/hw/arm/virt.h | 1 + > 6 files changed, 115 insertions(+) > create mode 100644 hw/gpio/gpio_pwr. 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charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 06, 2021 at 03:17:10PM +0800, Keqian Zhu wrote: > Correct sample code to avoid confusing readers. >=20 > Signed-off-by: Keqian Zhu > Cc: qemu-trivial@nongnu.org > Reviewed-by: Paolo Bonzini > Reviewed-by: Peter Xu > --- >=20 > v2: > - Add Cc and R-b. >=20 > --- > docs/devel/rcu.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Stefan Hajnoczi --xHFwDpU9dbj6ez1V Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAl/17Q0ACgkQnKSrs4Gr c8gZpgf/YNO4iFwAYjwd3y/gTXwdffsM/jadr2ElZQmD8kpXrxKzBjtCq7+zsDsU f0GmHKjd6WCJNg/0Fli7gExWwWcF6Yazol1pCK3XcilbEBSDyCgrWKsB0sOdHJMs 3zEBi6BQDE5uC61Vk7a2yezGZYl3w1NJ3D1Qn5JvlWx0yOWPt3pkz3MDNCP9GO0a A3diaDB355bcRfq0BiSKL5XjmTU/NdA7qHWIOHYdPgad5Vd7jLL2qbLfqysca1E6 StDse/NvG6/eIf0NupZX5qIkbpSFZUZ1yCM/ty7WJNv0V5Fhysyip+7agRGSd+C/ 5uWnnSR0kUSKZEcXVDDIBDrX5GNIkg== =i5Xn -----END PGP SIGNATURE----- --xHFwDpU9dbj6ez1V-- From MAILER-DAEMON Wed Jan 06 12:25:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxCYR-0000s6-IQ for mharc-qemu-arm@gnu.org; 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Wed, 06 Jan 2021 12:24:54 -0500 X-MC-Unique: Jtg0HOSwPiKuloQvfaQiEQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 014E0107ACE3; Wed, 6 Jan 2021 17:24:52 +0000 (UTC) Received: from localhost (unknown [10.40.208.13]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2F39619C66; Wed, 6 Jan 2021 17:24:31 +0000 (UTC) Date: Wed, 6 Jan 2021 18:24:30 +0100 From: Igor Mammedov To: Marian Posteuca Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, "Michael S. Tsirkin" , Paolo Bonzini , Sergio Lopez , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Dongjiu Geng , Xiao Guangrong , Peter Maydell , Shannon Zhao , Xiang Zheng , Ben Warren Subject: Re: [PATCH v3] acpi: Permit OEM ID and OEM table ID fields to be changed Message-ID: <20210106182430.6bf1823a@redhat.com> In-Reply-To: <20201230221302.26800-1-posteuca@mutex.one> References: <20201230221302.26800-1-posteuca@mutex.one> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jan 2021 17:25:02 -0000 On Thu, 31 Dec 2020 00:13:01 +0200 Marian Posteuca wrote: > Qemu's ACPI table generation sets the fields OEM ID and OEM table ID > to "BOCHS " and "BXPCxxxx" where "xxxx" is replaced by the ACPI > table name. >=20 > Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID > and OEM table ID for the strings "BOCHS" and "BXPC" and if they are > found, the game crashes(this may be an intentional detection > mechanism to prevent playing the game in a virtualized environment). >=20 > This patch allows you to override these default values. >=20 > The feature can be used in this manner: > qemu -machine oem-id=3DABCDEF,oem-table-id=3DGHIJKLMN >=20 > The oem-id string can be up to 6 bytes in size, and the > oem-table-id string can be up to 8 bytes in size. If the string are > smaller than their respective sizes they will be padded with space. > If either of these parameters is not set, the current default values > will be used for the one missing. >=20 > Note that the the OEM Table ID field will not be extended with the > name of the table, but will use either the default name or the user > provided one. >=20 > This does not affect the -acpitable option (for user-defined ACPI > tables), which has precedence over -machine option. overall looks good. Please add a test case for it, see tests/qtest/bios-tables-test.c for description how to do it an/or at "[PATCH v3 08/12] tests/acpi: allow updates for expected data files" and follow up patches on the list. Other than that, only my nitpicking below remains. >=20 > Signed-off-by: Marian Posteuca PS: here under --- should be changelog if it's not v1 > --- > hw/acpi/hmat.h | 3 +- > hw/i386/acpi-common.h | 3 +- > include/hw/acpi/acpi-defs.h | 2 +- > include/hw/acpi/aml-build.h | 8 ++-- > include/hw/acpi/ghes.h | 3 +- > include/hw/acpi/pci.h | 3 +- > include/hw/acpi/vmgenid.h | 2 +- > include/hw/arm/virt.h | 2 + > include/hw/i386/microvm.h | 4 ++ > include/hw/i386/pc.h | 5 ++- > include/hw/mem/nvdimm.h | 3 +- > hw/acpi/aml-build.c | 43 +++++++++++-------- > hw/acpi/ghes.c | 5 ++- > hw/acpi/hmat.c | 5 ++- > hw/acpi/nvdimm.c | 18 +++++--- > hw/acpi/pci.c | 5 ++- > hw/acpi/vmgenid.c | 4 +- > hw/arm/virt-acpi-build.c | 40 +++++++++++------ > hw/arm/virt.c | 57 ++++++++++++++++++++++++ > hw/i386/acpi-build.c | 86 +++++++++++++++++++++++++------------ > hw/i386/acpi-common.c | 5 ++- > hw/i386/acpi-microvm.c | 13 +++--- > hw/i386/microvm.c | 60 ++++++++++++++++++++++++++ > hw/i386/pc.c | 58 +++++++++++++++++++++++++ > 24 files changed, 344 insertions(+), 93 deletions(-) >=20 > diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h > index e9031cac01..b57f0e7e80 100644 > --- a/hw/acpi/hmat.h > +++ b/hw/acpi/hmat.h > @@ -37,6 +37,7 @@ > */ > #define HMAT_PROXIMITY_INITIATOR_VALID 0x1 > =20 > -void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_= state); > +void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_= state, > + const char *oem_id, const char *oem_table_id); > =20 > #endif > diff --git a/hw/i386/acpi-common.h b/hw/i386/acpi-common.h > index c30e461f18..b12cd73ea5 100644 > --- a/hw/i386/acpi-common.h > +++ b/hw/i386/acpi-common.h > @@ -9,6 +9,7 @@ > #define ACPI_BUILD_IOAPIC_ID 0x0 > =20 > void acpi_build_madt(GArray *table_data, BIOSLinker *linker, > - X86MachineState *x86ms, AcpiDeviceIf *adev); > + X86MachineState *x86ms, AcpiDeviceIf *adev, > + const char *oem_id, const char *oem_table_id); > =20 > #endif > diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h > index 38a42f409a..cf9f44299c 100644 > --- a/include/hw/acpi/acpi-defs.h > +++ b/include/hw/acpi/acpi-defs.h > @@ -41,7 +41,7 @@ enum { > }; > =20 > typedef struct AcpiRsdpData { > - uint8_t oem_id[6] QEMU_NONSTRING; /* OEM identification */ > + char *oem_id; /* OEM identification */ > uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ > =20 > unsigned *rsdt_tbl_offset; > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > index e727bea1bc..e22983bba1 100644 > --- a/include/hw/acpi/aml-build.h > +++ b/include/hw/acpi/aml-build.h > @@ -8,7 +8,7 @@ > #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 > =20 > #define ACPI_BUILD_APPNAME6 "BOCHS " > -#define ACPI_BUILD_APPNAME4 "BXPC" > +#define ACPI_BUILD_APPNAME8 "BXPC " > =20 > #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables" > #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp" > @@ -457,10 +457,12 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *ran= ge_set); > void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, > uint64_t len, int node, MemoryAffinityFlags flags= ); > =20 > -void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms= ); > +void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms= , > + const char *oem_id, const char *oem_table_id); > =20 > void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, > const char *oem_id, const char *oem_table_id); > =20 > -void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)= ; > +void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, > + const char *oem_id, const char *oem_table_id); > #endif > diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h > index 4ad025e09a..2ae8bc1ded 100644 > --- a/include/hw/acpi/ghes.h > +++ b/include/hw/acpi/ghes.h > @@ -67,7 +67,8 @@ typedef struct AcpiGhesState { > } AcpiGhesState; > =20 > void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)= ; > -void acpi_build_hest(GArray *table_data, BIOSLinker *linker); > +void acpi_build_hest(GArray *table_data, BIOSLinker *linker, > + const char *oem_id, const char *oem_table_id); > void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, > GArray *hardware_errors); > int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr= ); > diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h > index bf2a3ed0ba..e514f179d8 100644 > --- a/include/hw/acpi/pci.h > +++ b/include/hw/acpi/pci.h > @@ -33,5 +33,6 @@ typedef struct AcpiMcfgInfo { > uint32_t size; > } AcpiMcfgInfo; > =20 > -void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *in= fo); > +void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *in= fo, > + const char *oem_id, const char *oem_table_id); > #endif > diff --git a/include/hw/acpi/vmgenid.h b/include/hw/acpi/vmgenid.h > index cb4ad37fc5..dc8bb3433e 100644 > --- a/include/hw/acpi/vmgenid.h > +++ b/include/hw/acpi/vmgenid.h > @@ -31,7 +31,7 @@ static inline Object *find_vmgenid_dev(void) > } > =20 > void vmgenid_build_acpi(VmGenIdState *vms, GArray *table_data, GArray *g= uid, > - BIOSLinker *linker); > + BIOSLinker *linker, const char *oem_id); > void vmgenid_add_fw_cfg(VmGenIdState *vms, FWCfgState *s, GArray *guid); > =20 > #endif > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index abf54fab49..bba87ab6a3 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -164,6 +164,8 @@ struct VirtMachineState { > DeviceState *acpi_dev; > Notifier powerdown_notifier; > PCIBus *bus; > + char *oem_id; > + char *oem_table_id; > }; > =20 > #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) > diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h > index f25f837441..372b05774e 100644 > --- a/include/hw/i386/microvm.h > +++ b/include/hw/i386/microvm.h > @@ -76,6 +76,8 @@ > #define MICROVM_MACHINE_ISA_SERIAL "isa-serial" > #define MICROVM_MACHINE_OPTION_ROMS "x-option-roms" > #define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline" > +#define MICROVM_MACHINE_OEM_ID "oem-id" > +#define MICROVM_MACHINE_OEM_TABLE_ID "oem-table-id" > =20 > struct MicrovmMachineClass { > X86MachineClass parent; > @@ -104,6 +106,8 @@ struct MicrovmMachineState { > Notifier machine_done; > Notifier powerdown_req; > struct GPEXConfig gpex; > + char *oem_id; > + char *oem_table_id; > }; > =20 > #define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index 2aa8797c6e..5f93540a43 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -45,6 +45,8 @@ typedef struct PCMachineState { > bool pit_enabled; > bool hpet_enabled; > uint64_t max_fw_size; > + char *oem_id; > + char *oem_table_id; > =20 > /* NUMA information: */ > uint64_t numa_nodes; > @@ -62,7 +64,8 @@ typedef struct PCMachineState { > #define PC_MACHINE_SATA "sata" > #define PC_MACHINE_PIT "pit" > #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" > - > +#define PC_MACHINE_OEM_ID "oem-id" > +#define PC_MACHINE_OEM_TABLE_ID "oem-table-id" > /** > * PCMachineClass: > * > diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h > index c699842dd0..bcf62f825c 100644 > --- a/include/hw/mem/nvdimm.h > +++ b/include/hw/mem/nvdimm.h > @@ -154,7 +154,8 @@ void nvdimm_init_acpi_state(NVDIMMState *state, Memor= yRegion *io, > void nvdimm_build_srat(GArray *table_data); > void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, > BIOSLinker *linker, NVDIMMState *state, > - uint32_t ram_slots); > + uint32_t ram_slots, const char *oem_id, > + const char *oem_table_id); > void nvdimm_plug(NVDIMMState *state); > void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev); > #endif > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index f976aa667b..7e1fb0020f 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -1663,6 +1663,16 @@ Aml *aml_object_type(Aml *object) > return var; > } > =20 > +static void copy_pad_field(void *dst, const char *src, size_t dst_size) why not reuse strpadcpy() > +{ > + size_t copy_size; > + > + g_assert(src); > + copy_size =3D MIN(strlen(src), dst_size); > + memset(dst, 0x20, dst_size); > + memcpy(dst, src, copy_size); > +} > + > void > build_header(BIOSLinker *linker, GArray *table_data, > AcpiTableHeader *h, const char *sig, int len, uint8_t rev, > @@ -1670,25 +1680,19 @@ build_header(BIOSLinker *linker, GArray *table_da= ta, > { > unsigned tbl_offset =3D (char *)h - table_data->data; > unsigned checksum_offset =3D (char *)&h->checksum - table_data->data= ; > - memcpy(&h->signature, sig, 4); I wouldn't touch unrelated to oem_[table_]id fields in this patch. If you want to do that for consistency, it should be a separate patch > + > + copy_pad_field(&h->signature, sig, sizeof h->signature); > + > h->length =3D cpu_to_le32(len); > h->revision =3D rev; > =20 > - if (oem_id) { > - strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id); > - } else { > - memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6); > - } > - > - if (oem_table_id) { > - strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_tab= le_id)); > - } else { > - memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4); > - memcpy(h->oem_table_id + 4, sig, 4); > - } > + copy_pad_field(h->oem_id, oem_id, sizeof h->oem_id); > + copy_pad_field(h->oem_table_id, oem_table_id, sizeof h->oem_table_id= ); > =20 > h->oem_revision =3D cpu_to_le32(1); > - memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4); > + > + copy_pad_field(h->asl_compiler_id, oem_table_id, sizeof h->asl_compi= ler_id); > + > h->asl_compiler_revision =3D cpu_to_le32(1); > /* Checksum to be filled in by Guest linker */ > bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE, > @@ -1871,7 +1875,8 @@ void build_srat_memory(AcpiSratMemoryAffinity *numa= mem, uint64_t base, > * ACPI spec 5.2.17 System Locality Distance Information Table > * (Revision 2.0 or later) > */ > -void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms= ) > +void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms= , > + const char *oem_id, const char *oem_table_id) > { > int slit_start, i, j; > slit_start =3D table_data->len; > @@ -1892,7 +1897,7 @@ void build_slit(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms) > build_header(linker, table_data, > (void *)(table_data->data + slit_start), > "SLIT", > - table_data->len - slit_start, 1, NULL, NULL); > + table_data->len - slit_start, 1, oem_id, oem_table_id); > } > =20 > /* build rev1/rev3/rev5.1 FADT */ > @@ -2024,7 +2029,8 @@ build_hdr: > * table 7: TCG Hardware Interface Description Table Format for TPM 2.0 > * of TCG ACPI Specification, Family =E2=80=9C1.2=E2=80=9D and =E2=80=9C= 2.0=E2=80=9D, Version 1.2, Rev 8 > */ > -void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) > +void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, > + const char *oem_id, const char *oem_table_id) > { > uint8_t start_method_params[12] =3D {}; > unsigned log_addr_offset, tpm2_start; > @@ -2073,7 +2079,8 @@ void build_tpm2(GArray *table_data, BIOSLinker *lin= ker, GArray *tcpalog) > log_addr_offset, 8, > ACPI_BUILD_TPMLOG_FILE, 0); > build_header(linker, table_data, > - tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL= , NULL); > + tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, oem_= id, > + oem_table_id); > } > =20 > Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) > diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c > index f0ee9f51ca..a4dac6bf15 100644 > --- a/hw/acpi/ghes.c > +++ b/hw/acpi/ghes.c > @@ -359,7 +359,8 @@ static void build_ghes_v2(GArray *table_data, int sou= rce_id, BIOSLinker *linker) > } > =20 > /* Build Hardware Error Source Table */ > -void acpi_build_hest(GArray *table_data, BIOSLinker *linker) > +void acpi_build_hest(GArray *table_data, BIOSLinker *linker, > + const char *oem_id, const char *oem_table_id) > { > uint64_t hest_start =3D table_data->len; > =20 > @@ -372,7 +373,7 @@ void acpi_build_hest(GArray *table_data, BIOSLinker *= linker) > build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker); > =20 > build_header(linker, table_data, (void *)(table_data->data + hest_st= art), > - "HEST", table_data->len - hest_start, 1, NULL, NULL); > + "HEST", table_data->len - hest_start, 1, oem_id, oem_ta= ble_id); > } > =20 > void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s, > diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c > index 37806f7a06..edb3fd91b2 100644 > --- a/hw/acpi/hmat.c > +++ b/hw/acpi/hmat.c > @@ -253,7 +253,8 @@ static void hmat_build_table_structs(GArray *table_da= ta, NumaState *numa_state) > } > } > =20 > -void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_= state) > +void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_= state, > + const char *oem_id, const char *oem_table_id) > { > int hmat_start =3D table_data->len; > =20 > @@ -264,5 +265,5 @@ void build_hmat(GArray *table_data, BIOSLinker *linke= r, NumaState *numa_state) > =20 > build_header(linker, table_data, > (void *)(table_data->data + hmat_start), > - "HMAT", table_data->len - hmat_start, 2, NULL, NULL); > + "HMAT", table_data->len - hmat_start, 2, oem_id, oem_ta= ble_id); > } > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c > index aa95b0cbaf..e3d5fe1939 100644 > --- a/hw/acpi/nvdimm.c > +++ b/hw/acpi/nvdimm.c > @@ -402,7 +402,8 @@ void nvdimm_plug(NVDIMMState *state) > } > =20 > static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets, > - GArray *table_data, BIOSLinker *linker) > + GArray *table_data, BIOSLinker *linker, > + const char *oem_id, const char *oem_table_= id) > { > NvdimmFitBuffer *fit_buf =3D &state->fit_buf; > unsigned int header; > @@ -417,7 +418,8 @@ static void nvdimm_build_nfit(NVDIMMState *state, GAr= ray *table_offsets, > =20 > build_header(linker, table_data, > (void *)(table_data->data + header), "NFIT", > - sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, NULL, = NULL); > + sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, oem_id= , > + oem_table_id); > } > =20 > #define NVDIMM_DSM_MEMORY_SIZE 4096 > @@ -1278,7 +1280,7 @@ static void nvdimm_build_nvdimm_devices(Aml *root_d= ev, uint32_t ram_slots) > static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, > BIOSLinker *linker, > NVDIMMState *nvdimm_state, > - uint32_t ram_slots) > + uint32_t ram_slots, const char *oem_id) > { > Aml *ssdt, *sb_scope, *dev; > int mem_addr_offset, nvdimm_ssdt; > @@ -1331,7 +1333,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets= , GArray *table_data, > NVDIMM_DSM_MEM_FILE, 0); > build_header(linker, table_data, > (void *)(table_data->data + nvdimm_ssdt), > - "SSDT", table_data->len - nvdimm_ssdt, 1, NULL, "NVDIMM"); > + "SSDT", table_data->len - nvdimm_ssdt, 1, oem_id, "NVDI= MM"); > free_aml_allocator(); > } > =20 > @@ -1359,7 +1361,8 @@ void nvdimm_build_srat(GArray *table_data) > =20 > void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, > BIOSLinker *linker, NVDIMMState *state, > - uint32_t ram_slots) > + uint32_t ram_slots, const char *oem_id, > + const char *oem_table_id) > { > GSList *device_list; > =20 > @@ -1369,7 +1372,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArra= y *table_data, > } > =20 > nvdimm_build_ssdt(table_offsets, table_data, linker, state, > - ram_slots); > + ram_slots, oem_id); > =20 > device_list =3D nvdimm_get_device_list(); > /* no NVDIMM device is plugged. */ > @@ -1377,6 +1380,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArra= y *table_data, > return; > } > =20 > - nvdimm_build_nfit(state, table_offsets, table_data, linker); > + nvdimm_build_nfit(state, table_offsets, table_data, linker, > + oem_id, oem_table_id); > g_slist_free(device_list); > } > diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c > index 9510597a19..ec455c3b25 100644 > --- a/hw/acpi/pci.c > +++ b/hw/acpi/pci.c > @@ -28,7 +28,8 @@ > #include "hw/acpi/pci.h" > #include "hw/pci/pcie_host.h" > =20 > -void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *in= fo) > +void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *in= fo, > + const char *oem_id, const char *oem_table_id) > { > int mcfg_start =3D table_data->len; > =20 > @@ -56,6 +57,6 @@ void build_mcfg(GArray *table_data, BIOSLinker *linker,= AcpiMcfgInfo *info) > build_append_int_noprefix(table_data, 0, 4); > =20 > build_header(linker, table_data, (void *)(table_data->data + mcfg_st= art), > - "MCFG", table_data->len - mcfg_start, 1, NULL, NULL); > + "MCFG", table_data->len - mcfg_start, 1, oem_id, oem_ta= ble_id); > } > =20 > diff --git a/hw/acpi/vmgenid.c b/hw/acpi/vmgenid.c > index 2c8152d508..93efbcb22a 100644 > --- a/hw/acpi/vmgenid.c > +++ b/hw/acpi/vmgenid.c > @@ -23,7 +23,7 @@ > #include "sysemu/reset.h" > =20 > void vmgenid_build_acpi(VmGenIdState *vms, GArray *table_data, GArray *g= uid, > - BIOSLinker *linker) > + BIOSLinker *linker, const char *oem_id) > { > Aml *ssdt, *dev, *scope, *method, *addr, *if_ctx; > uint32_t vgia_offset; > @@ -117,7 +117,7 @@ void vmgenid_build_acpi(VmGenIdState *vms, GArray *ta= ble_data, GArray *guid, > =20 > build_header(linker, table_data, > (void *)(table_data->data + table_data->len - ssdt->buf->len), > - "SSDT", ssdt->buf->len, 1, NULL, "VMGENID"); > + "SSDT", ssdt->buf->len, 1, oem_id, "VMGENID"); > free_aml_allocator(); > } > =20 > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 711cf2069f..de95100a02 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -340,7 +340,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > iort->length =3D cpu_to_le32(iort_length); > =20 > build_header(linker, table_data, (void *)(table_data->data + iort_st= art), > - "IORT", table_data->len - iort_start, 0, NULL, NULL); > + "IORT", table_data->len - iort_start, 0, vms->oem_id, > + vms->oem_table_id); > } > =20 > static void > @@ -374,7 +375,8 @@ build_spcr(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > spcr->pci_vendor_id =3D 0xffff; /* PCI Vendor ID: not a PCI device = */ > =20 > build_header(linker, table_data, (void *)(table_data->data + spcr_st= art), > - "SPCR", table_data->len - spcr_start, 2, NULL, NULL); > + "SPCR", table_data->len - spcr_start, 2, vms->oem_id, > + vms->oem_table_id); > } > =20 > static void > @@ -426,7 +428,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > } > =20 > build_header(linker, table_data, (void *)(table_data->data + srat_st= art), > - "SRAT", table_data->len - srat_start, 3, NULL, NULL); > + "SRAT", table_data->len - srat_start, 3, vms->oem_id, > + vms->oem_table_id); > } > =20 > /* GTDT */ > @@ -461,7 +464,8 @@ build_gtdt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > =20 > build_header(linker, table_data, > (void *)(table_data->data + gtdt_start), "GTDT", > - table_data->len - gtdt_start, 2, NULL, NULL); > + table_data->len - gtdt_start, 2, vms->oem_id, > + vms->oem_table_id); > } > =20 > /* MADT */ > @@ -550,7 +554,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > =20 > build_header(linker, table_data, > (void *)(table_data->data + madt_start), "APIC", > - table_data->len - madt_start, 3, NULL, NULL); > + table_data->len - madt_start, 3, vms->oem_id, > + vms->oem_table_id); > } > =20 > /* FADT */ > @@ -580,7 +585,7 @@ static void build_fadt_rev5(GArray *table_data, BIOSL= inker *linker, > g_assert_not_reached(); > } > =20 > - build_fadt(table_data, linker, &fadt, NULL, NULL); > + build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id= ); > } > =20 > /* DSDT */ > @@ -644,7 +649,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) > g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); > build_header(linker, table_data, > (void *)(table_data->data + table_data->len - dsdt->buf->len), > - "DSDT", dsdt->buf->len, 2, NULL, NULL); > + "DSDT", dsdt->buf->len, 2, vms->oem_id, > + vms->oem_table_id); > free_aml_allocator(); > } > =20 > @@ -703,7 +709,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuild= Tables *tables) > .base =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, > .size =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, > }; > - build_mcfg(tables_blob, tables->linker, &mcfg); > + build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, > + vms->oem_table_id); > } > =20 > acpi_add_table(table_offsets, tables_blob); > @@ -712,7 +719,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuild= Tables *tables) > if (vms->ras) { > build_ghes_error_table(tables->hardware_errors, tables->linker); > acpi_add_table(table_offsets, tables_blob); > - acpi_build_hest(tables_blob, tables->linker); > + acpi_build_hest(tables_blob, tables->linker, vms->oem_id, > + vms->oem_table_id); > } > =20 > if (ms->numa_state->num_nodes > 0) { > @@ -720,13 +728,15 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBui= ldTables *tables) > build_srat(tables_blob, tables->linker, vms); > if (ms->numa_state->have_numa_distance) { > acpi_add_table(table_offsets, tables_blob); > - build_slit(tables_blob, tables->linker, ms); > + build_slit(tables_blob, tables->linker, ms, vms->oem_id, > + vms->oem_table_id); > } > } > =20 > if (ms->nvdimms_state->is_enabled) { > nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, > - ms->nvdimms_state, ms->ram_slots); > + ms->nvdimms_state, ms->ram_slots, vms->oem_id, > + vms->oem_table_id); > } > =20 > if (its_class_name() && !vmc->no_its) { > @@ -736,18 +746,20 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBui= ldTables *tables) > =20 > if (tpm_get_version(tpm_find()) =3D=3D TPM_VERSION_2_0) { > acpi_add_table(table_offsets, tables_blob); > - build_tpm2(tables_blob, tables->linker, tables->tcpalog); > + build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oe= m_id, > + vms->oem_table_id); > } > =20 > /* XSDT is pointed to by RSDP */ > xsdt =3D tables_blob->len; > - build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); > + build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, > + vms->oem_table_id); > =20 > /* RSDP is in FSEG memory, so allocate it separately */ > { > AcpiRsdpData rsdp_data =3D { > .revision =3D 2, > - .oem_id =3D ACPI_BUILD_APPNAME6, > + .oem_id =3D vms->oem_id, > .xsdt_tbl_offset =3D &xsdt, > .rsdt_tbl_offset =3D NULL, > }; > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 96985917d3..eb08a79aa3 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -2089,6 +2089,43 @@ static void virt_set_its(Object *obj, bool value, = Error **errp) > vms->its =3D value; > } > =20 > +static char *virt_get_oem_id(Object *obj, Error **errp) > +{ > + return g_strdup(VIRT_MACHINE(obj)->oem_id); ^^^^^^^^^^^^^^^^^^^^^^^^ such usage is not recommended, preferred way is: Foo *vm =3D VIRT_MACHINE(obj); then use vm->oem_id where it's needed. same applies to other similar places in this patch. > +} > + > +static void virt_set_oem_id(Object *obj, const char *value, Error **errp= ) > +{ > + size_t len =3D strlen(value); > + > + if (len > 6) { > + error_setg(errp, > + "User specified oem-id value is bigger than 6 bytes i= n size"); > + return; > + } > + > + strncpy(VIRT_MACHINE(obj)->oem_id, value, len + 1); > +} > + > +static char *virt_get_oem_table_id(Object *obj, Error **errp) > +{ > + return g_strdup(VIRT_MACHINE(obj)->oem_table_id); > +} > + > +static void virt_set_oem_table_id(Object *obj, const char *value, > + Error **errp) > +{ > + size_t len =3D strlen(value); > + > + if (len > 8) { > + error_setg(errp, > + "User specified oem-table-id value is bigger than 8 b= ytes in size"); > + return; > + } > + strncpy(VIRT_MACHINE(obj)->oem_table_id, value, len + 1); > +} > + > + > bool virt_is_acpi_enabled(VirtMachineState *vms) > { > if (vms->acpi =3D=3D ON_OFF_AUTO_OFF) { > @@ -2538,6 +2575,23 @@ static void virt_machine_class_init(ObjectClass *o= c, void *data) > "Set on/off to enable/disable = " > "ITS instantiation"); > =20 > + object_class_property_add_str(oc, "oem-id", > + virt_get_oem_id, > + virt_set_oem_id); > + object_class_property_set_description(oc, "oem-id", > + "Override the default value of= field OEMID " > + "in ACPI table header." > + "The string may be up to 6 byt= es in size"); > + > + > + object_class_property_add_str(oc, "oem-table-id", > + virt_get_oem_table_id, > + virt_set_oem_table_id); > + object_class_property_set_description(oc, "oem-table-id", > + "Override the default value of= field OEM Table ID " > + "in ACPI table header." > + "The string may be up to 8 byt= es in size"); > + > } > =20 > static void virt_instance_init(Object *obj) > @@ -2579,6 +2633,9 @@ static void virt_instance_init(Object *obj) > vms->irqmap =3D a15irqmap; > =20 > virt_flash_create(vms); > + > + vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); > + vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); > } > =20 > static const TypeInfo virt_machine_info =3D { > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index f18b71dea9..25898fdd37 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1636,12 +1636,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker= , > g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); > build_header(linker, table_data, > (void *)(table_data->data + table_data->len - dsdt->buf->len), > - "DSDT", dsdt->buf->len, 1, NULL, NULL); > + "DSDT", dsdt->buf->len, 1, pcms->oem_id, pcms->oem_tabl= e_id); > free_aml_allocator(); > } > =20 > static void > -build_hpet(GArray *table_data, BIOSLinker *linker) > +build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, > + const char *oem_table_id) > { > Acpi20Hpet *hpet; > =20 > @@ -1652,11 +1653,12 @@ build_hpet(GArray *table_data, BIOSLinker *linker= ) > hpet->timer_block_id =3D cpu_to_le32(0x8086a201); > hpet->addr.address =3D cpu_to_le64(HPET_BASE); > build_header(linker, table_data, > - (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); > + (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_tab= le_id); > } > =20 > static void > -build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) > +build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, > + const char *oem_id, const char *oem_table_id) > { > Acpi20Tcpa *tcpa =3D acpi_data_push(table_data, sizeof *tcpa); > unsigned log_addr_size =3D sizeof(tcpa->log_area_start_address); > @@ -1676,7 +1678,7 @@ build_tpm_tcpa(GArray *table_data, BIOSLinker *link= er, GArray *tcpalog) > ACPI_BUILD_TPMLOG_FILE, 0); > =20 > build_header(linker, table_data, > - (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); > + (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_tab= le_id); > } > =20 > #define HOLE_640K_START (640 * KiB) > @@ -1811,7 +1813,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, = MachineState *machine) > build_header(linker, table_data, > (void *)(table_data->data + srat_start), > "SRAT", > - table_data->len - srat_start, 1, NULL, NULL); > + table_data->len - srat_start, 1, pcms->oem_id, > + pcms->oem_table_id); > } > =20 > /* > @@ -1819,7 +1822,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, = MachineState *machine) > * (version Oct. 2014 or later) > */ > static void > -build_dmar_q35(GArray *table_data, BIOSLinker *linker) > +build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_i= d, > + const char *oem_table_id) > { > int dmar_start =3D table_data->len; > =20 > @@ -1869,7 +1873,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *link= er) > } > =20 > build_header(linker, table_data, (void *)(table_data->data + dmar_st= art), > - "DMAR", table_data->len - dmar_start, 1, NULL, NULL); > + "DMAR", table_data->len - dmar_start, 1, oem_id, oem_ta= ble_id); > } > =20 > /* > @@ -1880,7 +1884,8 @@ build_dmar_q35(GArray *table_data, BIOSLinker *link= er) > * Helpful to speedup Windows guests and ignored by others. > */ > static void > -build_waet(GArray *table_data, BIOSLinker *linker) > +build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, > + const char *oem_table_id) > { > int waet_start =3D table_data->len; > =20 > @@ -1896,7 +1901,7 @@ build_waet(GArray *table_data, BIOSLinker *linker) > build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good *= /, 4); > =20 > build_header(linker, table_data, (void *)(table_data->data + waet_st= art), > - "WAET", table_data->len - waet_start, 1, NULL, NULL); > + "WAET", table_data->len - waet_start, 1, oem_id, oem_ta= ble_id); > } > =20 > /* > @@ -1998,7 +2003,8 @@ ivrs_host_bridges(Object *obj, void *opaque) > } > =20 > static void > -build_amd_iommu(GArray *table_data, BIOSLinker *linker) > +build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_= id, > + const char *oem_table_id) > { > int ivhd_table_len =3D 24; > int iommu_start =3D table_data->len; > @@ -2093,7 +2099,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker) > } > =20 > build_header(linker, table_data, (void *)(table_data->data + iommu_s= tart), > - "IVRS", table_data->len - iommu_start, 1, NULL, NULL); > + "IVRS", table_data->len - iommu_start, 1, oem_id, > + oem_table_id); > } > =20 > typedef > @@ -2149,12 +2156,26 @@ void acpi_build(AcpiBuildTables *tables, MachineS= tate *machine) > GArray *tables_blob =3D tables->table_data; > AcpiSlicOem slic_oem =3D { .id =3D NULL, .table_id =3D NULL }; > Object *vmgenid_dev; > + char *oem_id; > + char *oem_table_id; > =20 > acpi_get_pm_info(machine, &pm); > acpi_get_misc_info(&misc); > acpi_get_pci_holes(&pci_hole, &pci_hole64); > acpi_get_slic_oem(&slic_oem); > =20 > + if (slic_oem.id) { > + oem_id =3D slic_oem.id; > + } else { > + oem_id =3D pcms->oem_id; > + } > + > + if (slic_oem.table_id) { > + oem_table_id =3D slic_oem.table_id; > + } else { > + oem_table_id =3D pcms->oem_table_id; > + } > + > table_offsets =3D g_array_new(false, true /* clear */, > sizeof(uint32_t)); > ACPI_BUILD_DPRINTF("init ACPI tables\n"); > @@ -2188,32 +2209,35 @@ void acpi_build(AcpiBuildTables *tables, MachineS= tate *machine) > pm.fadt.facs_tbl_offset =3D &facs; > pm.fadt.dsdt_tbl_offset =3D &dsdt; > pm.fadt.xdsdt_tbl_offset =3D &dsdt; > - build_fadt(tables_blob, tables->linker, &pm.fadt, > - slic_oem.id, slic_oem.table_id); > + build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_= id); > aml_len +=3D tables_blob->len - fadt; > =20 > acpi_add_table(table_offsets, tables_blob); > acpi_build_madt(tables_blob, tables->linker, x86ms, > - ACPI_DEVICE_IF(x86ms->acpi_dev)); > + ACPI_DEVICE_IF(x86ms->acpi_dev), pcms->oem_id, > + pcms->oem_table_id); > =20 > vmgenid_dev =3D find_vmgenid_dev(); > if (vmgenid_dev) { > acpi_add_table(table_offsets, tables_blob); > vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, > - tables->vmgenid, tables->linker); > + tables->vmgenid, tables->linker, pcms->oem_id= ); > } > =20 > if (misc.has_hpet) { > acpi_add_table(table_offsets, tables_blob); > - build_hpet(tables_blob, tables->linker); > + build_hpet(tables_blob, tables->linker, pcms->oem_id, > + pcms->oem_table_id); > } > if (misc.tpm_version !=3D TPM_VERSION_UNSPEC) { > if (misc.tpm_version =3D=3D TPM_VERSION_1_2) { > acpi_add_table(table_offsets, tables_blob); > - build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog)= ; > + build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, > + pcms->oem_id, pcms->oem_table_id); > } else { /* TPM_VERSION_2_0 */ > acpi_add_table(table_offsets, tables_blob); > - build_tpm2(tables_blob, tables->linker, tables->tcpalog); > + build_tpm2(tables_blob, tables->linker, tables->tcpalog, > + pcms->oem_id, pcms->oem_table_id); > } > } > if (pcms->numa_nodes) { > @@ -2221,34 +2245,40 @@ void acpi_build(AcpiBuildTables *tables, MachineS= tate *machine) > build_srat(tables_blob, tables->linker, machine); > if (machine->numa_state->have_numa_distance) { > acpi_add_table(table_offsets, tables_blob); > - build_slit(tables_blob, tables->linker, machine); > + build_slit(tables_blob, tables->linker, machine, pcms->oem_i= d, > + pcms->oem_table_id); > } > if (machine->numa_state->hmat_enabled) { > acpi_add_table(table_offsets, tables_blob); > - build_hmat(tables_blob, tables->linker, machine->numa_state)= ; > + build_hmat(tables_blob, tables->linker, machine->numa_state, > + pcms->oem_id, pcms->oem_table_id); > } > } > if (acpi_get_mcfg(&mcfg)) { > acpi_add_table(table_offsets, tables_blob); > - build_mcfg(tables_blob, tables->linker, &mcfg); > + build_mcfg(tables_blob, tables->linker, &mcfg, pcms->oem_id, > + pcms->oem_table_id); > } > if (x86_iommu_get_default()) { > IommuType IOMMUType =3D x86_iommu_get_type(); > if (IOMMUType =3D=3D TYPE_AMD) { > acpi_add_table(table_offsets, tables_blob); > - build_amd_iommu(tables_blob, tables->linker); > + build_amd_iommu(tables_blob, tables->linker, pcms->oem_id, > + pcms->oem_table_id); > } else if (IOMMUType =3D=3D TYPE_INTEL) { > acpi_add_table(table_offsets, tables_blob); > - build_dmar_q35(tables_blob, tables->linker); > + build_dmar_q35(tables_blob, tables->linker, pcms->oem_id, > + pcms->oem_table_id); > } > } > if (machine->nvdimms_state->is_enabled) { > nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, > - machine->nvdimms_state, machine->ram_slots); > + machine->nvdimms_state, machine->ram_slots, > + pcms->oem_id, pcms->oem_table_id); > } > =20 > acpi_add_table(table_offsets, tables_blob); > - build_waet(tables_blob, tables->linker); > + build_waet(tables_blob, tables->linker, pcms->oem_id, pcms->oem_tabl= e_id); > =20 > /* Add tables supplied by user (if any) */ > for (u =3D acpi_table_first(); u; u =3D acpi_table_next(u)) { > @@ -2261,13 +2291,13 @@ void acpi_build(AcpiBuildTables *tables, MachineS= tate *machine) > /* RSDT is pointed to by RSDP */ > rsdt =3D tables_blob->len; > build_rsdt(tables_blob, tables->linker, table_offsets, > - slic_oem.id, slic_oem.table_id); > + oem_id, oem_table_id); > =20 > /* RSDP is in FSEG memory, so allocate it separately */ > { > AcpiRsdpData rsdp_data =3D { > .revision =3D 0, > - .oem_id =3D ACPI_BUILD_APPNAME6, > + .oem_id =3D pcms->oem_id, > .xsdt_tbl_offset =3D NULL, > .rsdt_tbl_offset =3D &rsdt, > }; > diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c > index a6a30e8363..1f5947fcf9 100644 > --- a/hw/i386/acpi-common.c > +++ b/hw/i386/acpi-common.c > @@ -72,7 +72,8 @@ void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, > } > =20 > void acpi_build_madt(GArray *table_data, BIOSLinker *linker, > - X86MachineState *x86ms, AcpiDeviceIf *adev) > + X86MachineState *x86ms, AcpiDeviceIf *adev, > + const char *oem_id, const char *oem_table_id) > { > MachineClass *mc =3D MACHINE_GET_CLASS(x86ms); > const CPUArchIdList *apic_ids =3D mc->possible_cpu_arch_ids(MACHINE(= x86ms)); > @@ -157,6 +158,6 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *= linker, > =20 > build_header(linker, table_data, > (void *)(table_data->data + madt_start), "APIC", > - table_data->len - madt_start, 1, NULL, NULL); > + table_data->len - madt_start, 1, oem_id, oem_table_id); > } > =20 > diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c > index d34a301b84..54b3af478a 100644 > --- a/hw/i386/acpi-microvm.c > +++ b/hw/i386/acpi-microvm.c > @@ -149,7 +149,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *li= nker, > g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); > build_header(linker, table_data, > (void *)(table_data->data + table_data->len - dsdt->buf->len), > - "DSDT", dsdt->buf->len, 2, NULL, NULL); > + "DSDT", dsdt->buf->len, 2, mms->oem_id, mms->oem_table_= id); > free_aml_allocator(); > } > =20 > @@ -201,21 +201,24 @@ static void acpi_build_microvm(AcpiBuildTables *tab= les, > pmfadt.dsdt_tbl_offset =3D &dsdt; > pmfadt.xdsdt_tbl_offset =3D &dsdt; > acpi_add_table(table_offsets, tables_blob); > - build_fadt(tables_blob, tables->linker, &pmfadt, NULL, NULL); > + build_fadt(tables_blob, tables->linker, &pmfadt, mms->oem_id, > + mms->oem_table_id); > =20 > acpi_add_table(table_offsets, tables_blob); > acpi_build_madt(tables_blob, tables->linker, X86_MACHINE(machine), > - ACPI_DEVICE_IF(x86ms->acpi_dev)); > + ACPI_DEVICE_IF(x86ms->acpi_dev), mms->oem_id, > + mms->oem_table_id); > =20 > xsdt =3D tables_blob->len; > - build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); > + build_xsdt(tables_blob, tables->linker, table_offsets, mms->oem_id, > + mms->oem_table_id); > =20 > /* RSDP is in FSEG memory, so allocate it separately */ > { > AcpiRsdpData rsdp_data =3D { > /* ACPI 2.0: 5.2.4.3 RSDP Structure */ > .revision =3D 2, /* xsdt needs v2 */ > - .oem_id =3D ACPI_BUILD_APPNAME6, > + .oem_id =3D mms->oem_id, > .xsdt_tbl_offset =3D &xsdt, > .rsdt_tbl_offset =3D NULL, > }; > diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c > index edf2b0f061..904e3e65a1 100644 > --- a/hw/i386/microvm.c > +++ b/hw/i386/microvm.c > @@ -648,6 +648,45 @@ static void microvm_powerdown_req(Notifier *notifier= , void *data) > } > } > =20 > +static char *microvm_machine_get_oem_id(Object *obj, Error **errp) > +{ > + return g_strdup(MICROVM_MACHINE(obj)->oem_id); > +} > + > +static void microvm_machine_set_oem_id(Object *obj, const char *value, > + Error **errp) > +{ > + size_t len =3D strlen(value); > + > + if (len > 6) { > + error_setg(errp, > + "User specified "MICROVM_MACHINE_OEM_ID" value is bigger than = " > + "6 bytes in size"); > + return; > + } > + > + strncpy(MICROVM_MACHINE(obj)->oem_id, value, len + 1); > +} > + > +static char *microvm_machine_get_oem_table_id(Object *obj, Error **errp) > +{ > + return g_strdup(MICROVM_MACHINE(obj)->oem_table_id); > +} > + > +static void microvm_machine_set_oem_table_id(Object *obj, const char *va= lue, > + Error **errp) > +{ > + size_t len =3D strlen(value); > + > + if (len > 8) { > + error_setg(errp, > + "User specified "MICROVM_MACHINE_OEM_TABLE_ID" value is bigger= than " > + "8 bytes in size"); > + return; > + } > + strncpy(MICROVM_MACHINE(obj)->oem_table_id, value, len + 1); > +} > + > static void microvm_machine_initfn(Object *obj) > { > MicrovmMachineState *mms =3D MICROVM_MACHINE(obj); > @@ -669,6 +708,9 @@ static void microvm_machine_initfn(Object *obj) > qemu_add_machine_init_done_notifier(&mms->machine_done); > mms->powerdown_req.notify =3D microvm_powerdown_req; > qemu_register_powerdown_notifier(&mms->powerdown_req); > + > + mms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); > + mms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); > } > =20 > static void microvm_class_init(ObjectClass *oc, void *data) > @@ -757,6 +799,24 @@ static void microvm_class_init(ObjectClass *oc, void= *data) > MICROVM_MACHINE_AUTO_KERNEL_CMDLINE, > "Set off to disable adding virtio-mmio devices to the kernel cmd= line"); > =20 > + object_class_property_add_str(oc, MICROVM_MACHINE_OEM_ID, > + microvm_machine_get_oem_id, > + microvm_machine_set_oem_id); > + object_class_property_set_description(oc, MICROVM_MACHINE_OEM_ID, > + "Override the default value of= field OEMID " > + "in ACPI table header." > + "The string may be up to 6 byt= es in size"); > + > + > + object_class_property_add_str(oc, MICROVM_MACHINE_OEM_TABLE_ID, > + microvm_machine_get_oem_table_id, > + microvm_machine_set_oem_table_id); > + object_class_property_set_description(oc, MICROVM_MACHINE_OEM_TABLE_= ID, > + "Override the default value of= field OEM Table ID " > + "in ACPI table header." > + "The string may be up to 8 byt= es in size"); > + > + > machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); > } > =20 > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 5458f61d10..9c50abde68 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -1611,6 +1611,44 @@ static void pc_machine_set_max_fw_size(Object *obj= , Visitor *v, > pcms->max_fw_size =3D value; > } > =20 > +static char *pc_machine_get_oem_id(Object *obj, Error **errp) > +{ > + return g_strdup(PC_MACHINE(obj)->oem_id); > +} > + > +static void pc_machine_set_oem_id(Object *obj, const char *value, Error = **errp) > +{ > + size_t len =3D strlen(value); > + > + if (len > 6) { > + error_setg(errp, > + "User specified "PC_MACHINE_OEM_ID" value is bigger than " > + "6 bytes in size"); > + return; > + } > + > + strncpy(PC_MACHINE(obj)->oem_id, value, len + 1); > +} > + > +static char *pc_machine_get_oem_table_id(Object *obj, Error **errp) > +{ > + return g_strdup(PC_MACHINE(obj)->oem_table_id); > +} > + > +static void pc_machine_set_oem_table_id(Object *obj, const char *value, > + Error **errp) > +{ > + size_t len =3D strlen(value); > + > + if (len > 8) { > + error_setg(errp, > + "User specified "PC_MACHINE_OEM_TABLE_ID" value is bigger than= " > + "8 bytes in size"); > + return; > + } > + strncpy(PC_MACHINE(obj)->oem_table_id, value, len + 1); > +} > + > static void pc_machine_initfn(Object *obj) > { > PCMachineState *pcms =3D PC_MACHINE(obj); > @@ -1623,6 +1661,8 @@ static void pc_machine_initfn(Object *obj) > pcms->max_ram_below_4g =3D 0; /* use default */ > /* acpi build is enabled by default if machine supports it */ > pcms->acpi_build_enabled =3D PC_MACHINE_GET_CLASS(pcms)->has_acpi_bu= ild; > + pcms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); > + pcms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); > pcms->smbus_enabled =3D true; > pcms->sata_enabled =3D true; > pcms->pit_enabled =3D true; > @@ -1759,6 +1799,24 @@ static void pc_machine_class_init(ObjectClass *oc,= void *data) > NULL, NULL); > object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, > "Maximum combined firmware size"); > + > + object_class_property_add_str(oc, PC_MACHINE_OEM_ID, > + pc_machine_get_oem_id, > + pc_machine_set_oem_id); > + object_class_property_set_description(oc, PC_MACHINE_OEM_ID, > + "Override the default value of= field OEMID " > + "in ACPI table header." > + "The string may be up to 6 byt= es in size"); > + > + > + object_class_property_add_str(oc, PC_MACHINE_OEM_TABLE_ID, > + pc_machine_get_oem_table_id, > + pc_machine_set_oem_table_id); > + object_class_property_set_description(oc, PC_MACHINE_OEM_TABLE_ID, > + "Override the default value of= field OEM Table ID " > + "in ACPI table header." > + "The string may be up to 8 byt= es in size"); > + > } > =20 > static const TypeInfo pc_machine_info =3D { From MAILER-DAEMON Wed Jan 06 20:13:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxJrr-0000cX-7s for mharc-qemu-arm@gnu.org; Wed, 06 Jan 2021 20:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxJrq-0000b2-3K for qemu-arm@nongnu.org; Wed, 06 Jan 2021 20:13:34 -0500 Received: from mail-il1-x133.google.com ([2607:f8b0:4864:20::133]:37992) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxJro-0002hy-8S for qemu-arm@nongnu.org; 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Wed, 06 Jan 2021 17:13:30 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Haibo Xu Date: Thu, 7 Jan 2021 09:13:19 +0800 Message-ID: Subject: Re: MTE support inside QEMU? To: Yu Nexus Cc: qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::133; envelope-from=haibo.xu@linaro.org; helo=mail-il1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 01:13:34 -0000 On Wed, 6 Jan 2021 at 20:13, Yu Nexus wrote: > > Is there full support for ARMv8.5 Memory Tagging Extensions (MTE) inside QEMU? > So is this MTE example code supposed to work inside QEMU? https://www.kernel.org/doc/html/latest/arm64/memory-tagging-extension.html As far as I know MTE is supported with QEMU TCG mode, and the KVM mode support is still WIP. I have verified the MTE example code with Qemu KVM mode(patch still WIP), and it worked well. Regards, Haibo From MAILER-DAEMON Thu Jan 07 07:02:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxU01-0004Sl-BU for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 07:02:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxTzz-0004SE-9J for qemu-arm@nongnu.org; Thu, 07 Jan 2021 07:02:39 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]:46869) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxTzx-0003sf-J3 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 07:02:38 -0500 Received: by mail-ej1-x632.google.com with SMTP id t16so9232477ejf.13 for ; Thu, 07 Jan 2021 04:02:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B/JxDxDkvmOFXNJNBLofXY5rmgmrH3nOwnc03kHQz7I=; b=icUfLfvA1tgW3CEvXdy6hOZssccXsrya/F4RnQvFk82MvQlseOleQzmIugP65taCaF J8mk6wuWCGljfqECbQ8OAYvbUrW4Gi7kqRhhAH6rBRMnslEG2PHPssWiQLINZriZczPy 4BGeQVWn8J+e0BIXCz51c6OMIMTnUqV1+lBOZhqd3glsVxx1VwY6+uTinByk2IbqfJHi NLC2x2WsIWfhrIy7zw1dg+6peHlEgmCBIHONN+1OFHh1CcAMdj1Hge25i5T16yQivoLg SPVkbmWNh4eg/WxCKGJyHUFg9C8h6d8/mMdU+VeVm3zxrtgx9Has4jIp8mCw92OyxunM SHQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B/JxDxDkvmOFXNJNBLofXY5rmgmrH3nOwnc03kHQz7I=; b=N/1A+nKz679WxW4qg8alisPOR8ZdoR4tMSU/NkMR0T6jpkbJy0VjQf1nHxUQ4a5s+x w8rTU4E1rOfqL0YKTcnt4JYVt8nYe2tuSJJmt7DpDim+bJ77B3pqRTFM4RxvYS3qajCs 0cZy/psM18ul/8GZp6/70AAGQjduWEEw631obe7eaGMOUpRtrVh9tuuegCCa/XvOF6Ap +D08WqixfmMMrwMyIOBlMz9QfJBG2C5GtQITiBkWfnDvtxYrJ5kG7kd1cKH8dfBHAeG5 k24tWUxjNTXB7zy7mPWja/Ek9zicH+zVB1oMeJVBGwnQ7+hAOTHcIGS+ghQ7aPiorQUH N+gQ== X-Gm-Message-State: AOAM533WTQ9Y/MATnQm2za0uGSSCOYTgUWYm2Nnb/WB8ckXQb+teSz88 rUXd34+e4QJVbk6UeIRbg8Ep80+lKcOG9Yk1LtTCtA== X-Google-Smtp-Source: ABdhPJwUPbUAckckt54jVv8ArIqzVD2yTXUfcnAFZ9dT0Kq0zAtNqcHlYW/+pBYkaM5PysD+6B3OtbkLDlHGeV0DzOA= X-Received: by 2002:a17:906:6b88:: with SMTP id l8mr6120369ejr.482.1610020955980; Thu, 07 Jan 2021 04:02:35 -0800 (PST) MIME-Version: 1.0 References: <20201214222154.3480243-1-edgar.iglesias@gmail.com> In-Reply-To: <20201214222154.3480243-1-edgar.iglesias@gmail.com> From: Peter Maydell Date: Thu, 7 Jan 2021 12:02:24 +0000 Message-ID: Subject: Re: [PATCH v1 0/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs To: "Edgar E. Iglesias" Cc: QEMU Developers , qemu-arm , Richard Henderson , KONRAD Frederic , Alistair Francis , Luc Michel , Damien Hedde , Francisco Iglesias , Francisco Eduardo Iglesias , Stefano Stabellini , Sai Pavan Boddu , Edgar Iglesias Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 12:02:39 -0000 On Mon, 14 Dec 2020 at 22:21, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Hi, > > Found this while debugging an issue with lockups during boot of > Linux on Xen. > > In the particular setup, I'm running without EL3 firmware so group0 > interrupts are disabled on the physical interface and enabled on the > virtual interface. > > Looks like we're checking the wrong CPU_CTLR reg for vCPUs. This fixes > the problem on my side. Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Thu Jan 07 07:17:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxUE9-0001WN-Ls for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 07:17:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxUE8-0001WF-4V for qemu-arm@nongnu.org; Thu, 07 Jan 2021 07:17:16 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:40538) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxUE3-0002CL-VO for qemu-arm@nongnu.org; Thu, 07 Jan 2021 07:17:15 -0500 Received: by mail-ej1-x62d.google.com with SMTP id x16so9375171ejj.7 for ; Thu, 07 Jan 2021 04:17:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QNNwoy5PFKpKN9OXomCECGA2LaR6TvbCOQym7aWFzH0=; b=cn3kMB0JMRs6yRYvCyP3yS/0KwDIvNraZqD+5Dz7ErU97Fya0TmGWvF2q/1fsQRpgl h4ud0VX2wDogN9F9X1Z8R0nhtzcr/y7KVMbanOSsAkdk6RrsCFMb4xiZYRdglTGsvSQc B0WJZdKwcu30zuhoRj3rT6vv5+3vSn/rDiUIyrKvVZOkGkKjPfPGs3STQt2bWmY1db36 otPqDYqkHVxUEKmjaGyISuoXTp5fQJDjQpFlLCcYex+nnojA8vwu+3m/srY/5JJ+PJHE qkzqzp4+im5EjbErmPxkQF4VuDwRsx2IoIdX8vzCj7D/q5b4rYX/cTapf/BBcZa/mC4K ENTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QNNwoy5PFKpKN9OXomCECGA2LaR6TvbCOQym7aWFzH0=; b=bJN4Xq599W2gPicxe/lO+rjjVMExiAhcTbGlPtKLfS6qhxx1/iyczlAAsgk08p64V8 k0O6OBRZ8y6B1pXnMcJZG1S37SByTpskfsuSIWAXVN+QD0dyMHq+job1IZEUbavEkOUV cc46IyYs9kBAwJNWRT0rlefaKFAD2+ZW5AK/vIxPh8PYy262wQm76j/Ll+Ec9c/YCKoS JG/pBR4KxLoY8KsnDPNQLT3vbX54F8qCEODXAvnieipajn43dMf5QdejCpWjcE4OehGG 5DqAAIxsOjltzGFCkL31kKh1x0D9vbDrHDj7Xl4JpX29riuR29fT/PMwOcl+gwwqpX6w s6Mw== X-Gm-Message-State: AOAM5330EgFadEWPjSNinxSt7LKRvjZ5wMVRvt1hnMjFdJ6hGKM5HGOK N30kdSOXoR26XsTOfV07CieiLAZzL5vOCkIudwcTQA== X-Google-Smtp-Source: ABdhPJwUuot25qnzyLKqFmKYOtAadxH91AVBBxkO33P2zcf9wJqwwvFXFZqfrfqkook/NyK7yT/cFT+TGdtjaYMM+Js= X-Received: by 2002:a17:906:e94c:: with SMTP id jw12mr6372811ejb.56.1610021829946; Thu, 07 Jan 2021 04:17:09 -0800 (PST) MIME-Version: 1.0 References: <20201215174815.51520-1-drjones@redhat.com> <20201216064353.2n4evhicybkkuf7z@kamzik.brq.redhat.com> In-Reply-To: <20201216064353.2n4evhicybkkuf7z@kamzik.brq.redhat.com> From: Peter Maydell Date: Thu, 7 Jan 2021 12:16:58 +0000 Message-ID: Subject: Re: [PATCH] hw/arm/virt: Remove virt machine state 'smp_cpus' To: Andrew Jones Cc: David Edmondson , QEMU Developers , qemu-arm , Ying Fang , salil.mehta@huawei.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 12:17:16 -0000 On Wed, 16 Dec 2020 at 06:44, Andrew Jones wrote: > > On Tue, Dec 15, 2020 at 06:20:48PM +0000, David Edmondson wrote: > > On Tuesday, 2020-12-15 at 18:48:15 +01, Andrew Jones wrote: > > > > > virt machine's 'smp_cpus' and machine->smp.cpus must always have the > > > same value. And, anywhere we have virt machine state we have machine > > > state. So let's remove the redundancy. Also, to make it easier to see > > > that machine->smp is the true source for "smp_cpus" and "max_cpus", > > > avoid passing them in function parameters, preferring instead to get > > > them from the state. > > > static void fdt_add_cpu_nodes(const VirtMachineState *vms) > > > { > > > - int cpu; > > > - int addr_cells = 1; > > > const MachineState *ms = MACHINE(vms); > > > + int smp_cpus = ms->smp.cpus, cpu; > > > > Is it house-style to have initialised and un-initialised local variables > > declared on the same line? > > > > checkpatch.pl doesn't complain and a grep of qemu shows hundreds of other > examples. That said, I only see one other example in hw/arm/virt.c, so if > we'd rather avoid it, I'll repost. I think this is one of those things where the style guide doesn't say anything, so it comes down to individual developer preference. Personally I find declaring an uninitialized local on the same line and after an initialized local is a bit confusing to read so I've tweaked the patch, but it's not a big deal either way. Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Thu Jan 07 10:42:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXQY-0003Jm-28 for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 10:42:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXQW-0003IU-SP for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:42:16 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:39350) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXQV-00084T-0z for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:42:16 -0500 Received: by mail-ej1-x62b.google.com with SMTP id n26so10287670eju.6 for ; Thu, 07 Jan 2021 07:42:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Q1+BB7EAgsUKpRCVdjDUmj5z8BxSmmmAA8Vqd9CXW88=; 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Thu, 07 Jan 2021 07:42:13 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-3-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-3-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 15:42:02 +0000 Message-ID: Subject: Re: [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 15:42:17 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Use this to signal when memory access alignment is required. > This value comes from the CCR register for M-profile, and > from the SCTLR register for A-profile. > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.h | 20 +++++++++++--------- > target/arm/translate.h | 2 ++ > target/arm/helper.c | 19 +++++++++++++++++-- > target/arm/translate.c | 7 +++---- > 4 files changed, 33 insertions(+), 15 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e5514c8286..e074055a94 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3220,15 +3220,15 @@ typedef ARMCPU ArchCPU; > * We put flags which are shared between 32 and 64 bit mode at the top > * of the word, and flags which apply to only one mode at the bottom. > * > - * 31 20 18 14 9 0 > - * +--------------+-----+-----+----------+--------------+ > - * | | | TBFLAG_A32 | | > - * | | +-----+----------+ TBFLAG_AM32 | > - * | TBFLAG_ANY | |TBFLAG_M32| | > - * | +-----------+----------+--------------| > - * | | TBFLAG_A64 | > - * +--------------+-------------------------------------+ > - * 31 20 0 > + * 31 19 18 14 9 0 > + * +--------------+---+-----+----------+--------------+ > + * | | | TBFLAG_A32 | | > + * | | +-----+----------+ TBFLAG_AM32 | > + * | TBFLAG_ANY | |TBFLAG_M32| | > + * | +---------+----------+--------------| > + * | | TBFLAG_A64 | > + * +--------------+-----------------------------------+ > + * 31 19 0 > * > * Unless otherwise noted, these bits are cached in env->hflags. > */ > @@ -3241,6 +3241,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 24, 4) > FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) > /* For A-profile only, target EL for debug exceptions. */ > FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) > +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ > +FIELD(TBFLAG_ANY, ALIGN_MEM, 19, 1) This is trying to use the same bit as TBFLAG_A64 MTE0_ACTIVE... We might have to finally start in on using bits in cs_base. thanks -- PMM From MAILER-DAEMON Thu Jan 07 10:51:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXZd-0008GP-Hk for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 10:51:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXZb-0008EC-JI for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:51:39 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:36000) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXZZ-00035s-R7 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:51:39 -0500 Received: by mail-ej1-x629.google.com with SMTP id lt17so10371325ejb.3 for ; Thu, 07 Jan 2021 07:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=I/vDupz7Rxchh5Jd54TDGf5kcRCoouR9LesX9aPCKP4=; b=ZjRc8GELmEbuwFVc7lK7tsx6sPOdGHoKNiMrT73sb+rMY5yqwoMYqC/8h17/gXkJsY 5Ss8+qV9CkvXEYVM21d1nqowyyg4QOu5ya3taRudPbECehBifmndJD3u0It+KlzpbFHj yBObo9LwO9ZgxQ6scvi1tgKDLXdnn/k/E6TpNJF9OZcgN9rRIXTL4qDixZ1N/2rO6ufT 9vitrgUNc89A/5bVNhpkr989OQjCykr4t7zo54279PyRK1rWWPuSnUQLx9rBRNzwBtnq P4fMYUZrDRomUTAZBCDX9f1yCqtsMYGQFO1mxQ3l0jfgf+7NtkmRjt04k+PI8gTr687s shxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=I/vDupz7Rxchh5Jd54TDGf5kcRCoouR9LesX9aPCKP4=; b=HZt3nz5W6bEughmXV5DNKOQ7EqtSKMhVTGw2ZGC4Up6N1Y4sr/dJEkAaHDJngG1FXr mWUofVaTBggYM5Smlf+1QCSgOYNA9E1HEmgGCTzksuwKXDn3Te+uHE37DN1447GN+x9L oVQh2JveIkKvRpKhCd9QUK85BTKUXrVI4L4PPQZHXSRc/XJXc9E1NDqU9zqNmNQghD9h UETzSDG7dZyEjGbBtNXPV15f2GHD7DfBxQHtA1rWuIYfLDhaExuxvMRkV8+/0xzQ0IP5 BRNKiL/dIiC5h7HU98aOhzxmoxdFYhyfmn6A6pTRx5R3bj1i/rC0OzTr+qWZDhm7QpWs ETPA== X-Gm-Message-State: AOAM530m/bN/HJIXEWbqOSyIWnaGHwogjH03FgFjnZwldTYhnlMxY+mv sryI9/j/bLTykQNXrD9rMbMvkPCIjrn6kawCCYbF2g== X-Google-Smtp-Source: ABdhPJyO5OGvxGpPvw2wU2Wpvr44sZKL3rm7EkXoipEpaPSdzKD1aoan7m6GwpssqlzIHqBwl1tHQmNOtmr9I5SjViA= X-Received: by 2002:a17:906:6b88:: with SMTP id l8mr6821597ejr.482.1610034696057; Thu, 07 Jan 2021 07:51:36 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-4-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-4-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 15:51:24 +0000 Message-ID: Subject: Re: [PATCH v2 03/24] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 15:51:39 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Create a finalize_memop function that computes alignment and > endianness and returns the final MemOp for the operation. > > Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special > handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32 > so that s->be_data is not added by the callers. > > Signed-off-by: Richard Henderson > --- > target/arm/translate.h | 24 ++++++++ > target/arm/translate.c | 100 +++++++++++++++++--------------- > target/arm/translate-neon.c.inc | 9 +-- > 3 files changed, 79 insertions(+), 54 deletions(-) > > diff --git a/target/arm/translate.h b/target/arm/translate.h > index fb66b4d8a0..22a4b15d45 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -448,4 +448,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) > return statusptr; > } > > +/** > + * finalize_memop: > + * @s: DisasContext > + * @opc: size+sign+align of the memory operation > + * > + * Build the complete MemOp for a memory operation, including alignment > + * and endianness. > + * > + * If (op & MO_AMASK) then the operation already contains the required > + * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally > + * unaligned operation, e.g. for AccType_NORMAL. > + * > + * In the later case, there are configuration bits that require alignment, "latter case". > + * and this is applied here. Note that there is no way to indicate that > + * no alignment should ever be enforced; this must be handled manually. > + */ > +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) > +{ > + if (s->align_mem && !(opc & MO_AMASK)) { > + opc |= MO_ALIGN; > + } > + return opc | s->be_data; > +} > + > +#define DO_GEN_LD(SUFF, OPC) \ > + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ > + TCGv_i32 a32, int index) \ > + { \ > + gen_aa32_ld_i32(s, val, a32, index, OPC); \ > } > +#define DO_GEN_ST(SUFF, OPC) \ > + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ > + TCGv_i32 a32, int index) \ > + { \ > + gen_aa32_st_i32(s, val, a32, index, OPC); \ > + } Since these generated functions no longer do anything extra that the gen_aa32_{ld,st}_i32() that the call don't do, we could reasonably have a follow-on patch that makes all the callsites directly call those functions and remove the extra layer of indirection, I think. The main reason we had them before was so that we had somewhere to add the handling of s->be_data. For this patch, other than the typo above, Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 10:56:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXeg-0003yt-2A for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 10:56:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXee-0003wE-4T for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:56:52 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:42707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXeb-00053q-CG for qemu-arm@nongnu.org; Thu, 07 Jan 2021 10:56:51 -0500 Received: by mail-ej1-x62f.google.com with SMTP id d17so10316183ejy.9 for ; Thu, 07 Jan 2021 07:56:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tE6F8Y+uAOLiNnHj5XpVgy8AxDEDwhsX50dwch7V89E=; b=MyX55ryjtYkHwS9QKjoSp9NX6q/K6XFWgY8Lp3VIAqAmRqsgh+33URQiH9sU8RrMrZ ODAsPrSHfCn8IMrLalwt+K8VJ+NCYPjcrsa+RwKY8MhBGLmhMwCSjhC7NMtHtluff7tK za7rVhtYyaqUZWy4pamSkvb3QDETK+PUce2w1JpAAIq3fIHFMflOALe2Cifj8ldKLUCv awJGWHSBar4hA+oUZRDVTZ4fDe/h0HTx6K9P3KCWDKzsAiO6TO2f2oSheEvH2CejRP44 VVRamYt7gMtkHi3skLbJYGARymBv5UDxnqeLIxIl721yWpxk/11NgFo5lqlGU46ChaD8 mJVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tE6F8Y+uAOLiNnHj5XpVgy8AxDEDwhsX50dwch7V89E=; b=jWiYR5glmL+ImNBJ/3CGIqJ61TX8Ao7SG8z2N8PZwk5YSogfva8RHKKMxdzPxg10hs n8YsVonyT+WW4BiLBm9BuVumpxm0a+RpqLM0ep155B6g4sA/vxYdA+EjetdJXpyOY1PK rhBDcgDgQBl3Y2r9UwIolO/aJ+Qq94i7oEBQmcG8S1xhyps/dYk5Bfh7RafBb2VX+3Ue VbTgkZRQS5L+4XItKlZWuuraEYiKIKB+WvA38jJFNrftPlML7fHcc3gnlsPeMjlJI3Te WpdanWGeylS6dTjDYMoYuHTGmzXVNkcVXPePYh5B7UexANpW5tHJhxCk+cnNirxpB6dS 7pvQ== X-Gm-Message-State: AOAM531I9+OFO2YgzEFaRFs9IJVXzKzlh+YMQvOteq5CJSMSxGxON4Op /pMizK9oISXjtZ8URIxl2xNO0pjKlqCbOE+UDCWyGg== X-Google-Smtp-Source: ABdhPJw4FMjG4RReaHWTMdwYKn9IYKja1cYYp4l4ObWZPSmCFdck3x81fnaNwGUkZ3YIez/wwUXqz8+bf8+V039r6iw= X-Received: by 2002:a17:906:1151:: with SMTP id i17mr6970678eja.250.1610035007516; Thu, 07 Jan 2021 07:56:47 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-5-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-5-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 15:56:36 +0000 Message-ID: Subject: Re: [PATCH v2 04/24] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 15:56:52 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > This is the only caller. Adjust some commentary to talk > about SCTLR_B instead of the vanishing function. > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 37 ++++++++++++++++--------------------- > 1 file changed, 16 insertions(+), 21 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:00:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXiT-0007eW-UG for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 11:00:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXiO-0007de-BY for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:00:45 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:37182) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXiM-0006SX-1e for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:00:44 -0500 Received: by mail-ed1-x531.google.com with SMTP id cm17so8249343edb.4 for ; Thu, 07 Jan 2021 08:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nm2Ima4bp1U3JjhBWCY7piiq4gwIFTGYdxuTBWUSwxA=; b=n5PRIhTcIdazsXZIWOfUu5lS9yaMmgrFRwCnxoqdZIuwe9IvpHrFjhAhibqkzJFYeD 4FOGoPo6ct+qSyvaBQMzAR68yVE7ker2rWREGjsU6dMqqeKGs60mwx6aRgjOYOJiQNzo jp+JEAuSfYrUw6rUbyZKOV937XweNjvcVZt54rbe101Qkaa+asEB+OD7P1oAUjLNfItQ Z+vI7lMiHoruwmio6r0WRnRn6SXKhtZBVxBXk9jpd2y18WpsV8JkDnXXnKcO1OkAyK43 AOykowSSrEeCDPXdnyPpw2kGf/mj05sD7dlTauRxyrtZl7r0Ft06v5uY7rle7WGoWBwu IMvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nm2Ima4bp1U3JjhBWCY7piiq4gwIFTGYdxuTBWUSwxA=; b=Fpnxud+2cqLqtkG4fvrQ4BhYekk0pUPJIPrw0aLikIzdjtsxWKd1cSjTNSI2viCLVq XiTK8osh0iyJpyFE0acbDEVpXeVRjd2goPZUDp0V75PT/AlKLosEYJPZ2eofrfytB5+/ GxVgV8X6zCW6r5rd/cgGILLuh77gkVB4Xtqt/I9yKkeT8mFJOk/+iUdBWxofuZH+Lwja 25WtGOcvfZlF/O7vTtaPsXvB5cZJ+wQnAAGiUs5VEQ1Z+pTbj0KkbcPr3OeEq64SIm3x oB2pEW0+lV8PT2bB+8wHxg/Tg05TywLPRSUaP2W3XaWro4ODxcstGaOH+ltw6PpaiEbM Ntbg== X-Gm-Message-State: AOAM531SoXN0w3Svtn+Zs5V5D7rXN9ZRbS0UpPluEpWWibqc1rXHirx9 EsfmhOrOduhwQDX6hgccR4X2kwDG4ncQYki/1bVUcQ== X-Google-Smtp-Source: ABdhPJwaOdl3MCbeZWtzzeFg3+ziw2gRTwk9Grn0NiN/izVIbCAvQTDn7w1SwAyU39h2g6Vw9FK9MERDA/YtI7tRNQU= X-Received: by 2002:aa7:cdc3:: with SMTP id h3mr2139042edw.52.1610035239948; Thu, 07 Jan 2021 08:00:39 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-6-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-6-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 16:00:28 +0000 Message-ID: Subject: Re: [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:00:46 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Just because operating on a TCGv_i64 temporary does not > mean that we're performing a 64-bit operation. Restrict > the frobbing to actual 64-bit operations. If I understand correctly, this patch isn't actually a behaviour change because at this point the only users of gen_aa32_ld_i64() and gen_aa32_st_i64() are in fact performing 64-bit operations so the (opc & MO_SIZE) == MO_64 test is always true. (Presumably subsequent patches are going to add uses of these functions that want to load smaller sizes?) If that's right, worth mentioning explicitly in the commit message, I think. > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index f35d376341..ef9192cf6b 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -949,7 +949,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, > tcg_gen_qemu_ld_i64(val, addr, index, opc); > > /* Not needed for user-mode BE32, where we use MO_BE instead. */ > - if (!IS_USER_ONLY && s->sctlr_b) { > + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { > tcg_gen_rotri_i64(val, val, 32); > } > > @@ -968,7 +968,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, > TCGv addr = gen_aa32_addr(s, a32, opc); > > /* Not needed for user-mode BE32, where we use MO_BE instead. */ > - if (!IS_USER_ONLY && s->sctlr_b) { > + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { > TCGv_i64 tmp = tcg_temp_new_i64(); > tcg_gen_rotri_i64(tmp, val, 32); > tcg_gen_qemu_st_i64(tmp, addr, index, opc); Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:02:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXkK-0000bh-7d for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 11:02:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXkJ-0000ah-0p for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:02:43 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:33453) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXkG-0007OH-Cq for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:02:42 -0500 Received: by mail-ej1-x631.google.com with SMTP id b9so10484489ejy.0 for ; Thu, 07 Jan 2021 08:02:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QpTqdLWtIvPKAiK2Ykk3FpvmzTk+Xay+EHGBl3cmab0=; b=tSJxIK764+DKGtx/Z1lq2i+zye3TMPQyfdqdYSZ9Qo7yjeoARJqFh4Q2wUgB90JSTm qJEVSzv8GftAQvoF24/9+LMd3oJr8L+6nPR6rBEF8Z+4eUZYJSF2kGXyQAa+vu1W6Hoe XBIX3u2WmxwB6oROQacdss1IZ9iMiu2Tx6Vih2C0P+IUudJ/k0VWD6U8mdrePCX3qOV4 +imHFPE6DKT6oNaDGOVKqXURlVRb6FvqtcVQAFpMZO55P7uQ5iKRxtylX9B3AY7mTHvD zT/SXf41zgW9YZQg+5OGYpjqpK0gSpsVKtRW+Y0TzVub7SdDLj3boLNHpFEM9/LU0d7Q qFnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QpTqdLWtIvPKAiK2Ykk3FpvmzTk+Xay+EHGBl3cmab0=; b=o7BZt8Br6g64HptOlAtpiIaudnq0ru/+g7vrQqM+zQUGeyjuo3SHbwDbxHxvI1kW01 XbOkHfSDAzWpMhGpaMOPhWTfJPiR9iVnpwNF/hl9C9xiPwqxZ4NMl/oApaxDx9x+Tjl6 EsSIHipE4ivgdC5XluP3NKodLQV1BxUalH3EERA0hBn5SYVWErlLsxwSPGKBVqTvyypG 79X8223Gh/K0YiV1TdbXAcZCsMBC9R9H7TP2QBXsipKiAVUWREJICRL5n6kThQc4d7kv O0Q9BK+Xv4acKr4HWC1KBILJ6JmwrxqgJ9lr4lFF9Um+a7XBBumMFTXY+6qjIwrP2mMY Utaw== X-Gm-Message-State: AOAM5313jMmka5dPheMb/D/sG5shzSefpU1uWHhobGzv+fw56z7sTzM6 DOJW9QusaMaygTjPk5sCoX2ZLEq63A2nGhYy9IuJWQ== X-Google-Smtp-Source: ABdhPJxVxZCYtRbpg7yzOhubRw9C02wj3nK+xU7gUl1SU9onzeGH7+2Qty+wdvPpGPA/ZUljm0GIZo6cdslRZmG7jiU= X-Received: by 2002:a17:906:e94c:: with SMTP id jw12mr7069419ejb.56.1610035358781; Thu, 07 Jan 2021 08:02:38 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-7-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-7-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 16:02:27 +0000 Message-ID: Subject: Re: [PATCH v2 06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:02:43 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Adjust the interface to match what has been done to the > TCGv_i32 load/store functions. > > This is less obvious, because at present the only user of > these functions, trans_VLDST_multiple, also wants to manipulate > the endianness to speed up loading multiple bytes. Thus we > retain an "internal" interface which is identical to the > current gen_aa32_{ld,st}_i64 interface. > > The "new" interface will gain users as we remove the legacy > interfaces, gen_aa32_ld64 and gen_aa32_st64. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:08:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXq5-0005zN-92 for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 11:08:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxXpy-0005wu-AC for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:08:39 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:36258) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxXpw-0001ff-G1 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 11:08:34 -0500 Received: by mail-ej1-x631.google.com with SMTP id lt17so10452850ejb.3 for ; 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Thu, 07 Jan 2021 08:08:31 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-8-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-8-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 16:08:19 +0000 Message-ID: Subject: Re: [PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:08:39 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Buglink: https://bugs.launchpad.net/qemu/+bug/1905356 > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:10:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXrV-0007Em-IX for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:10:06 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:10:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXro-0007T4-9e for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:10:27 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:10:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXs7-0007pR-CH for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:10:44 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:10:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXsH-0007tA-RQ for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:10:53 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:14:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXvI-0002yS-Im for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:14:03 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-vfp.c.inc | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:14:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxXvX-0003Sc-1l for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:14:17 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-vfp.c.inc | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:26:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxY77-0002zp-2f for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:26:15 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-neon.c.inc | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Patch subject says "VLD1", but trans_VLD_all_lanes handles all of the "VLDn to all lanes" insns. > diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc > index 18d9042130..7cb89b18e0 100644 > --- a/target/arm/translate-neon.c.inc > +++ b/target/arm/translate-neon.c.inc > @@ -522,6 +522,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) > int size = a->size; > int nregs = a->n + 1; > TCGv_i32 addr, tmp; > + MemOp mop; > > if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { > return false; > @@ -556,12 +557,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) > */ > stride = a->t ? 2 : 1; > vec_size = nregs == 1 ? stride * 8 : 8; > - > + mop = size | (a->a ? MO_ALIGN : 0); > tmp = tcg_temp_new_i32(); > addr = tcg_temp_new_i32(); > load_reg_var(s, addr, a->rn); > for (reg = 0; reg < nregs; reg++) { > - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); > + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); > if ((vd & 1) && vec_size == 16) { > /* > * We cannot write 16 bytes at once because the I think this code is correct for VLD1 (A bit means "address must be aligned to the size of the element") and VLD3 (A bit is always 0), but not for VLD2 (A bit means "address must be aligned to 2* size of element") or VLD4 (A bit means "address must be aligned to 4* size", and there is a special case for size==3 meaning "32 bits at 16-byte alignment"). thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:40:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYLI-0007iz-B1 for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 11:40:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYLH-0007hk-3H for qemu-arm@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:40:55 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.h | 1 + > target/arm/translate.c | 15 +++++++++++++++ > target/arm/translate-neon.c.inc | 27 ++++++++++++++++++++++----- > 3 files changed, 38 insertions(+), 5 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 11:46:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYQl-0001lJ-1z for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 16:46:33 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-neon.c.inc | 48 ++++++++++++++++++++++++++++----- > 1 file changed, 42 insertions(+), 6 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:13:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYr3-0000e9-Az for mharc-qemu-arm@gnu.org; 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Thu, 7 Jan 2021 09:07:27 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id 2EED03F2E377; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 18A2F742C6B; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard Subject: [PATCH 5/9] riscv: Add semihosting support Date: Thu, 7 Jan 2021 09:07:13 -0800 Message-Id: <20210107170717.2098982-6-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:13:44 -0000 Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-6-keithp@keithp.com> --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak | 1 + .../targets/riscv64-linux-user.mak | 1 + hw/semihosting/common-semi.c | 82 ++++++++++++++++++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +- qemu-options.hx | 10 ++- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 +++ .../riscv/insn_trans/trans_privileged.c.inc | 37 ++++++++- target/riscv/translate.c | 11 +++ 13 files changed, 162 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f09deff4d3..f0cf5f10f5 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #include "qemu/osdep.h" @@ -222,6 +226,42 @@ common_semi_rambase(CPUState *cs) #endif /* TARGET_ARM */ +#ifdef TARGET_RISCV +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return env->gpr[xA0 + argno]; +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + env->gpr[xA0] = ret; +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); +} + +#ifndef CONFIG_USER_ONLY + +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return common_semi_find_region_base(env->gpr[xSP]); +} +#endif + +#endif + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -398,6 +438,12 @@ static target_ulong common_semi_flen_buf(CPUState *cs) sp = env->regs[13]; } #endif +#ifdef TARGET_RISCV + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + sp = env->gpr[xSP]; +#endif return sp - 64; } @@ -741,6 +787,37 @@ static const GuestFDFunctions guestfd_fns[] = { put_user_u32(val, args + (n) * 4)) #endif +#ifdef TARGET_RISCV + +/* + * get_user_ual is defined as get_user_u32 in softmmu-semi.h, + * we need a macro that fetches a target_ulong + */ +#define get_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + get_user_u64(arg, p) : \ + get_user_u32(arg, p)) + +/* + * put_user_ual is defined as put_user_u32 in softmmu-semi.h, + * we need a macro that stores a target_ulong + */ +#define put_user_utl(arg, p) \ + ((sizeof(target_ulong) == 8) ? \ + put_user_u64(arg, p) : \ + put_user_u32(arg, p)) + +#define GET_ARG(n) do { \ + if (get_user_utl(arg ## n, args + (n) * sizeof(target_ulong))) { \ + errno = EFAULT; \ + return set_swi_errno(cs, -1); \ + } \ + } while (0) + +#define SET_ARG(n, val) \ + put_user_utl(val, args + (n) * sizeof(target_ulong)) +#endif + /* * Do a semihosting call. * @@ -1179,6 +1256,9 @@ target_ulong do_common_semihosting(CPUState *cs) if (is_a64(cs->env_ptr)) { return 0; } +#endif +#ifdef TARGET_RISCV + return 0; #endif /* fall through -- invalid for A32/T32 */ default: diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h index bc53e92c79..0bfab1c669 100644 --- a/hw/semihosting/common-semi.h +++ b/hw/semihosting/common-semi.h @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -26,6 +26,9 @@ * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #ifndef COMMON_SEMI_H diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..17aa992165 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/linux-user/semihost.c b/linux-user/semihost.c index a1f0f6050e..c0015ee7f6 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -1,11 +1,11 @@ /* - * ARM Semihosting Console Support + * ARM Compatible Semihosting Console Support. * * Copyright (c) 2019 Linaro Ltd * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. + * Currently ARM and RISC-V are unique in having support for + * semihosting support in linux-user. So for now we implement the + * common console API but just for arm and risc-v linux-user. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/qemu-options.hx b/qemu-options.hx index 459c916d3d..cc6c3af936 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4190,10 +4190,10 @@ ERST DEF("semihosting", 0, QEMU_OPTION_semihosting, "-semihosting semihosting mode\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | - QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) + QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting`` - Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II only). + Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so should only be used with a trusted guest OS. @@ -4205,10 +4205,10 @@ DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config, "-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]\n" \ " semihosting configuration\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | -QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) +QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]`` - Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II + Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only). Note that this allows guest direct access to the host filesystem, so @@ -4223,6 +4223,8 @@ SRST open/read/write/seek/select. Tensilica baremetal libc for ISS and linux platform "sim" use this interface. + On RISC-V this implements the standard semihosting API, version 0.2. + ``target=native|gdb|auto`` Defines where the semihosting calls will be addressed, to QEMU (``native``) or to GDB (``gdb``). The default is ``auto``, which diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b41e8836c3..4196ef8b69 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define RISCV_EXCP_SEMIHOST 0x10 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 #define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a2afb95fa1..f8350f5f78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" +#include "hw/semihosting/common-semi.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -847,6 +848,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; + if (cause == RISCV_EXCP_SEMIHOST) { + if (env->priv >= PRV_S) { + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + return; + } + cause = RISCV_EXCP_BREAKPOINT; + } + if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 2a61a853bf..32312be202 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -29,7 +29,42 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a) static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) { - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + target_ulong ebreak_addr = ctx->base.pc_next; + target_ulong pre_addr = ebreak_addr - 4; + target_ulong post_addr = ebreak_addr + 4; + uint32_t pre = 0; + uint32_t ebreak = 0; + uint32_t post = 0; + + /* + * The RISC-V semihosting spec specifies the following + * three-instruction sequence to flag a semihosting call: + * + * slli zero, zero, 0x1f 0x01f01013 + * ebreak 0x00100073 + * srai zero, zero, 0x7 0x40705013 + * + * The two shift operations on the zero register are no-ops, used + * here to signify a semihosting exception, rather than a breakpoint. + * + * Uncompressed instructions are required so that the sequence is easy + * to validate. + * + * The three instructions are required to lie in the same page so + * that no exception will be raised when fetching them. + */ + + if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { + pre = opcode_at(&ctx->base, pre_addr); + ebreak = opcode_at(&ctx->base, ebreak_addr); + post = opcode_at(&ctx->base, post_addr); + } + + if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { + generate_exception(ctx, RISCV_EXCP_SEMIHOST); + } else { + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + } exit_tb(ctx); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 554d52a4be..0f28b5f41e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,6 +64,7 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + CPUState *cs; } DisasContext; #ifdef TARGET_RISCV64 @@ -747,6 +748,15 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, return true; } +static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUState *cpu = ctx->cs; + CPURISCVState *env = cpu->env_ptr; + + return cpu_ldl_code(env, pc); +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" @@ -814,6 +824,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->cs = cs; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrJ-0000qH-WB for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrD-0000pH-K7; Thu, 07 Jan 2021 12:13:56 -0500 Received: from home.keithp.com ([63.227.221.253]:55576 helo=elaine.keithp.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrB-0001cd-4k; Thu, 07 Jan 2021 12:13:55 -0500 Received: from localhost (localhost [127.0.0.1]) by elaine.keithp.com (Postfix) with ESMTP id CD0D83F2E3BD; Thu, 7 Jan 2021 09:07:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1610039245; bh=YnhUQZaG9di3JTUB6ONQsQkxSeXtwlkHPePjWsx+onM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KyOwmarEUyaMuxwJVRUOqjGHC5o0n42ZE6ZQk7wgZv5VnR2uf0zkDsgRnyaHxMfXH G1LqhuQ9MiOEDN/di17YKrXphm7EhSH/ihkQdSUEw1DBYT7FGUPvE2zhjvZoZx9Gze QNhVhJKaAsTwAjRx8jzNp/pyi6RRGUadfd7ZfDOgy/IuznQBX39c5vuF0ocE2AcOqJ ThnwTBlzVXkdURZ/xxUpDHeG7uRXVQ4jkgsHeUp9nQfDN5JIIFdHJIMtZHlbERk411 UJqwEtBjG2PFJSe4I57e0AeAkwitDgMnq5SgocuHzDQECdN/ZkmYRooXo531V1XkTC 2k3LFfx1QGP+g== X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from elaine.keithp.com ([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id VcT8lqcTjnrJ; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id E0E2D3F2E315; Thu, 7 Jan 2021 09:07:23 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 8C44F742C69; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard , Alistair Francis Subject: [PATCH 1/9] semihosting: Move ARM semihosting code to shared directories Date: Thu, 7 Jan 2021 09:07:09 -0800 Message-Id: <20210107170717.2098982-2-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:13:58 -0000 This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis ---- v2 Place common-semi.c name in arm_ss, just as arm-semi.c was v3 Create CONFIG_ARM_COMPATIBLE_SEMIHOSTING and assign in arm config files v4 Also update aarch64_be default config v5 Also update armeb default config --- default-configs/devices/arm-softmmu.mak | 1 + default-configs/targets/aarch64-linux-user.mak | 1 + default-configs/targets/aarch64_be-linux-user.mak | 1 + default-configs/targets/arm-linux-user.mak | 1 + default-configs/targets/armeb-linux-user.mak | 1 + hw/semihosting/Kconfig | 3 +++ target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 hw/semihosting/meson.build | 3 +++ linux-user/arm/meson.build | 3 --- linux-user/meson.build | 1 + linux-user/{arm => }/semihost.c | 0 target/arm/meson.build | 2 -- 12 files changed, 12 insertions(+), 5 deletions(-) rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) rename linux-user/{arm => }/semihost.c (100%) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-configs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/aarch64_be-linux-user.mak b/default-configs/targets/aarch64_be-linux-user.mak index 4c953cf8c5..fae831558d 100644 --- a/default-configs/targets/aarch64_be-linux-user.mak +++ b/default-configs/targets/aarch64_be-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/targets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/armeb-linux-user.mak b/default-configs/targets/armeb-linux-user.mak index 79bf10e99b..255e44e8b0 100644 --- a/default-configs/targets/armeb-linux-user.mak +++ b/default-configs/targets/armeb-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..4c30dc6b16 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,6 @@ config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool diff --git a/target/arm/arm-semi.c b/hw/semihosting/common-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/common-semi.c diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..5b4a170270 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('common-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrP-0000th-HO for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) 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AAv5r+TxQ508Q== X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from elaine.keithp.com ([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id gq7fO4VHvDkL; Thu, 7 Jan 2021 09:07:27 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id 3F63E3F2E381; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 2CFD2742D0D; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard Subject: [PATCH 7/9] semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ Date: Thu, 7 Jan 2021 09:07:15 -0800 Message-Id: <20210107170717.2098982-8-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:02 -0000 These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-8-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++++++++ include/qemu/timer.h | 2 ++ util/qemu-timer-common.c | 4 ++++ 3 files changed, 22 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f0cf5f10f5..b1368d945c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -38,6 +38,7 @@ #include "hw/semihosting/console.h" #include "hw/semihosting/common-semi.h" #include "qemu/log.h" +#include "qemu/timer.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" @@ -73,6 +74,8 @@ #define TARGET_SYS_EXIT 0x18 #define TARGET_SYS_SYNCCACHE 0x19 #define TARGET_SYS_EXIT_EXTENDED 0x20 +#define TARGET_SYS_ELAPSED 0x30 +#define TARGET_SYS_TICKFREQ 0x31 /* ADP_Stopped_ApplicationExit is used for exit(0), * anything else is implemented as exit(1) */ @@ -837,6 +840,7 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t ret; uint32_t len; GuestFD *gf; + int64_t elapsed; (void) env; /* Used implicitly by arm lock_user macro */ nr = common_semi_arg(cs, 0) & 0xffffffffU; @@ -1246,6 +1250,18 @@ target_ulong do_common_semihosting(CPUState *cs) } gdb_exit(cs->env_ptr, ret); exit(ret); + case TARGET_SYS_ELAPSED: + elapsed = get_clock() - clock_start; + if (sizeof(target_ulong) == 8) { + SET_ARG(0, elapsed); + } else { + SET_ARG(0, (uint32_t) elapsed); + SET_ARG(1, (uint32_t) (elapsed >> 32)); + } + return 0; + case TARGET_SYS_TICKFREQ: + /* qemu always uses nsec */ + return 1000000000; case TARGET_SYS_SYNCCACHE: /* * Clean the D-cache and invalidate the I-cache for the specified diff --git a/include/qemu/timer.h b/include/qemu/timer.h index bdecc5b41f..ca6fae51f1 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -806,6 +806,8 @@ static inline int64_t get_clock_realtime(void) return tv.tv_sec * 1000000000LL + (tv.tv_usec * 1000); } +extern int64_t clock_start; + /* Warning: don't insert tracepoints into these functions, they are also used by simpletrace backend and tracepoints would cause an infinite recursion! */ diff --git a/util/qemu-timer-common.c b/util/qemu-timer-common.c index baf3317f74..cc1326f726 100644 --- a/util/qemu-timer-common.c +++ b/util/qemu-timer-common.c @@ -27,6 +27,8 @@ /***********************************************************/ /* real time host monotonic timer */ +int64_t clock_start; + #ifdef _WIN32 int64_t clock_freq; @@ -41,6 +43,7 @@ static void __attribute__((constructor)) init_get_clock(void) exit(1); } clock_freq = freq.QuadPart; + clock_start = get_clock(); } #else @@ -55,5 +58,6 @@ static void __attribute__((constructor)) init_get_clock(void) if (clock_gettime(CLOCK_MONOTONIC, &ts) == 0) { use_rt_clock = 1; } + clock_start = get_clock(); } #endif -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrR-0000ut-6B for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrL-0000qa-HK; Thu, 07 Jan 2021 12:14:03 -0500 Received: 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([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id XOUfMGZHfuGL; Thu, 7 Jan 2021 09:07:28 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id 49C3F3F2E398; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 3DF96742C6B; Thu, 7 Jan 2021 09:07:24 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard Subject: [PATCH 9/9] semihosting: Implement SYS_ISERROR Date: Thu, 7 Jan 2021 09:07:17 -0800 Message-Id: <20210107170717.2098982-10-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:04 -0000 Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-10-keithp@keithp.com> --- hw/semihosting/common-semi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b0648c3812..abc15bf219 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -59,6 +59,7 @@ #define TARGET_SYS_WRITE 0x05 #define TARGET_SYS_READ 0x06 #define TARGET_SYS_READC 0x07 +#define TARGET_SYS_ISERROR 0x08 #define TARGET_SYS_ISTTY 0x09 #define TARGET_SYS_SEEK 0x0a #define TARGET_SYS_FLEN 0x0c @@ -967,6 +968,9 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: return qemu_semihosting_console_inc(cs->env_ptr); + case TARGET_SYS_ISERROR: + GET_ARG(0); + return (target_long) arg0 < 0 ? 1 : 0; case TARGET_SYS_ISTTY: GET_ARG(0); -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrU-00012U-PO for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrO-0000t4-Kl; Thu, 07 Jan 2021 12:14:06 -0500 Received: from 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(elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id JrZe3ojHtXJn; Thu, 7 Jan 2021 09:07:26 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id E5CE53F2E325; Thu, 7 Jan 2021 09:07:23 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 65703742C81; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar Subject: [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Date: Thu, 7 Jan 2021 09:07:08 -0800 Message-Id: <20210107170717.2098982-1-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:07 -0000 This series adds support for RISC-V Semihosting, version 0.2 as specified here: https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 This specification references the ARM semihosting release 2.0 as specified here: https://static.docs.arm.com/100863/0200/semihosting.pdf That specification includes several semihosting calls which were not previously implemented. This series includes implementations for the remaining calls so that both RISC-V and ARM versions are now complete. Tests for release 2.0 can be found in picolibc on the semihost-2.0-all branch: https://github.com/picolibc/picolibc/tree/semihost-2.0-all These tests uncovered a bug in the SYS_HEAPINFO implementation for ARM, which has been fixed in this series as well. The series is structured as follows: 1. Move shared semihosting files 2. Change public common semihosting APIs 3. Change internal semihosting interfaces 4. Fix SYS_HEAPINFO crash on ARM 5-6. Add RISC-V semihosting implementation 7-9. Add missing semihosting operations from release 2.0 From MAILER-DAEMON Thu Jan 07 12:14:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYro-0001N8-9I for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrl-0001FQ-7Q; Thu, 07 Jan 2021 12:14:30 -0500 Received: from home.keithp.com ([63.227.221.253]:55606 helo=elaine.keithp.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrh-0001kr-SK; Thu, 07 Jan 2021 12:14:28 -0500 Received: from localhost (localhost [127.0.0.1]) by elaine.keithp.com (Postfix) with ESMTP id 551883F2E362; Thu, 7 Jan 2021 09:07:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1610039248; bh=AZlHtW8kz5BBCXUeA7PKuNpaggryBx9EMe68Qb8hox4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; 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envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:31 -0000 Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-9-keithp@keithp.com> --- hw/semihosting/common-semi.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index b1368d945c..b0648c3812 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -835,6 +835,7 @@ target_ulong do_common_semihosting(CPUState *cs) CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; + target_ulong ul_ret; char * s; int nr; uint32_t ret; @@ -998,8 +999,24 @@ target_ulong do_common_semihosting(CPUState *cs) return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: - qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); - return -1; + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + if (asprintf(&s, "/tmp/qemu-%x%02x", getpid(), + (int) (arg1 & 0xff)) < 0) { + return -1; + } + ul_ret = (target_ulong) -1; + + /* Make sure there's enough space in the buffer */ + if (strlen(s) < arg2) { + char *output = lock_user(VERIFY_WRITE, arg0, arg2, 0); + strcpy(output, s); + unlock_user(output, arg0, arg2); + ul_ret = 0; + } + free(s); + return ul_ret; case TARGET_SYS_REMOVE: GET_ARG(0); GET_ARG(1); -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrq-0001UF-NE for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYro-0001Ox-Rx; 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Thu, 7 Jan 2021 09:07:27 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id 1F7EC3F2E362; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id 0445A742DC7; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard Subject: [PATCH 4/9] semihosting: Support SYS_HEAPINFO when env->boot_info is not set Date: Thu, 7 Jan 2021 09:07:12 -0800 Message-Id: <20210107170717.2098982-5-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:33 -0000 env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard Message-Id: <20201214200713.3886611-5-keithp@keithp.com> --- hw/semihosting/common-semi.c | 43 +++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 33c82f73b1..f09deff4d3 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -137,6 +137,36 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" +/* + * Find the base of a RAM region containing the specified address + */ +static inline hwaddr +common_semi_find_region_base(hwaddr addr) +{ + MemoryRegion *subregion; + + /* + * Find the chunk of R/W memory containing the address. This is + * used for the SYS_HEAPINFO semihosting call, which should + * probably be using information from the loaded application. + */ + QTAILQ_FOREACH(subregion, &get_system_memory()->subregions, + subregions_link) { + if (subregion->ram && !subregion->readonly) { + Int128 top128 = int128_add(int128_make64(subregion->addr), + subregion->size); + Int128 addr128 = int128_make64(addr); + if (subregion->addr <= addr && int128_lt(addr128, top128)) { + return subregion->addr; + } + } + } + return 0; +} +#endif + #ifdef TARGET_ARM static inline target_ulong common_semi_arg(CPUState *cs, int argno) @@ -175,7 +205,18 @@ common_semi_rambase(CPUState *cs) { CPUArchState *env = cs->env_ptr; const struct arm_boot_info *info = env->boot_info; - return info->loader_start; + target_ulong sp; + + if (info) { + return info->loader_start; + } + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + return common_semi_find_region_base(sp); } #endif -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:14:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYrx-0001lA-Nv for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:14:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYrw-0001i6-D4; Thu, 07 Jan 2021 12:14:40 -0500 Received: from home.keithp.com ([63.227.221.253]:55572 helo=elaine.keithp.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYru-0001ca-8p; Thu, 07 Jan 2021 12:14:40 -0500 Received: from localhost (localhost [127.0.0.1]) by elaine.keithp.com (Postfix) with ESMTP id CFE5D3F2E3BF; Thu, 7 Jan 2021 09:07:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1610039245; bh=s0SeB1l3Vqs614C1WWcDaVfalxIPXWknpXWaPyTYMuM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CCTQA2el5wFzXdfcyKgFTGSW3yb6q7DmlQehbdpd/YDOmWSbAqSKxYwdV5WNOYWd1 vbBSdddu+vCCP1KYUj0MSIwRy0dqbfP2oKDpMnKXqoRX9ByHs2gY7j6SOlUQPyQZQ6 hXpLN8CDn8Cgn4TcDeKMrbIhJqVY/PFuXWW4wVSn7TikVQPNPopSncvTpXuJVzKZyj m8WaBULSE7Da8viRMWdAmsyBsWFoPG3JHYBjxRoSvcx3bbUwv751fuGfUp1yP0Lrbe 914Y+WsFT2BpLx3BegtBGgwGRmyR5zUlShAoOc3hfzgs9sb5xQZCOFIAuFpYO8IHB2 gHOc/Fgx1r5kg== X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from elaine.keithp.com ([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id lWRxVpOPNSvL; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id EC28A3F2E33F; Thu, 7 Jan 2021 09:07:23 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id CF0A5742D1D; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard , Alistair Francis Subject: [PATCH 2/9] semihosting: Change common-semi API to be architecture-independent Date: Thu, 7 Jan 2021 09:07:10 -0800 Message-Id: <20210107170717.2098982-3-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:14:40 -0000 The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis Message-Id: <20201214200713.3886611-3-keithp@keithp.com> --- hw/semihosting/common-semi.c | 16 ++++++++++------ hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 -------- target/arm/helper.c | 5 +++-- target/arm/m_helper.c | 7 ++++++- 7 files changed, 59 insertions(+), 19 deletions(-) create mode 100644 hw/semihosting/common-semi.h diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index f7b7bff522..74f09c038c 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..49d9a314db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d0d4cd1e1..8b6f14e22b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:18:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYvt-0005sB-Lz for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:18:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYvs-0005oU-C4; Thu, 07 Jan 2021 12:18:44 -0500 Received: from home.keithp.com ([63.227.221.253]:55722 helo=elaine.keithp.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYvq-0003Uw-NM; Thu, 07 Jan 2021 12:18:44 -0500 Received: from localhost (localhost [127.0.0.1]) by elaine.keithp.com (Postfix) with ESMTP id D09783F2E325; Thu, 7 Jan 2021 09:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1610039246; bh=bhuL9gru7dcwx7hNurPSG0LXo6Gk/htLgalKFE4yYNQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zfa93vr1u9afwP+YSO+A13dxkreCFQveHsyyh3lk7ZvpgWFrCvari1WRkCYDBrWKT 4C3W4Q0V7YYrTBgZG8RPH5RWHfD9E8zLEKNNrmnrm9ZJA2dHpLmq+8abhN5wXaR7uF MzuWNAKCfX3SC17bNbirn6LgVAAhN8HwiAAPnusmC4/pckjgjzGdoDp1ddRN7iMxYg 2qDwD+pw/JAr+5Sn6kpL6iB8VsXe9pD6ZSd4spIWWZ196KRmfeuveGVR27BRp+6zFO J+OHYaEh9NPRZNBPrPebn4fce8N33gOC17EvQqHkyR86LsCinpfrf6/3PVRgWmJ2Ww IOV3iCgfXpTUw== X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from elaine.keithp.com ([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id TcbzPHBZo4ah; Thu, 7 Jan 2021 09:07:26 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id 0C36B3F2E35D; Thu, 7 Jan 2021 09:07:24 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id E3715742D0D; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Kito Cheng , Keith Packard Subject: [PATCH 6/9] riscv: Add semihosting support for user mode Date: Thu, 7 Jan 2021 09:07:14 -0800 Message-Id: <20210107170717.2098982-7-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:18:44 -0000 From: Kito Cheng This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Reviewed-by: Keith Packard Message-Id: <20201214200713.3886611-7-keithp@keithp.com> --- linux-user/riscv/cpu_loop.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437875..9665dabb09 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP; -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:18:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxYvz-00065H-5B for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:18:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYvx-000613-5E; Thu, 07 Jan 2021 12:18:49 -0500 Received: from home.keithp.com ([63.227.221.253]:55720 helo=elaine.keithp.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxYvt-0003Ux-NJ; Thu, 07 Jan 2021 12:18:48 -0500 Received: from localhost (localhost [127.0.0.1]) by elaine.keithp.com (Postfix) with ESMTP id 047B93F2E3C0; Thu, 7 Jan 2021 09:07:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1610039247; bh=I3WvAAfPGEOLQr/QpJ4MRUi8UAy9/P8vqf+Z3jWuHV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IaMBdi1ZbvgjCRDzXP+ufB6BDyqW1N8QIuWvdpTgl5kTCb1V+xlPvVqCBdksJm/Jy VrzhghF3SlpHZTiERpnw4I3nBw70gqMKKOltdieL7aEK+3qVCAJNITWMm1r9TjxTpe 6gifSig5lTdAeOTqBdSByAdXmyk6bTGophJOiBTWAGWMhZfoAh2kRo9assjHncM7yu PkR25/qtx5+c+OSGnfxmRSPQ75SPGoNDzDVOPHMBUkYxBgL4OkVKcwcMGLDFSVCjZo bjzVUaXEZYneMCGj7mzzCug/L1bcKb/SMxKoIcF3BPrHHbIr5A7cDYkEZsFNpYHcTg GfzYUJLLwkXlg== X-Virus-Scanned: Debian amavisd-new at keithp.com Received: from elaine.keithp.com ([127.0.0.1]) by localhost (elaine.keithp.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id D8NRhNGrTE2e; Thu, 7 Jan 2021 09:07:26 -0800 (PST) Received: from vr.keithp.com (vr.keithp.com [10.0.0.39]) by elaine.keithp.com (Postfix) with ESMTP id DAB693F2E263; Thu, 7 Jan 2021 09:07:23 -0800 (PST) Received: by vr.keithp.com (Postfix, from userid 1000) id AF169742C6B; Thu, 7 Jan 2021 09:07:23 -0800 (PST) From: Keith Packard To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar , Keith Packard , Alistair Francis Subject: [PATCH 3/9] semihosting: Change internal common-semi interfaces to use CPUState * Date: Thu, 7 Jan 2021 09:07:11 -0800 Message-Id: <20210107170717.2098982-4-keithp@keithp.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210107170717.2098982-1-keithp@keithp.com> References: <20210107170717.2098982-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=63.227.221.253; envelope-from=keithp@vr.keithp.com; helo=elaine.keithp.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:18:49 -0000 This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. static inline target_ulong common_semi_rambase(CPUState *cs) Returns the base of RAM region used for heap and stack. This is used to construct plausible values for the SYS_HEAPINFO call. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis ---- v2: Add common_semi_rambase hook to get memory address for SYS_HEAPINFO call. Message-Id: <20201214200713.3886611-4-keithp@keithp.com> --- hw/semihosting/common-semi.c | 351 +++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 164 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 74f09c038c..33c82f73b1 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -32,15 +32,18 @@ #include "cpu.h" #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" +#include "hw/semihosting/common-semi.h" #include "qemu/log.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" -#define ARM_ANGEL_HEAP_SIZE (128 * 1024 * 1024) +#define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024) #else #include "exec/gdbstub.h" #include "qemu/cutils.h" +#ifdef TARGET_ARM #include "hw/arm/boot.h" +#endif #include "hw/boards.h" #endif @@ -134,6 +137,50 @@ typedef struct GuestFD { static GArray *guestfd_array; +#ifdef TARGET_ARM +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + return env->xregs[argno]; + } else { + return env->regs[argno]; + } +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + if (is_a64(env)) { + env->xregs[0] = ret; + } else { + env->regs[0] = ret; + } +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); +} + +#ifndef CONFIG_USER_ONLY +#include "hw/arm/boot.h" +static inline target_ulong +common_semi_rambase(CPUState *cs) +{ + CPUArchState *env = cs->env_ptr; + const struct arm_boot_info *info = env->boot_info; + return info->loader_start; +} +#endif + +#endif /* TARGET_ARM */ + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -239,11 +286,10 @@ static target_ulong syscall_err; #include "exec/softmmu-semi.h" #endif -static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUState *cs, uint32_t code) { if (code == (uint32_t)-1) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->swi_errno = errno; @@ -254,10 +300,9 @@ static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) return code; } -static inline uint32_t get_swi_errno(CPUARMState *env) +static inline uint32_t get_swi_errno(CPUState *cs) { #ifdef CONFIG_USER_ONLY - CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; return ts->swi_errno; @@ -266,24 +311,22 @@ static inline uint32_t get_swi_errno(CPUARMState *env) #endif } -static target_ulong arm_semi_syscall_len; +static target_ulong common_semi_syscall_len; -static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; + target_ulong reg0 = common_semi_arg(cs, 0); if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); reg0 = ret; } else { /* Fixup syscalls that use nonstardard return conventions. */ switch (reg0) { case TARGET_SYS_WRITE: case TARGET_SYS_READ: - reg0 = arm_semi_syscall_len - ret; + reg0 = common_semi_syscall_len - ret; break; case TARGET_SYS_SEEK: reg0 = 0; @@ -293,77 +336,66 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) break; } } - if (is_a64(env)) { - env->xregs[0] = reg0; - } else { - env->regs[0] = reg0; - } + common_semi_set_ret(cs, reg0); } -static target_ulong arm_flen_buf(ARMCPU *cpu) +static target_ulong common_semi_flen_buf(CPUState *cs) { + target_ulong sp; +#ifdef TARGET_ARM /* Return an address in target memory of 64 bytes where the remote * gdb should write its stat struct. (The format of this structure * is defined by GDB's remote protocol and is not target-specific.) * We put this on the guest's stack just below SP. */ + ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong sp; if (is_a64(env)) { sp = env->xregs[31]; } else { sp = env->regs[13]; } +#endif return sp - 64; } -static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ uint32_t size; - cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0); + cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + 32, + (uint8_t *)&size, 4, 0); size = be32_to_cpu(size); - if (is_a64(env)) { - env->xregs[0] = size; - } else { - env->regs[0] = size; - } + common_semi_set_ret(cs, size); errno = err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); } -static int arm_semi_open_guestfd; +static int common_semi_open_guestfd; -static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void +common_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong err) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; if (ret == (target_ulong)-1) { errno = err; - set_swi_errno(env, -1); - dealloc_guestfd(arm_semi_open_guestfd); + set_swi_errno(cs, -1); + dealloc_guestfd(common_semi_open_guestfd); } else { - associate_guestfd(arm_semi_open_guestfd, ret); - ret = arm_semi_open_guestfd; - } - - if (is_a64(env)) { - env->xregs[0] = ret; - } else { - env->regs[0] = ret; + associate_guestfd(common_semi_open_guestfd, ret); + ret = common_semi_open_guestfd; } + common_semi_set_ret(cs, ret); } -static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, - const char *fmt, ...) +static target_ulong +common_semi_gdb_syscall(CPUState *cs, gdb_syscall_complete_cb cb, + const char *fmt, ...) { va_list va; - CPUARMState *env = &cpu->env; va_start(va, fmt); gdb_do_syscallv(cb, fmt, va); @@ -386,7 +418,7 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * doing something with the return value is not possible to make. */ - return is_a64(env) ? env->xregs[0] : env->regs[0]; + return common_semi_arg(cs, 0); } /* @@ -395,20 +427,18 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do the work and return the required return value for the guest, * setting the guest errno if appropriate. */ -typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_closefn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_isattyfn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset); -typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); +typedef uint32_t sys_flenfn(CPUState *cs, GuestFD *gf); -static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_closefn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; - /* * Only close the underlying host fd if it's one we opened on behalf * of the guest in SYS_OPEN. @@ -418,20 +448,21 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) gf->hostfd == STDERR_FILENO) { return 0; } - return set_swi_errno(env, close(gf->hostfd)); + return set_swi_errno(cs, close(gf->hostfd)); } -static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_READ, buf, len, 1); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* Return bytes not written on error */ return len; } - ret = set_swi_errno(env, write(gf->hostfd, s, len)); + ret = set_swi_errno(cs, write(gf->hostfd, s, len)); unlock_user(s, buf, 0); if (ret == (uint32_t)-1) { ret = 0; @@ -440,18 +471,19 @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t ret; - CPUARMState *env = &cpu->env; char *s = lock_user(VERIFY_WRITE, buf, len, 0); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* return bytes not read */ return len; } do { - ret = set_swi_errno(env, read(gf->hostfd, s, len)); + ret = set_swi_errno(cs, read(gf->hostfd, s, len)); } while (ret == -1 && errno == EINTR); unlock_user(s, buf, len); if (ret == (uint32_t)-1) { @@ -461,68 +493,66 @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, return len - ret; } -static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_isattyfn(CPUState *cs, GuestFD *gf) { return isatty(gf->hostfd); } -static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t host_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - CPUARMState *env = &cpu->env; - uint32_t ret = set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET)); + uint32_t ret = set_swi_errno(cs, lseek(gf->hostfd, offset, SEEK_SET)); if (ret == (uint32_t)-1) { return -1; } return 0; } -static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_flenfn(CPUState *cs, GuestFD *gf) { - CPUARMState *env = &cpu->env; struct stat buf; - uint32_t ret = set_swi_errno(env, fstat(gf->hostfd, &buf)); + uint32_t ret = set_swi_errno(cs, fstat(gf->hostfd, &buf)); if (ret == (uint32_t)-1) { return -1; } return buf.st_size; } -static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_closefn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "close,%x", gf->hostfd); } -static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "write,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len = len; - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len = len; + return common_semi_gdb_syscall(cs, common_semi_cb, "read,%x,%x,%x", + gf->hostfd, buf, len); } -static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_isattyfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "isatty,%x", gf->hostfd); } -static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t gdb_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", - gf->hostfd, offset); + return common_semi_gdb_syscall(cs, common_semi_cb, "lseek,%x,%x,0", + gf->hostfd, offset); } -static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_flenfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", - gf->hostfd, arm_flen_buf(cpu)); + return common_semi_gdb_syscall(cs, common_semi_flen_cb, "fstat,%x,%x", + gf->hostfd, common_semi_flen_buf(cs)); } #define SHFB_MAGIC_0 0x53 @@ -551,31 +581,29 @@ static void init_featurefile_guestfd(int guestfd) gf->featurefile_offset = 0; } -static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_closefn(CPUState *cs, GuestFD *gf) { /* Nothing to do */ return 0; } -static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { /* This fd can never be open for writing */ - CPUARMState *env = &cpu->env; errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } -static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env = cs->env_ptr; uint32_t i; -#ifndef CONFIG_USER_ONLY - CPUARMState *env = &cpu->env; -#endif char *s; + (void) env; /* Used in arm softmmu lock_user implicitly */ s = lock_user(VERIFY_WRITE, buf, len, 0); if (!s) { return len; @@ -595,19 +623,19 @@ static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, return len - i; } -static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_isattyfn(CPUState *cs, GuestFD *gf) { return 0; } -static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { gf->featurefile_offset = offset; return 0; } -static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_flenfn(CPUState *cs, GuestFD *gf) { return sizeof(featurefile_data); } @@ -651,16 +679,17 @@ static const GuestFDFunctions guestfd_fns[] = { /* Read the input value from the argument block; fail the semihosting * call if the memory read fails. */ +#ifdef TARGET_ARM #define GET_ARG(n) do { \ if (is_a64(env)) { \ if (get_user_u64(arg ## n, args + (n) * 8)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } else { \ if (get_user_u32(arg ## n, args + (n) * 4)) { \ errno = EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } \ } while (0) @@ -669,6 +698,7 @@ static const GuestFDFunctions guestfd_fns[] = { (is_a64(env) ? \ put_user_u64(val, args + (n) * 8) : \ put_user_u32(val, args + (n) * 4)) +#endif /* * Do a semihosting call. @@ -681,8 +711,7 @@ static const GuestFDFunctions guestfd_fns[] = { */ target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUArchState *env = cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -691,14 +720,9 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t len; GuestFD *gf; - if (is_a64(env)) { - /* Note that the syscall number is in W0, not X0 */ - nr = env->xregs[0] & 0xffffffffU; - args = env->xregs[1]; - } else { - nr = env->regs[0]; - args = env->regs[1]; - } + (void) env; /* Used implicitly by arm lock_user macro */ + nr = common_semi_arg(cs, 0) & 0xffffffffU; + args = common_semi_arg(cs, 1); switch (nr) { case TARGET_SYS_OPEN: @@ -711,19 +735,19 @@ target_ulong do_common_semihosting(CPUState *cs) s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (arg1 >= 12) { unlock_user(s, arg0, 0); errno = EINVAL; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } guestfd = alloc_guestfd(); if (guestfd < 0) { unlock_user(s, arg0, 0); errno = EMFILE; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (strcmp(s, ":tt") == 0) { @@ -752,18 +776,19 @@ target_ulong do_common_semihosting(CPUState *cs) if (arg1 != 0 && arg1 != 1) { dealloc_guestfd(guestfd); errno = EACCES; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } init_featurefile_guestfd(guestfd); return guestfd; } if (use_gdb_syscalls()) { - arm_semi_open_guestfd = guestfd; - ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, - (int)arg2 + 1, gdb_open_modeflags[arg1]); + common_semi_open_guestfd = guestfd; + ret = common_semi_gdb_syscall(cs, common_semi_open_cb, + "open,%s,%x,1a4", arg0, (int)arg2 + 1, + gdb_open_modeflags[arg1]); } else { - ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); + ret = set_swi_errno(cs, open(s, open_modeflags[arg1], 0644)); if (ret == (uint32_t)-1) { dealloc_guestfd(guestfd); } else { @@ -780,17 +805,17 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = guestfd_fns[gf->type].closefn(cpu, gf); + ret = guestfd_fns[gf->type].closefn(cs, gf); dealloc_guestfd(arg0); return ret; case TARGET_SYS_WRITEC: - qemu_semihosting_console_outc(env, args); + qemu_semihosting_console_outc(cs->env_ptr, args); return 0xdeadbeef; case TARGET_SYS_WRITE0: - return qemu_semihosting_console_outs(env, args); + return qemu_semihosting_console_outs(cs->env_ptr, args); case TARGET_SYS_WRITE: GET_ARG(0); GET_ARG(1); @@ -800,10 +825,10 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].writefn(cs, gf, arg1, len); case TARGET_SYS_READ: GET_ARG(0); GET_ARG(1); @@ -813,22 +838,22 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: - return qemu_semihosting_console_inc(env); + return qemu_semihosting_console_inc(cs->env_ptr); case TARGET_SYS_ISTTY: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].isattyfn(cpu, gf); + return guestfd_fns[gf->type].isattyfn(cs, gf); case TARGET_SYS_SEEK: GET_ARG(0); GET_ARG(1); @@ -836,20 +861,20 @@ target_ulong do_common_semihosting(CPUState *cs) gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); + return guestfd_fns[gf->type].seekfn(cs, gf, arg1); case TARGET_SYS_FLEN: GET_ARG(0); gf = get_guestfd(arg0); if (!gf) { errno = EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - return guestfd_fns[gf->type].flenfn(cpu, gf); + return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__); return -1; @@ -857,15 +882,15 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", - arg0, (int)arg1 + 1); + ret = common_semi_gdb_syscall(cs, common_semi_cb, "unlink,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, remove(s)); + ret = set_swi_errno(cs, remove(s)); unlock_user(s, arg0, 0); } return ret; @@ -875,17 +900,18 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(2); GET_ARG(3); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", - arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "rename,%s,%s", + arg0, (int)arg1 + 1, arg2, + (int)arg3 + 1); } else { char *s2; s = lock_user_string(arg0); s2 = lock_user_string(arg2); if (!s || !s2) { errno = EFAULT; - ret = set_swi_errno(env, -1); + ret = set_swi_errno(cs, -1); } else { - ret = set_swi_errno(env, rename(s, s2)); + ret = set_swi_errno(cs, rename(s, s2)); } if (s2) unlock_user(s2, arg2, 0); @@ -896,25 +922,25 @@ target_ulong do_common_semihosting(CPUState *cs) case TARGET_SYS_CLOCK: return clock() / (CLOCKS_PER_SEC / 100); case TARGET_SYS_TIME: - return set_swi_errno(env, time(NULL)); + return set_swi_errno(cs, time(NULL)); case TARGET_SYS_SYSTEM: GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", - arg0, (int)arg1 + 1); + return common_semi_gdb_syscall(cs, common_semi_cb, "system,%s", + arg0, (int)arg1 + 1); } else { s = lock_user_string(arg0); if (!s) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret = set_swi_errno(env, system(s)); + ret = set_swi_errno(cs, system(s)); unlock_user(s, arg0, 0); return ret; } case TARGET_SYS_ERRNO: - return get_swi_errno(env); + return get_swi_errno(cs); case TARGET_SYS_GET_CMDLINE: { /* Build a command-line from the original argv. @@ -966,21 +992,21 @@ target_ulong do_common_semihosting(CPUState *cs) if (output_size > input_size) { /* Not enough space to store command-line arguments. */ errno = E2BIG; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Adjust the command-line length. */ if (SET_ARG(1, output_size - 1)) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Lock the buffer on the ARM side. */ output_buffer = lock_user(VERIFY_WRITE, arg0, output_size, 0); if (!output_buffer) { errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } /* Copy the command-line arguments. */ @@ -996,7 +1022,7 @@ target_ulong do_common_semihosting(CPUState *cs) if (copy_from_user(output_buffer, ts->info->arg_start, output_size)) { errno = EFAULT; - status = set_swi_errno(env, -1); + status = set_swi_errno(cs, -1); goto out; } @@ -1021,8 +1047,7 @@ target_ulong do_common_semihosting(CPUState *cs) #ifdef CONFIG_USER_ONLY TaskState *ts = cs->opaque; #else - const struct arm_boot_info *info = env->boot_info; - target_ulong rambase = info->loader_start; + target_ulong rambase = common_semi_rambase(cs); #endif GET_ARG(0); @@ -1036,7 +1061,7 @@ target_ulong do_common_semihosting(CPUState *cs) abi_ulong ret; ts->heap_base = do_brk(0); - limit = ts->heap_base + ARM_ANGEL_HEAP_SIZE; + limit = ts->heap_base + COMMON_SEMI_HEAP_SIZE; /* Try a big heap, and reduce the size if that fails. */ for (;;) { ret = do_brk(limit); @@ -1064,23 +1089,19 @@ target_ulong do_common_semihosting(CPUState *cs) for (i = 0; i < ARRAY_SIZE(retvals); i++) { bool fail; - if (is_a64(env)) { - fail = put_user_u64(retvals[i], arg0 + i * 8); - } else { - fail = put_user_u32(retvals[i], arg0 + i * 4); - } + fail = SET_ARG(i, retvals[i]); if (fail) { /* Couldn't write back to argument block */ errno = EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } } return 0; } case TARGET_SYS_EXIT: case TARGET_SYS_EXIT_EXTENDED: - if (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { + if (common_semi_sys_exit_extended(cs, nr)) { /* * The A64 version of SYS_EXIT takes a parameter block, * so the application-exit type can return a subcode which @@ -1105,7 +1126,7 @@ target_ulong do_common_semihosting(CPUState *cs) */ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(cs->env_ptr, ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* @@ -1113,9 +1134,11 @@ target_ulong do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ - if (is_a64(env)) { +#ifdef TARGET_ARM + if (is_a64(cs->env_ptr)) { return 0; } +#endif /* fall through -- invalid for A32/T32 */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); -- 2.29.2 From MAILER-DAEMON Thu Jan 07 12:30:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZ7V-0004hF-5Y for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:30:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZ7R-0004ec-A6 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:30:41 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:34653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZ7O-00089D-QV for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:30:41 -0500 Received: by mail-ed1-x532.google.com with SMTP id dk8so8587058edb.1 for ; Thu, 07 Jan 2021 09:30:35 -0800 (PST) DKIM-Signature: v=1; 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Thu, 07 Jan 2021 09:30:34 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-18-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-18-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 17:30:23 +0000 Message-ID: Subject: Re: [PATCH v2 17/24] target/arm: Use finalize_memop for aa64 gpr load/store To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:30:42 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > In the case of gpr load, merge the size and is_signed arguments; > otherwise, simply convert size to memop. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:30:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZ7g-0004qy-VI for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:30:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZ7f-0004mq-Jd for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:30:55 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:42993) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZ7b-0008CJ-A9 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:30:55 -0500 Received: by mail-ej1-x633.google.com with SMTP id d17so10752371ejy.9 for ; Thu, 07 Jan 2021 09:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; 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Thu, 07 Jan 2021 09:30:49 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-19-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-19-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 17:30:37 +0000 Message-ID: Subject: Re: [PATCH v2 18/24] target/arm: Use finalize_memop for aa64 fpr load/store To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:30:56 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > For 128-bit load/store, use 16-byte alignment. This > requires that we perform the two operations in the > correct order so that we generate the alignment fault > before modifying memory. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:32:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZ90-00068v-A8 for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:32:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZ8z-00065m-7Q for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:32:17 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:40939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZ8v-0000Gp-Bg for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:32:16 -0500 Received: by mail-ed1-x529.google.com with SMTP id h16so8505701edt.7 for ; Thu, 07 Jan 2021 09:32:12 -0800 (PST) DKIM-Signature: v=1; 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Thu, 07 Jan 2021 09:32:11 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-20-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-20-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 17:32:00 +0000 Message-ID: Subject: Re: [PATCH v2 19/24] target/arm: Enforce alignment for aa64 load-acq/store-rel To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:32:17 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 23 ++++++++++++++--------- > 1 file changed, 14 insertions(+), 9 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:33:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZ9u-0006ii-Ej for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:33:13 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:36:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZCo-0001bV-1U for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:36:13 -0000 On Tue, 8 Dec 2020 at 18:01, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:37:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZDg-0002NI-Le for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:37:06 -0000 On Tue, 8 Dec 2020 at 18:02, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:37:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZDu-0002cl-Ua for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:37:21 -0000 On Tue, 8 Dec 2020 at 18:02, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-sve.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index 0c3a6d2121..6125e734af 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -5011,7 +5011,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) > clean_addr = gen_mte_check1(s, temp, false, true, msz); > > tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), > - s->be_data | dtype_mop[a->dtype]); > + finalize_memop(s, dtype_mop[a->dtype])); > > /* Broadcast to *all* elements. */ > tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), > -- Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:39:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZGF-0004r0-Gj for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:39:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZG7-0004mt-Bu for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:39:40 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:33989) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZG5-0003GO-0z for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:39:39 -0500 Received: by mail-ej1-x634.google.com with SMTP id g20so10918143ejb.1 for ; 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Thu, 07 Jan 2021 09:39:35 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-25-richard.henderson@linaro.org> In-Reply-To: <20201208180118.157911-25-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 17:39:24 +0000 Message-ID: Subject: Re: [PATCH v2 24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:39:41 -0000 On Tue, 8 Dec 2020 at 18:02, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate-sve.c | 58 +++++++++++++++++++++++++++++--------- > 1 file changed, 45 insertions(+), 13 deletions(-) > > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index 6125e734af..b481e97428 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -4263,7 +4263,8 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a) > * The load should begin at the address Rn + IMM. > */ > > -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) > +static void do_ldr(DisasContext *s, uint32_t vofs, int len, > + MemOp align, int rn, int imm) > { > int len_align = QEMU_ALIGN_DOWN(len, 8); > int len_remain = len % 8; > @@ -4276,6 +4277,10 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) > clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8); > tcg_temp_free_i64(dirty_addr); > > + if (!s->align_mem) { > + align = 0; > + } > + > /* > * Note that unpredicated load/store of vector/predicate registers > * are defined as a stream of bytes, which equates to little-endian > @@ -4288,7 +4293,8 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) > > t0 = tcg_temp_new_i64(); > for (i = 0; i < len_align; i += 8) { > - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); > + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ | align); > + align = 0; > tcg_gen_st_i64(t0, cpu_env, vofs + i); > tcg_gen_addi_i64(clean_addr, clean_addr, 8); > } > @@ -4302,6 +4308,16 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) > clean_addr = new_tmp_a64_local(s); > tcg_gen_mov_i64(clean_addr, t0); > > + if (align > MO_ALIGN_8) { > + t0 = tcg_temp_new_i64(); > + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ | align); > + tcg_gen_addi_i64(clean_addr, clean_addr, 8); > + tcg_gen_addi_ptr(i, i, 8); > + tcg_gen_st_i64(t0, cpu_env, vofs); > + tcg_temp_free_i64(t0); > + align = 0; > + } > + Why do we need to do this (and the similar thing in do_str()) ? Most of the rest of the patch is fairly clear in that it is just passing the alignment requirement through to the load/store fns, but this is a bit more opaque to me... thanks -- PMM From MAILER-DAEMON Thu Jan 07 12:43:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZJq-00011o-Ad for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 12:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZJo-0000yF-Pt for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:43:28 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]:40026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZJn-0004zQ-6Q for qemu-arm@nongnu.org; Thu, 07 Jan 2021 12:43:28 -0500 Received: by mail-ed1-x533.google.com with SMTP id h16so8539142edt.7 for ; Thu, 07 Jan 2021 09:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LBOgn61wexeXsurZm8vyfI7SFAM/KVT0qJzidYdDdIk=; b=jeKyFhW2nLQEfD1NVGZ/P7iV8L40GOO1rQjSPhjY+RLb3FzrfI9NG+sDVvXMvJzA0p f4+FYue+YCg3BycfSscA+8vziqs36jBdz7aFf366Lxf53QZaR1g2bGB88ng0Fz4rRw+E E2F5i1l/XSKAZymdqabL3oLiq4cmLMIubdl82+hqM1mAcsX260/62hQS/ke9zJVQ/13q cGsgqhK4D8ohjkqMA+QyCXDOpThz57HwdyHFWyCzJAiKVOoojb6+rjCZDeqBA6Wn3ItG 1/Vrw97rFMy+0o0bAjlN8398Mv91pxg9Jj8eKMTuzs/cC2W0R+Roat41zHQS0wNwdMY6 AenQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LBOgn61wexeXsurZm8vyfI7SFAM/KVT0qJzidYdDdIk=; b=MP3lYHkkyW6wvJLONaG+QMNvJ41/yVWQxctG5TrOAX4s24dFJE3cfDYTmxzKADJLbV 6LzUYEmt8hfuMeBHlwWTIG3sclxsCB7CpR4csW3Nl20VVGzglgPXevs6tP5yvajT8sLR abn4ky6+Y7R+qtNvTU0pKJeZ6Az4+J2cj8t1i3Wadw3T7npJhH9bZhtmvioAHr49WQ3B IpzjG46CFpzLTXJmpYdwZQXzuuVWU2NKpyV2dg7xbodNr+4TFMhFbOy4CSm9UV+aqWYl WN2LYeTR8qSRXjTaTJjThpVsue6ayZZBugYj785p5QfpA1/Fe8Q2p7ZsdwtUu8FJc+VY XY9A== X-Gm-Message-State: AOAM530IxtI3ldKqfdplhUGPYf/MRLUJzeFGHiMTwJC844O7zxbcrZ8k cO+6UzbtQZ1TCyH3j35iA0nMeH+dr0+tEJ3B9z8ENg== X-Google-Smtp-Source: ABdhPJxsAIe0quszlsx39/os5E/XhJP9EHfHqqyun8inAHqSvzz+rXq1MDWKU+VP9CcEOU05azZ0YepXznHMYka9a2E= X-Received: by 2002:a05:6402:1383:: with SMTP id b3mr2411472edv.100.1610041403544; Thu, 07 Jan 2021 09:43:23 -0800 (PST) MIME-Version: 1.0 References: <20201215114828.18076-1-leif@nuviainc.com> <20201215114828.18076-4-leif@nuviainc.com> <20201215164904.GY1664@vanye> <20201217121031.GK1664@vanye> <20201217122444.GL1664@vanye> In-Reply-To: <20201217122444.GL1664@vanye> From: Peter Maydell Date: Thu, 7 Jan 2021 17:43:12 +0000 Message-ID: Subject: Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h To: Leif Lindholm Cc: Laurent Desnogues , qemu-arm , "qemu-devel@nongnu.org" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 17:43:29 -0000 On Thu, 17 Dec 2020 at 12:24, Leif Lindholm wrote: > > On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote: > > I was thinking about changing the field names, not the register name > > because the register is the same, only the layout changes. So > > LINESIZE -> CCIDX_LINESIZE, etc. > > > > That's personal preference, Peter might have a different one. > > I see. Sure, that works too, and doesn't pollute the register name. > I'll wait for Peter before sending out v3. Laurent's suggestion works for me. thanks -- PMM From MAILER-DAEMON Thu Jan 07 13:02:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZcD-0007gx-7X for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 13:02:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZcB-0007es-7Y for qemu-arm@nongnu.org; Thu, 07 Jan 2021 13:02:27 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:39003) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxZc6-0004aK-94 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 13:02:27 -0500 Received: by mail-ed1-x529.google.com with SMTP id c7so8612402edv.6 for ; Thu, 07 Jan 2021 10:02:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OCGTGUYTbrpYxpy6N+yk8L7761YrfaK62v2oJ5rkRXc=; b=l0HvHX1mMxpjonD6nAipyV7YSNvjieW517tkRWgqvSMFToSJ0H2C9aWbLcNtpWa/0e ienqfKSU7i1TwpWiPmKzLlRPRGqvq7TW1XHL8RGTznxbLBlwUJl7pWrhV5N71k8/yxBM LXRjqS1s3Pq7iNfUx3i9wd/Tw+p0D7ohih8MWx4YR/AcP1P7O/n3kOL09kf4n+1OGoGX 0hSpBU/Maxmup4aQPqxY+NC6bIY8VaaK/FkoICuihOALssTPisDL+mCr0RuTF0zZ0J7J BuJ3b3Q5GN0o7suAia3rf3v1tCV8LJDdUvxHdDJn/C2M5aFW1YKxJVIkMZABQeSHyWsc vjvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OCGTGUYTbrpYxpy6N+yk8L7761YrfaK62v2oJ5rkRXc=; b=LRkerXXrCbhdjRG/1RDeQU1jUILCAyjd3q1ytV7kzm+lFNSGWOBtNsKVG192r/ClE8 pg2z89Uhp8KfBaXzAGXFGMU0sytGGwW+QWDyMbK9n4ap83gnZ1JZKZ4AbAdUqVj74oXQ RHYgQDA3l8tVHg4PICDLZLLeAQy4KWZx0bbw3yxydnL52FhTXETU3YEp82lIwp+YCAVI fPGfuDUaXqdCmCPRVKsECo5speM1TJF008dwFioCSvosCYK6HeC4RzrhDnOAK9p/vvR3 NJtcSbMxDbqcZyAUKa+bWkUiUV4efbXUuVdebi3z16j0newIvooMs8ItR5WWm/ETrPQg 11Ow== X-Gm-Message-State: AOAM533ueddbJzLxV6k7sFwd/bwpWr+goZswzYHUjUDD8Mv/6VfO6CvO ce5xDzqnHYWAEAEat211haljSh/VFQeI6N3/rhDasw== X-Google-Smtp-Source: ABdhPJzhuSRkRvEn1NMmn1jn/aQZZbdEbrEP33ZMLIerikWjHomA74AQiCeSTW5IGz7TeqB9qD6I2NglmQZotq/2P3o= X-Received: by 2002:a50:fd18:: with SMTP id i24mr2600174eds.146.1610042538965; Thu, 07 Jan 2021 10:02:18 -0800 (PST) MIME-Version: 1.0 References: <20201230172522.33629-1-richard.henderson@linaro.org> In-Reply-To: <20201230172522.33629-1-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 18:02:07 +0000 Message-ID: Subject: Re: [PATCH] target/arm: Fix sve pred_desc decoding To: Richard Henderson Cc: QEMU Developers , qemu-arm , qemu-stable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 18:02:27 -0000 On Wed, 30 Dec 2020 at 17:25, Richard Henderson wrote: > > There was an inconsistency between encoding, which uses > SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS. > This happened to be ok, until e2e7168a214, which reduced > the size of SIMD_OPRSZ_BITS, which lead to truncating all > predicate vector lengths. > > Cc: qemu-stable@nongnu.org > Buglink: https://bugs.launchpad.net/bugs/1908551 > Signed-off-by: Richard Henderson > --- > > Ouch. The patch that exposed this, e2e7168a214, went in near > the start of the 5.2 devel period, and I never noticed. I've > been doing most of my testing vs ArmIE of late, which due to > lack of a proper sve signal frame restricts RISU to sve128, > which worked fine with this truncation. I need to spend some > time getting FVP working again... > > > r~ > > --- > target/arm/sve_helper.c | 46 ++++++++++++++++++++--------------------- > 1 file changed, 23 insertions(+), 23 deletions(-) > > diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c > index 5f037c3a8f..99e4b70d2f 100644 > --- a/target/arm/sve_helper.c > +++ b/target/arm/sve_helper.c > @@ -914,7 +914,7 @@ uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words) > > uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc) > { > - intptr_t words = extract32(pred_desc, 0, SIMD_OPRSZ_BITS); > + intptr_t words = extract32(pred_desc, 0, SIMD_DATA_SHIFT); > intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); > uint32_t flags = PREDTEST_INIT; > uint64_t *d = vd, *g = vg, esz_mask; > @@ -1867,7 +1867,7 @@ static uint64_t compress_bits(uint64_t x, int n) > > void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) > { > - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; > + intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2; Why do we not get oprsz by extracting SIMD_OPRSZ_BITS starting at SIMD_OPRSZ_SHIFT ? (or even by calling simd_oprsz(), which certainly looks like it ought to be a helper function for extracting the oprsz...) If the encoding constants in tcg-gvec-desc.h are right then "SIMD_DATA_SHIFT bits starting at bit 0" is two fields glued together (MAXSZ and OPRSZ). thanks -- PMM From MAILER-DAEMON Thu Jan 07 13:14:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxZnY-0006Rw-4i for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 13:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxZnW-0006Pi-JB for qemu-arm@nongnu.org; Thu, 07 Jan 2021 13:14:10 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:24518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kxZnT-0000gP-Fq for qemu-arm@nongnu.org; Thu, 07 Jan 2021 13:14:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610043246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EevDkj3Eq5HGyjrzEGnkPKUnTQ5NdW9RJ/mZwCBu75Y=; b=VHnuf8xpX+gQoe4KSCS3PiBQmYJ1XuqJaZglLzfcwJ+oYl5KZ8/OB08n3yk/nOvAAny4m2 yCzCqhyb+384IThkskoYVbpCGqEfUufSdPFzjK1JdHjYr9O34tqofhaCXbK01ChTXoVHz2 ZtONlJ3eApbs7EWClfbWcy1rH6RGPgE= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-348-b38hnEtcM3ikSYhhjSV9Ow-1; Thu, 07 Jan 2021 13:14:05 -0500 X-MC-Unique: b38hnEtcM3ikSYhhjSV9Ow-1 Received: by mail-wr1-f70.google.com with SMTP id d2so2990964wrr.5 for ; Thu, 07 Jan 2021 10:14:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=EevDkj3Eq5HGyjrzEGnkPKUnTQ5NdW9RJ/mZwCBu75Y=; b=WSNafYnJt4aYN1oHe4nG2agDBe5gcATK4ndaCqfmPmfLqKJ65ZGz7KxlnrIkCowAT5 smhuw+sMHUpOchCVlaGjr6tQ7atmDCYcCLoVM1nXfOYTFyZDLWlal4ZlFPE3rDxqC5Qi c41306+MZEH9dBIuZwi6eMd6lEkHjtH3TTuI0yGjauFEjbm1cxCfCzD055JLaEEfjEdD My2VJOQm7RCtbloFj0uPDCs8OCzCH+kAWOMEA4twG5BNdpHorYuPxv2dK8iXiUKIgSU7 uPY+PcUjbxesQ9oAKpqYBWuzxa4l2LNXeRCaGGKUcBW3F+lvz5ICTq4LJ0kPzTnR2dtl rgKA== X-Gm-Message-State: AOAM5336x8IkXlqLQ9F0aDCAl94L9NOikOVyXg8WfAKzIhUUjtasa3mM SMOpDR/1Bvm5HG5ZqQTjEEhgBVVWcw0LYKlOI9txjDCtmYBPbcC2/Jrfvl2Xm40TgEEDpSpNgbV JJEAunPFe15+r X-Received: by 2002:a05:600c:2158:: with SMTP id v24mr8820024wml.129.1610043243053; Thu, 07 Jan 2021 10:14:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJyhpi5EQI3kZgP/cpmJXqwFHJ3L6zWKQJljm7pzpymkuvBcgJozVZYoJQ4/jifD8uvWmmabeQ== X-Received: by 2002:a05:600c:2158:: with SMTP id v24mr8820009wml.129.1610043242830; Thu, 07 Jan 2021 10:14:02 -0800 (PST) Received: from ?IPv6:2001:b07:6468:f312:c8dd:75d4:99ab:290a? ([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id j10sm9513535wmj.7.2021.01.07.10.14.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jan 2021 10:14:01 -0800 (PST) Subject: Re: [PATCH v2] Docs/RCU: Correct sample code of qatomic_rcu_set To: Keqian Zhu , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi Cc: Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wanghaibin.wang@huawei.com, qemu-trivial@nongnu.org References: <20210106071710.15836-1-zhukeqian1@huawei.com> From: Paolo Bonzini Message-ID: <1fc6cbdb-8ae1-efa9-d294-f8412a77c6ce@redhat.com> Date: Thu, 7 Jan 2021 19:14:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20210106071710.15836-1-zhukeqian1@huawei.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.246, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.267, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 18:14:10 -0000 On 06/01/21 08:17, Keqian Zhu wrote: > Correct sample code to avoid confusing readers. > > Signed-off-by: Keqian Zhu > Cc: qemu-trivial@nongnu.org > Reviewed-by: Paolo Bonzini > Reviewed-by: Peter Xu > --- > > v2: > - Add Cc and R-b. > > --- > docs/devel/rcu.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/devel/rcu.txt b/docs/devel/rcu.txt > index cdf002edd8..2e6cc607a1 100644 > --- a/docs/devel/rcu.txt > +++ b/docs/devel/rcu.txt > @@ -392,7 +392,7 @@ Instead, we store the size of the array with the array itself: > > /* Removal phase. */ > old_array = global_array; > - qatomic_rcu_set(&new_array->data, new_array); > + qatomic_rcu_set(&global_array, new_array); > synchronize_rcu(); > > /* Reclamation phase. */ > Queued, thanks. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id y5sm7051097pgs.90.2021.01.07.11.13.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jan 2021 11:13:56 -0800 (PST) Subject: Re: [PATCH] target/arm: Fix sve pred_desc decoding To: Peter Maydell Cc: QEMU Developers , qemu-arm , qemu-stable References: <20201230172522.33629-1-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <97afe9a0-c5b1-8dfe-62a2-f3d0a1b55540@linaro.org> Date: Thu, 7 Jan 2021 09:13:53 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.267, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 19:14:00 -0000 On 1/7/21 8:02 AM, Peter Maydell wrote: >> void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) >> { >> - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; >> + intptr_t oprsz = extract32(pred_desc, 0, SIMD_DATA_SHIFT) + 2; > > Why do we not get oprsz by extracting SIMD_OPRSZ_BITS starting at > SIMD_OPRSZ_SHIFT ? (or even by calling simd_oprsz(), which > certainly looks like it ought to be a helper function for > extracting the oprsz...) The predicate operations are small -- minimum 2 bytes -- and cannot encode with the real simd_oprsz (minumum 8, then multiples of 16). This is shear abuse of the SIMD_* defines. You're right that I shouldn't have done this in the first place, and should probably rename everything having to do with predicates. r~ From MAILER-DAEMON Thu Jan 07 14:55:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxbNp-0006Gf-04 for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 14:55:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxbNn-0006GU-5e for qemu-arm@nongnu.org; Thu, 07 Jan 2021 14:55:43 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:46558) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxbNk-0002Iy-Aa for qemu-arm@nongnu.org; Thu, 07 Jan 2021 14:55:42 -0500 Received: by mail-ed1-x52a.google.com with SMTP id b73so8843596edf.13 for ; Thu, 07 Jan 2021 11:55:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; 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Thu, 07 Jan 2021 11:55:38 -0800 (PST) MIME-Version: 1.0 References: <7884934.NyiUUSuA9g@basile.remlab.net> <002743e6-10d3-88b3-961a-8571efb4d1ed@linaro.org> <9468010.vzF1F9XyNR@philogene> <1b14279c-f620-5c03-b25c-a52fa370cc8e@linaro.org> In-Reply-To: <1b14279c-f620-5c03-b25c-a52fa370cc8e@linaro.org> From: Peter Maydell Date: Thu, 7 Jan 2021 19:55:27 +0000 Message-ID: Subject: Re: [PATCH 1/3] target/arm: keep translation start level unsigned To: Richard Henderson Cc: =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= , qemu-arm , QEMU Developers , =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 19:55:43 -0000 On Thu, 31 Dec 2020 at 16:43, Richard Henderson wrote: > > On 12/31/20 1:59 AM, R=C3=A9mi Denis-Courmont wrote: > > Le jeudi 31 d=C3=A9cembre 2020, 00:38:14 EET Richard Henderson a =C3=A9= crit : > >> On 12/30/20 2:10 PM, Richard Henderson wrote: > >>> On 12/18/20 6:33 AM, remi.denis.courmont@huawei.com wrote: > >>>> From: R=C3=A9mi Denis-Courmont > >>>> > >>>> Signed-off-by: R=C3=A9mi Denis-Courmont > >>>> --- > >>>> > >>>> target/arm/helper.c | 14 ++++++-------- > >>>> 1 file changed, 6 insertions(+), 8 deletions(-) > >>> > >>> The patch does more than what is described above. > >>> > >>>> diff --git a/target/arm/helper.c b/target/arm/helper.c > >>>> index df195c314c..b927e53ab0 100644 > >>>> --- a/target/arm/helper.c > >>>> +++ b/target/arm/helper.c > >>>> > >>>> @@ -10821,17 +10821,12 @@ do_fault: > >>>> * Returns true if the suggested S2 translation parameters are OK a= nd > >>>> * false otherwise. > >>>> */ > >>>> > >>>> -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level= , > >>>> +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint32_t > >>>> level, > >>>> > >>>> int inputsize, int stride) > >>>> > >>>> { > >>>> > >>>> const int grainsize =3D stride + 3; > >>>> int startsizecheck; > >>>> > >>>> - /* Negative levels are never allowed. */ > >>>> - if (level < 0) { > >>>> - return false; > >>>> - } > >>>> - > >>> > >>> I would expect this to be the only hunk from the patch description. > >>> Probably changing this negative check to a >=3D 3 check. > >> > >> Having read the next patch, I think you should drop this type change. > >> > >>>> @@ -11203,7 +11201,7 @@ static bool get_phys_addr_lpae(CPUARMState *= env, > >>>> uint64_t address,>> > >>>> if (!aarch64 || stride =3D=3D 9) { > >>>> > >>>> /* AArch32 or 4KB pages */ > >>>> > >>>> - startlevel =3D 2 - sl0; > >>>> + startlevel =3D (2 - sl0) & 3; > >> > >> This hunk belongs with the next patch, implementing TTST, and should b= e > >> conditional. I.e. > >> > >> if (stride =3D=3D 9) { > >> startlevel =3D 2 - sl0; > >> if (aarch64 && > >> cpu_isar_feature(aa64_st, env_archcpu(env)) { > >> startlevel &=3D 3; > >> } > > > > You can do that but: > > 1) Nothing in the spec says that SL0 =3D=3D b11 without ST means start = level -1. > > It's undefined, and I don't see any reasons to treat it differently tha= n with > > ST. > > By that logic there's no reason to treat it differently at all; you could= drop > the feature check entirely. In lieu, -1 makes a decent error indicator. > > > 2) Functionally, checking for ST seems to belong naturally within > > check_s2_mmu_setup() in this particular case. > > I guess. I'll leave it to Peter's preference. You've reviewed the patchset, I'm happy to go with whatever your preference is (because I don't want to have to duplicate the review work to form an opinion). thanks -- PMM From MAILER-DAEMON Thu Jan 07 14:58:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxbQQ-0008Sk-Lk for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 14:58:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxbQO-0008Pq-Hi for qemu-arm@nongnu.org; Thu, 07 Jan 2021 14:58:24 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:45722) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxbQN-0003bo-4h for qemu-arm@nongnu.org; Thu, 07 Jan 2021 14:58:24 -0500 Received: by mail-pg1-x529.google.com with SMTP id v19so5672770pgj.12 for ; Thu, 07 Jan 2021 11:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=MsJKpkvAdQay/uAZyKckKdRqHA4VcbTbkpGrIBkZSVs=; b=xNT1vJO9LVtuC9+dsfsrSMTR4BVBklQDk+JY43KfAWu9eUU/gmSALPh00M/iNhyQm5 NVbiLwSHuzlhqQ/ZJzzkGWMLuHEI/sG3WbWi3ph9N3UOnWvdWoyvOEo5im0qYqwBU4GA EarOsI0y8xEBxn0KB3EGTruiHP1bU93WMDnmgnIp16H07IkeaTB8ZFXZXI0Nab4NsgWw tDkYPiXIJGpx1sLCugUI5tbLZoi9/2Sg1Ourkz9WHfDkzQB9uvAuuSJCd3Nl8qdSTgn6 ZMzL4gsuZ9yH6hpJr/MjrU+aB/BNDusRTURllT4eh9tXI7/nl8KVHivbO0ikRisuqMEY vygg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=MsJKpkvAdQay/uAZyKckKdRqHA4VcbTbkpGrIBkZSVs=; b=d1IqZhL2RemCyIiQ9p03X1BBR/a8GWUALdK+wQkEXQG75GRcbyw7iCo5uOFrwYjUJg 5bRY58H1IE3GRkHbbzVtgfUrMoWKZXly4W+07U6sDE+JHUAcX6w2+Z7nfM1naGJZ5bsy qX1EAqzZPWiNT4paV2FFV6Dj7w+Anqbu3Y2/q3HNOXrBTFMh9XSSHTqPjqWh2FxQR/RL mUQh8ADnKzV56XPwfzrO59QNRhD72gYSNV/piOdGlUH1poQIlJYeMVmOTi7j8eeE1DZ2 +TAsCAa0/C54Rl0cB4n1VpFTULMvuvizHm+Z53FFE/uzlSj0bkH86a0iiVtnZ8Y72fAH srIw== X-Gm-Message-State: AOAM53186BFSPkcAEePDdkC5qKo+JPsVHjT6gWp4XWlDfpqpVF7mHnsm UbwBnlYBAVFMDzce2G2yC8uceb5aG5JT+g== X-Google-Smtp-Source: ABdhPJyzrj7LPGBjKV3ESOMyOex+wxBHaAb6JVW3/6XoUENWGrLaWhg21gbPmv/J/hcvF4Oi5OkKgA== X-Received: by 2002:aa7:80d5:0:b029:1a3:832a:1fd0 with SMTP id a21-20020aa780d50000b02901a3832a1fd0mr310351pfn.6.1610049501390; Thu, 07 Jan 2021 11:58:21 -0800 (PST) Received: from [10.25.18.38] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id i2sm2991449pjd.21.2021.01.07.11.58.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jan 2021 11:58:20 -0800 (PST) Subject: Re: [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-3-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <6ea987c7-af0f-1428-5cda-0a53393a3838@linaro.org> Date: Thu, 7 Jan 2021 09:58:17 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.267, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 19:58:24 -0000 On 1/7/21 5:42 AM, Peter Maydell wrote: >> +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ >> +FIELD(TBFLAG_ANY, ALIGN_MEM, 19, 1) > > This is trying to use the same bit as TBFLAG_A64 MTE0_ACTIVE... > We might have to finally start in on using bits in cs_base. Oops. Didn't notice this as I extended from a32 to a64. And then of course didn't enable mte while testing alignment... I'll use cs_base in the next version, moving all of the target-specific bits there, leaving only TBFLAG_ANY_* in tb->flags. r~ From MAILER-DAEMON Thu Jan 07 15:01:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxbTR-00025F-Ue for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 15:01:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxbTB-00021r-6E for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:01:20 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:43442) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxbT4-0004b8-LV for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:01:13 -0500 Received: by mail-ej1-x62f.google.com with SMTP id jx16so11345923ejb.10 for ; Thu, 07 Jan 2021 12:01:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5xw3j+kjjmJJDjmlmsVhdRn/Wx0+xXxnfBFmqL2+YXA=; b=xfR6lIs5ZhLXs57eL2Nm+cD4fhjqRhlM/nUvD4T6GYFnrqWTHn4HbOtZhn3CAcwLM+ WpYWPGRILHJFAfbWIQbfXb9cisFxN9JXnUpaeTTeen2QWrhqzN/LYd4Uy0COcBaMmuAB xd1EWE+pEV4KVhvR2/7gHhW5lNL2TI1bSFzLlROHWibR1ZwrW0gWtJZyqkjiYWIGLnM2 rtljSwm5veCxuB+7ZWrqqvufdJRepVI2qN+99BYoRDWlwzELEOxbDW2zxIuTxw53IZpi DVUcERZaajOByokWXuz2aY6tDiUHPm490MZW5IgoqQkHJs0g2zV4fDMVNBGV+rFasfvb BVBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5xw3j+kjjmJJDjmlmsVhdRn/Wx0+xXxnfBFmqL2+YXA=; b=e+lWstOER813f+LBVlEq5UOAvaHN2NFLljBrYDAOiu1AhMRrSVX3ubOUW6ov2oDfrP vxiI2VWrfTVNGrcRR88XwIIvsIT3YJO4igegRApOMbS35xitC5xAgN/+m5Pn93yNFYGQ 4C4SdhDBss/oYPDRYrj+ZIjhUPBqEz9nsi22RjXvvPh5LEUEVYSXD58U35QR9YhxSK/O 3ItC6EJnCW2/tonSJglzYDoFGF1TYn1BZ7YCa622IJtguyRmn2Y8tvh+t++ykmavaA5P H3eAcAOxlFiJJdbSCZDpkCKiNhzJ4o1xGTXUMQ9qQhxkiVwewtL6AlYS8AM9JdFw1uTS kzfw== X-Gm-Message-State: AOAM532cRlr9p/WNtmUfjIh8Z8GZ0+m2Okrk5sZpBRJnaMAOBPVwftpC XkXLUfrWr1xDu9mZLiX87Xy3gYntLLoTD2TbuCChdg== X-Google-Smtp-Source: ABdhPJzxbyYFEhzF7xl57UKz8ngmE11AqCofnDd3ABJlBMSPcXEeKiLSiJiERBiigq/2V/RcNsG9zt5PbYZmb5BknWQ= X-Received: by 2002:a17:906:e94c:: with SMTP id jw12mr364752ejb.56.1610049668968; Thu, 07 Jan 2021 12:01:08 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Peter Maydell Date: Thu, 7 Jan 2021 20:00:57 +0000 Message-ID: Subject: Re: [PATCH] Initialize Zynq7000 UART clocks on reset To: Michael Peter Cc: "qemu-devel@nongnu.org" , qemu-arm , "Edgar E. Iglesias" , Alistair Francis , Damien Hedde Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 20:01:28 -0000 Alistair/Edgar/Damien -- could I get a review from one of you for this Xilinx clock-gen related patch, please? thanks -- PMM On Tue, 24 Nov 2020 at 18:54, Michael Peter wrote: > > Pass an additional argument to zynq_slcr_compute_clocks that indicates whether an reset-exit condition > applies. If called from zynq_slcr_reset_exit, external clocks are assumed to be active, even if the > device state indicates a reset state. > > Signed-off-by: Michael Peter > --- > hw/misc/zynq_slcr.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c > index a2b28019e3..073122b934 100644 > --- a/hw/misc/zynq_slcr.c > +++ b/hw/misc/zynq_slcr.c > @@ -269,12 +269,12 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], > * But do not propagate them further. Connected clocks > * will not receive any updates (See zynq_slcr_compute_clocks()) > */ > -static void zynq_slcr_compute_clocks(ZynqSLCRState *s) > +static void zynq_slcr_compute_clocks(ZynqSLCRState *s, bool ignore_reset) > { > uint64_t ps_clk = clock_get(s->ps_clk); > > /* consider outputs clocks are disabled while in reset */ > - if (device_is_in_reset(DEVICE(s))) { > + if (!ignore_reset && device_is_in_reset(DEVICE(s))) { > ps_clk = 0; > } > > @@ -305,7 +305,7 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) > static void zynq_slcr_ps_clk_callback(void *opaque) > { > ZynqSLCRState *s = (ZynqSLCRState *) opaque; > - zynq_slcr_compute_clocks(s); > + zynq_slcr_compute_clocks(s, false); > zynq_slcr_propagate_clocks(s); > } > > @@ -410,7 +410,7 @@ static void zynq_slcr_reset_hold(Object *obj) > ZynqSLCRState *s = ZYNQ_SLCR(obj); > > /* will disable all output clocks */ > - zynq_slcr_compute_clocks(s); > + zynq_slcr_compute_clocks(s, false); > zynq_slcr_propagate_clocks(s); > } > > @@ -419,7 +419,7 @@ static void zynq_slcr_reset_exit(Object *obj) > ZynqSLCRState *s = ZYNQ_SLCR(obj); > > /* will compute output clocks according to ps_clk and registers */ > - zynq_slcr_compute_clocks(s); > + zynq_slcr_compute_clocks(s, true); > zynq_slcr_propagate_clocks(s); > } > > @@ -558,7 +558,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, > case R_ARM_PLL_CTRL: > case R_DDR_PLL_CTRL: > case R_UART_CLK_CTRL: > - zynq_slcr_compute_clocks(s); > + zynq_slcr_compute_clocks(s, false); > zynq_slcr_propagate_clocks(s); > break; > } > -- > 2.17.1 From MAILER-DAEMON Thu Jan 07 15:38:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxc2l-0004uU-JO for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 15:38:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxc2j-0004qW-U8 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:38:01 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:37839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxc2h-0000Zg-Qy for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:38:01 -0500 Received: by mail-pf1-x432.google.com with SMTP id 11so4626734pfu.4 for ; Thu, 07 Jan 2021 12:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=mCnTY9YH3EC4LSSj4YJLFMo2b7CqxHLmm6hE4pJzs6s=; b=HFAG/mktg+NZj22C7bg0yAHn0Fr92NH9PA19yh8a2IrHwQAO4z+oF49iHZnZrxhfdh 1k9iIIKT97auX160LTFVhzX8ftSsM+AISeRrLc/puBLl5mRVwOMWz/CjnQxSBs9sTXOn OF+nF+JcgkrZo5VwWDtXOBUbFTaE11BhOfczY3eN1w/KTC9MMX/FN9CjURCcz+WBOkel HB4mdbVAWuWWbAMZALpnbsvKScy7Si1Bn0YPvLWskDg23nsg5M/nziqN+JFFuDaax66v uON/C5NMmhrbQunM98Mta4KOv61lupZ2fUj1IGcw3aHbTcpyDjTq0nN1GAaP1+Nro5ZR zndw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=mCnTY9YH3EC4LSSj4YJLFMo2b7CqxHLmm6hE4pJzs6s=; b=BG0CneKwOET+nBrh2Uxmo29+VdVHUtdTnsXSUVi/8jPDTaVLD8qT3f5P4c7UP3ATjm V7r4eLH9TwdvlwYjPkBP1+HNHH85kJN/isvTfew8qs+Y6tismrPhkoGu+s7pLogvlWiY Xoq79+pOpegOxuO6f3ZtffE6zO8JGDWZWYDGmVKHnDA+0gqKDamh0/8ojRz5NFkSCdGb u9p/8TMd+GOaB/S/L+sfDi3a6ZoqhJoLdf6DsB8JVNySbkkXr/2a90k8mvy4nzQPfSBD cAY+cRGd4h+dmsQIb14mcJqjTfiiR2YdMH3bikqRJmi4hdGMi1XtBeFge3EWCy3v4fgz 6S/g== X-Gm-Message-State: AOAM531KMaGUYVX3Mbwygv6noazZd9gRcwg85cuvw4ioasXNeyTTd2Us sgs2w1/SWG/158HZDwsQT1d/KZqErl+y0Q== X-Google-Smtp-Source: ABdhPJz5/m977NotorsSUrgJqAf85gHCxSRKQAvZJlL/3Yab1qXVbSInzhTbdzbJ9O9nnXPTVsIBkQ== X-Received: by 2002:a63:f64c:: with SMTP id u12mr3600240pgj.98.1610051878136; Thu, 07 Jan 2021 12:37:58 -0800 (PST) Received: from [10.25.18.38] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id w19sm6951773pgf.23.2021.01.07.12.37.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jan 2021 12:37:57 -0800 (PST) Subject: Re: [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-6-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Thu, 7 Jan 2021 10:37:54 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.267, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 20:38:02 -0000 On 1/7/21 6:00 AM, Peter Maydell wrote: > On Tue, 8 Dec 2020 at 18:01, Richard Henderson > wrote: >> >> Just because operating on a TCGv_i64 temporary does not >> mean that we're performing a 64-bit operation. Restrict >> the frobbing to actual 64-bit operations. > > If I understand correctly, this patch isn't actually a behaviour > change because at this point the only users of gen_aa32_ld_i64() > and gen_aa32_st_i64() are in fact performing 64-bit operations > so the (opc & MO_SIZE) == MO_64 test is always true. Correct. > (Presumably > subsequent patches are going to add uses of these functions that > want to load smaller sizes?) Correct. > If that's right, worth mentioning > explicitly in the commit message, I think. Will do. r~ From MAILER-DAEMON Thu Jan 07 15:39:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxc4Y-0007iB-GS for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 15:39:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxc4P-0007gC-KF for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:39:49 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:37622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxc4M-00019d-FV for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:39:45 -0500 Received: by mail-ed1-x529.google.com with SMTP id cm17so9059864edb.4 for ; Thu, 07 Jan 2021 12:39:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0tOad4p4g9xxCxz+2A1NsHx49ZOrVhPXaqsHUq1scno=; b=aZcqVUW2PFjQgWmUQwjQiWKLnei/9GaTYb5HZ4bAiLsjR5RpkW/dpLJM31yw+Dj+nJ Qa6fajhBBQN05E90wGwkFIEclx4FuLhPOK7F+z6BEfo96dm1sbUynRV7svHZTy1l/MhK QCWCIv6fwrmn3ikyVSFyvzQEIEhZsjJDnA7vmhUsG+DUcEOCzQK0bhS+79TngaoxZoRC nOX0om1zzsHRGGk7Bo81IoIyIVLnaUSkuAwN1A6NuwkypXWfLQPv8/6xVYWxA7DptxwU 82Y6ytBusGyTmx/DijWQjMrdJJgykweg4KK0uZSrH7hE0LGOk6BKYrtD6zyqV0ECJ2vc iiQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0tOad4p4g9xxCxz+2A1NsHx49ZOrVhPXaqsHUq1scno=; b=H913zri5/5pj8SVrLCw5Lq87lhnHhgCv85g9islUjeFD0gySr5F5odsWzU6xQ+8kxB 3Xjb9vWTMcI8MyquYpaR2z+zkeEatAbt8iYcwTIDQqdeMDT496CSjT0/LKrLxb9gOAxR OHdX6jtt3knuX80DoKee8mwbNk0zh0fhrzIrYsNSG7E+UIhWV5v/q7nTAt+Ak89zsU3x bOFEl369tO/RnAkArFSc9Mw7bBJ02sBdf5zbj1ECxRKcyGfB+BoZTkxKCQap4rukIH6r ZfTkgzocpzyIIfC+fZlWtfTWpNzA/CpaaPkt2ThDgwi2I7HjD/QccFn4bZeJ88JnXaHs ea7A== X-Gm-Message-State: AOAM5323yh3YNMCHHWZLtroDKPCfB9Yh57gdvc+U6wWnd1Y8hc6dq/+l UZYBYbu5xyUYZkyd0Aoo4ehPJS/jHslYxK+jO6Gr0w== X-Google-Smtp-Source: ABdhPJwmDq14EHxkFhJkH+usdywR800KsfwOkyhanHW3r8SbQQb49/H3oD+3RcJZS/r5xAa8tZ1te87WDBagEJT5v/4= X-Received: by 2002:aa7:c353:: with SMTP id j19mr2960208edr.204.1610051979194; Thu, 07 Jan 2021 12:39:39 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-2-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-2-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 7 Jan 2021 20:39:28 +0000 Message-ID: Subject: Re: [PATCH v4 1/6] hw/misc: Add clock converter in NPCM7XX CLK module To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 20:39:49 -0000 On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > This patch allows NPCM7XX CLK module to compute clocks that are used by > other NPCM7XX modules. > > Add a new struct NPCM7xxClockConverterState which represents a > single converter. Each clock converter in CLK module represents one > converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter > takes one or more input clocks and converts them into one output clock. > They form a clock hierarchy in the CLK module and are responsible for > outputing clocks for various other modules in an NPCM7XX SoC. > > Each converter has a function pointer called "convert" which represents > the unique logic for that converter. > > The clock contains two initialization information: ConverterInitInfo and > ConverterConnectionInfo. They represent the vertices and edges in the > clock diagram respectively. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 15:51:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxcG5-00054O-5O for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 15:51:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxcG3-00050B-8d for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:51:47 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:45352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxcG1-00053s-06 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 15:51:47 -0500 Received: by mail-ej1-x62a.google.com with SMTP id qw4so11501589ejb.12 for ; Thu, 07 Jan 2021 12:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Gqi24Ai0MHhPoFwoMyHu9fKaAXLmhYyMzu9GXm1LsrM=; b=NjO57jFTI9+HM4g6sWEwJzQhjaD66Jd0feXVPmgziRSukdgI3JdsR+NR4mPMsqjkJ2 KZbMjvU+LB+MlP96cNzQN1gVF85tz1wXv4TGVArPrjDK0QfjhLF/Owlo9XTvo4kqvyB5 AFDlORPoemfXplrPyV/JilgYYyPWYac5AlZJyAaHkp3o9eK5cp3mDnmCmxLHRLsCgGry aLnc8UkU7OjARUnwd2GX8+ElIuwf6MEVCSr/xO8XzYHLh/ncG/iwAFmMLa/cI8CI7tw0 nCbBlrEIM9JUaiiJM+OkBblPGmuKT+ZbQE8IUtHSilIMo84ovSbAMl/0fIEUXhKAvsEB UoDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Gqi24Ai0MHhPoFwoMyHu9fKaAXLmhYyMzu9GXm1LsrM=; b=GLYjFi2exhHCvKuULhAWL2u69COQGsSBJRZmcoRRR0h2L1Wd2JiLZTHYLfqQeI6Ydp BNb4cw9N2v7hoGkjCBTzDm51yIPATUmRGT7c9Cm1XfPADwWrju2BcGMASbS6LNgzNjlm l3R2A5OggPjg/AgzSWDngQpqzX2E5S03+1jU6+BzdZuxWJ6WdQm5AAQ7aU3qbCSpkYcH LCbljk9M687IElHoJYmGglTkCOnleSMl644hjSqW3Yu2g5eWKXV15hc4cnuXJApaDGvL NDL6I46e1aRHORcAB7xQ73ZBN8HOLHEZeRyqzLRBwGzlGFgpMLTtpFMcywrR5Z4tWSG7 7yrw== X-Gm-Message-State: AOAM532l/XCK+cD2fdMGHmg2FKMK2/k0WAvGLFLdwBfQxEXcEcc9IxvJ nfQQv0012ANGrYOk4Z+7asjXUMfFrw1PN0zA24MZeA== X-Google-Smtp-Source: ABdhPJz28f09I3L+W6JJqpAaay2G29A3rVQh3AiQNv0lOQzACY9IsoulTpdVknPGVr+tjeAfdS/IQCaJ7iyAXGWkJe4= X-Received: by 2002:a17:906:6b88:: with SMTP id l8mr468767ejr.482.1610052702610; Thu, 07 Jan 2021 12:51:42 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-3-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-3-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 7 Jan 2021 20:51:31 +0000 Message-ID: Subject: Re: [PATCH v4 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 20:51:47 -0000 On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > This patch makes NPCM7XX Timer to use a the timer clock generated by the > CLK module instead of the magic number TIMER_REF_HZ. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu > --- > hw/arm/npcm7xx.c | 5 +++++ > hw/timer/npcm7xx_timer.c | 25 ++++++++++++++----------- > include/hw/misc/npcm7xx_clk.h | 6 ------ > include/hw/timer/npcm7xx_timer.h | 1 + > 4 files changed, 20 insertions(+), 17 deletions(-) > @@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) > { > int64_t ns = count; > > - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; > + ns *= clock_get_ns(t->ctrl->clock); > ns *= npcm7xx_tcsr_prescaler(t->tcsr); I'm afraid that since you wrote and sent this we've updated the clock API (in commits 554d523785ef868 and de6a65f11d7e5a2a93f), so clock_get_ns() doesn't exist any more. Instead there is a new function clock_ticks_to_ns(). The idea of the new function is that clocks don't necessarily have a period which is a whole number of nanoseconds, so doing arithmetic on the return value from clock_get_ns() introduces rounding errors, especially in the case of "multiply clock_get_ns() by a tick count to get a duration". (The worst case for this is "clock frequency >1GHz", at which point the rounding means that clock_get_ns() returns 0...) There is as yet no function for "convert duration to tick count", so code like: count = ns / clock_get_ns(t->ctrl->clock); should probably for the moment call clock_ticks_to_ns() passing a tick count of 1. But I plan to write a patchset soon which will avoid the need to do that. Strictly speaking, even "call clock_ticks_to_ns() and then multiply by the prescaler value" can introduce rounding error; to deal with that I think you'd need to either have an internal Clock object whose period you adjusted as the prescalar value was updated by the guest, or else do arithmetic with the return value of clock_get() (which is in units of 2^-32 ns); I'm not sure either is worth it. thanks -- PMM From MAILER-DAEMON Thu Jan 07 16:07:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxcVD-0004ZC-UG for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 16:07:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxcVB-0004Wo-S6 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:07:26 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:35640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxcV5-0002bS-PP for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:07:25 -0500 Received: by mail-ej1-x62b.google.com with SMTP id q22so11719348eja.2 for ; Thu, 07 Jan 2021 13:07:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nML7IqxwblApEN2NnbFGVwk0803/EiwYLNm+/Bxj8F4=; b=JYCRX0i+1V2HMySwUXaOGorxzp6Z76lVMqQSgGzV4Y4eJPG+eFtHRwzM170F4VUp6q kaM858ElI1B/vAq5qNxzwhA1lxQykDQr7kotiRFbO4G5MvT0qmgacBXwDl2SG1ykqQur 2WB1TEWOPhhNquKOJzgb6MR1BnRCO1kkr24vc1Ntesrk32il/V4ktsSsYXa8roiTOksb DH3qatHpv5BkQbopOKzWAkLb8TXugFBQevpF2ZyCYDZrMedR1gPzy5WdbRazwSXK3MNM ayOZCP0uV3Q3Gh7EmRKh3w1R/HlZvhsIxhqk920hB8I9eCgOFHNtzAYur0T3KVkbKUxz yT7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nML7IqxwblApEN2NnbFGVwk0803/EiwYLNm+/Bxj8F4=; b=Vd7gNKc3lXEv3lWiQRd6+/3jNxrbrKWsA/IaSDXpx5Tx++2SLrM4H7JKgjqTOxngOp QtMV+YigZ7B/qLcBWgzWHII+8Sg3O3KAWHeJ4GBmKkedGmBeoeoW+wz0t9yhSVIN4WSb itUxjX/bSN7vuFgF4iX6Yz7QVX+RitkrEk9wdH9BB1fh7hLpow6fKsOd1T5C8vtrRkRQ kanxys4V2urs+lt/p2pXhLnZld71594+Zt/tGg+meRB6yOvEy8Nbduf+RyutRjKa1rir 2CYTQ74uKp6ZutnLGXuaiLVep3rAN+aJy8WNdKrOWxDioXLYq5EFPsA3Vej8wjgO2tDY etvA== X-Gm-Message-State: AOAM531613jAS3TW85s1/CRbwLkWXAuVj3iId0/v3khTbDvATTXu6Lsw qb2O+eg4W7gCUkomXwNZ4bYwbanOnIAx0hdHwaYf4A== X-Google-Smtp-Source: ABdhPJyIj/TeLhEcBuKFC0MNLiZLNmiiJYcKYT9NSa6/bQTIQl72BVwwZDqWUqFTVfV/iio6WDbuTS7k6Iq5kNulnXM= X-Received: by 2002:a17:906:1151:: with SMTP id i17mr527842eja.250.1610053637978; Thu, 07 Jan 2021 13:07:17 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-4-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-4-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 7 Jan 2021 21:07:06 +0000 Message-ID: Subject: Re: [PATCH v4 3/6] hw/adc: Add an ADC module for NPCM7XX To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 21:07:26 -0000 On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > The ADC is part of NPCM7XX Module. Its behavior is controled by the > ADC_CON register. It converts one of the eight analog inputs into a > digital input and stores it in the ADC_DATA register when enabled. > > Users can alter input value by using qom-set QMP command. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu > --- > docs/system/arm/nuvoton.rst | 2 +- > hw/adc/meson.build | 1 + > hw/adc/npcm7xx_adc.c | 321 ++++++++++++++++++++++++++ > hw/adc/trace-events | 5 + > hw/arm/npcm7xx.c | 24 +- > include/hw/adc/npcm7xx_adc.h | 72 ++++++ > include/hw/arm/npcm7xx.h | 2 + > meson.build | 1 + > tests/qtest/meson.build | 3 +- > tests/qtest/npcm7xx_adc-test.c | 400 +++++++++++++++++++++++++++++++++ > 10 files changed, 828 insertions(+), 3 deletions(-) > create mode 100644 hw/adc/npcm7xx_adc.c > create mode 100644 hw/adc/trace-events > create mode 100644 include/hw/adc/npcm7xx_adc.h > create mode 100644 tests/qtest/npcm7xx_adc-test.c > > diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst > index b00d405d52..35829f8d0b 100644 > --- a/docs/system/arm/nuvoton.rst > +++ b/docs/system/arm/nuvoton.rst > @@ -41,6 +41,7 @@ Supported devices > * Random Number Generator (RNG) > * USB host (USBH) > * GPIO controller > + * Analog to Digital Converter (ADC) > > Missing devices > --------------- > @@ -58,7 +59,6 @@ Missing devices > * USB device (USBD) > * SMBus controller (SMBF) > * Peripheral SPI controller (PSPI) > - * Analog to Digital Converter (ADC) > * SD/MMC host > * PECI interface > * Pulse Width Modulation (PWM) > diff --git a/hw/adc/meson.build b/hw/adc/meson.build > index 0d62ae96ae..6ddee23813 100644 > --- a/hw/adc/meson.build > +++ b/hw/adc/meson.build > @@ -1 +1,2 @@ > softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) > +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) > diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c > new file mode 100644 > index 0000000000..f213b6a6df > --- /dev/null > +++ b/hw/adc/npcm7xx_adc.c > @@ -0,0 +1,321 @@ > +/* > + * Nuvoton NPCM7xx ADC Module > + * > + * Copyright 2020 Google LLC > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "hw/adc/npcm7xx_adc.h" First #include in every .c file must always be "qemu/osdep.h" (and .h files never include osdep.h). > +#include "hw/qdev-clock.h" > +#include "hw/qdev-properties.h" > +#include "migration/vmstate.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "qemu/timer.h" > +#include "qemu/units.h" > +#include "trace.h" > + > +/* 32-bit register indices. */ > +enum NPCM7xxADCRegisters { > + NPCM7XX_ADC_CON, > + NPCM7XX_ADC_DATA, > + NPCM7XX_ADC_REGS_END, > +}; > + > +/* Register field definitions. */ > +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) > +#define NPCM7XX_ADC_CON_INT_EN BIT(21) > +#define NPCM7XX_ADC_CON_REFSEL BIT(19) > +#define NPCM7XX_ADC_CON_INT BIT(18) > +#define NPCM7XX_ADC_CON_EN BIT(17) > +#define NPCM7XX_ADC_CON_RST BIT(16) > +#define NPCM7XX_ADC_CON_CONV BIT(14) > +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) > + > +#define NPCM7XX_ADC_MAX_RESULT 1023 > +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 > +#define NPCM7XX_ADC_CONV_CYCLES 20 > +#define NPCM7XX_ADC_RESET_CYCLES 10 > +#define NPCM7XX_ADC_R0_INPUT 500000 > +#define NPCM7XX_ADC_R1_INPUT 1500000 > + > +static void npcm7xx_adc_reset(NPCM7xxADCState *s) > +{ > + timer_del(&s->conv_timer); > + timer_del(&s->reset_timer); > + s->con = 0x000c0001; > + s->data = 0x00000000; > +} > + > +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) > +{ > + uint32_t result; > + > + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; > + if (result > NPCM7XX_ADC_MAX_RESULT) { > + result = NPCM7XX_ADC_MAX_RESULT; > + } > + > + return result; > +} > + > +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) > +{ > + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); > +} > + > +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, > + uint32_t cycles, uint32_t prescaler) > +{ > + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + int64_t freq = clock_get_hz(clk); > + int64_t ns; > + > + ns = (NANOSECONDS_PER_SECOND * cycles * prescaler / freq); Don't calculate time-in-nanoseconds via clock_get_hz(), please. Use (the new) clock_ticks_to_ns(). > + ns += now; > + timer_mod(timer, ns); > +} > + > +static void npcm7xx_adc_start_reset(NPCM7xxADCState *s) > +{ > + uint32_t prescaler = npcm7xx_adc_prescaler(s); > + > + npcm7xx_adc_start_timer(s->clock, &s->reset_timer, NPCM7XX_ADC_RESET_CYCLES, > + prescaler); > +} > + > +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) > +{ > + uint32_t prescaler = npcm7xx_adc_prescaler(s); > + > + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, > + prescaler); > +} > + > +static void npcm7xx_adc_reset_done(void *opaque) > +{ > + NPCM7xxADCState *s = opaque; > + > + npcm7xx_adc_reset(s); > +} > + > +static void npcm7xx_adc_convert_done(void *opaque) > +{ > + NPCM7xxADCState *s = opaque; > + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); > + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) > + ? s->iref : s->vref; > + > + g_assert(input < NPCM7XX_ADC_NUM_INPUTS); It looks to me given that the CON_MUX field is 4 bits and NUM_INPUTS is only 8 that the guest can trigger this assert if it writes a bogus value to the register. You should do something other than asserting in this situation (eg you can log a guest error and do nothing, or if you happen to know what the h/w does in this case that's the best thing). > + s->data = npcm7xx_adc_convert(s->adci[input], ref); > + if (s->con & NPCM7XX_ADC_CON_INT_EN) { > + s->con |= NPCM7XX_ADC_CON_INT; > + qemu_irq_raise(s->irq); > + } > + s->con &= ~NPCM7XX_ADC_CON_CONV; > +} > + > +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) > +{ > + adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, > + adc->iref); > + adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, > + adc->iref); > +} > + > +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) > +{ > + uint32_t old_con = s->con; > + > + /* Write ADC_INT to 1 to clear it */ > + if (new_con & NPCM7XX_ADC_CON_INT) { > + new_con &= ~NPCM7XX_ADC_CON_INT; > + } else if (old_con & NPCM7XX_ADC_CON_INT) { > + new_con |= NPCM7XX_ADC_CON_INT; > + } > + > + s->con = new_con; > + > + if (s->con & NPCM7XX_ADC_CON_RST) { > + if (!(old_con & NPCM7XX_ADC_CON_RST)) { > + npcm7xx_adc_start_reset(s); > + } > + } else { > + timer_del(&s->reset_timer); > + } Emulating "this device really takes X length of time to complete a guest-requested reset" is usually a higher degree of fidelity than we bother to model. I assume that some guest software can't cope with the device resetting faster than advertised ? > + if ((s->con & NPCM7XX_ADC_CON_EN)) { > + if (s->con & NPCM7XX_ADC_CON_CONV) { > + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { > + npcm7xx_adc_start_convert(s); > + } > + } else { > + timer_del(&s->conv_timer); > + } > + } > +} > + > +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size) > +{ > + uint64_t value = 0; > + NPCM7xxADCState *s = opaque; > + hwaddr reg = offset / sizeof(uint32_t); If you defined your register offsets with the REG32() macro in include/hw/registerfields.h then it would define A_FOO constants for you which are at the byte offsets of the 32-bit registers, and you could avoid converting the offset by dividing by 4 here. This isn't an obligatory change, but I think it ends up neater code. > diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h > new file mode 100644 > index 0000000000..7f9acbeaa1 > --- /dev/null > +++ b/include/hw/adc/npcm7xx_adc.h > @@ -0,0 +1,72 @@ > +/* > + * Nuvoton NPCM7xx ADC Module > + * > + * Copyright 2020 Google LLC > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > +#ifndef NPCM7XX_ADC_H > +#define NPCM7XX_ADC_H > + > +#include "qemu/osdep.h" .h files never include osdep.h (because the .c files always do). thanks -- PMM From MAILER-DAEMON Thu Jan 07 16:08:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxcWF-0005U9-TD for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 16:08:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxcWE-0005SW-9x for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:08:30 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:43169) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxcW8-00034a-Gx for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:08:30 -0500 Received: by mail-ed1-x534.google.com with SMTP id y24so9069964edt.10 for ; Thu, 07 Jan 2021 13:08:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zMl9HB+CoeXivwtGRa00mnivVk8GGwQAiI6UYMzRyho=; b=cXMp+Cy/JMgy9H01KiWx4ox09DK+ha8i9819ixe4IZnC1PIkjqlm7z+s7i3uUOsc3R WP5AG5FRVIWqK2cODy6n8fjXpkXkUGHLiiQzEsMuTPhfwgQk8QbQBYNRi99ZJYtSW+af QLFHah2y/ygnez4HR/zBEKC6aVCu9EBHvMFHN0M0wfySdAPIwGhuKaYfkFjgTYRP+GOZ bNrGKosxEPhfeFDj/ZvP+TY8nxsEI1cEFozxoKkEJWTzhfI9eg0zXT7lkcW3Gyw4buyd 2thOqB+UVgjMu4E76tSvk3VfSSENlyIwLBjog+z64ko9lULsEFqyR7oOyFvRbv+5WInS N7Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zMl9HB+CoeXivwtGRa00mnivVk8GGwQAiI6UYMzRyho=; b=bRqb7akbEfwH92g/j11t9kSOpMnoEqLWQIrisuPzu+6NDxqm8yMEwR5c5jlmS07OYi vtSu7qvCeYqcgCT1zP8fT2e34cShIEnBA7d6sAdsPdMWHxH8Jt2Xcdorddays+3BpCzz nJmGKDxxl9pTNLo9FYOOcL8HjHDLQ1i9Q87izt+KnFKYgS+ZlNTX8lDOaf/WsXn6hokz dohrb5LO4tHJIPmwGErnd5h4YGYpVhvsqvai0D3byle5BVHW9qenonteDQyvDkGoVdKM NnLTeXFerkTt4HR64KjmeWKOdjflZa2BDiDMkLsGWTl/51sUuLBZrZZv/s8BTBe5ZkeT Vz5w== X-Gm-Message-State: AOAM532A8VKrhjHmiNjJFuCbPWzabwT7greki5+hOpQutypX8ucMT77M 4aYVIxukcWu03i/dpKeuk3URy+nTOy8ZCnocNtGaVw== X-Google-Smtp-Source: ABdhPJz0z+v0gdhv3jktfNkT9wNFyLLzwqM6FJQGE0im0+EEEA4XwJ1oUJRrAdPwh2QHh8Yp9MWII6s9o5vALx6kyKg= X-Received: by 2002:aa7:d915:: with SMTP id a21mr2971927edr.251.1610053703000; Thu, 07 Jan 2021 13:08:23 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-7-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-7-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 7 Jan 2021 21:08:11 +0000 Message-ID: Subject: Re: [PATCH v4 6/6] hw/*: Use type casting for SysBusDevice in NPCM7XX To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 21:08:30 -0000 On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > A device shouldn't access its parent object which is QOM internal. > Instead it should use type cast for this purporse. This patch fixes this > issue for all NPCM7XX Devices. > > Signed-off-by: Hao Wu Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 16:10:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxcY6-0006mX-Mn for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 16:10:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxcY4-0006kQ-Kt for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:10:24 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:46969) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxcY0-0003aW-Cx for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:10:24 -0500 Received: by mail-ed1-x532.google.com with SMTP id v26so150852eds.13 for ; Thu, 07 Jan 2021 13:10:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OMeoWbothf8/Ef4qD/ayPFIJQJ3UmD5fLaQFggFJsRo=; b=ymGFm+GaGxKYWGRArnBN2pHrJhiGfw7CJMMQGaA5dKFC/it7n5NgVkAdpj8FIWPsxO HmgtT104eDKYEP2hcfFCqQXQhmDeDvJDlCkFQOWTcR1a/GR68Mt/V6tNxEVaeHMaRwdB AR5ADhy23e5A7b827v/2bkMOGhqnSWwurKrNFQGifcaRTePcCMTVAWcIYgDA+cIhU14Q km0JC9zPwgtwzeCG+IKXfuB/d3h8bn54tOjWo2Z0q8DxJz5RHVq3dhlzUoniYlZQl9lk UDc+33Vb2/A1ZTlTvqAHvhBhadtIi8kIw+mijR2JODBa+RUqB7dp3CYGFnxL/gQSHrQh VJsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OMeoWbothf8/Ef4qD/ayPFIJQJ3UmD5fLaQFggFJsRo=; b=Dh10hfNatN0HgDgMOuoI36TBXt9BlWuq5ify7gmLHG7c0ICA7rzbrztkZrHH72+i52 nJmlIqEzvwD1oer0V2guZxxLoPSC1W4V/7xbnki1tm7aPQJWYVtCe+dW+4im7lQxdbdF 6w4P7sJNqJVtJ0qBuwLwgukAVYTUTb8gPZM4bkytnajeS/ms8CrKI0/piMToO9tIZZo9 u+Fjy700dD5Dzu2Gsv4ixN9K4QrLsPmgeqfOrdybAJMvRkD5eYCYZP211KWhMrOmP/d+ PtPP71Mt4LpID0H0AM7PDx9nGk7ZOUE2qGEEI1LObHmHU5eSni5QQHYTswTxxwKbXBpS IR2w== X-Gm-Message-State: AOAM530gJc63s+/wWeQaryfFvtAYOpEhIDFRuyb/GYWb6/4QFj44FC5g j9K5HPFS0VJGqDbwHWSzBC7U+fqBdMpeAY1KUf3kxg== X-Google-Smtp-Source: ABdhPJxQBfXSL0HvSUCf2ZW0OZD9LRI8wRUDyxvCbyj/UdSR8P3y93fwrawS5BkcAqtjimHAHb/oiMbxfTj8pRsyaAQ= X-Received: by 2002:a05:6402:1383:: with SMTP id b3mr2951085edv.100.1610053818967; Thu, 07 Jan 2021 13:10:18 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-6-wuhaotsh@google.com> In-Reply-To: <20201217004349.3740927-6-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 7 Jan 2021 21:10:07 +0000 Message-ID: Subject: Re: [PATCH v4 5/6] hw/misc: Add QTest for NPCM7XX PWM Module To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 21:10:24 -0000 On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > We add a qtest for the PWM in the previous patch. It proves it works as > expected. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 07 16:43:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxd3x-0001l3-SE for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 16:43:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxd3w-0001k2-57 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:43:20 -0500 Received: from mail-lf1-x12a.google.com ([2a00:1450:4864:20::12a]:44658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxd3t-0006lk-JW for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:43:19 -0500 Received: by mail-lf1-x12a.google.com with SMTP id m25so18003783lfc.11 for ; Thu, 07 Jan 2021 13:43:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1JT21Ksn1nsFZ4DghxP3AoXJYW1SnYHBOVRlgQU7MUM=; b=Km/BQSKuzBOZTlgvydjgbBUwESiai4bRFItpsb5P+IntSnyZOVXE8epw97J1p2Or/l ybjToe+IoZL0eRt9YEBDDFbYw99aRnPOFnsOnX32KwQpoOjM+P1gdlG6rZMxYUD94jzW Kco5U3yuuPpz5Ky0fzEFkTFmGpHvUAdNnEvWzXgSJlj+xzz5V0cX8iEcJYkTqdL98zc3 7xIwJUSW9jCfiD/6mW4Xhuw2NvuemLpq7Asr/ArQp2lWKSmKet1PJk8yQ1dT/SDZ7xpN +S4mgEBPgWzN/hP1CsB9DvUjOPw6rQPC07xMaCb/XXgbk+MaUx89OUnmM5tNveZneQNd CWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1JT21Ksn1nsFZ4DghxP3AoXJYW1SnYHBOVRlgQU7MUM=; b=iak933GBtO51l1hQZP3pQBW2sP11uL1z1dkcGrSDT2xeLA+HjwZXaujnsB9Xgv18dS 8xYjibA98IwPPm5OjGKaArD6W17tGtJShxEIE6CqTxzy311456EPTM82wQiSl4NU8p5J Hm9XUav/ZBd6LXKUk0pDegX8wPhegg+xBmaBUDUdT8wgCquvYhj9FFLHQqfbt0WdhwEk umb9q64rPaFbgRyLmEGIFXbTDuafy0EEj8Llb+BssGste35bHPVN+kKfoS40cfngawtm oEOG23wt0bBF1tIw/r/uCiVgf4DOk/DM+wH2BQM3BF8r39M1k2UUeLqsxue/x2KKzHgD 8X7Q== X-Gm-Message-State: AOAM530EB/l1C81ws5I5M5KoqVR/GacFHQsrjp5tLim7uqQR5YGrW3H7 5AwE8wJxGAeyLzbKC9RFgsIdxG4WTR0eo2LWsK5/rA== X-Google-Smtp-Source: ABdhPJxbpB/RpjdIFsK3ti7hL7kr7EQvwVDSedISrMiUYm4gf53gA4/lbU12QPzM6ND0LRhQ7MzW27tRsGwfbmcS3cI= X-Received: by 2002:a05:651c:217:: with SMTP id y23mr175289ljn.247.1610055792309; Thu, 07 Jan 2021 13:43:12 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-3-wuhaotsh@google.com> In-Reply-To: From: Hao Wu Date: Thu, 7 Jan 2021 13:43:01 -0800 Message-ID: Subject: Re: [PATCH v4 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock To: Peter Maydell Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000924a2905b8565325" Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -179 X-Spam_score: -18.0 X-Spam_bar: ------------------ X-Spam_report: (-18.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.382, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 21:43:20 -0000 --000000000000924a2905b8565325 Content-Type: text/plain; charset="UTF-8" On Thu, Jan 7, 2021 at 12:51 PM Peter Maydell wrote: > On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > > > This patch makes NPCM7XX Timer to use a the timer clock generated by the > > CLK module instead of the magic number TIMER_REF_HZ. > > > > Reviewed-by: Havard Skinnemoen > > Reviewed-by: Tyrone Ting > > Signed-off-by: Hao Wu > > --- > > hw/arm/npcm7xx.c | 5 +++++ > > hw/timer/npcm7xx_timer.c | 25 ++++++++++++++----------- > > include/hw/misc/npcm7xx_clk.h | 6 ------ > > include/hw/timer/npcm7xx_timer.h | 1 + > > 4 files changed, 20 insertions(+), 17 deletions(-) > > > @@ -130,7 +130,7 @@ static int64_t > npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) > > { > > int64_t ns = count; > > > > - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; > > + ns *= clock_get_ns(t->ctrl->clock); > > ns *= npcm7xx_tcsr_prescaler(t->tcsr); > > I'm afraid that since you wrote and sent this we've updated the > clock API (in commits 554d523785ef868 and de6a65f11d7e5a2a93f), > so clock_get_ns() doesn't exist any more. Instead there is > a new function clock_ticks_to_ns(). > > The idea of the new function is that clocks don't necessarily > have a period which is a whole number of nanoseconds, so > doing arithmetic on the return value from clock_get_ns() > introduces rounding errors, especially in the case of > "multiply clock_get_ns() by a tick count to get a duration". > (The worst case for this is "clock frequency >1GHz", at which > point the rounding means that clock_get_ns() returns 0...) > > There is as yet no function for "convert duration to > tick count", so code like: > count = ns / clock_get_ns(t->ctrl->clock); > > should probably for the moment call clock_ticks_to_ns() > passing a tick count of 1. But I plan to write a patchset > soon which will avoid the need to do that. > > Strictly speaking, even "call clock_ticks_to_ns() and > then multiply by the prescaler value" can introduce > rounding error; to deal with that I think you'd need to > either have an internal Clock object whose period you > adjusted as the prescalar value was updated by the guest, > or else do arithmetic with the return value of clock_get() > (which is in units of 2^-32 ns); I'm not sure either is > worth it. > In this particular case, rounding error is less of a concern since the clock should be ~25MHz (in the old implementation it was a fixed value.) Since the prescaler is always an integer, a possible alternative might be ns = clock_ticks_to_ns(t->ctrl->clock, count * npcm7xx_tcsr_prescaler(t->tcsr)) and for code to convert ns to count can go count = ns / clock_ticks_to_ns(t->ctrl->clock, npcm7xx_tcsr_prescaler(t->tcsr)) or use the new API you proposed. We'll also need to apply similar changes to other places in the patchset (ADC and/or PWM) that need to compute clock value. > > thanks > -- PMM > --000000000000924a2905b8565325 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Thu, Jan 7, 2021 at 12:51 PM Peter May= dell <peter.maydell@linaro.o= rg> wrote:
wuhaotsh@google.com> wrote:
>
> This patch makes NPCM7XX Timer to use a the timer clock generated by t= he
> CLK module instead of the magic number TIMER_REF_HZ.
>
> Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> ---
>=C2=A0 hw/arm/npcm7xx.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0|=C2=A0 5 +++++
>=C2=A0 hw/timer/npcm7xx_timer.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 25 += +++++++++++++-----------
>=C2=A0 include/hw/misc/npcm7xx_clk.h=C2=A0 =C2=A0 |=C2=A0 6 ------
>=C2=A0 include/hw/timer/npcm7xx_timer.h |=C2=A0 1 +
>=C2=A0 4 files changed, 20 insertions(+), 17 deletions(-)

> @@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTi= mer *t, uint32_t count)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 int64_t ns =3D count;
>
> -=C2=A0 =C2=A0 ns *=3D NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;<= br> > +=C2=A0 =C2=A0 ns *=3D clock_get_ns(t->ctrl->clock);
>=C2=A0 =C2=A0 =C2=A0 ns *=3D npcm7xx_tcsr_prescaler(t->tcsr);

I'm afraid that since you wrote and sent this we've updated the
clock API (in commits 554d523785ef868 and de6a65f11d7e5a2a93f),
so clock_get_ns() doesn't exist any more. Instead there is
a new function clock_ticks_to_ns().

The idea of the new function is that clocks don't necessarily
have a period which is a whole number of nanoseconds, so
doing arithmetic on the return value from clock_get_ns()
introduces rounding errors, especially in the case of
"multiply clock_get_ns() by a tick count to get a duration".
(The worst case for this is "clock frequency >1GHz", at which<= br> point the rounding means that clock_get_ns() returns 0...)

There is as yet no function for "convert duration to
tick count", so code like:
=C2=A0 =C2=A0count =3D ns / clock_get_ns(t->ctrl->clock);

should probably for the moment call clock_ticks_to_ns()
passing a tick count of 1. But I plan to write a patchset
soon which will avoid the need to do that.

Strictly speaking, even "call clock_ticks_to_ns() and
then multiply by the prescaler value" can introduce
rounding error; to deal with that I think you'd need to
either have an internal Clock object whose period you
adjusted as the prescalar value was updated by the guest,
or else do arithmetic with the return value of clock_get()
(which is in units of 2^-32 ns); I'm not sure either is
worth it.
In this particular case, rounding error is l= ess of a concern since the clock should be ~25MHz (in the old implementatio= n it was a fixed value.)

Since the prescaler is al= ways an integer, a possible alternative might be
ns =3D clock_tic= ks_to_ns(t->ctrl->clock, count * npcm7xx_tcsr_prescaler(t->tcsr))<= /div>

and for code to convert ns to count can go
count =3D ns / clock_ticks_to_ns(t->ctrl->clock, npcm7xx_tcsr_pres= caler(t->tcsr))
or use the new API you proposed.

We'll also need to apply similar changes to other place= s in the patchset (ADC and/or PWM) that need=C2=A0to compute clock value.

thanks
-- PMM
--000000000000924a2905b8565325-- From MAILER-DAEMON Thu Jan 07 16:58:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxdIk-0006ez-Az for mharc-qemu-arm@gnu.org; Thu, 07 Jan 2021 16:58:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxdIi-0006eO-Bi for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:58:36 -0500 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]:33089) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxdIf-0003fK-35 for qemu-arm@nongnu.org; Thu, 07 Jan 2021 16:58:36 -0500 Received: by mail-lf1-x134.google.com with SMTP id l11so18304331lfg.0 for ; Thu, 07 Jan 2021 13:58:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=37c5XAQSC88OgOjcdUwpTG+36XDyQ4R5H1dW5QhNB48=; b=Y0CLpEj9XcoCswJniC5Z4gzd7D+U6y9ujI306XitjYGcE81z62S5BZrgOsKbqC0nyC nn/4O+SXrB0eoRzZL0c2h7NOQ0qDg36Sm8Hb0QusS10P0vq4jhaQTyUTrOP7tD9IeyVl lTaSUVWpwqXIAm23FHjqq4cryqUUYNHEZPC75AdvTpqEx/qFn1BZpSS/TMKpZZvRJxZ3 XHJspOsp/S3Ez4lOZOgGakMHY+KH3m482Z2hTCTMaEIjNR75l4xsQmSdA/PIQtPZ+WGP 2sA/Z2ch2Ys6Y5G1mxR6ssUspo3mQJSnS3MoBll8DhDxArGF5e5JdmkcILiz9rDJ27Ps JyVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=37c5XAQSC88OgOjcdUwpTG+36XDyQ4R5H1dW5QhNB48=; b=nodqo/yYOSqBJwwtaFf7i7YDohnIv0iROEtfVKJl9LKPTIU+yODbpaplkH0Xp0h6c5 ZP2jXfW1FmZcsNoI96N6gMOXCeOUO03bVn9rfndnRrsrHkYY7rUID8ou3vi/qgu/9diz ktXCsuBipDjEzX96oo+IZCf6CHbso3CNLynfQaKTBC2bSVeYrCnCXEwUhmuCdKo2yPPP QbU8obBC862tTZ3vijxGsNNW6qxDKtIwoHIvX+mHdIcux05Ro/W/tHkkhY97+ki8iaRC E3m3PZ/tSsskNp1Waqlz3gtUyZWqoL0NckkciVVYdR/oSTUDCiKCqS1Ztvdxc26pnuDK ANzg== X-Gm-Message-State: AOAM531Vt6JtnlTHl0mZ/Tsd31/43eJ1Jok7tUFEXm1c5lw/06Ko6vQj KEWIm7rcPOad0L8ujV7HrztiqlDLMhb2+a0KejbHtA== X-Google-Smtp-Source: ABdhPJz20toQcKAogiPIB3ml13uzX61prPqfHGrn/ernLj8rgFWI0hybSPASYDdRaZ06w0TaqDfGNiHSfsRq3jcrmIA= X-Received: by 2002:a19:cbc3:: with SMTP id b186mr305306lfg.554.1610056711035; Thu, 07 Jan 2021 13:58:31 -0800 (PST) MIME-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> <20201217004349.3740927-4-wuhaotsh@google.com> In-Reply-To: From: Hao Wu Date: Thu, 7 Jan 2021 13:58:18 -0800 Message-ID: Subject: Re: [PATCH v4 3/6] hw/adc: Add an ADC module for NPCM7XX To: Peter Maydell Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="00000000000054c10005b8568a9c" Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x134.google.com X-Spam_score_int: -179 X-Spam_score: -18.0 X-Spam_bar: ------------------ X-Spam_report: (-18.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.382, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 21:58:36 -0000 --00000000000054c10005b8568a9c Content-Type: text/plain; charset="UTF-8" Thanks for your review. We'll apply your suggestions. On Thu, Jan 7, 2021 at 1:07 PM Peter Maydell wrote: > On Thu, 17 Dec 2020 at 00:45, Hao Wu wrote: > > > > The ADC is part of NPCM7XX Module. Its behavior is controled by the > > ADC_CON register. It converts one of the eight analog inputs into a > > digital input and stores it in the ADC_DATA register when enabled. > > > > Users can alter input value by using qom-set QMP command. > > > > Reviewed-by: Havard Skinnemoen > > Reviewed-by: Tyrone Ting > > Signed-off-by: Hao Wu > > --- > > docs/system/arm/nuvoton.rst | 2 +- > > hw/adc/meson.build | 1 + > > hw/adc/npcm7xx_adc.c | 321 ++++++++++++++++++++++++++ > > hw/adc/trace-events | 5 + > > hw/arm/npcm7xx.c | 24 +- > > include/hw/adc/npcm7xx_adc.h | 72 ++++++ > > include/hw/arm/npcm7xx.h | 2 + > > meson.build | 1 + > > tests/qtest/meson.build | 3 +- > > tests/qtest/npcm7xx_adc-test.c | 400 +++++++++++++++++++++++++++++++++ > > 10 files changed, 828 insertions(+), 3 deletions(-) > > create mode 100644 hw/adc/npcm7xx_adc.c > > create mode 100644 hw/adc/trace-events > > create mode 100644 include/hw/adc/npcm7xx_adc.h > > create mode 100644 tests/qtest/npcm7xx_adc-test.c > > > > diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst > > index b00d405d52..35829f8d0b 100644 > > --- a/docs/system/arm/nuvoton.rst > > +++ b/docs/system/arm/nuvoton.rst > > @@ -41,6 +41,7 @@ Supported devices > > * Random Number Generator (RNG) > > * USB host (USBH) > > * GPIO controller > > + * Analog to Digital Converter (ADC) > > > > Missing devices > > --------------- > > @@ -58,7 +59,6 @@ Missing devices > > * USB device (USBD) > > * SMBus controller (SMBF) > > * Peripheral SPI controller (PSPI) > > - * Analog to Digital Converter (ADC) > > * SD/MMC host > > * PECI interface > > * Pulse Width Modulation (PWM) > > diff --git a/hw/adc/meson.build b/hw/adc/meson.build > > index 0d62ae96ae..6ddee23813 100644 > > --- a/hw/adc/meson.build > > +++ b/hw/adc/meson.build > > @@ -1 +1,2 @@ > > softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: > files('stm32f2xx_adc.c')) > > +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) > > diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c > > new file mode 100644 > > index 0000000000..f213b6a6df > > --- /dev/null > > +++ b/hw/adc/npcm7xx_adc.c > > @@ -0,0 +1,321 @@ > > +/* > > + * Nuvoton NPCM7xx ADC Module > > + * > > + * Copyright 2020 Google LLC > > + * > > + * This program is free software; you can redistribute it and/or modify > it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > > + * for more details. > > + */ > > + > > +#include "hw/adc/npcm7xx_adc.h" > > First #include in every .c file must always be "qemu/osdep.h" > (and .h files never include osdep.h). > We'll apply this globally in the patchset. > > > +#include "hw/qdev-clock.h" > > +#include "hw/qdev-properties.h" > > +#include "migration/vmstate.h" > > +#include "qemu/log.h" > > +#include "qemu/module.h" > > +#include "qemu/timer.h" > > +#include "qemu/units.h" > > +#include "trace.h" > > + > > +/* 32-bit register indices. */ > > +enum NPCM7xxADCRegisters { > > + NPCM7XX_ADC_CON, > > + NPCM7XX_ADC_DATA, > > + NPCM7XX_ADC_REGS_END, > > +}; > > + > > +/* Register field definitions. */ > > +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) > > +#define NPCM7XX_ADC_CON_INT_EN BIT(21) > > +#define NPCM7XX_ADC_CON_REFSEL BIT(19) > > +#define NPCM7XX_ADC_CON_INT BIT(18) > > +#define NPCM7XX_ADC_CON_EN BIT(17) > > +#define NPCM7XX_ADC_CON_RST BIT(16) > > +#define NPCM7XX_ADC_CON_CONV BIT(14) > > +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) > > + > > +#define NPCM7XX_ADC_MAX_RESULT 1023 > > +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 > > +#define NPCM7XX_ADC_CONV_CYCLES 20 > > +#define NPCM7XX_ADC_RESET_CYCLES 10 > > +#define NPCM7XX_ADC_R0_INPUT 500000 > > +#define NPCM7XX_ADC_R1_INPUT 1500000 > > + > > +static void npcm7xx_adc_reset(NPCM7xxADCState *s) > > +{ > > + timer_del(&s->conv_timer); > > + timer_del(&s->reset_timer); > > + s->con = 0x000c0001; > > + s->data = 0x00000000; > > +} > > + > > +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) > > +{ > > + uint32_t result; > > + > > + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; > > + if (result > NPCM7XX_ADC_MAX_RESULT) { > > + result = NPCM7XX_ADC_MAX_RESULT; > > + } > > + > > + return result; > > +} > > + > > +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) > > +{ > > + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); > > +} > > + > > +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, > > + uint32_t cycles, uint32_t prescaler) > > +{ > > + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > > + int64_t freq = clock_get_hz(clk); > > + int64_t ns; > > + > > + ns = (NANOSECONDS_PER_SECOND * cycles * prescaler / freq); > > Don't calculate time-in-nanoseconds via clock_get_hz(), > please. Use (the new) clock_ticks_to_ns(). > Agree. We'll apply this (in PWM as well.) > > > > + ns += now; > > + timer_mod(timer, ns); > > +} > > + > > +static void npcm7xx_adc_start_reset(NPCM7xxADCState *s) > > +{ > > + uint32_t prescaler = npcm7xx_adc_prescaler(s); > > + > > + npcm7xx_adc_start_timer(s->clock, &s->reset_timer, > NPCM7XX_ADC_RESET_CYCLES, > > + prescaler); > > +} > > + > > +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) > > +{ > > + uint32_t prescaler = npcm7xx_adc_prescaler(s); > > + > > + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, > NPCM7XX_ADC_CONV_CYCLES, > > + prescaler); > > +} > > + > > +static void npcm7xx_adc_reset_done(void *opaque) > > +{ > > + NPCM7xxADCState *s = opaque; > > + > > + npcm7xx_adc_reset(s); > > +} > > + > > +static void npcm7xx_adc_convert_done(void *opaque) > > +{ > > + NPCM7xxADCState *s = opaque; > > + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); > > + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) > > + ? s->iref : s->vref; > > + > > + g_assert(input < NPCM7XX_ADC_NUM_INPUTS); > > It looks to me given that the CON_MUX field is 4 bits and > NUM_INPUTS is only 8 that the guest can trigger this assert > if it writes a bogus value to the register. You should do > something other than asserting in this situation (eg you > can log a guest error and do nothing, or if you happen to > know what the h/w does in this case that's the best thing).' > The hardware behavior in this case is undefined. We'll log a guest error in this case. > > > + s->data = npcm7xx_adc_convert(s->adci[input], ref); > > + if (s->con & NPCM7XX_ADC_CON_INT_EN) { > > + s->con |= NPCM7XX_ADC_CON_INT; > > + qemu_irq_raise(s->irq); > > + } > > + s->con &= ~NPCM7XX_ADC_CON_CONV; > > +} > > + > > +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) > > +{ > > + adc->calibration_r_values[0] = > npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, > > + adc->iref); > > + adc->calibration_r_values[1] = > npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, > > + adc->iref); > > +} > > + > > +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) > > +{ > > + uint32_t old_con = s->con; > > + > > + /* Write ADC_INT to 1 to clear it */ > > + if (new_con & NPCM7XX_ADC_CON_INT) { > > + new_con &= ~NPCM7XX_ADC_CON_INT; > > + } else if (old_con & NPCM7XX_ADC_CON_INT) { > > + new_con |= NPCM7XX_ADC_CON_INT; > > + } > > + > > + s->con = new_con; > > + > > + if (s->con & NPCM7XX_ADC_CON_RST) { > > + if (!(old_con & NPCM7XX_ADC_CON_RST)) { > > + npcm7xx_adc_start_reset(s); > > + } > > + } else { > > + timer_del(&s->reset_timer); > > + } > > Emulating "this device really takes X length of time to > complete a guest-requested reset" is usually a higher > degree of fidelity than we bother to model. I assume > that some guest software can't cope with the device > resetting faster than advertised ? > Thanks for the suggestion. From the Linux driver it is unlikely to cause any problem if we reset immediately. So we can remove the reset_timer feature. > > > + if ((s->con & NPCM7XX_ADC_CON_EN)) { > > + if (s->con & NPCM7XX_ADC_CON_CONV) { > > + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { > > + npcm7xx_adc_start_convert(s); > > + } > > + } else { > > + timer_del(&s->conv_timer); > > + } > > + } > > +} > > + > > +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned > size) > > +{ > > + uint64_t value = 0; > > + NPCM7xxADCState *s = opaque; > > + hwaddr reg = offset / sizeof(uint32_t); > > If you defined your register offsets with the REG32() macro > in include/hw/registerfields.h then it would define > A_FOO constants for you which are at the byte offsets of > the 32-bit registers, and you could avoid converting > the offset by dividing by 4 here. This isn't an obligatory > change, but I think it ends up neater code. > Thanks. We'll apply. > > > > > diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h > > new file mode 100644 > > index 0000000000..7f9acbeaa1 > > --- /dev/null > > +++ b/include/hw/adc/npcm7xx_adc.h > > @@ -0,0 +1,72 @@ > > +/* > > + * Nuvoton NPCM7xx ADC Module > > + * > > + * Copyright 2020 Google LLC > > + * > > + * This program is free software; you can redistribute it and/or modify > it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > > + * for more details. > > + */ > > +#ifndef NPCM7XX_ADC_H > > +#define NPCM7XX_ADC_H > > + > > +#include "qemu/osdep.h" > > .h files never include osdep.h (because the .c files always do). > > thanks > -- PMM > --00000000000054c10005b8568a9c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks for your review. We'll apply your suggesti= ons.

On Thu, Jan 7, 2021 at 1:07 PM Peter Maydell <peter.maydell@linaro.org> wr= ote:
On Thu, 17 = Dec 2020 at 00:45, Hao Wu <wuhaotsh@google.com> wrote:
>
> The ADC is part of NPCM7XX Module. Its behavior is controled by the > ADC_CON register. It converts one of the eight analog inputs into a > digital input and stores it in the ADC_DATA register when enabled.
>
> Users can alter input value by using qom-set QMP command.
>
> Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> ---
>=C2=A0 docs/system/arm/nuvoton.rst=C2=A0 =C2=A0 |=C2=A0 =C2=A02 +-
>=C2=A0 hw/adc/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 =C2=A01 +
>=C2=A0 hw/adc/npcm7xx_adc.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 3= 21 ++++++++++++++++++++++++++
>=C2=A0 hw/adc/trace-events=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A05 +
>=C2=A0 hw/arm/npcm7xx.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0|=C2=A0 24 +-
>=C2=A0 include/hw/adc/npcm7xx_adc.h=C2=A0 =C2=A0|=C2=A0 72 ++++++
>=C2=A0 include/hw/arm/npcm7xx.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A02 +
>=C2=A0 meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 tests/qtest/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A03 +-
>=C2=A0 tests/qtest/npcm7xx_adc-test.c | 400 +++++++++++++++++++++++++++= ++++++
>=C2=A0 10 files changed, 828 insertions(+), 3 deletions(-)
>=C2=A0 create mode 100644 hw/adc/npcm7xx_adc.c
>=C2=A0 create mode 100644 hw/adc/trace-events
>=C2=A0 create mode 100644 include/hw/adc/npcm7xx_adc.h
>=C2=A0 create mode 100644 tests/qtest/npcm7xx_adc-test.c
>
> diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst=
> index b00d405d52..35829f8d0b 100644
> --- a/docs/system/arm/nuvoton.rst
> +++ b/docs/system/arm/nuvoton.rst
> @@ -41,6 +41,7 @@ Supported devices
>=C2=A0 =C2=A0* Random Number Generator (RNG)
>=C2=A0 =C2=A0* USB host (USBH)
>=C2=A0 =C2=A0* GPIO controller
> + * Analog to Digital Converter (ADC)
>
>=C2=A0 Missing devices
>=C2=A0 ---------------
> @@ -58,7 +59,6 @@ Missing devices
>=C2=A0 =C2=A0* USB device (USBD)
>=C2=A0 =C2=A0* SMBus controller (SMBF)
>=C2=A0 =C2=A0* Peripheral SPI controller (PSPI)
> - * Analog to Digital Converter (ADC)
>=C2=A0 =C2=A0* SD/MMC host
>=C2=A0 =C2=A0* PECI interface
>=C2=A0 =C2=A0* Pulse Width Modulation (PWM)
> diff --git a/hw/adc/meson.build b/hw/adc/meson.build
> index 0d62ae96ae..6ddee23813 100644
> --- a/hw/adc/meson.build
> +++ b/hw/adc/meson.build
> @@ -1 +1,2 @@
>=C2=A0 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: fi= les('stm32f2xx_adc.c'))
> +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('np= cm7xx_adc.c'))
> diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
> new file mode 100644
> index 0000000000..f213b6a6df
> --- /dev/null
> +++ b/hw/adc/npcm7xx_adc.c
> @@ -0,0 +1,321 @@
> +/*
> + * Nuvoton NPCM7xx ADC Module
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms of the GNU General Public License as published by = the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, bu= t WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Licen= se
> + * for more details.
> + */
> +
> +#include "hw/adc/npcm7xx_adc.h"

First #include in every .c file must always be "qemu/osdep.h"
(and .h files never include osdep.h).
We'll apply = this globally in the patchset.=C2=A0

> +#include "hw/qdev-clock.h"
> +#include "hw/qdev-properties.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/timer.h"
> +#include "qemu/units.h"
> +#include "trace.h"
> +
> +/* 32-bit register indices. */
> +enum NPCM7xxADCRegisters {
> +=C2=A0 =C2=A0 NPCM7XX_ADC_CON,
> +=C2=A0 =C2=A0 NPCM7XX_ADC_DATA,
> +=C2=A0 =C2=A0 NPCM7XX_ADC_REGS_END,
> +};
> +
> +/* Register field definitions. */
> +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
> +#define NPCM7XX_ADC_CON_INT_EN=C2=A0 BIT(21)
> +#define NPCM7XX_ADC_CON_REFSEL=C2=A0 BIT(19)
> +#define NPCM7XX_ADC_CON_INT=C2=A0 =C2=A0 =C2=A0BIT(18)
> +#define NPCM7XX_ADC_CON_EN=C2=A0 =C2=A0 =C2=A0 BIT(17)
> +#define NPCM7XX_ADC_CON_RST=C2=A0 =C2=A0 =C2=A0BIT(16)
> +#define NPCM7XX_ADC_CON_CONV=C2=A0 =C2=A0 BIT(14)
> +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
> +
> +#define NPCM7XX_ADC_MAX_RESULT=C2=A0 =C2=A0 =C2=A0 1023
> +#define NPCM7XX_ADC_DEFAULT_IREF=C2=A0 =C2=A0 2000000
> +#define NPCM7XX_ADC_CONV_CYCLES=C2=A0 =C2=A0 =C2=A020
> +#define NPCM7XX_ADC_RESET_CYCLES=C2=A0 =C2=A0 10
> +#define NPCM7XX_ADC_R0_INPUT=C2=A0 =C2=A0 =C2=A0 =C2=A0 500000
> +#define NPCM7XX_ADC_R1_INPUT=C2=A0 =C2=A0 =C2=A0 =C2=A0 1500000
> +
> +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
> +{
> +=C2=A0 =C2=A0 timer_del(&s->conv_timer);
> +=C2=A0 =C2=A0 timer_del(&s->reset_timer);
> +=C2=A0 =C2=A0 s->con =3D 0x000c0001;
> +=C2=A0 =C2=A0 s->data =3D 0x00000000;
> +}
> +
> +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
> +{
> +=C2=A0 =C2=A0 uint32_t result;
> +
> +=C2=A0 =C2=A0 result =3D input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;<= br> > +=C2=A0 =C2=A0 if (result > NPCM7XX_ADC_MAX_RESULT) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 result =3D NPCM7XX_ADC_MAX_RESULT;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return result;
> +}
> +
> +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
> +{
> +=C2=A0 =C2=A0 return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
> +}
> +
> +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t cycles, uint32_t prescaler)
> +{
> +=C2=A0 =C2=A0 int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);<= br> > +=C2=A0 =C2=A0 int64_t freq =3D clock_get_hz(clk);
> +=C2=A0 =C2=A0 int64_t ns;
> +
> +=C2=A0 =C2=A0 ns =3D (NANOSECONDS_PER_SECOND * cycles * prescaler / f= req);

Don't calculate time-in-nanoseconds via clock_get_hz(),
please. Use (the new) clock_ticks_to_ns().
Agree. We&#= 39;ll apply this (in PWM as well.)=C2=A0


> +=C2=A0 =C2=A0 ns +=3D now;
> +=C2=A0 =C2=A0 timer_mod(timer, ns);
> +}
> +
> +static void npcm7xx_adc_start_reset(NPCM7xxADCState *s)
> +{
> +=C2=A0 =C2=A0 uint32_t prescaler =3D npcm7xx_adc_prescaler(s);
> +
> +=C2=A0 =C2=A0 npcm7xx_adc_start_timer(s->clock, &s->reset_t= imer, NPCM7XX_ADC_RESET_CYCLES,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 prescaler);
> +}
> +
> +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
> +{
> +=C2=A0 =C2=A0 uint32_t prescaler =3D npcm7xx_adc_prescaler(s);
> +
> +=C2=A0 =C2=A0 npcm7xx_adc_start_timer(s->clock, &s->conv_ti= mer, NPCM7XX_ADC_CONV_CYCLES,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 prescaler);
> +}
> +
> +static void npcm7xx_adc_reset_done(void *opaque)
> +{
> +=C2=A0 =C2=A0 NPCM7xxADCState *s =3D opaque;
> +
> +=C2=A0 =C2=A0 npcm7xx_adc_reset(s);
> +}
> +
> +static void npcm7xx_adc_convert_done(void *opaque)
> +{
> +=C2=A0 =C2=A0 NPCM7xxADCState *s =3D opaque;
> +=C2=A0 =C2=A0 uint32_t input =3D NPCM7XX_ADC_CON_MUX(s->con);
> +=C2=A0 =C2=A0 uint32_t ref =3D (s->con & NPCM7XX_ADC_CON_REFSE= L)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ? s->iref : s->vref;
> +
> +=C2=A0 =C2=A0 g_assert(input < NPCM7XX_ADC_NUM_INPUTS);

It looks to me given that the CON_MUX field is 4 bits and
NUM_INPUTS is only 8 that the guest can trigger this assert
if it writes a bogus value to the register. You should do
something other than asserting in this situation (eg you
can log a guest error and do nothing, or if you happen to
know what the h/w does in this case that's the best thing).'
The hardware behavior in this case is undefined. We'll l= og a guest error in this case.

> +=C2=A0 =C2=A0 s->data =3D npcm7xx_adc_convert(s->adci[input], r= ef);
> +=C2=A0 =C2=A0 if (s->con & NPCM7XX_ADC_CON_INT_EN) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->con |=3D NPCM7XX_ADC_CON_INT;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_irq_raise(s->irq);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 s->con &=3D ~NPCM7XX_ADC_CON_CONV;
> +}
> +
> +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
> +{
> +=C2=A0 =C2=A0 adc->calibration_r_values[0] =3D npcm7xx_adc_convert= (NPCM7XX_ADC_R0_INPUT,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 adc->iref);
> +=C2=A0 =C2=A0 adc->calibration_r_values[1] =3D npcm7xx_adc_convert= (NPCM7XX_ADC_R1_INPUT,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 adc->iref);
> +}
> +
> +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_co= n)
> +{
> +=C2=A0 =C2=A0 uint32_t old_con =3D s->con;
> +
> +=C2=A0 =C2=A0 /* Write ADC_INT to 1 to clear it */
> +=C2=A0 =C2=A0 if (new_con & NPCM7XX_ADC_CON_INT) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 new_con &=3D ~NPCM7XX_ADC_CON_INT; > +=C2=A0 =C2=A0 } else if (old_con & NPCM7XX_ADC_CON_INT) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 new_con |=3D NPCM7XX_ADC_CON_INT;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 s->con =3D new_con;
> +
> +=C2=A0 =C2=A0 if (s->con & NPCM7XX_ADC_CON_RST) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!(old_con & NPCM7XX_ADC_CON_RST))= {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 npcm7xx_adc_start_reset(s);=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 timer_del(&s->reset_timer);
> +=C2=A0 =C2=A0 }

Emulating "this device really takes X length of time to
complete a guest-requested reset" is usually a higher
degree of fidelity than we bother to model. I assume
that some guest software can't cope with the device
resetting faster than advertised ?
Thanks for the sugg= estion. From the Linux driver it is unlikely to cause any problem if we res= et immediately. So we can remove the reset_timer feature.

> +=C2=A0 =C2=A0 if ((s->con & NPCM7XX_ADC_CON_EN)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->con & NPCM7XX_ADC_CON_CONV)= {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!(old_con & NPCM7XX= _ADC_CON_CONV)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 npcm7xx_adc_s= tart_convert(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 timer_del(&s->conv_t= imer);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 }
> +}
> +
> +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigne= d size)
> +{
> +=C2=A0 =C2=A0 uint64_t value =3D 0;
> +=C2=A0 =C2=A0 NPCM7xxADCState *s =3D opaque;
> +=C2=A0 =C2=A0 hwaddr reg =3D offset / sizeof(uint32_t);

If you defined your register offsets with the REG32() macro
in include/hw/registerfields.h then it would define
A_FOO constants for you which are at the byte offsets of
the 32-bit registers, and you could avoid converting
the offset by dividing by 4 here. This isn't an obligatory
change, but I think it ends up neater code.
Thanks. We= 'll apply.=C2=A0



> diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc= .h
> new file mode 100644
> index 0000000000..7f9acbeaa1
> --- /dev/null
> +++ b/include/hw/adc/npcm7xx_adc.h
> @@ -0,0 +1,72 @@
> +/*
> + * Nuvoton NPCM7xx ADC Module
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms of the GNU General Public License as published by = the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, bu= t WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Licen= se
> + * for more details.
> + */
> +#ifndef NPCM7XX_ADC_H
> +#define NPCM7XX_ADC_H
> +
> +#include "qemu/osdep.h"

.h files never include osdep.h (because the .c files always do).

thanks
-- PMM
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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id a4sm7972298pgn.40.2021.01.07.14.02.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jan 2021 14:02:25 -0800 (PST) Subject: Re: [PATCH v2 24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-25-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <6ff3c7b0-9254-2e36-89e0-e9eb59fd6e7f@linaro.org> Date: Thu, 7 Jan 2021 12:02:21 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.267, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jan 2021 22:02:29 -0000 On 1/7/21 7:39 AM, Peter Maydell wrote: >> + if (align > MO_ALIGN_8) { >> + t0 = tcg_temp_new_i64(); >> + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ | align); >> + tcg_gen_addi_i64(clean_addr, clean_addr, 8); >> + tcg_gen_addi_ptr(i, i, 8); >> + tcg_gen_st_i64(t0, cpu_env, vofs); >> + tcg_temp_free_i64(t0); >> + align = 0; >> + } >> + > > Why do we need to do this (and the similar thing in do_str()) ? > Most of the rest of the patch is fairly clear in that it is just > passing the alignment requirement through to the load/store fns, > but this is a bit more opaque to me... What follows this context is a single memory access within a tcg loop. When align is <= the size of the access, every access can use the same alignment mop. But for MO_ALIGN_16, since we're emitting 8-byte accesses, the second access will not be 16-byte aligned. So I peel off one loop iteration at the beginning to perform the alignment check. r~ From MAILER-DAEMON Fri Jan 08 04:08:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxnl1-0003qX-9r for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 04:08:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxnkz-0003pz-Dr; Fri, 08 Jan 2021 04:08:29 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:42254 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kxnku-00007E-LR; Fri, 08 Jan 2021 04:08:26 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id D41F85FC66; Fri, 8 Jan 2021 10:08:17 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCHv2 1/2] target/arm: ARMv8.4-TTST extension Date: Fri, 8 Jan 2021 11:08:16 +0200 Message-Id: <20210108090817.6127-1-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 09:08:29 -0000 From: Rémi Denis-Courmont This adds for the Small Translation tables extension in AArch64 state. Signed-off-by: Rémi Denis-Courmont --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..ad37ff61c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3936,6 +3936,11 @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; } +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d0d4cd1e1..bf54616c23 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10842,7 +10842,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k; - int select, tsz, tbi; + int select, tsz, tbi, max_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -10877,7 +10877,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract64(tcr, 42, 1); } } - tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + max_tsz = 48 - using64k; + } else { + max_tsz = 39; + } + + tsz = MIN(tsz, max_tsz); tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ /* Present TBI as a composite with TBID. */ @@ -11096,6 +11103,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (!aarch64 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; + + if (cpu_isar_feature(aa64_st, cpu)) { + startlevel &= 3; + } } else { /* 16KB or 64KB pages */ startlevel = 3 - sl0; -- 2.30.0 From MAILER-DAEMON Fri Jan 08 04:08:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxnl1-0003qa-G5 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 04:08:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxnkz-0003py-Dr; Fri, 08 Jan 2021 04:08:29 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:42252 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kxnku-00007F-LW; Fri, 08 Jan 2021 04:08:26 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 2F94C5FECC; Fri, 8 Jan 2021 10:08:18 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU Date: Fri, 8 Jan 2021 11:08:17 +0200 Message-Id: <20210108090817.6127-2-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 09:08:29 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc6..da24f94baa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr2; t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ cpu->isar.id_aa64mmfr2 = t; /* Replicate the same data to the 32-bit id registers. */ -- 2.30.0 From MAILER-DAEMON Fri Jan 08 07:33:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxqx7-0001qu-DC for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 07:33:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxqx2-0001pm-9A for qemu-arm@nongnu.org; Fri, 08 Jan 2021 07:33:09 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]:36737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxqwy-0005xo-5I for qemu-arm@nongnu.org; Fri, 08 Jan 2021 07:33:06 -0500 Received: by mail-ed1-x533.google.com with SMTP id b2so11059697edm.3 for ; Fri, 08 Jan 2021 04:33:03 -0800 (PST) DKIM-Signature: v=1; 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Fri, 08 Jan 2021 04:33:02 -0800 (PST) MIME-Version: 1.0 References: <20210106063504.10841-1-bmeng.cn@gmail.com> In-Reply-To: <20210106063504.10841-1-bmeng.cn@gmail.com> From: Peter Maydell Date: Fri, 8 Jan 2021 12:32:51 +0000 Message-ID: Subject: Re: [PATCH v3 0/4] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot To: Bin Meng Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , Jean-Christophe Dubois , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 12:33:09 -0000 On Wed, 6 Jan 2021 at 06:35, Bin Meng wrote: > > From: Bin Meng > > > At present the upstream U-Boot (as of today, v2021.01-rc3) does not > boot on QEMU sabrelite machine. > > This fixes several issues to improve emulation fidelity of the i.MX6 > sabrelite board. With this series, upstream U-Boot can boot to U-Boot > command shell. While we are here, add a target guide for this board > to help people run Linux kernel and U-Boot on QEMU. > > Changes in v3: > - correct 2 typos in sabrelite.rst > > Changes in v2: > - new patch: add sabrelite target guide > > Bin Meng (4): > hw/misc: imx6_ccm: Update PMU_MISC0 reset value > hw/msic: imx6_ccm: Correct register value for silicon type > hw/arm: sabrelite: Connect the Ethernet PHY at address 6 > docs/system: arm: Add sabrelite board description Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Fri Jan 08 09:15:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxsYF-0002ug-Qg for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 09:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxsYD-0002uB-WE for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:15:38 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:34062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxsYA-0007w2-6E for qemu-arm@nongnu.org; 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Fri, 08 Jan 2021 06:15:31 -0800 (PST) MIME-Version: 1.0 References: <20201216221247.522686-1-richard.henderson@linaro.org> <20201216221247.522686-2-richard.henderson@linaro.org> In-Reply-To: <20201216221247.522686-2-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 8 Jan 2021 14:15:20 +0000 Message-ID: Subject: Re: [PATCH v4 1/3] target/arm: Implement an IMPDEF pauth algorithm To: Richard Henderson Cc: QEMU Developers , qemu-arm , Mark Rutland Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 14:15:38 -0000 On Wed, 16 Dec 2020 at 22:12, Richard Henderson wrote: > > Without hardware acceleration, a cryptographically strong > algorithm is too expensive for pauth_computepac. > > Even with hardware accel, we are not currently expecting > to link the linux-user binaries to any crypto libraries, > and doing so would generally make the --static build fail. > > So choose XXH64 as a reasonably quick and decent hash. > > Tested-by: Mark Rutland > Signed-off-by: Richard Henderson > --- > v2: Move the XXH64 bits to xxhash.h (ajb). > Create isar_feature_aa64_pauth_arch and fixup a comment > in isar_feature_aa64_pauth that no longer applies. > --- > +static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier, > + ARMPACKey key) > +{ > + /* > + * The XXH64 algorithmm, simplified for size 32. > + * See the description of the algorithm in xxhash.h. > + */ > + uint64_t v1 = QEMU_XXHASH_SEED + XXH_PRIME64_1 + XXH_PRIME64_2; > + uint64_t v2 = QEMU_XXHASH_SEED + XXH_PRIME64_2; > + uint64_t v3 = QEMU_XXHASH_SEED + 0; > + uint64_t v4 = QEMU_XXHASH_SEED - XXH_PRIME64_1; > + > + v1 = XXH64_round(v1, data); > + v2 = XXH64_round(v2, modifier); > + v3 = XXH64_round(v3, key.lo); > + v4 = XXH64_round(v4, key.hi); > + > + return XXH64_avalanche(XXH64_mergerounds(v1, v2, v3, v4)); Since the only use of xxh64 we make is "feed in 4 64 bit inputs and get a 64 bit result", why provide all the components and stitch them together here rather than following the existing pattern we have for qemu_xxhash* (the xxh32 algorithm) and providing a function static inline uint64_t qemu_xxhash64_4(uint64_t a, uint64_t b, uint64_t c, uint64_t d) in xxhash.h ? thanks -- PMM From MAILER-DAEMON Fri Jan 08 09:16:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxsZ6-0003eB-9B for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 09:16:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxsZ4-0003cU-Ig for qemu-arm@nongnu.org; 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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mLQfpG/xAL/ln16xrJTSA3DJ4YwPS5WhjEJngGqR6gs=; b=tz05AjqdYlmtNfprwcaoRCil+nKcty/pgb2uTJczPqx6IOs1uWNN4XtbwH1E9JnqW1 Ww6s5zzGxfjbT+zYFi1N+CqZ4/t0IWHoZTF41VKx/MLO4k4gIAWaICb2HMphWoQgcdwg X8AdimlV4VBtWOh1dQKdp7d54zrocJ/8ynZTWX1HNMSlHLc9dgAT6ti1iZguSm1xf4iM twTT7YvyXDGEsFMoKddgQCfxfScXyx9VQhnc+b00ipYUUlyFLoZ7YeW97F6YODctuHKR l9kzJtUmPoRxGnoIhy8fVU6Db4WrMeQXyDjC1IAbEK/H5eYrhuq6VLa0bdyspaSZNiOm BhDg== X-Gm-Message-State: AOAM531iKPBAdcRiarmbHYltxBjwsHElSBFgigrXSho5mpwZiFzCefp9 dE0N0IG3PYIQ11klyo5RKizHOtQPjDu1K/dS7ZGbmQ== X-Google-Smtp-Source: ABdhPJw0aE36WY54qH+BMgSJyx0k7eybjb0JnPmB93miANsU45Jxtqvx/VAgZZgqHLY8McIXx6W02wqUzFQFWZHEYzs= X-Received: by 2002:a05:6402:366:: with SMTP id s6mr5296788edw.44.1610115387614; Fri, 08 Jan 2021 06:16:27 -0800 (PST) MIME-Version: 1.0 References: <20201216221247.522686-1-richard.henderson@linaro.org> <20201216221247.522686-3-richard.henderson@linaro.org> In-Reply-To: <20201216221247.522686-3-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 8 Jan 2021 14:16:16 +0000 Message-ID: Subject: Re: [PATCH v4 2/3] target/arm: Add cpu properties to control pauth To: Richard Henderson Cc: QEMU Developers , qemu-arm , Mark Rutland , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 14:16:30 -0000 On Wed, 16 Dec 2020 at 22:12, Richard Henderson wrote: > > The crypto overhead of emulating pauth can be significant for > some workloads. Add two boolean properties that allows the > feature to be turned off, on with the architected algorithm, > or on with an implementation defined algorithm. > > We need two intermediate booleans to control the state while > parsing properties lest we clobber ID_AA64ISAR1 into an invalid > intermediate state. > > Tested-by: Mark Rutland > Reviewed-by: Andrew Jones > Signed-off-by: Richard Henderson Could we have some documentation of the properties in docs/system/arm/cpu-features.rst, please? thanks -- PMM From MAILER-DAEMON Fri Jan 08 09:32:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxso6-0000sC-Ag for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 09:32:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxso4-0000ro-Oq for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:32:00 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:41862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxso2-0005MN-1l for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:32:00 -0500 Received: by mail-ej1-x629.google.com with SMTP id ce23so14752212ejb.8 for ; Fri, 08 Jan 2021 06:31:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Z2fET9aT5jYvH4mQ6JfrVdx+5XT3aGRhAsHcbfWCoRU=; b=c2NE2SnxwR/oBnwjpP7cI199pSHyqdvz9xe5r9t490W3su6eoYeNozjuEsWjj3Sfhc cD90yI71Lv4luMKf0RViHEfXp8iwAMqNs8qDhE9lonIc3lWsfFoSfXRT+8V4Uqb/Le6o gs9Pi3swK0UfSAlLrPN276V55UFKFrQWmrRmrjcNVbpmHzMaeGQ8WC0szso9ZdgfHYt+ phguDuIjUj7tZegMkQhrunBCelOWxqKjjGEroXiPNzKtnIE34Zjh8NrAUaTo6V6H4gZ8 gLi7vxMmH7627UgTCQuPOvKrUT2zLpY0M4aUPlQjpuyPUjAA6V/kzTOKKAgs7tRsw3Nm 9UBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Z2fET9aT5jYvH4mQ6JfrVdx+5XT3aGRhAsHcbfWCoRU=; b=MPbnjmyw0LUnfnpgHDSA8pit/ydYFhmGLBD1jQyeYK83spi7zJkhEMCcXG1G0TcbUK pp9G9/+pN5RTPqWvRJ0ejM5QufVrgfmrD7aQ3uaQC9fqvSTjsZmuZKz/ejTriBBkZIGZ nkguYAC094uZ7QlIPPMfn+BtLaVl0Y5MyfLS6qda0qnaX3rWVea7FQnjvtwCu5kQfvDV jBK0Gwyy25QE5KEUsZbKhZF41O9G5eE0zCDnOnpI1yZvUUxQRhG5WSJtIPXf/HlPrE3z gQ4mNtihttm34OPIYc+f3MNnA51JlqME/aIPJY1MESwBDGQf5cNIVGxkgLldZyG40k+B tn+w== X-Gm-Message-State: AOAM532Pt+qbkn43zM1UcOkbTDyflBAVUvLhqyIIQmrdJQs1vraFncTz w1OdKvVfpH1nQy0zMypLZxBmltFOnUat0a95loow4w== X-Google-Smtp-Source: ABdhPJyeEfL4ghWf0n/9cpXyuZqG6GBzpJxNV96yHUhTxjaF9ONiNfumMsnTzbc18N4d7lVkG77kPu2V8zZlqPt+cyE= X-Received: by 2002:a17:906:31d2:: with SMTP id f18mr2744082ejf.407.1610116315014; Fri, 08 Jan 2021 06:31:55 -0800 (PST) MIME-Version: 1.0 References: <20210106163426.9971-1-maxim.uvarov@linaro.org> In-Reply-To: <20210106163426.9971-1-maxim.uvarov@linaro.org> From: Peter Maydell Date: Fri, 8 Jan 2021 14:31:43 +0000 Message-ID: Subject: Re: [PATCHv3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 14:32:01 -0000 On Wed, 6 Jan 2021 at 16:34, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). > Use the same gpio 3 and gpio 4 which were used by > non acpi variant of linux power control gpios. > > Signed-off-by: Maxim Uvarov > --- > v3: added missed include qemu/log.h for qemu_log(.. > v2: replace printf with qemu_log (Philippe Mathieu-Daud=C3=A9) > > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 24 ++++++++++++ > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 85 +++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > include/hw/arm/virt.h | 1 + > 6 files changed, 115 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c Could you put "Implement new gpio_pwr device" and "wire up gpio_pwr device in virt board" in separate patches please? (That is, turn this into a two-patch patchset.) > +static void create_gpio_secure(const VirtMachineState *vms) > +{ > + DeviceState *pl061_dev; > + static DeviceState *gpio_pwr_dev; > + > + hwaddr base =3D vms->memmap[VIRT_SECURE_GPIO].base; > + int irq =3D vms->irqmap[VIRT_SECURE_GPIO]; > + > + pl061_dev =3D sysbus_create_simple("pl061", base, > + qdev_get_gpio_in(vms->gic, irq)); sysbus_create_simple() will map the device into the default (NonSecure) address space. You need to pass secure_sysmem into the create_ function and use that (compare create_uart()). > + > + gpio_pwr_dev =3D sysbus_create_simple("gpio-pwr", -1, > + qdev_get_gpio_in(pl061_dev, 3)); > + > + qdev_connect_gpio_out(pl061_dev, 3, qdev_get_gpio_in(gpio_pwr_dev, 3= )); > + qdev_connect_gpio_out(pl061_dev, 4, qdev_get_gpio_in(gpio_pwr_dev, 4= )); > +} > + > static void create_virtio_devices(const VirtMachineState *vms) > { > int i; > @@ -1993,6 +2013,10 @@ static void machvirt_init(MachineState *machine) > create_gpio(vms); > } > > + if (vms->secure) { > + create_gpio_secure(vms); > + } The 'virt' board has strict versioning -- this means that, for instance, the 'virt-5.2' machine must always look exactly like the version of 'virt' that shipped in QEMU's 5.2 release, with no extra guest visible devices. So you need to add the flags and code so that this new secure PL061 is only present from virt-6.0 and onwards. This means a flag no_secure_gpio in the VirtMachineClass and a flag secure_gpio in the VirtMachineState, a line setting vmc->no_secure_gpio to true in virt_machine_5_2_options(), code in virt_instance_init() to set vms->secure_gpio from vmc->no_secure_gpio, and then only create the secure GPIO if vms->secure_gpio is true. The 'no_its'/'its' flags are the right pattern to use. (Yes, having no_foo in the class struct and foo in the state struct is deliberate.) > diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c > new file mode 100644 > index 0000000000..0d0680c9f7 > --- /dev/null > +++ b/hw/gpio/gpio_pwr.c > @@ -0,0 +1,85 @@ > +/* > + * GPIO qemu power controller > + * > + * Copyright (c) 2020 Linaro Limited > + * > + * Author: Maxim Uvarov > + * > + * Virtual gpio driver which can be used on top of pl061 > + * to reboot and shutdown qemu virtual machine. One of use > + * case is gpio driver for secure world application (ARM > + * Trusted Firmware.). > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or la= ter. > + * See the COPYING file in the top-level directory. > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ What is the interface of this device intended to be? As written it has: * 8 input GPIO lines, of which all except 3 and 4 are ignored; asserting input line 3 triggers a shutdown, and asserting input line 4 triggers a reset * one output IRQ line, which is asserted whenever any input GPIO line is set to any level, and never cleared This seems a very weird choice of interface. I was expecting something much more simple: * no output IRQ or GPIO lines * two named input GPIO lines: 'reset' : when asserted, trigger system reset 'shutdown' : when asserted, trigger system shutdown thanks -- PMM From MAILER-DAEMON Fri Jan 08 09:40:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxswU-0005Bo-BY for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 09:40:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxswT-0005BN-0O for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:40:41 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:42050) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxswN-0008V0-Fk for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:40:40 -0500 Received: by mail-ed1-x530.google.com with SMTP id g24so11374439edw.9 for ; Fri, 08 Jan 2021 06:40:34 -0800 (PST) DKIM-Signature: v=1; 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Fri, 08 Jan 2021 06:40:33 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> <20201202144523.24526-2-bmeng.cn@gmail.com> In-Reply-To: <20201202144523.24526-2-bmeng.cn@gmail.com> From: Peter Maydell Date: Fri, 8 Jan 2021 14:40:22 +0000 Message-ID: Subject: Re: [PATCH v2 2/2] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() To: Bin Meng Cc: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , QEMU Developers , Xuzhou Cheng , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 14:40:41 -0000 On Wed, 2 Dec 2020 at 14:45, Bin Meng wrote: > > From: Xuzhou Cheng > > When a write to ECSPI_CONREG register to disable the SPI controller, > imx_spi_reset() is called to reset the controller, during which CS > lines should have been disabled, otherwise the state machine of any > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > its last state and responds incorrectly to any follow-up commands. > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng > Acked-by: Alistair Francis > > --- > > Changes in v2: > - Fix the "Fixes" tag in the commit message > > hw/ssi/imx_spi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049a21..85c172e815 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > static void imx_spi_reset(DeviceState *dev) > { > IMXSPIState *s = IMX_SPI(dev); > + int i; > > DPRINTF("\n"); > > @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) > > imx_spi_update_irq(s); > > + for (i = 0; i < ECSPI_NUM_CS; i++) { > + qemu_set_irq(s->cs_lines[i], 1); > + } Calling qemu_set_irq() in a device reset function is a bad idea, because you don't know whether the thing on the other end of the IRQ line (a) has already reset before you or (b) is going to reset after you. If you need to do this then I think you need to convert this device (and perhaps whatever it's connected to) to the 3-phase-reset API. (But you probably don't, see below.) Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change. If this is required only for the case of "guest requested a controller reset via the ECSPI_CONREG register" and not for full system reset, then you can handle that by having an imx_spi_soft_reset() which calls imx_spi_reset() and then does the qemu_set_irq() calls, so full system (power-cycle) reset still goes to imx_spi_reset() but guest-commanded reset via the register interface calls imx_spi_soft_reset(). thanks -- PMM From MAILER-DAEMON Fri Jan 08 09:49:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxt4z-00087z-Iu for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 09:49:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxt4y-00087l-4R for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:49:28 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:43389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxt4v-0002um-Az for qemu-arm@nongnu.org; Fri, 08 Jan 2021 09:49:27 -0500 Received: by mail-ej1-x630.google.com with SMTP id jx16so14789906ejb.10 for ; Fri, 08 Jan 2021 06:49:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EPrlCp8NjczREcv59nZpUeZQD3tdKHQamXpMTRmG/NE=; b=qRt7mPVdi6i0OXx7q83lbdqMrI6t0AayzvJgQj8Iw35ln7dAbgLG25aVugw5NgQCvu hWZYcf3rrwHkDRE66an7JrfLxWWs1fR+emKJqaUw5/RWJ2nij2tf4rVSorADLrhYmcdY in397cOZms27hcpiFbVqJVon4kDDTVMCPhTbv1wRGDi3PqhK4kmVKvy32gIe5UPDPEKn BlhTgxfTS3Us0O0J0E3LCqz4zbrAOJNuC37Qlj1oz+eo5aj2xC5V7xOwjqbnkD231CIw koGJHmP5n5E2nICGZDEC1K41nzuvgRu6PY5jd7EclGZskNSFnfD5rydXv7UOciWDnK56 pBIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EPrlCp8NjczREcv59nZpUeZQD3tdKHQamXpMTRmG/NE=; b=ZEgiU1aCkxYVBdEzMK2kbAIM0IjtiCozA8wY9M+KVwWOpamzGtGDTpgVyeNooE9UrD WeYO22YuSPnID5+G5J6x+/x1jM3s/kEqaTV8xWqPSJLXE9Pac6x2fu3hEdY6Rs0D4HEe R5UDSBfvPONCr7sFSFBHIrSjDc+akYcqRODc3nWPZ0MTNYjKR5jZzxMr8lBNbrJy8nfj PA+EBm/bNVcB5QQFrhgFv+bCe78IveTmv1/Hgex2Mke1W2vsDIdKTFP1y/b94WavhpuP gaAg+NVp0ZcBh2279ZrYCvd6Mel5UIUwUTBaS2Zpiu8vY9a0oi4KuJPWWzE1T4f6rzFV qtHA== X-Gm-Message-State: AOAM530aj3PdFvtC/DMs7m9kGj3maDhhy/MpdTnEGCpYa8QBRi2dcIDs 92+Rq5q8hfDM/RJNhxRMKRAboqV5oTWmGYgBb1W3ng== X-Google-Smtp-Source: ABdhPJySm8GDeTlVwpa2iuR8HVPiQmc+lao42kRoueGnkWMjiRDeIsATjUH9WgQn01ZcDK3i5bhxr3rP3VSTqTQuUZA= X-Received: by 2002:a17:906:e250:: with SMTP id gq16mr2773095ejb.382.1610117363818; Fri, 08 Jan 2021 06:49:23 -0800 (PST) MIME-Version: 1.0 References: <1608182913-54603-1-git-send-email-bmeng.cn@gmail.com> <1608182913-54603-2-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1608182913-54603-2-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Fri, 8 Jan 2021 14:49:12 +0000 Message-ID: Subject: Re: [PATCH 2/2] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Bin Meng Cc: Jean-Christophe Dubois , Alistair Francis , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 14:49:28 -0000 On Thu, 17 Dec 2020 at 05:28, Bin Meng wrote: > > From: Bin Meng > > The endianness of data exchange between tx and rx fifo is incorrect. > Earlier bytes are supposed to show up on MSB and later bytes on LSB, > ie: in big endian. The manual does not explicitly say this, but the > U-Boot and Linux driver codes have a swap on the data transferred > to tx fifo and from rx fifo. To check my understanding, if we have a burst length of 16 bits, say, when we do the fifo32_pop() of a 32 bit word, where in that word and which way round are the 2 bytes we are going to transfer ? > With this change, U-Boot read from / write to SPI flash tests pass. > > => sf test 1ff000 1000 > SPI flash test: > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > Test passed > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Bin Meng > > --- > > hw/ssi/imx_spi.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 509fb9f..71f0902 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -156,13 +156,14 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > { > uint32_t tx; > uint32_t rx; > + uint32_t data; > + uint8_t byte; > > DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n", > fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); > > while (!fifo32_is_empty(&s->tx_fifo)) { > int tx_burst = 0; > - int index = 0; > > if (s->burst_length <= 0) { > s->burst_length = imx_spi_burst_length(s); > @@ -183,10 +184,18 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > tx_burst = 32; > } > > + data = 0; > + for (int i = 0; i < tx_burst / 8; i++) { > + byte = tx & 0xff; > + tx = tx >> 8; > + data = (data << 8) | byte; > + } > + tx = data; > + Why carefully reverse the order of bytes in the word and then take a byte at a time from the bottom of the word in the loop below, when you could change the loop to take bytes from the top of the word instead ? > rx = 0; > > while (tx_burst > 0) { > - uint8_t byte = tx & 0xff; > + byte = tx & 0xff; > > DPRINTF("writing 0x%02x\n", (uint32_t)byte); > > @@ -196,12 +205,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > DPRINTF("0x%02x read\n", (uint32_t)byte); > > tx = tx >> 8; > - rx |= (byte << (index * 8)); > + rx = (rx << 8) | byte; > > /* Remove 8 bits from the actual burst */ > tx_burst -= 8; > s->burst_length -= 8; > - index++; > } > > DPRINTF("data rx:0x%08x\n", rx); > -- > 2.7.4 thanks -- PMM From MAILER-DAEMON Fri Jan 08 10:56:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxu7P-0000OM-G0 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 10:56:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxu7O-0000NC-TN; Fri, 08 Jan 2021 10:56:02 -0500 Received: from mail-yb1-xb2d.google.com ([2607:f8b0:4864:20::b2d]:39092) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxu7N-0001M8-3D; Fri, 08 Jan 2021 10:56:02 -0500 Received: by mail-yb1-xb2d.google.com with SMTP id k4so9772455ybp.6; Fri, 08 Jan 2021 07:55:59 -0800 (PST) DKIM-Signature: v=1; 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Fri, 08 Jan 2021 07:55:59 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> <20201202144523.24526-2-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Fri, 8 Jan 2021 23:55:48 +0800 Message-ID: Subject: Re: [PATCH v2 2/2] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() To: Peter Maydell Cc: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , QEMU Developers , Xuzhou Cheng , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2d; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 15:56:03 -0000 On Fri, Jan 8, 2021 at 10:40 PM Peter Maydell wrote: > > On Wed, 2 Dec 2020 at 14:45, Bin Meng wrote: > > > > From: Xuzhou Cheng > > > > When a write to ECSPI_CONREG register to disable the SPI controller, > > imx_spi_reset() is called to reset the controller, during which CS > > lines should have been disabled, otherwise the state machine of any > > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > > its last state and responds incorrectly to any follow-up commands. > > > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > > Signed-off-by: Xuzhou Cheng > > Signed-off-by: Bin Meng > > Acked-by: Alistair Francis > > > > --- > > > > Changes in v2: > > - Fix the "Fixes" tag in the commit message > > > > hw/ssi/imx_spi.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index e605049a21..85c172e815 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -231,6 +231,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > static void imx_spi_reset(DeviceState *dev) > > { > > IMXSPIState *s = IMX_SPI(dev); > > + int i; > > > > DPRINTF("\n"); > > > > @@ -243,6 +244,10 @@ static void imx_spi_reset(DeviceState *dev) > > > > imx_spi_update_irq(s); > > > > + for (i = 0; i < ECSPI_NUM_CS; i++) { > > + qemu_set_irq(s->cs_lines[i], 1); > > + } > > Calling qemu_set_irq() in a device reset function is a bad > idea, because you don't know whether the thing on the other > end of the IRQ line (a) has already reset before you or > (b) is going to reset after you. If you need to do this then > I think you need to convert this device (and perhaps whatever > it's connected to) to the 3-phase-reset API. (But you probably > don't, see below.) > Thanks for the review. What about the imx_spi_update_irq() in the imx_spi_reset()? Should we remove that from the imx_spi_reset() as well? > Usually the approach is that the device on the other end > of the line is going to reset its state anyway, so there's > no need to actively signal an irq line change. > > If this is required only for the case of "guest requested > a controller reset via the ECSPI_CONREG register" and not > for full system reset, then you can handle that by having > an imx_spi_soft_reset() which calls imx_spi_reset() and then > does the qemu_set_irq() calls, so full system (power-cycle) > reset still goes to imx_spi_reset() but guest-commanded > reset via the register interface calls imx_spi_soft_reset(). > Regards, Bin From MAILER-DAEMON Fri Jan 08 11:00:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxuCA-0005Al-6W for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 11:00:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxuC8-0005A0-EO for qemu-arm@nongnu.org; Fri, 08 Jan 2021 11:00:56 -0500 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]:39778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxuC6-0003AP-GA for qemu-arm@nongnu.org; Fri, 08 Jan 2021 11:00:55 -0500 Received: by mail-ed1-x52e.google.com with SMTP id c7so11672605edv.6 for ; Fri, 08 Jan 2021 08:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=T2Z3JJqh6lJ4+2UuFN+lpZ/yFsy8mzeTUPDi4ohDRp0=; b=cDMIOnPfIKfubaTtfn4xKksco14U2ABle0lZWXSr4YVdwfsB+sXYmM+7EGmcK72xth mbU+/KglcXSH51oxWG6749e/6OCu5idrAFvDask9vAdMKrxTtNFwb6ITwDXdP3D2ATu5 X2wfTdyhcr8JP6/raPXQahawyM/zSqhw34ZqRcZ5nal8lBsFO0yTpJG4vFzd2UWVVvQj xVJa7c64cH5iRrxUjQnkAXVaITmbsJE3RYh1iFuaoR8rwzZ+NoFm88IR7dM4WSkqxb4z PC/TpJNuyKEoeUchnQLLklt/hg26RTUjUUnA5KCNcHEkzwkXJaIsf1GlIZRMdOhSBKPS wi2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=T2Z3JJqh6lJ4+2UuFN+lpZ/yFsy8mzeTUPDi4ohDRp0=; b=CacNLOgwbrlPvSW5NyjAkS5WnqYaooaTUQ/0l0ErH86G2g4mZrcGsoa2ghAETnVohH /D/AK6iqCipJ1k4oouiIkPwrNkYNHAuC7M+qb9TBKxtQacBVDgDZAlckYzYeI2fvxCGo jaHQLS+apGQZhP97f/4DDSj0Qn0vzTAtfBKjpQ80ozuRqjto+fB98h9Utv9daM9QZJYx 1d5ZD+dB1qnTXz7Y4dXgEdEDBWKb7rrt1fKN8iJ2pO7b+GolxLw+O1fNHC+vUv17DKQl 5p41dWk7eGNLNfmSVylg7TuiodLSjIyBXXVdUx6FvDI6NPe96wvRlv8ZnUxQGFHhVVL4 wYlQ== X-Gm-Message-State: AOAM530tyL+pj1mSYxsn2pEKqsERfiObOBTSAndo2s92YHLLQpHIUpIX 1FggylQyogw6SXiFNAcCIy8dxDZaZVZJLzU4G2aMXA== X-Google-Smtp-Source: ABdhPJx0RChmuYNnqZ8wVI9Rykary9rpIRRLdrs6053r8DXoAwd+ROoSSUTY6qniVDiUluOmkf9yibqXg+PY62foH1w= X-Received: by 2002:aa7:cdc3:: with SMTP id h3mr5652445edw.52.1610121652158; Fri, 08 Jan 2021 08:00:52 -0800 (PST) MIME-Version: 1.0 References: <20201202144523.24526-1-bmeng.cn@gmail.com> <20201202144523.24526-2-bmeng.cn@gmail.com> In-Reply-To: From: Peter Maydell Date: Fri, 8 Jan 2021 16:00:40 +0000 Message-ID: Subject: Re: [PATCH v2 2/2] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() To: Bin Meng Cc: Alistair Francis , Jean-Christophe Dubois , Peter Chubb , qemu-arm , QEMU Developers , Xuzhou Cheng , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 16:00:56 -0000 On Fri, 8 Jan 2021 at 15:55, Bin Meng wrote: > > On Fri, Jan 8, 2021 at 10:40 PM Peter Maydell wrote: > > Calling qemu_set_irq() in a device reset function is a bad > > idea, because you don't know whether the thing on the other > > end of the IRQ line (a) has already reset before you or > > (b) is going to reset after you. If you need to do this then > > I think you need to convert this device (and perhaps whatever > > it's connected to) to the 3-phase-reset API. (But you probably > > don't, see below.) > > > > Thanks for the review. What about the imx_spi_update_irq() in the > imx_spi_reset()? Should we remove that from the imx_spi_reset() as > well? Yes, I think so. thanks -- PMM From MAILER-DAEMON Fri Jan 08 12:22:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxvTI-0005MI-Sy for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 12:22:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxvTG-0005Jy-QH for qemu-arm@nongnu.org; Fri, 08 Jan 2021 12:22:43 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:32867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxvTB-0000sD-4u for qemu-arm@nongnu.org; Fri, 08 Jan 2021 12:22:42 -0500 Received: by mail-ed1-x531.google.com with SMTP id j16so12005758edr.0 for ; Fri, 08 Jan 2021 09:22:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=HF4ple/5xnClgAKtApuD8Y+fJ7QJ8R+A0KPk+uOsra4=; b=pqQ2EwNLrRhDpu2CXcIejt1h6rOknYNW5m40LYBglp+UDHQTb08r1gV0CLIMFSHfv2 8IwDDSCElbrp6NySHP82p6uTJjtSbl24WDNA7z3yitayTfpJa69bkdVlfqZhafdo5Lch z0DSqOmrtG1J3KIqU/p+w5KBan5PI2QK+pGHbWMA1fPnG4nAjufA7qDZa+2GbWULLALE ID7BJYKtEQ6YFBPbzy+Y+tIAumzLNlIwWFuj3FldF6ZlluM/LuSD8UqxxNChPqa3dDYA ZHjawLaCVKv6I99Ig/m+FPVMSKhxbZuLz3vp3SSqkOlUbHFKNN63T3xO0Oib4ZZa+Aey 0oUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HF4ple/5xnClgAKtApuD8Y+fJ7QJ8R+A0KPk+uOsra4=; b=GoDGc3PIs06nCDYvqA3eiHu0xdnPlfSaY7yepK/WHE9dCyz54t8qK0PiZUAu/Hc4sh 83o8yepXVxqdian2m3SDTPuo8XMkSgS33ytBn0VJo949fMADm8S+JsL/SDszxvWLfUdy Pd5+MG11w/1iZxq2ZD59BfjphsFuyghh28f2x3WWpgIz0XBW9LZgMbj4OkgtyjzV45b+ 0Wb+gyrtHR6/O/xsRhW9YQC/N9Oy68Rwe6J31M4oegqLotD1Su5Aelk2rY8e0XjKNyP/ ZipVVfMSgyciFHc6NCToYNAF++dsNTx/u77FcvnYX9fprEMvDS98xzZ5NnofoTbTIB7R 9MDw== X-Gm-Message-State: AOAM530VbIaZG2t3XfhocvSrZy7PgXpx30FjQNpXIIr+7kwWAaPfQw+3 j/vjRa7DRindzLlvPks5nptPOBehybSKxLeIt5/aNA== X-Google-Smtp-Source: ABdhPJyDldYlLTF/CLQLkdfkkYFoTRKyCCaQDlhe8ggAieXQT/H6BnX2kZh03oqudMncTR5DfADJPHyg+xUjF0XuAc0= X-Received: by 2002:aa7:c388:: with SMTP id k8mr5962574edq.36.1610126555306; Fri, 08 Jan 2021 09:22:35 -0800 (PST) MIME-Version: 1.0 References: <20201208180118.157911-1-richard.henderson@linaro.org> <20201208180118.157911-25-richard.henderson@linaro.org> <6ff3c7b0-9254-2e36-89e0-e9eb59fd6e7f@linaro.org> In-Reply-To: <6ff3c7b0-9254-2e36-89e0-e9eb59fd6e7f@linaro.org> From: Peter Maydell Date: Fri, 8 Jan 2021 17:22:24 +0000 Message-ID: Subject: Re: [PATCH v2 24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 17:22:43 -0000 On Thu, 7 Jan 2021 at 22:02, Richard Henderson wrote: > > On 1/7/21 7:39 AM, Peter Maydell wrote: > >> + if (align > MO_ALIGN_8) { > >> + t0 = tcg_temp_new_i64(); > >> + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ | align); > >> + tcg_gen_addi_i64(clean_addr, clean_addr, 8); > >> + tcg_gen_addi_ptr(i, i, 8); > >> + tcg_gen_st_i64(t0, cpu_env, vofs); > >> + tcg_temp_free_i64(t0); > >> + align = 0; > >> + } > >> + > > > > Why do we need to do this (and the similar thing in do_str()) ? > > Most of the rest of the patch is fairly clear in that it is just > > passing the alignment requirement through to the load/store fns, > > but this is a bit more opaque to me... > > What follows this context is a single memory access within a tcg loop. > > When align is <= the size of the access, every access can use the same > alignment mop. But for MO_ALIGN_16, since we're emitting 8-byte accesses, the > second access will not be 16-byte aligned. So I peel off one loop iteration at > the beginning to perform the alignment check. OK. Could you add comments to that effect, please? Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 08 13:04:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxw7O-0000K1-LU for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:04:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxw7N-0000Hm-2u for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:09 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55307) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxw7K-0000of-1U for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:08 -0500 Received: by mail-wm1-x32c.google.com with SMTP id c124so8470080wma.5 for ; Fri, 08 Jan 2021 10:04:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=sLl9sUWU5h1UaKwkdvYGg+aIysds12c5wVsNDj2Vf+M=; b=jNl9yJZ7H9EuXoiJUE+GCLCalCIeZA7XK+lgB2M9mdx1MUIBVgm18vzdMOKaOzOEj9 mrLhLKYK/npPjTDe8nC8FunizcZNJ/E3oIpr65nQq40q1OCB0cW+4SH9sm5u8fOcDjak doLX0dyZTytslaClQ86fD8IyStuxIAP/elNFVvq9cuIyx35ehK9AZh/ChAge1O2sizNE p3KkoqFaLV6BlozLRwoPH2CpqXAP2uttsWxAd+zrfCwJaZpujmD6Ql4tu/ujxKWnOYMy B02Stu2tAZAuIoA4YhrubM9ZFTA7OTE0ma++9nIEVt0b3mvqKjrk80Qf7ONLn4juEtnG Qqvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=sLl9sUWU5h1UaKwkdvYGg+aIysds12c5wVsNDj2Vf+M=; b=s9UIOWfLEFjST6wQ5Qb9RMC+6x1qtn7/Zs/7hcbq1iRRXYUyyb/g/HplYwEvvTGs1I Eqznc0mVAY8fxvpoBZm5neliLV29rWS7sjJdde+TKTAXt4coGhC8wfZ+D+HtAy9SwCIA rHZ6pyWHtCu1oy2k6VunSq4hxJfCPv9YHOOYVl8aqgn2thKiGQMf1nw5S/ZHdqz21rtu 7SsT6+bkNIrM3SzaLwa7LDDtL2lWPS6WF0itYI2K4tFaSD3Ftufg91iZ4pPyU5sQ+5pZ UicdADXJwWP65kyNngV/Pd/HQXRFvTruAkcnWPu63y59tdT3ou8uyRwucNZ3BGvPmS2L 8HSw== X-Gm-Message-State: AOAM532TGcUPXwFVZGm+z1fngyJSrE59g1xeH1ib5QtAI7RVj3RDYURS xSIoRbItBcInDSrHkOHR/DXOXtS423chJA== X-Google-Smtp-Source: ABdhPJz9DmDPttTCwS15baNoiSUx8u5O9TxMrQ1/lF3Kr7J7V4BHdmBYyCcezHgjWyMe0hTGsIoiwA== X-Received: by 2002:a1c:a344:: with SMTP id m65mr4059516wme.108.1610129043909; Fri, 08 Jan 2021 10:04:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s1sm13423029wrv.97.2021.01.08.10.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:04:03 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/2] lan9118: Fix RX Status FIFO PEEK value Date: Fri, 8 Jan 2021 18:03:59 +0000 Message-Id: <20210108180401.2263-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:04:09 -0000 This patchset fixes https://bugs.launchpad.net/bugs/1904954 : we give a bogus value for the RX Status FIFO peek register, because of a copy-and-paste error. (This bug has been present since 2009 when the device model was first added.) Patch 1 fixes the bug; patch 2 does a little bit of tidyup while I was looking at this bit of the code. thanks -- PMM Peter Maydell (2): hw/net/lan9118: Fix RX Status FIFO PEEK value hw/net/lan9118: Add symbolic constants for register offsets hw/net/lan9118.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:04:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxw7P-0000MS-IL for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:04:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxw7O-0000K3-La for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:10 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:43624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxw7M-0000pn-1K for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:10 -0500 Received: by mail-wr1-x42f.google.com with SMTP id y17so9828847wrr.10 for ; Fri, 08 Jan 2021 10:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Cltfwd92MkrmvHsb6h8wjp9eDpmVWfQV41adHitKqbs=; b=WWDNZg4XlRJ2pRMkulGUta0K4mI0jBtVsFYEQ6LH0w4kzci3R8+KHuWq0EFKgTCcAh Riaf9sXFozKBE0WusjFJq6QpnHbA+EP0XF8PZI4Yhdak5AOk/cqyAcDTY3qQhcbLpOyl tdUNEEpYcTjL6HYYs3KEqmVnK6CwL0a08o+bwMQSj26rnSNSx0e0w6efMBQ6BSEU4U9I b/kVt/Dxf1QOiEgzBjTjK5NUnTmWCH2bH4+ZWylIu1fNJsyLHcY+uaSR1ABGZMtqp6hs u48Ljkdb0nWSNHGyQ6LGJwgGFjj02C3pxY32oi/888GXDri46n35GLFZ2DDn778Ghq2g TC2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cltfwd92MkrmvHsb6h8wjp9eDpmVWfQV41adHitKqbs=; b=E4Q7+fTfAvNJuqLgjnabzS4NAbMCttBCzMwhqCncpPBK3rco18ABNC0dmwICAqYwQJ Gv0ZioR1Iy5zZ5TDdewFvuhKc0RpmD41tnSLdi44cAL+b96SD6pG7Wn0VVgh/SOWIvLP huvfsQSyBOIzKpumaE8O/qlqRC63j8I4bhjAhWSoaTO7pbcASTWPJavFDZuPjYdy18sK ySzTqdPwiZx8SpVYmqSIKGfEztu7d8O+x0+xwo30GSvZJxvkmIgyZz0BE30s9cmAETyA FG2Qt7lSKx0MSH7tVhfVsREGxp07m2qpxqPaPMC/7jXtQWhjTygVAMkaKjDbuPljVQAW ZWjA== X-Gm-Message-State: AOAM532ysCUOrpW6sNF6tPv4wbPc35+6RnBsiP8shLpS4wnBdaqrKdQF FwRpciJJo67zbb+S4IciQdfXKoEVrANp9g== X-Google-Smtp-Source: ABdhPJxPo1Z8Pih0fRnNAlF7tiD6eiEb4oHHwQo7MQPX6KqzOSbfR6dOQJeqbsbj1Y35iJcROiEelw== X-Received: by 2002:a5d:55c6:: with SMTP id i6mr4767784wrw.137.1610129046389; Fri, 08 Jan 2021 10:04:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s1sm13423029wrv.97.2021.01.08.10.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:04:05 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/net/lan9118: Add symbolic constants for register offsets Date: Fri, 8 Jan 2021 18:04:01 +0000 Message-Id: <20210108180401.2263-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108180401.2263-1-peter.maydell@linaro.org> References: <20210108180401.2263-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:04:10 -0000 The lan9118 code mostly uses symbolic constants for register offsets; the exceptions are those which the datasheet doesn't give an official symbolic name to. Add some names for the registers which don't already have them, based on the longer names they are given in the memory map. Signed-off-by: Peter Maydell --- hw/net/lan9118.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 13d469fe24f..abc796285ab 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -40,6 +40,17 @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) #endif +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ +#define RX_DATA_FIFO_PORT_FIRST 0x00 +#define RX_DATA_FIFO_PORT_LAST 0x1f +#define TX_DATA_FIFO_PORT_FIRST 0x20 +#define TX_DATA_FIFO_PORT_LAST 0x3f + +#define RX_STATUS_FIFO_PORT 0x40 +#define RX_STATUS_FIFO_PEEK 0x44 +#define TX_STATUS_FIFO_PORT 0x48 +#define TX_STATUS_FIFO_PEEK 0x4c + #define CSR_ID_REV 0x50 #define CSR_IRQ_CFG 0x54 #define CSR_INT_STS 0x58 @@ -1020,7 +1031,8 @@ static void lan9118_writel(void *opaque, hwaddr offset, offset &= 0xff; //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); - if (offset >= 0x20 && offset < 0x40) { + if (offset >= TX_DATA_FIFO_PORT_FIRST && + offset <= TX_DATA_FIFO_PORT_LAST) { /* TX FIFO */ tx_fifo_push(s, val); return; @@ -1198,18 +1210,18 @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, lan9118_state *s = (lan9118_state *)opaque; //DPRINTF("Read reg 0x%02x\n", (int)offset); - if (offset < 0x20) { + if (offset <= RX_DATA_FIFO_PORT_LAST) { /* RX FIFO */ return rx_fifo_pop(s); } switch (offset) { - case 0x40: + case RX_STATUS_FIFO_PORT: return rx_status_fifo_pop(s); - case 0x44: + case RX_STATUS_FIFO_PEEK: return s->rx_status_fifo[s->rx_status_fifo_head]; - case 0x48: + case TX_STATUS_FIFO_PORT: return tx_status_fifo_pop(s); - case 0x4c: + case TX_STATUS_FIFO_PEEK: return s->tx_status_fifo[s->tx_status_fifo_head]; case CSR_ID_REV: return 0x01180001; -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:04:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxw7R-0000OW-4o for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:04:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxw7O-0000KG-QS for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:10 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxw7K-0000om-Sw for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:04:10 -0500 Received: by mail-wr1-x429.google.com with SMTP id 91so9851925wrj.7 for ; Fri, 08 Jan 2021 10:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5ppBHYzxmgl5hzoC4HlriYit+ub13d9GiK837Ur2BnM=; b=cYOu5ZhKgHgxLahkRk1JnxBaaA+Cae58P2KvgDh/HGo/HE0eDBuk8Y+iwi/y4invWN 1J20T+rA5UpvgHJmaGQJewAgCnICg8ToikH9EDtD6gGbqJWuQ9X5QKZ5FGgXvwGkxbRt /avwownMSmBSUOp434ehS08Z97XkIpLGIsNvUQU8Vi53Z1/QezIOJXdPfq7YI102kPic Luk3/mV7r5YtRP+LVSivaqOSdLQ8zDK9oLduG4AWgQxo6ckS3qSdYWPbIaNtwkrU3p9l BS6/Hd6jJbP+6jbXwXj8WWFzKjP5sTX0t+WjqRKkveVYqSTu/qwOt5hpTiOSOPzG7joa 2f5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5ppBHYzxmgl5hzoC4HlriYit+ub13d9GiK837Ur2BnM=; b=V9eQ/+FmZitZv/Ah+VLXltsyMCN0gICFLGOYeP6CwiXoc9j2z3dUJMsWAihevD7U1G zJirZdu2TmJOeEi40GtGK1s6SNbclosj0B2orC99UsjnkOBe+Rc+7oMVEdWeM8E9vCJd VVDFz7pLW+JkmmbrgHE/KHr41fnFqgog2zuDGurgzkH3iM6a09dV8iGq8Lj+p2+LMDR/ 8QJbQneeGlRH9SdbmN9Y1h/HAT3Jb7GV2irroX/vhktonvZ17oFed+ac1lHA6/F9j7UK xExp6OZQIl/lacJTCmKc4hSvlgB8TcLPTa7xDK9M5DOC2xZZlgcAJHV46Z1zNWBBkq7E IdFw== X-Gm-Message-State: AOAM533RCboT73rDtYUlGqSyHSVjrWzib/sURwS+oqhT0zvKyoqqb4YG pogD3eKaJJtIOXPGNSjM7mF5FpFuSh6RcQ== X-Google-Smtp-Source: ABdhPJxiedntBPCu418+U3VaeN1srE1PVzk6avlZhNVFua3G5Lj0XroIZHwH3IRes00yNr3yZTzF6Q== X-Received: by 2002:a5d:4f8a:: with SMTP id d10mr4713721wru.219.1610129045021; Fri, 08 Jan 2021 10:04:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id s1sm13423029wrv.97.2021.01.08.10.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:04:04 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/net/lan9118: Fix RX Status FIFO PEEK value Date: Fri, 8 Jan 2021 18:04:00 +0000 Message-Id: <20210108180401.2263-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108180401.2263-1-peter.maydell@linaro.org> References: <20210108180401.2263-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:04:11 -0000 A copy-and-paste error meant that the return value for register offset 0x44 (the RX Status FIFO PEEK register) returned a byte from a bogus offset in the rx status FIFO. Fix the typo. Cc: qemu-stable@nongnu.org Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 Signed-off-by: Peter Maydell --- hw/net/lan9118.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index ab57c02c8e1..13d469fe24f 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1206,7 +1206,7 @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, case 0x40: return rx_status_fifo_pop(s); case 0x44: - return s->rx_status_fifo[s->tx_status_fifo_head]; + return s->rx_status_fifo[s->rx_status_fifo_head]; case 0x48: return tx_status_fifo_pop(s); case 0x4c: -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:13:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwGe-0007Xo-NJ for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:13:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwGZ-0007UA-UG; Fri, 08 Jan 2021 13:13:40 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:42128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwGX-000494-DO; Fri, 08 Jan 2021 13:13:39 -0500 Received: by mail-wr1-x42f.google.com with SMTP id m5so9854584wrx.9; Fri, 08 Jan 2021 10:13:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=etDvuXBAUM11ZaEBnBYy/KiVDdiLH2tl4ZJyUxGTR0E=; b=keXfF6Jy6+xUmQdywT4uR/AB9u9qwxiagwqP7BBlMVNNxlb/RX6OOaJUNJJggtth+G Gvlu2A6C0zkqsAyjjcgKw0rA6TnPIv1EjCoLl8iU88oW1riUHwk0c1Be0WVlG6uNq+QN 8OueFWL+bp2mNzG2VysUpfrmLpjdmXkDflp/0tuA7fBN5bAlELjgjtXHSWnSsfL8212e KmuI52SGsj+XZjAmbWTWxvpOl89nIYxG8VJHSHr/+mRFwcUOact4gtDy7zL5QD7+inrt E79LPDrFIpniFBRHaOF1NrkDWf/bdcw9dQFKI3Mwvx6zTqxVbRV0fv1TRUmrq0MXdt4+ 5GyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=etDvuXBAUM11ZaEBnBYy/KiVDdiLH2tl4ZJyUxGTR0E=; b=JDFzlfiKjsZSlLXlVHWyMhVNP/fKKyL5bBuIylALh6RZXcw2XAsGs/cm7e3bbXlgxQ IAcANCCvgpDefM9I33aptyJxHJWzFk2uyBSYVD5qBzltFBEtlq7SjukYyfhPfKQmCKpn 7B3uTNqTXwA6NyiV3dNku+hH3h1//3kTum7bMeIY1D0jYK+1rxes5KCjKW7aG9uHCaD8 9FM+kKUll/T5i/ytNhFC/+YZLJXc+93lH/VO/evaO2D6genOQrMdzbQoZ4vgibcysRSj 2yt/codA4ZkGo2wxb9VcSHiGFABqXGHzuDbjTmB2AiBmIIyLXvNXCjyjIAQjxWWSeqJz 5JbA== X-Gm-Message-State: AOAM532V4QREk4OU2lW7JpUM3Qr7yu4Yr81aj7tuLOXgaRnSEjkHYPab y15vdrmco+6Q667bV5rrJawBugnIwWI= X-Google-Smtp-Source: ABdhPJzp0dFG+5QMk9DvH0fB3ygRSYd2bo3/0dNdAtgq07gxOTx+TMnaX1HnEngBSce5RY8uROVSKA== X-Received: by 2002:adf:f60b:: with SMTP id t11mr4902941wrp.401.1610129615002; Fri, 08 Jan 2021 10:13:35 -0800 (PST) Received: from [192.168.1.36] (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id a14sm14009127wrn.3.2021.01.08.10.13.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jan 2021 10:13:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 1/2] hw/net/lan9118: Fix RX Status FIFO PEEK value To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210108180401.2263-1-peter.maydell@linaro.org> <20210108180401.2263-2-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 8 Jan 2021 19:13:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210108180401.2263-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.241, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:13:41 -0000 On 1/8/21 7:04 PM, Peter Maydell wrote: > A copy-and-paste error meant that the return value for register offset 0x44 > (the RX Status FIFO PEEK register) returned a byte from a bogus offset in > the rx status FIFO. Fix the typo. Wow, nice catch :) Reviewed-by: Philippe Mathieu-Daudé > Cc: qemu-stable@nongnu.org > Fixes: https://bugs.launchpad.net/qemu/+bug/1904954 > Signed-off-by: Peter Maydell > --- > hw/net/lan9118.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c > index ab57c02c8e1..13d469fe24f 100644 > --- a/hw/net/lan9118.c > +++ b/hw/net/lan9118.c > @@ -1206,7 +1206,7 @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, > case 0x40: > return rx_status_fifo_pop(s); > case 0x44: > - return s->rx_status_fifo[s->tx_status_fifo_head]; > + return s->rx_status_fifo[s->rx_status_fifo_head]; > case 0x48: > return tx_status_fifo_pop(s); > case 0x4c: > From MAILER-DAEMON Fri Jan 08 13:16:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwJ7-0000Zy-7t for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:16:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwIy-0000Yi-QQ; Fri, 08 Jan 2021 13:16:10 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:35481) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwIx-00058q-DA; Fri, 08 Jan 2021 13:16:08 -0500 Received: by mail-wm1-x335.google.com with SMTP id e25so9223237wme.0; Fri, 08 Jan 2021 10:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=kzW+etdvWCxLvil8pyMDDG+XQ0COh7mraCS06TiMlQo=; b=rPxwEtKl5X2ES8OdMBh3M43QyJn7qvrwbZRI+9RbAHrTlYrBzd4LuLco08OoQhnjTG mgZgY24rnM/lyvW7wtyC+yhDiQqP3rnl6Ajf99ejz0smdp8tQG9I4iX+pLpbYIC8eYDa hdpp7wmPVEXHBW23VoIBwtAvNc2IDuuoqSARyVwlS2CIiA6GbJVDamylEQAhe6LHjRh8 5ABd4eshyhjwpilcN54XD4+/FpXsKP5xwW1PvuhfuVuR/o/6NypQr3XOruXjqL0UsYSU VEZE2RmmPyVcEpZa4YAjCY6Qcn5leZ2WDJj4ZR3Idok/ExVORp5yJeVJvg0uD9GIL0kA msiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=kzW+etdvWCxLvil8pyMDDG+XQ0COh7mraCS06TiMlQo=; b=STJn958BNod7w3czjbBxrj2zszO6gkns+ZF6hx4ORBPXQMoLWs+QxRD0r2uCYpQBbS r3v7ThkxTiWt9p9TaTbx9D5hnC1kVi7bPh2KpjiRj7ukiCU8qd2icsqxpirkkUx5Q+jg 4MCvFVDsuRBC0Nq6eTEb70y3Gz/m/TZeYaS9ZGcYQEI+izX3U74q02dpNVr8XU3ODWfx DzPJIDwta00q0VxIr28oLg2goxNddRk4BGVzEjijk/KALfJnHOyMawCG0fO73PMOIlhn g/A8VzyymIYO22/KhZCf6HUg6mhfVSNWIryMeN+vpFauhBNJOLmlHIOuALp4MIJCe8Xs 7ECA== X-Gm-Message-State: AOAM532ats1KyIdw0LL44cfBlB7Hf7j1vX5jSN0XRpPc6yN4EspcrXB9 wBOYiJ5ydmmqPXefGyAJb55uk3rPYEQ= X-Google-Smtp-Source: ABdhPJyeKi4FC5pRgnnJuTkiVTgJh3qpllLZKQeokr+WGasxdfO2T+bDVDgB0/suwymO6DY+a1kRzw== X-Received: by 2002:a1c:6741:: with SMTP id b62mr4150526wmc.21.1610129765304; Fri, 08 Jan 2021 10:16:05 -0800 (PST) Received: from [192.168.1.36] (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id s13sm14823188wra.53.2021.01.08.10.16.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jan 2021 10:16:04 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 2/2] hw/net/lan9118: Add symbolic constants for register offsets To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210108180401.2263-1-peter.maydell@linaro.org> <20210108180401.2263-3-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 8 Jan 2021 19:16:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210108180401.2263-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.241, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:16:12 -0000 On 1/8/21 7:04 PM, Peter Maydell wrote: > The lan9118 code mostly uses symbolic constants for register offsets; > the exceptions are those which the datasheet doesn't give an official > symbolic name to. > > Add some names for the registers which don't already have them, based > on the longer names they are given in the memory map. > > Signed-off-by: Peter Maydell > --- > hw/net/lan9118.c | 24 ++++++++++++++++++------ > 1 file changed, 18 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Fri Jan 08 13:52:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwrg-00023U-42 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwrf-00022a-91 for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:51:59 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50260) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwrd-0000sB-CH for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:51:58 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 190so8615677wmz.0 for ; Fri, 08 Jan 2021 10:51:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AcoXdrrQcxeAFhHhxtwxElcM60mUZAzjqTpSoPTvLh4=; b=hC4C6LQOdtDEKJXxG2+zbxD2AnHBsOEWwTjrveojRTVMyNpC/pMXz/tXE9r61Jo2jR HjfUfKSBAPdotbHCvEBKBhccltfTZNZIzP30dO+fItSR+7Mh82vuoDzJTlvht/Mor+Qy AwNuUSzbkmARxV+ijLdQc+ftUoQ38iebVWJ1zxgCjOFq3adUzgXyedWJIz6YBpRV3gd3 z3l10EmvjfA1thHZcGnQv8mRpYDKYCNefm4AtZl1SR08uDteDcM3JVSQdwEhchyyBKvM HUJPytFPWVISAhUa3Z+5F5H4qTf17c+2WJJ1KcJgDXivbOyZbcRAMjmfxoeF0GRIIQVH C0rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AcoXdrrQcxeAFhHhxtwxElcM60mUZAzjqTpSoPTvLh4=; b=VaiXLzoulftg3b9bbJaILMsGVxX60Hk4J2547gnmLUp0tSJFEUPnOrZBmzcmFl5sMp kAkgfEPSWbuNJ5R1P63JeNPhFaok2b7JF2v9hsGKyOh0kLkJ/HYB/qnvKfXNEl8xd7hj EENKRIfiVilZYzNr6dxlyJ3QHqZ1UaMpYrgVIB3yePqjfr22+Xvy79Sg2RC2tTisiHPa aYJ0fEfc4bvCl1cqQgHrJ5B4eaZ9LbOrYWXME4BD88+vCUlC4nfwbr7l6UUZ0YxnMEvY nu2qEmAmXFJp0ZrGRd7yPfULJrDcxOh19sRXrqj+47h63NWGHmxSP6co7GauZqAD7bh2 oyaQ== X-Gm-Message-State: AOAM5313EfTIAnlMzHJhudVjQZnUnLhIF7qj1V46MR/egcSQp8D7o6Ab hAWPPR5SzanT5G7svAZfY03cYw== X-Google-Smtp-Source: ABdhPJw4J5/wIw14t3OegeqZ7NZITGqmwyv2z9qxBBW73HJwpF8RynBbcyiNllyPzbatJTVMiI/7Cg== X-Received: by 2002:a05:600c:2f17:: with SMTP id r23mr4239075wmn.157.1610131915578; Fri, 08 Jan 2021 10:51:55 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:55 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues Subject: [PATCH v3 0/6] target/arm: various changes to cpu.h Date: Fri, 8 Jan 2021 18:51:48 +0000 Message-Id: <20210108185154.8108-1-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=leif@nuviainc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:51:59 -0000 First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS). Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined by the ARM ARM. Third, add field definitions for CLIDR (excepting the Ttype fields, since I was unsure of prefererred naming - Ttype7-Ttype1?). Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c, Lastly, add all ID_ (aarch32) registers/fields. Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be submitting shortly, and some of those features also exist for aarch32. v2->v3: - Add missing R-b tags. - Add separate definition for CCSIDR_EL1 fields when FEAT_CCIDX implemented. - Add patch extending also ARMCPU.ctr to 64-bit. - Rebase to current master. v1->v2: - Correct CCSIDR_EL1 field sizes in 3/5. - Rebase to current master. Leif Lindholm (6): target/arm: fix typo in cpu.h ID_AA64PFR1 field name target/arm: make ARMCPU.clidr 64-bit target/arm: make ARMCPU.ctr 64-bit target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h target/arm: add aarch64 ID register fields to cpu.h target/arm: add aarch32 ID register fields to cpu.h target/arm/cpu.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 3 deletions(-) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwrg-00025C-U9 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwrg-00023Z-4w for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:00 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:34992) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwrd-0000sq-PL for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:51:59 -0500 Received: by mail-wr1-x431.google.com with SMTP id r3so9987606wrt.2 for ; Fri, 08 Jan 2021 10:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E6mZPiQraiTh4Bg0YyL1OAnwyrTn4m3pw4jIvmfgdr8=; b=OJtJfz2cno5qxT9BC/EfF1BoMXPJV/wgmu3AliPwQcl5NOwQ8v19EwpX0Rw2IWjnza D9akoSh28WwyLxMt1qbJKIKD1rswYXBddIaeQoojzGjJ3mcafi/p191MezPgw/pqpnMy aqhVOf6cfgwB5I5vZKCcRMmJb6XFOotPYV21BrOrE1l3arg0OMltz7uSzp3xwmIzuheC FMOihFoj4osKVy7PbkJViSUB264+2WlqBPH8n5iWfyx8eDpmmjTPUSAwCZgEjxALZJYJ QqLt1UJ+6soELKCmN14DDMe5nu7sZeqczdkgOJ1yZafAR8R17mMLop+MLJx2A0jcUByS bcKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E6mZPiQraiTh4Bg0YyL1OAnwyrTn4m3pw4jIvmfgdr8=; b=Yw8lPFgAiy72ga87p2JWMSiYYWI1oqTHmxSena/PN7T9oMNdSYffxyCV/PVGsh6jgk cThQFQB/kMhTHjVaQIX0rhwEljgsBSZDulM8vuz84k44BR7MNdz/eiKvzG24UXauOsMz 5nkTKBml0HP5iW64CRFGnlEN9zupIASJRRdEKJGuGmWjcOtevcHsge1hDerz2fyQ5g9/ eC8MQzEEfGo/GONUHGSXwv5VlCOAQhuwiebyBuM0VZ9DXkKFnVa4gO9zjrFmcBx77MES uB4u2M2nT1AsUYAYVqbPAqbogQgDLFxoLWIDcRP2h/hkC1vZeEziTs7C6WbnEjNHp3Bs NZRQ== X-Gm-Message-State: AOAM530l9STaQRoJmE+HB4V9m+xe1MCreJtd1ca39wK+9fwR/SScZCs/ D9MnfKnf8KBkPZIw7s/ZZsO/ow== X-Google-Smtp-Source: ABdhPJxloU63I2rkd2m8M+5YYjgCB64+oQ5QRSDFapKBOcG26ZuE+fJxXbu/dy3V7mHlVF7lUiWHew== X-Received: by 2002:adf:f6cc:: with SMTP id y12mr4967155wrp.35.1610131916364; Fri, 08 Jan 2021 10:51:56 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:55 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 1/6] target/arm: fix typo in cpu.h ID_AA64PFR1 field name Date: Fri, 8 Jan 2021 18:51:49 +0000 Message-Id: <20210108185154.8108-2-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=leif@nuviainc.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:00 -0000 SBSS -> SSBS Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..5e3cf77ec7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1883,7 +1883,7 @@ FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) FIELD(ID_AA64PFR1, BT, 0, 4) -FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwri-00026w-77 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwrg-00024t-OF for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:00 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:39185) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwre-0000tM-Pp for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:00 -0500 Received: by mail-wr1-x431.google.com with SMTP id c5so9947065wrp.6 for ; Fri, 08 Jan 2021 10:51:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=His0BTVqpkxUWnuh2zB20a08QgRZucIAGlzkuVBHQw8=; b=NpxhsKMmh298L34oB2RbvEmviBUMbnsGzkA0xxITwvtMV4o8n6HoSQppY+lp4BR80T DBX0LNTENyUFFrAFoBWWMHvoa8Ixipz8mH4aPVWjmtrQFYMfX7l8Fq8PMtBZhw1ZKyX9 tn+EDJ1kWOTy+mNYSdwcZ9Jqhy6mbOTfRPICJDntXjwwcT/ho4EdYUEd8xXaByF6PAW2 6gkfGWn0l5xbur/Y7+z/4nK+gk4hkoA2ht9BGhu7F3W10bFlCeqhqJoeSfTr1lGJB7/T kn2lQ5FvAoJqjKKjaaXeHL+5rYb5NecXrukSsUpAEI3LSImBznkOMl/o7UEKJaTrsddk hWzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=His0BTVqpkxUWnuh2zB20a08QgRZucIAGlzkuVBHQw8=; b=jfZsCeI6r6CdXrgRGBGCfTARl1Y+L1dCEXHXVpNwotrOYTAAdVuY5pTJrWFzrqOwfh LQXCaPpSibAajQWMpUcJ1Hg3B9vw/mryjBLjiuZ3YUwgEcmPL7scYS7X0SMaH+GgY3ly rOGIDqxyfPMRVLA4O4LHxBtma3tpDMVThP39l2D6+OivepK5SF21sjOxQb60NZ/CVoFg qGeRDhggWr6pKXrqdE89dkZtjcSJIPG1CmWw3OW7D9H8uZ+QhbrEKMGTusEHpw95aWpl cAS2twctWzml/S4Oy7cEpQlu64cnKewiKILVcvNLbYtt7M/YhByaNqUMlvuBcTze7ZAV 4lEQ== X-Gm-Message-State: AOAM533sNSexD07l2vtQPQNOmg3llitUwVHLViJxdH4ht3vW3PAT14FM VFfdmrJXHb9XafyVBvaDC5aD9w== X-Google-Smtp-Source: ABdhPJzIIQftpfU779wAGJgK6CwRkHCv2kkoYPCblbsKhpZelMBNDbxICxG4cUQKICWQOE+nrz3wJg== X-Received: by 2002:a5d:4c4e:: with SMTP id n14mr5039201wrt.209.1610131917585; Fri, 08 Jan 2021 10:51:57 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:56 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 2/6] target/arm: make ARMCPU.clidr 64-bit Date: Fri, 8 Jan 2021 18:51:50 +0000 Message-Id: <20210108185154.8108-3-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=leif@nuviainc.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:01 -0000 The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e3cf77ec7..fadd1a47df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwrl-000291-1K for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwrh-00026Q-SN for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:01 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39989) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwrf-0000tU-Nf for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:01 -0500 Received: by mail-wr1-x430.google.com with SMTP id 91so9969657wrj.7 for ; Fri, 08 Jan 2021 10:51:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2hPNMUgLjGsZrofLM5ryEx3n5GB4TeZrlJdrp1nvvfk=; b=refXlTezGFlTShhI14ujOQG2wRkydbRfMU1xpG2mLGK0IDxt30Iu6spwWEmDtqNBCN rlTnUriaKdxckSpcOTwMHRosc/gQ7cOVDPwZOZLLbPZ2wDqLPOGgbIuOn0GrerN7Ua+0 TYYwV6UtJg+7yhTese+eP3oUc7UHkOlOSqs8UgiIjbwK58y0ao1t2DYak0wv9A3oiovg qEifirTyi9juzBwucnY5D5FVXAoYMProqX7vK0HQS52JqHX0x5Ul98cguXSQwhbhHZX0 BnpfI+BB++rXsZM9HuO7gtLURS1Sc+vup2T5cZ9HONVMcZKAjsi43K+9xeaV5QlSg4iw uQxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2hPNMUgLjGsZrofLM5ryEx3n5GB4TeZrlJdrp1nvvfk=; b=Egd083/midEMmI6wrR5K28NxZm0290OUYEa731jo+jSwkqZm85bn8A3xlsokZ/GaY+ 1nwMamPVWl/i0v9o6zCTT4x9r661A/l+Ph2xrVQbK8kiUIIkk+nAe8I+Gj2qjYEgHlia UUyRQeHygjmRjp+ZobrvBSuFWalQ8YBL7uw1lfgZQxkbVaxaWc4n9tJlE1rdkPi9mAOa zpafHWz/9/kFUg7A/q0kSH9pBg6qbDgpjIV3UCcy82z0G0936NQdZmqk0HMSX5fiArXb yy0rCxTdNt/DV9dutxdalsKqHbVBKDAWCLmPnCSh6d5Ke3CNb+AO1DKuJ416mC4yDuzf niLA== X-Gm-Message-State: AOAM5333sPo3Kh2tvwuiSBfgB5zUzYawGNcnUI4bKFJ+eDf6CEwryLlw r9KZEZ3f7+ObYBi5WOk2uEfl/Q== X-Google-Smtp-Source: ABdhPJyDH7b4UK5Hn5qzzQQor/2N0wRAoAmoGNgBjgAsX8opPc324S1Su4XyxMGNWpmSbKR6lkXlVQ== X-Received: by 2002:adf:b519:: with SMTP id a25mr4908777wrd.263.1610131918416; Fri, 08 Jan 2021 10:51:58 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:58 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues Subject: [PATCH v3 3/6] target/arm: make ARMCPU.ctr 64-bit Date: Fri, 8 Jan 2021 18:51:51 +0000 Message-Id: <20210108185154.8108-4-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=leif@nuviainc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:02 -0000 When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the TminLine field in bits [37:32]. Extend the ctr field to be able to hold this context. Signed-off-by: Leif Lindholm --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fadd1a47df..063228de2a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -931,7 +931,7 @@ struct ARMCPU { uint64_t midr; uint32_t revidr; uint32_t reset_fpsid; - uint32_t ctr; + uint64_t ctr; uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwro-0002B3-Q1 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwri-00026d-3F for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:02 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:38475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwrg-0000tw-Im for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:01 -0500 Received: by mail-wr1-x431.google.com with SMTP id r7so9956210wrc.5 for ; Fri, 08 Jan 2021 10:52:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=puA6/puXorIWl8XVvGX9+7qdGtTAWfovzDg6hzeCqzU=; b=e+Y85H6iaUqPYHcxfNj7Djbm2xfNZwQsFBtoS82ht05TZkYZXVOO8TDYK6/day16BG k9mfawz3IrR9ymxLsklYsJgJWy/U0+1DK455mnAQYNgmqgyGlCgGjwkIho53xzEIWnsE Wkm5ow5ImbRAUwaMgQzNC3PvzWysDAn9LNe909u+IITIdnX1OokLEkO0vFDoZEZ4Qfji OQbm+sOKEQ8rpyfEanmoNlW3Jol/uS7Ngkrbt6TKWDzjXt6F3O6wABPTcfMNSH0hPXqp Lw6ulIesFrTm5yymV8pUJgZ5VZT2MG55UscNpivESY1IkTi4fKf1ifSU4DOtEpU5AuGp vpwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=puA6/puXorIWl8XVvGX9+7qdGtTAWfovzDg6hzeCqzU=; b=iI1nnkIuEwUq2t4Zweha7sbWOwaHeLZtrLKw+NSpz14zME0BsmR7S3dHwEx97zkobp TfihAVWLP0Djn7NKPH4TMmrv2uaYOPy1ZY2xs5KxK5F+aVdpIm0mj+/5QYtPhY0z6dAW 72frg49Rl4+VbyZ1ZF1rUlhX/kesSqtLY72P+67HUP4y9LxVysV5/uXzqJBSb5SEpMvi 9YnuldqtT9yOW/pJFzpIqGTeidoxYl9hPTku+cgVAa1HDsiFXgmVGL3QXlrNPdlmRFTN TnvuvfX/rIxonKK7bFugOHUjov4ik1UniJJAh1aikiyGkjHItdNuym1ry+uAi3vZjrsQ iANQ== X-Gm-Message-State: AOAM5320dk9gh8K5sApmEUxjLUsMoSKYmHplDizZpKwfURMLq5UldUdQ nqdmEpWiwA3mi9A0yD8iAYro7A== X-Google-Smtp-Source: ABdhPJwQmo8WCGXwztg+movEQFMWwlVZODimGGFInmo09t9NDOVp6HwanSIq25wtXVg3UFclM9fEAw== X-Received: by 2002:a5d:6708:: with SMTP id o8mr4970661wru.64.1610131919324; Fri, 08 Jan 2021 10:51:59 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:58 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues Subject: [PATCH v3 4/6] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h Date: Fri, 8 Jan 2021 18:51:52 +0000 Message-Id: <20210108185154.8108-5-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=leif@nuviainc.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:02 -0000 Signed-off-by: Leif Lindholm --- target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 063228de2a..18c1cb02bb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1736,6 +1736,37 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) /* * System register ID fields. */ +FIELD(CLIDR_EL1, CTYPE1, 0, 3) +FIELD(CLIDR_EL1, CTYPE2, 3, 3) +FIELD(CLIDR_EL1, CTYPE3, 6, 3) +FIELD(CLIDR_EL1, CTYPE4, 9, 3) +FIELD(CLIDR_EL1, CTYPE5, 12, 3) +FIELD(CLIDR_EL1, CTYPE6, 15, 3) +FIELD(CLIDR_EL1, CTYPE7, 18, 3) +FIELD(CLIDR_EL1, LOUIS, 21, 3) +FIELD(CLIDR_EL1, LOC, 24, 3) +FIELD(CLIDR_EL1, LOUU, 27, 3) +FIELD(CLIDR_EL1, ICB, 30, 3) + +/* When FEAT_CCIDX is implemented */ +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) + +/* When FEAT_CCIDX is not implemented */ +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) + +FIELD(CTR_EL0, IMINLINE, 0, 4) +FIELD(CTR_EL0, L1IP, 14, 2) +FIELD(CTR_EL0, DMINLINE, 16, 4) +FIELD(CTR_EL0, ERG, 20, 4) +FIELD(CTR_EL0, CWG, 24, 4) +FIELD(CTR_EL0, IDC, 28, 1) +FIELD(CTR_EL0, DIC, 29, 1) +FIELD(CTR_EL0, TMINLINE, 32, 6) + FIELD(MIDR_EL1, REVISION, 0, 4) FIELD(MIDR_EL1, PARTNUM, 4, 12) FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwrq-0002En-6F for mharc-qemu-arm@gnu.org; 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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:52:00 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues Subject: [PATCH v3 6/6] target/arm: add aarch32 ID register fields to cpu.h Date: Fri, 8 Jan 2021 18:51:54 +0000 Message-Id: <20210108185154.8108-7-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=leif@nuviainc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:06 -0000 Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8300341a26..af3cce51f4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1830,6 +1830,8 @@ FIELD(ID_ISAR6, DP, 4, 4) FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_ISAR6, BF16, 20, 4) +FIELD(ID_ISAR6, I8MM, 24, 4) FIELD(ID_MMFR0, VMSA, 0, 4) FIELD(ID_MMFR0, PMSA, 4, 4) @@ -1840,6 +1842,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4) FIELD(ID_MMFR0, FCSE, 24, 4) FIELD(ID_MMFR0, INNERSHR, 28, 4) +FIELD(ID_MMFR1, L1HVDVA, 0, 4) +FIELD(ID_MMFR1, L1UNIVA, 4, 4) +FIELD(ID_MMFR1, L1HVDSW, 8, 4) +FIELD(ID_MMFR1, L1UNISW, 12, 4) +FIELD(ID_MMFR1, L1HVD, 16, 4) +FIELD(ID_MMFR1, L1UNI, 20, 4) +FIELD(ID_MMFR1, L1TSTCLN, 24, 4) +FIELD(ID_MMFR1, BPRED, 28, 4) + +FIELD(ID_MMFR2, L1HVDFG, 0, 4) +FIELD(ID_MMFR2, L1HVDBG, 4, 4) +FIELD(ID_MMFR2, L1HVDRNG, 8, 4) +FIELD(ID_MMFR2, HVDTLB, 12, 4) +FIELD(ID_MMFR2, UNITLB, 16, 4) +FIELD(ID_MMFR2, MEMBARR, 20, 4) +FIELD(ID_MMFR2, WFISTALL, 24, 4) +FIELD(ID_MMFR2, HWACCFLG, 28, 4) + FIELD(ID_MMFR3, CMAINTVA, 0, 4) FIELD(ID_MMFR3, CMAINTSW, 4, 4) FIELD(ID_MMFR3, BPMAINT, 8, 4) @@ -1858,6 +1878,8 @@ FIELD(ID_MMFR4, LSM, 20, 4) FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) +FIELD(ID_MMFR5, ETS, 0, 4) + FIELD(ID_PFR0, STATE0, 0, 4) FIELD(ID_PFR0, STATE1, 4, 4) FIELD(ID_PFR0, STATE2, 8, 4) @@ -1876,6 +1898,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4) FIELD(ID_PFR1, VIRT_FRAC, 24, 4) FIELD(ID_PFR1, GIC, 28, 4) +FIELD(ID_PFR2, CSV3, 0, 4) +FIELD(ID_PFR2, SSBS, 4, 4) +FIELD(ID_PFR2, RAS_FRAC, 8, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) @@ -1990,6 +2016,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) +FIELD(ID_DFR1, MTPMU, 0, 4) + FIELD(DBGDIDR, SE_IMP, 12, 1) FIELD(DBGDIDR, NSUHD_IMP, 14, 1) FIELD(DBGDIDR, VERSION, 16, 4) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 13:52:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxwrq-0002Fc-DV for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 13:52:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34238) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxwrl-00028v-0l for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:06 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33495) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxwrh-0000un-Jl for qemu-arm@nongnu.org; Fri, 08 Jan 2021 13:52:02 -0500 Received: by mail-wr1-x42d.google.com with SMTP id t30so9998124wrb.0 for ; Fri, 08 Jan 2021 10:52:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jBQ465cDwNWEY9JJSZIV4j2V7wZd54tnbvPI3yNzMNM=; b=vp8OfeqfLFLbNMdMqRns1yMGUKLSVz72PkW0vPlqPz+zSbelo1mAwvheuK0x1g3Qm8 DhTzu5SRn9sDQ8rQG0ZeEMc7F71HZcOUqJlfZNoavr1eNWi1impQYbIWpiC4foH4aBR0 R8pUpQJNrYroeIEm5f9sV7YLEJFL3fvRSqoI/t2k5pV/DRt5SMZteQt42a6zWRulw6c2 HVAWYMfhnac/i2tSMHOPlIj71yAa1S1kmaFCG+Gx/m9i31mbY5Nbnn8pYHbdYxFnX1kM FdGUvV0wjxLxtSLTfgbkK2AhHosiv+Uh+wdzd0zNT7MrjCa57B8lTeaRhXVMmvWN7Km1 CnlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jBQ465cDwNWEY9JJSZIV4j2V7wZd54tnbvPI3yNzMNM=; b=Q79rjXxoII0r0dYXy3v1RJPOSpp+0iqa/h/V6nt177xHMi6gPIixK7sLkC3bmZQl0C XJOrFzzBrTbUhhq4SLlEW8FaukHEdBSLqVv9Vk0l63dUjQlXVlKD+72J1g1FysUbJNf3 RRAuaKIF2k/2Zpb+YFdv6X8vpwU+MAx4FBuWkknhzPJk6lhvjXgdd2/QKIKxx4cEzuTP OOUVATU2V1PPUNzS2Ksb0yjbGqmOkrP3TkX4xIol4VbPXaz63l0RdpAiohIfnt79Asi5 cjORAhSFXizGkQSo0lLvguF5FklaAXMPH/yARUbBuAZ2W6se2U9tlkAIf7GfSlqI6+Kd ZP1Q== X-Gm-Message-State: AOAM530XApv39OqGRg4kALQBt/UjwRYZDuWjUYxqw8tyfPlqSag5j17H E85HyrgKsIistfQI1nXVS2hh7LIGpO4gGMSG X-Google-Smtp-Source: ABdhPJzfkIZajyWZeL8HXTDvZ8uh/X3BLIwLvouG0MAAjsbreM98XYXMAXFMpexX175bIpnHRL+udQ== X-Received: by 2002:a05:6000:14b:: with SMTP id r11mr5090150wrx.53.1610131920213; Fri, 08 Jan 2021 10:52:00 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:59 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Laurent Desnogues Subject: [PATCH v3 5/6] target/arm: add aarch64 ID register fields to cpu.h Date: Fri, 8 Jan 2021 18:51:53 +0000 Message-Id: <20210108185154.8108-6-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 18:52:06 -0000 Add entries present in ARM DDI 0487F.c (August 2020). Signed-off-by: Leif Lindholm Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18c1cb02bb..8300341a26 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1902,6 +1902,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4) FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) FIELD(ID_AA64ISAR1, SB, 36, 4) FIELD(ID_AA64ISAR1, SPECRES, 40, 4) +FIELD(ID_AA64ISAR1, BF16, 44, 4) +FIELD(ID_AA64ISAR1, DGH, 48, 4) +FIELD(ID_AA64ISAR1, I8MM, 52, 4) FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -1912,11 +1915,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, SEL2, 36, 4) +FIELD(ID_AA64PFR0, MPAM, 40, 4) +FIELD(ID_AA64PFR0, AMU, 44, 4) +FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -1930,6 +1940,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) FIELD(ID_AA64MMFR0, EXS, 44, 4) +FIELD(ID_AA64MMFR0, FGT, 56, 4) +FIELD(ID_AA64MMFR0, ECV, 60, 4) FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) @@ -1939,6 +1951,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4) FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR1, TWED, 32, 4) +FIELD(ID_AA64MMFR1, ETS, 36, 4) FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -1965,6 +1979,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, MTPMU, 48, 4) FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) -- 2.20.1 From MAILER-DAEMON Fri Jan 08 14:03:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx2k-0007Js-Vp for mharc-qemu-arm@gnu.org; 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boundary="0000000000008c909e05b86835e9" Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -179 X-Spam_score: -18.0 X-Spam_bar: ------------------ X-Spam_report: (-18.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:03:25 -0000 --0000000000008c909e05b86835e9 Content-Type: text/plain; charset="UTF-8" On Fri, Jan 8, 2021 at 10:54 AM Leif Lindholm wrote: > When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the > TminLine field in bits [37:32]. > Extend the ctr field to be able to hold this context. > > Signed-off-by: Leif Lindholm > Reviewed-by: Hao Wu > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index fadd1a47df..063228de2a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -931,7 +931,7 @@ struct ARMCPU { > uint64_t midr; > uint32_t revidr; > uint32_t reset_fpsid; > - uint32_t ctr; > + uint64_t ctr; > uint32_t reset_sctlr; > uint64_t pmceid0; > uint64_t pmceid1; > -- > 2.20.1 > > > --0000000000008c909e05b86835e9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Fri, Jan 8, 2021 at 10:54 AM Leif = Lindholm <leif@nuviainc.com>= wrote:
When FEA= T_MTE is implemented, the AArch64 view of CTR_EL0 adds the
TminLine field in bits [37:32].
Extend the ctr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Ha= o Wu <wuhaotsh@google.com>= =C2=A0
---
=C2=A0target/arm/cpu.h | 2 +-
=C2=A01 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..063228de2a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -931,7 +931,7 @@ struct ARMCPU {
=C2=A0 =C2=A0 =C2=A0uint64_t midr;
=C2=A0 =C2=A0 =C2=A0uint32_t revidr;
=C2=A0 =C2=A0 =C2=A0uint32_t reset_fpsid;
-=C2=A0 =C2=A0 uint32_t ctr;
+=C2=A0 =C2=A0 uint64_t ctr;
=C2=A0 =C2=A0 =C2=A0uint32_t reset_sctlr;
=C2=A0 =C2=A0 =C2=A0uint64_t pmceid0;
=C2=A0 =C2=A0 =C2=A0uint64_t pmceid1;
--
2.20.1


--0000000000008c909e05b86835e9-- From MAILER-DAEMON Fri Jan 08 14:10:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9F-0000v8-4s for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Cq74XwgKCE8DByr5A9yx55x2v.t537v3B-r83454x4B.58x@flex--wuhaotsh.bounces.google.com>) id 1kxx9E-0000uj-2J for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:08 -0500 Received: from mail-qt1-x84a.google.com ([2607:f8b0:4864:20::84a]:39922) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Cq74XwgKCE8DByr5A9yx55x2v.t537v3B-r83454x4B.58x@flex--wuhaotsh.bounces.google.com>) id 1kxx9B-00078y-Kx for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:07 -0500 Received: by mail-qt1-x84a.google.com with SMTP id m21so4926305qtp.6 for ; Fri, 08 Jan 2021 11:10:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:message-id:mime-version:subject:from:to:cc; bh=nHvdj59Ch2nmxrN2pE7SpwLDq8+oyR7alTPwtuKq8zk=; b=ICYEggskogiqhQPO+dRrONig2qf/wuOO6Hyfc5e8i0kweIMWAyMN4K7qkWN8hJj7gq Utk7DmX+Z3/0/BhjdzR08b0I2xtzySjRqJTB8leb6mosku6ON2QQkujw8LX7Ifr7mc4c YZ4FlatTebmWeSGZigPCzMJ0pINeKDpL8aedcYEqAyTSdy89Evq0/Vfgy+4NneDmmPgF YwRAgRDKVYr/vq+BBhctEK13SKVQxH6JVm0lQ/VNGKfySnlRBzJDLpIDYRR6AmFoS9Ry IpDd3u+ktPFmii23T/oFPCHc5UImQTalqHHXODzOVrCIyhkZF0NjDFMTWz0UlUj/4exh hjVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:message-id:mime-version:subject:from :to:cc; bh=nHvdj59Ch2nmxrN2pE7SpwLDq8+oyR7alTPwtuKq8zk=; b=qiU9hg9bYL6zukV8Kwb5ukjbDYT4qXVpbG/hjWA8y+rgUnT1TPamwCiZ4hCxcNyqyw Ts9mSB2QS9xwuxjL36hMeawBlWYUJFLTwdGP82YNi7M64Eq6Aav2uz0oAtCG23/57KbH 7TfsQhRrqqr8d4lqWtZNe3yQXdYfZw6L77AKlzoQ0eb812/I95jBvxMOEcBTCb/Z1kgs SP893BYE/pN/qUi1cWJo8MjiKkpLxx/GtO/UD+cG6ozX5Df4Uz1UlXCWVArtCgboYezs DzeFfuF9YZd4tXVMjpuMThLUVdOyaE5aYl6v+Prinu1UOthsC7LA6LZU6LqgLNgZvcub xwlw== X-Gm-Message-State: AOAM533uj+XKSY+0rCRLY1qa/6acWTH5D6M5xQAiDt89Rv+hU1mJt+E5 XvKfcqx8pgXUBQRrcrf/hiAi/9KJxRJKfg== X-Google-Smtp-Source: ABdhPJyO0P8T5+J8H0cKDZvp4scnplV5z9iYKr63PAlvcr4CP2PygqOEywp+Yh0iYbCjCIEg4El/gRzKN4KFKA== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:ad4:46cb:: with SMTP id g11mr4883888qvw.42.1610133002990; Fri, 08 Jan 2021 11:10:02 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:39 -0800 Message-Id: <20210108190945.949196-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 0/6] Additional NPCM7xx devices From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::84a; envelope-from=3Cq74XwgKCE8DByr5A9yx55x2v.t537v3B-r83454x4B.58x@flex--wuhaotsh.bounces.google.com; helo=mail-qt1-x84a.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:08 -0000 This patch series include a few more NPCM7XX devices including - Analog Digital Converter (ADC) - Pulse Width Modulation (PWM) We also modified the CLK module to generate clock values using qdev_clock. These clocks are used to determine various clocks in NPCM7XX devices. Thank you for your review. Changes since v4: - Use clock_ticks_to_ns to compute clock time in nanoseconds. (Didn't apply to PWM patch since it requires a frequency as output.) - Removed reset_timer and resets immediately in ADC patch. - Removed "qemu/osdep.h" from headers and include them in .c files. - Use REG32 for register fields. - Fix a g_assert that a guest can trigger with incorrect input. Changes since v3: - Use type casting instead of accessing parent object in all devices. Changes since v2: - Split PWM test into a separate patch in the patch set - Add trace events for PWM's update_freq/update_duty - Add trace events for ioread/iowrite in ADC and PWM - Use timer_get_ns in hw/timer/npcm7xx_timer.c - Update commit message in ADC/PWM to mention qom-get/set method for usage - Fix typos Changes since v1: - We removed the IPMI and KCS related code from this patch set. Hao Wu (6): hw/misc: Add clock converter in NPCM7XX CLK module hw/timer: Refactor NPCM7XX Timer to use CLK clock hw/adc: Add an ADC module for NPCM7XX hw/misc: Add a PWM module for NPCM7XX hw/misc: Add QTest for NPCM7XX PWM Module hw/*: Use type casting for SysBusDevice in NPCM7XX docs/system/arm/nuvoton.rst | 4 +- hw/adc/meson.build | 1 + hw/adc/npcm7xx_adc.c | 301 ++++++++++++ hw/adc/trace-events | 5 + hw/arm/npcm7xx.c | 55 ++- hw/arm/npcm7xx_boards.c | 2 +- hw/mem/npcm7xx_mc.c | 2 +- hw/misc/meson.build | 1 + hw/misc/npcm7xx_clk.c | 797 ++++++++++++++++++++++++++++++- hw/misc/npcm7xx_gcr.c | 2 +- hw/misc/npcm7xx_pwm.c | 550 +++++++++++++++++++++ hw/misc/npcm7xx_rng.c | 2 +- hw/misc/trace-events | 6 + hw/nvram/npcm7xx_otp.c | 2 +- hw/ssi/npcm7xx_fiu.c | 2 +- hw/timer/npcm7xx_timer.c | 39 +- include/hw/adc/npcm7xx_adc.h | 69 +++ include/hw/arm/npcm7xx.h | 4 + include/hw/misc/npcm7xx_clk.h | 146 +++++- include/hw/misc/npcm7xx_pwm.h | 105 ++++ include/hw/timer/npcm7xx_timer.h | 1 + meson.build | 1 + tests/qtest/meson.build | 4 +- tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++ tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++ 25 files changed, 2920 insertions(+), 48 deletions(-) create mode 100644 hw/adc/npcm7xx_adc.c create mode 100644 hw/adc/trace-events create mode 100644 hw/misc/npcm7xx_pwm.c create mode 100644 include/hw/adc/npcm7xx_adc.h create mode 100644 include/hw/misc/npcm7xx_pwm.h create mode 100644 tests/qtest/npcm7xx_adc-test.c create mode 100644 tests/qtest/npcm7xx_pwm-test.c -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:10:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9f-000185-SK for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3IK74XwgKCGUZXKDRWVKJRRJOH.FRPTHPX-DUPQRQJQX.RUJ@flex--wuhaotsh.bounces.google.com>) id 1kxx9e-00017I-BA for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:34 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]:36579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3IK74XwgKCGUZXKDRWVKJRRJOH.FRPTHPX-DUPQRQJQX.RUJ@flex--wuhaotsh.bounces.google.com>) id 1kxx9X-0007K3-RG for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:34 -0500 Received: by mail-pj1-x1049.google.com with SMTP id q10so7545007pjg.1 for ; Fri, 08 Jan 2021 11:10:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=0mxuQctenD5q3cEFitgZ8dhJ0SSY9BkENI18PY6j88g=; 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Fri, 08 Jan 2021 11:10:24 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:40 -0800 In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> Message-Id: <20210108190945.949196-2-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 1/6] hw/misc: Add clock converter in NPCM7XX CLK module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3IK74XwgKCGUZXKDRWVKJRRJOH.FRPTHPX-DUPQRQJQX.RUJ@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:34 -0000 This patch allows NPCM7XX CLK module to compute clocks that are used by other NPCM7XX modules. Add a new struct NPCM7xxClockConverterState which represents a single converter. Each clock converter in CLK module represents one converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter takes one or more input clocks and converts them into one output clock. They form a clock hierarchy in the CLK module and are responsible for outputing clocks for various other modules in an NPCM7XX SoC. Each converter has a function pointer called "convert" which represents the unique logic for that converter. The clock contains two initialization information: ConverterInitInfo and ConverterConnectionInfo. They represent the vertices and edges in the clock diagram respectively. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm7xx_clk.c | 795 +++++++++++++++++++++++++++++++++- include/hw/misc/npcm7xx_clk.h | 140 +++++- 2 files changed, 927 insertions(+), 8 deletions(-) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 6732437fe2..48bc9bdda5 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -18,6 +18,7 @@ #include "hw/misc/npcm7xx_clk.h" #include "hw/timer/npcm7xx_timer.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -27,9 +28,22 @@ #include "trace.h" #include "sysemu/watchdog.h" +/* + * The reference clock hz, and the SECCNT and CNTR25M registers in this module, + * is always 25 MHz. + */ +#define NPCM7XX_CLOCK_REF_HZ (25000000) + +/* Register Field Definitions */ +#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ + #define PLLCON_LOKI BIT(31) #define PLLCON_LOKS BIT(30) #define PLLCON_PWDEN BIT(12) +#define PLLCON_FBDV(con) extract32((con), 16, 12) +#define PLLCON_OTDV2(con) extract32((con), 13, 3) +#define PLLCON_OTDV1(con) extract32((con), 8, 3) +#define PLLCON_INDV(con) extract32((con), 0, 6) enum NPCM7xxCLKRegisters { NPCM7XX_CLK_CLKEN1, @@ -89,12 +103,609 @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = { [NPCM7XX_CLK_AHBCKFI] = 0x000000c8, }; -/* Register Field Definitions */ -#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */ - /* The number of watchdogs that can trigger a reset. */ #define NPCM7XX_NR_WATCHDOGS (3) +/* Clock converter functions */ + +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll" +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \ + (obj), TYPE_NPCM7XX_CLOCK_PLL) +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel" +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \ + (obj), TYPE_NPCM7XX_CLOCK_SEL) +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider" +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \ + (obj), TYPE_NPCM7XX_CLOCK_DIVIDER) + +static void npcm7xx_clk_update_pll(void *opaque) +{ + NPCM7xxClockPLLState *s = opaque; + uint32_t con = s->clk->regs[s->reg]; + uint64_t freq; + + /* The PLL is grounded if it is not locked yet. */ + if (con & PLLCON_LOKI) { + freq = clock_get_hz(s->clock_in); + freq *= PLLCON_FBDV(con); + freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con); + } else { + freq = 0; + } + + clock_update_hz(s->clock_out, freq); +} + +static void npcm7xx_clk_update_sel(void *opaque) +{ + NPCM7xxClockSELState *s = opaque; + uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, + s->len); + + if (index >= s->input_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SEL index: %u out of range\n", + __func__, index); + index = 0; + } + clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); +} + +static void npcm7xx_clk_update_divider(void *opaque) +{ + NPCM7xxClockDividerState *s = opaque; + uint32_t freq; + + freq = s->divide(s); + clock_update_hz(s->clock_out, freq); +} + +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) / s->divisor; +} + +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) / + (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); +} + +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s) +{ + return divide_by_reg_divisor(s) / 2; +} + +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s) +{ + return clock_get_hz(s->clock_in) >> + extract32(s->clk->regs[s->reg], s->offset, s->len); +} + +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg) +{ + switch (reg) { + case NPCM7XX_CLK_PLLCON0: + return NPCM7XX_CLOCK_PLL0; + case NPCM7XX_CLK_PLLCON1: + return NPCM7XX_CLOCK_PLL1; + case NPCM7XX_CLK_PLLCON2: + return NPCM7XX_CLOCK_PLL2; + case NPCM7XX_CLK_PLLCONG: + return NPCM7XX_CLOCK_PLLG; + default: + g_assert_not_reached(); + } +} + +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) +{ + int i; + + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + npcm7xx_clk_update_pll(&clk->plls[i]); + } +} + +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) +{ + int i; + + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + npcm7xx_clk_update_sel(&clk->sels[i]); + } +} + +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) +{ + int i; + + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + npcm7xx_clk_update_divider(&clk->dividers[i]); + } +} + +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) +{ + clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); + npcm7xx_clk_update_all_plls(clk); + npcm7xx_clk_update_all_sels(clk); + npcm7xx_clk_update_all_dividers(clk); +} + +/* Types of clock sources. */ +typedef enum ClockSrcType { + CLKSRC_REF, + CLKSRC_PLL, + CLKSRC_SEL, + CLKSRC_DIV, +} ClockSrcType; + +typedef struct PLLInitInfo { + const char *name; + ClockSrcType src_type; + int src_index; + int reg; + const char *public_name; +} PLLInitInfo; + +typedef struct SELInitInfo { + const char *name; + uint8_t input_size; + ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT]; + int src_index[NPCM7XX_CLK_SEL_MAX_INPUT]; + int offset; + int len; + const char *public_name; +} SELInitInfo; + +typedef struct DividerInitInfo { + const char *name; + ClockSrcType src_type; + int src_index; + uint32_t (*divide)(NPCM7xxClockDividerState *s); + int reg; /* not used when type == CONSTANT */ + int offset; /* not used when type == CONSTANT */ + int len; /* not used when type == CONSTANT */ + int divisor; /* used only when type == CONSTANT */ + const char *public_name; +} DividerInitInfo; + +static const PLLInitInfo pll_init_info_list[] = { + [NPCM7XX_CLOCK_PLL0] = { + .name = "pll0", + .src_type = CLKSRC_REF, + .reg = NPCM7XX_CLK_PLLCON0, + }, + [NPCM7XX_CLOCK_PLL1] = { + .name = "pll1", + .src_type = CLKSRC_REF, + .reg = NPCM7XX_CLK_PLLCON1, + }, + [NPCM7XX_CLOCK_PLL2] = { + .name = "pll2", + .src_type = CLKSRC_REF, + .reg = NPCM7XX_CLK_PLLCON2, + }, + [NPCM7XX_CLOCK_PLLG] = { + .name = "pllg", + .src_type = CLKSRC_REF, + .reg = NPCM7XX_CLK_PLLCONG, + }, +}; + +static const SELInitInfo sel_init_info_list[] = { + [NPCM7XX_CLOCK_PIXCKSEL] = { + .name = "pixcksel", + .input_size = 2, + .src_type = {CLKSRC_PLL, CLKSRC_REF}, + .src_index = {NPCM7XX_CLOCK_PLLG, 0}, + .offset = 5, + .len = 1, + .public_name = "pixel-clock", + }, + [NPCM7XX_CLOCK_MCCKSEL] = { + .name = "mccksel", + .input_size = 4, + .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF, + /*MCBPCK, shouldn't be used in normal operation*/ + CLKSRC_REF}, + .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0}, + .offset = 12, + .len = 2, + .public_name = "mc-phy-clock", + }, + [NPCM7XX_CLOCK_CPUCKSEL] = { + .name = "cpucksel", + .input_size = 4, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, + /*SYSBPCK, shouldn't be used in normal operation*/ + CLKSRC_REF}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0}, + .offset = 0, + .len = 2, + .public_name = "system-clock", + }, + [NPCM7XX_CLOCK_CLKOUTSEL] = { + .name = "clkoutsel", + .input_size = 5, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, + CLKSRC_PLL, CLKSRC_DIV}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2}, + .offset = 18, + .len = 3, + .public_name = "tock", + }, + [NPCM7XX_CLOCK_UARTCKSEL] = { + .name = "uartcksel", + .input_size = 4, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset = 8, + .len = 2, + }, + [NPCM7XX_CLOCK_TIMCKSEL] = { + .name = "timcksel", + .input_size = 4, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset = 14, + .len = 2, + }, + [NPCM7XX_CLOCK_SDCKSEL] = { + .name = "sdcksel", + .input_size = 4, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset = 6, + .len = 2, + }, + [NPCM7XX_CLOCK_GFXMSEL] = { + .name = "gfxmksel", + .input_size = 2, + .src_type = {CLKSRC_REF, CLKSRC_PLL}, + .src_index = {0, NPCM7XX_CLOCK_PLL2}, + .offset = 21, + .len = 1, + }, + [NPCM7XX_CLOCK_SUCKSEL] = { + .name = "sucksel", + .input_size = 4, + .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV}, + .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, + NPCM7XX_CLOCK_PLL2D2}, + .offset = 10, + .len = 2, + }, +}; + +static const DividerInitInfo divider_init_info_list[] = { + [NPCM7XX_CLOCK_PLL1D2] = { + .name = "pll1d2", + .src_type = CLKSRC_PLL, + .src_index = NPCM7XX_CLOCK_PLL1, + .divide = divide_by_constant, + .divisor = 2, + }, + [NPCM7XX_CLOCK_PLL2D2] = { + .name = "pll2d2", + .src_type = CLKSRC_PLL, + .src_index = NPCM7XX_CLOCK_PLL2, + .divide = divide_by_constant, + .divisor = 2, + }, + [NPCM7XX_CLOCK_MC_DIVIDER] = { + .name = "mc-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_MCCKSEL, + .divide = divide_by_constant, + .divisor = 2, + .public_name = "mc-clock" + }, + [NPCM7XX_CLOCK_AXI_DIVIDER] = { + .name = "axi-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_CPUCKSEL, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 0, + .len = 1, + .public_name = "clk2" + }, + [NPCM7XX_CLOCK_AHB_DIVIDER] = { + .name = "ahb-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AXI_DIVIDER, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 26, + .len = 2, + .public_name = "clk4" + }, + [NPCM7XX_CLOCK_AHB3_DIVIDER] = { + .name = "ahb3-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 6, + .len = 5, + .public_name = "ahb3-spi3-clock" + }, + [NPCM7XX_CLOCK_SPI0_DIVIDER] = { + .name = "spi0-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV3, + .offset = 6, + .len = 5, + .public_name = "spi0-clock", + }, + [NPCM7XX_CLOCK_SPIX_DIVIDER] = { + .name = "spix-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV3, + .offset = 1, + .len = 5, + .public_name = "spix-clock", + }, + [NPCM7XX_CLOCK_APB1_DIVIDER] = { + .name = "apb1-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 24, + .len = 2, + .public_name = "apb1-clock", + }, + [NPCM7XX_CLOCK_APB2_DIVIDER] = { + .name = "apb2-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 26, + .len = 2, + .public_name = "apb2-clock", + }, + [NPCM7XX_CLOCK_APB3_DIVIDER] = { + .name = "apb3-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 28, + .len = 2, + .public_name = "apb3-clock", + }, + [NPCM7XX_CLOCK_APB4_DIVIDER] = { + .name = "apb4-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 30, + .len = 2, + .public_name = "apb4-clock", + }, + [NPCM7XX_CLOCK_APB5_DIVIDER] = { + .name = "apb5-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_AHB_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 22, + .len = 2, + .public_name = "apb5-clock", + }, + [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = { + .name = "clkout-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_CLKOUTSEL, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 16, + .len = 5, + .public_name = "clkout", + }, + [NPCM7XX_CLOCK_UART_DIVIDER] = { + .name = "uart-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_UARTCKSEL, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 16, + .len = 5, + .public_name = "uart-clock", + }, + [NPCM7XX_CLOCK_TIMER_DIVIDER] = { + .name = "timer-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_TIMCKSEL, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 21, + .len = 5, + .public_name = "timer-clock", + }, + [NPCM7XX_CLOCK_ADC_DIVIDER] = { + .name = "adc-divider", + .src_type = CLKSRC_DIV, + .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER, + .divide = shift_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 28, + .len = 3, + .public_name = "adc-clock", + }, + [NPCM7XX_CLOCK_MMC_DIVIDER] = { + .name = "mmc-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_SDCKSEL, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV1, + .offset = 11, + .len = 5, + .public_name = "mmc-clock", + }, + [NPCM7XX_CLOCK_SDHC_DIVIDER] = { + .name = "sdhc-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_SDCKSEL, + .divide = divide_by_reg_divisor_times_2, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 0, + .len = 4, + .public_name = "sdhc-clock", + }, + [NPCM7XX_CLOCK_GFXM_DIVIDER] = { + .name = "gfxm-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_GFXMSEL, + .divide = divide_by_constant, + .divisor = 3, + .public_name = "gfxm-clock", + }, + [NPCM7XX_CLOCK_UTMI_DIVIDER] = { + .name = "utmi-divider", + .src_type = CLKSRC_SEL, + .src_index = NPCM7XX_CLOCK_SUCKSEL, + .divide = divide_by_reg_divisor, + .reg = NPCM7XX_CLK_CLKDIV2, + .offset = 8, + .len = 5, + .public_name = "utmi-clock", + }, +}; + +static void npcm7xx_clk_pll_init(Object *obj) +{ + NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj); + + pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", + npcm7xx_clk_update_pll, pll); + pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); +} + +static void npcm7xx_clk_sel_init(Object *obj) +{ + int i; + NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); + + for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), + g_strdup_printf("clock-in[%d]", i), + npcm7xx_clk_update_sel, sel); + } + sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); +} +static void npcm7xx_clk_divider_init(Object *obj) +{ + NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj); + + div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", + npcm7xx_clk_update_divider, div); + div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); +} + +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, + NPCM7xxCLKState *clk, const PLLInitInfo *init_info) +{ + pll->name = init_info->name; + pll->clk = clk; + pll->reg = init_info->reg; + if (init_info->public_name != NULL) { + qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, + NPCM7xxCLKState *clk, const SELInitInfo *init_info) +{ + int input_size = init_info->input_size; + + sel->name = init_info->name; + sel->clk = clk; + sel->input_size = init_info->input_size; + g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT); + sel->offset = init_info->offset; + sel->len = init_info->len; + if (init_info->public_name != NULL) { + qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, + NPCM7xxCLKState *clk, const DividerInitInfo *init_info) +{ + div->name = init_info->name; + div->clk = clk; + + div->divide = init_info->divide; + if (div->divide == divide_by_constant) { + div->divisor = init_info->divisor; + } else { + div->reg = init_info->reg; + div->offset = init_info->offset; + div->len = init_info->len; + } + if (init_info->public_name != NULL) { + qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), + init_info->public_name); + } +} + +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, + int index) +{ + switch (type) { + case CLKSRC_REF: + return clk->clkref; + case CLKSRC_PLL: + return clk->plls[index].clock_out; + case CLKSRC_SEL: + return clk->sels[index].clock_out; + case CLKSRC_DIV: + return clk->dividers[index].clock_out; + default: + g_assert_not_reached(); + } +} + +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) +{ + int i, j; + Clock *src; + + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, + pll_init_info_list[i].src_index); + clock_set_source(clk->plls[i].clock_in, src); + } + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + for (j = 0; j < sel_init_info_list[i].input_size; ++j) { + src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j], + sel_init_info_list[i].src_index[j]); + clock_set_source(clk->sels[i].clock_in[j], src); + } + } + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, + divider_init_info_list[i].src_index); + clock_set_source(clk->dividers[i].clock_in, src); + } +} + static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) { uint32_t reg = offset / sizeof(uint32_t); @@ -129,7 +740,7 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) * * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000. */ - value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ; + value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; break; default: @@ -183,6 +794,20 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset, value |= (value & PLLCON_LOKS); } } + /* Only update PLL when it is locked. */ + if (value & PLLCON_LOKI) { + npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); + } + break; + + case NPCM7XX_CLK_CLKSEL: + npcm7xx_clk_update_all_sels(s); + break; + + case NPCM7XX_CLK_CLKDIV1: + case NPCM7XX_CLK_CLKDIV2: + case NPCM7XX_CLK_CLKDIV3: + npcm7xx_clk_update_all_dividers(s); break; case NPCM7XX_CLK_CNTR25M: @@ -234,6 +859,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) case RESET_TYPE_COLD: memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + npcm7xx_clk_update_all_clocks(s); return; } @@ -245,6 +871,42 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) __func__, type); } +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) +{ + int i; + + s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL); + + /* First pass: init all converter modules */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list) + != NPCM7XX_CLOCK_NR_DIVIDERS); + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + object_initialize_child(OBJECT(s), pll_init_info_list[i].name, + &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); + npcm7xx_init_clock_pll(&s->plls[i], s, + &pll_init_info_list[i]); + } + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + object_initialize_child(OBJECT(s), sel_init_info_list[i].name, + &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); + npcm7xx_init_clock_sel(&s->sels[i], s, + &sel_init_info_list[i]); + } + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + object_initialize_child(OBJECT(s), divider_init_info_list[i].name, + &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); + npcm7xx_init_clock_divider(&s->dividers[i], s, + ÷r_init_info_list[i]); + } + + /* Second pass: connect converter modules */ + npcm7xx_connect_clocks(s); + + clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); +} + static void npcm7xx_clk_init(Object *obj) { NPCM7xxCLKState *s = NPCM7XX_CLK(obj); @@ -252,21 +914,114 @@ static void npcm7xx_clk_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, TYPE_NPCM7XX_CLK, 4 * KiB); sysbus_init_mmio(&s->parent, &s->iomem); +} + +static int npcm7xx_clk_post_load(void *opaque, int version_id) +{ + if (version_id >= 1) { + NPCM7xxCLKState *clk = opaque; + + npcm7xx_clk_update_all_clocks(clk); + } + + return 0; +} + +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) +{ + int i; + NPCM7xxCLKState *s = NPCM7XX_CLK(dev); + qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); + npcm7xx_clk_init_clock_hierarchy(s); + + /* Realize child devices */ + for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) { + if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { + return; + } + } + for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) { + if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { + return; + } + } + for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) { + if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { + return; + } + } } -static const VMStateDescription vmstate_npcm7xx_clk = { - .name = "npcm7xx-clk", +static const VMStateDescription vmstate_npcm7xx_clk_pll = { + .name = "npcm7xx-clock-pll", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_clk_sel = { + .name = "npcm7xx-clock-sel", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState, + NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_clk_divider = { + .name = "npcm7xx-clock-divider", .version_id = 0, .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_clk = { + .name = "npcm7xx-clk", + .version_id = 1, + .minimum_version_id = 1, + .post_load = npcm7xx_clk_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), VMSTATE_INT64(ref_ns, NPCM7xxCLKState), + VMSTATE_CLOCK(clkref, NPCM7xxCLKState), VMSTATE_END_OF_LIST(), }, }; +static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx Clock PLL Module"; + dc->vmsd = &vmstate_npcm7xx_clk_pll; +} + +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx Clock SEL Module"; + dc->vmsd = &vmstate_npcm7xx_clk_sel; +} + +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx Clock Divider Module"; + dc->vmsd = &vmstate_npcm7xx_clk_divider; +} + static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) { ResettableClass *rc = RESETTABLE_CLASS(klass); @@ -276,9 +1031,34 @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) dc->desc = "NPCM7xx Clock Control Registers"; dc->vmsd = &vmstate_npcm7xx_clk; + dc->realize = npcm7xx_clk_realize; rc->phases.enter = npcm7xx_clk_enter_reset; } +static const TypeInfo npcm7xx_clk_pll_info = { + .name = TYPE_NPCM7XX_CLOCK_PLL, + .parent = TYPE_DEVICE, + .instance_size = sizeof(NPCM7xxClockPLLState), + .instance_init = npcm7xx_clk_pll_init, + .class_init = npcm7xx_clk_pll_class_init, +}; + +static const TypeInfo npcm7xx_clk_sel_info = { + .name = TYPE_NPCM7XX_CLOCK_SEL, + .parent = TYPE_DEVICE, + .instance_size = sizeof(NPCM7xxClockSELState), + .instance_init = npcm7xx_clk_sel_init, + .class_init = npcm7xx_clk_sel_class_init, +}; + +static const TypeInfo npcm7xx_clk_divider_info = { + .name = TYPE_NPCM7XX_CLOCK_DIVIDER, + .parent = TYPE_DEVICE, + .instance_size = sizeof(NPCM7xxClockDividerState), + .instance_init = npcm7xx_clk_divider_init, + .class_init = npcm7xx_clk_divider_class_init, +}; + static const TypeInfo npcm7xx_clk_info = { .name = TYPE_NPCM7XX_CLK, .parent = TYPE_SYS_BUS_DEVICE, @@ -289,6 +1069,9 @@ static const TypeInfo npcm7xx_clk_info = { static void npcm7xx_clk_register_type(void) { + type_register_static(&npcm7xx_clk_pll_info); + type_register_static(&npcm7xx_clk_sel_info); + type_register_static(&npcm7xx_clk_divider_info); type_register_static(&npcm7xx_clk_info); } type_init(npcm7xx_clk_register_type); diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h index 2338fbbdb5..f641f95f3e 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm7xx_clk.h @@ -17,6 +17,7 @@ #define NPCM7XX_CLK_H #include "exec/memory.h" +#include "hw/clock.h" #include "hw/sysbus.h" /* @@ -33,16 +34,151 @@ #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" -typedef struct NPCM7xxCLKState { +/* Maximum amount of clock inputs in a SEL module. */ +#define NPCM7XX_CLK_SEL_MAX_INPUT 5 + +/* PLLs in CLK module. */ +typedef enum NPCM7xxClockPLL { + NPCM7XX_CLOCK_PLL0, + NPCM7XX_CLOCK_PLL1, + NPCM7XX_CLOCK_PLL2, + NPCM7XX_CLOCK_PLLG, + NPCM7XX_CLOCK_NR_PLLS, +} NPCM7xxClockPLL; + +/* SEL/MUX in CLK module. */ +typedef enum NPCM7xxClockSEL { + NPCM7XX_CLOCK_PIXCKSEL, + NPCM7XX_CLOCK_MCCKSEL, + NPCM7XX_CLOCK_CPUCKSEL, + NPCM7XX_CLOCK_CLKOUTSEL, + NPCM7XX_CLOCK_UARTCKSEL, + NPCM7XX_CLOCK_TIMCKSEL, + NPCM7XX_CLOCK_SDCKSEL, + NPCM7XX_CLOCK_GFXMSEL, + NPCM7XX_CLOCK_SUCKSEL, + NPCM7XX_CLOCK_NR_SELS, +} NPCM7xxClockSEL; + +/* Dividers in CLK module. */ +typedef enum NPCM7xxClockDivider { + NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */ + NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */ + NPCM7XX_CLOCK_MC_DIVIDER, + NPCM7XX_CLOCK_AXI_DIVIDER, + NPCM7XX_CLOCK_AHB_DIVIDER, + NPCM7XX_CLOCK_AHB3_DIVIDER, + NPCM7XX_CLOCK_SPI0_DIVIDER, + NPCM7XX_CLOCK_SPIX_DIVIDER, + NPCM7XX_CLOCK_APB1_DIVIDER, + NPCM7XX_CLOCK_APB2_DIVIDER, + NPCM7XX_CLOCK_APB3_DIVIDER, + NPCM7XX_CLOCK_APB4_DIVIDER, + NPCM7XX_CLOCK_APB5_DIVIDER, + NPCM7XX_CLOCK_CLKOUT_DIVIDER, + NPCM7XX_CLOCK_UART_DIVIDER, + NPCM7XX_CLOCK_TIMER_DIVIDER, + NPCM7XX_CLOCK_ADC_DIVIDER, + NPCM7XX_CLOCK_MMC_DIVIDER, + NPCM7XX_CLOCK_SDHC_DIVIDER, + NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */ + NPCM7XX_CLOCK_UTMI_DIVIDER, + NPCM7XX_CLOCK_NR_DIVIDERS, +} NPCM7xxClockConverter; + +typedef struct NPCM7xxCLKState NPCM7xxCLKState; + +/** + * struct NPCM7xxClockPLLState - A PLL module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @clock_in: The input clock of this module. + * @clock_out: The output clock of this module. + * @reg: The control registers for this PLL module. + */ +typedef struct NPCM7xxClockPLLState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + Clock *clock_in; + Clock *clock_out; + + int reg; +} NPCM7xxClockPLLState; + +/** + * struct NPCM7xxClockSELState - A SEL module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @input_size: The size of inputs of this module. + * @clock_in: The input clocks of this module. + * @clock_out: The output clocks of this module. + * @offset: The offset of this module in the control register. + * @len: The length of this module in the control register. + */ +typedef struct NPCM7xxClockSELState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + uint8_t input_size; + Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; + Clock *clock_out; + + int offset; + int len; +} NPCM7xxClockSELState; + +/** + * struct NPCM7xxClockDividerState - A Divider module in CLK module. + * @name: The name of the module. + * @clk: The CLK module that owns this module. + * @clock_in: The input clock of this module. + * @clock_out: The output clock of this module. + * @divide: The function the divider uses to divide the input. + * @reg: The index of the control register that contains the divisor. + * @offset: The offset of the divisor in the control register. + * @len: The length of the divisor in the control register. + * @divisor: The divisor for a constant divisor + */ +typedef struct NPCM7xxClockDividerState { + DeviceState parent; + + const char *name; + NPCM7xxCLKState *clk; + Clock *clock_in; + Clock *clock_out; + + uint32_t (*divide)(struct NPCM7xxClockDividerState *s); + union { + struct { + int reg; + int offset; + int len; + }; + int divisor; + }; +} NPCM7xxClockDividerState; + +struct NPCM7xxCLKState { SysBusDevice parent; MemoryRegion iomem; + /* Clock converters */ + NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; + NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; + NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; + uint32_t regs[NPCM7XX_CLK_NR_REGS]; /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ int64_t ref_ns; -} NPCM7xxCLKState; + + /* The incoming reference clock. */ + Clock *clkref; +}; #define TYPE_NPCM7XX_CLK "npcm7xx-clk" #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:10:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9l-0001AV-G4 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Ia74XwgKCGYaYLESXWLKSSKPI.GSQUIQY-EVQRSRKRY.SVK@flex--wuhaotsh.bounces.google.com>) id 1kxx9h-00018i-PQ for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:38 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]:46180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Ia74XwgKCGYaYLESXWLKSSKPI.GSQUIQY-EVQRSRKRY.SVK@flex--wuhaotsh.bounces.google.com>) id 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<20210108190945.949196-3-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3Ia74XwgKCGYaYLESXWLKSSKPI.GSQUIQY-EVQRSRKRY.SVK@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:39 -0000 This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 5 ++++ hw/timer/npcm7xx_timer.c | 39 +++++++++++++++----------------- include/hw/misc/npcm7xx_clk.h | 6 ----- include/hw/timer/npcm7xx_timer.h | 1 + 4 files changed, 24 insertions(+), 27 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 47e2b6fc40..fabfb1697b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -22,6 +22,7 @@ #include "hw/char/serial.h" #include "hw/loader.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/units.h" @@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) int first_irq; int j; + /* Connect the timer clock. */ + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "timer-clock")); + sysbus_realize(sbd, &error_abort); sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index d24445bd6e..36e2c07db2 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -17,8 +17,8 @@ #include "qemu/osdep.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" -#include "hw/misc/npcm7xx_clk.h" #include "hw/timer/npcm7xx_timer.h" #include "migration/vmstate.h" #include "qemu/bitops.h" @@ -128,23 +128,18 @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) /* Convert a timer cycle count to a time interval in nanoseconds. */ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) { - int64_t ns = count; + int64_t ticks = count; - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; - ns *= npcm7xx_tcsr_prescaler(t->tcsr); + ticks *= npcm7xx_tcsr_prescaler(t->tcsr); - return ns; + return clock_ticks_to_ns(t->ctrl->clock, ticks); } /* Convert a time interval in nanoseconds to a timer cycle count. */ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) { - int64_t count; - - count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); - count /= npcm7xx_tcsr_prescaler(t->tcsr); - - return count; + return ns / clock_ticks_to_ns(t->ctrl->clock, + npcm7xx_tcsr_prescaler(t->tcsr)); } static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) @@ -166,8 +161,8 @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, int64_t cycles) { - uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t); - int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles; + int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); + int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); /* * The reset function always clears the current timer. The caller of the @@ -176,7 +171,6 @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, */ npcm7xx_timer_clear(&t->base_timer); - ns *= prescaler; t->base_timer.remaining_ns = ns; } @@ -606,10 +600,11 @@ static void npcm7xx_timer_hold_reset(Object *obj) qemu_irq_lower(s->watchdog_timer.irq); } -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) +static void npcm7xx_timer_init(Object *obj) { - NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev); - SysBusDevice *sbd = &s->parent; + NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); + DeviceState *dev = DEVICE(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); int i; NPCM7xxWatchdogTimer *w; @@ -627,11 +622,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) npcm7xx_watchdog_timer_expired, w); sysbus_init_irq(sbd, &w->irq); - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, TYPE_NPCM7XX_TIMER, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_out_named(dev, &w->reset_signal, NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); + s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); } static const VMStateDescription vmstate_npcm7xx_base_timer = { @@ -675,10 +671,11 @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { .name = "npcm7xx-timer-ctrl", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, NPCM7xxTimer), @@ -697,7 +694,6 @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); dc->desc = "NPCM7xx Timer Controller"; - dc->realize = npcm7xx_timer_realize; dc->vmsd = &vmstate_npcm7xx_timer_ctrl; rc->phases.enter = npcm7xx_timer_enter_reset; rc->phases.hold = npcm7xx_timer_hold_reset; @@ -708,6 +704,7 @@ static const TypeInfo npcm7xx_timer_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(NPCM7xxTimerCtrlState), .class_init = npcm7xx_timer_class_init, + .instance_init = npcm7xx_timer_init, }; static void npcm7xx_timer_register_type(void) diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h index f641f95f3e..d5c8d16ca4 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm7xx_clk.h @@ -20,12 +20,6 @@ #include "hw/clock.h" #include "hw/sysbus.h" -/* - * The reference clock frequency for the timer modules, and the SECCNT and - * CNTR25M registers in this module, is always 25 MHz. - */ -#define NPCM7XX_TIMER_REF_HZ (25000000) - /* * Number of registers in our device state structure. Don't change this without * incrementing the version_id in the vmstate. diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h index 6993fd723a..d45c051b56 100644 --- a/include/hw/timer/npcm7xx_timer.h +++ b/include/hw/timer/npcm7xx_timer.h @@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState { uint32_t tisr; + Clock *clock; NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; NPCM7xxWatchdogTimer watchdog_timer; }; -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:10:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9n-0001Bo-1X for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Ka74XwgKCG4igTMafeTSaaSXQ.OaYcQYg-MdYZaZSZg.adS@flex--wuhaotsh.bounces.google.com>) id 1kxx9j-00019S-Dt for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:40 -0500 Received: from mail-pf1-x449.google.com ([2607:f8b0:4864:20::449]:35498) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Ka74XwgKCG4igTMafeTSaaSXQ.OaYcQYg-MdYZaZSZg.adS@flex--wuhaotsh.bounces.google.com>) id 1kxx9f-0007MU-H7 for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:39 -0500 Received: by mail-pf1-x449.google.com with SMTP id k13so7209831pfc.2 for ; Fri, 08 Jan 2021 11:10:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=hNm0ut2O+1mIOJ9J+86PhKTX0lwSI4vyPoH9VqTzsXI=; b=VfBXqzECNGvBewlj3It9ry2PgO5f0nywYkp74DWkdaQtCaptakXmNFarrXlSu3TaCL J3mCIqNUT4/1sU4Ppm3+kopykDmEtn2UkE6sDLujaDEJCtRI3sr6ouxNvExVHpCpB1EK 3WMNBoLVj2afTYTTjFzAIr/Rj4BTI7Z8KabH5i6syzCiFS50Q1hu4d11RRn898N9bxRJ XFY9I7hCV5AEPax3RC7yH5qW1pG4K81Lfs6DdQl9F4UoVu7ECwkwaXAX3X1OmVh/7ZTF tgQ8BnSByfYHVWTIURpw9LGzteZqul35vxkvdbuEZxOoMRxJNIi7XrkEcwm0wzev04Ur VjRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=hNm0ut2O+1mIOJ9J+86PhKTX0lwSI4vyPoH9VqTzsXI=; b=N/ShHoiPVHskpkJfl/Wo+vMl1xb8kEl4rQes8q5cbJKrHWKon3l2zlTs4NJ7gBODpb GgNzma53YMidrJ78dCiVd5p8SdO+mPxnX+svgJCZV8hgmMAzu5RGmfVyWTyTFgesRF0m nBR80okcdQ0ftUWSoP8AhKeErzAUSVYBkfoi0W9imXBKODxSQVQL9yOhYlKheli5hy5w WEbssTE39gdX81JQiSOIhoFtuydjaYxfFD2nvngg9LSp03PvbgXn90d0ZugBEAcJrJwu 1cx695GcDoKWw0UaalybTd07lWNTmjz8+IOwTquD0PSGLDL1f/5RteX04mJ7Ozb4MfZL laOQ== X-Gm-Message-State: AOAM533+MhVO4ak/GL1ZDPTzo60TE5Sc0i2YAEZG3FVryzxjDvtdwB33 uazhTBnUiUAf8Mk1+zPgZ3AWZN0K824iPg== X-Google-Smtp-Source: ABdhPJy91Atode/M5C4++yLdoH978miwg6ED/2QXrMUSV43RQMLBYskQIFvTtom+zfkwWrIsMZF6Nqt/ZnWxHA== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:90a:a485:: with SMTP id z5mr5279205pjp.160.1610133033191; Fri, 08 Jan 2021 11:10:33 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:45 -0800 In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> Message-Id: <20210108190945.949196-7-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 6/6] hw/*: Use type casting for SysBusDevice in NPCM7XX From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::449; envelope-from=3Ka74XwgKCG4igTMafeTSaaSXQ.OaYcQYg-MdYZaZSZg.adS@flex--wuhaotsh.bounces.google.com; helo=mail-pf1-x449.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:41 -0000 A device shouldn't access its parent object which is QOM internal. Instead it should use type cast for this purporse. This patch fixes this issue for all NPCM7XX Devices. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 2 +- hw/mem/npcm7xx_mc.c | 2 +- hw/misc/npcm7xx_clk.c | 2 +- hw/misc/npcm7xx_gcr.c | 2 +- hw/misc/npcm7xx_rng.c | 2 +- hw/nvram/npcm7xx_otp.c | 2 +- hw/ssi/npcm7xx_fiu.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 306260fa67..3fdd5cab01 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -82,7 +82,7 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, uint32_t hw_straps) { NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); - MachineClass *mc = &nmc->parent; + MachineClass *mc = MACHINE_CLASS(nmc); Object *obj; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c index 0435d06ab4..abc5af5620 100644 --- a/hw/mem/npcm7xx_mc.c +++ b/hw/mem/npcm7xx_mc.c @@ -62,7 +62,7 @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", NPCM7XX_MC_REGS_SIZE); - sysbus_init_mmio(&s->parent, &s->mmio); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); } static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c index 48bc9bdda5..0bcae9ce95 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm7xx_clk.c @@ -913,7 +913,7 @@ static void npcm7xx_clk_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, TYPE_NPCM7XX_CLK, 4 * KiB); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } static int npcm7xx_clk_post_load(void *opaque, int version_id) diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c index 745f690809..eace9e1967 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm7xx_gcr.c @@ -220,7 +220,7 @@ static void npcm7xx_gcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, TYPE_NPCM7XX_GCR, 4 * KiB); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } static const VMStateDescription vmstate_npcm7xx_gcr = { diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c index f650f3401f..b01df7cdb2 100644 --- a/hw/misc/npcm7xx_rng.c +++ b/hw/misc/npcm7xx_rng.c @@ -143,7 +143,7 @@ static void npcm7xx_rng_init(Object *obj) memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs", NPCM7XX_RNG_REGS_SIZE); - sysbus_init_mmio(&s->parent, &s->iomem); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } static const VMStateDescription vmstate_npcm7xx_rng = { diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c index b16ca530ba..c61f2fc1aa 100644 --- a/hw/nvram/npcm7xx_otp.c +++ b/hw/nvram/npcm7xx_otp.c @@ -371,7 +371,7 @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp) { NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev); NPCM7xxOTPState *s = NPCM7XX_OTP(dev); - SysBusDevice *sbd = &s->parent; + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memset(s->array, 0, sizeof(s->array)); diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 5040132b07..4eedb2927e 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -498,7 +498,7 @@ static void npcm7xx_fiu_hold_reset(Object *obj) static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) { NPCM7xxFIUState *s = NPCM7XX_FIU(dev); - SysBusDevice *sbd = &s->parent; + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; if (s->cs_count <= 0) { -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:10:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9v-0001Ev-Rk for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3JK74XwgKCGkdbOHVaZONVVNSL.JVTXLTb-HYTUVUNUb.VYN@flex--wuhaotsh.bounces.google.com>) id 1kxx9n-0001Bw-2N for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:44 -0500 Received: from mail-pf1-x449.google.com ([2607:f8b0:4864:20::449]:53736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3JK74XwgKCGkdbOHVaZONVVNSL.JVTXLTb-HYTUVUNUb.VYN@flex--wuhaotsh.bounces.google.com>) id 1kxx9e-0007LF-CI for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:42 -0500 Received: by mail-pf1-x449.google.com with SMTP id q22so7185133pfj.20 for ; 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Fri, 08 Jan 2021 11:10:28 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:42 -0800 In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> Message-Id: <20210108190945.949196-4-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 3/6] hw/adc: Add an ADC module for NPCM7XX From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::449; envelope-from=3JK74XwgKCGkdbOHVaZONVVNSL.JVTXLTb-HYTUVUNUb.VYN@flex--wuhaotsh.bounces.google.com; helo=mail-pf1-x449.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:44 -0000 The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores it in the ADC_DATA register when enabled. Users can alter input value by using qom-set QMP command. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu --- docs/system/arm/nuvoton.rst | 2 +- hw/adc/meson.build | 1 + hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ hw/adc/trace-events | 5 + hw/arm/npcm7xx.c | 24 ++- include/hw/adc/npcm7xx_adc.h | 69 ++++++ include/hw/arm/npcm7xx.h | 2 + meson.build | 1 + tests/qtest/meson.build | 3 +- tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ 10 files changed, 782 insertions(+), 3 deletions(-) create mode 100644 hw/adc/npcm7xx_adc.c create mode 100644 hw/adc/trace-events create mode 100644 include/hw/adc/npcm7xx_adc.h create mode 100644 tests/qtest/npcm7xx_adc-test.c diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index b00d405d52..35829f8d0b 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -41,6 +41,7 @@ Supported devices * Random Number Generator (RNG) * USB host (USBH) * GPIO controller + * Analog to Digital Converter (ADC) Missing devices --------------- @@ -58,7 +59,6 @@ Missing devices * USB device (USBD) * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) - * Analog to Digital Converter (ADC) * SD/MMC host * PECI interface * Pulse Width Modulation (PWM) diff --git a/hw/adc/meson.build b/hw/adc/meson.build index 0d62ae96ae..6ddee23813 100644 --- a/hw/adc/meson.build +++ b/hw/adc/meson.build @@ -1 +1,2 @@ softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c')) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c new file mode 100644 index 0000000000..870a6d50c2 --- /dev/null +++ b/hw/adc/npcm7xx_adc.c @@ -0,0 +1,301 @@ +/* + * Nuvoton NPCM7xx ADC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/adc/npcm7xx_adc.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "qemu/units.h" +#include "trace.h" + +REG32(NPCM7XX_ADC_CON, 0x0) +REG32(NPCM7XX_ADC_DATA, 0x4) + +/* Register field definitions. */ +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4) +#define NPCM7XX_ADC_CON_INT_EN BIT(21) +#define NPCM7XX_ADC_CON_REFSEL BIT(19) +#define NPCM7XX_ADC_CON_INT BIT(18) +#define NPCM7XX_ADC_CON_EN BIT(17) +#define NPCM7XX_ADC_CON_RST BIT(16) +#define NPCM7XX_ADC_CON_CONV BIT(14) +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) + +#define NPCM7XX_ADC_MAX_RESULT 1023 +#define NPCM7XX_ADC_DEFAULT_IREF 2000000 +#define NPCM7XX_ADC_CONV_CYCLES 20 +#define NPCM7XX_ADC_RESET_CYCLES 10 +#define NPCM7XX_ADC_R0_INPUT 500000 +#define NPCM7XX_ADC_R1_INPUT 1500000 + +static void npcm7xx_adc_reset(NPCM7xxADCState *s) +{ + timer_del(&s->conv_timer); + s->con = 0x000c0001; + s->data = 0x00000000; +} + +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref) +{ + uint32_t result; + + result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref; + if (result > NPCM7XX_ADC_MAX_RESULT) { + result = NPCM7XX_ADC_MAX_RESULT; + } + + return result; +} + +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s) +{ + return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1); +} + +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer, + uint32_t cycles, uint32_t prescaler) +{ + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int64_t ticks = cycles; + int64_t ns; + + ticks *= prescaler; + ns = clock_ticks_to_ns(clk, ticks); + ns += now; + timer_mod(timer, ns); +} + +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s) +{ + uint32_t prescaler = npcm7xx_adc_prescaler(s); + + npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES, + prescaler); +} + +static void npcm7xx_adc_convert_done(void *opaque) +{ + NPCM7xxADCState *s = opaque; + uint32_t input = NPCM7XX_ADC_CON_MUX(s->con); + uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL) + ? s->iref : s->vref; + + if (input >= NPCM7XX_ADC_NUM_INPUTS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n", + __func__, input); + return; + } + s->data = npcm7xx_adc_convert(s->adci[input], ref); + if (s->con & NPCM7XX_ADC_CON_INT_EN) { + s->con |= NPCM7XX_ADC_CON_INT; + qemu_irq_raise(s->irq); + } + s->con &= ~NPCM7XX_ADC_CON_CONV; +} + +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc) +{ + adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT, + adc->iref); + adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT, + adc->iref); +} + +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con) +{ + uint32_t old_con = s->con; + + /* Write ADC_INT to 1 to clear it */ + if (new_con & NPCM7XX_ADC_CON_INT) { + new_con &= ~NPCM7XX_ADC_CON_INT; + qemu_irq_lower(s->irq); + } else if (old_con & NPCM7XX_ADC_CON_INT) { + new_con |= NPCM7XX_ADC_CON_INT; + } + + s->con = new_con; + + if (s->con & NPCM7XX_ADC_CON_RST) { + npcm7xx_adc_reset(s); + return; + } + + if ((s->con & NPCM7XX_ADC_CON_EN)) { + if (s->con & NPCM7XX_ADC_CON_CONV) { + if (!(old_con & NPCM7XX_ADC_CON_CONV)) { + npcm7xx_adc_start_convert(s); + } + } else { + timer_del(&s->conv_timer); + } + } +} + +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t value = 0; + NPCM7xxADCState *s = opaque; + + switch (offset) { + case A_NPCM7XX_ADC_CON: + value = s->con; + break; + + case A_NPCM7XX_ADC_DATA: + value = s->data; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + + trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value); + return value; +} + +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v, + unsigned size) +{ + NPCM7xxADCState *s = opaque; + + trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v); + switch (offset) { + case A_NPCM7XX_ADC_CON: + npcm7xx_adc_write_con(s, v); + break; + + case A_NPCM7XX_ADC_DATA: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", + __func__, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + +} + +static const struct MemoryRegionOps npcm7xx_adc_ops = { + .read = npcm7xx_adc_read, + .write = npcm7xx_adc_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void npcm7xx_adc_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxADCState *s = NPCM7XX_ADC(obj); + + npcm7xx_adc_reset(s); +} + +static void npcm7xx_adc_hold_reset(Object *obj) +{ + NPCM7xxADCState *s = NPCM7XX_ADC(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_adc_init(Object *obj) +{ + NPCM7xxADCState *s = NPCM7XX_ADC(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + int i; + + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL, + npcm7xx_adc_convert_done, s); + memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s, + TYPE_NPCM7XX_ADC, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + + for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { + object_property_add_uint32_ptr(obj, "adci[*]", + &s->adci[i], OBJ_PROP_FLAG_WRITE); + } + object_property_add_uint32_ptr(obj, "vref", + &s->vref, OBJ_PROP_FLAG_WRITE); + npcm7xx_adc_calibrate(s); +} + +static const VMStateDescription vmstate_npcm7xx_adc = { + .name = "npcm7xx-adc", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_TIMER(conv_timer, NPCM7xxADCState), + VMSTATE_UINT32(con, NPCM7xxADCState), + VMSTATE_UINT32(data, NPCM7xxADCState), + VMSTATE_CLOCK(clock, NPCM7xxADCState), + VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS), + VMSTATE_UINT32(vref, NPCM7xxADCState), + VMSTATE_UINT32(iref, NPCM7xxADCState), + VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState, + NPCM7XX_ADC_NUM_CALIB), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm7xx_timer_properties[] = { + DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx ADC Module"; + dc->vmsd = &vmstate_npcm7xx_adc; + rc->phases.enter = npcm7xx_adc_enter_reset; + rc->phases.hold = npcm7xx_adc_hold_reset; + + device_class_set_props(dc, npcm7xx_timer_properties); +} + +static const TypeInfo npcm7xx_adc_info = { + .name = TYPE_NPCM7XX_ADC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxADCState), + .class_init = npcm7xx_adc_class_init, + .instance_init = npcm7xx_adc_init, +}; + +static void npcm7xx_adc_register_types(void) +{ + type_register_static(&npcm7xx_adc_info); +} + +type_init(npcm7xx_adc_register_types); diff --git a/hw/adc/trace-events b/hw/adc/trace-events new file mode 100644 index 0000000000..4c3279ece2 --- /dev/null +++ b/hw/adc/trace-events @@ -0,0 +1,5 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# npcm7xx_adc.c +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index fabfb1697b..b22a8c966d 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -51,6 +51,9 @@ #define NPCM7XX_EHCI_BA (0xf0806000) #define NPCM7XX_OHCI_BA (0xf0807000) +/* ADC Module */ +#define NPCM7XX_ADC_BA (0xf000c000) + /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) #define NPCM7XX_RAM3_SZ (4 * KiB) @@ -61,6 +64,7 @@ #define NPCM7XX_ROM_BA (0xffff0000) #define NPCM7XX_ROM_SZ (64 * KiB) + /* Clock configuration values to be fixed up when bypassing bootloader */ /* Run PLL1 at 1600 MHz */ @@ -73,6 +77,7 @@ * interrupts. */ enum NPCM7xxInterrupt { + NPCM7XX_ADC_IRQ = 0, NPCM7XX_UART0_IRQ = 2, NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, @@ -296,6 +301,14 @@ static void npcm7xx_init_fuses(NPCM7xxState *s) sizeof(value)); } +static void npcm7xx_write_adc_calibration(NPCM7xxState *s) +{ + /* Both ADC and the fuse array must have realized. */ + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); +} + static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) { return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); @@ -322,6 +335,7 @@ static void npcm7xx_init(Object *obj) TYPE_NPCM7XX_FUSE_ARRAY); object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); @@ -414,6 +428,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); + /* ADC Modules. Cannot fail. */ + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "adc-clock")); + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, + npcm7xx_irq(s, NPCM7XX_ADC_IRQ)); + npcm7xx_write_adc_calibration(s); + /* Timer Modules (TIM). Cannot fail. */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { @@ -528,7 +551,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); - create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h new file mode 100644 index 0000000000..7d8442107a --- /dev/null +++ b/include/hw/adc/npcm7xx_adc.h @@ -0,0 +1,69 @@ +/* + * Nuvoton NPCM7xx ADC Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_ADC_H +#define NPCM7XX_ADC_H + +#include "hw/clock.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" + +#define NPCM7XX_ADC_NUM_INPUTS 8 +/** + * This value should not be changed unless write_adc_calibration function in + * hw/arm/npcm7xx.c is also changed. + */ +#define NPCM7XX_ADC_NUM_CALIB 2 + +/** + * struct NPCM7xxADCState - Analog to Digital Converter Module device state. + * @parent: System bus device. + * @iomem: Memory region through which registers are accessed. + * @conv_timer: The timer counts down remaining cycles for the conversion. + * @irq: GIC interrupt line to fire on expiration (if enabled). + * @con: The Control Register. + * @data: The Data Buffer. + * @clock: The ADC Clock. + * @adci: The input voltage in units of uV. 1uv = 1e-6V. + * @vref: The external reference voltage. + * @iref: The internal reference voltage, initialized at launch time. + * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. + */ +typedef struct { + SysBusDevice parent; + + MemoryRegion iomem; + + QEMUTimer conv_timer; + + qemu_irq irq; + uint32_t con; + uint32_t data; + Clock *clock; + + /* Voltages are in unit of uV. 1V = 1000000uV. */ + uint32_t adci[NPCM7XX_ADC_NUM_INPUTS]; + uint32_t vref; + uint32_t iref; + + uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; +} NPCM7xxADCState; + +#define TYPE_NPCM7XX_ADC "npcm7xx-adc" +#define NPCM7XX_ADC(obj) \ + OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) + +#endif /* NPCM7XX_ADC_H */ diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 5469247e38..51e1c7620d 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -17,6 +17,7 @@ #define NPCM7XX_H #include "hw/boards.h" +#include "hw/adc/npcm7xx_adc.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" #include "hw/mem/npcm7xx_mc.h" @@ -76,6 +77,7 @@ typedef struct NPCM7xxState { NPCM7xxGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; + NPCM7xxADCState adc; NPCM7xxOTPState key_storage; NPCM7xxOTPState fuse_array; NPCM7xxMCState mc; diff --git a/meson.build b/meson.build index 563688d682..88966516a5 100644 --- a/meson.build +++ b/meson.build @@ -1687,6 +1687,7 @@ if have_system 'chardev', 'hw/9pfs', 'hw/acpi', + 'hw/adc', 'hw/alpha', 'hw/arm', 'hw/audio', diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6a67c538be..955710d1c5 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -134,7 +134,8 @@ qtests_sparc64 = \ ['prom-env-test', 'boot-serial-test'] qtests_npcm7xx = \ - ['npcm7xx_gpio-test', + ['npcm7xx_adc-test', + 'npcm7xx_gpio-test', 'npcm7xx_rng-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c new file mode 100644 index 0000000000..f029706945 --- /dev/null +++ b/tests/qtest/npcm7xx_adc-test.c @@ -0,0 +1,377 @@ +/* + * QTests for Nuvoton NPCM7xx ADCModules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "libqos/libqtest.h" +#include "qapi/qmp/qdict.h" + +#define REF_HZ (25000000) + +#define CON_OFFSET 0x0 +#define DATA_OFFSET 0x4 + +#define NUM_INPUTS 8 +#define DEFAULT_IREF 2000000 +#define CONV_CYCLES 20 +#define RESET_CYCLES 10 +#define R0_INPUT 500000 +#define R1_INPUT 1500000 +#define MAX_RESULT 1023 + +#define DEFAULT_CLKDIV 5 + +#define FUSE_ARRAY_BA 0xf018a000 +#define FCTL_OFFSET 0x14 +#define FST_OFFSET 0x0 +#define FADDR_OFFSET 0x4 +#define FDATA_OFFSET 0x8 +#define ADC_CALIB_ADDR 24 +#define FUSE_READ 0x2 + +/* Register field definitions. */ +#define CON_MUX(rv) ((rv) << 24) +#define CON_INT_EN BIT(21) +#define CON_REFSEL BIT(19) +#define CON_INT BIT(18) +#define CON_EN BIT(17) +#define CON_RST BIT(16) +#define CON_CONV BIT(14) +#define CON_DIV(rv) extract32(rv, 1, 8) + +#define FST_RDST BIT(1) +#define FDATA_MASK 0xff + +#define MAX_ERROR 10000 +#define MIN_CALIB_INPUT 100000 +#define MAX_CALIB_INPUT 1800000 + +static const uint32_t input_list[] = { + 100000, + 500000, + 1000000, + 1500000, + 1800000, + 2000000, +}; + +static const uint32_t vref_list[] = { + 2000000, + 2200000, + 2500000, +}; + +static const uint32_t iref_list[] = { + 1800000, + 1900000, + 2000000, + 2100000, + 2200000, +}; + +static const uint32_t div_list[] = {0, 1, 3, 7, 15}; + +typedef struct ADC { + int irq; + uint64_t base_addr; +} ADC; + +ADC adc = { + .irq = 0, + .base_addr = 0xf000c000 +}; + +static uint32_t adc_read_con(QTestState *qts, const ADC *adc) +{ + return qtest_readl(qts, adc->base_addr + CON_OFFSET); +} + +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value) +{ + qtest_writel(qts, adc->base_addr + CON_OFFSET, value); +} + +static uint32_t adc_read_data(QTestState *qts, const ADC *adc) +{ + return qtest_readl(qts, adc->base_addr + DATA_OFFSET); +} + +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv) +{ + return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) + / (int32_t)(rv[1] - rv[0]); +} + +static void adc_qom_set(QTestState *qts, const ADC *adc, + const char *name, uint32_t value) +{ + QDict *response; + const char *path = "/machine/soc/adc"; + + g_test_message("Setting properties %s of %s with value %u", + name, path, value); + response = qtest_qmp(qts, "{ 'execute': 'qom-set'," + " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}", + path, name, value); + /* The qom set message returns successfully. */ + g_assert_true(qdict_haskey(response, "return")); +} + +static void adc_write_input(QTestState *qts, const ADC *adc, + uint32_t index, uint32_t value) +{ + char name[100]; + + sprintf(name, "adci[%u]", index); + adc_qom_set(qts, adc, name, value); +} + +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value) +{ + adc_qom_set(qts, adc, "vref", value); +} + +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref) +{ + uint32_t output; + + g_assert_cmpuint(input, <=, ref); + output = (input * (MAX_RESULT + 1)) / ref; + if (output > MAX_RESULT) { + output = MAX_RESULT; + } + + return output; +} + +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc) +{ + uint32_t div = extract32(adc_read_con(qts, adc), 1, 8); + + return 2 * (div + 1); +} + +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, + uint32_t clkdiv) +{ + return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; +} + +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc, + uint32_t clkdiv) +{ + uint32_t prescaler = adc_prescaler(qts, adc); + + /* + * ADC should takes roughly 20 cycles to convert one sample. So we assert it + * should take 10~30 cycles here. + */ + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler, + clkdiv)); + /* ADC is still converting. */ + g_assert_true(adc_read_con(qts, adc) & CON_CONV); + qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv)); + /* ADC has finished conversion. */ + g_assert_false(adc_read_con(qts, adc) & CON_CONV); +} + +/* Check ADC can be reset to default value. */ +static void test_init(gconstpointer adc_p) +{ + const ADC *adc = adc_p; + + QTestState *qts = qtest_init("-machine quanta-gsj"); + adc_write_con(qts, adc, CON_REFSEL | CON_INT); + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL); + qtest_quit(qts); +} + +/* Check ADC can convert from an internal reference. */ +static void test_convert_internal(gconstpointer adc_p) +{ + const ADC *adc = adc_p; + uint32_t index, input, output, expected_output; + QTestState *qts = qtest_init("-machine quanta-gsj"); + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + for (index = 0; index < NUM_INPUTS; ++index) { + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { + input = input_list[i]; + expected_output = adc_calculate_output(input, DEFAULT_IREF); + + adc_write_input(qts, adc, index, input); + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | + CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | + CON_REFSEL | CON_EN); + g_assert_false(qtest_get_irq(qts, adc->irq)); + output = adc_read_data(qts, adc); + g_assert_cmpuint(output, ==, expected_output); + } + } + + qtest_quit(qts); +} + +/* Check ADC can convert from an external reference. */ +static void test_convert_external(gconstpointer adc_p) +{ + const ADC *adc = adc_p; + uint32_t index, input, vref, output, expected_output; + QTestState *qts = qtest_init("-machine quanta-gsj"); + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + + for (index = 0; index < NUM_INPUTS; ++index) { + for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) { + for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) { + input = input_list[i]; + vref = vref_list[j]; + expected_output = adc_calculate_output(input, vref); + + adc_write_input(qts, adc, index, input); + adc_write_vref(qts, adc, vref); + adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN | + CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), ==, + CON_MUX(index) | CON_EN); + g_assert_false(qtest_get_irq(qts, adc->irq)); + output = adc_read_data(qts, adc); + g_assert_cmpuint(output, ==, expected_output); + } + } + } + + qtest_quit(qts); +} + +/* Check ADC interrupt files if and only if CON_INT_EN is set. */ +static void test_interrupt(gconstpointer adc_p) +{ + const ADC *adc = adc_p; + uint32_t index, input, output, expected_output; + QTestState *qts = qtest_init("-machine quanta-gsj"); + + index = 1; + input = input_list[1]; + expected_output = adc_calculate_output(input, DEFAULT_IREF); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + adc_write_input(qts, adc, index, input); + g_assert_false(qtest_get_irq(qts, adc->irq)); + adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT + | CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN + | CON_REFSEL | CON_INT | CON_EN); + g_assert_true(qtest_get_irq(qts, adc->irq)); + output = adc_read_data(qts, adc); + g_assert_cmpuint(output, ==, expected_output); + + qtest_quit(qts); +} + +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */ +static void test_reset(gconstpointer adc_p) +{ + const ADC *adc = adc_p; + QTestState *qts = qtest_init("-machine quanta-gsj"); + + for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) { + uint32_t div = div_list[i]; + + adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div)); + qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES, + adc_prescaler(qts, adc), DEFAULT_CLKDIV)); + g_assert_false(adc_read_con(qts, adc) & CON_EN); + } + qtest_quit(qts); +} + +/* Check ADC Calibration works as desired. */ +static void test_calibrate(gconstpointer adc_p) +{ + int i, j; + const ADC *adc = adc_p; + + for (j = 0; j < ARRAY_SIZE(iref_list); ++j) { + uint32_t iref = iref_list[j]; + uint32_t expected_rv[] = { + adc_calculate_output(R0_INPUT, iref), + adc_calculate_output(R1_INPUT, iref), + }; + char buf[100]; + QTestState *qts; + + sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref); + qts = qtest_init(buf); + + /* Check the converted value is correct using the calibration value. */ + for (i = 0; i < ARRAY_SIZE(input_list); ++i) { + uint32_t input; + uint32_t output; + uint32_t expected_output; + uint32_t calibrated_voltage; + uint32_t index = 0; + + input = input_list[i]; + /* Calibration only works for input range 0.1V ~ 1.8V. */ + if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) { + continue; + } + expected_output = adc_calculate_output(input, iref); + + adc_write_input(qts, adc, index, input); + adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT | + CON_EN | CON_CONV); + adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV); + g_assert_cmphex(adc_read_con(qts, adc), ==, + CON_REFSEL | CON_MUX(index) | CON_EN); + output = adc_read_data(qts, adc); + g_assert_cmpuint(output, ==, expected_output); + + calibrated_voltage = adc_calibrate(output, expected_rv); + g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR); + g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR); + } + + qtest_quit(qts); + } +} + +static void adc_add_test(const char *name, const ADC* wd, + GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name); + qtest_add_data_func(full_name, wd, fn); +} +#define add_test(name, td) adc_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + add_test(init, &adc); + add_test(convert_internal, &adc); + add_test(convert_external, &adc); + add_test(interrupt, &adc); + add_test(reset, &adc); + add_test(calibrate, &adc); + + return g_test_run(); +} -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:10:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxx9w-0001FY-22 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 14:10:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Ja74XwgKCGoecPIWbaPOWWOTM.KWUYMUc-IZUVWVOVc.WZO@flex--wuhaotsh.bounces.google.com>) id 1kxx9m-0001Bk-VE for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:44 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]:54085) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Ja74XwgKCGoecPIWbaPOWWOTM.KWUYMUc-IZUVWVOVc.WZO@flex--wuhaotsh.bounces.google.com>) id 1kxx9e-0007LN-DX for qemu-arm@nongnu.org; Fri, 08 Jan 2021 14:10:42 -0500 Received: by mail-pj1-x1049.google.com with SMTP id q21so7157053pjp.3 for ; Fri, 08 Jan 2021 11:10:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=r+c8gA3nmxYNL7aBu2zdA8HqAK+wSYkjLQrk13sw7cg=; b=gKrLTVpjgNbbiR6i/na8jJLGb4k3XlrqMtU+USgazvWi46azrCyxsMifqwq7i4Jv1Y e3tmpRe99hBbj0bzZ4GI3qOYJS4xfZPmcIVullN+XhazpojIGXVKq1l8tSTSnaSQ9J5e IqimepUirEbWPqV4r8gcy6DVGw74B7ZZXnKlFM1hPSianFbONcSOTodF/PR84YGIP9cH 6ubv1fm1+MCUmidHKEVIemBDpfW+pIzMGbvj9nXlL4Qyo8qC7FxfbjR4BCkKybPDdBpU JvUcnYEhZZUYyzGU4vb7EkSCL/NmubHHqD3/lHNMSvslzab89aVj7yt95ldp3ebbsMRP DAyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=r+c8gA3nmxYNL7aBu2zdA8HqAK+wSYkjLQrk13sw7cg=; b=D8HM//yb6+A9+55CpIuxVmxtxCtYWZRpXqKxAKAsMcblXcCgZnMw1bRQCfLTe09CiL wEiZllID/PCGZiLhCOBXaD8E6oLUroKZ5GRC6m+fHTFH/H6d4bf2IrFBzSAh/7RYiQ6W 1d2HNUyd5f2i/67UO6/NscYyQBLxZBz1+Izg7io96jpjTj8+bbVT6B2wsfYcW6yF2AL9 oitm4sPALq2Iiuit4ETLtE9atgQUgSejMapYTPAHsw0nB6i9B1H8Vok3R53QzKouZQgy YllVTBFGdgq/+f8k6Am2mRLCBTMqa1fALk4TsbuAJJt2VYnbwkZ8A7IKS6nuFmmdOT5U sSGQ== X-Gm-Message-State: AOAM531YE5f1nxEXpewTKyrF1znZZTeGtB6cT4AGrqAaa/e9bv1uZZm/ 0pBijeP8rf/EEO+6AWjN/MPGyHdcl35Sog== X-Google-Smtp-Source: ABdhPJyKzOOrjBP0P4HpWQn5EA0Rd6V1PnVNY1fumrQi7ubMwg4QObCGCU3dh8TOtV4vmUkKnpKcih621PV97A== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:902:7207:b029:da:fd0c:521a with SMTP id ba7-20020a1709027207b02900dafd0c521amr5193681plb.45.1610133029830; Fri, 08 Jan 2021 11:10:29 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:43 -0800 In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> Message-Id: <20210108190945.949196-5-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 4/6] hw/misc: Add a PWM module for NPCM7XX From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3Ja74XwgKCGoecPIWbaPOWWOTM.KWUYMUc-IZUVWVOVc.WZO@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:44 -0000 The PWM module is part of NPCM7XX module. Each NPCM7XX module has two identical PWM modules. Each module contains 4 PWM entries. Each PWM has two outputs: frequency and duty_cycle. Both are computed using inputs from software side. This module does not model detail pulse signals since it is expensive. It also does not model interrupts and watchdogs that are dependant on the detail models. The interfaces for these are left in the module so that anyone in need for these functionalities can implement on their own. The user can read the duty cycle and frequency using qom-get command. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu --- docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 26 +- hw/misc/meson.build | 1 + hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 6 + include/hw/arm/npcm7xx.h | 2 + include/hw/misc/npcm7xx_pwm.h | 105 +++++++ 7 files changed, 689 insertions(+), 3 deletions(-) create mode 100644 hw/misc/npcm7xx_pwm.c create mode 100644 include/hw/misc/npcm7xx_pwm.h diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 35829f8d0b..a1786342e2 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -42,6 +42,7 @@ Supported devices * USB host (USBH) * GPIO controller * Analog to Digital Converter (ADC) + * Pulse Width Modulation (PWM) Missing devices --------------- @@ -61,7 +62,6 @@ Missing devices * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface - * Pulse Width Modulation (PWM) * Tachometer * PCI and PCIe root complex and bridges * VDM and MCTP support diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index b22a8c966d..72040d4079 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -102,6 +102,8 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ NPCM7XX_EHCI_IRQ = 61, NPCM7XX_OHCI_IRQ = 62, + NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ + NPCM7XX_PWM1_IRQ, /* PWM module 1 */ NPCM7XX_GPIO0_IRQ = 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -144,6 +146,12 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = { 0xb8000000, /* CS3 */ }; +/* Register base address for each PWM Module */ +static const hwaddr npcm7xx_pwm_addr[] = { + 0xf0103000, + 0xf0104000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -353,6 +361,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], TYPE_NPCM7XX_FIU); } + + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); + } } static void npcm7xx_realize(DeviceState *dev, Error **errp) @@ -513,6 +525,18 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); + /* PWM Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); + for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); + + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "apb3-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]); + sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects * specified, but this is a programming error. @@ -580,8 +604,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); - create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB); - create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB); create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB); create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB); create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index ce15ffceb9..607cd38a21 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -64,6 +64,7 @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c')) softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm7xx_clk.c', 'npcm7xx_gcr.c', + 'npcm7xx_pwm.c', 'npcm7xx_rng.c', )) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c new file mode 100644 index 0000000000..e99e3cc7ef --- /dev/null +++ b/hw/misc/npcm7xx_pwm.c @@ -0,0 +1,550 @@ +/* + * Nuvoton NPCM7xx PWM Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/misc/npcm7xx_pwm.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "trace.h" + +REG32(NPCM7XX_PWM_PPR, 0x00); +REG32(NPCM7XX_PWM_CSR, 0x04); +REG32(NPCM7XX_PWM_PCR, 0x08); +REG32(NPCM7XX_PWM_CNR0, 0x0c); +REG32(NPCM7XX_PWM_CMR0, 0x10); +REG32(NPCM7XX_PWM_PDR0, 0x14); +REG32(NPCM7XX_PWM_CNR1, 0x18); +REG32(NPCM7XX_PWM_CMR1, 0x1c); +REG32(NPCM7XX_PWM_PDR1, 0x20); +REG32(NPCM7XX_PWM_CNR2, 0x24); +REG32(NPCM7XX_PWM_CMR2, 0x28); +REG32(NPCM7XX_PWM_PDR2, 0x2c); +REG32(NPCM7XX_PWM_CNR3, 0x30); +REG32(NPCM7XX_PWM_CMR3, 0x34); +REG32(NPCM7XX_PWM_PDR3, 0x38); +REG32(NPCM7XX_PWM_PIER, 0x3c); +REG32(NPCM7XX_PWM_PIIR, 0x40); +REG32(NPCM7XX_PWM_PWDR0, 0x44); +REG32(NPCM7XX_PWM_PWDR1, 0x48); +REG32(NPCM7XX_PWM_PWDR2, 0x4c); +REG32(NPCM7XX_PWM_PWDR3, 0x50); + +/* Register field definitions. */ +#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8) +#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3) +#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4) +#define NPCM7XX_CH_EN BIT(0) +#define NPCM7XX_CH_INV BIT(2) +#define NPCM7XX_CH_MOD BIT(3) + +/* Offset of each PWM channel's prescaler in the PPR register. */ +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 }; +/* Offset of each PWM channel's clock selector in the CSR register. */ +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 }; +/* Offset of each PWM channel's control variable in the PCR register. */ +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 }; + +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) +{ + uint32_t ppr; + uint32_t csr; + uint32_t freq; + + if (!p->running) { + return 0; + } + + csr = NPCM7XX_CSR(p->module->csr, p->index); + ppr = NPCM7XX_PPR(p->module->ppr, p->index); + freq = clock_get_hz(p->module->clock); + freq /= ppr + 1; + /* csr can only be 0~4 */ + if (csr > 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid csr value %u\n", + __func__, csr); + csr = 4; + } + /* freq won't be changed if csr == 4. */ + if (csr < 4) { + freq >>= csr + 1; + } + + return freq / (p->cnr + 1); +} + +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) +{ + uint64_t duty; + + if (p->running) { + if (p->cnr == 0) { + duty = 0; + } else if (p->cmr >= p->cnr) { + duty = NPCM7XX_PWM_MAX_DUTY; + } else { + duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); + } + } else { + duty = 0; + } + + if (p->inverted) { + duty = NPCM7XX_PWM_MAX_DUTY - duty; + } + + return duty; +} + +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p) +{ + uint32_t freq = npcm7xx_pwm_calculate_freq(p); + + if (freq != p->freq) { + trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path, + p->index, p->freq, freq); + p->freq = freq; + } +} + +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p) +{ + uint32_t duty = npcm7xx_pwm_calculate_duty(p); + + if (duty != p->duty) { + trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path, + p->index, p->duty, duty); + p->duty = duty; + } +} + +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p) +{ + npcm7xx_pwm_update_freq(p); + npcm7xx_pwm_update_duty(p); +} + +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr) +{ + int i; + uint32_t old_ppr = s->ppr; + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE); + s->ppr = new_ppr; + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) { + npcm7xx_pwm_update_freq(&s->pwm[i]); + } + } +} + +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr) +{ + int i; + uint32_t old_csr = s->csr; + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE); + s->csr = new_csr; + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) { + npcm7xx_pwm_update_freq(&s->pwm[i]); + } + } +} + +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr) +{ + int i; + bool inverted; + uint32_t pcr; + NPCM7xxPWM *p; + + s->pcr = new_pcr; + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE); + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + p = &s->pwm[i]; + pcr = NPCM7XX_CH(new_pcr, i); + inverted = pcr & NPCM7XX_CH_INV; + + /* + * We only run a PWM channel with toggle mode. Single-shot mode does not + * generate frequency and duty-cycle values. + */ + if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) { + if (p->running) { + /* Re-run this PWM channel if inverted changed. */ + if (p->inverted ^ inverted) { + p->inverted = inverted; + npcm7xx_pwm_update_duty(p); + } + } else { + /* Run this PWM channel. */ + p->running = true; + p->inverted = inverted; + npcm7xx_pwm_update_output(p); + } + } else { + /* Clear this PWM channel. */ + p->running = false; + p->inverted = inverted; + npcm7xx_pwm_update_output(p); + } + } + +} + +static hwaddr npcm7xx_cnr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + return 0; + case A_NPCM7XX_PWM_CNR1: + return 1; + case A_NPCM7XX_PWM_CNR2: + return 2; + case A_NPCM7XX_PWM_CNR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_cmr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_CMR0: + return 0; + case A_NPCM7XX_PWM_CMR1: + return 1; + case A_NPCM7XX_PWM_CMR2: + return 2; + case A_NPCM7XX_PWM_CMR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_pdr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_PDR0: + return 0; + case A_NPCM7XX_PWM_PDR1: + return 1; + case A_NPCM7XX_PWM_PDR2: + return 2; + case A_NPCM7XX_PWM_PDR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static hwaddr npcm7xx_pwdr_index(hwaddr offset) +{ + switch (offset) { + case A_NPCM7XX_PWM_PWDR0: + return 0; + case A_NPCM7XX_PWM_PWDR1: + return 1; + case A_NPCM7XX_PWM_PWDR2: + return 2; + case A_NPCM7XX_PWM_PWDR3: + return 3; + default: + g_assert_not_reached(); + } +} + +static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCM7xxPWMState *s = opaque; + uint64_t value = 0; + + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + case A_NPCM7XX_PWM_CNR1: + case A_NPCM7XX_PWM_CNR2: + case A_NPCM7XX_PWM_CNR3: + value = s->pwm[npcm7xx_cnr_index(offset)].cnr; + break; + + case A_NPCM7XX_PWM_CMR0: + case A_NPCM7XX_PWM_CMR1: + case A_NPCM7XX_PWM_CMR2: + case A_NPCM7XX_PWM_CMR3: + value = s->pwm[npcm7xx_cmr_index(offset)].cmr; + break; + + case A_NPCM7XX_PWM_PDR0: + case A_NPCM7XX_PWM_PDR1: + case A_NPCM7XX_PWM_PDR2: + case A_NPCM7XX_PWM_PDR3: + value = s->pwm[npcm7xx_pdr_index(offset)].pdr; + break; + + case A_NPCM7XX_PWM_PWDR0: + case A_NPCM7XX_PWM_PWDR1: + case A_NPCM7XX_PWM_PWDR2: + case A_NPCM7XX_PWM_PWDR3: + value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr; + break; + + case A_NPCM7XX_PWM_PPR: + value = s->ppr; + break; + + case A_NPCM7XX_PWM_CSR: + value = s->csr; + break; + + case A_NPCM7XX_PWM_PCR: + value = s->pcr; + break; + + case A_NPCM7XX_PWM_PIER: + value = s->pier; + break; + + case A_NPCM7XX_PWM_PIIR: + value = s->piir; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } + + trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value); + return value; +} + +static void npcm7xx_pwm_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxPWMState *s = opaque; + NPCM7xxPWM *p; + uint32_t value = v; + + trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value); + switch (offset) { + case A_NPCM7XX_PWM_CNR0: + case A_NPCM7XX_PWM_CNR1: + case A_NPCM7XX_PWM_CNR2: + case A_NPCM7XX_PWM_CNR3: + p = &s->pwm[npcm7xx_cnr_index(offset)]; + p->cnr = value; + npcm7xx_pwm_update_output(p); + break; + + case A_NPCM7XX_PWM_CMR0: + case A_NPCM7XX_PWM_CMR1: + case A_NPCM7XX_PWM_CMR2: + case A_NPCM7XX_PWM_CMR3: + p = &s->pwm[npcm7xx_cmr_index(offset)]; + p->cmr = value; + npcm7xx_pwm_update_output(p); + break; + + case A_NPCM7XX_PWM_PDR0: + case A_NPCM7XX_PWM_PDR1: + case A_NPCM7XX_PWM_PDR2: + case A_NPCM7XX_PWM_PDR3: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PWDR0: + case A_NPCM7XX_PWM_PWDR1: + case A_NPCM7XX_PWM_PWDR2: + case A_NPCM7XX_PWM_PWDR3: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PPR: + npcm7xx_pwm_write_ppr(s, value); + break; + + case A_NPCM7XX_PWM_CSR: + npcm7xx_pwm_write_csr(s, value); + break; + + case A_NPCM7XX_PWM_PCR: + npcm7xx_pwm_write_pcr(s, value); + break; + + case A_NPCM7XX_PWM_PIER: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", + __func__, offset); + break; + + case A_NPCM7XX_PWM_PIIR: + qemu_log_mask(LOG_UNIMP, + "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n", + __func__, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid offset 0x%04" HWADDR_PRIx "\n", + __func__, offset); + break; + } +} + +static const struct MemoryRegionOps npcm7xx_pwm_ops = { + .read = npcm7xx_pwm_read, + .write = npcm7xx_pwm_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); + int i; + + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + NPCM7xxPWM *p = &s->pwm[i]; + + p->cnr = 0x00000000; + p->cmr = 0x00000000; + p->pdr = 0x00000000; + p->pwdr = 0x00000000; + } + + s->ppr = 0x00000000; + s->csr = 0x00000000; + s->pcr = 0x00000000; + s->pier = 0x00000000; + s->piir = 0x00000000; +} + +static void npcm7xx_pwm_hold_reset(Object *obj) +{ + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); + int i; + + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + qemu_irq_lower(s->pwm[i].irq); + } +} + +static void npcm7xx_pwm_init(Object *obj) +{ + NPCM7xxPWMState *s = NPCM7XX_PWM(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + int i; + + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) { + NPCM7xxPWM *p = &s->pwm[i]; + p->module = s; + p->index = i; + sysbus_init_irq(sbd, &p->irq); + } + + memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s, + TYPE_NPCM7XX_PWM, 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL); + + for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) { + object_property_add_uint32_ptr(obj, "freq[*]", + &s->pwm[i].freq, OBJ_PROP_FLAG_READ); + object_property_add_uint32_ptr(obj, "duty[*]", + &s->pwm[i].duty, OBJ_PROP_FLAG_READ); + } +} + +static const VMStateDescription vmstate_npcm7xx_pwm = { + .name = "npcm7xx-pwm", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_BOOL(running, NPCM7xxPWM), + VMSTATE_BOOL(inverted, NPCM7xxPWM), + VMSTATE_UINT8(index, NPCM7xxPWM), + VMSTATE_UINT32(cnr, NPCM7xxPWM), + VMSTATE_UINT32(cmr, NPCM7xxPWM), + VMSTATE_UINT32(pdr, NPCM7xxPWM), + VMSTATE_UINT32(pwdr, NPCM7xxPWM), + VMSTATE_UINT32(freq, NPCM7xxPWM), + VMSTATE_UINT32(duty, NPCM7xxPWM), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_npcm7xx_pwm_module = { + .name = "npcm7xx-pwm-module", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_CLOCK(clock, NPCM7xxPWMState), + VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState, + NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm, + NPCM7xxPWM), + VMSTATE_UINT32(ppr, NPCM7xxPWMState), + VMSTATE_UINT32(csr, NPCM7xxPWMState), + VMSTATE_UINT32(pcr, NPCM7xxPWMState), + VMSTATE_UINT32(pier, NPCM7xxPWMState), + VMSTATE_UINT32(piir, NPCM7xxPWMState), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx PWM Controller"; + dc->vmsd = &vmstate_npcm7xx_pwm_module; + rc->phases.enter = npcm7xx_pwm_enter_reset; + rc->phases.hold = npcm7xx_pwm_hold_reset; +} + +static const TypeInfo npcm7xx_pwm_info = { + .name = TYPE_NPCM7XX_PWM, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxPWMState), + .class_init = npcm7xx_pwm_class_init, + .instance_init = npcm7xx_pwm_init, +}; + +static void npcm7xx_pwm_register_type(void) +{ + type_register_static(&npcm7xx_pwm_info); +} +type_init(npcm7xx_pwm_register_type); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b5118acd3f..d626b9d7a7 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -120,6 +120,12 @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +# npcm7xx_pwm.c +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" + # stm32f4xx_syscfg.c stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 51e1c7620d..f6227aa8aa 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -23,6 +23,7 @@ #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" +#include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" @@ -78,6 +79,7 @@ typedef struct NPCM7xxState { NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; NPCM7xxADCState adc; + NPCM7xxPWMState pwm[2]; NPCM7xxOTPState key_storage; NPCM7xxOTPState fuse_array; NPCM7xxMCState mc; diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h new file mode 100644 index 0000000000..5a689d3f66 --- /dev/null +++ b/include/hw/misc/npcm7xx_pwm.h @@ -0,0 +1,105 @@ +/* + * Nuvoton NPCM7xx PWM Module + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_PWM_H +#define NPCM7XX_PWM_H + +#include "hw/clock.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +/* Each PWM module holds 4 PWM channels. */ +#define NPCM7XX_PWM_PER_MODULE 4 + +/* + * Number of registers in one pwm module. Don't change this without increasing + * the version_id in vmstate. + */ +#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) + +/* + * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty + * value of 100,000 the duty cycle for that PWM is 10%. + */ +#define NPCM7XX_PWM_MAX_DUTY 1000000 + +typedef struct NPCM7xxPWMState NPCM7xxPWMState; + +/** + * struct NPCM7xxPWM - The state of a single PWM channel. + * @module: The PWM module that contains this channel. + * @irq: GIC interrupt line to fire on expiration if enabled. + * @running: Whether this PWM channel is generating output. + * @inverted: Whether this PWM channel is inverted. + * @index: The index of this PWM channel. + * @cnr: The counter register. + * @cmr: The comparator register. + * @pdr: The data register. + * @pwdr: The watchdog register. + * @freq: The frequency of this PWM channel. + * @duty: The duty cycle of this PWM channel. One unit represents + * 1/NPCM7XX_MAX_DUTY cycles. + */ +typedef struct NPCM7xxPWM { + NPCM7xxPWMState *module; + + qemu_irq irq; + + bool running; + bool inverted; + + uint8_t index; + uint32_t cnr; + uint32_t cmr; + uint32_t pdr; + uint32_t pwdr; + + uint32_t freq; + uint32_t duty; +} NPCM7xxPWM; + +/** + * struct NPCM7xxPWMState - Pulse Width Modulation device state. + * @parent: System bus device. + * @iomem: Memory region through which registers are accessed. + * @clock: The PWM clock. + * @pwm: The PWM channels owned by this module. + * @ppr: The prescaler register. + * @csr: The clock selector register. + * @pcr: The control register. + * @pier: The interrupt enable register. + * @piir: The interrupt indication register. + */ +struct NPCM7xxPWMState { + SysBusDevice parent; + + MemoryRegion iomem; + + Clock *clock; + NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; + + uint32_t ppr; + uint32_t csr; + uint32_t pcr; + uint32_t pier; + uint32_t piir; +}; + +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm" +#define NPCM7XX_PWM(obj) \ + OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) + +#endif /* NPCM7XX_PWM_H */ -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:11:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxxAA-0001He-PM for mharc-qemu-arm@gnu.org; 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Fri, 08 Jan 2021 11:10:31 -0800 (PST) Date: Fri, 8 Jan 2021 11:09:44 -0800 In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> Message-Id: <20210108190945.949196-6-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog Subject: [PATCH v5 5/6] hw/misc: Add QTest for NPCM7XX PWM Module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, minyard@acm.org, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, f4bug@amsat.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3J674XwgKCGwgeRKYdcRQYYQVO.MYWaOWe-KbWXYXQXe.YbQ@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.386, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:10:46 -0000 We add a qtest for the PWM in the previous patch. It proves it works as expected. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++ 2 files changed, 491 insertions(+) create mode 100644 tests/qtest/npcm7xx_pwm-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 955710d1c5..0b5467f084 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -136,6 +136,7 @@ qtests_sparc64 = \ qtests_npcm7xx = \ ['npcm7xx_adc-test', 'npcm7xx_gpio-test', + 'npcm7xx_pwm-test', 'npcm7xx_rng-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c new file mode 100644 index 0000000000..33fbdf5f54 --- /dev/null +++ b/tests/qtest/npcm7xx_pwm-test.c @@ -0,0 +1,490 @@ +/* + * QTests for Nuvoton NPCM7xx PWM Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/libqtest.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" + +#define REF_HZ 25000000 + +/* Register field definitions. */ +#define CH_EN BIT(0) +#define CH_INV BIT(2) +#define CH_MOD BIT(3) + +/* Registers shared between all PWMs in a module */ +#define PPR 0x00 +#define CSR 0x04 +#define PCR 0x08 +#define PIER 0x3c +#define PIIR 0x40 + +/* CLK module related */ +#define CLK_BA 0xf0801000 +#define CLKSEL 0x04 +#define CLKDIV1 0x08 +#define CLKDIV2 0x2c +#define PLLCON0 0x0c +#define PLLCON1 0x10 +#define PLL_INDV(rv) extract32((rv), 0, 6) +#define PLL_FBDV(rv) extract32((rv), 16, 12) +#define PLL_OTDV1(rv) extract32((rv), 8, 3) +#define PLL_OTDV2(rv) extract32((rv), 13, 3) +#define APB3CKDIV(rv) extract32((rv), 28, 2) +#define CLK2CKDIV(rv) extract32((rv), 0, 1) +#define CLK4CKDIV(rv) extract32((rv), 26, 2) +#define CPUCKSEL(rv) extract32((rv), 0, 2) + +#define MAX_DUTY 1000000 + +typedef struct PWMModule { + int irq; + uint64_t base_addr; +} PWMModule; + +typedef struct PWM { + uint32_t cnr_offset; + uint32_t cmr_offset; + uint32_t pdr_offset; + uint32_t pwdr_offset; +} PWM; + +typedef struct TestData { + const PWMModule *module; + const PWM *pwm; +} TestData; + +static const PWMModule pwm_module_list[] = { + { + .irq = 93, + .base_addr = 0xf0103000 + }, + { + .irq = 94, + .base_addr = 0xf0104000 + } +}; + +static const PWM pwm_list[] = { + { + .cnr_offset = 0x0c, + .cmr_offset = 0x10, + .pdr_offset = 0x14, + .pwdr_offset = 0x44, + }, + { + .cnr_offset = 0x18, + .cmr_offset = 0x1c, + .pdr_offset = 0x20, + .pwdr_offset = 0x48, + }, + { + .cnr_offset = 0x24, + .cmr_offset = 0x28, + .pdr_offset = 0x2c, + .pwdr_offset = 0x4c, + }, + { + .cnr_offset = 0x30, + .cmr_offset = 0x34, + .pdr_offset = 0x38, + .pwdr_offset = 0x50, + }, +}; + +static const int ppr_base[] = { 0, 0, 8, 8 }; +static const int csr_base[] = { 0, 4, 8, 12 }; +static const int pcr_base[] = { 0, 8, 12, 16 }; + +static const uint32_t ppr_list[] = { + 0, + 1, + 10, + 100, + 255, /* Max possible value. */ +}; + +static const uint32_t csr_list[] = { + 0, + 1, + 2, + 3, + 4, /* Max possible value. */ +}; + +static const uint32_t cnr_list[] = { + 0, + 1, + 50, + 100, + 150, + 200, + 1000, + 10000, + 65535, /* Max possible value. */ +}; + +static const uint32_t cmr_list[] = { + 0, + 1, + 10, + 50, + 100, + 150, + 200, + 1000, + 10000, + 65535, /* Max possible value. */ +}; + +/* Returns the index of the PWM module. */ +static int pwm_module_index(const PWMModule *module) +{ + ptrdiff_t diff = module - pwm_module_list; + + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list)); + + return diff; +} + +/* Returns the index of the PWM entry. */ +static int pwm_index(const PWM *pwm) +{ + ptrdiff_t diff = pwm - pwm_list; + + g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list)); + + return diff; +} + +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name) +{ + QDict *response; + + g_test_message("Getting properties %s from %s", name, path); + response = qtest_qmp(qts, "{ 'execute': 'qom-get'," + " 'arguments': { 'path': %s, 'property': %s}}", + path, name); + /* The qom set message returns successfully. */ + g_assert_true(qdict_haskey(response, "return")); + return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return"))); +} + +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index) +{ + char path[100]; + char name[100]; + + sprintf(path, "/machine/soc/pwm[%d]", module_index); + sprintf(name, "freq[%d]", pwm_index); + + return pwm_qom_get(qts, path, name); +} + +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index) +{ + char path[100]; + char name[100]; + + sprintf(path, "/machine/soc/pwm[%d]", module_index); + sprintf(name, "duty[%d]", pwm_index); + + return pwm_qom_get(qts, path, name); +} + +static uint32_t get_pll(uint32_t con) +{ + return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con) + * PLL_OTDV2(con)); +} + +static uint64_t read_pclk(QTestState *qts) +{ + uint64_t freq = REF_HZ; + uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); + uint32_t pllcon; + uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1); + uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2); + + switch (CPUCKSEL(clksel)) { + case 0: + pllcon = qtest_readl(qts, CLK_BA + PLLCON0); + freq = get_pll(pllcon); + break; + case 1: + pllcon = qtest_readl(qts, CLK_BA + PLLCON1); + freq = get_pll(pllcon); + break; + case 2: + break; + case 3: + break; + default: + g_assert_not_reached(); + } + + freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2)); + + return freq; +} + +static uint32_t pwm_selector(uint32_t csr) +{ + switch (csr) { + case 0: + return 2; + case 1: + return 4; + case 2: + return 8; + case 3: + return 16; + case 4: + return 1; + default: + g_assert_not_reached(); + } +} + +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, + uint32_t cnr) +{ + return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); +} + +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) +{ + uint64_t duty; + + if (cnr == 0) { + /* PWM is stopped. */ + duty = 0; + } else if (cmr >= cnr) { + duty = MAX_DUTY; + } else { + duty = MAX_DUTY * (cmr + 1) / (cnr + 1); + } + + if (inverted) { + duty = MAX_DUTY - duty; + } + + return duty; +} + +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset) +{ + return qtest_readl(qts, td->module->base_addr + offset); +} + +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset, + uint32_t value) +{ + qtest_writel(qts, td->module->base_addr + offset, value); +} + +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8); +} + +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value) +{ + pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3); +} + +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value) +{ + pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td) +{ + return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4); +} + +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value) +{ + pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]); +} + +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td) +{ + return pwm_read(qts, td, td->pwm->cnr_offset); +} + +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value) +{ + pwm_write(qts, td, td->pwm->cnr_offset, value); +} + +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td) +{ + return pwm_read(qts, td, td->pwm->cmr_offset); +} + +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value) +{ + pwm_write(qts, td, td->pwm->cmr_offset, value); +} + +/* Check pwm registers can be reset to default value */ +static void test_init(gconstpointer test_data) +{ + const TestData *td = test_data; + QTestState *qts = qtest_init("-machine quanta-gsj"); + int module = pwm_module_index(td->module); + int pwm = pwm_index(td->pwm); + + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); + + qtest_quit(qts); +} + +/* One-shot mode should not change frequency and duty cycle. */ +static void test_oneshot(gconstpointer test_data) +{ + const TestData *td = test_data; + QTestState *qts = qtest_init("-machine quanta-gsj"); + int module = pwm_module_index(td->module); + int pwm = pwm_index(td->pwm); + uint32_t ppr, csr, pcr; + int i, j; + + pcr = CH_EN; + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { + ppr = ppr_list[i]; + pwm_write_ppr(qts, td, ppr); + + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { + csr = csr_list[j]; + pwm_write_csr(qts, td, csr); + pwm_write_pcr(qts, td, pcr); + + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0); + } + } + + qtest_quit(qts); +} + +/* In toggle mode, the PWM generates correct outputs. */ +static void test_toggle(gconstpointer test_data) +{ + const TestData *td = test_data; + QTestState *qts = qtest_init("-machine quanta-gsj"); + int module = pwm_module_index(td->module); + int pwm = pwm_index(td->pwm); + uint32_t ppr, csr, pcr, cnr, cmr; + int i, j, k, l; + uint64_t expected_freq, expected_duty; + + pcr = CH_EN | CH_MOD; + for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) { + ppr = ppr_list[i]; + pwm_write_ppr(qts, td, ppr); + + for (j = 0; j < ARRAY_SIZE(csr_list); ++j) { + csr = csr_list[j]; + pwm_write_csr(qts, td, csr); + + for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) { + cnr = cnr_list[k]; + pwm_write_cnr(qts, td, cnr); + + for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) { + cmr = cmr_list[l]; + pwm_write_cmr(qts, td, cmr); + expected_freq = pwm_compute_freq(qts, ppr, csr, cnr); + expected_duty = pwm_compute_duty(cnr, cmr, false); + + pwm_write_pcr(qts, td, pcr); + g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr); + g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr); + g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr); + g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), + ==, expected_duty); + if (expected_duty != 0 && expected_duty != 100) { + /* Duty cycle with 0 or 100 doesn't need frequency. */ + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), + ==, expected_freq); + } + + /* Test inverted mode */ + expected_duty = pwm_compute_duty(cnr, cmr, true); + pwm_write_pcr(qts, td, pcr | CH_INV); + g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV); + g_assert_cmpuint(pwm_get_duty(qts, module, pwm), + ==, expected_duty); + if (expected_duty != 0 && expected_duty != 100) { + /* Duty cycle with 0 or 100 doesn't need frequency. */ + g_assert_cmpuint(pwm_get_freq(qts, module, pwm), + ==, expected_freq); + } + + } + } + } + } + + qtest_quit(qts); +} + +static void pwm_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf( + "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module), + pwm_index(td->pwm), name); + qtest_add_data_func(full_name, td, fn); +} +#define add_test(name, td) pwm_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) { + for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) { + TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j]; + + td->module = &pwm_module_list[i]; + td->pwm = &pwm_list[j]; + + add_test(init, td); + add_test(oneshot, td); + add_test(toggle, td); + } + } + + return g_test_run(); +} -- 2.29.2.729.g45daf8777d-goog From MAILER-DAEMON Fri Jan 08 14:52:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxxnq-0002Et-BQ for mharc-qemu-arm@gnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b127sm15338635wmc.45.2021.01.08.11.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 11:51:59 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Guenter Roeck Subject: [PATCH] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns Date: Fri, 8 Jan 2021 19:51:57 +0000 Message-Id: <20210108195157.32067-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 19:52:04 -0000 In commit cd8be50e58f63413c0 we converted the A32 coprocessor insns to decodetree. This accidentally broke XScale/iWMMXt insns, because it moved the handling of "cp insns which are handled by looking up the cp register in the hashtable" from after the call to the legacy disas_xscale_insn() decode to before it, with the result that all XScale/iWMMXt insns now UNDEF. Update valid_cp() so that it knows that on XScale cp 0 and 1 are not standard coprocessor instructions; this will cause the decodetree trans_ functions to ignore them, so that execution will correctly get through to the legacy decode again. Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck Signed-off-by: Peter Maydell --- With this Guenter's test image now successfully boots and shuts down again. --- target/arm/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76a..528b93dffa2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp) * only cp14 and cp15 are valid, and other values aren't considered * to be in the coprocessor-instruction space at all. v8M still * permits coprocessors 0..7. + * For XScale, we must not decode the XScale cp0, cp1 space as + * a standard coprocessor insn, because we want to fall through to + * the legacy disas_xscale_insn() decoder after decodetree is done. */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_V8) && !arm_dc_feature(s, ARM_FEATURE_M)) { return cp >= 14; -- 2.20.1 From MAILER-DAEMON Fri Jan 08 15:09:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kxy4e-0001lr-Hr for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 15:09:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxy4d-0001l2-KT for qemu-arm@nongnu.org; Fri, 08 Jan 2021 15:09:27 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:33546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kxy4b-0002Ol-0W for qemu-arm@nongnu.org; Fri, 08 Jan 2021 15:09:27 -0500 Received: by mail-pg1-x52f.google.com with SMTP id n25so8333598pgb.0 for ; Fri, 08 Jan 2021 12:09:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lB68adO6GrIyK320+aTFNTpiiJBBuCJBQZObKpChUMY=; b=HQekSAIz+3mdrcj378y3SzlysmDaVv4O0JdmdMiFwerukroC0ey4tlcENlhcQaQzEo A5/folDv+Z8kav6FvAXB5dc8vGJZqISV9QO3qAxtRh4+DT8DFDXHyAejzXNewCZCTyA9 gxxOelchZofvUm7Zke+SMJC9FOB3BZscfZK51mY9X75HtVQkghg/lp/JSIRa3JkVhhJI e+MvHXtFxgm1GySJHHq8TsAkU2rWaVoakKLoo/bnian8pqLSiioUslzKPsYALm9lSU7t MdiePuJYKHsbSBeV/CAOd5rHaD96s8b4xDO17q0DZquijKKdh/Ijshqy1aJ5NxJMhJnU VY2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lB68adO6GrIyK320+aTFNTpiiJBBuCJBQZObKpChUMY=; b=ZeS2PAmB7E+gCtou8GPHZWUNk8xmwf9vzJdlPrVDB7tJ3r8fJRH9Ai1Y/pisakqq8l YQaoLwuR9SZJO+7jqqalexnk/yg83adgscsXGoX7iL9Bi/S5D6NC6g5ABperAb7hidOr aCnbaWrnlUhkhHBsqbAX7UKt8sMRaO65AqmO4WIgwrgsJXlULtJB29wvniHj/IcqOxM7 m//PgeOh6K37ZKxc1d7wlvDc6rrbC4nNlU1XAcdcUHC1Jlw+yh3WxnxO+Bd5mAkuli2m ucLLzZuKLXg7OOz7GWLPDBsIFll5eBQSYPQUt9+9RCfs+b91oJt3kGJDftnDKNuiBhKT NaGw== X-Gm-Message-State: AOAM533C7tmS8enOBgrkDBprjPPs3z2jc/so4bi9g2+bP9vLQR5UV4Hw JoR1DsHV4tydIEQQ1PqoYdJyaw== X-Google-Smtp-Source: ABdhPJwzVq5jEosN93vIs/MFprcwAC1yYzhFdJ+LpR0Ionjn4P5T7hk1gzA7uuhV5nbhbftDJr5+aQ== X-Received: by 2002:a63:170f:: with SMTP id x15mr8635801pgl.157.1610136563457; Fri, 08 Jan 2021 12:09:23 -0800 (PST) Received: from [10.25.18.7] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id a131sm10794419pfd.171.2021.01.08.12.09.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jan 2021 12:09:22 -0800 (PST) Subject: Re: [PATCH] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Guenter Roeck References: <20210108195157.32067-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <93a29bfc-bc4c-b46c-3e8c-9be3ef40356a@linaro.org> Date: Fri, 8 Jan 2021 10:09:19 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108195157.32067-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.241, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 20:09:27 -0000 On 1/8/21 9:51 AM, Peter Maydell wrote: > In commit cd8be50e58f63413c0 we converted the A32 coprocessor > insns to decodetree. This accidentally broke XScale/iWMMXt insns, > because it moved the handling of "cp insns which are handled > by looking up the cp register in the hashtable" from after the > call to the legacy disas_xscale_insn() decode to before it, > with the result that all XScale/iWMMXt insns now UNDEF. > > Update valid_cp() so that it knows that on XScale cp 0 and 1 > are not standard coprocessor instructions; this will cause > the decodetree trans_ functions to ignore them, so that > execution will correctly get through to the legacy decode again. > > Cc: qemu-stable@nongnu.org > Reported-by: Guenter Roeck > Signed-off-by: Peter Maydell > --- > With this Guenter's test image now successfully boots > and shuts down again. > --- Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Jan 08 17:33:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0Jm-0001Q1-MV for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 17:33:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ky0Jj-0001Pi-QX for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:33:12 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ky0Jg-0004td-Vt for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:33:11 -0500 Received: by mail-wr1-x436.google.com with SMTP id d13so10338101wrc.13 for ; Fri, 08 Jan 2021 14:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=JV+V99tt4EQveY06Mm4McJZehVQDN620TryUZlVZr5U=; b=ZXkAe5PL5VggHFWOH407981UnXQ/rWErsV9kbX2N6oAwXK7eTTCsnp25uo17z5SNea j+1sIo3SaCMWZjlhqyM/YskpQieW2oTfL0WAS0CPpfDtc+C2B/q0t6sowRuet6YaMp24 XFWY6TmZvD+AUjniaTNh5KyDmGDQTPb49an3BRsME7K7TavXb6YTu5L/LcKNa9EL8cCu 9RKNlPE76N6SCulGWcdaIjfMoX/Rh5g8oQmhOL39m+0oLLQ2+wUBC+ad92U1mBXHBnNC HYVkOn3pnqRasr3JS5bXQu0oMYpLGcfNU2SoNn77W4Mfa4q2D5Lx1SBva01Q4qTK6va9 +yfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=JV+V99tt4EQveY06Mm4McJZehVQDN620TryUZlVZr5U=; b=RqswfE6P1KQ2Y8UuVoYPJmd/F1GnE+Ku6ehfIzvTaskpM4KXonYaCSFRcdlGGEVArx X5JBGGNC47Em2mVhpJVvQ6jJ3rGQH/bdcfoorShP1RYw7kdG5wcwGAnX1XqONrZTTghz aT0reKOJom4i7nXnLuudRs67eLD4vDaZFYcM9+1k8oNbdmLQW2DId6iBquKbOKF/l61T Uix85fqIzEYGt9myiw1WCFjKJYQkju7/S3z5IfBb/ix0GEjNd3rfc8c66EDlXvTAaQDK KAjmaV3jojWxCdIx3igYvnBUxIFuviaaQLgstVk+x81bCFJFym+N95Sxxc2R19dXm2JO j0lA== X-Gm-Message-State: AOAM530NIeJGHdsQp9sdgX0JyUf6ZSbrDSniyd3gtsYapbGnbkLt5PZz VcyUtmIIg1dMQnDrf/izy5X3Mg== X-Google-Smtp-Source: ABdhPJztM2AwqFao3hRN6xK5I88EEJLwP7ACRM+wdZ3IwRSwmVPLuc5oBddOreaQZtM09re12VwuYA== X-Received: by 2002:a5d:6045:: with SMTP id j5mr5361404wrt.223.1610145187532; Fri, 08 Jan 2021 14:33:07 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c81sm13843090wmd.6.2021.01.08.14.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 14:33:06 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E5FC71FF7E; Fri, 8 Jan 2021 22:33:05 +0000 (GMT) References: <20210107170717.2098982-1-keithp@keithp.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Keith Packard Cc: qemu-devel@nongnu.org, Alistair Francis , Bastian Koppelmann , Laurent Vivier , Palmer Dabbelt , Peter Maydell , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Sagar Karandikar Subject: Re: [PATCH 0/9] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Date: Fri, 08 Jan 2021 22:32:57 +0000 In-reply-to: <20210107170717.2098982-1-keithp@keithp.com> Message-ID: <87turrys7y.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:33:12 -0000 Keith Packard writes: > This series adds support for RISC-V Semihosting, version 0.2 as > specified here: > > https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > This specification references the ARM semihosting release 2.0 as > specified here: > > https://static.docs.arm.com/100863/0200/semihosting.pdf > > That specification includes several semihosting calls which were not > previously implemented. This series includes implementations for the > remaining calls so that both RISC-V and ARM versions are now complete. > > Tests for release 2.0 can be found in picolibc on the semihost-2.0-all > branch: > > https://github.com/picolibc/picolibc/tree/semihost-2.0-all > > These tests uncovered a bug in the SYS_HEAPINFO implementation for > ARM, which has been fixed in this series as well. > > The series is structured as follows: > > 1. Move shared semihosting files > 2. Change public common semihosting APIs > 3. Change internal semihosting interfaces > 4. Fix SYS_HEAPINFO crash on ARM > 5-6. Add RISC-V semihosting implementation > 7-9. Add missing semihosting operations from release 2.0 Queued to semihosting/next, thanks. --=20 Alex Benn=C3=A9e From MAILER-DAEMON Fri Jan 08 17:33:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0KI-0001kv-OF for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 17:33:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ky0KE-0001jb-1v for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:33:42 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:39963) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ky0KC-0005GK-2A for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:33:41 -0500 Received: by mail-pj1-x1031.google.com with SMTP id m5so6988031pjv.5 for ; Fri, 08 Jan 2021 14:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=0hER6CK+Qtb8Bjy/Ktns56cKHbxMqNzSvuPBlZa/m2g=; b=lRgKeMoQxf1w+CpNs6J7qf+2YIQsNq0DcBXf6uKWsLR4pVyH+LRIGSVJkFV15LxVHC Ehkm86CHSviIW9AGi4x2lxDFknpLhLqdsCX+PI4LoUQ4v7WKnZDd4JplUhpTPIlNs765 9BktfK0Oyc0wR70brDPFwf+eFeBFbNgdbhN77rcwGdTmH4mCc4bLeqT1yMpm51epJUFx lDIpoUgmbCTL8Nlsmix+e1RpWgq7Gdx0Ch74ajRDAVHH+phJ4kP+5gVmHEOsQTvcSSIm nASKxD/5OSYKu6Q5SB9RZDtthmo6uccx9evyRXDgaIpBdbkxJInH+J9d+V26+a6ess0z Csig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=0hER6CK+Qtb8Bjy/Ktns56cKHbxMqNzSvuPBlZa/m2g=; b=S9U1Th+q9KzQD3LNfda4pBWc+dpK0KGXnHmvFEzJxAwaP2GnOmFoX5TvGx88n7GGf3 cpmC6toc4+XtEfshqRLl692ytS+dftqLxP8pxEcLli4vv1yLQW5zoJUoRvivrk4Hbhr4 EkoTJf+xi1LdACIiv8cHyr/gKRS2Lv6VRd5+0bKBsFZmQwL2DqrKINyBTzmPWFlNFgtt pLSDVj8I7R7Sw3Mqx6Luvfx1tVyw2B8ERbDVtUd4jpQwui3nI6ToRC15lQYXSXeHdYZc lBOKTKIERUj5/nCD1Mr1O39m08IzMAEt7Z3eOa0NTMmg5I9aZYRSgpaAcMi74KbpRFHs 6IUA== X-Gm-Message-State: AOAM532zCrQCgRO2bZ2U3mEz72rB+BtP1DuBqOs/iIrg7dg0OTINoAL9 2eV1i8RQVtwBRkS2t42tQG1QXkpKXqMw+g== X-Google-Smtp-Source: ABdhPJwNxpeTF6Y+Kf/tStmPqm8vDtisGR1wUOXYx+zC8MvWl2tNSUIqQYz9g5fi3+n9/oC1tZ7yzQ== X-Received: by 2002:a17:902:9896:b029:dc:3306:8aa7 with SMTP id s22-20020a1709029896b02900dc33068aa7mr9165927plp.6.1610145218302; Fri, 08 Jan 2021 14:33:38 -0800 (PST) Received: from [10.25.18.7] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id x1sm11171526pgj.37.2021.01.08.14.33.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jan 2021 14:33:37 -0800 (PST) Subject: Re: [PATCH v3 3/6] target/arm: make ARMCPU.ctr 64-bit To: Leif Lindholm , qemu-devel@nongnu.org Cc: Laurent Desnogues , Peter Maydell , qemu-arm@nongnu.org References: <20210108185154.8108-1-leif@nuviainc.com> <20210108185154.8108-4-leif@nuviainc.com> From: Richard Henderson Message-ID: <49ed5e5a-411d-2947-40d7-844554770519@linaro.org> Date: Fri, 8 Jan 2021 12:33:33 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108185154.8108-4-leif@nuviainc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.241, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:33:43 -0000 On 1/8/21 8:51 AM, Leif Lindholm wrote: > When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the > TminLine field in bits [37:32]. > Extend the ctr field to be able to hold this context. > > Signed-off-by: Leif Lindholm > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Fri Jan 08 17:43:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0TR-0005nS-9F for mharc-qemu-arm@gnu.org; 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Fri, 08 Jan 2021 14:43:01 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 63DFA1FF91; Fri, 8 Jan 2021 22:42:57 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 05/20] gdbstub: implement a softmmu based test Date: Fri, 8 Jan 2021 22:42:41 +0000 Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:43:11 -0000 This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to: - add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201218112707.28348-5-alex.bennee@linaro.org> Signed-off-by: Alex Bennée --- tests/guest-debug/run-test.py | 36 +++-- tests/tcg/aarch64/Makefile.softmmu-target | 1 + tests/tcg/aarch64/system/boot.S | 1 + tests/tcg/i386/Makefile.softmmu-target | 1 + tests/tcg/i386/system/boot.S | 2 +- tests/tcg/multiarch/gdbstub/memory.py | 130 ++++++++++++++++++ .../multiarch/system/Makefile.softmmu-target | 19 ++- tests/tcg/x86_64/Makefile.softmmu-target | 1 + tests/tcg/x86_64/system/boot.S | 2 +- 9 files changed, 181 insertions(+), 12 deletions(-) create mode 100644 tests/tcg/multiarch/gdbstub/memory.py diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index 0c4f5c3808..8b91ff95af 100755 --- a/tests/guest-debug/run-test.py +++ b/tests/guest-debug/run-test.py @@ -16,6 +16,7 @@ import subprocess import shutil import shlex import os +from time import sleep from tempfile import TemporaryDirectory def get_args(): @@ -27,10 +28,21 @@ def get_args(): required=True) parser.add_argument("--test", help="GDB test script", required=True) - parser.add_argument("--gdb", help="The gdb binary to use", default=None) + parser.add_argument("--gdb", help="The gdb binary to use", + default=None) + parser.add_argument("--output", help="A file to redirect output to") return parser.parse_args() + +def log(output, msg): + if output: + output.write(msg + "\n") + output.flush() + else: + print(msg) + + if __name__ == '__main__': args = get_args() @@ -42,18 +54,25 @@ if __name__ == '__main__': if not args.gdb: print("We need gdb to run the test") exit(-1) + if args.output: + output = open(args.output, "w") + else: + output = None socket_dir = TemporaryDirectory("qemu-gdbstub") socket_name = os.path.join(socket_dir.name, "gdbstub.socket") # Launch QEMU with binary if "system" in args.qemu: - cmd = "%s %s %s -s -S" % (args.qemu, args.qargs, args.binary) + cmd = "%s %s %s -gdb unix:path=%s,server" % (args.qemu, + args.qargs, + args.binary, + socket_name) else: cmd = "%s %s -g %s %s" % (args.qemu, args.qargs, socket_name, args.binary) - print("QEMU CMD: %s" % (cmd)) + log(output, "QEMU CMD: %s" % (cmd)) inferior = subprocess.Popen(shlex.split(cmd)) # Now launch gdb with our test and collect the result @@ -63,16 +82,15 @@ if __name__ == '__main__': # disable prompts in case of crash gdb_cmd += " -ex 'set confirm off'" # connect to remote - if "system" in args.qemu: - gdb_cmd += " -ex 'target remote localhost:1234'" - else: - gdb_cmd += " -ex 'target remote %s'" % (socket_name) + gdb_cmd += " -ex 'target remote %s'" % (socket_name) # finally the test script itself gdb_cmd += " -x %s" % (args.test) - print("GDB CMD: %s" % (gdb_cmd)) - result = subprocess.call(gdb_cmd, shell=True); + sleep(1) + log(output, "GDB CMD: %s" % (gdb_cmd)) + + result = subprocess.call(gdb_cmd, shell=True, stdout=output) # A negative result is the result of an internal gdb failure like # a crash. We force a return of 0 so we don't fail the test on diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 1057a8ac49..a7286ac295 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -15,6 +15,7 @@ CRT_PATH=$(AARCH64_SYSTEM_SRC) LINK_SCRIPT=$(AARCH64_SYSTEM_SRC)/kernel.ld LDFLAGS=-Wl,-T$(LINK_SCRIPT) TESTS+=$(AARCH64_TESTS) $(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index b14e94f332..e190b1efa6 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -197,6 +197,7 @@ __start: bl main /* pass return value to sys exit */ +_exit: mov x1, x0 ldr x0, =0x20026 /* ADP_Stopped_ApplicationExit */ stp x0, x1, [sp, #-16]! diff --git a/tests/tcg/i386/Makefile.softmmu-target b/tests/tcg/i386/Makefile.softmmu-target index 1c8790eecd..5266f2335a 100644 --- a/tests/tcg/i386/Makefile.softmmu-target +++ b/tests/tcg/i386/Makefile.softmmu-target @@ -19,6 +19,7 @@ CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc TESTS+=$(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) # building head blobs .PRECIOUS: $(CRT_OBJS) diff --git a/tests/tcg/i386/system/boot.S b/tests/tcg/i386/system/boot.S index 90aa174908..794c2cb0ad 100644 --- a/tests/tcg/i386/system/boot.S +++ b/tests/tcg/i386/system/boot.S @@ -76,7 +76,7 @@ _start: */ call main - /* output any non-zero result in eax to isa-debug-exit device */ +_exit: /* output any non-zero result in eax to isa-debug-exit device */ test %al, %al jz 1f out %ax, $0xf4 diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gdbstub/memory.py new file mode 100644 index 0000000000..67864ad902 --- /dev/null +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -0,0 +1,130 @@ +from __future__ import print_function +# +# Test some of the softmmu debug features with the multiarch memory +# test. It is a port of the original vmlinux focused test case but +# using the "memory" test instead. +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb +import sys + +failcount = 0 + + +def report(cond, msg): + "Report success/fail of test" + if cond: + print("PASS: %s" % (msg)) + else: + print("FAIL: %s" % (msg)) + global failcount + failcount += 1 + + +def check_step(): + "Step an instruction, check it moved." + start_pc = gdb.parse_and_eval('$pc') + gdb.execute("si") + end_pc = gdb.parse_and_eval('$pc') + + return not (start_pc == end_pc) + + +# +# Currently it's hard to create a hbreak with the pure python API and +# manually matching PC to symbol address is a bit flaky thanks to +# function prologues. However internally QEMU's gdbstub treats them +# the same as normal breakpoints so it will do for now. +# +def check_break(sym_name): + "Setup breakpoint, continue and check we stopped." + sym, ok = gdb.lookup_symbol(sym_name) + bp = gdb.Breakpoint(sym_name, gdb.BP_BREAKPOINT) + + gdb.execute("c") + + # hopefully we came back + end_pc = gdb.parse_and_eval('$pc') + report(bp.hit_count == 1, + "break @ %s (%s %d hits)" % (end_pc, sym.value(), bp.hit_count)) + + bp.delete() + + +def do_one_watch(sym, wtype, text): + + wp = gdb.Breakpoint(sym, gdb.BP_WATCHPOINT, wtype) + gdb.execute("c") + report_str = "%s for %s" % (text, sym) + + if wp.hit_count > 0: + report(True, report_str) + wp.delete() + else: + report(False, report_str) + + +def check_watches(sym_name): + "Watch a symbol for any access." + + # Should hit for any read + do_one_watch(sym_name, gdb.WP_ACCESS, "awatch") + + # Again should hit for reads + do_one_watch(sym_name, gdb.WP_READ, "rwatch") + + # Finally when it is written + do_one_watch(sym_name, gdb.WP_WRITE, "watch") + + +def run_test(): + "Run through the tests one by one" + + print("Checking we can step the first few instructions") + step_ok = 0 + for i in range(3): + if check_step(): + step_ok += 1 + + report(step_ok == 3, "single step in boot code") + + # If we get here we have missed some of the other breakpoints. + print("Setup catch-all for _exit") + cbp = gdb.Breakpoint("_exit", gdb.BP_BREAKPOINT) + + check_break("main") + check_watches("test_data[128]") + + report(cbp.hit_count == 0, "didn't reach backstop") + +# +# This runs as the script it sourced (via -x, via run-test.py) +# +try: + inferior = gdb.selected_inferior() + arch = inferior.architecture() + print("ATTACHED: %s" % arch.name()) +except (gdb.error, AttributeError): + print("SKIPPING (not connected)", file=sys.stderr) + exit(0) + +if gdb.parse_and_eval('$pc') == 0: + print("SKIP: PC not set") + exit(0) + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + + # Run the actual tests + run_test() +except (gdb.error): + print("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + pass + +# Finally kill the inferior and exit gdb with a count of failures +gdb.execute("kill") +exit(failcount) diff --git a/tests/tcg/multiarch/system/Makefile.softmmu-target b/tests/tcg/multiarch/system/Makefile.softmmu-target index db4bbeda44..4657f6e4cf 100644 --- a/tests/tcg/multiarch/system/Makefile.softmmu-target +++ b/tests/tcg/multiarch/system/Makefile.softmmu-target @@ -7,8 +7,25 @@ # complications of building. # -MULTIARCH_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/multiarch/system +MULTIARCH_SRC=$(SRC_PATH)/tests/tcg/multiarch +MULTIARCH_SYSTEM_SRC=$(MULTIARCH_SRC)/system VPATH+=$(MULTIARCH_SYSTEM_SRC) MULTIARCH_TEST_SRCS=$(wildcard $(MULTIARCH_SYSTEM_SRC)/*.c) MULTIARCH_TESTS = $(patsubst $(MULTIARCH_SYSTEM_SRC)/%.c, %, $(MULTIARCH_TEST_SRCS)) + +ifneq ($(HAVE_GDB_BIN),) +GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py + +run-gdbstub-memory: memory + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(HAVE_GDB_BIN) \ + --qemu $(QEMU) \ + --output $<.gdb.out \ + --qargs \ + "-monitor none -display none -chardev file$(COMMA)path=$<.out$(COMMA)id=output $(QEMU_OPTS)" \ + --bin $< --test $(MULTIARCH_SRC)/gdbstub/memory.py, \ + "softmmu gdbstub support") + +MULTIARCH_RUNS += run-gdbstub-memory +endif diff --git a/tests/tcg/x86_64/Makefile.softmmu-target b/tests/tcg/x86_64/Makefile.softmmu-target index df252e761c..1bd763f2e6 100644 --- a/tests/tcg/x86_64/Makefile.softmmu-target +++ b/tests/tcg/x86_64/Makefile.softmmu-target @@ -19,6 +19,7 @@ CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc TESTS+=$(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) # building head blobs .PRECIOUS: $(CRT_OBJS) diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S index 73b19a2bda..f8a2fcc839 100644 --- a/tests/tcg/x86_64/system/boot.S +++ b/tests/tcg/x86_64/system/boot.S @@ -124,7 +124,7 @@ _start: /* don't worry about stack frame, assume everthing is garbage when we return */ call main - /* output any non-zero result in eax to isa-debug-exit device */ +_exit: /* output any non-zero result in eax to isa-debug-exit device */ test %al, %al jz 1f out %ax, $0xf4 -- 2.20.1 From MAILER-DAEMON Fri Jan 08 17:43:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0TU-0005vL-Qb for mharc-qemu-arm@gnu.org; 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Fri, 08 Jan 2021 14:43:03 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A205C1FF93; Fri, 8 Jan 2021 22:42:57 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Chris Wulff , Marek Vasut , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 07/20] gdbstub: drop CPUEnv from gdb_exit() Date: Fri, 8 Jan 2021 22:42:43 +0000 Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:43:12 -0000 gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201214153012.12723-5-alex.bennee@linaro.org> Message-Id: <20201218112707.28348-7-alex.bennee@linaro.org> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 2 +- bsd-user/syscall.c | 6 +++--- gdbstub.c | 2 +- linux-user/exit.c | 2 +- target/arm/arm-semi.c | 2 +- target/m68k/m68k-semi.c | 2 +- target/nios2/nios2-semi.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 94d8f83e92..492db0f512 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -46,7 +46,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...); void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va); int use_gdb_syscalls(void); void gdb_set_stop_cpu(CPUState *cpu); -void gdb_exit(CPUArchState *, int); +void gdb_exit(int); #ifdef CONFIG_USER_ONLY /** * gdb_handlesig: yield control to gdb diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index d38ec7a162..adc3d21b54 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -333,7 +333,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); @@ -435,7 +435,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); @@ -514,7 +514,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); diff --git a/gdbstub.c b/gdbstub.c index 15d3a8e1f5..afa553e8fc 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -3068,7 +3068,7 @@ static void gdb_read_byte(uint8_t ch) } /* Tell the remote gdb that the process has exited. */ -void gdb_exit(CPUArchState *env, int code) +void gdb_exit(int code) { char buf[4]; diff --git a/linux-user/exit.c b/linux-user/exit.c index 1594015444..70b344048c 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -34,6 +34,6 @@ void preexit_cleanup(CPUArchState *env, int code) #ifdef CONFIG_GCOV __gcov_dump(); #endif - gdb_exit(env, code); + gdb_exit(code); qemu_plugin_atexit_cb(); } diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index f7b7bff522..93360e28c7 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -1101,7 +1101,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) */ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 27600e0cc0..d919245e4f 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -195,7 +195,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) args = env->dregs[1]; switch (nr) { case HOSTED_EXIT: - gdb_exit(env, env->dregs[0]); + gdb_exit(env->dregs[0]); exit(env->dregs[0]); case HOSTED_OPEN: GET_ARG(0); diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index d7a80dd303..e508b2fafc 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -215,7 +215,7 @@ void do_nios2_semihosting(CPUNios2State *env) args = env->regs[R_ARG1]; switch (nr) { case HOSTED_EXIT: - gdb_exit(env, env->regs[R_ARG0]); + gdb_exit(env->regs[R_ARG0]); exit(env->regs[R_ARG0]); case HOSTED_OPEN: GET_ARG(0); -- 2.20.1 From MAILER-DAEMON Fri Jan 08 17:43:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0Tf-00064P-J4 for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 17:43:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ky0Tb-00062h-Pm for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:43:24 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:40133) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ky0TV-0003LD-QW for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:43:19 -0500 Received: by mail-wm1-x329.google.com with SMTP id r4so9657448wmh.5 for ; Fri, 08 Jan 2021 14:43:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 08 Jan 2021 14:43:16 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l7sm13316032wme.4.2021.01.08.14.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 14:43:08 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2BC261FF9B; Fri, 8 Jan 2021 22:42:58 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Keith Packard , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 12/20] semihosting: Move ARM semihosting code to shared directories Date: Fri, 8 Jan 2021 22:42:48 +0000 Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:43:25 -0000 From: Keith Packard This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis Signed-off-by: Alex Bennée Message-Id: <20210107170717.2098982-2-keithp@keithp.com> --- default-configs/devices/arm-softmmu.mak | 1 + default-configs/targets/aarch64-linux-user.mak | 1 + default-configs/targets/aarch64_be-linux-user.mak | 1 + default-configs/targets/arm-linux-user.mak | 1 + default-configs/targets/armeb-linux-user.mak | 1 + target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 linux-user/{arm => }/semihost.c | 0 hw/semihosting/Kconfig | 3 +++ hw/semihosting/meson.build | 3 +++ linux-user/arm/meson.build | 3 --- linux-user/meson.build | 1 + target/arm/meson.build | 2 -- 12 files changed, 12 insertions(+), 5 deletions(-) rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) rename linux-user/{arm => }/semihost.c (100%) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-configs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/aarch64_be-linux-user.mak b/default-configs/targets/aarch64_be-linux-user.mak index 4c953cf8c5..fae831558d 100644 --- a/default-configs/targets/aarch64_be-linux-user.mak +++ b/default-configs/targets/aarch64_be-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/targets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/armeb-linux-user.mak b/default-configs/targets/armeb-linux-user.mak index 79bf10e99b..255e44e8b0 100644 --- a/default-configs/targets/armeb-linux-user.mak +++ b/default-configs/targets/armeb-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/arm-semi.c b/hw/semihosting/common-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/common-semi.c diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..4c30dc6b16 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,6 @@ config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..5b4a170270 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('common-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.20.1 From MAILER-DAEMON Fri Jan 08 17:43:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0Tj-000677-PT for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 17:43:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ky0Td-00063u-OA for qemu-arm@nongnu.org; Fri, 08 Jan 2021 17:43:27 -0500 Received: from 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(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 14:43:08 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E67FE1FF99; Fri, 8 Jan 2021 22:42:57 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Luis Machado , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Date: Fri, 8 Jan 2021 22:42:46 +0000 Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:43:27 -0000 While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée Cc: Luis Machado Message-Id: <20201218112707.28348-10-alex.bennee@linaro.org> Signed-off-by: Alex Bennée --- target/arm/gdbstub.c | 75 ++++++++------------- target/arm/helper.c | 2 +- tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +++ 3 files changed, 41 insertions(+), 47 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 866595b4f1..a8fff2a3d0 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { { "uint128", 128, 'q', 'u' }, { "int128", 128, 'q', 's' }, /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, { "uint64", 64, 'd', 'u' }, { "int64", 64, 'd', 's' }, - { "ieee_double", 64, 'd', 'f' }, /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, { "uint32", 32, 's', 'u' }, { "int32", 32, 's', 's' }, - { "ieee_single", 32, 's', 'f' }, /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, { "uint16", 16, 'h', 'u' }, { "int16", 16, 'h', 's' }, - /* - * TODO: currently there is no reliable way of telling - * if the remote gdb actually understands ieee_half so - * we don't expose it in the target description for now. - * { "ieee_half", 16, 'h', 'f' }, - */ /* bytes */ { "uint8", 8, 'b', 'u' }, { "int8", 8, 'b', 's' }, @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; g_autoptr(GString) ts = g_string_new(""); - int i, bits, reg_width = (cpu->sve_max_vq * 128); + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); info->num = 0; g_string_printf(s, ""); g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + g_string_append_printf(s, ""); /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "vq%d%c%c", count, - vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); g_string_append_printf(s, "", ts->str, vec_lanes[i].gdb_type, count); @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) * signed and potentially float versions of each size from 128 to * 8 bits. */ - for (bits = 128; bits >= 8; bits /= 2) { - int count = reg_width / bits; - g_string_append_printf(s, "", count); - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - if (vec_lanes[i].size == bits) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - count, - vec_lanes[i].sz, vec_lanes[i].suffix); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", suf[i]); + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { + if (vec_lanes[j].size == bits) { + g_string_append_printf(s, "", + vec_lanes[j].suffix, + vec_lanes[j].sz, vec_lanes[j].suffix); } } g_string_append(s, ""); } /* And now the final union of unions */ - g_string_append(s, ""); - for (bits = 128; bits >= 8; bits /= 2) { - int count = reg_width / bits; - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - if (vec_lanes[i].size == bits) { - g_string_append_printf(s, "", - vec_lanes[i].sz, count); - break; - } - } + g_string_append(s, ""); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", + suf[i], suf[i]); } g_string_append(s, ""); + /* Finally the sve prefix type */ + g_string_append_printf(s, + "", + reg_width / 8); + /* Then define each register in parts for each vq */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", + " regnum=\"%d\" type=\"svev\"/>", i, reg_width, base_reg++); info->num++; } @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) " regnum=\"%d\" group=\"float\"" " type=\"int\"/>", base_reg++); info->num += 2; - /* - * Predicate registers aren't so big they are worth splitting up - * but we do need to define a type to hold the array of quad - * references. - */ - g_string_append_printf(s, - "", - cpu->sve_max_vq); + for (i = 0; i < 16; i++) { g_string_append_printf(s, "", + " regnum=\"%d\" type=\"svep\"/>", i, cpu->sve_max_vq * 16, base_reg++); info->num++; } g_string_append_printf(s, "", + " type=\"svep\"/>", cpu->sve_max_vq * 16, base_reg++); g_string_append_printf(s, "", + " regnum=\"%d\" type=\"int\"/>", base_reg++); info->num += 2; g_string_append_printf(s, ""); diff --git a/target/arm/helper.c b/target/arm/helper.c index d077dd9ef5..d434044f07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg32(buf, vq * 2); + return gdb_get_reg64(buf, vq * 2); } default: /* gdbstub asked for something out our range */ diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py index 972cf73c31..b9ef169c1a 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): except gdb.error: report(False, "checking zregs (out of range)") + # Check the aliased V registers are set and GDB has correctly + # created them for us having recognised and handled SVE. + try: + for i in range(0, 16): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) + report(int(val_z) == int(val_v), + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) + except gdb.error: + report(False, "checking vregs (out of range)") + def run_test(): "Run through the tests one by one" -- 2.20.1 From MAILER-DAEMON Fri Jan 08 17:43:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky0Tr-00069P-2p for mharc-qemu-arm@gnu.org; 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Fri, 08 Jan 2021 14:43:11 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4B2511FF9C; Fri, 8 Jan 2021 22:42:58 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Keith Packard , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v1 13/20] semihosting: Change common-semi API to be architecture-independent Date: Fri, 8 Jan 2021 22:42:49 +0000 Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108224256.2321-1-alex.bennee@linaro.org> References: <20210108224256.2321-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:43:31 -0000 From: Keith Packard The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Signed-off-by: Alex Bennée --- hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 8 -------- hw/semihosting/common-semi.c | 16 ++++++++++------ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/helper.c | 5 +++-- target/arm/m_helper.c | 7 ++++++- 7 files changed, 59 insertions(+), 19 deletions(-) create mode 100644 hw/semihosting/common-semi.h diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..49d9a314db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 93360e28c7..2e959aba08 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/helper.c b/target/arm/helper.c index d434044f07..a2ad77eb4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108195157.32067-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=groeck7@gmail.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.241, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jan 2021 22:51:37 -0000 On 1/8/21 11:51 AM, Peter Maydell wrote: > In commit cd8be50e58f63413c0 we converted the A32 coprocessor > insns to decodetree. This accidentally broke XScale/iWMMXt insns, > because it moved the handling of "cp insns which are handled > by looking up the cp register in the hashtable" from after the > call to the legacy disas_xscale_insn() decode to before it, > with the result that all XScale/iWMMXt insns now UNDEF. > > Update valid_cp() so that it knows that on XScale cp 0 and 1 > are not standard coprocessor instructions; this will cause > the decodetree trans_ functions to ignore them, so that > execution will correctly get through to the legacy decode again. > > Cc: qemu-stable@nongnu.org > Reported-by: Guenter Roeck > Signed-off-by: Peter Maydell > --- > With this Guenter's test image now successfully boots > and shuts down again. > --- Thanks a lot for the fix! Tested-by: Guenter Roeck > target/arm/translate.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index f5acd32e76a..528b93dffa2 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp) > * only cp14 and cp15 are valid, and other values aren't considered > * to be in the coprocessor-instruction space at all. v8M still > * permits coprocessors 0..7. > + * For XScale, we must not decode the XScale cp0, cp1 space as > + * a standard coprocessor insn, because we want to fall through to > + * the legacy disas_xscale_insn() decoder after decodetree is done. > */ > + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { > + return false; > + } > + > if (arm_dc_feature(s, ARM_FEATURE_V8) && > !arm_dc_feature(s, ARM_FEATURE_M)) { > return cp >= 14; > From MAILER-DAEMON Fri Jan 08 21:13:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ky3kt-0006l8-0b for mharc-qemu-arm@gnu.org; Fri, 08 Jan 2021 21:13:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ky3kp-0006ku-HA; Fri, 08 Jan 2021 21:13:23 -0500 Received: from mail-yb1-xb36.google.com ([2607:f8b0:4864:20::b36]:40695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ky3km-0004jz-UU; Fri, 08 Jan 2021 21:13:23 -0500 Received: by mail-yb1-xb36.google.com with SMTP id b64so11199776ybg.7; Fri, 08 Jan 2021 18:13:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AmzsnuS1/ptNkKeTubhLjde1fJ6lG71g4whwGDpBGaY=; b=CBmP99owggPuceNfVdRnDsAnlejjE1yh0JxCqwh7HAOTy2PXc9/W630y3zpDbY77nq HdPm9r+ehFP8n4xZuikewgrKWyRSatHg4swDsfy0ovQLwI+aEfsSuP3lpQKLX6hT6N10 3aWgMns8HBle9SYs/cQatzk2mUhs1FoL/N7XrqubnETV/tNuF0DxaXNOJwjwBoUkw0NZ LrwoMWupm9T+HXJb8MiYIHmaPy4MM+q81shuWmVZ6r8fjjM2JNqu/MNNJtXECq8jY4fI 3IPzCj/eZXPHmM8b1mIb8qo5wEgP1joL58dG5edcD555hs4X0bC02kNc30ZcIR5EWEsg al7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AmzsnuS1/ptNkKeTubhLjde1fJ6lG71g4whwGDpBGaY=; b=dCMQhauTIdrw+E7w9ib47vtw41EOmHFShYv7sXNnAM1sDODSRZhu+NjYcRERgbBcmD Y68l62NoObVmF1N4Blu++lFkwGUxXF2i6J9/5LEmKXL6QNlLU52svEeTe1fU+mSn3AWD HWEnYQL4RzJ9BICAyd8+xmyNvfCCsKKdB+D29o+zj9RQjT4jgbQaN1IZEcWe8vMA+Aom O/pEuirIFcwmOoMa+XOkxjxcEsjHeZxMouAITkGsRZh4akqO8Vqfixe0SF1qzWyTyCzW xqLfO0s1yjduXxx+5ocNqX8puh7raXfn/pH/rhi50rBQv3phKlJUgcI9t2/aPjPdelX9 uBbg== X-Gm-Message-State: AOAM5302H7dnjVPAYQtc9qGPuhVki70MT5tdmFYZSwH5JohKBzqEx3sR ZVCN7OzWjyGfWrvP0W30Jok9abCRyoUm3dyHBrA= X-Google-Smtp-Source: ABdhPJxo6TIj5DvFFetxTsPK12HerL0jMOo4BOzcjguyClc/AvzfRKUPTE7zayeMRL/Bo0m4qDwh03TF++QG/4N7PZc= X-Received: by 2002:a25:4744:: with SMTP id u65mr10641312yba.239.1610158399626; Fri, 08 Jan 2021 18:13:19 -0800 (PST) MIME-Version: 1.0 References: <1608182913-54603-1-git-send-email-bmeng.cn@gmail.com> <1608182913-54603-2-git-send-email-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Sat, 9 Jan 2021 10:13:08 +0800 Message-ID: Subject: Re: [PATCH 2/2] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Peter Maydell Cc: Jean-Christophe Dubois , Alistair Francis , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b36; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 02:13:24 -0000 Hi Peter, On Fri, Jan 8, 2021 at 10:49 PM Peter Maydell wrote: > > On Thu, 17 Dec 2020 at 05:28, Bin Meng wrote: > > > > From: Bin Meng > > > > The endianness of data exchange between tx and rx fifo is incorrect. > > Earlier bytes are supposed to show up on MSB and later bytes on LSB, > > ie: in big endian. The manual does not explicitly say this, but the > > U-Boot and Linux driver codes have a swap on the data transferred > > to tx fifo and from rx fifo. > > To check my understanding, if we have a burst length of 16 bits, say, > when we do the fifo32_pop() of a 32 bit word, where in that > word and which way round are the 2 bytes we are going to transfer ? Say the fifo was written with a value of 0x00001234 when the burst length is 16 bits, 0x12 will be transferred first then followed by 0x34. > > > With this change, U-Boot read from / write to SPI flash tests pass. > > > > => sf test 1ff000 1000 > > SPI flash test: > > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > Test passed > > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > > Signed-off-by: Bin Meng > > > > --- > > > > hw/ssi/imx_spi.c | 16 ++++++++++++---- > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index 509fb9f..71f0902 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -156,13 +156,14 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > { > > uint32_t tx; > > uint32_t rx; > > + uint32_t data; > > + uint8_t byte; > > > > DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n", > > fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); > > > > while (!fifo32_is_empty(&s->tx_fifo)) { > > int tx_burst = 0; > > - int index = 0; > > > > if (s->burst_length <= 0) { > > s->burst_length = imx_spi_burst_length(s); > > @@ -183,10 +184,18 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > tx_burst = 32; > > } > > > > + data = 0; > > + for (int i = 0; i < tx_burst / 8; i++) { > > + byte = tx & 0xff; > > + tx = tx >> 8; > > + data = (data << 8) | byte; > > + } > > + tx = data; > > + > > Why carefully reverse the order of bytes in the word and then > take a byte at a time from the bottom of the word in the loop below, > when you could change the loop to take bytes from the top of the word > instead ? Ah, yes, this can be rewritten to simplify a little. > > > rx = 0; > > > > while (tx_burst > 0) { > > - uint8_t byte = tx & 0xff; > > + byte = tx & 0xff; > > > > DPRINTF("writing 0x%02x\n", (uint32_t)byte); > > > > @@ -196,12 +205,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > DPRINTF("0x%02x read\n", (uint32_t)byte); > > > > tx = tx >> 8; > > - rx |= (byte << (index * 8)); > > + rx = (rx << 8) | byte; > > > > /* Remove 8 bits from the actual burst */ > > tx_burst -= 8; > > s->burst_length -= 8; > > - index++; > > } > > > > DPRINTF("data rx:0x%08x\n", rx); > > -- Regards, Bin From MAILER-DAEMON Sat Jan 09 07:36:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTf-0000zO-LX for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTR-0000od-Pn; Sat, 09 Jan 2021 07:36:05 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46409) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTP-0001VM-DI; Sat, 09 Jan 2021 07:36:05 -0500 Received: by mail-pl1-x634.google.com with SMTP id v3so7093989plz.13; Sat, 09 Jan 2021 04:36:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Rw7xFilfQauR99xCZ/G49M0Aibqgn0UsL5cXaRjCAxk=; b=B2IV64Xu2I6y4r2MrkdMNeN98K1kkSWNPa+XhpuO01kYDE9jwTmvHPXgnzxFSpusZT F6SzeNZQ7SLP8emTySCLAZFRMrqPVKTlr/aUgrfh7aPfNZFDY7FHrM/5qZv4B6p4NYNS PduEyQi4qG9GMRGx1I/RmjtE0GkWwqp2d1BAJ1qyGFW+15K1Qt+kOp3qcGl03otkaAKP ljw6RPewMiURm2rFC6Hgk5vWTSQFkofaE1Xjbar0ywGCrbs9T6dnOmmU+vcKUPVwgX81 1mWqo/RTvXy1BkuSkD64qZN0PicrQS5dpHTAdrR2qAjtdQAKafKHSZsqywR/clFecxK3 t40A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Rw7xFilfQauR99xCZ/G49M0Aibqgn0UsL5cXaRjCAxk=; b=MH9H0KOl+I81LhPsjk5kebr3oWkRZR69UKk0vWLHdv5cxQ3+OZSt/1JNwLxFdyfpnV jd+uqs5OxFrjxBgtB9YVi99nOMWzSRNGZDVMN1vwswA0jEO0eMiuaC9rW3BwBnH6Gs/m CewaIP6AFP/12GG6c0w7VVlunGJdM3/IbZIsFOm3ZuzMT+CjjlUH+wmhci70cM1rtIit lrbc6aniPw7yGSYwDQGtuLVme0BSvMhI2bZAK0Jd+RBe6RweJ2vUXSqNKbWP/tcOqfgQ C8XCrCleZcxlq/yH9pH1UcCe28fBJ/2QtBmEn7foPCwFEZz7d50YLvqmLjrZLkfPjhnF q8dg== X-Gm-Message-State: AOAM530z7ZKjTPcVx0sRki7+cevNb/jc2ZzOfOt8jA3UQpSzAnu7qIbf TdZ/sjHPAGaUHTsvMbemxfM= X-Google-Smtp-Source: ABdhPJwViZy1F5D/e4CMHQ7DVKQBbaAgFV7HFkknkJuZ8VpMTJum1OUvs8cTgWGmOKwamEUldZq+rQ== X-Received: by 2002:a17:903:230f:b029:dc:9b7f:bd0e with SMTP id d15-20020a170903230fb02900dc9b7fbd0emr8310938plh.47.1610195761467; Sat, 09 Jan 2021 04:36:01 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:00 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 0/6] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Sat, 9 Jan 2021 20:35:39 +0800 Message-Id: <20210109123545.12001-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:06 -0000 From: Bin Meng This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is disabled - remove imx_spi_update_irq() in imx_spi_reset() - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v3: - Move the chip selects disable out of imx_spi_reset() - new patch: remove imx_spi_update_irq() in imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Log unimplemented burst length hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 42 ++++++++++++++++++++++++++++------------ 2 files changed, 34 insertions(+), 13 deletions(-) -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTg-00010e-DJ for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTZ-0000ue-ID; Sat, 09 Jan 2021 07:36:13 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:38511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTU-0001XJ-0e; Sat, 09 Jan 2021 07:36:13 -0500 Received: by mail-pf1-x434.google.com with SMTP id d2so8018878pfq.5; Sat, 09 Jan 2021 04:36:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=co4+01plcMDklfphwAUe6tgXN/qjYqocNNI7W6fX0o0=; b=SYFIVItpDjUMf9Urp35g6no2zi5PbB2hOcTikRIGkcAoKGd3m5X3wVPzjAuo9FP9wI bZ8cGc1eAe1UIEVp4iLKJDOY1HstFJX+wBFqqglUFd90xHM2Gnh4AxCzBiCoccSHTU5N iZwkOK7fpjAQQ/cTtn/UGJ766utRjT3IC/imxHcydlBCwfukSWm3OmYfgSRl+ydajfjr DXa3fvqMm4SfbRVNb/OXhPUPsTjz0HBGx0QCFCjGr/ugb/Aw2XJveIbKKSB7egDJTUs6 5cY/13oJNSOhsJvGCYlIuZPN3yc+BPNqQqP/FGK22A46AfJdgYiaAHx1WPQIdj7YxBKG njkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=co4+01plcMDklfphwAUe6tgXN/qjYqocNNI7W6fX0o0=; b=JjOqnIVpQlbbKF3vFTHDO0vRd3TszNv55vHOSg9iNlPrGT/cNjZL8Of0hvxQFH8tYX 5mAuXNK5Rf0QT+9pHafZkphBa2Cf/fmn4MVxme2NaNMP1XWSOha/RcJp0jKw1RmEdpFV g72LZlYFkV0sZyxWSh6fC7rTz3NoSqXmiW3Q0Vf7aVj5I9VlwKaWyMt8EHbASgdcQTFD 3B8PfIHo32ng/u9NreksnbOlJJymG9ZEqzvTnkhvkOvi40rtKg24GAy2/a/V+PKEjIkq HXY+vdDcMjf+EA1iukhIsg1xL1oqXJKVBSf93k4J7S3vlujHXxw+373XL+mHV2SNOdFf 7ZjA== X-Gm-Message-State: AOAM53328TaaJWqD8x6ZYleH8lACKQg3YLyMwywRGW493lSv3arehSf8 6FMxtNbPv06bHUpR0Swogyg= X-Google-Smtp-Source: ABdhPJyECys33XlgX+x9BOV27QKrBoIP7h4PA2iUgOaeSwjw2GtcigjY73ceV/XCV1BSJJ/4JOCzOA== X-Received: by 2002:a63:4559:: with SMTP id u25mr11304263pgk.306.1610195766316; Sat, 09 Jan 2021 04:36:06 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:05 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 1/6] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Sat, 9 Jan 2021 20:35:40 +0800 Message-Id: <20210109123545.12001-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:14 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTg-00011S-JO for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTc-0000x4-2u; Sat, 09 Jan 2021 07:36:17 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTa-0001bt-Jr; Sat, 09 Jan 2021 07:36:15 -0500 Received: by mail-pl1-x62d.google.com with SMTP id be12so7117197plb.4; Sat, 09 Jan 2021 04:36:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CWiCj98t+f0mr4YmBNn3+N3Pi7U13845ZRj24tN9IZs=; b=FoO6lgt4wn5W9f09pIYcvEpjmr/xMyXpZ828JJDcVZdhgvxtFaRy4QT+X21Ia17oFi dTc/i/O9L0J+bYbv6Jbn2dq2y4bEWYC1bfdr/3X6kMrk3LPND69jmKq+cz3mwNmHxz7o 69WJOvvy64iZiwOWnxzDfkF+7WPQlt720q4E6NeCwBotn8+VtrIOvtkV9/XLforCTR60 iV8BXkXYW+N6qfPFBj/QIgOC2Sqy7lwR/OQi8ZfaXggB91rmZBJdZk2QQevlJiXuJszc eYCcTHPvJOjkNvCdTxGl5NXKEY2iddlzgQFO92UFpYdjWMMP2l3JgArTWUxGSXyfyD2g TFqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CWiCj98t+f0mr4YmBNn3+N3Pi7U13845ZRj24tN9IZs=; b=obm3q1MifXLL+jRtilWlFrozIljLmNteCSK4rc0XsreOrQmYrdbV5EnQ2V5ExFiEdG DOKiRhuWYYtRkT8FjtY7FnoApWY8f63yfw3C2kGVI6ixHqc3iXVDaJoEPRUAPmniWtwJ tluMrzGv5w6NbId3Soz6BO6CQo0aBxc3AmpofkZSrmt2fXZIEGFJ+SXtYPQYs4MOuzgK kGBkcDQrOhiT1X6ppxkuXX1nXAi44S2Iev7uVYbjmBzQkC25wpO4GqyAtxF9SYzkwBAB 5wqUY3gMVGF3YQnAmk+5ePjQwPQvS5kpAPWHV0C0ATgOaqxyn7QFUuSp9/bqVNza0fAT WyRA== X-Gm-Message-State: AOAM532OXDa22UFUw32wAFhAcwLxBIhwzMbRleYKnbeaFr6a++LLFvmB sLDe2xuIKwWHapgGqI7ZQ7o= X-Google-Smtp-Source: ABdhPJzqTSVUBd0zt7PVoHbv12i3bV/Gk3oALSnWBwNZPUnwniQ1GFpYzssFajo8IyQp9IDOqc3VBw== X-Received: by 2002:a17:902:850c:b029:da:e4a6:3641 with SMTP id bj12-20020a170902850cb02900dae4a63641mr11379088plb.57.1610195772812; Sat, 09 Jan 2021 04:36:12 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:12 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng Subject: [PATCH v3 2/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Sat, 9 Jan 2021 20:35:41 +0800 Message-Id: <20210109123545.12001-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:18 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..8d429e703f 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -353,6 +353,11 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, if (!imx_spi_is_enabled(s)) { /* device is disabled, so this is a reset */ imx_spi_reset(DEVICE(s)); + + for (int i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + return; } -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTj-00019L-PE for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTi-00015X-6J; Sat, 09 Jan 2021 07:36:22 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:36628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTg-0001gV-GG; Sat, 09 Jan 2021 07:36:21 -0500 Received: by mail-pl1-x62d.google.com with SMTP id j1so7122157pld.3; Sat, 09 Jan 2021 04:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XsYyOi2OZpNJC/4Ru50m0sZSQZAyiL3Ec/GdFu9piXs=; b=MEmtSnpE7C/H1ANy6VQ2NYk8qxzplQE+2ouV8oKkLGia0lakMUNuy1aUDkyseCH/q/ Gg37F1EvwNNxnRc6sZ7L30LZFOyfSwjZypgSoEGI/ziN7HgWehz6RRCKA2BcTuegYcJI vPg50M50oIxnXtAr9F7GWLS8X1pRVAb2FMHFa0hCkgO/m539h5XLarf6ro5WDK8fmCv3 9c0Wshe7LymPoDg+9kmP28cyfVesLkzOAYCkSfiIi68xz/+hA9zLJ93sxb5YNjUUXpUw mLJ1C/5MZHS5pJ9um3ZcjHuxEBcxe2L96l4VUruGKpUrkcD2ybtcrxm4QG7Sy9h8oVi6 pzKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XsYyOi2OZpNJC/4Ru50m0sZSQZAyiL3Ec/GdFu9piXs=; b=Lx3AyAbDRDsQJ3PTskUm8oOHMeqtmaiLIfMzWJFrshjQ79b/YPo0Fg+aWWAcIPpGNb eoEqv9FOiZivkr0IlPJoKMigPbKzmmbLsMX4c1cslIGVP4z6nznSoAUfrlUPVjiUv5g6 vlwh7k5AHjNxy7DKhbGB7aytKvL+3nucBFmQGo2vfz6/kW6JkIGrfrLvfxNpx1++Etwy dcTZSIREHWyH6cOWbijt7YIiqHrh6yLu3/zpk1DdJQdV/uyNe6iEuH8RbZnXFmbraWyV cdYAVAI47/g/wCzqwCRkSmR0sVGposObM2PBSX+cfPIjHkgo3Fx3gOXZ5o0wlQXZZN24 0x5Q== X-Gm-Message-State: AOAM532onYI/4s1+TwCZwJMa7kVgGk0lYBmJfblXk3ni4eMd2q1AR3nc Z0Hzoz29WcXt+KWpY/u5zUo= X-Google-Smtp-Source: ABdhPJxgheoTQ4iQqcjKfnfozsUxwV5gPH4yE1oPXoIpGBmImUXOnHZUp5lrDvAs0SPdou/Q3zdA9Q== X-Received: by 2002:a17:90b:3596:: with SMTP id mm22mr8603229pjb.235.1610195778931; Sat, 09 Jan 2021 04:36:18 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:18 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 3/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Sat, 9 Jan 2021 20:35:42 +0800 Message-Id: <20210109123545.12001-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:22 -0000 From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), along with the disabling of chip selects, to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng --- Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8d429e703f..880939f595 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,9 +241,20 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); + s->burst_length = 0; +} + +static void imx_spi_soft_reset(IMXSPIState *s) +{ + int i; + + imx_spi_reset(DEVICE(s)); + imx_spi_update_irq(s); - s->burst_length = 0; + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) @@ -351,12 +362,8 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); - - for (int i = 0; i < ECSPI_NUM_CS; i++) { - qemu_set_irq(s->cs_lines[i], 1); - } + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); return; } -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTp-0001EW-Ca for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTm-00019Q-LW; Sat, 09 Jan 2021 07:36:27 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:34966) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTl-0001ho-4P; Sat, 09 Jan 2021 07:36:26 -0500 Received: by mail-pl1-x62b.google.com with SMTP id g3so7131207plp.2; Sat, 09 Jan 2021 04:36:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yI7TE3+aIpF0BmDNmiLFBF7fafnCCaEi0n+wo9FW9iw=; b=hXJEsaTlnE/ROdYSwRPaU0zmcrW79wC8GC3sb2uRnfqOISzBcqyIBIiGM1ZlAqTjRX ydO2cdSZQAMIWR1uliCHWsaFfHKWPvIVgXzk5zpNsNr+c2hVb/dg54KmcSsWzLEzkRcF WZAbwERsyRlE6vnWE5m3OylISAiGXn+4E+Er194ZdrLTmnC5mFc/L8RdEbSCvhr+vqKp kHrhfLAKR3lTCpJ1+naKg9sHu+WUCaX5Jb8Jzf+0psKuK+Pfwe4VZ++4U39iYzILX+45 +knQPoPqp+HKHS8CWY/4wLHRumXwQfA+NsgDWouhpuJqu+LbR+jnBtCiPGCww0yj1ER0 DEIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yI7TE3+aIpF0BmDNmiLFBF7fafnCCaEi0n+wo9FW9iw=; b=BZyOefW2GTbZlHtd1oqHg9VlIM6mjNC+jJIicYQo9QWKsvjYnKgs9MQ9fDqMV47LZR P6OsEw0nXWUebtZyvx4lovpKaIIu2IVdZre82KwJGPCRwoVaa7SuqJ/++hn6KpZkgSJD 7njdBDUkFG/7EQ+oioTbfgCLi6DqPYO5zmIzoO32M2+LicPj0CiCuZvNJYj+cg2/WcfG 4cUc+bjIsUfBIMxP3Pxph8Yq8VkeznsTXYgRFvLIvS4HeqOqGNDOYT2W0O1dzd0fFE8W w8KgVYjRK51mQ2yuT/VPyCIUtFHaX5CGT0zckHIA0ZH+8Itd53S50jDOZm/Cm89v30M0 01VQ== X-Gm-Message-State: AOAM530RYUM0IZldlzOpDqOR3PevERueDA3OsAIJV+LmWDf+XLxcxVUR d5SiMnubRcsuZiDBSJ5WTkY= X-Google-Smtp-Source: ABdhPJwnnRWB22hY8AneIxrmFpB3Mpe+m9xEZCyye7Wk2h1cKOFMNxf2zxpVC0WNZ8iV2d56X2KamQ== X-Received: by 2002:a17:902:bcc6:b029:db:e257:9050 with SMTP id o6-20020a170902bcc6b02900dbe2579050mr8354128pls.22.1610195783627; Sat, 09 Jan 2021 04:36:23 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:23 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 4/6] hw/ssi: imx_spi: Log unimplemented burst length Date: Sat, 9 Jan 2021 20:35:43 +0800 Message-Id: <20210109123545.12001-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:27 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most normal use case. In case the burst length is not what we expect, log it to give user a chance to notice it. Signed-off-by: Bin Meng --- Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 880939f595..609d4b658e 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,16 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length not multiple of 8!\n", + TYPE_IMX_SPI, __func__); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTt-0001QW-Tc for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTs-0001MM-Cx; Sat, 09 Jan 2021 07:36:32 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:37129) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTq-0001kd-6D; Sat, 09 Jan 2021 07:36:32 -0500 Received: by mail-pg1-x535.google.com with SMTP id z21so9432533pgj.4; Sat, 09 Jan 2021 04:36:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B2jAlpjFw7XPhC0HC48VFfcY7gcoBuUEhgdvZgD7bo0=; b=hP8DW9agdXeqI+RMPb09GuMDQF5cuJlmvKV7kaR7lrAbDASzxGesPsSHaiLDZlkNur KHiqZVSAkD07BZ2VRK5xPHce1Kt1oIJ+8OZeGwc5dYJKhyNPtURIXDg7IZspVV4XZYz3 E/KcUCqT1zb1XKySZ6UlKKWsfSnXyCjdNU9p+m/f+PZi6Yf9hYYvM5oMEpEg6tsrmCrH K6UCpaDz9My+o1QZI9kR6/orf/KxKhn4AoVi/61whBRqjYEqI7/8oNLKAndoeNNA+/AB 7FBKXlBRcUl10f0f9HHZbFWCivPXiVLnXbScLTkxJWiLo/sT0DiKKkkhyhGH2XFnW94c KZIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B2jAlpjFw7XPhC0HC48VFfcY7gcoBuUEhgdvZgD7bo0=; b=DkUPxIp6KYl9oCCOPrsUSbnThdQkf3qEidxBF62A4psPK49nXPXE5OjMjBGsk7CyN/ ioCWDDFXF/RUCPU0OC0Sxn7GfkjgnYZvlT9t4cKIa/tX9idSRhCsSeojVSlkJheZka0L Xu4mhA1/gnvhSixmLKD6aLEijSXZXE5HY1FhwYR5w/JDGW4cbADbgKmXBjar8hJwF1z5 O/i9y6cX9JhlNnyAXpaPP9VcOYI04UucJoipSsDMmClFuO8ytk+VjBbxa15xk8fG/y7A TU88oQOZR65K2qaceFsStzA3U2PJ3EAYqw5ZvM/ZPEjTI8h+n1NyzID8ELyLGfK+uz7d kH1w== X-Gm-Message-State: AOAM533viWHVrDFQ8gs0mxkHvJKx1OL7xgJdX2clOAvvG9M53xvXrON9 22S1H3Ihc0bY8u15ozthIi0= X-Google-Smtp-Source: ABdhPJwFEIst+OPDpKt7TP+mgIB+rDv2luHBXUSCDZyA6QWkdg1vSFxaMVz3ZrtFYESn5J8Q8DgSOQ== X-Received: by 2002:a63:174f:: with SMTP id 15mr11537566pgx.49.1610195788448; Sat, 09 Jan 2021 04:36:28 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:28 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 5/6] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Sat, 9 Jan 2021 20:35:44 +0800 Message-Id: <20210109123545.12001-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:32 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 609d4b658e..68a32b689e 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -187,7 +187,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.25.1 From MAILER-DAEMON Sat Jan 09 07:36:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyDTx-0001Zz-2H for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 07:36:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyDTv-0001W9-LX; Sat, 09 Jan 2021 07:36:35 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:36903) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyDTu-0001mL-03; Sat, 09 Jan 2021 07:36:35 -0500 Received: by mail-pf1-x42a.google.com with SMTP id 11so8018199pfu.4; Sat, 09 Jan 2021 04:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mG1MTXK9dNCfs7Rn1MWcFj8sMscSVuyy26GcmnPOYdM=; b=pcYzFWX0Y0ahryzO4n3aYv78WToGnijRSHa/OoRZPdYNXUL1VhvMQXJvTCphAIo6E4 IqBXKb/89RvHo3zlXgrdbqOkn16bSwX0yopprU/52ph/rnwyAQm/BMY1kYjpvyXpj+8Z qcBxSNUn9460CiE0VEzGgHkDgWjqOGKu/4EUkUB0AWRaLyC9vmnTiWReCWl6SoBb4PB6 JZfNb6mI+DKuRUhUdUTN4meXS0+IJ7xHx8ZYQtMqzGaAqwWAi6fhaT7HDb8Xc0FXKyNh t8fsjJzOqjNVW0w6YmQbw2Wh15xd03yzW7fvmtYP3TJKbJZ8x344hh04yuyQVqU8yp3T k5KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mG1MTXK9dNCfs7Rn1MWcFj8sMscSVuyy26GcmnPOYdM=; b=jsjoHXgSaZEsKRgLGASAMYixeJcISiqthjDUPS9NiMSfWiW/OaKudHrnQHIXvouaCQ axTPRqhy5o5AzDi5Hswgj7EFpE78UaZmNm5vxz+she2CTLpCI8KBMn5S2v+lehkwM14y CjaseVQIg6v/tsYtiZ7Z9ZSzWgIJNc5ySS9fE8wdRemvexgzoJT0Fng7U5XqL3DWKpht BKYbcQLFdr3anmbPysVtRfngYpRwu1JwGvX+275dcQrd5a4V9oF58u235aJ89dVbBTDG cLXpdy9ub+GJhYJfmxn/6EwRrLV3DYMRaTuKXOUn2hMpG7NP2/oq8NGW16eOFMCBctQ0 We+g== X-Gm-Message-State: AOAM531AszTHEmJpyBCA8y/TSrDsc6XpVdJwgf9Cyi4denkOtpn/O/M8 US5UgVZ9aoAVHJ00E5LBxwra5a790Ho= X-Google-Smtp-Source: ABdhPJyttpSoLeyDjOMY0mGkKPkD6qFK0H+opSslOdu+Wuk3ZZaxf4oNcu//OPxxQgkal6Ju2z0ouA== X-Received: by 2002:a63:1d59:: with SMTP id d25mr11322861pgm.259.1610195792482; Sat, 09 Jan 2021 04:36:32 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:31 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v3 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Sat, 9 Jan 2021 20:35:45 +0800 Message-Id: <20210109123545.12001-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 12:36:36 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng --- Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 68a32b689e..a81242e860 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -171,7 +171,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -192,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -201,13 +200,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.25.1 From MAILER-DAEMON Sat Jan 09 18:45:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyNvV-0000B7-6C for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 18:45:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyNvT-00008h-0m; Sat, 09 Jan 2021 18:45:43 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:35017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyNvR-0007iM-I0; Sat, 09 Jan 2021 18:45:42 -0500 Received: by mail-wm1-x332.google.com with SMTP id e25so11579610wme.0; Sat, 09 Jan 2021 15:45:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=I0bhdjWcxmFuZogU0y/NYMm6U6toxyEVThjZP/+f6wE=; b=uyx+XXsgotMrzrXjSvdisVZIimxuj3sy+ZSK+FAlNLYg6KspMmRs3dMnzYjeq5Qu9a d7XPmYBkHuI9eGCbtbOiHb9j27RCMlyeWiQ5J06BdyXzO0m7jJxXIbG10jNU6i91whnf Bwty1hOY19k6hKCgybdX6IHQmRq8Mod8xZNjM4DKMyJnhF7w5wjQ6e7kRXCVrCH2CFO7 TeVhALjikG6ECcmPlqis1ey4+/Tx644i7DWJm586ucQFrOCMtud2BCCTa3eQfGr4jne3 6XhGQSRDYkXrckD7pQBo7o7JDjzkSCFw06wflq1WqpuX1hqTunuidvI+h6C5TcKfKC6d oaKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=I0bhdjWcxmFuZogU0y/NYMm6U6toxyEVThjZP/+f6wE=; b=FFDCOYyX9sxdk5oog4XUtN2Ji4lsgWeN98RWwa5p6yXBBiqtDx1Y3vNajNi2sjNiq4 iCHg++/6+yfERyD35HF11zSOMMsjcnkXZipU0GhCZJ6YXHQyQEh6egyLBPzjGy/GNsBc nP2pgqXx4r5ziJDYYaY6bFf/Zs6jBsFatZQaGGhMEUasK7ibObh3yTt9NyYo0rv+QYNY iwu0HZjhckCYOHiS78gkjwLzHUQF5dQyqrl39JBu6N/g7fIjUnnopn9oP4PMxdlMLkfV 5Syg/pNpGw3bCYRzaIDSv49s/tSFfvTlAkf/R4tfeTlD8iOcKMTuL6aZ3K7uyTEopPDN m2aQ== X-Gm-Message-State: AOAM533Mlaq3TXYaYq33ccGIHHSrV63L0DdBq82dZbQT3N6mJOuxfacx R4S2zxToQCuJqy1kdzflHlE= X-Google-Smtp-Source: ABdhPJyei8xrOUERkuWHAyjS7jvLnvWKdyQGgELW0zR7CiofjmfO+nMbM3Mde4UqK3y9WaH0Ph0QbA== X-Received: by 2002:a1c:f604:: with SMTP id w4mr8917025wmc.39.1610235939994; Sat, 09 Jan 2021 15:45:39 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id z6sm19028484wrw.58.2021.01.09.15.45.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Jan 2021 15:45:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v3 1/6] hw/ssi: imx_spi: Use a macro for number of chip selects supported To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng References: <20210109123545.12001-1-bmeng.cn@gmail.com> <20210109123545.12001-2-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <95e18158-ea7b-8bf2-690b-41f1fb459863@amsat.org> Date: Sun, 10 Jan 2021 00:45:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210109123545.12001-2-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 23:45:43 -0000 On 1/9/21 1:35 PM, Bin Meng wrote: > From: Bin Meng > > Avoid using a magic number (4) everywhere for the number of chip > selects supported. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis > --- > > (no changes since v1) > > include/hw/ssi/imx_spi.h | 5 ++++- > hw/ssi/imx_spi.c | 4 ++-- > 2 files changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Sat Jan 09 18:48:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyNyH-00029A-Hq for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 18:48:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyNyG-00028o-AC; Sat, 09 Jan 2021 18:48:36 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:40142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyNyE-0000Bx-QM; Sat, 09 Jan 2021 18:48:36 -0500 Received: by mail-wr1-x432.google.com with SMTP id 91so12538945wrj.7; Sat, 09 Jan 2021 15:48:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=AahDlJxVPatn9sJ1ZQtpyj7Ll4wMRUx+//C+VUoI0GQ=; b=pKLtd+aMhKGbgAthXHlv0BwAEGzQUy/xbLEgaJrMR2IjstpJOY/KCovQLLh99SwQYe FX0Cc2ogMYQD00GSz9fQ28ZtVlGVCiBWk/Dm3n/ofuC5wsbdIBAt3YUlLbppkUymGBI8 X2sPBuXmLRCCYrcLXeYv48uO0vUW1WcfhYUc9yKcnXk6ejgGaOTAwxvkd1Qa+WJ5V29Z QsiGqIaT+eSKO9lMl13APPUq3iLPB5ouIxTnFAhMFptHYX5vfWZAJCWObNelNLtSnfOz DWc38hhcwNLNSM6ckbgkLWzYddVVOBAwe9izoBH/IdANl3CVNu/z8lMoSYJ9QqadaYA1 mSfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=AahDlJxVPatn9sJ1ZQtpyj7Ll4wMRUx+//C+VUoI0GQ=; b=YreFpp9PCQMmMNDSuatd/zbZHfIMYyyCpuDdeUUaKzR/cM4+c0Rrkk0YnWbJ6dVkiH 2qvWoHGhPtEUVJVvWZUOiuxKoXR80GmVkD6rvXOD56m0FUxcCtm4QHRbcBNaiORBc/bU lxSGhTHuibW0B4xEN2bEsoeHaRktZ8nep5vQeEVI8Sz1qutK4tULUqRTGQvo0dkGZpd0 BQ82S83/cKMLKsk1kayD9dD30RLglKVBTsL/wYEdDSP6j/4K6702RxdZF2xJcDgTDDd6 mlJeZkwik10WbfWvcdZwXhOk8hmzL1ChuAR+TNsAldCE2X3etK5EA/6EfimQw18kSeJM pgHQ== X-Gm-Message-State: AOAM5319BoyShaKjX1IwODDv+JCGeX0ueNZsyeCvTHOyWtNMqzYAhWuT EeP5mNXa+XU/PVvxeM2ofPY= X-Google-Smtp-Source: ABdhPJxnkuhJfAC9nlU6gfnMMGAL2wMUFepRXizOmSIQ05S/5Eeudlypshm5F/TpxPKE9id+dh6IVg== X-Received: by 2002:adf:97d2:: with SMTP id t18mr9879421wrb.228.1610236112644; Sat, 09 Jan 2021 15:48:32 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id w189sm17182044wmg.31.2021.01.09.15.48.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Jan 2021 15:48:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v3 2/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng References: <20210109123545.12001-1-bmeng.cn@gmail.com> <20210109123545.12001-3-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <444f895d-7758-88f6-fd02-118ce67d431e@amsat.org> Date: Sun, 10 Jan 2021 00:48:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210109123545.12001-3-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 23:48:36 -0000 Hi, On 1/9/21 1:35 PM, Bin Meng wrote: > From: Xuzhou Cheng > > When a write to ECSPI_CONREG register to disable the SPI controller, > imx_spi_reset() is called to reset the controller, but chip select > lines should have been disabled, otherwise the state machine of any > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > its last state and responds incorrectly to any follow-up commands. > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng > > --- > > Changes in v3: > - Move the chip selects disable out of imx_spi_reset() > > Changes in v2: > - Fix the "Fixes" tag in the commit message > > hw/ssi/imx_spi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049a21..8d429e703f 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -353,6 +353,11 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > if (!imx_spi_is_enabled(s)) { > /* device is disabled, so this is a reset */ > imx_spi_reset(DEVICE(s)); > + > + for (int i = 0; i < ECSPI_NUM_CS; i++) { > + qemu_set_irq(s->cs_lines[i], 1); > + } Shouldn't this be done in imx_spi_reset()? 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id v20sm19929879wra.19.2021.01.09.15.53.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Jan 2021 15:53:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v3 3/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng References: <20210109123545.12001-1-bmeng.cn@gmail.com> <20210109123545.12001-4-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sun, 10 Jan 2021 00:53:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210109123545.12001-4-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 23:53:24 -0000 On 1/9/21 1:35 PM, Bin Meng wrote: > From: Bin Meng > > Usually the approach is that the device on the other end of the line > is going to reset its state anyway, so there's no need to actively > signal an irq line change during the reset hook. > > Move imx_spi_update_irq() out of imx_spi_reset(), along with the > disabling of chip selects, to a new function imx_spi_soft_reset() > that is called when the controller is disabled. Now I read this patch, forget my comment on previous patch. > > Signed-off-by: Bin Meng > > --- > > Changes in v3: > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > hw/ssi/imx_spi.c | 21 ++++++++++++++------- > 1 file changed, 14 insertions(+), 7 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 8d429e703f..880939f595 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -241,9 +241,20 @@ static void imx_spi_reset(DeviceState *dev) > imx_spi_rxfifo_reset(s); > imx_spi_txfifo_reset(s); > > + s->burst_length = 0; > +} > + > +static void imx_spi_soft_reset(IMXSPIState *s) > +{ > + int i; > + > + imx_spi_reset(DEVICE(s)); Hmm usually hard reset include soft reset. > + > imx_spi_update_irq(s); > > - s->burst_length = 0; > + for (i = 0; i < ECSPI_NUM_CS; i++) { > + qemu_set_irq(s->cs_lines[i], 1); Isn't this part of the hard reset? > + } > } > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > @@ -351,12 +362,8 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > s->regs[ECSPI_CONREG] = value; > > if (!imx_spi_is_enabled(s)) { > - /* device is disabled, so this is a reset */ > - imx_spi_reset(DEVICE(s)); > - > - for (int i = 0; i < ECSPI_NUM_CS; i++) { > - qemu_set_irq(s->cs_lines[i], 1); > - } > + /* device is disabled, so this is a soft reset */ > + imx_spi_soft_reset(s); Maybe you can restructure patches 2/3, first introduce imx_spi_soft_reset() - this patch - then fix ECSPI_CONREG - the previous patch -. > > return; > } > From MAILER-DAEMON Sat Jan 09 18:55:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyO4g-0004rc-BE for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 18:55:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyO4e-0004r7-DB; Sat, 09 Jan 2021 18:55:12 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51479) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyO4c-0002R9-Cw; Sat, 09 Jan 2021 18:55:11 -0500 Received: by mail-wm1-x32c.google.com with SMTP id v14so10684479wml.1; Sat, 09 Jan 2021 15:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=vijG4FFreQy6BJ60KhlPviZ62YJiRPrEV+PjAUukHhY=; b=qWuNT32Phdvc7LAOanhFdba1eloGqKA2ViJP7EQJnhg94OiFjenn00Jwl08RTrQ4/0 mWhAf4ybj0KvU6qAcmr9nqmW0fpoRmQOHxDyMoY77pC6D84RHmCQeGRxLZsdghZCdjNE Jj9aK1lEq6zkoTBuYz5M0a3oaSTchUNPYwhLqlptJgD68W1pkG2hPFsaYIKf5c/O/XEa v6iydhnbWA/9gpj360dSwqPugQYnSg5oPhRUEBttL4CqfX8hsE03oqgj3GTU4NkekTWF FZD3CKeCT70gbfVS2jQ0Z9wneFCUA3UspWBzSLDyFlelGssLPBe0Vu+w5UdoLznmp2Vy Lu0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=vijG4FFreQy6BJ60KhlPviZ62YJiRPrEV+PjAUukHhY=; b=g3eE0vV0h+WoYq1nvGgM7kzpMfhhJkLd+kmbumwO0rbnS5FOjBb2Lr7b5Ar/j93V0L chWwVnQpzsKH6isAdAjscBUio+j+uNHfTdv7ADmMSQXZ28KzfWr5ds/kGiF5E/m58fdD A2oyVqaz6st1BiMFQ5/MKLcfePRp3wC1GF6u7x0kulY4s2ftK3sLS3/7iKA+cktb+JMN swhF6Xz1cZEVHvydxd/C8ggtueOqMZO7zWA//AAepqKgNnAte4BzR9OY9XRsDa7tnvSv Oe1tShmPMij5HTF9afkcWTfw89shTfJz6nWLnfA9St692zWeAbNlaDeVxUp8Zk5/kSJP IJUg== X-Gm-Message-State: AOAM531j4nSx+fFQ9IpB6OyKCD0w+UdEPRSsrFowEpq0t1TwiMMv8kbP CbNkgXLzvTuOiJlOK3Me1d4= X-Google-Smtp-Source: ABdhPJxmHg43O0NlN/rjDbI/dXqs7nTLQW7A21md0OXZH5q4GfWkFH/Od+r38QmKdypq/v4CHGMmTg== X-Received: by 2002:a1c:220a:: with SMTP id i10mr8667970wmi.93.1610236507989; Sat, 09 Jan 2021 15:55:07 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id k1sm18892921wrn.46.2021.01.09.15.55.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Jan 2021 15:55:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v3 4/6] hw/ssi: imx_spi: Log unimplemented burst length To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng References: <20210109123545.12001-1-bmeng.cn@gmail.com> <20210109123545.12001-5-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7c966c4e-eccd-3fe9-7811-b5b2c6c65c69@amsat.org> Date: Sun, 10 Jan 2021 00:55:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210109123545.12001-5-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jan 2021 23:55:12 -0000 On 1/9/21 1:35 PM, Bin Meng wrote: > From: Bin Meng > > Current implementation of the imx spi controller expects the burst > length to be multiple of 8, which is the most normal use case. s/normal/common/? > > In case the burst length is not what we expect, log it to give user > a chance to notice it. > > Signed-off-by: Bin Meng > > --- > > Changes in v3: > - new patch: log unimplemented burst length > > hw/ssi/imx_spi.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 880939f595..609d4b658e 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -128,7 +128,16 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) > > static uint32_t imx_spi_burst_length(IMXSPIState *s) > { > - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; > + uint32_t burst; > + > + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; > + if (burst % 8) { > + qemu_log_mask(LOG_UNIMP, > + "[%s]%s: burst length not multiple of 8!\n", > + TYPE_IMX_SPI, __func__); Please log the burst length value in the log message. With it: Reviewed-by: Philippe Mathieu-Daudé > + } > + > + return burst; > } > > static bool imx_spi_is_enabled(IMXSPIState *s) > From MAILER-DAEMON Sat Jan 09 20:41:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyPjh-0004is-MS for mharc-qemu-arm@gnu.org; Sat, 09 Jan 2021 20:41:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyPjf-0004hB-EK; Sat, 09 Jan 2021 20:41:39 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:43880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyPjd-0004pC-BQ; Sat, 09 Jan 2021 20:41:39 -0500 Received: by mail-yb1-xb30.google.com with SMTP id y128so13351385ybf.10; Sat, 09 Jan 2021 17:41:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=gIjULYWuqJ1F49GLhY2vgT82AIUwduomrfCmJVdsDwk=; b=t2fxiP7XfkaBv7tUSVql5HnMX1NcPEQ+d2JVrp27r7931ruUQPzeP20Bk0VOUDitio ENquTruoG2URu37Yg7hyHCPHR2DwlXAUcLGwyzRWNYS4SqBpm50oBZ8x+iUIY0Zjn6N1 ZddTKM/p8v/xtpEsnsGQ/41Rg69piA1IJty9268M5+S+70FnrWKNlDXWHR0g3jJ3lAgO w8qTaUILXXga+6BMSqdO/dO60+2AzZsybc0iTrodRm/13TrHPJ4ECcpqkx8JZF9Sd556 ljlkgBNue5EZf9CWsnyhetvKC1OMQxLdWueCUN3+gh+pRGW7TA+0X9QjKQPo3+PzrB58 yc7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=gIjULYWuqJ1F49GLhY2vgT82AIUwduomrfCmJVdsDwk=; b=QqoXjxg/ylFX/ZTCpXPD3YNBKIAsUpvfc+xeZAzu920UM8AfsmmJ3/Cgxo48EgE1Zy l+mq/B47JSAxdulAnXv4iE+MSoQFL8i58GsNNoXJ7/xZs7qq5s+3WIVoIsHZC7eu6O0a nhO2lUIMHXTg9IYh+fpWEtDDY1F8umQMkk1Ww9xYN8tPX2EbYMECYaHrtf4fauRXrAHZ 65CSIubc8qsbgzAQoFAjbubrqYmCBn44QY8sjk0+Ho+Qln+nv8MyFwNnXVegRPNnyUk0 PVCYipop5j3UpKoA/wjH9NtTxKWqPJSd7cEXab8dXrJzt0ga5g7WtCnjduYlk0jMQMRS I8JQ== X-Gm-Message-State: AOAM533a2ywe3+mzecNXhDgjYopAmPM0wXOZM9ybAl/fKL6in1b27AXv 8jZcPwVCSKpsfzgUHAgnngB+AB+bWdTASdyCkHI= X-Google-Smtp-Source: ABdhPJx6J4hTMdhlbv2voj8NXY0L6f+kbkIb9oFjHH9ULsXRYpbH1PKy1T0RB6jhY/tFLG9+7l3A7B1aVwYrBnzH8Ko= X-Received: by 2002:a25:aaee:: with SMTP id t101mr14666001ybi.517.1610242895594; Sat, 09 Jan 2021 17:41:35 -0800 (PST) MIME-Version: 1.0 References: <20210109123545.12001-1-bmeng.cn@gmail.com> <20210109123545.12001-4-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Sun, 10 Jan 2021 09:41:24 +0800 Message-ID: Subject: Re: [PATCH v3 3/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 01:41:39 -0000 Hi Philippe, On Sun, Jan 10, 2021 at 7:53 AM Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/9/21 1:35 PM, Bin Meng wrote: > > From: Bin Meng > > > > Usually the approach is that the device on the other end of the line > > is going to reset its state anyway, so there's no need to actively > > signal an irq line change during the reset hook. > > > > Move imx_spi_update_irq() out of imx_spi_reset(), along with the > > disabling of chip selects, to a new function imx_spi_soft_reset() > > that is called when the controller is disabled. > > Now I read this patch, forget my comment on previous patch. > > > > > Signed-off-by: Bin Meng > > > > --- > > > > Changes in v3: > > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > > > hw/ssi/imx_spi.c | 21 ++++++++++++++------- > > 1 file changed, 14 insertions(+), 7 deletions(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index 8d429e703f..880939f595 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -241,9 +241,20 @@ static void imx_spi_reset(DeviceState *dev) > > imx_spi_rxfifo_reset(s); > > imx_spi_txfifo_reset(s); > > > > + s->burst_length =3D 0; > > +} > > + > > +static void imx_spi_soft_reset(IMXSPIState *s) > > +{ > > + int i; > > + > > + imx_spi_reset(DEVICE(s)); > > Hmm usually hard reset include soft reset. That's my understanding as well. > > > + > > imx_spi_update_irq(s); > > > > - s->burst_length =3D 0; > > + for (i =3D 0; i < ECSPI_NUM_CS; i++) { > > + qemu_set_irq(s->cs_lines[i], 1); > > Isn't this part of the hard reset? > I think we can rename the name to imx_spi_hard_reset() to avoid such confus= ion. > > + } > > } > > > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned siz= e) > > @@ -351,12 +362,8 @@ static void imx_spi_write(void *opaque, hwaddr off= set, uint64_t value, > > s->regs[ECSPI_CONREG] =3D value; > > > > if (!imx_spi_is_enabled(s)) { > > - /* device is disabled, so this is a reset */ > > - imx_spi_reset(DEVICE(s)); > > - > > - for (int i =3D 0; i < ECSPI_NUM_CS; i++) { > > - qemu_set_irq(s->cs_lines[i], 1); > > - } > > + /* device is disabled, so this is a soft reset */ > > + imx_spi_soft_reset(s); > > Maybe you can restructure patches 2/3, first introduce > imx_spi_soft_reset() - this patch - then fix ECSPI_CONREG > - the previous patch -. Sure. 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:13 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 0/6] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Sun, 10 Jan 2021 16:14:23 +0800 Message-Id: <20210110081429.10126-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:18 -0000 From: Bin Meng This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is disabled - remove imx_spi_update_irq() in imx_spi_reset() - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Log unimplemented burst length hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 42 ++++++++++++++++++++++++++++------------ 2 files changed, 34 insertions(+), 13 deletions(-) -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVsf-0002rH-1s for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVsd-0002pq-Tj; Sun, 10 Jan 2021 03:15:19 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:38486) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsc-0005zy-Dg; Sun, 10 Jan 2021 03:15:19 -0500 Received: by mail-pg1-x532.google.com with SMTP id q7so8656029pgm.5; Sun, 10 Jan 2021 00:15:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yiZYra9gqHUl+N2i47qt4AFi/fzPb5dHXFPbEQlB07k=; b=FX2A05NGeP+4h8z00v1eu/L+MQtV3kotxT7akCuflOLL8F+yI/cFwHmV96pt404Z/s syeYnPBO//xRaakbgeP80JIfgXPBqWJWtI4T/hRyZLoSDR1SlxzduEbczsAuFnO4tMd6 /c715WQ08aWocvRL/NRyculieNESKluipnjOYeqhh29HNrAkK+ZwWbC/lPCo0VghKwHA nSbkHQvMZzpPt6SMvCqzVNhHkmXi99KJ8Htk7TFfAJpY4c9sc15NUV5UK7eKOCATsI6n CAR3+BbkTg2qvqPRGWHwRa53n2+rU8Geg8kY37dzspm6YO5V5/FMKhTWifDLX3s4AXGp swLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yiZYra9gqHUl+N2i47qt4AFi/fzPb5dHXFPbEQlB07k=; b=mb+iZEbdRg4407GtXe/VkagtMnX+k7bDkqh4d12zdBLGUv6emyliBdCi+6A7XwtWFJ 8p6UXkrF1bzckMvPoyYr1B9jpQZHweXbQLfqjBEMP/QvWWfqE9OdITmRPQHuJnhiyIdR qO9w4qi4Urio0I8xvivzQfQp4jwUiUqHW4Q2XNkB/0zzjMp5jCkLLUjFPR4ZxibhrmxI o4sAx+Ydk8Zg1rn8cWcTgcGX5fedPxenG/Eq1oCZlpEkUfIrmagTC+ywVFKv35S18mmf r0IoeJp9jA9IWeYXPqnAFJ+st2r9cLq/JQBSaHBmFj7Qw/VSqtDr4L8IXGCW6da+6lfp tsgg== X-Gm-Message-State: AOAM5305URRwdE0DECmJ7pQNDC+XhdDU8i1PS8JYQOkSzVGPNeEOHHdh 5PTsrf19xvbojAY4XLoTc8g= X-Google-Smtp-Source: ABdhPJxcPPskbBNqVtnT+0U4EAvzBNE8Kdji5ECt+C0psZz3Tq/DJzf/+2n4YMo/Lf1XsoYPnLpjbQ== X-Received: by 2002:aa7:9846:0:b029:1ae:7f23:c5 with SMTP id n6-20020aa798460000b02901ae7f2300c5mr3819063pfq.44.1610266516969; Sun, 10 Jan 2021 00:15:16 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:16 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 1/6] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Sun, 10 Jan 2021 16:14:24 +0800 Message-Id: <20210110081429.10126-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:20 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVsi-0002wF-9V for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVsg-0002u4-Mi; Sun, 10 Jan 2021 03:15:22 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:34522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsf-00061p-3W; Sun, 10 Jan 2021 03:15:22 -0500 Received: by mail-pl1-x62f.google.com with SMTP id t6so7910753plq.1; Sun, 10 Jan 2021 00:15:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kp/asB4SUZhcGXZTIA1Vo7cfXDfSmw5jhTVajVVX1DA=; b=jvmYw0REdF/GMDleM2qGccaFP/ZnBm298S7sgpWreYpYFzhs/yDOakjPbNkB7jh08Y xr+cYcdPAOO4DX8LMw4HhsxiM1j8kWUwb7W39rofOYr4hDNYw2yxM9fs3IFpw675Hkye f3HXpEugxF/1xGR7PHYY7zkGQzIuIGlp4SK04U8VY3/ZAaxMjmfG0kabqkpD2ztcXOuz 0BZ9OAyyLtrL63icGtFknQ5QYLZPp119gB8IdqhskZMN5IZKYQ0dqjvbhjYNnUkE7PJ5 0hQ+TIK1KDEHasImC4ebVFXPLzlNhAY5sYSvMPABTfdwPBN49/VWYzmmrbptIInt9DsH ExvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kp/asB4SUZhcGXZTIA1Vo7cfXDfSmw5jhTVajVVX1DA=; b=iQaruKslhVfD2Nx/u/5VPUctfGsd63+okFUKZqdob1EEJL1wM9BOWPdNGebbKKErze 75STUN+rkWsTKmWzvDG34yAgaAJAhTK0dsLtLBJDLIA6QTCepRCNFANaJMrFZ/Or/n9n m+UwonxywOEXJIHIp69N5Ub2FiJFrFKmm/ipMymnzQpb2Rx+3DnQShhpzBdnHhAKTGT6 AGCsD3n/8KEd35PyEZlKX1pnv26UyFgp8aGQfQ+Woy3GG4g3jawM/ggprEzT2AWjDi34 HQnH3IeHawPPA40Whg3EIETG7c5i25iL9afnpRaGcncatTz8jtlI4kTxtpg9WQFc0rMZ s9rA== X-Gm-Message-State: AOAM533LTVGlyIBBG6lCrl6h2MXwlkKrAutOAq1E3R+LTBMdIQNZp9jE Oav4lc/MI9ZIohrHYH7XNQs= X-Google-Smtp-Source: ABdhPJwASmVqybp0TqDarfsUG6i0pv4VnlY5SDobkMx2VWrTsxBhb+YyTEOBE3556+tMOBqoZa+nzw== X-Received: by 2002:a17:90a:fa0c:: with SMTP id cm12mr12144373pjb.87.1610266519516; Sun, 10 Jan 2021 00:15:19 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:19 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Sun, 10 Jan 2021 16:14:25 +0800 Message-Id: <20210110081429.10126-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:23 -0000 From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_hard_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng --- Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..2c4c5ec1b8 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); - imx_spi_update_irq(s); - s->burst_length = 0; } +static void imx_spi_hard_reset(IMXSPIState *s) +{ + imx_spi_reset(DEVICE(s)); + + imx_spi_update_irq(s); +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); + /* device is disabled, so this is a hard reset */ + imx_spi_hard_reset(s); + return; } -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVsk-000330-NZ for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVsj-0002zm-Hg; Sun, 10 Jan 2021 03:15:25 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:51944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsh-000662-W1; Sun, 10 Jan 2021 03:15:25 -0500 Received: by mail-pj1-x102c.google.com with SMTP id y12so1715223pji.1; Sun, 10 Jan 2021 00:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=raxUFNmH8R2fISFPC7w8bqWEMorGOUJfhPU9VBrmArU=; b=SPz/O9MQTzZR4oyly2n7hULf+XN52ErN7r1Jwh/49PixjST/66u9OPC/LUpNOEIQns WukwvNWO6hywMfQKFJMlFIHAmDXyvh0XaCvtg+oT4VlUDAHv1dc7Hjz5WkEaOhX105w4 Cp49R8tecY/m/BfwBEVLXGcTShvnsRK9GfMSmBibj9lbXnJwDWypI8cntGjX2F5VmlWH SaPOQyKrt/sqt95pRGsW6fxnzMktcoghfQPqAZN1A4K2+2Ra4nSmTNi3Lt64In9vITwG i8+eUQl1XIXp6lO3gHF+gXmge/4Dcfbk2WzZ0Uqq7tabwcguRNoiaLWbqX16LEDmhR2t aCcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=raxUFNmH8R2fISFPC7w8bqWEMorGOUJfhPU9VBrmArU=; b=RLvoDqP3oje6zzn1HU33e9g01o4CkYP/HYX2R18i7X3pyIAFs3izce3/l3IXV7huCJ TxC/ki8CCAFJ/I1xceP5X5Nr1+aErIDBdPpVU8q5AvvXCAk29ijBmIbz5bcpOtqUXEPk Gldbbo1iDjEaRWHnzFYCSHvZruD7RyX3In38so/c7CG3p8VZk5cfvqSJcfrgHoxn/rki P2lLrr0r8bMdITyI/Nt04qWHu3xymkjIYe0FnDGzzGXQrAWq+mgysdg4m6tzZv92pLva +eoR/UnDlqKLTYoDifSe7RuyOo1Lnu7+ldqZi8J+r17VOJyHM5ibeYVyEVcovtTcn8JP taYg== X-Gm-Message-State: AOAM5326Y4bsdbUPDGOtxcm0ryeLW9ipG+lV4PetsnmxdDblOEA/CAgn yosGQrGW7Gn2khZr1N63Znk= X-Google-Smtp-Source: ABdhPJwDmcTxIQZbqnwQMCPpPlqAiB+iWQZ1TN7ENPWN2Q7WQv5QgdBKW6ndJp7woU3utNKl1ShuxA== X-Received: by 2002:a17:902:bb95:b029:dc:e7b:fd6e with SMTP id m21-20020a170902bb95b02900dc0e7bfd6emr14576164pls.12.1610266522279; Sun, 10 Jan 2021 00:15:22 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:21 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng Subject: [PATCH v4 3/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Sun, 10 Jan 2021 16:14:26 +0800 Message-Id: <20210110081429.10126-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:25 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2c4c5ec1b8..168ea95440 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -246,9 +246,15 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_hard_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVsn-00038W-0Y for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVsl-00035M-Tk; Sun, 10 Jan 2021 03:15:27 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:38847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsk-00067Q-Ac; Sun, 10 Jan 2021 03:15:27 -0500 Received: by mail-pl1-x629.google.com with SMTP id 4so7894566plk.5; Sun, 10 Jan 2021 00:15:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iq04GWIRz/WrU8q6UvIbx7bFtBJren64Lt595RXDSaQ=; b=KzFnZI/v16JvTQygJMGC3WtYBrCfx3May+8cxFp+qU8MuCo/8BNkfHB65r4iJv3o6a AY0lKPn+6tKQFOOl6lNQNwreFTLMAS+H7raiIMd3TrJcfz9vvUkIfLrdgUfCkwfVfQbU 2PPTChGFhSweTcdESA1Lh69o8jvnkOLSaSVgfAlCrdkSIg4gJWwqKC/X3WXACd12DGLl YNlbgK94JjtQxQ5MdKJ5ezuMYtTcd2MMfGm0mWvRe/1mAzHtL3ki35KpY+LBoqJ4vapZ Xe0Gik8mOgqr1afTOhomb/1g6daQslSI2pKHRyMG6oKlLC7ZADRElmBKJlfRjx7heQhD h8LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iq04GWIRz/WrU8q6UvIbx7bFtBJren64Lt595RXDSaQ=; b=FJBn0W6EWUsh/HpNkDSK9PkJ7m8AJiAkBtWkOzq6Kw1MmnrZcVZpKsdG6cT9CayZl2 yuhX3MeGgmkwXH0QUb436nQSIADapDihEJ2EXH+srMfBNS0lLzPxt8W9FK6JHpvNdt/X bf1TAj1ZpXsoKnj2Rp9hhtXSWNN12oeaiPSRZDFGDUpV8gkIDT3G92mXhU8kyMyYilR5 /xMQQ/l5AOE7VoQN1ahzcAhUjasXiE3fqu4Xo17ezJvqaEOUC3/jWZfZP+ugNoIOLK9g nPeDoxBvhbT1FTMjR2+qioPnCfH9ISl+tC02fBxJfxTMkhXk9TVLXygQSckY5tSdTsNC cDmg== X-Gm-Message-State: AOAM532BB5Gg1Y248AtLM3exjUsUpc1p/HBVqJGen5PoYYU0xrmivng3 Fl4+RGYAfYKwzaeaCNP0Jtk= X-Google-Smtp-Source: ABdhPJzp9Isxq9RLvhIx1eOKg8oUzcVCzJnijz2HNp9fpV/7W5vU2kgb+eQjjBi8b6oLezkup+78Kg== X-Received: by 2002:a17:902:b693:b029:da:e92c:fc23 with SMTP id c19-20020a170902b693b02900dae92cfc23mr11504616pls.55.1610266524801; Sun, 10 Jan 2021 00:15:24 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:24 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 4/6] hw/ssi: imx_spi: Log unimplemented burst length Date: Sun, 10 Jan 2021 16:14:27 +0800 Message-Id: <20210110081429.10126-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:28 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- Changes in v4: - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 168ea95440..7f81b329a4 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,16 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVsq-0003Gc-Cv for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVso-0003CC-Fk; Sun, 10 Jan 2021 03:15:30 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:46017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsm-00068o-SZ; Sun, 10 Jan 2021 03:15:30 -0500 Received: by mail-pl1-x62a.google.com with SMTP id e2so7874830plt.12; Sun, 10 Jan 2021 00:15:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LQvfnj7woxwAyoAooXJjlnYpcF3uwPljUdCZJXOXThs=; b=G7knzXg6eignm4/rz+x+mn0isCiEYk2zAfWQX0t4TaBQWZsdOUHVdawxZ86/unqHqh 08sXk/5kimwCJN+KwShdwAr2zdj2tBfO49DAQpFDLv5zdMwgs+T9qUUlGts2hV776RtX Urddb69A5iT6J/rf3+DteEDn8FKqDhrfgdlWh9GNVK5JVjRA3Sv2wXlWdz/lkUM5j6Xn zwm551Tgb7rGcWYRwszGXCLWw+DfhcMWqhjyBY92aqXcp16njzi+sG51xnm8EnAjaqrd HUkcIYy/LRvqTM8Zs5msxU2vRzm0ZKOOVRFYWlr1mIgzeLKpGK2PpeDCShhvD1A6anSV VFHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LQvfnj7woxwAyoAooXJjlnYpcF3uwPljUdCZJXOXThs=; b=VSfQSBQNRvREh7CLTJY1VA5icpVpwPTGLkIr1ZBTLq+iOS5ma+1ZuWEZX89wsVoDOn ATtT3sjpRmv0YA4rqQOFXx/qK/MQMEnjBr+otMuRPGfArLIEBXEBtbc13LNeoJaVNaMA 6DLQVVnkPKQZxMSfGvdGJ0urlC8PJgnwY0hD39Qj/uK4yqei7YYv96ZUVHUjjsVBiJ8b wxMOApcr9+hlc5FFsqx+oPZNQunNDEfj48p89FWePKn2kJ5PRcSS5XMMrOgUv97wUqSf hJmmF5on8jEB9njz3oKjrqVquvag79QxSallu/E5QYTAkduFqGTPXdJgSmkritkdqZVT Lk6A== X-Gm-Message-State: AOAM533DDfBd8VskjwdMhB/W6wrY/JV/lU/juijJ+ERbrVlqhL7XNvK9 6JS51IfV4d/ptcVcK0N5lHU= X-Google-Smtp-Source: ABdhPJyIOOiD82ayPsXCVgSWnjNiU2NdSQqvqbbxgVnOJ/MbCn1S8YsU3OIICajUAkvhO1e4bA3z8A== X-Received: by 2002:a17:90a:c8d:: with SMTP id v13mr12105712pja.75.1610266527303; Sun, 10 Jan 2021 00:15:27 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:26 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 5/6] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Sun, 10 Jan 2021 16:14:28 +0800 Message-Id: <20210110081429.10126-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:30 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 7f81b329a4..47c8a0f572 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -187,7 +187,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.25.1 From MAILER-DAEMON Sun Jan 10 03:15:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyVt2-0003LY-Dz for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 03:15:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyVst-0003KB-OW; Sun, 10 Jan 2021 03:15:37 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:42085) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyVsp-0006AE-Go; Sun, 10 Jan 2021 03:15:35 -0500 Received: by mail-pl1-x633.google.com with SMTP id s15so7881972plr.9; Sun, 10 Jan 2021 00:15:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jc5qCCv8yOqGsR9K5aIOE6SIqlfFPiNl3jIRInfxLho=; b=FpDSXqOIAPy2ER5fSbuJzBOGRXd/ke6d5nLDhQOV3qm3lgIz4p0BYQXJth275HT8T5 ijDJ0PGUh/5J5Wd4qqPxWemCadQErF8zioyGvNs9Mvfmp0t2ATnj9z3xMdL8UTrSwv8q NvYZAEZ5YLZthljph77KW8gnzWtvZm4ULbANpKyiWcGiNkmCB/wd9Vq1z7B65s5b4YKi CZ1Cj0vwWAxORoHM/njN06TTX7ghUU90PAyAGmL9wUqbmB1vhT+trPyRoQBUTudwqXU4 fn33GIxwlqtng86943W0FE/qYJ52BISm0xAIeVXZtVJFNZLMAXyWxBWqn1h6q8bbFo6l Datg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jc5qCCv8yOqGsR9K5aIOE6SIqlfFPiNl3jIRInfxLho=; b=XMyTUOiJPgEDoO17qSIL/qTAW4xdpxGCHiX8ZfGF54dhTsocxG7HJtjgDOhaDpkYDz nUE+uKGjkPhpB71SOHj1Tdvy6JhoPxXRqcHM+McZVByrbP6aQFliifAmHCex8ENZrvYz rAuY7L6r0XfIsZIB7fYy3EAxwg5Fft6I7PmxxJvZlmyfhOCY2gJP6w3J84TCT3VPr9CD +RMKLSog39F6HO3j/mvB6QfIjKsTG/WbH2vk2uHT0969IYtZXKD8CobiL5hIUWg3SuVe 8FUHHCjqVJtMnEX8VMBhmuqqst7LnB66hAenqKCRvFKuuIHt97x7IINVZVmDFrtZNomr qM+g== X-Gm-Message-State: AOAM532zJvni0gfy2W9Lv+lyMCIvQ5Yq3c6Q/DlbbaIKyTxlLz/32MbA gPqzGeKzsvo4D+VbHseC6Tc= X-Google-Smtp-Source: ABdhPJzdQkVJKgjc8+6VQAccRhh7AVaBrNnTZh1crqoYj+05CL+Wz/qWdY/mNmF4qdUYP4h+LBT9qg== X-Received: by 2002:a17:90a:4d84:: with SMTP id m4mr12168444pjh.145.1610266529858; Sun, 10 Jan 2021 00:15:29 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id jx4sm13519070pjb.24.2021.01.10.00.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 00:15:29 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v4 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Sun, 10 Jan 2021 16:14:29 +0800 Message-Id: <20210110081429.10126-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210110081429.10126-1-bmeng.cn@gmail.com> References: <20210110081429.10126-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 08:15:38 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 47c8a0f572..b5124a6426 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -171,7 +171,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -192,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -201,13 +200,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.25.1 From MAILER-DAEMON Sun Jan 10 06:15:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyYhN-0001jz-UI for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 06:15:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyYhM-0001jn-G1; Sun, 10 Jan 2021 06:15:52 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:35191) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyYhL-0005Sl-0Y; Sun, 10 Jan 2021 06:15:52 -0500 Received: by mail-wr1-x42b.google.com with SMTP id r3so13418943wrt.2; Sun, 10 Jan 2021 03:15:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=GkDv4xfFHaW/8MrwXHnWCqtNS6/TPnwuCxBpZlEqsxs=; b=QttRMd70OYgLpkrnAiVDKsGNZP8XA7rmWeg37fZEq0zyO55hGUR0NAy5oe812w62z/ zjQ0dzrK//JlwpZBmzdh7ELrIVxWMp0UXPd6+MENFw01KVtmrK/wZ2xfmxfOBNOifCc1 jRblNDOn1D7VadBtneEy+Mvw9pANJSZQdvPKvIj/TbxTFF2Kn0K5fQwI/SiBMOqXcSnF EJSkwFaHVFpJF233Lg4tJodWWxJErz2OcK+JEabLHzmfD4OiVy8pa4hgisTAhC0VlDBh 762DVLREXrn43FWiDwKp8740ptybxiJBwsZG+BW2fItIhAnwKvui+foepwjZdT4XISpZ xOTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=GkDv4xfFHaW/8MrwXHnWCqtNS6/TPnwuCxBpZlEqsxs=; b=OOL5oe9IsrNvtnFr5LYw32oErcp9RJ0cre4N/ZCPIfyhcZdUazqPTZd1TwoY8G5D/s XaKgFkfMwFopstD3OFwKYVWyip6bwXWC/0JHAVtx+53NiZADPTDqzmnxaLfMKi4mr8La sStmoyWqeIO9U0cI6La1av9HnZvNqaJq7qHioinvIbzy6R+86tmMQzljStE5HPgUItie VkyZqSXrax6dQ8wFQirr6tw7keg9o38Iq6RQXUF9mq/OTZKXyg9OeXPZuWm8pxxS7yTa 7/C3Qwje+eY0DZJ4EqDGPOD+cn1hGrAoJjVItM/IVu81gngEdBDLmWv4ta4ZrgMHYGQ+ JEBQ== X-Gm-Message-State: AOAM531A4YQDDkvN1AYoPfzdjow8IxkBX9nJJ5KMPWgezwel27MKjUGX zSEhRkhMl/ZD1le95qecRd0= X-Google-Smtp-Source: ABdhPJwbDZ+9rh1wdw9ZZdP/48jHhyhuiaux4z06M2Iz1n2sGBJBHPar4rk6cNhbcz8mAuvD6v1ZKg== X-Received: by 2002:a5d:530c:: with SMTP id e12mr11769905wrv.54.1610277348984; Sun, 10 Jan 2021 03:15:48 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id c7sm22418489wro.16.2021.01.10.03.15.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Jan 2021 03:15:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <40b62e4a-6139-7427-77bc-b33436687f92@amsat.org> Date: Sun, 10 Jan 2021 12:15:46 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210110081429.10126-3-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 11:15:52 -0000 On 1/10/21 9:14 AM, Bin Meng wrote: > From: Bin Meng > > Usually the approach is that the device on the other end of the line > is going to reset its state anyway, so there's no need to actively > signal an irq line change during the reset hook. > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > imx_spi_hard_reset() that is called when the controller is disabled. > > Signed-off-by: Bin Meng > > --- > > Changes in v4: > - adujst the patch 2,3 order > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > Changes in v3: > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > hw/ssi/imx_spi.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049a21..2c4c5ec1b8 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > imx_spi_rxfifo_reset(s); > imx_spi_txfifo_reset(s); > > - imx_spi_update_irq(s); > - > s->burst_length = 0; > } > > +static void imx_spi_hard_reset(IMXSPIState *s) > +{ > + imx_spi_reset(DEVICE(s)); > + > + imx_spi_update_irq(s); > +} > + > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > { > uint32_t value = 0; > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > s->regs[ECSPI_CONREG] = value; > > if (!imx_spi_is_enabled(s)) { > - /* device is disabled, so this is a reset */ > - imx_spi_reset(DEVICE(s)); > + /* device is disabled, so this is a hard reset */ > + imx_spi_hard_reset(s); > + > return; > } > Almost good :) DeviceReset handler is a hard reset, so you need: dc->reset = imx_spi_hard_reset; Thus you also need this function prototype: void imx_spi_hard_reset(DeviceState *dev) Eventually renaming imx_spi_reset() -> imx_spi_soft_reset() will make things even easier. Regards, Phil. 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id r7sm17937812wmh.2.2021.01.10.03.16.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Jan 2021 03:16:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v4 3/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-4-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <36530f58-0aa7-b861-fbd5-6a41a0cd3a76@amsat.org> Date: Sun, 10 Jan 2021 12:16:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210110081429.10126-4-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.255, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 11:16:33 -0000 On 1/10/21 9:14 AM, Bin Meng wrote: > From: Xuzhou Cheng > > When a write to ECSPI_CONREG register to disable the SPI controller, > imx_spi_reset() is called to reset the controller, but chip select > lines should have been disabled, otherwise the state machine of any > devices (e.g.: SPI flashes) connected to the SPI master is stuck to > its last state and responds incorrectly to any follow-up commands. > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - Move the chip selects disable out of imx_spi_reset() > > Changes in v2: > - Fix the "Fixes" tag in the commit message > > hw/ssi/imx_spi.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Sun Jan 10 07:04:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyZSU-00045i-Oo for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 07:04:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyZST-00045Q-6g; Sun, 10 Jan 2021 07:04:33 -0500 Received: from mail-yb1-xb35.google.com ([2607:f8b0:4864:20::b35]:42420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyZSI-000110-NN; Sun, 10 Jan 2021 07:04:32 -0500 Received: by mail-yb1-xb35.google.com with SMTP id j17so14133172ybt.9; Sun, 10 Jan 2021 04:04:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=xG8U7TIsKlN/tujt2SnC5DAcpADsKwXN5jx1HZq7xoA=; b=N+6y8fmHIRt6FXQcqTurEgi6FseIdbSInE3gCZWiDPaYoiNXy2y6hM/gdPx4FPsem3 NrCgzcKhPby7JX9FJGsIiKKJyoucyktGuOIEn3A9gs3bf+3A00Vty4JbK1reqeb25oTp 8xdzxOHGd7v7JUWgVeKqSpK4KILcSgyHkuZBeJmTnO9wnGB1lQjC4JXlpn4hF9b8P5UW yfmWuNItHgJP0fqB6kk5vRQrd3djDSzAqR/Ibbgw+c0zzW00l7Gz/gGQWcU72H11Xcwe f1Iv1fpncfv1r9y4dqEYYnM+gZ/d7Sx96LEZh8AFHK56wB4GG/fn6zaFIuCV2xbVE+jq DOww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=xG8U7TIsKlN/tujt2SnC5DAcpADsKwXN5jx1HZq7xoA=; b=LZ/RpEMoTVEcCxWRIgNpqof7g73e3s4sMlnQAUaAVvq/vJw3sF1qVPXhIHTBqQ5CGK wEbY465w22a4HFOY+6UF/dTpGfvJ9MnyxjFeXXpfjhPw+yImnw85Nu35Hh0AcL0+a8VG arjtQ6X83Ey0axBdW4KHYud3q360rhnCnAmaPfO2vqZm7P1mA4jDn6w07tbHTPdjtZ1w nnxUqGviBGUYyu0FlE+/iAE4NU1X07kh0fVx4kxsaZWB818YcQR5Agnvyav0eyFV+4ri GZCY1Wp/vJEMm9EqPQMVZpTeVYHqecaSfybyeaxg82rV3Zs5Ip3dx5PI5XGzZiYHbgd2 i3ww== X-Gm-Message-State: AOAM531luXcevwxY+26+5uept8OIJQ4ZQVptON5KlpMtUTU/LtAdaPqG Wj26/E/fe5HnVQJCp47cMFA2cKiIAwiNpMIueuA= X-Google-Smtp-Source: ABdhPJyRMupABjSS3SGTjilsXdils6rBU/t3FdPii3/U+zYgfqlG/xrrm2m5ooq+M0GttqC1QXSHcyUIR7lvX5l6eAo= X-Received: by 2002:a25:690b:: with SMTP id e11mr17502703ybc.314.1610280261611; Sun, 10 Jan 2021 04:04:21 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> <40b62e4a-6139-7427-77bc-b33436687f92@amsat.org> In-Reply-To: <40b62e4a-6139-7427-77bc-b33436687f92@amsat.org> From: Bin Meng Date: Sun, 10 Jan 2021 20:04:10 +0800 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm , "qemu-devel@nongnu.org Developers" , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jan 2021 12:04:33 -0000 Hi Philippe, On Sun, Jan 10, 2021 at 7:15 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/10/21 9:14 AM, Bin Meng wrote: > > From: Bin Meng > > > > Usually the approach is that the device on the other end of the line > > is going to reset its state anyway, so there's no need to actively > > signal an irq line change during the reset hook. > > > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > > imx_spi_hard_reset() that is called when the controller is disabled. > > > > Signed-off-by: Bin Meng > > > > --- > > > > Changes in v4: > > - adujst the patch 2,3 order > > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusio= n > > > > Changes in v3: > > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > > > hw/ssi/imx_spi.c | 14 ++++++++++---- > > 1 file changed, 10 insertions(+), 4 deletions(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index e605049a21..2c4c5ec1b8 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > > imx_spi_rxfifo_reset(s); > > imx_spi_txfifo_reset(s); > > > > - imx_spi_update_irq(s); > > - > > s->burst_length =3D 0; > > } > > > > +static void imx_spi_hard_reset(IMXSPIState *s) > > +{ > > + imx_spi_reset(DEVICE(s)); > > + > > + imx_spi_update_irq(s); > > +} > > + > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned siz= e) > > { > > uint32_t value =3D 0; > > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offs= et, uint64_t value, > > s->regs[ECSPI_CONREG] =3D value; > > > > if (!imx_spi_is_enabled(s)) { > > - /* device is disabled, so this is a reset */ > > - imx_spi_reset(DEVICE(s)); > > + /* device is disabled, so this is a hard reset */ > > + imx_spi_hard_reset(s); > > + > > return; > > } > > > > Almost good :) > > DeviceReset handler is a hard reset, so you need: > > dc->reset =3D imx_spi_hard_reset; > > Thus you also need this function prototype: > > void imx_spi_hard_reset(DeviceState *dev) > > Eventually renaming imx_spi_reset() -> imx_spi_soft_reset() > will make things even easier. Now I am confused. The v3 patch did the above already, but you mentioned that usually the hard reset includes the soft reset. But in the hard reset the imx_spi_update_irq() does not need to be called. Regards, Bin From MAILER-DAEMON Sun Jan 10 20:57:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kymSi-0000iZ-8j for mharc-qemu-arm@gnu.org; Sun, 10 Jan 2021 20:57:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyljw-0001yi-F3; Sun, 10 Jan 2021 20:11:24 -0500 Received: from mail-io1-xd34.google.com ([2607:f8b0:4864:20::d34]:45093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kylju-0007T4-F8; Sun, 10 Jan 2021 20:11:24 -0500 Received: by mail-io1-xd34.google.com with SMTP id n4so16159671iow.12; Sun, 10 Jan 2021 17:11:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=40xBpLb9i5JA4ltONMM4DzrFU4VYMiEYWHZMM/Qqmkk=; b=Mz47lXaKQWi00yo77UwbZK85P1iMJ2oCt5Wzq+qFQnYI8+kFTNZqE2yttwE6ggfJ4B 8nSeeSOB+92QEFbhZ78NSX4r2ntLwWso1xWns3QoMKoN638m8rXR6fKKxq05HfJTQhhb PtQoF/jHCaILpRRJNH9tBRD9o/w2fuH1umnT/EzaIn+5CnwIMfl6AELkQENdAE+mAfKM J74EK7H8dkdUEvEbYv5tDCGYpY8HY8mRfQA6fNU/9W/jOFYgsSg95+olvifWqQfC294v H70JZXKXIPHkRX/WsAsA4T4VCrBb6oOb2DOjmsqNUZKuQxv106zeXsU+gZRM94w5fVxb GxMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=40xBpLb9i5JA4ltONMM4DzrFU4VYMiEYWHZMM/Qqmkk=; b=GOkutqKoYCab9X6zerrLmYzqtNwAqu/koJXpozU062fEFcEmM0zfhUIC9ukjfwWJad LF07TfAxuN+yGm0xnQ9x8OZzmvX0O6jEYzGbD393cECQ9Z9KFbN8cF9tFM2UPZDWvIGf vQ6i9fc3JpslcU3sQ0FE3XrqoaTneg2+uP17AvXf+baVuy96ya0K4X+OCQ+1T4m0oS+Z CzGnyXw3KxUgRLENCjh/V9+d1PqOehIrdY0N54Wv2uyLbNC/auB+ooCM5uGJlnlnwHRP sqtLHa7tpGc3MPrI6yu8yySIlOrsRctXNfE67xxjkBl/CT9PTBF8C9h4clF4Fh88V2A0 kQbQ== X-Gm-Message-State: AOAM532W/TaamU1jvRmuaBTAIoZtasrL/67jyXthKclFr0aCN1aKmBwt usIIG7J+rCVNGHtpEroQ0Os= X-Google-Smtp-Source: ABdhPJwtbFyaFg0BHygcsRMzEUS7s4kD2yXpMBrhSAKmvQQm3/sNY0LE3+VQS1BqqfVM0lAtJgTJ/g== X-Received: by 2002:a02:91c2:: with SMTP id s2mr12672310jag.48.1610327479943; Sun, 10 Jan 2021 17:11:19 -0800 (PST) Received: from ubuntu-m3-large-x86 ([2604:1380:45f1:1d00::1]) by smtp.gmail.com with ESMTPSA id m19sm13943066ila.81.2021.01.10.17.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jan 2021 17:11:19 -0800 (PST) Date: Sun, 10 Jan 2021 18:11:17 -0700 From: Nathan Chancellor To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Peter Maydell , Aleksandar Rikalo , qemu-trivial@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Aleksandar Markovic , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Huacai Chen , Aurelien Jarno , David Gibson , Mark Cave-Ayland Subject: Re: [PATCH 4/5] hw/ppc/ppc4xx_pci: Replace pointless warning by assert() Message-ID: <20210111011117.GA215408@ubuntu-m3-large-x86> References: <20200901104043.91383-1-f4bug@amsat.org> <20200901104043.91383-5-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200901104043.91383-5-f4bug@amsat.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=natechancellor@gmail.com; helo=mail-io1-xd34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 10 Jan 2021 20:57:38 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 01:11:24 -0000 On Tue, Sep 01, 2020 at 12:40:42PM +0200, Philippe Mathieu-Daud wrote: > We call pci_register_root_bus() to register 4 IRQs with the > ppc4xx_pci_set_irq() handler. As it can only be called with > values in the [0-4[ range, replace the pointless warning by > an assert(). > > Signed-off-by: Philippe Mathieu-Daud > --- > hw/ppc/ppc4xx_pci.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c > index cd3f192a138..503ef46b39a 100644 > --- a/hw/ppc/ppc4xx_pci.c > +++ b/hw/ppc/ppc4xx_pci.c > @@ -256,10 +256,7 @@ static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) > qemu_irq *pci_irqs = opaque; > > trace_ppc4xx_pci_set_irq(irq_num); > - if (irq_num < 0) { > - fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); > - return; > - } > + assert(irq_num >= 0); > qemu_set_irq(pci_irqs[irq_num], level); > } > > -- > 2.26.2 > > Hopefully reporting this here is okay, I find Launchpad hard to use but I can file it there if need be. The assertion added by this patch triggers while trying to boot a ppc44x_defconfig Linux kernel: $ qemu-system-ppc \ -machine bamboo \ -no-reboot \ -append console=ttyS0 \ -display none \ -kernel uImage \ -m 128m \ -nodefaults \ -serial mon:stdio Linux version 5.11.0-rc3 (nathan@ubuntu-m3-large-x86) (powerpc-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #1 Sun Jan 10 15:52:24 MST 2021 Using PowerPC 44x Platform machine description ioremap() called early from find_legacy_serial_ports+0x64c/0x794. Use early_ioremap() instead printk: bootconsole [udbg0] enabled ----------------------------------------------------- phys_mem_size = 0x8000000 dcache_bsize = 0x20 icache_bsize = 0x20 cpu_features = 0x0000000000000100 possible = 0x0000000040000100 always = 0x0000000000000100 cpu_user_features = 0x8c008000 0x00000000 mmu_features = 0x00000008 ----------------------------------------------------- Zone ranges: Normal [mem 0x0000000000000000-0x0000000007ffffff] Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000000000000-0x0000000007ffffff] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] MMU: Allocated 1088 bytes of context maps for 255 contexts Built 1 zonelists, mobility grouping on. Total pages: 32448 Kernel command line: console=ttyS0 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) mem auto-init: stack:off, heap alloc:off, heap free:off Memory: 122712K/131072K available (5040K kernel code, 236K rwdata, 1260K rodata, 200K init, 134K bss, 8360K reserved, 0K cma-reserved) Kernel virtual memory layout: * 0xffbdf000..0xfffff000 : fixmap * 0xffbdd000..0xffbdf000 : early ioremap * 0xd1000000..0xffbdd000 : vmalloc & ioremap SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16 UIC0 (32 IRQ sources) at DCR 0xc0 random: get_random_u32 called from start_kernel+0x370/0x508 with crng_init=0 clocksource: timebase: mask: 0xffffffffffffffff max_cycles: 0x5c4093a7d1, max_idle_ns: 440795210635 ns clocksource: timebase mult[2800000] shift[24] registered pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns futex hash table entries: 256 (order: -1, 3072 bytes, linear) NET: Registered protocol family 16 DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations PCI host bridge /plb/pci@ec000000 (primary) ranges: MEM 0x00000000a0000000..0x00000000bfffffff -> 0x00000000a0000000 IO 0x00000000e8000000..0x00000000e800ffff -> 0x0000000000000000 4xx PCI DMA offset set to 0x00000000 4xx PCI DMA window base to 0x0000000000000000 DMA window size 0x0000000080000000 PCI: Probing PCI hardware PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x0000-0xffff] pci_bus 0000:00: root bus resource [mem 0xa0000000-0xbfffffff] pci_bus 0000:00: root bus resource [bus 00-ff] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff pci 0000:00:00.0: [1014:027f] type 00 class 0x068000 qemu-system-ppc: ../hw/ppc/ppc4xx_pci.c:259: ppc4xx_pci_set_irq: Assertion `irq_num >= 0' failed. On v5.2.0, it looks like a higher assertion triggers, added by commit 459ca8bfa4 ("pci: Assert irqnum is between 0 and bus->nirqs in pci_bus_change_irq_level"). qemu-system-ppc: ../hw/pci/pci.c:253: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed. I have uploaded the kernel image here: https://github.com/nathanchance/bug-files/blob/8edf230441bd8eda067973fdf0eb063c94f04379/qemu-0270d74ef886235051c13c39b0de88500c628a02/uImage Cheers, Nathan From MAILER-DAEMON Mon Jan 11 02:35:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyrjH-0005gl-03 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 02:35:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyrjF-0005gM-Ae; Mon, 11 Jan 2021 02:35:05 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2631) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyrjB-0005Kf-S3; Mon, 11 Jan 2021 02:35:04 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DDlnS18f9z7Sdj; Mon, 11 Jan 2021 15:33:48 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.184.42) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Mon, 11 Jan 2021 15:34:40 +0800 From: Keqian Zhu To: Kirti Wankhede , Alex Williamson , , CC: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Stefan Hajnoczi" , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , "Dr . David Alan Gilbert" , Igor Mammedov , , Zenghui Yu , Subject: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener Date: Mon, 11 Jan 2021 15:34:39 +0800 Message-ID: <20210111073439.20236-1-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.35; envelope-from=zhukeqian1@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 07:35:05 -0000 For now the switch of vfio dirty page tracking is integrated into the vfio_save_handler, it causes some problems [1]. The object of dirty tracking is guest memory, but the object of the vfio_save_handler is device state. This mixed logic produces unnecessary coupling and conflicts: 1. Coupling: Their saving granule is different (perVM vs perDevice). vfio will enable dirty_page_tracking for each devices, actually once is enough. 2. Conflicts: The ram_save_setup() traverses all memory_listeners to execute their log_start() and log_sync() hooks to get the first round dirty bitmap, which is used by the bulk stage of ram saving. However, it can't get dirty bitmap from vfio, as @savevm_ram_handlers is registered before @vfio_save_handler. Move the switch of vfio dirty_page_tracking into vfio_memory_listener can solve above problems. Besides, Do not require devices in SAVING state for vfio_sync_dirty_bitmap(). [1] https://www.spinics.net/lists/kvm/msg229967.html Reported-by: Zenghui Yu Signed-off-by: Keqian Zhu --- hw/vfio/common.c | 53 +++++++++++++++++++++++++++++++++++++-------- hw/vfio/migration.c | 35 ------------------------------ 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 6ff1daa763..9128cd7ee1 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -311,7 +311,7 @@ bool vfio_mig_active(void) return true; } -static bool vfio_devices_all_saving(VFIOContainer *container) +static bool vfio_devices_all_dirty_tracking(VFIOContainer *container) { VFIOGroup *group; VFIODevice *vbasedev; @@ -329,13 +329,8 @@ static bool vfio_devices_all_saving(VFIOContainer *container) return false; } - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { - if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) - && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { - return false; - } - continue; - } else { + if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) + && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { return false; } } @@ -987,6 +982,44 @@ static void vfio_listener_region_del(MemoryListener *listener, } } +static void vfio_set_dirty_page_tracking(VFIOContainer *container, bool start) +{ + int ret; + struct vfio_iommu_type1_dirty_bitmap dirty = { + .argsz = sizeof(dirty), + }; + + if (start) { + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; + } else { + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; + } + + ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); + if (ret) { + error_report("Failed to set dirty tracking flag 0x%x errno: %d", + dirty.flags, errno); + } +} + +static void vfio_listener_log_start(MemoryListener *listener, + MemoryRegionSection *section, + int old, int new) +{ + VFIOContainer *container = container_of(listener, VFIOContainer, listener); + + vfio_set_dirty_page_tracking(container, true); +} + +static void vfio_listener_log_stop(MemoryListener *listener, + MemoryRegionSection *section, + int old, int new) +{ + VFIOContainer *container = container_of(listener, VFIOContainer, listener); + + vfio_set_dirty_page_tracking(container, false); +} + static int vfio_get_dirty_bitmap(VFIOContainer *container, uint64_t iova, uint64_t size, ram_addr_t ram_addr) { @@ -1128,7 +1161,7 @@ static void vfio_listerner_log_sync(MemoryListener *listener, return; } - if (vfio_devices_all_saving(container)) { + if (vfio_devices_all_dirty_tracking(container)) { vfio_sync_dirty_bitmap(container, section); } } @@ -1136,6 +1169,8 @@ static void vfio_listerner_log_sync(MemoryListener *listener, static const MemoryListener vfio_memory_listener = { .region_add = vfio_listener_region_add, .region_del = vfio_listener_region_del, + .log_start = vfio_listener_log_start, + .log_stop = vfio_listener_log_stop, .log_sync = vfio_listerner_log_sync, }; diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 00daa50ed8..c0f646823a 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -395,40 +395,10 @@ static int vfio_load_device_config_state(QEMUFile *f, void *opaque) return qemu_file_get_error(f); } -static int vfio_set_dirty_page_tracking(VFIODevice *vbasedev, bool start) -{ - int ret; - VFIOMigration *migration = vbasedev->migration; - VFIOContainer *container = vbasedev->group->container; - struct vfio_iommu_type1_dirty_bitmap dirty = { - .argsz = sizeof(dirty), - }; - - if (start) { - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; - } else { - return -EINVAL; - } - } else { - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; - } - - ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); - if (ret) { - error_report("Failed to set dirty tracking flag 0x%x errno: %d", - dirty.flags, errno); - return -errno; - } - return ret; -} - static void vfio_migration_cleanup(VFIODevice *vbasedev) { VFIOMigration *migration = vbasedev->migration; - vfio_set_dirty_page_tracking(vbasedev, false); - if (migration->region.mmaps) { vfio_region_unmap(&migration->region); } @@ -469,11 +439,6 @@ static int vfio_save_setup(QEMUFile *f, void *opaque) return ret; } - ret = vfio_set_dirty_page_tracking(vbasedev, true); - if (ret) { - return ret; - } - qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE); ret = qemu_file_get_error(f); -- 2.19.1 From MAILER-DAEMON Mon Jan 11 05:04:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyu3v-0005RE-Ue for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 05:04:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyu3t-0005PF-Q0; Mon, 11 Jan 2021 05:04:33 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:32780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyu3r-0008Co-Fs; Mon, 11 Jan 2021 05:04:33 -0500 Received: by mail-ed1-x536.google.com with SMTP id j16so18221667edr.0; Mon, 11 Jan 2021 02:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id t26sm6874307eji.22.2021.01.11.02.04.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 02:04:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 4/5] hw/ppc/ppc4xx_pci: Replace pointless warning by assert() To: Nathan Chancellor , Peter Maydell Cc: qemu-devel@nongnu.org, Peter Maydell , Aleksandar Rikalo , qemu-trivial@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Aleksandar Markovic , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Huacai Chen , Aurelien Jarno , David Gibson , Mark Cave-Ayland References: <20200901104043.91383-1-f4bug@amsat.org> <20200901104043.91383-5-f4bug@amsat.org> <20210111011117.GA215408@ubuntu-m3-large-x86> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9bf21ccd-7e23-8329-35b8-bf09d35e335b@amsat.org> Date: Mon, 11 Jan 2021 11:04:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210111011117.GA215408@ubuntu-m3-large-x86> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.012, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 10:04:34 -0000 +Peter On 1/11/21 2:11 AM, Nathan Chancellor wrote: > On Tue, Sep 01, 2020 at 12:40:42PM +0200, Philippe Mathieu-Daudé wrote: >> We call pci_register_root_bus() to register 4 IRQs with the >> ppc4xx_pci_set_irq() handler. As it can only be called with >> values in the [0-4[ range, replace the pointless warning by >> an assert(). >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/ppc/ppc4xx_pci.c | 5 +---- >> 1 file changed, 1 insertion(+), 4 deletions(-) >> >> diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c >> index cd3f192a138..503ef46b39a 100644 >> --- a/hw/ppc/ppc4xx_pci.c >> +++ b/hw/ppc/ppc4xx_pci.c >> @@ -256,10 +256,7 @@ static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) >> qemu_irq *pci_irqs = opaque; >> >> trace_ppc4xx_pci_set_irq(irq_num); >> - if (irq_num < 0) { >> - fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); >> - return; >> - } >> + assert(irq_num >= 0); >> qemu_set_irq(pci_irqs[irq_num], level); >> } >> >> -- >> 2.26.2 >> >> > > Hopefully reporting this here is okay, I find Launchpad hard to use but > I can file it there if need be. > > The assertion added by this patch triggers while trying to boot a > ppc44x_defconfig Linux kernel: > > $ qemu-system-ppc \ > -machine bamboo \ > -no-reboot \ > -append console=ttyS0 \ > -display none \ > -kernel uImage \ > -m 128m \ > -nodefaults \ > -serial mon:stdio > Linux version 5.11.0-rc3 (nathan@ubuntu-m3-large-x86) (powerpc-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #1 Sun Jan 10 15:52:24 MST 2021 > Using PowerPC 44x Platform machine description > ioremap() called early from find_legacy_serial_ports+0x64c/0x794. Use early_ioremap() instead ... > PCI: Probing PCI hardware > PCI host bridge to bus 0000:00 > pci_bus 0000:00: root bus resource [io 0x0000-0xffff] > pci_bus 0000:00: root bus resource [mem 0xa0000000-0xbfffffff] > pci_bus 0000:00: root bus resource [bus 00-ff] > pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff > pci 0000:00:00.0: [1014:027f] type 00 class 0x068000 > qemu-system-ppc: ../hw/ppc/ppc4xx_pci.c:259: ppc4xx_pci_set_irq: Assertion `irq_num >= 0' failed. > > On v5.2.0, it looks like a higher assertion triggers, added by > commit 459ca8bfa4 ("pci: Assert irqnum is between 0 and bus->nirqs in > pci_bus_change_irq_level"). > > qemu-system-ppc: ../hw/pci/pci.c:253: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed. Running with '-trace ppc4xx_pci\*': 1275265@1610357661.994462:ppc4xx_pci_map_irq devfn 0x0 irq 0 -> 0 1275265@1610357661.994480:ppc4xx_pci_set_irq PCI irq -1 (gdb) bt #0 0x00007fc70a8a19e5 in raise () at /lib64/libc.so.6 #1 0x00007fc70a88a895 in abort () at /lib64/libc.so.6 #2 0x00007fc70a88a769 in _nl_load_domain.cold () at /lib64/libc.so.6 #3 0x00007fc70a899e76 in annobin_assert.c_end () at /lib64/libc.so.6 #4 0x0000560953c2bfe0 in ppc4xx_pci_set_irq (opaque=0x560955dcf9a0, irq_num=-1, level=0) at hw/ppc/ppc4xx_pci.c:259 #5 0x0000560953a20474 in pci_change_irq_level (pci_dev=0x560955dd0e40, irq_num=-1, change=0) at hw/pci/pci.c:262 #6 0x0000560953a1d028 in pci_update_irq_disabled (d=0x560955dd0e40, was_irq_disabled=0) at hw/pci/pci.c:1375 #7 0x0000560953a1ccb3 in pci_default_write_config (d=0x560955dd0e40, addr=4, val_in=1030, l=2) at hw/pci/pci.c:1415 #8 0x0000560953978977 in pci_host_config_write_common (pci_dev=0x560955dd0e40, addr=4, limit=256, val=1030, len=2) at hw/pci/pci_host.c:83 #9 0x0000560953978cb9 in pci_data_write (s=0x560955dd0210, addr=2147483652, val=1030, len=2) at hw/pci/pci_host.c:120 #10 0x0000560953978eeb in pci_host_data_write (opaque=0x560955dcf350, addr=0, val=1030, len=2) at hw/pci/pci_host.c:167 How can irq be -1? pci_update_irq_disabled() hasn't been updated since commit a7b15a5cc626 (2009-12-23): 1368 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1369 { 1370 int i, disabled = pci_irq_disabled(d); 1371 if (disabled == was_irq_disabled) 1372 return; 1373 for (i = 0; i < PCI_NUM_PINS; ++i) { 1374 int state = pci_irq_state(d, i); 1375 pci_change_irq_level(d, i, disabled ? -state : state); 1376 } 1377 } Let's rebuild using --enable-sanitizers to check an overflow occured: 1286013@1610358549.342593:ppc4xx_pci_map_irq devfn 0x0 irq 0 -> 0 ================================================================= ==1286011==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200004f78c at pc 0x55b6d738454c bp 0x7f779b9f7810 sp 0x7f779b9f7808 READ of size 4 at 0x60200004f78c thread T2 #0 0x55b6d738454b in pci_change_irq_level hw/pci/pci.c:261:29 #1 0x55b6d73763be in pci_update_irq_disabled hw/pci/pci.c:1375:9 #2 0x55b6d7374e2d in pci_default_write_config hw/pci/pci.c:1415:9 #3 0x55b6d70cb8ec in pci_host_config_write_common hw/pci/pci_host.c:83:5 #4 0x55b6d70cc43f in pci_data_write hw/pci/pci_host.c:120:5 #5 0x55b6d70ccd43 in pci_host_data_write hw/pci/pci_host.c:167:9 #6 0x55b6d8505348 in memory_region_write_accessor softmmu/memory.c:483:5 #7 0x55b6d8504c1a in access_with_adjusted_size softmmu/memory.c:544:18 #8 0x55b6d8503316 in memory_region_dispatch_write softmmu/memory.c:1465:16 #9 0x55b6d878ab51 in flatview_write_continue exec.c:3177:23 #10 0x55b6d8779046 in flatview_write exec.c:3217:14 #11 0x55b6d879d1ab in subpage_write exec.c:2829:12 #12 0x55b6d8505af7 in memory_region_write_with_attrs_accessor softmmu/memory.c:503:12 #13 0x55b6d8504af4 in access_with_adjusted_size softmmu/memory.c:539:18 #14 0x55b6d850376e in memory_region_dispatch_write softmmu/memory.c:1472:13 #15 0x55b6d8485b60 in io_writex accel/tcg/cputlb.c:1121:9 #16 0x55b6d845ef8b in store_helper accel/tcg/cputlb.c:2140:13 #17 0x55b6d845f558 in helper_le_stw_mmu accel/tcg/cputlb.c:2194:5 #18 0x7f77a40c0252 () 0x60200004f78c is located 4 bytes to the left of 16-byte region [0x60200004f790,0x60200004f7a0) allocated by thread T0 here: #0 0x55b6d6ab9227 in calloc (qemu-system-ppc+0x1a9f227) #1 0x7f77f3ab19b0 in g_malloc0 (/lib64/libglib-2.0.so.0+0x589b0) #2 0x55b6d7370ef0 in pci_register_root_bus hw/pci/pci.c:493:5 #3 0x55b6d7dec5de in ppc4xx_pcihost_realize hw/ppc/ppc4xx_pci.c:318:9 #4 0x55b6d8a04ffb in device_set_realized hw/core/qdev.c:864:13 #5 0x55b6d89309e8 in property_set_bool qom/object.c:2202:5 #6 0x55b6d8928f92 in object_property_set qom/object.c:1349:5 #7 0x55b6d891aa29 in object_property_set_qobject qom/qom-qobject.c:28:10 #8 0x55b6d8929d71 in object_property_set_bool qom/object.c:1416:15 #9 0x55b6d89f76fc in qdev_realize hw/core/qdev.c:379:12 #10 0x55b6d89f7734 in qdev_realize_and_unref hw/core/qdev.c:386:11 #11 0x55b6d7ccc37e in sysbus_realize_and_unref hw/core/sysbus.c:261:12 #12 0x55b6d7ccc0a3 in sysbus_create_varargs hw/core/sysbus.c:236:5 #13 0x55b6d7dbce60 in bamboo_init hw/ppc/ppc440_bamboo.c:212:11 #14 0x55b6d6c3cdae in machine_run_board_init hw/core/machine.c:1144:5 #15 0x55b6d86893ee in qemu_init softmmu/vl.c:4355:5 #16 0x55b6d6af0f49 in main softmmu/main.c:49:5 #17 0x7f77f23bd041 in __libc_start_main (/lib64/libc.so.6+0x27041) Thread T2 created by T0 here: #0 0x55b6d6a32bb6 in pthread_create (qemu-system-ppc+0x1a18bb6) #1 0x55b6d92a1df4 in qemu_thread_create util/qemu-thread-posix.c:558:11 #2 0x55b6d8807dc5 in qemu_tcg_init_vcpu softmmu/cpus.c:1926:13 #3 0x55b6d8807142 in qemu_init_vcpu softmmu/cpus.c:2047:9 #4 0x55b6d7e79f88 in ppc_cpu_realize target/ppc/translate_init.c.inc:10146:5 #5 0x55b6d8a04ffb in device_set_realized hw/core/qdev.c:864:13 #6 0x55b6d89309e8 in property_set_bool qom/object.c:2202:5 #7 0x55b6d8928f92 in object_property_set qom/object.c:1349:5 #8 0x55b6d891aa29 in object_property_set_qobject qom/qom-qobject.c:28:10 #9 0x55b6d8929d71 in object_property_set_bool qom/object.c:1416:15 #10 0x55b6d89f76fc in qdev_realize hw/core/qdev.c:379:12 #11 0x55b6d724d4db in cpu_create hw/core/cpu.c:62:10 #12 0x55b6d7dbc024 in bamboo_init hw/ppc/ppc440_bamboo.c:183:11 #13 0x55b6d6c3cdae in machine_run_board_init hw/core/machine.c:1144:5 #14 0x55b6d86893ee in qemu_init softmmu/vl.c:4355:5 #15 0x55b6d6af0f49 in main softmmu/main.c:49:5 #16 0x7f77f23bd041 in __libc_start_main (/lib64/libc.so.6+0x27041) SUMMARY: AddressSanitizer: heap-buffer-overflow hw/pci/pci.c:261:29 in pci_change_irq_level Shadow bytes around the buggy address: 0x0c0480001ea0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 0x0c0480001eb0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 0x0c0480001ec0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 0x0c0480001ed0: fa fa 00 00 fa fa 00 00 fa fa 00 01 fa fa 05 fa 0x0c0480001ee0: fa fa 06 fa fa fa fd fd fa fa 06 fa fa fa 00 03 =>0x0c0480001ef0: fa[fa]00 00 fa fa fd fa fa fa fd fa fa fa fd fa 0x0c0480001f00: fa fa fd fa fa fa 00 01 fa fa fd fd fa fa fd fa 0x0c0480001f10: fa fa fd fd fa fa 00 02 fa fa fd fa fa fa 00 02 0x0c0480001f20: fa fa 05 fa fa fa 07 fa fa fa 00 01 fa fa 07 fa 0x0c0480001f30: fa fa 05 fa fa fa 07 fa fa fa fd fd fa fa 00 02 0x0c0480001f40: fa fa 05 fa fa fa 07 fa fa fa 00 01 fa fa 07 fa Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb Shadow gap: cc ==1286011==ABORTING I see this sysbus_create_varargs() call in bamboo_init() has recently been updated by Peter in commit 0270d74ef88 ("hw/ppc/ppc440_bamboo: Drop use of ppcuic_init()"). Running with current master (7b09f127738) the assert is not reached: Linux version 5.11.0-rc3 (nathan@ubuntu-m3-large-x86) (powerpc-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #1 Sun Jan 10 15:52:24 MST 2021 Using PowerPC 44x Platform machine description ioremap() called early from find_legacy_serial_ports+0x64c/0x794. Use early_ioremap() instead printk: bootconsole [udbg0] enabled ----------------------------------------------------- phys_mem_size = 0x8000000 dcache_bsize = 0x20 icache_bsize = 0x20 cpu_features = 0x0000000000000100 possible = 0x0000000040000100 always = 0x0000000000000100 cpu_user_features = 0x8c008000 0x00000000 mmu_features = 0x00000008 ----------------------------------------------------- Zone ranges: Normal [mem 0x0000000000000000-0x0000000007ffffff] Movable zone start for each node Early memory node ranges node 0: [mem 0x0000000000000000-0x0000000007ffffff] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] MMU: Allocated 1088 bytes of context maps for 255 contexts Built 1 zonelists, mobility grouping on. Total pages: 32448 Kernel command line: console=ttyS0 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) mem auto-init: stack:off, heap alloc:off, heap free:off Memory: 122712K/131072K available (5040K kernel code, 236K rwdata, 1260K rodata, 200K init, 134K bss, 8360K reserved, 0K cma-reserved) Kernel virtual memory layout: * 0xffbdf000..0xfffff000 : fixmap * 0xffbdd000..0xffbdf000 : early ioremap * 0xd1000000..0xffbdd000 : vmalloc & ioremap SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16 Oops: Exception in kernel mode, sig: 4 [#1] BE PAGE_SIZE=4K PowerPC 44x Platform Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 5.11.0-rc3 #1 NIP: c0019e58 LR: c062e3a0 CTR: c0019e58 REGS: c067fe90 TRAP: 0700 Not tainted (5.11.0-rc3) MSR: 000a1000 CR: 84000224 XER: 20000000 GPR00: c062e370 c067ff50 c065c300 c0019e58 00000000 c0019238 c067fde0 c065c300 GPR08: 00000000 00000000 c066fca4 00000066 84000222 00000000 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 c0000010 00000000 GPR24: c0651594 c0651594 c0690000 c7ffe080 c0690000 c05c6f64 c0680000 c0802100 NIP [c0019e58] __mtdcr_table+0xc20/0x3ff8 LR [c062e3a0] uic_init_one+0x13c/0x214 Call Trace: [c067ff50] [c062e370] uic_init_one+0x10c/0x214 (unreliable) [c067ff80] [c062e4f8] uic_init_tree+0x80/0x174 [c067ffb0] [c0627af8] start_kernel+0x33c/0x508 [c067fff0] [c0000044] _start+0x44/0x88 Instruction dump: 7c9f2b86 4e800020 7c603286 4e800020 7c803386 4e800020 7c613286 4e800020 7c813386 4e800020 7c623286 4e800020 <7c823386> 4e800020 7c633286 4e800020 random: get_random_bytes called from oops_exit+0x44/0x84 with crng_init=0 ---[ end trace 0000000000000000 ]--- Kernel panic - not syncing: Attempted to kill the idle task! Rebooting in 180 seconds.. I suppose we can end this thread as NOTABUG. Thanks for testing and your report, Phil. From MAILER-DAEMON Mon Jan 11 05:30:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyuSu-0006Z0-Mq for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 05:30:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyuSs-0006XX-Ra; Mon, 11 Jan 2021 05:30:22 -0500 Received: from mail-il1-x130.google.com ([2607:f8b0:4864:20::130]:42224) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyuSr-0003bX-CH; Mon, 11 Jan 2021 05:30:22 -0500 Received: by mail-il1-x130.google.com with SMTP id t3so13708898ilh.9; Mon, 11 Jan 2021 02:30:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5nSU6fUOxAJjBR8ApEe65dcbCJlA4HQiEorIUVGq9lo=; b=aVEwhY0hlLS5h90fgub7GMKQxSB1/L2/TN4AShMkxLporyqlp4GSEDcGIE1oLljb40 SXucZZrzgcERc/j37m4F0monqAlz4l0ZE5RQlzSliVlstGBgeqFsvIXl8Szqme3rV3FZ w6uaCASYsDUzRaXblD+AWazorKve78YjazsL2RiOMjJeglF4FQx3jHxQGn49oHm/ot26 wmBNP6+7Pz7QmyY4Mtd7VnOH4bObRJigjhCyMcqy8NIYNeXc05+wdR6Ob6AT9OlRL8Ev 28vhFzO8YqOWq+8ATJ1d441ShW/80h8VeT8UpwYdn2z1+GH+SvEY6cLTJdR8M4pTkWFD b2LA== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=laurent.desnogues@gmail.com; helo=mail-il1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 10:30:23 -0000 On Fri, Jan 8, 2021 at 7:51 PM Leif Lindholm wrote: > > Signed-off-by: Leif Lindholm Reviewed-by: Laurent Desnogues Thanks, Laurent > --- > target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 063228de2a..18c1cb02bb 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1736,6 +1736,37 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1) > /* > * System register ID fields. > */ > +FIELD(CLIDR_EL1, CTYPE1, 0, 3) > +FIELD(CLIDR_EL1, CTYPE2, 3, 3) > +FIELD(CLIDR_EL1, CTYPE3, 6, 3) > +FIELD(CLIDR_EL1, CTYPE4, 9, 3) > +FIELD(CLIDR_EL1, CTYPE5, 12, 3) > +FIELD(CLIDR_EL1, CTYPE6, 15, 3) > +FIELD(CLIDR_EL1, CTYPE7, 18, 3) > +FIELD(CLIDR_EL1, LOUIS, 21, 3) > +FIELD(CLIDR_EL1, LOC, 24, 3) > +FIELD(CLIDR_EL1, LOUU, 27, 3) > +FIELD(CLIDR_EL1, ICB, 30, 3) > + > +/* When FEAT_CCIDX is implemented */ > +FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) > +FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) > +FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) > + > +/* When FEAT_CCIDX is not implemented */ > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3) > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) > +FIELD(CCSIDR_EL1, NUMSETS, 13, 15) > + > +FIELD(CTR_EL0, IMINLINE, 0, 4) > +FIELD(CTR_EL0, L1IP, 14, 2) > +FIELD(CTR_EL0, DMINLINE, 16, 4) > +FIELD(CTR_EL0, ERG, 20, 4) > +FIELD(CTR_EL0, CWG, 24, 4) > +FIELD(CTR_EL0, IDC, 28, 1) > +FIELD(CTR_EL0, DIC, 29, 1) > +FIELD(CTR_EL0, TMINLINE, 32, 6) > + > FIELD(MIDR_EL1, REVISION, 0, 4) > FIELD(MIDR_EL1, PARTNUM, 4, 12) > FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) > -- > 2.20.1 > From MAILER-DAEMON Mon Jan 11 05:31:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyuU8-00078m-37 for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=laurent.desnogues@gmail.com; helo=mail-il1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 10:31:36 -0000 On Fri, Jan 8, 2021 at 7:51 PM Leif Lindholm wrote: > > When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the > TminLine field in bits [37:32]. > Extend the ctr field to be able to hold this context. > > Signed-off-by: Leif Lindholm Reviewed-by: Laurent Desnogues Thanks, Laurent > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index fadd1a47df..063228de2a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -931,7 +931,7 @@ struct ARMCPU { > uint64_t midr; > uint32_t revidr; > uint32_t reset_fpsid; > - uint32_t ctr; > + uint64_t ctr; > uint32_t reset_sctlr; > uint64_t pmceid0; > uint64_t pmceid1; > -- > 2.20.1 > From MAILER-DAEMON Mon Jan 11 08:21:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyx8B-0008B1-9v for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 08:21:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyx86-00088M-Sy for qemu-arm@nongnu.org; Mon, 11 Jan 2021 08:21:08 -0500 Received: from mail-qk1-x72c.google.com ([2607:f8b0:4864:20::72c]:43072) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyx7w-00057b-Qu for qemu-arm@nongnu.org; Mon, 11 Jan 2021 08:21:06 -0500 Received: by mail-qk1-x72c.google.com with SMTP id 143so14436368qke.10 for ; Mon, 11 Jan 2021 05:20:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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([2804:7f0:8284:874d:20e9:a3d4:1db5:c30a]) by smtp.gmail.com with ESMTPSA id c139sm8439799qke.24.2021.01.11.05.20.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 05:20:51 -0800 (PST) Subject: Re: [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , "open list:ARM TCG CPUs" References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-11-alex.bennee@linaro.org> From: Luis Machado Message-ID: <9ee1443e-821d-9cec-c29a-6111385937ad@linaro.org> Date: Mon, 11 Jan 2021 10:20:48 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108224256.2321-11-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=luis.machado@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 13:21:08 -0000 For the record, the layout looks OK to me. Just a reminder that GDB will soon support bfloat16 types. A patch may be pushed this month. On 1/8/21 7:42 PM, Alex Bennée wrote: > While GDB can work with any XML description given to it there is > special handling for SVE registers on the GDB side which makes the > users life a little better. The changes aren't that major and all the > registers save the $vg reported the same. All that changes is: > > - report org.gnu.gdb.aarch64.sve > - use gdb nomenclature for names and types > - minor re-ordering of the types to match reference > - re-enable ieee_half (as we know gdb supports it now) > - $vg is now a 64 bit int > - check $vN and $zN aliasing in test > > Signed-off-by: Alex Bennée > Cc: Luis Machado > Message-Id: <20201218112707.28348-10-alex.bennee@linaro.org> > Signed-off-by: Alex Bennée > --- > target/arm/gdbstub.c | 75 ++++++++------------- > target/arm/helper.c | 2 +- > tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +++ > 3 files changed, 41 insertions(+), 47 deletions(-) > > diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > index 866595b4f1..a8fff2a3d0 100644 > --- a/target/arm/gdbstub.c > +++ b/target/arm/gdbstub.c > @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { > { "uint128", 128, 'q', 'u' }, > { "int128", 128, 'q', 's' }, > /* 64 bit */ > + { "ieee_double", 64, 'd', 'f' }, > { "uint64", 64, 'd', 'u' }, > { "int64", 64, 'd', 's' }, > - { "ieee_double", 64, 'd', 'f' }, > /* 32 bit */ > + { "ieee_single", 32, 's', 'f' }, > { "uint32", 32, 's', 'u' }, > { "int32", 32, 's', 's' }, > - { "ieee_single", 32, 's', 'f' }, > /* 16 bit */ > + { "ieee_half", 16, 'h', 'f' }, > { "uint16", 16, 'h', 'u' }, > { "int16", 16, 'h', 's' }, > - /* > - * TODO: currently there is no reliable way of telling > - * if the remote gdb actually understands ieee_half so > - * we don't expose it in the target description for now. > - * { "ieee_half", 16, 'h', 'f' }, > - */ > /* bytes */ > { "uint8", 8, 'b', 'u' }, > { "int8", 8, 'b', 's' }, > @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > GString *s = g_string_new(NULL); > DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; > g_autoptr(GString) ts = g_string_new(""); > - int i, bits, reg_width = (cpu->sve_max_vq * 128); > + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); > info->num = 0; > g_string_printf(s, ""); > g_string_append_printf(s, ""); > - g_string_append_printf(s, ""); > + g_string_append_printf(s, ""); > > /* First define types and totals in a whole VL */ > for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > int count = reg_width / vec_lanes[i].size; > - g_string_printf(ts, "vq%d%c%c", count, > - vec_lanes[i].sz, vec_lanes[i].suffix); > + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); > g_string_append_printf(s, > "", > ts->str, vec_lanes[i].gdb_type, count); > @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > * signed and potentially float versions of each size from 128 to > * 8 bits. > */ > - for (bits = 128; bits >= 8; bits /= 2) { > - int count = reg_width / bits; > - g_string_append_printf(s, "", count); > - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > - if (vec_lanes[i].size == bits) { > - g_string_append_printf(s, "", > - vec_lanes[i].suffix, > - count, > - vec_lanes[i].sz, vec_lanes[i].suffix); > + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { > + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; > + g_string_append_printf(s, "", suf[i]); > + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { > + if (vec_lanes[j].size == bits) { > + g_string_append_printf(s, "", > + vec_lanes[j].suffix, > + vec_lanes[j].sz, vec_lanes[j].suffix); > } > } > g_string_append(s, ""); > } > /* And now the final union of unions */ > - g_string_append(s, ""); > - for (bits = 128; bits >= 8; bits /= 2) { > - int count = reg_width / bits; > - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > - if (vec_lanes[i].size == bits) { > - g_string_append_printf(s, "", > - vec_lanes[i].sz, count); > - break; > - } > - } > + g_string_append(s, ""); > + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { > + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; > + g_string_append_printf(s, "", > + suf[i], suf[i]); > } > g_string_append(s, ""); > > + /* Finally the sve prefix type */ > + g_string_append_printf(s, > + "", > + reg_width / 8); > + > /* Then define each register in parts for each vq */ > for (i = 0; i < 32; i++) { > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"vq\"/>", > + " regnum=\"%d\" type=\"svev\"/>", > i, reg_width, base_reg++); > info->num++; > } > @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > " regnum=\"%d\" group=\"float\"" > " type=\"int\"/>", base_reg++); > info->num += 2; > - /* > - * Predicate registers aren't so big they are worth splitting up > - * but we do need to define a type to hold the array of quad > - * references. > - */ > - g_string_append_printf(s, > - "", > - cpu->sve_max_vq); > + > for (i = 0; i < 16; i++) { > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"vqp\"/>", > + " regnum=\"%d\" type=\"svep\"/>", > i, cpu->sve_max_vq * 16, base_reg++); > info->num++; > } > g_string_append_printf(s, > " " regnum=\"%d\" group=\"vector\"" > - " type=\"vqp\"/>", > + " type=\"svep\"/>", > cpu->sve_max_vq * 16, base_reg++); > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"uint32\"/>", > + " regnum=\"%d\" type=\"int\"/>", > base_reg++); > info->num += 2; > g_string_append_printf(s, ""); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d077dd9ef5..d434044f07 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) > * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. > */ > int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; > - return gdb_get_reg32(buf, vq * 2); > + return gdb_get_reg64(buf, vq * 2); > } > default: > /* gdbstub asked for something out our range */ > diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > index 972cf73c31..b9ef169c1a 100644 > --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): > except gdb.error: > report(False, "checking zregs (out of range)") > > + # Check the aliased V registers are set and GDB has correctly > + # created them for us having recognised and handled SVE. > + try: > + for i in range(0, 16): > + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) > + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) > + report(int(val_z) == int(val_v), > + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) > + except gdb.error: > + report(False, "checking vregs (out of range)") > + > > def run_test(): > "Run through the tests one by one" > From MAILER-DAEMON Mon Jan 11 09:37:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyKQ-0002WI-Bt for mharc-qemu-arm@gnu.org; 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Mon, 11 Jan 2021 06:37:46 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2E85A1FF7E; Mon, 11 Jan 2021 14:37:46 +0000 (GMT) References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-11-alex.bennee@linaro.org> <9ee1443e-821d-9cec-c29a-6111385937ad@linaro.org> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Luis Machado Cc: qemu-devel@nongnu.org, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Date: Mon, 11 Jan 2021 14:36:36 +0000 In-reply-to: <9ee1443e-821d-9cec-c29a-6111385937ad@linaro.org> Message-ID: <87zh1fo7yd.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 14:37:52 -0000 Luis Machado writes: > For the record, the layout looks OK to me. So a Reviewed-by? > Just a reminder that GDB will soon support bfloat16 types. A patch may=20 > be pushed this month. Will we be able to probe for the support - or will an older GDB silently accept and drop any bfloat16 fields? > > On 1/8/21 7:42 PM, Alex Benn=C3=A9e wrote: >> While GDB can work with any XML description given to it there is >> special handling for SVE registers on the GDB side which makes the >> users life a little better. The changes aren't that major and all the >> registers save the $vg reported the same. All that changes is: >>=20 >> - report org.gnu.gdb.aarch64.sve >> - use gdb nomenclature for names and types >> - minor re-ordering of the types to match reference >> - re-enable ieee_half (as we know gdb supports it now) >> - $vg is now a 64 bit int >> - check $vN and $zN aliasing in test >>=20 >> Signed-off-by: Alex Benn=C3=A9e >> Cc: Luis Machado >> Message-Id: <20201218112707.28348-10-alex.bennee@linaro.org> >> Signed-off-by: Alex Benn=C3=A9e >> --- >> target/arm/gdbstub.c | 75 ++++++++------------- >> target/arm/helper.c | 2 +- >> tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +++ >> 3 files changed, 41 insertions(+), 47 deletions(-) >>=20 >> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >> index 866595b4f1..a8fff2a3d0 100644 >> --- a/target/arm/gdbstub.c >> +++ b/target/arm/gdbstub.c >> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] =3D { >> { "uint128", 128, 'q', 'u' }, >> { "int128", 128, 'q', 's' }, >> /* 64 bit */ >> + { "ieee_double", 64, 'd', 'f' }, >> { "uint64", 64, 'd', 'u' }, >> { "int64", 64, 'd', 's' }, >> - { "ieee_double", 64, 'd', 'f' }, >> /* 32 bit */ >> + { "ieee_single", 32, 's', 'f' }, >> { "uint32", 32, 's', 'u' }, >> { "int32", 32, 's', 's' }, >> - { "ieee_single", 32, 's', 'f' }, >> /* 16 bit */ >> + { "ieee_half", 16, 'h', 'f' }, >> { "uint16", 16, 'h', 'u' }, >> { "int16", 16, 'h', 's' }, >> - /* >> - * TODO: currently there is no reliable way of telling >> - * if the remote gdb actually understands ieee_half so >> - * we don't expose it in the target description for now. >> - * { "ieee_half", 16, 'h', 'f' }, >> - */ >> /* bytes */ >> { "uint8", 8, 'b', 'u' }, >> { "int8", 8, 'b', 's' }, >> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> GString *s =3D g_string_new(NULL); >> DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; >> g_autoptr(GString) ts =3D g_string_new(""); >> - int i, bits, reg_width =3D (cpu->sve_max_vq * 128); >> + int i, j, bits, reg_width =3D (cpu->sve_max_vq * 128); >> info->num =3D 0; >> g_string_printf(s, ""); >> g_string_append_printf(s, ""); >> - g_string_append_printf(s, ""); >> + g_string_append_printf(s, ""); >>=20=20=20 >> /* First define types and totals in a whole VL */ >> for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> int count =3D reg_width / vec_lanes[i].size; >> - g_string_printf(ts, "vq%d%c%c", count, >> - vec_lanes[i].sz, vec_lanes[i].suffix); >> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].s= uffix); >> g_string_append_printf(s, >> "", >> ts->str, vec_lanes[i].gdb_type, count); >> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> * signed and potentially float versions of each size from 128 to >> * 8 bits. >> */ >> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >> - int count =3D reg_width / bits; >> - g_string_append_printf(s, "", count); >> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size =3D=3D bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].suffix, >> - count, >> - vec_lanes[i].sz, vec_lanes[i].su= ffix); >> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", suf[i]); >> + for (j =3D 0; j < ARRAY_SIZE(vec_lanes); j++) { >> + if (vec_lanes[j].size =3D=3D bits) { >> + g_string_append_printf(s, "", >> + vec_lanes[j].suffix, >> + vec_lanes[j].sz, vec_lanes[j].su= ffix); >> } >> } >> g_string_append(s, ""); >> } >> /* And now the final union of unions */ >> - g_string_append(s, ""); >> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >> - int count =3D reg_width / bits; >> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size =3D=3D bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].sz, count); >> - break; >> - } >> - } >> + g_string_append(s, ""); >> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", >> + suf[i], suf[i]); >> } >> g_string_append(s, ""); >>=20=20=20 >> + /* Finally the sve prefix type */ >> + g_string_append_printf(s, >> + "", >> + reg_width / 8); >> + >> /* Then define each register in parts for each vq */ >> for (i =3D 0; i < 32; i++) { >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vq\"/>", >> + " regnum=3D\"%d\" type=3D\"svev\"/>", >> i, reg_width, base_reg++); >> info->num++; >> } >> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> " regnum=3D\"%d\" group=3D\"float\"" >> " type=3D\"int\"/>", base_reg++); >> info->num +=3D 2; >> - /* >> - * Predicate registers aren't so big they are worth splitting up >> - * but we do need to define a type to hold the array of quad >> - * references. >> - */ >> - g_string_append_printf(s, >> - "", >> - cpu->sve_max_vq); >> + >> for (i =3D 0; i < 16; i++) { >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vqp\"/>", >> + " regnum=3D\"%d\" type=3D\"svep\"/>", >> i, cpu->sve_max_vq * 16, base_reg++); >> info->num++; >> } >> g_string_append_printf(s, >> "> " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vqp\"/>", >> + " type=3D\"svep\"/>", >> cpu->sve_max_vq * 16, base_reg++); >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"uint32\"/>", >> + " regnum=3D\"%d\" type=3D\"int\"/>", >> base_reg++); >> info->num +=3D 2; >> g_string_append_printf(s, ""); >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index d077dd9ef5..d434044f07 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByt= eArray *buf, int reg) >> * while the ZCR works in Vector Quads (VQ) which is 128bit ch= unks. >> */ >> int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >> - return gdb_get_reg32(buf, vq * 2); >> + return gdb_get_reg64(buf, vq * 2); >> } >> default: >> /* gdbstub asked for something out our range */ >> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aar= ch64/gdbstub/test-sve-ioctl.py >> index 972cf73c31..b9ef169c1a 100644 >> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >> except gdb.error: >> report(False, "checking zregs (out of range)") >>=20=20=20 >> + # Check the aliased V registers are set and GDB has correctly >> + # created them for us having recognised and handled SVE. >> + try: >> + for i in range(0, 16): >> + val_z =3D gdb.parse_and_eval("$z0.b.u[%d]" % i) >> + val_v =3D gdb.parse_and_eval("$v0.b.u[%d]" % i) >> + report(int(val_z) =3D=3D int(val_v), >> + "v0.b.u[%d] =3D=3D z0.b.u[%d]" % (i, i)) >> + except gdb.error: >> + report(False, "checking vregs (out of range)") >> + >>=20=20=20 >> def run_test(): >> "Run through the tests one by one" >>=20 --=20 Alex Benn=C3=A9e From MAILER-DAEMON Mon Jan 11 09:50:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyWd-0001OL-GK for mharc-qemu-arm@gnu.org; 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([2804:7f0:8284:874d:20e9:a3d4:1db5:c30a]) by smtp.gmail.com with ESMTPSA id i129sm8265616qkd.114.2021.01.11.06.50.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 06:50:23 -0800 (PST) Subject: Re: [PATCH v1 10/20] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, Peter Maydell , "open list:ARM TCG CPUs" References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-11-alex.bennee@linaro.org> <9ee1443e-821d-9cec-c29a-6111385937ad@linaro.org> <87zh1fo7yd.fsf@linaro.org> From: Luis Machado Message-ID: <50da05ee-f7fb-1a18-391d-a707b5df2dba@linaro.org> Date: Mon, 11 Jan 2021 11:50:20 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <87zh1fo7yd.fsf@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=luis.machado@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 14:50:30 -0000 Hi, On 1/11/21 11:36 AM, Alex Bennée wrote: > > Luis Machado writes: > >> For the record, the layout looks OK to me. > > So a Reviewed-by? > Yes. >> Just a reminder that GDB will soon support bfloat16 types. A patch may >> be pushed this month. > > Will we be able to probe for the support - or will an older GDB silently > accept and drop any bfloat16 fields? > No probing unfortunately. I think GDB wouldn't handle it nicely. Older GDB's not supporting bfloat16 may throw an internal error when they see an unknown type. That may need to be corrected to make it more robust. >> >> On 1/8/21 7:42 PM, Alex Bennée wrote: >>> While GDB can work with any XML description given to it there is >>> special handling for SVE registers on the GDB side which makes the >>> users life a little better. The changes aren't that major and all the >>> registers save the $vg reported the same. All that changes is: >>> >>> - report org.gnu.gdb.aarch64.sve >>> - use gdb nomenclature for names and types >>> - minor re-ordering of the types to match reference >>> - re-enable ieee_half (as we know gdb supports it now) >>> - $vg is now a 64 bit int >>> - check $vN and $zN aliasing in test >>> >>> Signed-off-by: Alex Bennée >>> Cc: Luis Machado >>> Message-Id: <20201218112707.28348-10-alex.bennee@linaro.org> >>> Signed-off-by: Alex Bennée >>> --- >>> target/arm/gdbstub.c | 75 ++++++++------------- >>> target/arm/helper.c | 2 +- >>> tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +++ >>> 3 files changed, 41 insertions(+), 47 deletions(-) >>> >>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >>> index 866595b4f1..a8fff2a3d0 100644 >>> --- a/target/arm/gdbstub.c >>> +++ b/target/arm/gdbstub.c >>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { >>> { "uint128", 128, 'q', 'u' }, >>> { "int128", 128, 'q', 's' }, >>> /* 64 bit */ >>> + { "ieee_double", 64, 'd', 'f' }, >>> { "uint64", 64, 'd', 'u' }, >>> { "int64", 64, 'd', 's' }, >>> - { "ieee_double", 64, 'd', 'f' }, >>> /* 32 bit */ >>> + { "ieee_single", 32, 's', 'f' }, >>> { "uint32", 32, 's', 'u' }, >>> { "int32", 32, 's', 's' }, >>> - { "ieee_single", 32, 's', 'f' }, >>> /* 16 bit */ >>> + { "ieee_half", 16, 'h', 'f' }, >>> { "uint16", 16, 'h', 'u' }, >>> { "int16", 16, 'h', 's' }, >>> - /* >>> - * TODO: currently there is no reliable way of telling >>> - * if the remote gdb actually understands ieee_half so >>> - * we don't expose it in the target description for now. >>> - * { "ieee_half", 16, 'h', 'f' }, >>> - */ >>> /* bytes */ >>> { "uint8", 8, 'b', 'u' }, >>> { "int8", 8, 'b', 's' }, >>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> GString *s = g_string_new(NULL); >>> DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; >>> g_autoptr(GString) ts = g_string_new(""); >>> - int i, bits, reg_width = (cpu->sve_max_vq * 128); >>> + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); >>> info->num = 0; >>> g_string_printf(s, ""); >>> g_string_append_printf(s, ""); >>> - g_string_append_printf(s, ""); >>> + g_string_append_printf(s, ""); >>> >>> /* First define types and totals in a whole VL */ >>> for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> int count = reg_width / vec_lanes[i].size; >>> - g_string_printf(ts, "vq%d%c%c", count, >>> - vec_lanes[i].sz, vec_lanes[i].suffix); >>> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); >>> g_string_append_printf(s, >>> "", >>> ts->str, vec_lanes[i].gdb_type, count); >>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> * signed and potentially float versions of each size from 128 to >>> * 8 bits. >>> */ >>> - for (bits = 128; bits >= 8; bits /= 2) { >>> - int count = reg_width / bits; >>> - g_string_append_printf(s, "", count); >>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> - if (vec_lanes[i].size == bits) { >>> - g_string_append_printf(s, "", >>> - vec_lanes[i].suffix, >>> - count, >>> - vec_lanes[i].sz, vec_lanes[i].suffix); >>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >>> + g_string_append_printf(s, "", suf[i]); >>> + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { >>> + if (vec_lanes[j].size == bits) { >>> + g_string_append_printf(s, "", >>> + vec_lanes[j].suffix, >>> + vec_lanes[j].sz, vec_lanes[j].suffix); >>> } >>> } >>> g_string_append(s, ""); >>> } >>> /* And now the final union of unions */ >>> - g_string_append(s, ""); >>> - for (bits = 128; bits >= 8; bits /= 2) { >>> - int count = reg_width / bits; >>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> - if (vec_lanes[i].size == bits) { >>> - g_string_append_printf(s, "", >>> - vec_lanes[i].sz, count); >>> - break; >>> - } >>> - } >>> + g_string_append(s, ""); >>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >>> + g_string_append_printf(s, "", >>> + suf[i], suf[i]); >>> } >>> g_string_append(s, ""); >>> >>> + /* Finally the sve prefix type */ >>> + g_string_append_printf(s, >>> + "", >>> + reg_width / 8); >>> + >>> /* Then define each register in parts for each vq */ >>> for (i = 0; i < 32; i++) { >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vq\"/>", >>> + " regnum=\"%d\" type=\"svev\"/>", >>> i, reg_width, base_reg++); >>> info->num++; >>> } >>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> " regnum=\"%d\" group=\"float\"" >>> " type=\"int\"/>", base_reg++); >>> info->num += 2; >>> - /* >>> - * Predicate registers aren't so big they are worth splitting up >>> - * but we do need to define a type to hold the array of quad >>> - * references. >>> - */ >>> - g_string_append_printf(s, >>> - "", >>> - cpu->sve_max_vq); >>> + >>> for (i = 0; i < 16; i++) { >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vqp\"/>", >>> + " regnum=\"%d\" type=\"svep\"/>", >>> i, cpu->sve_max_vq * 16, base_reg++); >>> info->num++; >>> } >>> g_string_append_printf(s, >>> ">> " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vqp\"/>", >>> + " type=\"svep\"/>", >>> cpu->sve_max_vq * 16, base_reg++); >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"uint32\"/>", >>> + " regnum=\"%d\" type=\"int\"/>", >>> base_reg++); >>> info->num += 2; >>> g_string_append_printf(s, ""); >>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>> index d077dd9ef5..d434044f07 100644 >>> --- a/target/arm/helper.c >>> +++ b/target/arm/helper.c >>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) >>> * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. >>> */ >>> int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >>> - return gdb_get_reg32(buf, vq * 2); >>> + return gdb_get_reg64(buf, vq * 2); >>> } >>> default: >>> /* gdbstub asked for something out our range */ >>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> index 972cf73c31..b9ef169c1a 100644 >>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >>> except gdb.error: >>> report(False, "checking zregs (out of range)") >>> >>> + # Check the aliased V registers are set and GDB has correctly >>> + # created them for us having recognised and handled SVE. >>> + try: >>> + for i in range(0, 16): >>> + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) >>> + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) >>> + report(int(val_z) == int(val_v), >>> + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) >>> + except gdb.error: >>> + report(False, "checking vregs (out of range)") >>> + >>> >>> def run_test(): >>> "Run through the tests one by one" >>> > > From MAILER-DAEMON Mon Jan 11 10:00:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyfs-00088n-KQ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:00:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyfq-00087B-OQ; Mon, 11 Jan 2021 10:00:02 -0500 Received: from mail.mutex.one ([62.77.152.124]:37726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyfo-00012w-UF; Mon, 11 Jan 2021 10:00:02 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id B9A74BF4048F; Mon, 11 Jan 2021 16:59:56 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 31n7mnM33THg; Mon, 11 Jan 2021 16:59:56 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id EE8D5BF4010A; Mon, 11 Jan 2021 16:59:55 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1610377196; bh=YdTUoUk+skkqNAaKlUTiQZsyezzqhs0DzOvszAagqMQ=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=UqNcLOAvJ/IxbvZxM2D8iAabYEQPDAMF5R+fPBVVucPDK5gAdv4zPMHAeZi8n/i2W TSbHxIgBOjEYlQXByHN8k4JUh0Zm6mCqYP+IB0ksVW5DK9fM+nOivFkH5EcwEvxcpr NJ7uysxeauGGiEVxmYRiominuJNFFBJa9kh4y8z0= From: Marian Posteuca To: Igor Mammedov Cc: Peter Maydell , Eduardo Habkost , Sergio Lopez , "Michael S. Tsirkin" , Ben Warren , Richard Henderson , qemu-devel@nongnu.org, Dongjiu Geng , Shannon Zhao , Xiang Zheng , qemu-arm@nongnu.org, Paolo Bonzini , Xiao Guangrong Subject: Re: [PATCH v3] acpi: Permit OEM ID and OEM table ID fields to be changed In-Reply-To: <20210106182430.6bf1823a@redhat.com> References: <20201230221302.26800-1-posteuca@mutex.one> <20210106182430.6bf1823a@redhat.com> Date: Mon, 11 Jan 2021 16:59:54 +0200 Message-ID: <87bldvldsl.fsf@mutex.one> MIME-Version: 1.0 Content-Type: text/plain Received-SPF: pass client-ip=62.77.152.124; envelope-from=posteuca@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:00:03 -0000 Igor Mammedov writes: > overall looks good. > Please add a test case for it, see > tests/qtest/bios-tables-test.c for description how to do it > an/or at > "[PATCH v3 08/12] tests/acpi: allow updates for expected data files" > and follow up patches on the list. When you say add a test case, do you mean only updating the binary files in tests/data/acpi/{microvm,pc,q35,virt} according to the steps at the start of the file bios-tables-test.c? Or do you also mean an actual test case to be added in bios-tables-test.c? Also the step 6 described in bios-tables-test.c mentions that the diff of the ACPI table must be added to the commit log, but my change touches all the tables for all architectures so that would mean that I would have to create a huge commit log. How should I approach this? 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id p24sm45023edr.65.2021.01.11.07.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Subject: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Date: Mon, 11 Jan 2021 16:01:09 +0100 Message-Id: <20210111150114.1415930-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:23 -0000 Attempt to fix the warning reported by Miroslav using GCC 10:=0D https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html=0D =0D Philippe Mathieu-Daud=C3=A9 (5):=0D tcg/arm: Hoist common argument loads in tcg_out_op()=0D tcg/ppc: Hoist common argument loads in tcg_out_op()=0D tcg/s390: Hoist common argument loads in tcg_out_op()=0D tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements=0D tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements=0D =0D tcg/tcg.c | 19 ++-=0D tcg/aarch64/tcg-target.c.inc | 3 +-=0D tcg/arm/tcg-target.c.inc | 173 ++++++++++----------=0D tcg/i386/tcg-target.c.inc | 6 +-=0D tcg/mips/tcg-target.c.inc | 3 +-=0D tcg/ppc/tcg-target.c.inc | 297 +++++++++++++++++------------------=0D tcg/riscv/tcg-target.c.inc | 3 +-=0D tcg/s390/tcg-target.c.inc | 252 ++++++++++++++---------------=0D tcg/tci/tcg-target.c.inc | 5 +-=0D 9 files changed, 372 insertions(+), 389 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Mon Jan 11 10:01:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyhW-0001IY-8x for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:01:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyhN-0001Dq-Uv; Mon, 11 Jan 2021 10:01:39 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:36354) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyyhJ-0001Si-7s; Mon, 11 Jan 2021 10:01:36 -0500 Received: by mail-ej1-x629.google.com with SMTP id lt17so59704ejb.3; Mon, 11 Jan 2021 07:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vf/wZ0/y/41t2lXyI9D2kezLuMSTe1BhgghJsOVZPUU=; b=T/O1VpQahTfQSxTND+Epa3K10kGhyPr4JFJWUlRboUKfymWu58/DYV7EsO9JlZR4Wo owyv7FiWnvYpfWVyplreK6uD9on35nlBmcA7V35qJ4OcxY75JR/BQR2pDLUz9osOJOeg AawAGG8HPE66nNBBr1jA48uBiOmMPcFPBhtHM44DUl7q+25q8QxOzI00CDjneqAQaxHC puAEcbvNae1ll8IIiTh5MhXBrc3af84XTQeZMkFis5ZqBgXz3oyhBBCleEluo2TYkAgc hnKqKrD26LnG1q5iMu+Z/JJWTdoBArVvagq0tTNu45DkMB115OPA5pKOPZEbGGBEz0hI tO7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vf/wZ0/y/41t2lXyI9D2kezLuMSTe1BhgghJsOVZPUU=; b=IBLt67gRaeE8raUib2UTEY3GhtUdqESiUsfpneD3uTdqXPP5gksH8ZLxmaWaaNvhGj 3o+kuEF0UsWmZIHFlR9KeZELKqd1i1LJP11RpFlN7rfkq043PaEacDUiqaNLwHpQMXEh Xp5EtFHzPFuqq9exZ1Kayy4u7pv3Nq7NzjSfP+MeLTaY9M0J8GFwCBPwA+msTj9CwBko 14WWbuKpjGYMeNjZldD7A7xHv9EvA392GEPBJT8m3/b6kaOFDbZdin5Dtej47ITWldBE T+GAcKF2h4JktLih/RojIJE1n3U83VFDvhaQLpwg2FTMT+FHMEQV8l/u3sUpBUr5SpfF qiSQ== X-Gm-Message-State: AOAM530KT2/XyWsCkECQbezh6MJxQXtvm6T0sCx5QN935pfYTjt3bxlJ PZLtAlb6u1Tw72oZ+xrEvIb52dXz+68= X-Google-Smtp-Source: ABdhPJxBaleYdSx2Ns1d+A/mXqWtcAFzmwdZEzz+xPUdu3b8aObS789d/hP+MtNjQh1ipvWP3gTgVA== X-Received: by 2002:a17:906:4756:: with SMTP id j22mr11543878ejs.353.1610377290055; Mon, 11 Jan 2021 07:01:30 -0800 (PST) Received: from x1w.redhat.com (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id mc25sm7102202ejb.58.2021.01.11.07.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Subject: [PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op() Date: Mon, 11 Jan 2021 16:01:11 +0100 Message-Id: <20210111150114.1415930-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:43 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/ppc/tcg-target.c.inc | 294 ++++++++++++++++++--------------------- 1 file changed, 138 insertions(+), 156 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 19a4a12f155..d37b519d693 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2357,15 +2357,23 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCLR | BO_ALWAYS); } -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; - int c; + int c, c1, c2; + + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c1 = const_args[1]; + c2 = const_args[2]; switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, a0); tcg_out_b(s, 0, tcg_code_gen_epilogue); break; case INDEX_op_goto_tb: @@ -2376,24 +2384,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, if ((uintptr_t)s->code_ptr & 7) { tcg_out32(s, NOP); } - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); } else { - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); tcg_out32(s, B); - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); break; } } else { /* Indirect jump. */ tcg_debug_assert(s->tb_jmp_insn_offset == NULL); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, - (intptr_t)(s->tb_jmp_insn_offset + args[0])); + (intptr_t)(s->tb_jmp_insn_offset + a0)); } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, @@ -2401,16 +2409,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_goto_ptr: - tcg_out32(s, MTSPR | RS(args[0]) | CTR); + tcg_out32(s, MTSPR | RS(a0) | CTR); if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); break; case INDEX_op_br: { - TCGLabel *l = arg_label(args[0]); + TCGLabel *l = arg_label(a0); uint32_t insn = B; if (l->has_value) { @@ -2424,50 +2432,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); break; case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); - tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); + tcg_out32(s, EXTSB | RS(a0) | RA(a0)); break; case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i64: - tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHZ, LHZX, a0, a1, a2); break; case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i64: - tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHA, LHAX, a0, a1, a2); break; case INDEX_op_ld_i32: case INDEX_op_ld32u_i64: - tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWZ, LWZX, a0, a1, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWA, LWAX, a0, a1, a2); break; case INDEX_op_ld_i64: - tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LD, LDX, a0, a1, a2); break; case INDEX_op_st8_i32: case INDEX_op_st8_i64: - tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STB, STBX, a0, a1, a2); break; case INDEX_op_st16_i32: case INDEX_op_st16_i64: - tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STH, STHX, a0, a1, a2); break; case INDEX_op_st_i32: case INDEX_op_st32_i64: - tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STW, STWX, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STD, STDX, a0, a1, a2); break; case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { do_addi_32: tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); } else { @@ -2475,14 +2482,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { - if (const_args[2]) { + if (c1) { + if (c2) { tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); } else { tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); } - } else if (const_args[2]) { + } else if (c2) { a2 = -a2; goto do_addi_32; } else { @@ -2491,16 +2497,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_andi32(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_andi64(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(a1, a0, a2)); @@ -2508,8 +2512,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_or_i64: case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_ori32(s, a0, a1, a2); } else { tcg_out32(s, OR | SAB(a1, a0, a2)); @@ -2517,83 +2520,75 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_xor_i64: case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_xori32(s, a0, a1, a2); } else { tcg_out32(s, XOR | SAB(a1, a0, a2)); } break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_andi32(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_andi64(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_orc_i32: - if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); + if (c2) { + tcg_out_ori32(s, a0, a1, ~a2); break; } /* FALLTHRU */ case INDEX_op_orc_i64: - tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + tcg_out32(s, ORC | SAB(a1, a0, a2)); break; case INDEX_op_eqv_i32: - if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); + if (c2) { + tcg_out_xori32(s, a0, a1, ~a2); break; } /* FALLTHRU */ case INDEX_op_eqv_i64: - tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + tcg_out32(s, EQV | SAB(a1, a0, a2)); break; case INDEX_op_nand_i32: case INDEX_op_nand_i64: - tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + tcg_out32(s, NAND | SAB(a1, a0, a2)); break; case INDEX_op_nor_i32: case INDEX_op_nor_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + tcg_out32(s, NOR | SAB(a1, a0, a2)); break; case INDEX_op_clz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, a0, a1, a2, c2); break; case INDEX_op_ctz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, a0, a1, a2, c2); break; case INDEX_op_ctpop_i32: - tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPW | SAB(a1, a0, 0)); break; case INDEX_op_clz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, a0, a1, a2, c2); break; case INDEX_op_ctz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, a0, a1, a2, c2); break; case INDEX_op_ctpop_i64: - tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPD | SAB(a1, a0, 0)); break; case INDEX_op_mul_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { tcg_out32(s, MULLW | TAB(a0, a1, a2)); @@ -2601,62 +2596,58 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_div_i32: - tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVW | TAB(a0, a1, a2)); break; case INDEX_op_divu_i32: - tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVWU | TAB(a0, a1, a2)); break; case INDEX_op_shl_i32: - if (const_args[2]) { + if (c2) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli32(s, args[0], args[1], args[2] & 31); + tcg_out_shli32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLW | SAB(a1, a0, a2)); } break; case INDEX_op_shr_i32: - if (const_args[2]) { + if (c2) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri32(s, args[0], args[1], args[2] & 31); + tcg_out_shri32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRW | SAB(a1, a0, a2)); } break; case INDEX_op_sar_i32: - if (const_args[2]) { + if (c2) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31)); + tcg_out32(s, SRAWI | RS(a1) | RA(a0) | SH(a2 & 31)); } else { - tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAW | SAB(a1, a0, a2)); } break; case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); + if (c2) { + tcg_out_rlw(s, RLWINM, a0, a1, a2, 0, 31); } else { - tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) - | MB(0) | ME(31)); + tcg_out32(s, RLWNM | SAB(a1, a0, a2) | MB(0) | ME(31)); } break; case INDEX_op_rotr_i32: - if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); + if (c2) { + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 0, 31); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); - tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) - | MB(0) | ME(31)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 32)); + tcg_out32(s, RLWNM | SAB(a1, a0, TCG_REG_R0) | MB(0) | ME(31)); } break; case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], - arg_label(args[3]), TCG_TYPE_I32); + tcg_out_brcond(s, a2, a0, a1, c1, arg_label(args[3]), TCG_TYPE_I32); break; case INDEX_op_brcond_i64: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], - arg_label(args[3]), TCG_TYPE_I64); + tcg_out_brcond(s, a2, a0, a1, c1, arg_label(args[3]), TCG_TYPE_I64); break; case INDEX_op_brcond2_i32: tcg_out_brcond2(s, args, const_args); @@ -2664,17 +2655,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_neg_i32: case INDEX_op_neg_i64: - tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); + tcg_out32(s, NEG | RT(a0) | RA(a1)); break; case INDEX_op_not_i32: case INDEX_op_not_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); + tcg_out32(s, NOR | SAB(a1, a0, a1)); break; case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { do_addi_64: tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); } else { @@ -2682,14 +2672,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { - if (const_args[2]) { + if (c1) { + if (c2) { tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); } else { tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); } - } else if (const_args[2]) { + } else if (c2) { a2 = -a2; goto do_addi_64; } else { @@ -2698,58 +2687,57 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: - if (const_args[2]) { + if (c2) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli64(s, args[0], args[1], args[2] & 63); + tcg_out_shli64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLD | SAB(a1, a0, a2)); } break; case INDEX_op_shr_i64: - if (const_args[2]) { + if (c2) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri64(s, args[0], args[1], args[2] & 63); + tcg_out_shri64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRD | SAB(a1, a0, a2)); } break; case INDEX_op_sar_i64: - if (const_args[2]) { - int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); - tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); + if (c2) { + int sh = SH(a2 & 0x1f) | (((a2 >> 5) & 1) << 1); + tcg_out32(s, SRADI | RA(a0) | RS(a1) | sh); } else { - tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAD | SAB(a1, a0, a2)); } break; case INDEX_op_rotl_i64: - if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); + if (c2) { + tcg_out_rld(s, RLDICL, a0, a1, a2, 0); } else { - tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); + tcg_out32(s, RLDCL | SAB(a1, a0, a2) | MB64(0)); } break; case INDEX_op_rotr_i64: - if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); + if (c2) { + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 0); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); - tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 64)); + tcg_out32(s, RLDCL | SAB(a1, a0, TCG_REG_R0) | MB64(0)); } break; case INDEX_op_mul_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { tcg_out32(s, MULLD | TAB(a0, a1, a2)); } break; case INDEX_op_div_i64: - tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVD | TAB(a0, a1, a2)); break; case INDEX_op_divu_i64: - tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVDU | TAB(a0, a1, a2)); break; case INDEX_op_qemu_ld_i32: @@ -2778,19 +2766,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, c = EXTSW; goto gen_ext; gen_ext: - tcg_out32(s, c | RS(args[1]) | RA(args[0])); + tcg_out32(s, c | RS(a1) | RA(a0)); break; case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); + tcg_out_ext32u(s, a0, a1); break; case INDEX_op_setcond_i32: - tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, + c2); break; case INDEX_op_setcond_i64: - tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, + c2); break; case INDEX_op_setcond2_i32: tcg_out_setcond2(s, args, const_args); @@ -2798,7 +2786,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: - a0 = args[0], a1 = args[1]; /* a1 = abcd */ if (a0 != a1) { /* a0 = (a1 r<< 24) & 0xff # 000c */ @@ -2818,10 +2805,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: /* Stolen from gcc's builtin_bswap32 */ - a1 = args[1]; - a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; + a0 = a0 == a1 ? TCG_REG_R0 : a0; - /* a1 = args[1] # abcd */ + /* a1 = a1 # abcd */ /* a0 = rotate_left (a1, 8) # bcda */ tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ @@ -2830,12 +2816,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); if (a0 == TCG_REG_R0) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + tcg_out_mov(s, TCG_TYPE_REG, a0, a0); } break; case INDEX_op_bswap64_i64: - a0 = args[0], a1 = args[1], a2 = TCG_REG_R0; + a2 = TCG_REG_R0; if (a0 == a1) { a0 = TCG_REG_R0; a2 = a1; @@ -2862,44 +2848,42 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23); if (a0 == 0) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + tcg_out_mov(s, TCG_TYPE_REG, a0, a0); } break; case INDEX_op_deposit_i32: - if (const_args[2]) { + if (c2) { uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi32(s, args[0], args[0], ~mask); + tcg_out_andi32(s, a0, a0, ~mask); } else { - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + tcg_out_rlw(s, RLWIMI, a0, a2, args[3], 32 - args[3] - args[4], 31 - args[3]); } break; case INDEX_op_deposit_i64: - if (const_args[2]) { + if (c2) { uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi64(s, args[0], args[0], ~mask); + tcg_out_andi64(s, a0, a0, ~mask); } else { - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + tcg_out_rld(s, RLDIMI, a0, a2, args[3], 64 - args[3] - args[4]); } break; case INDEX_op_extract_i32: - tcg_out_rlw(s, RLWINM, args[0], args[1], - 32 - args[2], 32 - args[3], 31); + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 32 - args[3], 31); break; case INDEX_op_extract_i64: - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 64 - args[3]); break; case INDEX_op_movcond_i32: - tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], - args[3], args[4], const_args[2]); + tcg_out_movcond(s, TCG_TYPE_I32, args[5], a0, a1, a2, + args[3], args[4], c2); break; case INDEX_op_movcond_i64: - tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], - args[3], args[4], const_args[2]); + tcg_out_movcond(s, TCG_TYPE_I64, args[5], a0, a1, a2, + args[3], args[4], c2); break; #if TCG_TARGET_REG_BITS == 64 @@ -2910,14 +2894,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, /* Note that the CA bit is defined based on the word size of the environment. So in 64-bit mode it's always carry-out of bit 63. The fallback code using deposit works just as well for 32-bit. */ - a0 = args[0], a1 = args[1]; if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { a0 = TCG_REG_R0; } if (const_args[4]) { - tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); + tcg_out32(s, ADDIC | TAI(a0, a2, args[4])); } else { - tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); + tcg_out32(s, ADDC | TAB(a0, a2, args[4])); } if (const_args[5]) { tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); @@ -2925,7 +2908,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); } if (a0 != args[0]) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + tcg_out_mov(s, TCG_TYPE_REG, a0, a0); } break; @@ -2934,14 +2917,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #else case INDEX_op_sub2_i32: #endif - a0 = args[0], a1 = args[1]; if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { a0 = TCG_REG_R0; } - if (const_args[2]) { - tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); + if (c2) { + tcg_out32(s, SUBFIC | TAI(a0, args[4], a2)); } else { - tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); + tcg_out32(s, SUBFC | TAB(a0, args[4], a2)); } if (const_args[3]) { tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); @@ -2949,25 +2931,25 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); } if (a0 != args[0]) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + tcg_out_mov(s, TCG_TYPE_REG, a0, a0); } break; case INDEX_op_muluh_i32: - tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHWU | TAB(a0, a1, a2)); break; case INDEX_op_mulsh_i32: - tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHW | TAB(a0, a1, a2)); break; case INDEX_op_muluh_i64: - tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHDU | TAB(a0, a1, a2)); break; case INDEX_op_mulsh_i64: - tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHD | TAB(a0, a1, a2)); break; case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:01:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyhX-0001Kw-4o for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:01:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyhG-0001Da-JP; Mon, 11 Jan 2021 10:01:37 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:35853) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyyhC-0001RU-Vx; Mon, 11 Jan 2021 10:01:29 -0500 Received: by mail-ed1-x531.google.com with SMTP id b2so47014edm.3; Mon, 11 Jan 2021 07:01:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7h+ZogQhx4K7jgIahkOF5Dqk41tHkgsSVlTN0LVAfCk=; b=dP4/4q4XQWeA6wBuzQkSzM8QWT1yNWctBl4v3qpL9diGRWgKWVySO3+0AwWetA7z7q WJb5CWk97B+VcDrbdXBatONWkudewoH040b9og40B1GpKmJStkNLH0uuFVgQcL/qopT7 dCgpJUbOnmUByhU+kvGzWAntK6PU1Ag2Zr4PTfEAzICRkxSfUmISopPo+xKvfm2BZH+K 8eE+lZK2EXN3JETu5+5e0j30mWYwVrv+XkuWVZNDqgnMaaoPxFspsOJqtRZl3R4+rtTQ MMPhZMK9p+1+zHNmXY5VebVyTnixI2L5a452D3Q7cXXKZUJa6dQL4DWxR8rDwvwM8V4s NY3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7h+ZogQhx4K7jgIahkOF5Dqk41tHkgsSVlTN0LVAfCk=; b=a9h458TGwuS51e622vSKLH4wyALMDS9ijbjk45/v+tnQ7//9Pe6fmQmb9VBn4ZTrOj I2Wbzo6rC1fqwpdEjs2GiAxNjvUfo1NS8ryG0ojXS3Y0IhEcEPIsZ7VsaxDie3pFotCy 5YxDqi1ZXqzjVGwhTkez4v91+vP+QM54gQQzmYE7Y6aVz16bjmUvbQ+Maw7o/Pl56Qit E5WBzOmYHl2tZp4Vs4xezPA3qXWPcOMo6YJYHEJCZHVkQmwpiAdKqprvCzHpqH3KG55i ovjfsEIkcRsusGws3X4S77yDgjG744GjrNesRxWnIMwXuiQdSXX4Xw5BJBfpHjeQmsa7 JVgw== X-Gm-Message-State: AOAM530yGw41a/8+36g6QtDlzKfIDIAs6JyaiikdqN375rloG6NzMhCE tzOly2Im58xJc6yONIrkyBKTAv2Ajbs= X-Google-Smtp-Source: ABdhPJw0uOiojo/r1bm05kVgFe0MoLXFzs4Tx0Yl8HbgBEyJFjgJ0jlUULuplszIh99BQk/9az2MjQ== X-Received: by 2002:aa7:d485:: with SMTP id b5mr13875717edr.214.1610377284077; Mon, 11 Jan 2021 07:01:24 -0800 (PST) Received: from x1w.redhat.com (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id cw7sm5317247ejc.13.2021.01.11.07.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Subject: [PATCH 1/5] tcg/arm: Hoist common argument loads in tcg_out_op() Date: Mon, 11 Jan 2021 16:01:10 +0100 Message-Id: <20210111150114.1415930-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:43 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/arm/tcg-target.c.inc | 173 +++++++++++++++++++-------------------- 1 file changed, 86 insertions(+), 87 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0fd11264544..94cc12a0fc6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1747,15 +1747,24 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) static void tcg_out_epilogue(TCGContext *s); -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2, a3, a4, a5; int c; + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + a3 = args[3]; + a4 = args[4]; + a5 = args[5]; + switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, a0); tcg_out_epilogue(s); break; case INDEX_op_goto_tb: @@ -1765,7 +1774,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGReg base = TCG_REG_PC; tcg_debug_assert(s->tb_jmp_insn_offset == 0); - ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + args[0]); + ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0); dif = tcg_pcrel_diff(s, (void *)ptr) - 8; dil = sextract32(dif, 0, 12); if (dif != dil) { @@ -1778,39 +1787,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi32(s, COND_AL, base, ptr - dil); } tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); } break; case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); + tcg_out_bx(s, COND_AL, a0); break; case INDEX_op_br: - tcg_out_goto_label(s, COND_AL, arg_label(args[0])); + tcg_out_goto_label(s, COND_AL, arg_label(a0)); break; case INDEX_op_ld8u_i32: - tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld8s_i32: - tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16u_i32: - tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16s_i32: - tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld_i32: - tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld32u(s, COND_AL, a0, a1, a2); break; case INDEX_op_st8_i32: - tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st8(s, COND_AL, a0, a1, a2); break; case INDEX_op_st16_i32: - tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st16(s, COND_AL, a0, a1, a2); break; case INDEX_op_st_i32: - tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st32(s, COND_AL, a0, a1, a2); break; case INDEX_op_movcond_i32: @@ -1818,34 +1827,33 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, * so we only need to do "if condition passed, move v1 to dest". */ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, - ARITH_MVN, args[0], 0, args[3], const_args[3]); + a1, a2, const_args[2]); + tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[a5], ARITH_MOV, + ARITH_MVN, a0, 0, a3, const_args[3]); break; case INDEX_op_add_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, - args[0], args[1], args[2], const_args[2]); + a0, a1, a2, const_args[2]); break; case INDEX_op_sub_i32: if (const_args[1]) { if (const_args[2]) { - tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + tcg_out_movi32(s, COND_AL, a0, a1 - a2); } else { - tcg_out_dat_rI(s, COND_AL, ARITH_RSB, - args[0], args[2], args[1], 1); + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, a0, a2, a1, 1); } } else { tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + a0, a1, a2, const_args[2]); } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, - args[0], args[1], args[2], const_args[2]); + a0, a1, a2, const_args[2]); break; case INDEX_op_andc_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); + a0, a1, a2, const_args[2]); break; case INDEX_op_or_i32: c = ARITH_ORR; @@ -1854,11 +1862,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, c = ARITH_EOR; /* Fall through. */ gen_arith: - tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rI(s, COND_AL, c, a0, a1, a2, const_args[2]); break; case INDEX_op_add2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; if (a0 == a3 || (a0 == a5 && !const_args[5])) { a0 = TCG_REG_TMP; } @@ -1866,11 +1872,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0, a2, a4, const_args[4]); tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, a1, a3, a5, const_args[5]); - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_sub2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { a0 = TCG_REG_TMP; } @@ -1894,68 +1898,64 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, a1, a3, a5, const_args[5]); } - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_neg_i32: - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a1, 0); break; case INDEX_op_not_i32: - tcg_out_dat_reg(s, COND_AL, - ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); break; case INDEX_op_mul_i32: - tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_mul32(s, COND_AL, a0, a1, a2); break; case INDEX_op_mulu2_i32: - tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_umull32(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_muls2_i32: - tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_smull32(s, COND_AL, a0, a1, a2, a3); break; - /* XXX: Perhaps args[2] & 0x1f is wrong */ + /* XXX: Perhaps a2 & 0x1f is wrong */ case INDEX_op_shl_i32: c = const_args[2] ? - SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); + SHIFT_IMM_LSL(a2 & 0x1f) : SHIFT_REG_LSL(a2); goto gen_shift32; case INDEX_op_shr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); + c = const_args[2] ? (a2 & 0x1f) ? SHIFT_IMM_LSR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(a2); goto gen_shift32; case INDEX_op_sar_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); + c = const_args[2] ? (a2 & 0x1f) ? SHIFT_IMM_ASR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(a2); goto gen_shift32; case INDEX_op_rotr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); + c = const_args[2] ? (a2 & 0x1f) ? SHIFT_IMM_ROR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(a2); /* Fall through. */ gen_shift32: - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, c); break; case INDEX_op_rotl_i32: if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], - ((0x20 - args[2]) & 0x1f) ? - SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, + ((0x20 - a2) & 0x1f) ? + SHIFT_IMM_ROR((0x20 - a2) & 0x1f) : SHIFT_IMM_LSL(0)); } else { - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, a2, 0x20); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(TCG_REG_TMP)); } break; case INDEX_op_ctz_i32: - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); + tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); a1 = TCG_REG_TMP; goto do_clz; case INDEX_op_clz_i32: - a1 = args[1]; do_clz: - a0 = args[0]; - a2 = args[2]; c = const_args[2]; if (c && a2 == 32) { tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); @@ -1970,28 +1970,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_brcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[0], args[1], const_args[1]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], - arg_label(args[3])); + a0, a1, const_args[1]); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[a2], + arg_label(a3)); break; case INDEX_op_setcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], - ARITH_MOV, args[0], 0, 0); + a1, a2, const_args[2]); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[a3], + ARITH_MOV, a0, 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(a3)], + ARITH_MOV, a0, 0, 0); break; case INDEX_op_brcond2_i32: c = tcg_out_cmp2(s, args, const_args); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(a5)); break; case INDEX_op_setcond2_i32: c = tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, a0, 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], - ARITH_MOV, args[0], 0, 0); + ARITH_MOV, a0, 0, 0); break; case INDEX_op_qemu_ld_i32: @@ -2008,63 +2008,62 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, COND_AL, args[0], args[1]); + tcg_out_bswap16(s, COND_AL, a0, a1); break; case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, COND_AL, args[0], args[1]); + tcg_out_bswap32(s, COND_AL, a0, a1); break; case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, COND_AL, args[0], args[1]); + tcg_out_ext8s(s, COND_AL, a0, a1); break; case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, COND_AL, args[0], args[1]); + tcg_out_ext16s(s, COND_AL, a0, a1); break; case INDEX_op_ext16u_i32: - tcg_out_ext16u(s, COND_AL, args[0], args[1]); + tcg_out_ext16u(s, COND_AL, a0, a1); break; case INDEX_op_deposit_i32: - tcg_out_deposit(s, COND_AL, args[0], args[2], - args[3], args[4], const_args[2]); + tcg_out_deposit(s, COND_AL, a0, a2, a3, a4, const_args[2]); break; case INDEX_op_extract_i32: - tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_extract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_sextract_i32: - tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_sextract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_extract2_i32: /* ??? These optimization vs zero should be generic. */ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ if (const_args[1]) { if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); + tcg_out_movi(s, TCG_TYPE_REG, a0, 0); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a2, SHIFT_IMM_LSL(32 - a3)); } } else if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[1], SHIFT_IMM_LSR(args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a1, SHIFT_IMM_LSR(a3)); } else { /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, - args[1], SHIFT_IMM_LSR(args[3])); + a2, SHIFT_IMM_LSL(32 - a3)); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, TCG_REG_TMP, + a1, SHIFT_IMM_LSR(a3)); } break; case INDEX_op_div_i32: - tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_sdiv(s, COND_AL, a0, a1, a2); break; case INDEX_op_divu_i32: - tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_udiv(s, COND_AL, a0, a1, a2); break; case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:01:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyhX-0001NO-TL for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:01:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyhU-0001GG-5m; Mon, 11 Jan 2021 10:01:45 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:44615) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyyhQ-0001To-AZ; Mon, 11 Jan 2021 10:01:43 -0500 Received: by mail-ej1-x634.google.com with SMTP id w1so25073692ejf.11; Mon, 11 Jan 2021 07:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cmtTLwEGX1dw53y5AJ0KBqy6hzYnmQzAtFAizRBeHUI=; b=fgSU/bDj3BWQqTShdEUk4J8q20Gznt8Qy06beeH0diwfPtADHe6eeIIPoNNiR+E+t1 1iyl9r7DuRMLWHBUQzZZnJpAn8TKzjMQQHN4iLqkKc0gqrKJMjgVse4Fu2RDhQlTE6Kg znqrWSZz26wllprtqJX7udtgxYE3+8gGm0x1ni39kpP2PwiFZ/dIXTedqionrbyT91D6 ua1Tro4uLV//w+lAQiRrZB3OFfIEjfqQ/hAL3r8OnyZ8u2pbUlCBlHvcsTPg4GvZnmlC sWTzP8mYkazJ0SfUVZ450wUv8hRwEjXwyU/AF+aQe8/W5vfsChl/FtbsjFNhnztpxMHR sf1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cmtTLwEGX1dw53y5AJ0KBqy6hzYnmQzAtFAizRBeHUI=; b=j2qjPsHNOSfJch/EkoLMoEWgR9KJJrjyh8hy3LO2NBBFbI+8s5C3fFXfkjJw7GkS3S uNHM6z2OiSJTJsZ30P41EJSKeqEjsBduj+q/eIsxqB0/zxtStg+M9KyM1lnmKOPV1sxW pnLRoIZ2qrd5vAEd6TbSG+/telVE3Y8L9yKSfDQIZCG4c46ZblqMdJ73JOb1Z4BuokA2 jVOi1Y3Jn3taZZGJJnEdY+PBkzEzjD3tx/00J1RmtxrFhCODKaU8Tpa4uf1pyYcQ5ZbJ 7fd+VYasOrBl4mwlKOMf03Vydib25CAUSOI7JdJcXbk2YzO3UoEMDnLOHHN2NYFEEPTd x2lw== X-Gm-Message-State: AOAM533XBPpU5iqw4koS7H2dZTV6Bjflsqcoj3TxQqc6jf09HDN3pK9n C6OovTey8Et9avP4giqaRZXnYkBn1Fs= X-Google-Smtp-Source: ABdhPJxkq/3BfKPT91aIGx8RgaeSQUgn7s2TMl4tsBTyn0IoInnOOQVXQpZp6FDEObfaky062L2g1A== X-Received: by 2002:a17:907:9d0:: with SMTP id bx16mr11714469ejc.426.1610377295803; Mon, 11 Jan 2021 07:01:35 -0800 (PST) Received: from x1w.redhat.com (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id g10sm33212edu.97.2021.01.11.07.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Subject: [PATCH 3/5] tcg/s390: Hoist common argument loads in tcg_out_op() Date: Mon, 11 Jan 2021 16:01:12 +0100 Message-Id: <20210111150114.1415930-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:45 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/s390/tcg-target.c.inc | 252 ++++++++++++++++++-------------------- 1 file changed, 122 insertions(+), 130 deletions(-) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index d7ef0790556..74b2314c78a 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1732,15 +1732,23 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, case glue(glue(INDEX_op_,x),_i64) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { S390Opcode op, op2; TCGArg a0, a1, a2; + int c2, c3, c4; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c2 = const_args[2]; + c3 = const_args[3]; + c4 = const_args[4]; switch (opc) { case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ - a0 = args[0]; if (a0 == 0) { tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); } else { @@ -1750,7 +1758,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_tb: - a0 = args[0]; if (s->tb_jmp_insn_offset) { /* * branch displacement must be aligned for atomic patching; @@ -1784,7 +1791,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_ptr: - a0 = args[0]; if (USE_REG_TB) { tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } @@ -1794,45 +1800,43 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, OP_32_64(ld8u): /* ??? LLC (RXY format) is only present with the extended-immediate facility, whereas LLGC is always present. */ - tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGC, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(ld8s): /* ??? LB is no smaller than LGB, so no point to using it. */ - tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGB, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(ld16u): /* ??? LLH (RXY format) is only present with the extended-immediate facility, whereas LLGH is always present. */ - tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGH, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld16s_i32: - tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_LH, RXY_LHY, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); break; OP_32_64(st8): - tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STC, RXY_STCY, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(st16): - tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STH, RXY_STHY, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_st_i32: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; - if (const_args[2]) { + a2 = (int32_t)a2; + if (c2) { do_addi_32: if (a0 == a1) { if (a2 == (int16_t)a2) { @@ -1852,8 +1856,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; - if (const_args[2]) { + a2 = (int32_t)a2; + if (c2) { a2 = -a2; goto do_addi_32; } else if (a0 == a1) { @@ -1864,8 +1868,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { + a2 = (uint32_t)a2; + if (c2) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_andi(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { @@ -1875,8 +1879,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { + a2 = (uint32_t)a2; + if (c2) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_ori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { @@ -1886,30 +1890,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { + a2 = (uint32_t)a2; + if (c2) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_xori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { - tcg_out_insn(s, RR, XR, args[0], args[2]); + tcg_out_insn(s, RR, XR, a0, a2); } else { tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; case INDEX_op_neg_i32: - tcg_out_insn(s, RR, LCR, args[0], args[1]); + tcg_out_insn(s, RR, LCR, a0, a1); break; case INDEX_op_mul_i32: - if (const_args[2]) { - if ((int32_t)args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MHI, args[0], args[2]); + if (c2) { + if ((int32_t)a2 == (int16_t)a2) { + tcg_out_insn(s, RI, MHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + tcg_out_insn(s, RRE, MSR, a0, a2); } break; @@ -1924,16 +1928,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, op = RS_SLL; op2 = RSY_SLLK; do_shift32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + a2 = (int32_t)a2; if (a0 == a1) { - if (const_args[2]) { + if (c2) { tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); } else { tcg_out_sh32(s, op, a0, a2, 0); } } else { /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ - if (const_args[2]) { + if (c2) { tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); } else { tcg_out_sh64(s, op2, a0, a1, a2, 0); @@ -1951,112 +1955,108 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_rotl_i32: /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); + if (c2) { + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLL, a0, a1, a2, 0); } break; case INDEX_op_rotr_i32: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], - TCG_REG_NONE, (32 - args[2]) & 31); + if (c2) { + tcg_out_sh64(s, RSY_RLL, a0, a1, + TCG_REG_NONE, (32 - a2) & 31); } else { - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_TMP0, 0); } break; case INDEX_op_ext8s_i32: - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16s_i32: - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16u_i32: - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I32, a0, a1); break; OP_32_64(bswap16): /* The TCG bswap definition requires bits 0-47 already be zero. Thus we don't need the G-type insns to implement bswap16_i64. */ - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); + tcg_out_insn(s, RRE, LRVR, a0, a1); + tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); break; OP_32_64(bswap32): - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVR, a0, a1); break; case INDEX_op_add2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); + if (c4) { + tcg_out_insn(s, RIL, ALFI, a0, args[4]); } else { - tcg_out_insn(s, RR, ALR, args[0], args[4]); + tcg_out_insn(s, RR, ALR, a0, args[4]); } - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCR, a1, args[5]); break; case INDEX_op_sub2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); + if (c4) { + tcg_out_insn(s, RIL, SLFI, a0, args[4]); } else { - tcg_out_insn(s, RR, SLR, args[0], args[4]); + tcg_out_insn(s, RR, SLR, a0, args[4]); } - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBR, a1, args[5]); break; case INDEX_op_br: - tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); + tgen_branch(s, S390_CC_ALWAYS, arg_label(a0)); break; case INDEX_op_brcond_i32: - tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I32, a2, a0, a1, c1, arg_label(args[3])); break; case INDEX_op_setcond_i32: - tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, c2); break; case INDEX_op_movcond_i32: - tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I32, args[5], a0, a1, a2, c2, args[3], c3); break; case INDEX_op_qemu_ld_i32: /* ??? Technically we can use a non-extending instruction. */ case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, a0, a1, a2); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, a0, a1, a2); break; case INDEX_op_ld16s_i64: - tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGH, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32u_i64: - tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); break; case INDEX_op_st32_i64: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); break; case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { do_addi_64: if (a0 == a1) { if (a2 == (int16_t)a2) { @@ -2084,8 +2084,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { a2 = -a2; goto do_addi_64; } else if (a0 == a1) { @@ -2096,19 +2095,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); + tgen_andi(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { - tcg_out_insn(s, RRE, NGR, args[0], args[2]); + tcg_out_insn(s, RRE, NGR, a0, a2); } else { tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_ori(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { @@ -2118,8 +2115,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { + if (c2) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_xori(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { @@ -2130,21 +2126,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_neg_i64: - tcg_out_insn(s, RRE, LCGR, args[0], args[1]); + tcg_out_insn(s, RRE, LCGR, a0, a1); break; case INDEX_op_bswap64_i64: - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVGR, a0, a1); break; case INDEX_op_mul_i64: - if (const_args[2]) { - if (args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MGHI, args[0], args[2]); + if (c2) { + if (a2 == (int16_t)a2) { + tcg_out_insn(s, RI, MGHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSGFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + tcg_out_insn(s, RRE, MSGR, a0, a2); } break; @@ -2165,10 +2161,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i64: op = RSY_SLLG; do_shift64: - if (const_args[2]) { - tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); + if (c2) { + tcg_out_sh64(s, op, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, op, args[0], args[1], args[2], 0); + tcg_out_sh64(s, op, a0, a1, a2, 0); } break; case INDEX_op_shr_i64: @@ -2179,87 +2175,83 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, goto do_shift64; case INDEX_op_rotl_i64: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, args[2]); + if (c2) { + tcg_out_sh64(s, RSY_RLLG, a0, a1, + TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLLG, a0, a1, a2, 0); } break; case INDEX_op_rotr_i64: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, (64 - args[2]) & 63); + if (c2) { + tcg_out_sh64(s, RSY_RLLG, a0, a1, + TCG_REG_NONE, (64 - a2) & 63); } else { /* We can use the smaller 32-bit negate because only the low 6 bits are examined for the rotate. */ - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_TMP0, 0); } break; case INDEX_op_ext8s_i64: - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16s_i64: - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: - tgen_ext32s(s, args[0], args[1]); + tgen_ext32s(s, a0, a1); break; case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16u_i64: - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: - tgen_ext32u(s, args[0], args[1]); + tgen_ext32u(s, a0, a1); break; case INDEX_op_add2_i64: - if (const_args[4]) { + if (c4) { if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); + tcg_out_insn(s, RIL, ALGFI, a0, args[4]); } else { - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, SLGFI, a0, -args[4]); } } else { - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); + tcg_out_insn(s, RRE, ALGR, a0, args[4]); } - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCGR, a1, args[5]); break; case INDEX_op_sub2_i64: - if (const_args[4]) { + if (c4) { if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); + tcg_out_insn(s, RIL, SLGFI, a0, args[4]); } else { - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, ALGFI, a0, -args[4]); } } else { - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); + tcg_out_insn(s, RRE, SLGR, a0, args[4]); } - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBGR, a1, args[5]); break; case INDEX_op_brcond_i64: - tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I64, a2, a0, a1, c1, arg_label(args[3])); break; case INDEX_op_setcond_i64: - tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, c2); break; case INDEX_op_movcond_i64: - tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I64, args[5], a0, a1, a2, c2, args[3], c3); break; OP_32_64(deposit): - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { + if (c1) { tgen_deposit(s, a0, a2, args[3], args[4], 1); } else { /* Since we can't support "0Z" as a constraint, we allow a1 in @@ -2277,17 +2269,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; OP_32_64(extract): - tgen_extract(s, args[0], args[1], args[2], args[3]); + tgen_extract(s, a0, a1, a2, args[3]); break; case INDEX_op_clz_i64: - tgen_clz(s, args[0], args[1], args[2], const_args[2]); + tgen_clz(s, a0, a1, a2, c2); break; case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ - if (args[0] & TCG_MO_ST_LD) { + if (a0 & TCG_MO_ST_LD) { tcg_out_insn(s, RR, BCR, s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); } -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:01:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyha-0001Se-0K for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:01:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyhX-0001Ls-DV; Mon, 11 Jan 2021 10:01:47 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:45529) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kyyhU-0001Uv-Ro; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id cc8sm68591edb.17.2021.01.11.07.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt , Miroslav Rezanina Subject: [RFC PATCH 4/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Date: Mon, 11 Jan 2021 16:01:13 +0100 Message-Id: <20210111150114.1415930-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:48 -0000 tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. The Aarch64 target already does this since commit 8d8db193f25 ("tcg-aarch64: Hoist common argument loads in tcg_out_op"), SPARC since commit b357f902bff ("tcg-sparc: Hoist common argument loads in tcg_out_op"). RISCV missed it upon introduction in commit bdf503819ee ("tcg/riscv: Add the out op decoder"), MIPS since commit 22ee3a987d5 ("tcg-mips: Hoist args loads") and i386 since commit 42d5b514928 ("tcg/i386: Hoist common arguments in tcg_out_op"). Provide this information as a hint to the compiler in the function prototype, and update the funtion definitions. This fixes this warning (using GCC 11): tcg/aarch64/tcg-target.c.inc:1855:37: error: argument 3 of type 'const TCGArg[16]' {aka 'const long unsigned int[16]'} with mismatched bound [-Werror=array-parameter=] tcg/aarch64/tcg-target.c.inc:1856:34: error: argument 4 of type 'const int[16]' with mismatched bound [-Werror=array-parameter=] Reported-by: Miroslav Rezanina Signed-off-by: Philippe Mathieu-Daudé --- RFC because such compiler hint is somehow "new" to me. Also I expect this to be superseeded by Richard 'tcg constant' branch mentioned here: https://www.mail-archive.com/qemu-devel@nongnu.org/msg771401.html --- tcg/tcg.c | 5 +++-- tcg/i386/tcg-target.c.inc | 3 ++- tcg/mips/tcg-target.c.inc | 3 ++- tcg/riscv/tcg-target.c.inc | 3 ++- tcg/tci/tcg-target.c.inc | 5 +++-- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 472bf1755bf..97d074d8fab 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -110,8 +110,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args); +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 46e856f4421..d121dca8789 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2215,7 +2215,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) } static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; int c, const_a2, vexop, rexw = 0; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index add157f6c32..b9bb54f0ecc 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1691,7 +1691,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, } static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c60b91ba58f..5bf0d069532 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1238,7 +1238,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0 = args[0]; TCGArg a1 = args[1]; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d5a4d9d37cf..60464524f3d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -553,8 +553,9 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { uint8_t *old_code_ptr = s->code_ptr; -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:01:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyhg-0001gD-8z for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:01:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyhd-0001a3-2S; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id b21sm51043edr.53.2021.01.11.07.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:01:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Subject: [RFC PATCH 5/5] tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements Date: Mon, 11 Jan 2021 16:01:14 +0100 Message-Id: <20210111150114.1415930-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:01:54 -0000 tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 14 ++++++++------ tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/i386/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 97d074d8fab..3a20327f9cb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -120,9 +120,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg); -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args); +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #else static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) @@ -139,9 +140,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, { g_assert_not_reached(); } -static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args) +static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { g_assert_not_reached(); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ab199b143f3..32811976e78 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2276,7 +2276,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const AArch64Insn cmp_insn[16] = { [TCG_COND_EQ] = I3616_CMEQ, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d121dca8789..87bf75735a1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2654,7 +2654,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static int const add_insn[4] = { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d37b519d693..279ec4b743c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3137,7 +3137,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const uint32_t add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:20:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyzn-0001vx-1v for mharc-qemu-arm@gnu.org; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id y17sm7157263ejj.84.2021.01.11.07.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:20:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: [PATCH 0/2] sysemu: Let VMChangeStateHandler take boolean 'running' argument Date: Mon, 11 Jan 2021 16:20:18 +0100 Message-Id: <20210111152020.1422021-1-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:20:37 -0000 Trivial prototype change to clarify the use of the 'running'=0D argument of VMChangeStateHandler.=0D =0D Green CI:=0D https://gitlab.com/philmd/qemu/-/pipelines/239497352=0D =0D Philippe Mathieu-Daud=C3=A9 (2):=0D sysemu/runstate: Let runstate_is_running() return bool=0D sysemu: Let VMChangeStateHandler take boolean 'running' argument=0D =0D include/sysemu/runstate.h | 12 +++++++++---=0D target/arm/kvm_arm.h | 2 +-=0D target/ppc/cpu-qom.h | 2 +-=0D accel/xen/xen-all.c | 2 +-=0D audio/audio.c | 2 +-=0D block/block-backend.c | 2 +-=0D gdbstub.c | 2 +-=0D hw/block/pflash_cfi01.c | 2 +-=0D hw/block/virtio-blk.c | 2 +-=0D hw/display/qxl.c | 2 +-=0D hw/i386/kvm/clock.c | 2 +-=0D hw/i386/kvm/i8254.c | 2 +-=0D hw/i386/kvmvapic.c | 2 +-=0D hw/i386/xen/xen-hvm.c | 2 +-=0D hw/ide/core.c | 2 +-=0D hw/intc/arm_gicv3_its_kvm.c | 2 +-=0D hw/intc/arm_gicv3_kvm.c | 2 +-=0D hw/intc/spapr_xive_kvm.c | 2 +-=0D hw/misc/mac_via.c | 2 +-=0D hw/net/e1000e_core.c | 2 +-=0D hw/nvram/spapr_nvram.c | 2 +-=0D hw/ppc/ppc.c | 2 +-=0D hw/ppc/ppc_booke.c | 2 +-=0D hw/s390x/tod-kvm.c | 2 +-=0D hw/scsi/scsi-bus.c | 2 +-=0D hw/usb/hcd-ehci.c | 2 +-=0D hw/usb/host-libusb.c | 2 +-=0D hw/usb/redirect.c | 2 +-=0D hw/vfio/migration.c | 2 +-=0D hw/virtio/virtio-rng.c | 2 +-=0D hw/virtio/virtio.c | 2 +-=0D net/net.c | 2 +-=0D softmmu/memory.c | 2 +-=0D softmmu/runstate.c | 4 ++--=0D target/arm/kvm.c | 2 +-=0D target/i386/kvm/kvm.c | 2 +-=0D target/i386/sev.c | 2 +-=0D target/i386/whpx/whpx-all.c | 2 +-=0D target/mips/kvm.c | 4 ++--=0D ui/gtk.c | 2 +-=0D ui/spice-core.c | 2 +-=0D 41 files changed, 51 insertions(+), 45 deletions(-)=0D =0D --=20=0D 2.26.2=0D =0D From MAILER-DAEMON Mon Jan 11 10:20:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyyzo-00021k-Sz for mharc-qemu-arm@gnu.org; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id c12sm76932edw.55.2021.01.11.07.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:20:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: [PATCH 1/2] sysemu/runstate: Let runstate_is_running() return bool Date: Mon, 11 Jan 2021 16:20:19 +0100 Message-Id: <20210111152020.1422021-2-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111152020.1422021-1-philmd@redhat.com> References: <20210111152020.1422021-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:20:39 -0000 runstate_check() returns a boolean. runstate_is_running() returns what runstate_check() returns, also a boolean. Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/runstate.h | 2 +- softmmu/runstate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h index e557f470d42..3ab35a039a0 100644 --- a/include/sysemu/runstate.h +++ b/include/sysemu/runstate.h @@ -6,7 +6,7 @@ bool runstate_check(RunState state); void runstate_set(RunState new_state); -int runstate_is_running(void); +bool runstate_is_running(void); bool runstate_needs_reset(void); bool runstate_store(char *str, size_t size); diff --git a/softmmu/runstate.c b/softmmu/runstate.c index 636aab0addb..c7a67147d17 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -217,7 +217,7 @@ void runstate_set(RunState new_state) current_run_state = new_state; } -int runstate_is_running(void) +bool runstate_is_running(void) { return runstate_check(RUN_STATE_RUNNING); } -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:20:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyz01-0002Gp-B2 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:20:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyyzx-0002CY-1c for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:20:49 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:54380) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kyyzr-00046s-LX for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:20:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610378443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2MgTFVQIGAogKeGjtgnMyQWeyj36PU1W60Mle8ZvTl4=; b=L52p+ekpgKAkdaoc9LLei/UCDXdhMeYIU3tj2xOkwHEDGcvvJlnfeijWHguafgZQPolMuY iVIzZvzCiWObUCoJjBNwq6kRpUSVrI+V6ZopqlIiBUmBRGGslV4ieNfK9nHifE/qyikdxh HE33RzFlM2GyVgHf+gcMNyN2ef443ZY= Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-129-beglW1IKPhej_VAw6KQecw-1; Mon, 11 Jan 2021 10:20:41 -0500 X-MC-Unique: beglW1IKPhej_VAw6KQecw-1 Received: by mail-ed1-f72.google.com with SMTP id u18so8388078edy.5 for ; Mon, 11 Jan 2021 07:20:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2MgTFVQIGAogKeGjtgnMyQWeyj36PU1W60Mle8ZvTl4=; b=S7fRgJhANFhEihm7OwoEj6Due5QrvX27tDZ4DHHv2mvzl0BHvTc1F13AovkuB0UiKl zubF6u6k9qPEl4ZIBEDUnZLdF6Od2HaecyxC3rcD4tjdaVlvFRE7/+QBkZaPEoX7QV25 TsCvXHcdw9AL4hM5ExIxyQskAG8a2KM712zzYLXBWEClLS/7ewZNq5mASc37N6ez0yYc nmcvgeoefUkfmEALiZAYZzdmxKtLNTvVewiM4lsUitFQ1wGTmVWbfYgrf7afSQ3/leHU pyaz3jWPr/O8pnePfaQWZJ4K+C6bDqQfD85C2ayww153Z/lhx1NZoZ25OxzWkI7+xriy zMxw== X-Gm-Message-State: AOAM530/otkb+AeBZHOvkeE70Rl6Zkyt4uS+TTCS3NOWy/mY4usrRBYj IcavQX54ti0Qs6vQisFdltqBoB1c5dIuZNHtZWlekEpckmaV3pu1403LNBuKU7i9nKOXxGoCtEL 06PxLaHphW2SA X-Received: by 2002:aa7:cccf:: with SMTP id y15mr14611623edt.112.1610378438959; Mon, 11 Jan 2021 07:20:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJxcMF+UJehYZiO17PyZzy9+j70Zu9ldss/OST7FfZYyo9mNlmtdppkrmgXvwyrPuWC1Fb5iiw== X-Received: by 2002:aa7:cccf:: with SMTP id y15mr14611598edt.112.1610378438650; Mon, 11 Jan 2021 07:20:38 -0800 (PST) Received: from x1w.redhat.com (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id h16sm7097043eji.110.2021.01.11.07.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 07:20:37 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: [PATCH 2/2] sysemu: Let VMChangeStateHandler take boolean 'running' argument Date: Mon, 11 Jan 2021 16:20:20 +0100 Message-Id: <20210111152020.1422021-3-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210111152020.1422021-1-philmd@redhat.com> References: <20210111152020.1422021-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:20:50 -0000 The 'running' argument from VMChangeStateHandler does not require other value than 0 / 1. Make it a plain boolean. Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/runstate.h | 10 ++++++++-- target/arm/kvm_arm.h | 2 +- target/ppc/cpu-qom.h | 2 +- accel/xen/xen-all.c | 2 +- audio/audio.c | 2 +- block/block-backend.c | 2 +- gdbstub.c | 2 +- hw/block/pflash_cfi01.c | 2 +- hw/block/virtio-blk.c | 2 +- hw/display/qxl.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/kvm/i8254.c | 2 +- hw/i386/kvmvapic.c | 2 +- hw/i386/xen/xen-hvm.c | 2 +- hw/ide/core.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_kvm.c | 2 +- hw/intc/spapr_xive_kvm.c | 2 +- hw/misc/mac_via.c | 2 +- hw/net/e1000e_core.c | 2 +- hw/nvram/spapr_nvram.c | 2 +- hw/ppc/ppc.c | 2 +- hw/ppc/ppc_booke.c | 2 +- hw/s390x/tod-kvm.c | 2 +- hw/scsi/scsi-bus.c | 2 +- hw/usb/hcd-ehci.c | 2 +- hw/usb/host-libusb.c | 2 +- hw/usb/redirect.c | 2 +- hw/vfio/migration.c | 2 +- hw/virtio/virtio-rng.c | 2 +- hw/virtio/virtio.c | 2 +- net/net.c | 2 +- softmmu/memory.c | 2 +- softmmu/runstate.c | 2 +- target/arm/kvm.c | 2 +- target/i386/kvm/kvm.c | 2 +- target/i386/sev.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- target/mips/kvm.c | 4 ++-- ui/gtk.c | 2 +- ui/spice-core.c | 2 +- 41 files changed, 49 insertions(+), 43 deletions(-) diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h index 3ab35a039a0..a5356915734 100644 --- a/include/sysemu/runstate.h +++ b/include/sysemu/runstate.h @@ -10,7 +10,7 @@ bool runstate_is_running(void); bool runstate_needs_reset(void); bool runstate_store(char *str, size_t size); -typedef void VMChangeStateHandler(void *opaque, int running, RunState state); +typedef void VMChangeStateHandler(void *opaque, bool running, RunState state); VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, void *opaque); @@ -20,7 +20,13 @@ VMChangeStateEntry *qdev_add_vm_change_state_handler(DeviceState *dev, VMChangeStateHandler *cb, void *opaque); void qemu_del_vm_change_state_handler(VMChangeStateEntry *e); -void vm_state_notify(int running, RunState state); +/** + * vm_state_notify: Notify the state of the VM + * + * @running: whether the VM is running or not. + * @state: the #RunState of the VM. + */ +void vm_state_notify(bool running, RunState state); static inline bool shutdown_caused_by_guest(ShutdownCause cause) { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index eb81b7059eb..68ec970c4f4 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -352,7 +352,7 @@ void kvm_arm_get_virtual_time(CPUState *cs); */ void kvm_arm_put_virtual_time(CPUState *cs); -void kvm_arm_vm_state_change(void *opaque, int running, RunState state); +void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); int kvm_arm_vgic_probe(void); diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 63b9e8632ca..118baf8d41f 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -218,7 +218,7 @@ extern const VMStateDescription vmstate_ppc_timebase; .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ } -void cpu_ppc_clock_vm_state_change(void *opaque, int running, +void cpu_ppc_clock_vm_state_change(void *opaque, bool running, RunState state); #endif diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 878a4089d97..3756aca27be 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -122,7 +122,7 @@ static void xenstore_record_dm_state(struct xs_handle *xs, const char *state) } -static void xen_change_state_handler(void *opaque, int running, +static void xen_change_state_handler(void *opaque, bool running, RunState state) { if (running) { diff --git a/audio/audio.c b/audio/audio.c index b48471bb3f6..f2d56e7e57d 100644 --- a/audio/audio.c +++ b/audio/audio.c @@ -1549,7 +1549,7 @@ static int audio_driver_init(AudioState *s, struct audio_driver *drv, } } -static void audio_vm_change_state_handler (void *opaque, int running, +static void audio_vm_change_state_handler (void *opaque, bool running, RunState state) { AudioState *s = opaque; diff --git a/block/block-backend.c b/block/block-backend.c index ce78d30794a..9175eb237a2 100644 --- a/block/block-backend.c +++ b/block/block-backend.c @@ -163,7 +163,7 @@ static const char *blk_root_get_name(BdrvChild *child) return blk_name(child->opaque); } -static void blk_vm_state_changed(void *opaque, int running, RunState state) +static void blk_vm_state_changed(void *opaque, bool running, RunState state) { Error *local_err = NULL; BlockBackend *blk = opaque; diff --git a/gdbstub.c b/gdbstub.c index d99bc0bf2ea..9f2998f8d03 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2691,7 +2691,7 @@ void gdb_set_stop_cpu(CPUState *cpu) } #ifndef CONFIG_USER_ONLY -static void gdb_vm_state_change(void *opaque, int running, RunState state) +static void gdb_vm_state_change(void *opaque, bool running, RunState state) { CPUState *cpu = gdbserver_state.c_cpu; g_autoptr(GString) buf = g_string_new(NULL); diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index ccf326793db..badcbccf012 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -1014,7 +1014,7 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) loc_pop(&loc); } -static void postload_update_cb(void *opaque, int running, RunState state) +static void postload_update_cb(void *opaque, bool running, RunState state) { PFlashCFI01 *pfl = opaque; diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c index bac2d6fa2b2..5207ef617f0 100644 --- a/hw/block/virtio-blk.c +++ b/hw/block/virtio-blk.c @@ -870,7 +870,7 @@ static void virtio_blk_dma_restart_bh(void *opaque) virtio_blk_process_queued_requests(s, true); } -static void virtio_blk_dma_restart_cb(void *opaque, int running, +static void virtio_blk_dma_restart_cb(void *opaque, bool running, RunState state) { VirtIOBlock *s = opaque; diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 431c1070967..d22e84ba13e 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1992,7 +1992,7 @@ static void qxl_dirty_surfaces(PCIQXLDevice *qxl) } } -static void qxl_vm_change_state_handler(void *opaque, int running, +static void qxl_vm_change_state_handler(void *opaque, bool running, RunState state) { PCIQXLDevice *qxl = opaque; diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 2d8a3663693..51872dd84c0 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -162,7 +162,7 @@ static void do_kvmclock_ctrl(CPUState *cpu, run_on_cpu_data data) } } -static void kvmclock_vm_state_change(void *opaque, int running, +static void kvmclock_vm_state_change(void *opaque, bool running, RunState state) { KVMClockState *s = opaque; diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c index c73254e8866..c558893961b 100644 --- a/hw/i386/kvm/i8254.c +++ b/hw/i386/kvm/i8254.c @@ -239,7 +239,7 @@ static void kvm_pit_irq_control(void *opaque, int n, int enable) kvm_pit_put(pit); } -static void kvm_pit_vm_state_change(void *opaque, int running, +static void kvm_pit_vm_state_change(void *opaque, bool running, RunState state) { KVMPITState *s = opaque; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 2c1898032e4..46315445d22 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -748,7 +748,7 @@ static void do_vapic_enable(CPUState *cs, run_on_cpu_data data) s->state = VAPIC_ACTIVE; } -static void kvmvapic_vm_state_change(void *opaque, int running, +static void kvmvapic_vm_state_change(void *opaque, bool running, RunState state) { MachineState *ms = MACHINE(qdev_get_machine()); diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 68821d90f52..7ce672e5a5c 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -1235,7 +1235,7 @@ static void xen_main_loop_prepare(XenIOState *state) } -static void xen_hvm_change_state_handler(void *opaque, int running, +static void xen_hvm_change_state_handler(void *opaque, bool running, RunState rstate) { XenIOState *state = opaque; diff --git a/hw/ide/core.c b/hw/ide/core.c index b49e4cfbc6c..b5c6e967b2e 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2677,7 +2677,7 @@ static void ide_restart_bh(void *opaque) } } -static void ide_restart_cb(void *opaque, int running, RunState state) +static void ide_restart_cb(void *opaque, bool running, RunState state) { IDEBus *bus = opaque; diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 057cb53f13c..b554d2ede0a 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -71,7 +71,7 @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) * * The tables get flushed to guest RAM whenever the VM gets stopped. */ -static void vm_change_state_handler(void *opaque, int running, +static void vm_change_state_handler(void *opaque, bool running, RunState state) { GICv3ITSState *s = (GICv3ITSState *)opaque; diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index d040a5d1e99..65a4c880a35 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -743,7 +743,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { * * The tables get flushed to guest RAM whenever the VM gets stopped. */ -static void vm_change_state_handler(void *opaque, int running, +static void vm_change_state_handler(void *opaque, bool running, RunState state) { GICv3State *s = (GICv3State *)opaque; diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index acc8c3650c4..c0083311607 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -504,7 +504,7 @@ static int kvmppc_xive_get_queues(SpaprXive *xive, Error **errp) * runs again. If an interrupt was queued while the VM was stopped, * simply generate a trigger. */ -static void kvmppc_xive_change_state_handler(void *opaque, int running, +static void kvmppc_xive_change_state_handler(void *opaque, bool running, RunState state) { SpaprXive *xive = opaque; diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 488d086a17c..ca2f939dd58 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1098,7 +1098,7 @@ static void mac_via_init(Object *obj) TYPE_ADB_BUS, DEVICE(obj), "adb.0"); } -static void postload_update_cb(void *opaque, int running, RunState state) +static void postload_update_cb(void *opaque, bool running, RunState state) { MacVIAState *m = MAC_VIA(opaque); diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 4dcb92d966b..b75f2ab8fc1 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -3298,7 +3298,7 @@ e1000e_autoneg_resume(E1000ECore *core) } static void -e1000e_vm_state_change(void *opaque, int running, RunState state) +e1000e_vm_state_change(void *opaque, bool running, RunState state) { E1000ECore *core = opaque; diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index 9e51bc82ae4..01f77520146 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -217,7 +217,7 @@ static int spapr_nvram_pre_load(void *opaque) return 0; } -static void postload_update_cb(void *opaque, int running, RunState state) +static void postload_update_cb(void *opaque, bool running, RunState state) { SpaprNvram *nvram = opaque; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 5cbbff1f8d0..bf28d6bfc8d 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1059,7 +1059,7 @@ static void timebase_load(PPCTimebase *tb) } } -void cpu_ppc_clock_vm_state_change(void *opaque, int running, +void cpu_ppc_clock_vm_state_change(void *opaque, bool running, RunState state) { PPCTimebase *tb = opaque; diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 652a21b8064..974c0c8a752 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -317,7 +317,7 @@ static void ppc_booke_timer_reset_handle(void *opaque) * action will be taken. To avoid this we always clear the watchdog state when * state changes to running. */ -static void cpu_state_change_handler(void *opaque, int running, RunState state) +static void cpu_state_change_handler(void *opaque, bool running, RunState state) { PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; diff --git a/hw/s390x/tod-kvm.c b/hw/s390x/tod-kvm.c index 6e21d83181d..0b944774861 100644 --- a/hw/s390x/tod-kvm.c +++ b/hw/s390x/tod-kvm.c @@ -78,7 +78,7 @@ static void kvm_s390_tod_set(S390TODState *td, const S390TOD *tod, Error **errp) } } -static void kvm_s390_tod_vm_state_change(void *opaque, int running, +static void kvm_s390_tod_vm_state_change(void *opaque, bool running, RunState state) { S390TODState *td = opaque; diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index c349fb7f2d1..f990d5b3b03 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -181,7 +181,7 @@ void scsi_req_retry(SCSIRequest *req) req->retry = true; } -static void scsi_dma_restart_cb(void *opaque, int running, RunState state) +static void scsi_dma_restart_cb(void *opaque, bool running, RunState state) { SCSIDevice *s = opaque; diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index aca018d8b5f..98d08c325ea 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -2436,7 +2436,7 @@ static int usb_ehci_post_load(void *opaque, int version_id) return 0; } -static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) +static void usb_ehci_vm_state_change(void *opaque, bool running, RunState state) { EHCIState *ehci = opaque; diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c index b950501d100..ecbf3f66f42 100644 --- a/hw/usb/host-libusb.c +++ b/hw/usb/host-libusb.c @@ -1755,7 +1755,7 @@ type_init(usb_host_register_types) static QEMUTimer *usb_auto_timer; static VMChangeStateEntry *usb_vmstate; -static void usb_host_vm_state(void *unused, int running, RunState state) +static void usb_host_vm_state(void *unused, bool running, RunState state) { if (running) { usb_host_auto_check(unused); diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 7e9e3fecbfe..17f06f34179 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1395,7 +1395,7 @@ static void usbredir_chardev_event(void *opaque, QEMUChrEvent event) * init + destroy */ -static void usbredir_vm_state_change(void *priv, int running, RunState state) +static void usbredir_vm_state_change(void *priv, bool running, RunState state) { USBRedirDevice *dev = priv; diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 00daa50ed81..134bdccc4f8 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -727,7 +727,7 @@ static SaveVMHandlers savevm_vfio_handlers = { /* ---------------------------------------------------------------------- */ -static void vfio_vmstate_change(void *opaque, int running, RunState state) +static void vfio_vmstate_change(void *opaque, bool running, RunState state) { VFIODevice *vbasedev = opaque; VFIOMigration *migration = vbasedev->migration; diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c index 76ce9376931..cc8e9f775d8 100644 --- a/hw/virtio/virtio-rng.c +++ b/hw/virtio/virtio-rng.c @@ -133,7 +133,7 @@ static uint64_t get_features(VirtIODevice *vdev, uint64_t f, Error **errp) return f; } -static void virtio_rng_vm_state_change(void *opaque, int running, +static void virtio_rng_vm_state_change(void *opaque, bool running, RunState state) { VirtIORNG *vrng = opaque; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index b308026596f..38dc623c89e 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -3208,7 +3208,7 @@ void virtio_cleanup(VirtIODevice *vdev) qemu_del_vm_change_state_handler(vdev->vmstate); } -static void virtio_vmstate_change(void *opaque, int running, RunState state) +static void virtio_vmstate_change(void *opaque, bool running, RunState state) { VirtIODevice *vdev = opaque; BusState *qbus = qdev_get_parent_bus(DEVICE(vdev)); diff --git a/net/net.c b/net/net.c index e1035f21d18..8a85d1e3f7b 100644 --- a/net/net.c +++ b/net/net.c @@ -1341,7 +1341,7 @@ void qmp_set_link(const char *name, bool up, Error **errp) } } -static void net_vm_change_state_handler(void *opaque, int running, +static void net_vm_change_state_handler(void *opaque, bool running, RunState state) { NetClientState *nc; diff --git a/softmmu/memory.c b/softmmu/memory.c index 333e1ed7b05..ab7f2e5aa07 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -2675,7 +2675,7 @@ static void memory_global_dirty_log_do_stop(void) MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse); } -static void memory_vm_change_state_handler(void *opaque, int running, +static void memory_vm_change_state_handler(void *opaque, bool running, RunState state) { if (running) { diff --git a/softmmu/runstate.c b/softmmu/runstate.c index c7a67147d17..cb07a65925c 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -316,7 +316,7 @@ void qemu_del_vm_change_state_handler(VMChangeStateEntry *e) g_free(e); } -void vm_state_notify(int running, RunState state) +void vm_state_notify(bool running, RunState state) { VMChangeStateEntry *e, *next; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ffe186de8d1..53d6c4a17eb 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -844,7 +844,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) return MEMTXATTRS_UNSPECIFIED; } -void kvm_arm_vm_state_change(void *opaque, int running, RunState state) +void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) { CPUState *cs = opaque; ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6dc1ee052d5..170ad55c09c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -690,7 +690,7 @@ static int kvm_inject_mce_oldstyle(X86CPU *cpu) return 0; } -static void cpu_update_state(void *opaque, int running, RunState state) +static void cpu_update_state(void *opaque, bool running, RunState state) { CPUX86State *env = opaque; diff --git a/target/i386/sev.c b/target/i386/sev.c index 15466068118..e7890f61906 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -670,7 +670,7 @@ sev_launch_finish(SevGuestState *sev) } static void -sev_vm_state_change(void *opaque, int running, RunState state) +sev_vm_state_change(void *opaque, bool running, RunState state) { SevGuestState *sev = opaque; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3b824fc9d7c..850dfe72e75 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1318,7 +1318,7 @@ void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) static Error *whpx_migration_blocker; -static void whpx_cpu_update_state(void *opaque, int running, RunState state) +static void whpx_cpu_update_state(void *opaque, bool running, RunState state) { CPUX86State *env = opaque; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..09945ad2455 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -37,7 +37,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; -static void kvm_mips_update_state(void *opaque, int running, RunState state); +static void kvm_mips_update_state(void *opaque, bool running, RunState state); unsigned long kvm_arch_vcpu_id(CPUState *cs) { @@ -552,7 +552,7 @@ static int kvm_mips_restore_count(CPUState *cs) /* * Handle the VM clock being started or stopped */ -static void kvm_mips_update_state(void *opaque, int running, RunState state) +static void kvm_mips_update_state(void *opaque, bool running, RunState state) { CPUState *cs = opaque; int ret; diff --git a/ui/gtk.c b/ui/gtk.c index a752aa22be0..a5bf8ed8429 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -672,7 +672,7 @@ static const DisplayChangeListenerOps dcl_egl_ops = { /** QEMU Events **/ -static void gd_change_runstate(void *opaque, int running, RunState state) +static void gd_change_runstate(void *opaque, bool running, RunState state) { GtkDisplayState *s = opaque; diff --git a/ui/spice-core.c b/ui/spice-core.c index 5746d0aae7c..22c77c04151 100644 --- a/ui/spice-core.c +++ b/ui/spice-core.c @@ -622,7 +622,7 @@ static int add_channel(void *opaque, const char *name, const char *value, return 0; } -static void vm_change_state_handler(void *opaque, int running, +static void vm_change_state_handler(void *opaque, bool running, RunState state) { if (running) { -- 2.26.2 From MAILER-DAEMON Mon Jan 11 10:30:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyz92-00033h-2E for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:30:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyz90-00030j-8J for qemu-arm@nongnu.org; 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id x17sm85147edq.77.2021.01.11.07.30.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 07:30:02 -0800 (PST) Subject: Re: [PATCH v1 12/20] semihosting: Move ARM semihosting code to shared directories To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , Keith Packard , Laurent Vivier , "open list:ARM TCG CPUs" , Alistair Francis References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-13-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <15248375-2760-8e5c-4468-b952b247ed2d@redhat.com> Date: Mon, 11 Jan 2021 16:30:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210108224256.2321-13-alex.bennee@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:30:10 -0000 On 1/8/21 11:42 PM, Alex Bennée wrote: > From: Keith Packard > > This commit renames two files which provide ARM semihosting support so > that they can be shared by other architectures: > > 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c > 2. linux-user/arm/semihost.c -> linux-user/semihost.c > > The build system was modified use a new config variable, > CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM > softmmu and linux-user default configs. The contents of the source > files has not been changed in this patch. > > Signed-off-by: Keith Packard > Reviewed-by: Alistair Francis > Signed-off-by: Alex Bennée > Message-Id: <20210107170717.2098982-2-keithp@keithp.com> > --- > default-configs/devices/arm-softmmu.mak | 1 + > default-configs/targets/aarch64-linux-user.mak | 1 + > default-configs/targets/aarch64_be-linux-user.mak | 1 + > default-configs/targets/arm-linux-user.mak | 1 + > default-configs/targets/armeb-linux-user.mak | 1 + > target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 > linux-user/{arm => }/semihost.c | 0 > hw/semihosting/Kconfig | 3 +++ > hw/semihosting/meson.build | 3 +++ > linux-user/arm/meson.build | 3 --- > linux-user/meson.build | 1 + > target/arm/meson.build | 2 -- > 12 files changed, 12 insertions(+), 5 deletions(-) > rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) > rename linux-user/{arm => }/semihost.c (100%) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Mon Jan 11 10:32:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyzBZ-0004HD-VE for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:32:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyzBT-0004Fx-Mh for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:32:44 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:33354) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kyzBO-0005s6-R0 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:32:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610379157; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oFhE1fuK2u+lt8651i050zlH4eIqB40KpbdOdnqE+Ks=; b=hiSWa/H5MnnN1q6NkdRh8KknCyia3k2ADek94CY2bkvZkbNv9t6bAG2OXe6An39UgXJXmc jefrr2n5o5guU1Khf9QgaWO6at2O2IDQNAQ4t/XZRCgA49ZrhMBhepF3tgCQug3H/8ppHQ fTzSznoVAbqaIxK+nUm3s8j2BxgBwFo= Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-483-KIUeApbOOlG6roJtiO7XNQ-1; Mon, 11 Jan 2021 10:32:35 -0500 X-MC-Unique: KIUeApbOOlG6roJtiO7XNQ-1 Received: by mail-ej1-f70.google.com with SMTP id h17so37685ejk.21 for ; Mon, 11 Jan 2021 07:32:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:references:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=oFhE1fuK2u+lt8651i050zlH4eIqB40KpbdOdnqE+Ks=; b=uKTsQcW/OCvYvTxXm+kGByERu6F5ruENAuuw2lvaOaHxRrv8cBND4iWcCy6hWyREgK Ryhl96ZxCsvn4h5I/B4Sa2OD3zw3TLnyMUmnLtBbOxaMIG2hx7+6906ZU+jCAuwZeZe9 fGfjotcBQXvj4fk7AkQ75h17qkLz9wWtSbB9y/cpHQ3sHZGYvkYBOmFG21KbD4cjmrb5 aMx3qvrW7oK/DBUgIGoOTAGps6WLT8odZTdJxDmyStEgUlZNm15A9evDn5uSspxg8cNF F6G27roQHNNzZWA68hpeIVxlx8pQRngwoTAG61PHGz8dGTP7yabZj3Fs6lJb0Gs+hWWm HalQ== X-Gm-Message-State: AOAM5326YWbrPnYYVAJB5gkXydUpXGts02AJ3kjr6rG32D/6Jew8Ef7m nRilrVkDB3E14mYKHvhsdot0AmDgrfnQ6H616U6eZoNImJAp1zt9FqPn0tXDLrmmyPgz8PjXiik zAwN+hLLsu43M X-Received: by 2002:a17:907:271c:: with SMTP id w28mr42964ejk.140.1610379154515; Mon, 11 Jan 2021 07:32:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJzY2Fxok49+7rEcrn+mlf7bsO1dhX3X4Fr0GxY2lR97nSdK2NzTqVi65g64QjbNmDc8TIrDFA== X-Received: by 2002:a17:907:271c:: with SMTP id w28mr42948ejk.140.1610379154281; Mon, 11 Jan 2021 07:32:34 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id r21sm73326eds.91.2021.01.11.07.32.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 07:32:33 -0800 (PST) Subject: Re: [PATCH v1 12/20] semihosting: Move ARM semihosting code to shared directories From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , Keith Packard , Laurent Vivier , "open list:ARM TCG CPUs" , Alistair Francis References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-13-alex.bennee@linaro.org> <15248375-2760-8e5c-4468-b952b247ed2d@redhat.com> Message-ID: <5f7091fe-a7ff-d2c6-528a-728b97434d3a@redhat.com> Date: Mon, 11 Jan 2021 16:32:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <15248375-2760-8e5c-4468-b952b247ed2d@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:32:44 -0000 On 1/11/21 4:30 PM, Philippe Mathieu-Daudé wrote: > On 1/8/21 11:42 PM, Alex Bennée wrote: >> From: Keith Packard >> >> This commit renames two files which provide ARM semihosting support so >> that they can be shared by other architectures: >> >> 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c >> 2. linux-user/arm/semihost.c -> linux-user/semihost.c >> >> The build system was modified use a new config variable, >> CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM >> softmmu and linux-user default configs. The contents of the source >> files has not been changed in this patch. >> >> Signed-off-by: Keith Packard >> Reviewed-by: Alistair Francis >> Signed-off-by: Alex Bennée >> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> >> --- >> default-configs/devices/arm-softmmu.mak | 1 + >> default-configs/targets/aarch64-linux-user.mak | 1 + >> default-configs/targets/aarch64_be-linux-user.mak | 1 + >> default-configs/targets/arm-linux-user.mak | 1 + >> default-configs/targets/armeb-linux-user.mak | 1 + >> target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 >> linux-user/{arm => }/semihost.c | 0 >> hw/semihosting/Kconfig | 3 +++ >> hw/semihosting/meson.build | 3 +++ >> linux-user/arm/meson.build | 3 --- >> linux-user/meson.build | 1 + >> target/arm/meson.build | 2 -- >> 12 files changed, 12 insertions(+), 5 deletions(-) >> rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) >> rename linux-user/{arm => }/semihost.c (100%) Can we name these file with some explicit "arm_compat_semihosting"? > > Reviewed-by: Philippe Mathieu-Daudé > From MAILER-DAEMON Mon Jan 11 10:34:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyzDA-0005bX-6P for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 10:34:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyzD7-0005Zf-6R for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:34:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:28166) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kyzD5-0005z0-9O for qemu-arm@nongnu.org; Mon, 11 Jan 2021 10:34:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610379262; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lM+jdFO86j9foXQsJJLV0yH/AxIpWuravSnIwRVQSIM=; b=fjZTBvvOPuAeqW5ACxRXhh9Y29gSFhI9faXacAUELe19w0geJO4YQkVe/oyQ+Ox9Jqnz9d 4tkw+MZsaC8u3/Y1lbt6IkSzECc3WdNIocdPfSApiwBeeokx8t6wNjzJCiU9OjtUHRFMZN jQhEaibb1xCXDTIxCdIJTxu3VuGJ40M= Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-409--IvPh_T-PuS-WzG4SkrYiA-1; Mon, 11 Jan 2021 10:34:20 -0500 X-MC-Unique: -IvPh_T-PuS-WzG4SkrYiA-1 Received: by mail-ej1-f71.google.com with SMTP id dc13so54485ejb.9 for ; Mon, 11 Jan 2021 07:34:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lM+jdFO86j9foXQsJJLV0yH/AxIpWuravSnIwRVQSIM=; b=YmVUEuqIChCiboVOaWZVsqdob4sh+uDpcza+0cC6GHU/A3TYFzWPfuV54w/d+QjGd9 uV+c7/pCwq1lDdg+cE957ijXech4HEgOOn47Z8e1I1wUTBsKwGKQO+QW2bJuyd061L7j cfmfjXQJf0gr+ifzNak7n9hVxYaSZbgb/j8/jbN/3SU0UC38uIwZ3o5/On3KDwt3r19h G+JKX9V11B6P4WZHApnXkoEq817vfu9SBd8WQrRKYWzpjrBmsWfbOvcRCWxiXfIuqOSJ 4LWQzQLROndJuE1NxeOgvLeCdX5T1PnHvOXG1RdiaZIHed1K5ypnyWi1/VH1+FSAe5+g LfDQ== X-Gm-Message-State: AOAM530XR/oWRFQLLau5QCspbcAE587YgPREgJqI4PTzQZvIecCTAqVs wkgaMygvdzG01YbeITqjajtWnT7N4r/wg/riY0M1vTxm3QJ+50NVpficJuOO4GaWhw+L3S7eA1N bi4IRMdtf2Bp1 X-Received: by 2002:a05:6402:a5b:: with SMTP id bt27mr14731973edb.222.1610379258749; Mon, 11 Jan 2021 07:34:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSrZn/HzjbSm+Mx2MBp74Kvk3UMEgnEdHPRS/9wyRBby9gHoUtcG27VxFrIW8Kl5ylMVxPVg== X-Received: by 2002:a05:6402:a5b:: with SMTP id bt27mr14731958edb.222.1610379258539; Mon, 11 Jan 2021 07:34:18 -0800 (PST) Received: from [192.168.1.36] (129.red-88-21-205.staticip.rima-tde.net. [88.21.205.129]) by smtp.gmail.com with ESMTPSA id d4sm99773edq.36.2021.01.11.07.34.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 07:34:17 -0800 (PST) Subject: Re: [PATCH v1 13/20] semihosting: Change common-semi API to be architecture-independent To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , Keith Packard , Laurent Vivier , "open list:ARM TCG CPUs" , Alistair Francis References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-14-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <3e3340c7-7eac-9385-1fb4-707be4a1f598@redhat.com> Date: Mon, 11 Jan 2021 16:34:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210108224256.2321-14-alex.bennee@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:34:25 -0000 On 1/8/21 11:42 PM, Alex Bennée wrote: > From: Keith Packard > > The public API is now defined in > hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * > instead of CPUARMState *. All internal functions have been renamed > common_semi_ instead of arm_semi_ or arm_. Aside from the API change, > there are no functional changes in this patch. > > Signed-off-by: Keith Packard > Reviewed-by: Alistair Francis > Message-Id: <20210107170717.2098982-3-keithp@keithp.com> > Signed-off-by: Alex Bennée > --- > hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ > target/arm/cpu.h | 8 -------- > hw/semihosting/common-semi.c | 16 ++++++++++------ > linux-user/aarch64/cpu_loop.c | 3 ++- > linux-user/arm/cpu_loop.c | 3 ++- > target/arm/helper.c | 5 +++-- > target/arm/m_helper.c | 7 ++++++- > 7 files changed, 59 insertions(+), 19 deletions(-) > create mode 100644 hw/semihosting/common-semi.h > > diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h > new file mode 100644 > index 0000000000..bc53e92c79 > --- /dev/null > +++ b/hw/semihosting/common-semi.h > @@ -0,0 +1,36 @@ > +/* > + * Semihosting support for systems modeled on the Arm "Angel" > + * semihosting syscalls design. > + * > + * Copyright (c) 2005, 2007 CodeSourcery. > + * Copyright (c) 2019 Linaro > + * Written by Paul Brook. > + * > + * Copyright © 2020 by Keith Packard > + * Adapted for systems other than ARM, including RISC-V, by Keith Packard > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + * > + * ARM Semihosting is documented in: > + * Semihosting for AArch32 and AArch64 Release 2.0 > + * https://static.docs.arm.com/100863/0200/semihosting.pdf > + * > + */ > + > +#ifndef COMMON_SEMI_H > +#define COMMON_SEMI_H > + > +target_ulong do_common_semihosting(CPUState *cs); Can we name this do_arm_compat_semihosting(CPUState *cs)? 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[88.21.205.129]) by smtp.gmail.com with ESMTPSA id d13sm7204083ejc.44.2021.01.11.07.46.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 07:46:10 -0800 (PST) Subject: Re: [PATCH v1 12/20] semihosting: Move ARM semihosting code to shared directories To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , Keith Packard , Laurent Vivier , "open list:ARM TCG CPUs" , Alistair Francis References: <20210108224256.2321-1-alex.bennee@linaro.org> <20210108224256.2321-13-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <60effd22-55a1-1021-ecbe-4899e68ea9cd@redhat.com> Date: Mon, 11 Jan 2021 16:46:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210108224256.2321-13-alex.bennee@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:46:21 -0000 On 1/8/21 11:42 PM, Alex Bennée wrote: > From: Keith Packard > > This commit renames two files which provide ARM semihosting support so > that they can be shared by other architectures: > > 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c > 2. linux-user/arm/semihost.c -> linux-user/semihost.c > > The build system was modified use a new config variable, > CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM > softmmu and linux-user default configs. The contents of the source > files has not been changed in this patch. > > Signed-off-by: Keith Packard > Reviewed-by: Alistair Francis > Signed-off-by: Alex Bennée > Message-Id: <20210107170717.2098982-2-keithp@keithp.com> > --- > default-configs/devices/arm-softmmu.mak | 1 + > default-configs/targets/aarch64-linux-user.mak | 1 + > default-configs/targets/aarch64_be-linux-user.mak | 1 + > default-configs/targets/arm-linux-user.mak | 1 + > default-configs/targets/armeb-linux-user.mak | 1 + > target/arm/arm-semi.c => hw/semihosting/common-semi.c | 0 > linux-user/{arm => }/semihost.c | 0 > hw/semihosting/Kconfig | 3 +++ > hw/semihosting/meson.build | 3 +++ > linux-user/arm/meson.build | 3 --- > linux-user/meson.build | 1 + > target/arm/meson.build | 2 -- > 12 files changed, 12 insertions(+), 5 deletions(-) > rename target/arm/arm-semi.c => hw/semihosting/common-semi.c (100%) > rename linux-user/{arm => }/semihost.c (100%) ... > diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig > index efe0a30734..4c30dc6b16 100644 > --- a/hw/semihosting/Kconfig > +++ b/hw/semihosting/Kconfig > @@ -1,3 +1,6 @@ > > config SEMIHOSTING > bool > + > +config ARM_COMPATIBLE_SEMIHOSTING > + bool This misses: "select SEMIHOSTING" 'SEMIHOSTING' is a bit confusing. Wondering about better names, maybe SEMIHOSTING_HOST_CONSOLE is clearer? (question not related to this patch). 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Mon, 11 Jan 2021 15:49:38 +0000 (UTC) Date: Mon, 11 Jan 2021 10:49:37 -0500 (EST) From: Miroslav Rezanina To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt Message-ID: <245930420.32442484.1610380177977.JavaMail.zimbra@redhat.com> In-Reply-To: <20210111150114.1415930-5-f4bug@amsat.org> References: <20210111150114.1415930-1-f4bug@amsat.org> <20210111150114.1415930-5-f4bug@amsat.org> Subject: Re: [RFC PATCH 4/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements MIME-Version: 1.0 X-Originating-IP: [10.40.192.93, 10.4.195.1] Thread-Topic: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Thread-Index: NYNXgELFV+TcZBY9QJ2v3tKDyrLcCQ== X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mrezanin@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=mrezanin@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 15:49:51 -0000 ----- Original Message ----- > From: "Philippe Mathieu-Daud=C3=A9" > To: qemu-devel@nongnu.org > Cc: "Huacai Chen" , "Aurelien Jarno" , "Aleksandar Rikalo" > , "Thomas Huth" , "Stefan= Weil" , > qemu-riscv@nongnu.org, qemu-arm@nongnu.org, "Jiaxun Yang" , qemu-s390x@nongnu.org, > "Philippe Mathieu-Daud=C3=A9" , "Cornelia Huck" , "Richard Henderson" > , "Andrzej Zaborowski" ,= "Alistair Francis" > , "Palmer Dabbelt" , "Miros= lav Rezanina" > Sent: Monday, January 11, 2021 4:01:13 PM > Subject: [RFC PATCH 4/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_= OP_ARGS elements >=20 > tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. >=20 > The Aarch64 target already does this since commit 8d8db193f25 > ("tcg-aarch64: Hoist common argument loads in tcg_out_op"), > SPARC since commit b357f902bff ("tcg-sparc: Hoist common argument > loads in tcg_out_op"). >=20 > RISCV missed it upon introduction in commit bdf503819ee > ("tcg/riscv: Add the out op decoder"), MIPS since commit > 22ee3a987d5 ("tcg-mips: Hoist args loads") and i386 since > commit 42d5b514928 ("tcg/i386: Hoist common arguments in > tcg_out_op"). >=20 > Provide this information as a hint to the compiler in the function > prototype, and update the funtion definitions. >=20 > This fixes this warning (using GCC 11): >=20 > tcg/aarch64/tcg-target.c.inc:1855:37: error: argument 3 of type 'cons= t > TCGArg[16]' {aka 'const long unsigned int[16]'} with mismatched bound > [-Werror=3Darray-parameter=3D] > tcg/aarch64/tcg-target.c.inc:1856:34: error: argument 4 of type 'cons= t > int[16]' with mismatched bound [-Werror=3Darray-parameter=3D] >=20 > Reported-by: Miroslav Rezanina > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > RFC because such compiler hint is somehow "new" to me. >=20 > Also I expect this to be superseeded by Richard 'tcg constant' > branch mentioned here: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg771401.html > --- > tcg/tcg.c | 5 +++-- > tcg/i386/tcg-target.c.inc | 3 ++- > tcg/mips/tcg-target.c.inc | 3 ++- > tcg/riscv/tcg-target.c.inc | 3 ++- > tcg/tci/tcg-target.c.inc | 5 +++-- > 5 files changed, 12 insertions(+), 7 deletions(-) >=20 > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 472bf1755bf..97d074d8fab 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -110,8 +110,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, > TCGReg ret, TCGReg arg1, > static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg > arg); > static void tcg_out_movi(TCGContext *s, TCGType type, > TCGReg ret, tcg_target_long arg); > -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, > - const int *const_args); > +static void tcg_out_op(TCGContext *s, TCGOpcode opc, > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]); > #if TCG_TARGET_MAYBE_vec > static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, > TCGReg dst, TCGReg src); > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 46e856f4421..d121dca8789 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -2215,7 +2215,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg > *args, bool is64) > } > =20 > static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > - const TCGArg *args, const int *const_args) > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > TCGArg a0, a1, a2; > int c, const_a2, vexop, rexw =3D 0; > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index add157f6c32..b9bb54f0ecc 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1691,7 +1691,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opc= v2, > MIPSInsn opcv6, > } > =20 > static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > - const TCGArg *args, const int *const_args) > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > MIPSInsn i1, i2; > TCGArg a0, a1, a2; > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index c60b91ba58f..5bf0d069532 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1238,7 +1238,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg > *args, bool is_64) > static const tcg_insn_unit *tb_ret_addr; > =20 > static void tcg_out_op(TCGContext *s, TCGOpcode opc, > - const TCGArg *args, const int *const_args) > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > TCGArg a0 =3D args[0]; > TCGArg a1 =3D args[1]; > diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc > index d5a4d9d37cf..60464524f3d 100644 > --- a/tcg/tci/tcg-target.c.inc > +++ b/tcg/tci/tcg-target.c.inc > @@ -553,8 +553,9 @@ static inline void tcg_out_call(TCGContext *s, const > tcg_insn_unit *arg) > old_code_ptr[1] =3D s->code_ptr - old_code_ptr; > } > =20 > -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, > - const int *const_args) > +static void tcg_out_op(TCGContext *s, TCGOpcode opc, > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > uint8_t *old_code_ptr =3D s->code_ptr; > =20 > -- > 2.26.2 >=20 > Reviewed-by: Miroslav Rezanina =20 --=20 Miroslav Rezanina Software Engineer - Virtualization Team Maintainer From MAILER-DAEMON Mon Jan 11 11:09:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kyzko-0000CY-JF for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 11:09:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyzkm-00008p-SD for qemu-arm@nongnu.org; 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Mon, 11 Jan 2021 11:09:07 -0500 X-MC-Unique: O2U0HcbVM36YveqpPWI5Bw-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 04077803622; Mon, 11 Jan 2021 16:09:03 +0000 (UTC) Received: from [10.36.115.103] (ovpn-115-103.ams2.redhat.com [10.36.115.103]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7DA6B19C59; Mon, 11 Jan 2021 16:08:39 +0000 (UTC) Subject: Re: [PATCH 1/2] sysemu/runstate: Let runstate_is_running() return bool To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang References: <20210111152020.1422021-1-philmd@redhat.com> <20210111152020.1422021-2-philmd@redhat.com> From: David Hildenbrand Organization: Red Hat GmbH Message-ID: Date: Mon, 11 Jan 2021 17:08:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20210111152020.1422021-2-philmd@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Received-SPF: pass client-ip=216.205.24.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 16:09:13 -0000 On 11.01.21 16:20, Philippe Mathieu-Daudé wrote: > runstate_check() returns a boolean. runstate_is_running() > returns what runstate_check() returns, also a boolean. > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/sysemu/runstate.h | 2 +- > softmmu/runstate.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h > index e557f470d42..3ab35a039a0 100644 > --- a/include/sysemu/runstate.h > +++ b/include/sysemu/runstate.h > @@ -6,7 +6,7 @@ > > bool runstate_check(RunState state); > void runstate_set(RunState new_state); > -int runstate_is_running(void); > +bool runstate_is_running(void); > bool runstate_needs_reset(void); > bool runstate_store(char *str, size_t size); > > diff --git a/softmmu/runstate.c b/softmmu/runstate.c > index 636aab0addb..c7a67147d17 100644 > --- a/softmmu/runstate.c > +++ b/softmmu/runstate.c > @@ -217,7 +217,7 @@ void runstate_set(RunState new_state) > current_run_state = new_state; > } > > -int runstate_is_running(void) > +bool runstate_is_running(void) > { > return runstate_check(RUN_STATE_RUNNING); > } > Reviewed-by: David Hildenbrand -- Thanks, David / dhildenb From MAILER-DAEMON Mon Jan 11 11:46:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz0Kp-0004HI-EF for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 11:46:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz0Kl-0004FS-88; Mon, 11 Jan 2021 11:46:24 -0500 Received: from mail-qk1-x730.google.com ([2607:f8b0:4864:20::730]:41355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz0Ki-00024w-I1; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9bf21ccd-7e23-8329-35b8-bf09d35e335b@amsat.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=natechancellor@gmail.com; helo=mail-qk1-x730.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 16:46:25 -0000 On Mon, Jan 11, 2021 at 11:04:25AM +0100, Philippe Mathieu-Daudé wrote: > +Peter > > On 1/11/21 2:11 AM, Nathan Chancellor wrote: > > On Tue, Sep 01, 2020 at 12:40:42PM +0200, Philippe Mathieu-Daudé wrote: > >> We call pci_register_root_bus() to register 4 IRQs with the > >> ppc4xx_pci_set_irq() handler. As it can only be called with > >> values in the [0-4[ range, replace the pointless warning by > >> an assert(). > >> > >> Signed-off-by: Philippe Mathieu-Daudé > >> --- > >> hw/ppc/ppc4xx_pci.c | 5 +---- > >> 1 file changed, 1 insertion(+), 4 deletions(-) > >> > >> diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c > >> index cd3f192a138..503ef46b39a 100644 > >> --- a/hw/ppc/ppc4xx_pci.c > >> +++ b/hw/ppc/ppc4xx_pci.c > >> @@ -256,10 +256,7 @@ static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) > >> qemu_irq *pci_irqs = opaque; > >> > >> trace_ppc4xx_pci_set_irq(irq_num); > >> - if (irq_num < 0) { > >> - fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); > >> - return; > >> - } > >> + assert(irq_num >= 0); > >> qemu_set_irq(pci_irqs[irq_num], level); > >> } > >> > >> -- > >> 2.26.2 > >> > >> > > > > Hopefully reporting this here is okay, I find Launchpad hard to use but > > I can file it there if need be. > > > > The assertion added by this patch triggers while trying to boot a > > ppc44x_defconfig Linux kernel: > > > > $ qemu-system-ppc \ > > -machine bamboo \ > > -no-reboot \ > > -append console=ttyS0 \ > > -display none \ > > -kernel uImage \ > > -m 128m \ > > -nodefaults \ > > -serial mon:stdio > > Linux version 5.11.0-rc3 (nathan@ubuntu-m3-large-x86) (powerpc-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #1 Sun Jan 10 15:52:24 MST 2021 > > Using PowerPC 44x Platform machine description > > ioremap() called early from find_legacy_serial_ports+0x64c/0x794. Use early_ioremap() instead > ... > > PCI: Probing PCI hardware > > PCI host bridge to bus 0000:00 > > pci_bus 0000:00: root bus resource [io 0x0000-0xffff] > > pci_bus 0000:00: root bus resource [mem 0xa0000000-0xbfffffff] > > pci_bus 0000:00: root bus resource [bus 00-ff] > > pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff > > pci 0000:00:00.0: [1014:027f] type 00 class 0x068000 > > qemu-system-ppc: ../hw/ppc/ppc4xx_pci.c:259: ppc4xx_pci_set_irq: Assertion `irq_num >= 0' failed. > > > > On v5.2.0, it looks like a higher assertion triggers, added by > > commit 459ca8bfa4 ("pci: Assert irqnum is between 0 and bus->nirqs in > > pci_bus_change_irq_level"). > > > > qemu-system-ppc: ../hw/pci/pci.c:253: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed. > > Running with '-trace ppc4xx_pci\*': > > 1275265@1610357661.994462:ppc4xx_pci_map_irq devfn 0x0 irq 0 -> 0 > 1275265@1610357661.994480:ppc4xx_pci_set_irq PCI irq -1 > > (gdb) bt > #0 0x00007fc70a8a19e5 in raise () at /lib64/libc.so.6 > #1 0x00007fc70a88a895 in abort () at /lib64/libc.so.6 > #2 0x00007fc70a88a769 in _nl_load_domain.cold () at /lib64/libc.so.6 > #3 0x00007fc70a899e76 in annobin_assert.c_end () at /lib64/libc.so.6 > #4 0x0000560953c2bfe0 in ppc4xx_pci_set_irq (opaque=0x560955dcf9a0, > irq_num=-1, level=0) at hw/ppc/ppc4xx_pci.c:259 > #5 0x0000560953a20474 in pci_change_irq_level (pci_dev=0x560955dd0e40, > irq_num=-1, change=0) at hw/pci/pci.c:262 > #6 0x0000560953a1d028 in pci_update_irq_disabled (d=0x560955dd0e40, > was_irq_disabled=0) at hw/pci/pci.c:1375 > #7 0x0000560953a1ccb3 in pci_default_write_config (d=0x560955dd0e40, > addr=4, val_in=1030, l=2) at hw/pci/pci.c:1415 > #8 0x0000560953978977 in pci_host_config_write_common > (pci_dev=0x560955dd0e40, addr=4, limit=256, val=1030, len=2) at > hw/pci/pci_host.c:83 > #9 0x0000560953978cb9 in pci_data_write (s=0x560955dd0210, > addr=2147483652, val=1030, len=2) at hw/pci/pci_host.c:120 > #10 0x0000560953978eeb in pci_host_data_write (opaque=0x560955dcf350, > addr=0, val=1030, len=2) at hw/pci/pci_host.c:167 > > How can irq be -1? pci_update_irq_disabled() hasn't been updated > since commit a7b15a5cc626 (2009-12-23): > > 1368 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) > 1369 { > 1370 int i, disabled = pci_irq_disabled(d); > 1371 if (disabled == was_irq_disabled) > 1372 return; > 1373 for (i = 0; i < PCI_NUM_PINS; ++i) { > 1374 int state = pci_irq_state(d, i); > 1375 pci_change_irq_level(d, i, disabled ? -state : state); > 1376 } > 1377 } > > Let's rebuild using --enable-sanitizers to check an overflow occured: > > 1286013@1610358549.342593:ppc4xx_pci_map_irq devfn 0x0 irq 0 -> 0 > ================================================================= > ==1286011==ERROR: AddressSanitizer: heap-buffer-overflow on address > 0x60200004f78c at pc 0x55b6d738454c bp 0x7f779b9f7810 sp 0x7f779b9f7808 > READ of size 4 at 0x60200004f78c thread T2 > #0 0x55b6d738454b in pci_change_irq_level hw/pci/pci.c:261:29 > #1 0x55b6d73763be in pci_update_irq_disabled hw/pci/pci.c:1375:9 > #2 0x55b6d7374e2d in pci_default_write_config hw/pci/pci.c:1415:9 > #3 0x55b6d70cb8ec in pci_host_config_write_common hw/pci/pci_host.c:83:5 > #4 0x55b6d70cc43f in pci_data_write hw/pci/pci_host.c:120:5 > #5 0x55b6d70ccd43 in pci_host_data_write hw/pci/pci_host.c:167:9 > #6 0x55b6d8505348 in memory_region_write_accessor softmmu/memory.c:483:5 > #7 0x55b6d8504c1a in access_with_adjusted_size softmmu/memory.c:544:18 > #8 0x55b6d8503316 in memory_region_dispatch_write > softmmu/memory.c:1465:16 > #9 0x55b6d878ab51 in flatview_write_continue exec.c:3177:23 > #10 0x55b6d8779046 in flatview_write exec.c:3217:14 > #11 0x55b6d879d1ab in subpage_write exec.c:2829:12 > #12 0x55b6d8505af7 in memory_region_write_with_attrs_accessor > softmmu/memory.c:503:12 > #13 0x55b6d8504af4 in access_with_adjusted_size softmmu/memory.c:539:18 > #14 0x55b6d850376e in memory_region_dispatch_write > softmmu/memory.c:1472:13 > #15 0x55b6d8485b60 in io_writex accel/tcg/cputlb.c:1121:9 > #16 0x55b6d845ef8b in store_helper accel/tcg/cputlb.c:2140:13 > #17 0x55b6d845f558 in helper_le_stw_mmu accel/tcg/cputlb.c:2194:5 > #18 0x7f77a40c0252 () > > 0x60200004f78c is located 4 bytes to the left of 16-byte region > [0x60200004f790,0x60200004f7a0) > allocated by thread T0 here: > #0 0x55b6d6ab9227 in calloc (qemu-system-ppc+0x1a9f227) > #1 0x7f77f3ab19b0 in g_malloc0 (/lib64/libglib-2.0.so.0+0x589b0) > #2 0x55b6d7370ef0 in pci_register_root_bus hw/pci/pci.c:493:5 > #3 0x55b6d7dec5de in ppc4xx_pcihost_realize hw/ppc/ppc4xx_pci.c:318:9 > #4 0x55b6d8a04ffb in device_set_realized hw/core/qdev.c:864:13 > #5 0x55b6d89309e8 in property_set_bool qom/object.c:2202:5 > #6 0x55b6d8928f92 in object_property_set qom/object.c:1349:5 > #7 0x55b6d891aa29 in object_property_set_qobject qom/qom-qobject.c:28:10 > #8 0x55b6d8929d71 in object_property_set_bool qom/object.c:1416:15 > #9 0x55b6d89f76fc in qdev_realize hw/core/qdev.c:379:12 > #10 0x55b6d89f7734 in qdev_realize_and_unref hw/core/qdev.c:386:11 > #11 0x55b6d7ccc37e in sysbus_realize_and_unref hw/core/sysbus.c:261:12 > #12 0x55b6d7ccc0a3 in sysbus_create_varargs hw/core/sysbus.c:236:5 > #13 0x55b6d7dbce60 in bamboo_init hw/ppc/ppc440_bamboo.c:212:11 > #14 0x55b6d6c3cdae in machine_run_board_init hw/core/machine.c:1144:5 > #15 0x55b6d86893ee in qemu_init softmmu/vl.c:4355:5 > #16 0x55b6d6af0f49 in main softmmu/main.c:49:5 > #17 0x7f77f23bd041 in __libc_start_main (/lib64/libc.so.6+0x27041) > > Thread T2 created by T0 here: > #0 0x55b6d6a32bb6 in pthread_create (qemu-system-ppc+0x1a18bb6) > #1 0x55b6d92a1df4 in qemu_thread_create util/qemu-thread-posix.c:558:11 > #2 0x55b6d8807dc5 in qemu_tcg_init_vcpu softmmu/cpus.c:1926:13 > #3 0x55b6d8807142 in qemu_init_vcpu softmmu/cpus.c:2047:9 > #4 0x55b6d7e79f88 in ppc_cpu_realize > target/ppc/translate_init.c.inc:10146:5 > #5 0x55b6d8a04ffb in device_set_realized hw/core/qdev.c:864:13 > #6 0x55b6d89309e8 in property_set_bool qom/object.c:2202:5 > #7 0x55b6d8928f92 in object_property_set qom/object.c:1349:5 > #8 0x55b6d891aa29 in object_property_set_qobject qom/qom-qobject.c:28:10 > #9 0x55b6d8929d71 in object_property_set_bool qom/object.c:1416:15 > #10 0x55b6d89f76fc in qdev_realize hw/core/qdev.c:379:12 > #11 0x55b6d724d4db in cpu_create hw/core/cpu.c:62:10 > #12 0x55b6d7dbc024 in bamboo_init hw/ppc/ppc440_bamboo.c:183:11 > #13 0x55b6d6c3cdae in machine_run_board_init hw/core/machine.c:1144:5 > #14 0x55b6d86893ee in qemu_init softmmu/vl.c:4355:5 > #15 0x55b6d6af0f49 in main softmmu/main.c:49:5 > #16 0x7f77f23bd041 in __libc_start_main (/lib64/libc.so.6+0x27041) > > SUMMARY: AddressSanitizer: heap-buffer-overflow hw/pci/pci.c:261:29 in > pci_change_irq_level > Shadow bytes around the buggy address: > 0x0c0480001ea0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 > 0x0c0480001eb0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 > 0x0c0480001ec0: fa fa fd fd fa fa fd fd fa fa 00 06 fa fa 00 02 > 0x0c0480001ed0: fa fa 00 00 fa fa 00 00 fa fa 00 01 fa fa 05 fa > 0x0c0480001ee0: fa fa 06 fa fa fa fd fd fa fa 06 fa fa fa 00 03 > =>0x0c0480001ef0: fa[fa]00 00 fa fa fd fa fa fa fd fa fa fa fd fa > 0x0c0480001f00: fa fa fd fa fa fa 00 01 fa fa fd fd fa fa fd fa > 0x0c0480001f10: fa fa fd fd fa fa 00 02 fa fa fd fa fa fa 00 02 > 0x0c0480001f20: fa fa 05 fa fa fa 07 fa fa fa 00 01 fa fa 07 fa > 0x0c0480001f30: fa fa 05 fa fa fa 07 fa fa fa fd fd fa fa 00 02 > 0x0c0480001f40: fa fa 05 fa fa fa 07 fa fa fa 00 01 fa fa 07 fa > Shadow byte legend (one shadow byte represents 8 application bytes): > Addressable: 00 > Partially addressable: 01 02 03 04 05 06 07 > Heap left redzone: fa > Freed heap region: fd > Stack left redzone: f1 > Stack mid redzone: f2 > Stack right redzone: f3 > Stack after return: f5 > Stack use after scope: f8 > Global redzone: f9 > Global init order: f6 > Poisoned by user: f7 > Container overflow: fc > Array cookie: ac > Intra object redzone: bb > ASan internal: fe > Left alloca redzone: ca > Right alloca redzone: cb > Shadow gap: cc > ==1286011==ABORTING > > I see this sysbus_create_varargs() call in bamboo_init() > has recently been updated by Peter in commit 0270d74ef88 > ("hw/ppc/ppc440_bamboo: Drop use of ppcuic_init()"). > > Running with current master (7b09f127738) the assert is > not reached: > > Linux version 5.11.0-rc3 (nathan@ubuntu-m3-large-x86) (powerpc-linux-gcc > (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #1 Sun Jan 10 15:52:24 MST 2021 > Using PowerPC 44x Platform machine description > ioremap() called early from find_legacy_serial_ports+0x64c/0x794. Use > early_ioremap() instead > printk: bootconsole [udbg0] enabled > ----------------------------------------------------- > phys_mem_size = 0x8000000 > dcache_bsize = 0x20 > icache_bsize = 0x20 > cpu_features = 0x0000000000000100 > possible = 0x0000000040000100 > always = 0x0000000000000100 > cpu_user_features = 0x8c008000 0x00000000 > mmu_features = 0x00000008 > ----------------------------------------------------- > Zone ranges: > Normal [mem 0x0000000000000000-0x0000000007ffffff] > Movable zone start for each node > Early memory node ranges > node 0: [mem 0x0000000000000000-0x0000000007ffffff] > Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff] > MMU: Allocated 1088 bytes of context maps for 255 contexts > Built 1 zonelists, mobility grouping on. Total pages: 32448 > Kernel command line: console=ttyS0 > Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear) > Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear) > mem auto-init: stack:off, heap alloc:off, heap free:off > Memory: 122712K/131072K available (5040K kernel code, 236K rwdata, 1260K > rodata, 200K init, 134K bss, 8360K reserved, 0K cma-reserved) > Kernel virtual memory layout: > * 0xffbdf000..0xfffff000 : fixmap > * 0xffbdd000..0xffbdf000 : early ioremap > * 0xd1000000..0xffbdd000 : vmalloc & ioremap > SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 > NR_IRQS: 512, nr_irqs: 512, preallocated irqs: 16 > Oops: Exception in kernel mode, sig: 4 [#1] > BE PAGE_SIZE=4K PowerPC 44x Platform > Modules linked in: > CPU: 0 PID: 0 Comm: swapper Not tainted 5.11.0-rc3 #1 > NIP: c0019e58 LR: c062e3a0 CTR: c0019e58 > REGS: c067fe90 TRAP: 0700 Not tainted (5.11.0-rc3) > MSR: 000a1000 CR: 84000224 XER: 20000000 > > GPR00: c062e370 c067ff50 c065c300 c0019e58 00000000 c0019238 c067fde0 > c065c300 > GPR08: 00000000 00000000 c066fca4 00000066 84000222 00000000 00000000 > 00000000 > GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 c0000010 > 00000000 > GPR24: c0651594 c0651594 c0690000 c7ffe080 c0690000 c05c6f64 c0680000 > c0802100 > NIP [c0019e58] __mtdcr_table+0xc20/0x3ff8 > LR [c062e3a0] uic_init_one+0x13c/0x214 > Call Trace: > [c067ff50] [c062e370] uic_init_one+0x10c/0x214 (unreliable) > [c067ff80] [c062e4f8] uic_init_tree+0x80/0x174 > [c067ffb0] [c0627af8] start_kernel+0x33c/0x508 > [c067fff0] [c0000044] _start+0x44/0x88 > Instruction dump: > 7c9f2b86 4e800020 7c603286 4e800020 7c803386 4e800020 7c613286 4e800020 > 7c813386 4e800020 7c623286 4e800020 <7c823386> 4e800020 7c633286 4e800020 > random: get_random_bytes called from oops_exit+0x44/0x84 with crng_init=0 > ---[ end trace 0000000000000000 ]--- > > Kernel panic - not syncing: Attempted to kill the idle task! > Rebooting in 180 seconds.. > > I suppose we can end this thread as NOTABUG. > > Thanks for testing and your report, > > Phil. For what it's worth, I initially ran into this assertion on v5.2.0, which does not include Peter's commit since it is only in master (and I reported a problem with separately). If they are indeed related then fair enough :) thanks for taking a look. Cheers, Nathan From MAILER-DAEMON Mon Jan 11 12:23:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz0uG-00059k-OF for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 12:23:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz0uE-00056b-C9 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:23:02 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:41821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz0uB-0000nx-LE for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:23:01 -0500 Received: by mail-pf1-x42b.google.com with SMTP id q20so314635pfu.8 for ; Mon, 11 Jan 2021 09:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=KcBBYyRIsubFJ5K7YVoag2+OIR54LyMij+S3tqSg3SU=; b=Ass7ItIgdyqkDHQpekFD7Pdvu8l5Lc8O3Aj7ZjiXf8uVKZQhMM+311Wx84fd7Mm5rY VWSJBdvVkvg9ZpXQIIOSTngKPOwdyFUR17oWDe1hDYEF59L291wQ3sZ4eN6fil+N5V03 xqMTjozaCEWuKyqTYmJGsL8rl9OnY1oBG4ugG3ku17Sj5XlRL/fRP64xvfrj3myHZ0z3 cSMnycpq+XOyuYWmFPtsL78SfefCn9Bh6wykm/r3fY8YNsPFFBMoK6RT1D5YFZS/TbrZ t5MlNk5zKBvYkfBs+X+ByPuzoq+/FX0bVC2TG5NAFJ2tekOJrSzbYSv3Kh9NrUO8r54+ PE/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=KcBBYyRIsubFJ5K7YVoag2+OIR54LyMij+S3tqSg3SU=; b=m/Re5ySnjFOo64PLl/TTAT5X61J2dPUAfTvv9VQs6SAS8ArDAopqT43Ylgykac98Qe lnNoCtGY+koEpAXtNbMTQawlveZ83ZQD5H87bP3N055QR2aaNo8sE0LeuUI/4m9gWQ/E F9f6/Kr144P9T+VPBMVpFsqjCsBNMPw98U1z+VZDIkprSCMBMhXDji8Aa9dH8UnhAZu/ 7BKdMM5ymlyyzv7eW7QF6dd/TMUVyNcJDnBaYQtES+gzcNmQG3OxSFjv9tF/GSCwsb+y HiR2Oyy7hyIqec3jXF33XxJRwhOOEiZt2pbijrpz8LKr/ktaeIpyXgX3aAj75ti6Ix1B w2xA== X-Gm-Message-State: AOAM531gYiOB5KVgBIugR9/yzx4Q7F37wyurMgsyK/XjnBS73JPiTmub r0PbqnsIK1cWcwUKrXGElNm/MQ== X-Google-Smtp-Source: ABdhPJzwPL60+c4oVmvuxvwyRiOaudTy7LIObvZ0OOlgaXDIJjZL2P1rVdRkmZebGYDh/cPQWh6iQw== X-Received: by 2002:aa7:95a4:0:b029:19e:abd2:4a88 with SMTP id a4-20020aa795a40000b029019eabd24a88mr432060pfk.2.1610385778087; Mon, 11 Jan 2021 09:22:58 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id v19sm86080pjg.50.2021.01.11.09.22.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 09:22:56 -0800 (PST) Subject: Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Huacai Chen , Aurelien Jarno , Aleksandar Rikalo , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Jiaxun Yang , qemu-s390x@nongnu.org, Cornelia Huck , Andrzej Zaborowski , Alistair Francis , Palmer Dabbelt References: <20210111150114.1415930-1-f4bug@amsat.org> From: Richard Henderson Message-ID: <43f360be-af44-27ce-619b-7a2ad169aa2f@linaro.org> Date: Mon, 11 Jan 2021 07:22:52 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210111150114.1415930-1-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 17:23:03 -0000 On 1/11/21 5:01 AM, Philippe Mathieu-Daudé wrote: > Attempt to fix the warning reported by Miroslav using GCC 10: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html > > Philippe Mathieu-Daudé (5): > tcg/arm: Hoist common argument loads in tcg_out_op() > tcg/ppc: Hoist common argument loads in tcg_out_op() > tcg/s390: Hoist common argument loads in tcg_out_op() > tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements > tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements I've been trying to figure out a cleaner way to handle these, but this is certainly ok for now, and avoids the Werror. Reviewed-by: Richard Henderson Will queue to tcg-next. r~ From MAILER-DAEMON Mon Jan 11 12:48:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz1IP-0008Mr-1H for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 12:48:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57252) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz1IM-0008Ks-7B for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:47:58 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:35668) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz1IH-0004tu-RP for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:47:57 -0500 Received: by mail-wr1-x42e.google.com with SMTP id r3so690730wrt.2 for ; Mon, 11 Jan 2021 09:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=7PomrZU0jMeuj2pSx76rGsVMpY5/lWRJj77kNrVmTOQ=; b=eN3dBxOzR44brDRBdWt3v4cXwY6j30skPdqKuTGRWe/DKoQpXBEbYCNfUfWnxSmOMu XBy0JNbmcqHL9/5eTyQHRZK0TylvdmoTIQtrHYnXogIczvSNKQKMvqS2IDa41gSpOeb0 jCa+KqJnWspIoTNo5Vo72FWylPM+UqOOAL93Y9lhyE/E+JSasH8i1x5Qt4PEIRazuKwW 47iItS+Yn4S8d/GkngwvwwLE36JBsUFx206rpGBdpMxlY9JBo+PoakQ2ux2Lr1L6YVLy T4Sq750nq5cgVMPwYor3Gt9Bgx5x9vcasoQAVPtwwZubrFxLtHxMm/RPTAu3LFDIRtjD wmlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=7PomrZU0jMeuj2pSx76rGsVMpY5/lWRJj77kNrVmTOQ=; b=dYFPg7yNevs/3nHaMYOGqpIHmFFVrBbo3fMOiAhtCt4bNu2gSrqpjvo0bX62V45SG4 rcClsHb/KCxlYzEKzZyPRPOPFb3X4LYaMtQn1i5L58q6C+b5evJ6seWixqke8TxcfG7L 9lF+6Gd9bUzIG4xYytLhb4+hEQq4RuzeeZHBblsBXuGebRl6HASpCmlJzu6MP/kYgeJi c2QufFOXDJBnT95cNabW/PieERpNt4H9tYKxvgcMheyNDVyIWc6B8I75g4J+v9puNF4u sWFPAzJhjySEAzHsKTglp1tAoJtzyDbvX+s1MXvmXklQOP5WeHw+NHhzKzngBhviSGn2 cfhg== X-Gm-Message-State: AOAM530mG+25jdom+rRq12XtTk6YK9E22qEqqUvGQbo8FNCEApYsehLB zdvPbKoNndtNrJXxxvlidV5huA== X-Google-Smtp-Source: ABdhPJyEoJCuSw+5tRtzaJyx6mVyGEBtWFwj20lKG9ywN4EzrcnynxBCh/RF0f45AqXVj56ADnb/VQ== X-Received: by 2002:a5d:5385:: with SMTP id d5mr269757wrv.384.1610387272416; Mon, 11 Jan 2021 09:47:52 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id v20sm26616wml.34.2021.01.11.09.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 09:47:51 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8337D1FF7E; Mon, 11 Jan 2021 17:47:50 +0000 (GMT) References: <20210111152020.1422021-1-philmd@redhat.com> <20210111152020.1422021-2-philmd@redhat.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?utf-8?Q?C=C3=A9dric?= Le Goater , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: Re: [PATCH 1/2] sysemu/runstate: Let runstate_is_running() return bool Date: Mon, 11 Jan 2021 17:46:36 +0000 In-reply-to: <20210111152020.1422021-2-philmd@redhat.com> Message-ID: <87o8hvnz5l.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 17:47:58 -0000 Philippe Mathieu-Daud=C3=A9 writes: > runstate_check() returns a boolean. runstate_is_running() > returns what runstate_check() returns, also a boolean. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e From MAILER-DAEMON Mon Jan 11 12:48:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz1JL-0001Eu-IK for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 12:48:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz1JJ-0001BU-E8 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:48:57 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:54174) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz1JF-00054B-TJ for qemu-arm@nongnu.org; Mon, 11 Jan 2021 12:48:57 -0500 Received: by mail-wm1-x32c.google.com with SMTP id k10so43501wmi.3 for ; Mon, 11 Jan 2021 09:48:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=HjFjB02VUOcj2JDmR/K56mtMUPw1JqKruxO3gsfgtG0=; b=Z1BLHnk/IllfoIqIlxKJ0XD2wgjI2evX/5XsMH9aGtoY/foB5Zp0OZr8+O18Z54N3P vFsoIVlUr7x9Y30UZt1g+VOvY8vJ0NhhFFf2vN/wzVP3Kpz1pVqYsTLQ3muqdwj0v8Y5 F9VbBO51j75TEHi3Hsgg7/C+0sYNIOp0sLXBtkDC9Q/35JGz6cyiqvyi3+ptkFR33Rvf 3RBT2H7VMu8ETRySwN8DK70ixgS2jWeoVWpQS1Wylo7thAyY7nH2Kq28D8Zatl3+Bobs TdnNFPVrst4l7kXfPxCLsQ62wZ5e8A8OpP+u3d7lU4jKfBn2zsMJ+iKqTpkuPX5Vqm2S db4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=HjFjB02VUOcj2JDmR/K56mtMUPw1JqKruxO3gsfgtG0=; b=ePKXekXUGHjCMCfyUwzz5/H7kKSaiBjA1vq0N3TBcLyRKvA8ilC9+aWI6fn84H+Xmp Ykqvd/0EUL9355+m6suYcYsFUiorlyadhYKTeZkk6lrCMFnHpalMNvHWyXzIC0J+Gj1s DT/Br0omC3xLFB1d7iBgEyIi8Q2N6Gt5LfbbuRWtuGA642RmyCCEj/wmQv/u4uikZ815 epKaPuk0lz7dJF2lyxYRonr0m2ZgGgHVI3XhmCReoNKIY8FcUInEYPypSGzgKBQQvhgq zk9Nexxv3OtkIicQ/mx0c+YQX7ZVC17M0awerbieAzUCH5wWJ4mWXFHXZvwozvlASyZY b4EA== X-Gm-Message-State: AOAM533PvCBEnMWz4qoCuZc+Fgg2Ux6PkXMvz+HzGanFCcvHmBUGUbuG 3qrsKVMyabTKZfviLLLCzMMMFg== X-Google-Smtp-Source: ABdhPJxFl0pGJIm5UheooE53gyVfAACVfyEjNoEnS7yM3rBuAokl0gYAMKI4jSlEoOleDrcPABVpeg== X-Received: by 2002:a1c:7213:: with SMTP id n19mr15554wmc.14.1610387332427; Mon, 11 Jan 2021 09:48:52 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id o3sm396503wrc.93.2021.01.11.09.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 09:48:51 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B2CE01FF7E; Mon, 11 Jan 2021 17:48:50 +0000 (GMT) References: <20210111152020.1422021-1-philmd@redhat.com> <20210111152020.1422021-3-philmd@redhat.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?utf-8?Q?C=C3=A9dric?= Le Goater , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: Re: [PATCH 2/2] sysemu: Let VMChangeStateHandler take boolean 'running' argument Date: Mon, 11 Jan 2021 17:48:41 +0000 In-reply-to: <20210111152020.1422021-3-philmd@redhat.com> Message-ID: <87lfcznz3x.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 17:48:57 -0000 Philippe Mathieu-Daud=C3=A9 writes: > The 'running' argument from VMChangeStateHandler does not require > other value than 0 / 1. Make it a plain boolean. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Seems reasonable Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e From MAILER-DAEMON Mon Jan 11 14:01:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RP-0005gp-If for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RN-0005fT-Fd for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:21 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:39219) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RK-0006MM-9L for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:21 -0500 Received: by mail-pl1-x62c.google.com with SMTP id x18so336833pln.6 for ; Mon, 11 Jan 2021 11:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/F/kqeHksImGvstf5taTsaI7j9+MkxMQkwgzkDOwKP0=; b=DKsuor1vXPGPlQYxFbaQbgeI509RcGrRpvHlU9zKMUE+dyet4PeT7FIpHCD9F5GAJF Uf+r5mGGOfcp1p3oxmBfbd30TNnoaE0QWlkUteBVpfsbiDOQGDftTTGmpdz9GGhm5E4o a1VN/++xo/Z6axdYmGA/rxRj5AuOoeXhxYmRTf2wNOhNvlMUQRWXDmuuQo6pC0P9+OT4 v1j7QViPDcRgODsjUZ10O+27Exb1rinIIA/HI9URDbP+IQ7j0p2S9XobouAHROQoVuvS 1dyPK+jpoqdOGRINqrKCXgnf6BattDrLmx15POgb653X+eF3263vjf7ZWQ1vI2ba/9gC lMFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/F/kqeHksImGvstf5taTsaI7j9+MkxMQkwgzkDOwKP0=; b=d5BupVcRkEMRC3VgKECwnMJ+2XsL75YwIUmJiDUwdXQM2iYBTQwScleTQskTOqHoS6 FZFhKuZki9LV/vPkEcDULfVss4VgQJXJgmGrn/sfajKSCQtcrkr77OZQUd+lkPmTY3e/ ESvgyaqRiY6eYGSPudhLVHtRUOPN6JgtgRQ9c8EMVd0t6+pbBmGe3a+WoRLf4mrCRSaD +bOSC9rhn/uOs2NZBIsLhjZV8RDefKK2anoXx8HINec3hu9P5hrVNkyeMWjFvvq2EVBY FWBgsSgSPbQOSReCNfgjEmmW4VFa6t4ZW4VB7yTeZywWluuLNsorA3DYcKsmEIAAbor9 q3xQ== X-Gm-Message-State: AOAM532KitglD3cWKPDNeRITvCZB3K8IhE+E0rZjv9C/ywSjBRxaLOES 3lkub4H0B8GkSfE9vIdM9EMK0g== X-Google-Smtp-Source: ABdhPJwR6jy8mvrpFHjLBze7Tbegg86o/eoL/c8qNzHb5ZSol1iNmOWLj+FDbZ5jVHYfz+kOp+32Cw== X-Received: by 2002:a17:90b:14d3:: with SMTP id jz19mr298131pjb.196.1610391676277; Mon, 11 Jan 2021 11:01:16 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 00/30] target/arm: enforce alignment Date: Mon, 11 Jan 2021 09:00:43 -1000 Message-Id: <20210111190113.303726-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:22 -0000 As reported in https://bugs.launchpad.net/bugs/1905356 Changes for v3: * Move TBFLAG_{A64,A32,M32,AM32} to tb->cs_base, leaving only TBFLAG_ANY in tb->flags. This solves our current problem of running out of bits in tb->flags. * Dropped "Enforce alignment for sve unpredicated LDR/STR"; there are more changes required for SVE, and I think I'll integrate those into my SVE2 patch set. Changes for v2: * Rearranged things a bit, which has made it easy to support SCTLR.A/CCR.UNALIGN_TRAP. At least for non-sve code, where we issue tcg load/store operations. Predicated sve load/stores will require more work within the helpers. r~ Richard Henderson (30): target/arm: Fix decode of align in VLDST_single target/arm: Rename TBFLAG_A32, SCTLR_B target/arm: Rename TBFLAG_ANY, PSTATE_SS target/arm: Add wrapper macros for accessing tbflags target/arm: Introduce CPUARMTBFlags target/arm: Move mode specific TB flags to tb->cs_base target/arm: Move TBFLAG_AM32 bits to the top target/arm: Move TBFLAG_ANY bits to the bottom target/arm: Add ALIGN_MEM to TBFLAG_ANY target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 target/arm: Fix SCTLR_B test for TCGv_i64 load/store target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness target/arm: Enforce word alignment for LDRD/STRD target/arm: Enforce alignment for LDA/LDAH/STL/STLH target/arm: Enforce alignment for LDM/STM target/arm: Enforce alignment for RFE target/arm: Enforce alignment for SRS target/arm: Enforce alignment for VLDM/VSTM target/arm: Enforce alignment for VLDR/VSTR target/arm: Enforce alignment for VLDn (all lanes) target/arm: Enforce alignment for VLDn/VSTn (multiple) target/arm: Enforce alignment for VLDn/VSTn (single) target/arm: Use finalize_memop for aa64 gpr load/store target/arm: Use finalize_memop for aa64 fpr load/store target/arm: Enforce alignment for aa64 load-acq/store-rel target/arm: Use MemOp for size + endian in aa64 vector ld/st target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) target/arm: Enforce alignment for aa64 vector LDn/STn (single) target/arm: Enforce alignment for sve LD1R target/arm/cpu.h | 105 ++++++++----- target/arm/translate.h | 38 +++++ target/arm/neon-ls.decode | 4 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 160 +++++++++++--------- target/arm/translate-a64.c | 214 +++++++++++++------------- target/arm/translate-sve.c | 2 +- target/arm/translate.c | 258 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 117 ++++++++++++--- target/arm/translate-vfp.c.inc | 20 +-- 10 files changed, 555 insertions(+), 365 deletions(-) -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RR-0005iP-9T for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RP-0005gR-As for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:23 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:44639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RM-0006Mf-5n for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:23 -0500 Received: by mail-pf1-x434.google.com with SMTP id a188so480973pfa.11 for ; Mon, 11 Jan 2021 11:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8XIA/+X37AvNazV2jisISm3ZiIWDvYr5zvekcj4Rlqc=; b=cN938TE5rE+EPWVe+3ynvGY0NH2UDEeH9IIQGdwXBJ6IWOSFjRT1qQdhx758J0QVAg lX9CHNXanximN3zGvU7oCdaeZSgrd+6xOrvByA9PWSH85NzmY52XhIBBshAvin+3M+W1 B1jr7CUGnZkK7A8Qyfk0wPumg+Ah9iLetOZIvV4QJTU7Wo/6anyhJ+E3xCWu5WrLb18e qpQqLfhljYzVX7S7OF9E8zQVvc5WgOMDAO03PPAf3IitkAnBc+BDV1ARjXTYl0gRW5eI Ta+IAB0rii3/I3GKQtKE9B1Ni5kDyWzAQ7Qnbv/ox0lOtPJkmqQmPiYyEuU5GaPMDapH IaDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8XIA/+X37AvNazV2jisISm3ZiIWDvYr5zvekcj4Rlqc=; b=DZMB/RBp9nWWI1yprd0Z9umg+5NyvY77EFWB/6fN0Oszu2S/YljjE6jwdXHNORv7J/ dMljcR6gCDR+eEkebwaEjpl1BYxhDWJ20nqK+1i3lAJDqRk3ayc0f+qpQLPs/wZqgJKM tiiCTgeQlsDGM6tCXMzBPilbXZv83/1Z3OpPkyByeKhwUluHZ1ZXf2+Nk4caF26TYL3Z bhxGUkwUjS5PsfU1OA65cYssXLcJVzGOhk7m6sCcABDi59wmU1YhxeGBVsu69OgAR7mt Ny4EjPTOKhN6xo7QOEolAvqUXQjf6D73I0K12Fzo/pmEtELK1l+Z4CuY4sjlE/4x1k+p s5ng== X-Gm-Message-State: AOAM531fVeS6hvAQPF9uSwQgoJH2RlqkxgAqbBuRyS8BcUpSJDASTV5g 23HCvYyfb4b0wqg08wKfwCa6nA== X-Google-Smtp-Source: ABdhPJy2SsTdEWEhpq6hGb/bnU6XX5ezhtXrC5MgDhJITpgXInM5F8ixNh5LgQB9Raw2rmv5PHgd8g== X-Received: by 2002:a63:5642:: with SMTP id g2mr930203pgm.434.1610391678178; Mon, 11 Jan 2021 11:01:18 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single Date: Mon, 11 Jan 2021 09:00:44 -1000 Message-Id: <20210111190113.303726-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:23 -0000 The encoding of size = 2 and size = 3 had the incorrect decode for align, overlapping the stride field. This error was hidden by what should have been unnecessary masking in translate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/neon-ls.decode | 4 ++-- target/arm/translate-neon.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode index c17f5019e3..0a2a0e15db 100644 --- a/target/arm/neon-ls.decode +++ b/target/arm/neon-ls.decode @@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ vd=%vd_dp size=0 stride=1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \ vd=%vd_dp size=1 stride=%imm1_5_p1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \ vd=%vd_dp size=2 stride=%imm1_6_p1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index f6c68e30ab..0e5828744b 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) switch (nregs) { case 1: if (((a->align & (1 << a->size)) != 0) || - (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { + (a->size == 2 && (a->align == 1 || a->align == 2))) { return false; } break; @@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) } break; case 4: - if ((a->size == 2) && ((a->align & 3) == 3)) { + if (a->size == 2 && a->align == 3) { return false; } break; -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RT-0005mN-JP for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RQ-0005iH-Mb for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:25 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:42003) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RO-0006NO-VT for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:24 -0500 Received: by mail-pl1-x634.google.com with SMTP id s15so327741plr.9 for ; Mon, 11 Jan 2021 11:01:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5o6p1C7v9u1rYVGcSBwWhWoi7b3iNDgzQwEbf6mExPY=; b=ZkjMUq72RsfIIrpUdML+UKLNv5NwNmGxQvCuyAlukFVQ8NpAJWOE5ckZe+teWrTRzn v3fWS6WnVvW/Ov0j9fa5bdD8gm62oCrytk5cKbG8z6pFX+EXgTtNhTDBYObfXYUr1y2H xEFKw79OYrPiCkeejIWm4dwOvP5plL5oE597qssLIl1squKzQFvobY29nVpgnEPLjZW1 h2jjH+oBsef/73LyyxImZZvojQPceexHat+m3dSAWiOjlyxshAaAu7lZCKRe3uVONpEi mBei9Gbr6DIHID7Vkv+s/KpYsTQYCGLe3hliLw2NZSFmxtz2C8UTSN3lDVPSbU1WMv+Z IIHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5o6p1C7v9u1rYVGcSBwWhWoi7b3iNDgzQwEbf6mExPY=; b=nVcIWyIG6U3pmsOZdgIFjQnbjQoRLsXQLLwuH9ekvGpxIPH7lXhS7XiWE+yDd5wBkp EK10VapC2+CsE4bslY+TwoqMddDYke/9Ix8lD9Vxc9Fq2nIJBLcNU26KDYcVDLac74bS ASPdK8QJ/sBYiAgIbJPcMDoPn8oOCESviZ6c8pWIC1OSNm1oGfH39rgyJATYmlxSCsRp Anqb+J0SPBwrSfyQVDXRtRt7ugt6QmHDnJPgvvMpWMonjxA6paC4es7thiwylZ9MXjrF 3O1B4KzznCgPcpHxS5gyDvOzfFPtZ1b8OG3jiovel80q2IM3Jy0PLwe8KmUzN73Q4cGQ JjCw== X-Gm-Message-State: AOAM532XERd9h/ON2RbBydH3pjq+9BkPLCe8xCzXfFiPRQ+dKPWpIK4V T8NKMmYmLbxpnow2qdpNvsBZr15iroGeQA== X-Google-Smtp-Source: ABdhPJyi1/U4qXgPXXUhxMNhe9yJiad7JjSKnvX1Ajzqv+rmfOysc9WkSY1RMR161Wxns+SexO3XkQ== X-Received: by 2002:a17:90a:658c:: with SMTP id k12mr283372pjj.31.1610391681404; Mon, 11 Jan 2021 11:01:21 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Date: Mon, 11 Jan 2021 09:00:46 -1000 Message-Id: <20210111190113.303726-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:25 -0000 We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So PSTATE_SS -> PSTATE__SS in the uses, and document it. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa0bc6e281..89d69cbcd1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3266,7 +3266,7 @@ typedef ARMCPU ArchCPU; */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ FIELD(TBFLAG_ANY, BE_DATA, 28, 1) FIELD(TBFLAG_ANY, MMUIDX, 24, 4) /* Target EL if we take a floating-point-disabled exception */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d70b37adc..7a7e4c3ad4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13094,11 +13094,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && (pstate_for_ss & PSTATE_SS)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); } *pflags = flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ef63edfc68..80a3a5f5fb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14748,7 +14748,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * end the TB */ dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex = false; dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); diff --git a/target/arm/translate.c b/target/arm/translate.c index 460476384c..67d509d29c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8872,7 +8872,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * end the TB */ dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); dc->is_ldex = false; dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK; -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RV-0005ot-4c for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RT-0005mL-IS for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:27 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:39482) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RQ-0006Nn-Kt for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:27 -0500 Received: by mail-pj1-x102c.google.com with SMTP id u4so98584pjn.4 for ; Mon, 11 Jan 2021 11:01:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=De5nYIi0fzT6bB7B3n3IhJbRiZ6qrmEQ5nHTXg1fEtg=; b=tqdtLgPzQQC+G30aO8MPUXdn6qwav7ojNzSCmDVsKi0yO5lERyEyjcIQ3wn237Rs7+ PF2bBQJfdaqtgwkBPKqn1XnSKR4L4zF4cnj+Xvr20f14oxfAsjJcwntEmX/DaiIRlkmE EXJR7Wp0dt6RPGA2B3AtrRhPBdkJpX192xDoz+W0uC4eK1/1HWRKi3thFrVxQzqTtcdF 5vgzk8hPAncebAmgjW+EfwbHjcpFikm53zrhnwpKvV0oDqKmopIMyFQPPXsUbAZaIftV 2A6M3IztNgtzuHi1yQ2OetAGW2KMuSwbv9tGBXlsM50d3XFT7jy18du41dBIW9Jmm0v3 uFTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=De5nYIi0fzT6bB7B3n3IhJbRiZ6qrmEQ5nHTXg1fEtg=; b=nP0qZAM0c72QVhaVvOwuuZtJW0zNT5Ad5bqdE8aXrf1HpdDMc3rK+fLYD1xNYYP2mo PHnahnNZfyWlSvImAYlMmhbr0G8xccOV8F7UyLpJdeX7F5erMDaL05ymrtEKepqLLPt3 m6I2EHOQIulWI3Xl8y53htIfpH+WsTW425vfA5wt1SkUmLUA9lHdWZZF+WHECMtqkwLU M7dY25qx3mP3OanXu1/ToHzBNvEhgBODzI+woxWb7Af0fn6u3ZMnrYWrbDpcyIO5Ig61 ArHnUg8mRW+MqOZMWmjGhdLCF3uI5liwuGxgGTvCRG2/lW0o6OQUO9mUUBGgrDpc3fTr G/Eg== X-Gm-Message-State: AOAM5303MyvncMZ2ts/f1+WjrIFsNCNiafkMQI1GH2O4ywZFhNiqGFsa JRIn4+uFh+IL+PEtNg6lUWijrA== X-Google-Smtp-Source: ABdhPJwfpIadcLVyeay+kp9UJYL1i5JG42hRNdiyji5SUIjYfzBgwc6TFrlGOhou7CG8RK2eVTxYFA== X-Received: by 2002:a17:90a:c82:: with SMTP id v2mr263353pja.171.1610391683111; Mon, 11 Jan 2021 11:01:23 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags Date: Mon, 11 Jan 2021 09:00:47 -1000 Message-Id: <20210111190113.303726-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:27 -0000 We're about to split tbflags into two parts. These macros will ensure that the correct part is used with the correct set of bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 22 +++++++++- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 85 +++++++++++++++++--------------------- target/arm/translate-a64.c | 36 ++++++++-------- target/arm/translate.c | 48 ++++++++++----------- 5 files changed, 101 insertions(+), 92 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d69cbcd1..894266ef02 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3332,6 +3332,26 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) +/* + * Helpers for using the above. + */ +#define DP_TBFLAG_ANY(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) +#define DP_TBFLAG_A64(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) +#define DP_TBFLAG_A32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) +#define DP_TBFLAG_M32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) +#define DP_TBFLAG_AM32(DST, WHICH, VAL) \ + (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) + /** * cpu_mmu_index: * @env: The cpu environment @@ -3342,7 +3362,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) */ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) { - return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); + return EX_TBFLAG_ANY(env->hflags, MMUIDX); } static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 30b2ad119f..7a7a06b3b7 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1039,7 +1039,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * the hflags rebuild, since we can pull the composite TBII field * from there. */ - tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII); + tbii = EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ int core_mmu_idx = cpu_mmu_index(env, false); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a7e4c3ad4..76bb306f26 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12746,12 +12746,11 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, - arm_to_core_mmu_idx(mmu_idx)); + DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); + DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); } return flags; } @@ -12762,12 +12761,12 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, bool sctlr_b = arm_sctlr_b(env); if (sctlr_b) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); + DP_TBFLAG_A32(flags, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } @@ -12778,7 +12777,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, uint32_t flags = 0; if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); + DP_TBFLAG_M32(flags, HANDLER, 1); } /* @@ -12789,7 +12788,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); + DP_TBFLAG_M32(flags, STACKCHECK, 1); } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -12799,8 +12798,7 @@ static uint32_t rebuild_hflags_aprofile(CPUARMState *env) { int flags = 0; - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, - arm_debug_target_el(env)); + DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } @@ -12810,12 +12808,12 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, uint32_t flags = rebuild_hflags_aprofile(env); if (arm_el_is_aa64(env, 1)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); + DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); @@ -12830,14 +12828,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, uint64_t sctlr; int tbii, tbid; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); /* Get control bits for tagged addresses. */ tbid = aa64_va_parameter_tbi(tcr, mmu_idx); tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + DP_TBFLAG_A64(flags, TBII, tbii); + DP_TBFLAG_A64(flags, TBID, tbid); if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el = sve_exception_el(env, el); @@ -12852,14 +12850,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } else { zcr_len = sve_zcr_len_for_el(env, el); } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); + DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); } sctlr = regime_sctlr(env, stage1); if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + DP_TBFLAG_ANY(flags, BE_DATA, 1); } if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { @@ -12870,14 +12868,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * The decision of which action to take is left to a helper. */ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); } } if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + DP_TBFLAG_A64(flags, BT, 1); } } @@ -12889,7 +12887,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: @@ -12899,7 +12897,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * gated by HCR_EL2. == '11', and so is LDTR. */ if (env->cp15.hcr_el2 & HCR_TGE) { - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + DP_TBFLAG_A64(flags, UNPRIV, 1); } break; default: @@ -12917,24 +12915,23 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, * 4) If no Allocation Tag Access, then all accesses are Unchecked. */ if (allocation_tag_access_enabled(env, el, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1); + DP_TBFLAG_A64(flags, ATA, 1); if (tbid && !(env->pstate & PSTATE_TCO) && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { - flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); } } /* And again for unprivileged accesses, if required. */ - if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) + if (EX_TBFLAG_A64(flags, UNPRIV) && tbid && !(env->pstate & PSTATE_TCO) && (sctlr & SCTLR_TCF) && allocation_tag_access_enabled(env, 0, sctlr)) { - flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); } /* Cache TCMA as well as TBI. */ - flags = FIELD_DP32(flags, TBFLAG_A64, TCMA, - aa64_va_parameter_tcma(tcr, mmu_idx)); + DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -13031,10 +13028,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *cs_base = 0; assert_hflags_rebuild_correctly(env); - if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + DP_TBFLAG_A64(flags, BTYPE, env->btype); } pstate_for_ss = env->pstate; } else { @@ -13044,7 +13041,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); } if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && @@ -13056,12 +13053,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * active FP context; we must create a new FP context before * executing any FP insn. */ - flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1); + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); } bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); + DP_TBFLAG_M32(flags, LSPACT, 1); } } else { /* @@ -13069,21 +13066,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * Note that VECLEN+VECSTRIDE are RES0 for M-profile. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); } else { - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, - env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, - env->vfp.vec_stride); + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + DP_TBFLAG_A32(flags, VFPEN, 1); } } - flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits); + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); pstate_for_ss = env->uncached_cpsr; } @@ -13096,9 +13090,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && - (pstate_for_ss & PSTATE_SS)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1); + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (pstate_for_ss & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } *pflags = flags; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 80a3a5f5fb..c260fc573d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14699,28 +14699,28 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx); - dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); - dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); - dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA); + dc->tbii = EX_TBFLAG_A64(tb_flags, TBII); + dc->tbid = EX_TBFLAG_A64(tb_flags, TBID); + dc->tcma = EX_TBFLAG_A64(tb_flags, TCMA); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); - dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); - dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; - dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); - dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); - dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); - dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV); - dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA); - dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); - dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE); + dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); + dc->bt = EX_TBFLAG_A64(tb_flags, BT); + dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); + dc->unpriv = EX_TBFLAG_A64(tb_flags, UNPRIV); + dc->ata = EX_TBFLAG_A64(tb_flags, ATA); + dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); + dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -14747,10 +14747,10 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; - dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); + dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); /* Bound the number of insns to execute to those left on the page. */ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 67d509d29c..87ba22d1b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8811,46 +8811,42 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB); - dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; - condexec = FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC); + dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); + dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; + condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC); dc->condexec_mask = (condexec & 0xf) << 1; dc->condexec_cond = condexec >> 4; - core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; dc->be_data = MO_TE; - dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER); + dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK); - dc->v8m_fpccr_s_wrong = - FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG); + dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK); + dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed = - FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED); - dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT); + EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED); + dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); } else { - dc->be_data = - FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; - dc->debug_target_el = - FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); - dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); - dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); - dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); + dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); + dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); + dc->ns = EX_TBFLAG_A32(tb_flags, NS); + dc->vfp_enabled = EX_TBFLAG_A32(tb_flags, VFPEN); if (arm_feature(env, ARM_FEATURE_XSCALE)) { - dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->c15_cpar = EX_TBFLAG_A32(tb_flags, XSCALE_CPAR); } else { - dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); - dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN); + dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE); } } dc->cp_regs = cpu->cp_regs; @@ -8871,8 +8867,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); - dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS); + dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); + dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK; @@ -9316,11 +9312,11 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; - if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) { + if (EX_TBFLAG_AM32(tb->flags, THUMB)) { ops = &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { + if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) { ops = &aarch64_translator_ops; } #endif -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RW-0005s5-F5 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RU-0005oD-IM for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:28 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51263) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RS-0006OG-Ah for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:28 -0500 Received: by mail-pj1-x102b.google.com with SMTP id y12so102331pji.1 for ; Mon, 11 Jan 2021 11:01:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u3gPsRgSV9emvsK63Aw7U+QzPwKlYGtgQ7T1VzVraGc=; b=tsvogfq8bMSN8rPfJF/PwGWlTD/SgDMoQ36jhWYakN53EEajAbco025MdjTqVPY7+2 wujiCdqqbQcrwmnMvQkKKJ8woILa6Ysc/X5erETzpoeK8W3sLlqe2HbGJyJ0tk0KKWMr eynd8sVT24zn0yItzQ7Hc0Emv51+Rkpfa6vt3UvfbPcz/zIulgvGOT013D7R2rUVxP2X umm2Bcd5NELT9xVgFOPHRGuxmMT8dCPX5IJFkV//dDDmhBkmWTOhpXBZlZa6NKgZpOZE It4fBO2QoUp4TOR16a451D/bdpzd9HA50JZ+tuxPvv5eTsbMlJaiDZOBFUfSGJmSbuCA iDGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3gPsRgSV9emvsK63Aw7U+QzPwKlYGtgQ7T1VzVraGc=; b=C3y8DL5c00YBnwDvQZPW3LELzLCEF+nROVmb23824+6acm76qgrv9mite8tfBVbEIr 5l8Uz2fF81roDvyW/O+ddzEBGKbWSpj2WNJtth8fv4nbXqnNQs6F//IgKfFK2XL3sJR8 H4u9VzRnzJJmkdcYGlG3LkPybeObBAwUL313oQA0g+BFZIRwc8sYo2JnAIBaU0lHZD46 PeDeoui00p5EJ5697VkNOm0SBc3z+o5zBbOOL+MWBKrh9dfmCHvhLF4HNJ4cXkf9SCMW fgPk4DXNKCjb6RI4OVUy7Ap4WqiU0BK+2zVipN5J/cFgbZMuJHP+eSskSG3enga3+Juc aW7g== X-Gm-Message-State: AOAM533tiTuSqJBK7/V3AlUoAp08KEw15UxfstJQGoca7AkcKzAoTFkG O9UVU1eoR2Xvcr7eqEa7MkLm5Q== X-Google-Smtp-Source: ABdhPJzWfjzfYh6nVsorxA6m0aHVwuRGwLyUnxSpmw7rqO78uceHrd5bYJqU5zk14G/yyZUOAZ8dBw== X-Received: by 2002:a17:90a:e64e:: with SMTP id ep14mr276172pjb.5.1610391685019; Mon, 11 Jan 2021 11:01:25 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags Date: Mon, 11 Jan 2021 09:00:48 -1000 Message-Id: <20210111190113.303726-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:28 -0000 In preparation for splitting tb->flags across multiple fields, introduce a structure to hold the value(s). So far this only migrates the one uint32_t and fixes all of the places that require adjustment to match. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 +++++++++++--------- target/arm/translate.h | 11 +++++++++ target/arm/helper.c | 50 +++++++++++++++++++++----------------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 7 +++--- 5 files changed, 59 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 894266ef02..c7700c9c85 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -218,6 +218,10 @@ typedef struct ARMPACKey { } ARMPACKey; #endif +/* See the commentary above the TBFLAG field definitions. */ +typedef struct CPUARMTBFlags { + uint32_t flags; +} CPUARMTBFlags; typedef struct CPUARMState { /* Regs for current mode. */ @@ -246,7 +250,7 @@ typedef struct CPUARMState { uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ /* Cached TBFLAGS state. See below for which bits are included. */ - uint32_t hflags; + CPUARMTBFlags hflags; /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access @@ -3336,21 +3340,21 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) * Helpers for using the above. */ #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL)) + (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) -#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df..f30287e554 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -394,6 +394,17 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); +/** + * arm_tbflags_from_tb: + * @tb: the TranslationBlock + * + * Extract the flag values from @tb. + */ +static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) +{ + return (CPUARMTBFlags){ tb->flags }; +} + /* * Enum for argument to fpstatus_ptr(). */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 76bb306f26..cc73acc927 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12743,8 +12743,9 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif -static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); @@ -12755,8 +12756,9 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } -static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx, uint32_t flags) +static CPUARMTBFlags +rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, CPUARMTBFlags flags) { bool sctlr_b = arm_sctlr_b(env); @@ -12771,10 +12773,10 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = 0; + CPUARMTBFlags flags = {}; if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -12794,18 +12796,19 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +static CPUARMTBFlags +rebuild_hflags_aprofile(CPUARMState *env) { - int flags = 0; + CPUARMTBFlags flags = {}; DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); return flags; } -static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = rebuild_hflags_aprofile(env); if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); @@ -12819,10 +12822,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, - ARMMMUIdx mmu_idx) +static CPUARMTBFlags +rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - uint32_t flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; @@ -12937,7 +12940,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } -static uint32_t rebuild_hflags_internal(CPUARMState *env) +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); @@ -12966,6 +12969,7 @@ void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); } @@ -12986,6 +12990,7 @@ void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); } @@ -13008,12 +13013,12 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) static inline void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG - uint32_t env_flags_current = env->hflags; - uint32_t env_flags_rebuilt = rebuild_hflags_internal(env); + CPUARMTBFlags c = env->hflags; + CPUARMTBFlags r = rebuild_hflags_internal(env); - if (unlikely(env_flags_current != env_flags_rebuilt)) { + if (unlikely(c.flags != r.flags)) { fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", - env_flags_current, env_flags_rebuilt); + c.flags, r.flags); abort(); } #endif @@ -13022,11 +13027,12 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags = env->hflags; + CPUARMTBFlags flags; uint32_t pstate_for_ss; *cs_base = 0; assert_hflags_rebuild_correctly(env); + flags = env->hflags; if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { *pc = env->pc; @@ -13094,7 +13100,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } - *pflags = flags; + *pflags = flags.flags; } #ifdef TARGET_AARCH64 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c260fc573d..010e81e0b4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14685,7 +14685,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = env_archcpu(env); - uint32_t tb_flags = dc->base.tb->flags; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb); int bound, core_mmu_idx; dc->isar = &arm_cpu->isar; diff --git a/target/arm/translate.c b/target/arm/translate.c index 87ba22d1b6..189b2ee3cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8799,7 +8799,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = env_archcpu(env); - uint32_t tb_flags = dc->base.tb->flags; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; dc->isar = &cpu->isar; @@ -9311,12 +9311,13 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) { DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; + CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb); - if (EX_TBFLAG_AM32(tb->flags, THUMB)) { + if (EX_TBFLAG_AM32(tb_flags, THUMB)) { ops = &thumb_translator_ops; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base Date: Mon, 11 Jan 2021 09:00:49 -1000 Message-Id: <20210111190113.303726-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:30 -0000 Now that we have all of the proper macros defined, expanding the CPUARMTBFlags structure and populating the two TB fields is relatively simple. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------ target/arm/translate.h | 2 +- target/arm/helper.c | 2 +- 3 files changed, 30 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7700c9c85..af70462cfa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -221,6 +221,7 @@ typedef struct ARMPACKey { /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { uint32_t flags; + target_ulong flags2; } CPUARMTBFlags; typedef struct CPUARMState { @@ -3251,20 +3252,26 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" /* - * Bit usage in the TB flags field: bit 31 indicates whether we are - * in 32 or 64 bit mode. The meaning of the other bits depends on that. - * We put flags which are shared between 32 and 64 bit mode at the top - * of the word, and flags which apply to only one mode at the bottom. + * We have more than 32-bits worth of state per TB, so we split the data + * between tb->flags and tb->cs_base, which is otherwise unused for ARM. + * We collect these two parts in CPUARMTBFlags where they are named + * flags and flags2 respectively. * - * 31 20 18 14 9 0 - * +--------------+-----+-----+----------+--------------+ - * | | | TBFLAG_A32 | | - * | | +-----+----------+ TBFLAG_AM32 | - * | TBFLAG_ANY | |TBFLAG_M32| | - * | +-----------+----------+--------------| - * | | TBFLAG_A64 | - * +--------------+-------------------------------------+ - * 31 20 0 + * The flags that are shared between all execution modes, TBFLAG_ANY, + * are stored in flags. The flags that are specific to a given mode + * are stores in flags2. Since cs_base is sized on the configured + * address size, flags2 always has 64-bits for A64, and a minimum of + * 32-bits for A32 and M32. + * + * The bits for 32-bit A-profile and M-profile partially overlap: + * + * 18 9 0 + * +----------------+--------------+ + * | TBFLAG_A32 | | + * +-----+----------+ TBFLAG_AM32 | + * | |TBFLAG_M32| | + * +-----+----------+--------------+ + * 14 9 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3342,19 +3349,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) #define DP_TBFLAG_A64(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) #define DP_TBFLAG_A32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) #define DP_TBFLAG_M32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ - (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL)) + (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) -#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH) -#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH) -#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH) -#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH) +#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) +#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) +#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) +#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) /** * cpu_mmu_index: diff --git a/target/arm/translate.h b/target/arm/translate.h index f30287e554..50c2aba066 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); */ static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) { - return (CPUARMTBFlags){ tb->flags }; + return (CPUARMTBFlags){ tb->flags, tb->cs_base }; } /* diff --git a/target/arm/helper.c b/target/arm/helper.c index cc73acc927..0d7c8817b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13030,7 +13030,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, CPUARMTBFlags flags; uint32_t pstate_for_ss; - *cs_base = 0; assert_hflags_rebuild_correctly(env); flags = env->hflags; @@ -13101,6 +13100,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags.flags; + *cs_base = flags.flags2; } #ifdef TARGET_AARCH64 -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RZ-0005y2-DJ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RX-0005up-Tg for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top Date: Mon, 11 Jan 2021 09:00:50 -1000 Message-Id: <20210111190113.303726-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:32 -0000 Now that these bits have been moved out of tb->flags, where TBFLAG_ANY was filling from the top, move AM32 to fill from the top, and A32 and M32 to fill from the bottom. This means fewer changes when adding new bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af70462cfa..43bcd21959 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3265,13 +3265,13 @@ typedef ARMCPU ArchCPU; * * The bits for 32-bit A-profile and M-profile partially overlap: * - * 18 9 0 - * +----------------+--------------+ - * | TBFLAG_A32 | | - * +-----+----------+ TBFLAG_AM32 | - * | |TBFLAG_M32| | - * +-----+----------+--------------+ - * 14 9 0 + * 31 23 11 10 0 + * +-------------+----------+----------------+ + * | | | TBFLAG_A32 | + * | TBFLAG_AM32 | +-----+----------+ + * | | |TBFLAG_M32| + * +-------------+----------------+----------+ + * 31 23 5 4 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3288,44 +3288,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. */ -FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ -FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ +FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ /* * Bit usage when in AArch32 state, for A-profile only. */ -FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) -FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ -FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) +FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ +FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) /* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 17, 1) +FIELD(TBFLAG_A32, NS, 10, 1) /* * Bit usage when in AArch32 state, for M-profile only. */ /* Handler (ie not Thread) mode */ -FIELD(TBFLAG_M32, HANDLER, 9, 1) +FIELD(TBFLAG_M32, HANDLER, 0, 1) /* Whether we should generate stack-limit checks */ -FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +FIELD(TBFLAG_M32, STACKCHECK, 1, 1) /* Set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ /* Set if we must create a new FP context */ -FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* * Bit usage when in AArch64 state -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2Ra-00060w-JZ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RZ-0005yI-Gg for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:33 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:34655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RX-0006QN-M0 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:33 -0500 Received: by mail-pg1-x532.google.com with SMTP id i5so283012pgo.1 for ; Mon, 11 Jan 2021 11:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t7cb1wo+zig4w5wRyfLayVY9BN4eEXg6/tPvYTE+r/M=; b=nXwMW4Q9gwcedvGzBG/JeCMSXLQGMumCuHav6OoSOTfElFgD6ewT5f1YHRN25Fp06M PgwurTbe7eQ/8aTCQxmu8IEB0poaF1rC4fULY4Ye3CYufZBTmOQHe0LkEnAx7CAeVmUh 6UkzPMFZGGq2USV74v77Pe7idqzBCWiuFbohsZELfWq2AFXkJYWZpW551UT6JyYY/+mw CdqAB6KbFt1wPNrmOYpDBiCHfTrzJoBSsBai6jmFYbX7QoNiuobgje+3dJEZola7Lu1g KlnEf4mYr6YbIHAxWzzzLASDrhSQVIICAykV3UeDEubkMnx6xNwdh6KQMonHI8qevHW5 kZAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t7cb1wo+zig4w5wRyfLayVY9BN4eEXg6/tPvYTE+r/M=; b=tiJff+FXm3r8DYbM+dB1ivAUmWO9h0u0JIJxqZU+RzjzWh8GB2zJXitBiXkjwkyfIK ecRxfi+o/E3FOGWhbmj5BO8k31/cHz9LJO9Nn/br4+rzgp8hyFbpmRuukHuZcz3yIzjf YeTCcPloc5OzrOvx1d/2tRlhEVSSpRIhayhCp+dJnYUxkoHBZk0BY37yPMH8UJWwtHVu QCbdm2fYw3p/4PFir9Ug9JbOrnYa72MsejduYW69mXFcdFXor8IEuOa/dtpvLAbQt6DX p5b2dFKy47qW1H7dezYzF67DjEPX/tFUBYRLEZAshkNnPgOgcku3rQW8Wn+Dzo2OiTyU HKyQ== X-Gm-Message-State: AOAM532rrTv9h92Uih4ywOv4UKWpPbkOgf3ZgiDmRBpDIK0IWudLh+Wh lGZD4cDBzrbVoCKtgKSa3huAv0YYBi2iyg== X-Google-Smtp-Source: ABdhPJwRt/Psw0yU185psFnt8lgKOvQmrukRQOvQrtIeDyekmebSqnvnzxACDgs4iux2/eAwnIAWQw== X-Received: by 2002:aa7:8d12:0:b029:1ae:4344:3b4f with SMTP id j18-20020aa78d120000b02901ae43443b4fmr780455pfe.16.1610391690404; Mon, 11 Jan 2021 11:01:30 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Date: Mon, 11 Jan 2021 09:00:51 -1000 Message-Id: <20210111190113.303726-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:33 -0000 Now that other bits have been moved out of tb->flags, there's no point in filling from the top. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 43bcd21959..aa2f2d3a04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3275,15 +3275,15 @@ typedef ARMCPU ArchCPU; * * Unless otherwise noted, these bits are cached in env->hflags. */ -FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) -FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) -FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */ -FIELD(TBFLAG_ANY, BE_DATA, 28, 1) -FIELD(TBFLAG_ANY, MMUIDX, 24, 4) +FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) +FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) +FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ +FIELD(TBFLAG_ANY, BE_DATA, 3, 1) +FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ -FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) +FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) +FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2RT-0005mm-QF for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2RP-0005gN-8I for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:23 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:38361) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RN-0006Mv-7f for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:22 -0500 Received: by mail-pj1-x1035.google.com with SMTP id j13so102637pjz.3 for ; Mon, 11 Jan 2021 11:01:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+W6xF9BlSZ0veTM9KZDcL7jHpIjRPVY9kjtTlwGlZ0M=; b=JxfD0fC1AGe/Scuvi00ucHUFMSFQBMfGuuHGNG9umnt4bKy0EzUM/LSpN9+mFPGvp/ 8jafBDdWC6ijhrPTwJBxFFyJQwM/c9VCotR5fBiW8Bl9VrAwWLtCIOZ75SmxBOIRtmkJ ANXx7OO0A89AouZkmEmD3KnNlJiPzNygtVgKWOfaUqc6Rt/czqdFwpSl7xeUb7cwbtyb merjP1I6RdHXK5sPIpgqb418XhJb7Cwu6nQDhHiiG708MXGEcKuKuW/m1S06FCKAF9pG SNPPgf3O/iRPDDWdlp5WcBBVOuMH0gilQSKqOkirbG7JO9EeDKUebmOiE6uu8mj1K0xx OtPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+W6xF9BlSZ0veTM9KZDcL7jHpIjRPVY9kjtTlwGlZ0M=; b=VMD1pgnv8XYlD6K5UnXbBCgJT6IcN7i4HJxaVyNp2EkJbs+3RMDC+63CttdW+3NB4W eojpvtmTQ1hjfzvyVPQMD2ogIazjgjZka5PbLj3e1Ad9YlOd+yxmG3C7bNM4eeM7lqaS dvArh8zPm7FJSE1vCT0J9khvWjwu4vMIC217lKV6J8WVEfeFJZ2dms8NXt+DNSDxtWJj 4JmbTbgt19YM2Jfv3qYove3K8vl8mqA6mqfAW+Q6wq3ix7UOqhxH/JLMFqbFQIbbFg5+ VDpEe0XjXuZMMqcd7anJsv0JV7dgYt803dHl1f+OR1dq7mHsMU/RWdVHkiU9CvIbgqw5 t7JA== X-Gm-Message-State: AOAM531xy2GCgXJ7ejc+sM3wai3Mfx8DRHb+KNXSu+H0DsvLSRK62rrG JXv+Dos1lrmSOq0fhqjMIzARQA== X-Google-Smtp-Source: ABdhPJxU8/97v+fEY2TZ46UjpQ9sLuy6x8u8YSQH2bu2ivql8FPrBBXAci0PSrPlE0s3AvqkWhAPug== X-Received: by 2002:a17:90a:674c:: with SMTP id c12mr302602pjm.98.1610391679789; Mon, 11 Jan 2021 11:01:19 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Date: Mon, 11 Jan 2021 09:00:45 -1000 Message-Id: <20210111190113.303726-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:23 -0000 We're about to rearrange the macro expansion surrounding tbflags, and this field name will be expanded using the bit definition of the same name, resulting in a token pasting error. So SCTLR_B -> SCTLR__B in the 3 uses, and document it. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..aa0bc6e281 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3293,7 +3293,7 @@ FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ */ FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, SCTLR_B, 15, 1) +FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) /* * Indicates whether cp register reads and writes by guest code should access diff --git a/target/arm/helper.c b/target/arm/helper.c index d077dd9ef5..0d70b37adc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12762,7 +12762,7 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, bool sctlr_b = arm_sctlr_b(env); if (sctlr_b) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1); } if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76..460476384c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8842,7 +8842,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL); - dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B); dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2Rd-00064h-5Y for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rb-00062b-9F for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:35 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:51264) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2RZ-0006Qh-Cy for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:34 -0500 Received: by mail-pj1-x102b.google.com with SMTP id y12so102542pji.1 for ; Mon, 11 Jan 2021 11:01:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Gp5YJhUdu7O2iWG1ZDTCi/OY2TUbd2kY+8E+Hd/FJ4=; b=Hrwh+m3ahWF0A68aHzHCSsJcTJ2MdggXky1MWjQ8UbK/3xzqALsVjPcGEb6ua3AvAB mkEdcSaZFJI8+9YmuHmTtwWz5S55vTvRCH9MfmbMQ7El26sfzx1Gszl2WOItWlokFJkM efliDgDbuiJvMzT/CzUtCMDDTplqzw7Q0Sx1loMVYXRu0lXpZzsQJ28i5jdB9kEzCh3N Ab8GChSy/af0ly3xPFkw6o3AONctV2VgcnQ0kEm3kNxWZBVBk6b7s3z350QVihXBbXrb zUR/TZHkQkc5OIL3M3PF/+YdKl1QtFOHPMe9j6dMQtsnDUP7jOGHIsyRT2pR4KW6Tr9v wEmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Gp5YJhUdu7O2iWG1ZDTCi/OY2TUbd2kY+8E+Hd/FJ4=; b=LvIteszH2Ms2HtrAowSpHCw8C0oxh3iqWmlpjIvo7cD2ThO6DSUxfY8XrNbaAHTTw5 r5/oimS8qa87iPFsdGb++V/wAySJ8++nCgoXl9REMa48XwiqyqTaOD8FarUvJmM+AXlJ umda6/qK3pau7JzrXRHfznr8ponWn+Ch80uXrXT83a0iD6QEd6zbpEDDhLjzVe71Qocj G4DFdC8u0I0hnpsb8S413ZSI102vCDD3qHrhBXnBKT1dVdEKwPmg5uMHp5r8Az/wEeDT Exlm+rsyTsOYna0dU+JhwlR7Qul25UBlvykkfw+yZnGNwXP7VKcuI6eMkoXEOPkvXBgF 9n8g== X-Gm-Message-State: AOAM53159d1dpGkKwdolHL3HQFbRC8KTWVILbSpELzGMQbyw3kgHRPXP ovf9Gjxo/vmdnXo4O9EHl+hMbej817YckQ== X-Google-Smtp-Source: ABdhPJxwk4trQ9IUSW1+XD/ZuaLra9ijGckYYc4rW49vdRJjTnxQ8faaFnli8GO2o522HkTma3hQzg== X-Received: by 2002:a17:90a:d70e:: with SMTP id y14mr288483pju.9.1610391692145; Mon, 11 Jan 2021 11:01:32 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Date: Mon, 11 Jan 2021 09:00:52 -1000 Message-Id: <20210111190113.303726-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:35 -0000 Use this to signal when memory access alignment is required. This value comes from the CCR register for M-profile, and from the SCTLR register for A-profile. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++-- target/arm/translate-a64.c | 1 + target/arm/translate.c | 7 +++---- 5 files changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aa2f2d3a04..4adac2f193 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 4, 4) FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) /* For A-profile only, target EL for debug exceptions. */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) +/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ +FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 50c2aba066..b185c14a03 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -87,6 +87,8 @@ typedef struct DisasContext { bool bt; /* True if any CP15 access is trapped by HSTR_EL2 */ bool hstr_active; + /* True if memory operations require alignment */ + bool align_mem; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d7c8817b6..fc38cc58aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12777,6 +12777,12 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags = {}; + uint32_t ccr = env->v7m.ccr[env->v7m.secure]; + + /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ + if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } if (arm_v7m_is_handler_mode(env)) { DP_TBFLAG_M32(flags, HANDLER, 1); @@ -12789,7 +12795,7 @@ rebuild_hflags_m32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) */ if (arm_feature(env, ARM_FEATURE_V8) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { DP_TBFLAG_M32(flags, STACKCHECK, 1); } @@ -12809,12 +12815,17 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + int el = arm_current_el(env); + + if (arm_sctlr(env, el) & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } if (arm_el_is_aa64(env, 1)) { DP_TBFLAG_A32(flags, VFPEN, 1); } - if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } @@ -12859,6 +12870,10 @@ rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) sctlr = regime_sctlr(env, stage1); + if (sctlr & SCTLR_A) { + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); + } + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { DP_TBFLAG_ANY(flags, BE_DATA, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 010e81e0b4..69d401da21 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14712,6 +14712,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); diff --git a/target/arm/translate.c b/target/arm/translate.c index 189b2ee3cb..3fc058e8d0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -933,8 +933,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -948,8 +947,7 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -8824,6 +8822,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2Ry-0006CW-FW for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rd-00065A-Dc for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:37 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:37369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rb-0006R0-3Y for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:37 -0500 Received: by mail-pj1-x102b.google.com with SMTP id b5so106293pjk.2 for ; Mon, 11 Jan 2021 11:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Date: Mon, 11 Jan 2021 09:00:53 -1000 Message-Id: <20210111190113.303726-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:37 -0000 X-List-Received-Date: Mon, 11 Jan 2021 19:01:37 -0000 Create a finalize_memop function that computes alignment and endianness and returns the final MemOp for the operation. Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32 so that s->be_data is not added by the callers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 24 ++++++++ target/arm/translate.c | 100 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 9 +-- 3 files changed, 79 insertions(+), 54 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index b185c14a03..0c60b83b3d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -459,4 +459,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) return statusptr; } +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Build the complete MemOp for a memory operation, including alignment + * and endianness. + * + * If (op & MO_AMASK) then the operation already contains the required + * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally + * unaligned operation, e.g. for AccType_NORMAL. + * + * In the latter case, there are configuration bits that require alignment, + * and this is applied here. Note that there is no way to indicate that + * no alignment should ever be enforced; this must be handled manually. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + if (s->align_mem && !(opc & MO_AMASK)) { + opc |= MO_ALIGN; + } + return opc | s->be_data; +} + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 3fc058e8d0..8e6f8dd57a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,7 +908,8 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif -/* Abstractions of "generate code to do a guest load/store for +/* + * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero * extended if we're a 64 bit core) and data is also * 32 bits unless specifically doing a 64 bit access. @@ -916,7 +917,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) * that the address argument is TCGv_i32 rather than TCGv. */ -static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { TCGv addr = tcg_temp_new(); tcg_gen_extu_i32_tl(addr, a32); @@ -928,47 +929,51 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) return addr; } +/* + * Internal routines are used for NEON cases where the endianness + * and/or alignment has already been taken into account and manipulated. + */ +static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_ld_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + tcg_gen_qemu_st_i32(val, addr, index, opc); + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; - - if (s->align_mem) { - opc |= MO_ALIGN; - } - - addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i32(val, addr, index, opc); - tcg_temp_free(addr); + gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr; + gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); +} - if (s->align_mem) { - opc |= MO_ALIGN; +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ } - addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_st_i32(val, addr, index, opc); - tcg_temp_free(addr); -} - -#define DO_GEN_LD(SUFF, OPC) \ -static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} - -#define DO_GEN_ST(SUFF, OPC) \ -static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ - TCGv_i32 a32, int index) \ -{ \ - gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) { @@ -6419,7 +6424,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); /* @@ -6440,7 +6445,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); @@ -6463,13 +6468,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt + 1, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6492,13 +6497,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); op_addr_rr_post(s, a, addr, -4); @@ -6563,7 +6568,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); /* @@ -6584,7 +6589,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); tcg_temp_free_i32(tmp); @@ -6600,13 +6605,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); store_reg(s, rt2, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6639,13 +6644,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); tcg_temp_free_i32(tmp); op_addr_ri_post(s, a, addr, -4); @@ -6871,7 +6876,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) addr = load_reg(s, a->rn); tmp = load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); tcg_temp_free_i32(tmp); @@ -7027,7 +7032,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) addr = load_reg(s, a->rn); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); @@ -8211,8 +8216,7 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) addr = load_reg(s, a->rn); tcg_gen_add_i32(addr, addr, tmp); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - half ? MO_UW | s->be_data : MO_UB); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); tcg_temp_free_i32(addr); tcg_gen_add_i32(tmp, tmp, tmp); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 0e5828744b..c82aa1412e 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -559,8 +559,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); if ((vd & 1) && vec_size == 16) { /* * We cannot write 16 bytes at once because the @@ -650,13 +649,11 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) */ for (reg = 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); } vd += a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2Ry-0006Cu-OX for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rj-000662-PK for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:45 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:33110) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rd-0006RQ-4b for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:41 -0500 Received: by mail-pf1-x436.google.com with SMTP id h186so517545pfe.0 for ; Mon, 11 Jan 2021 11:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9xtb+ptQ+2FmtaEsBjHPl225W/jJkhKr+UDtc5NzbLQ=; b=ghTHlB3AKLnw5BwdMC4s99hJGi7DeX9MFTsiDssviiLVkX4UfhFLfxyqRRcm863Il9 a893BR6xkjSrvLIN5YB0th5dSrjNXLbcukzrhRRuhkOCX9qecSYKRfgPBDjPZkDdpjoM Jugs2qBSQpJH3CulZtSwrjRTUTk7Xe1Vpnp8eGTAZaFm/HljV/Ldjjomy+CEulJQv1Zs /8nRGfAFYOygm7mL2euGu40kMgDZhJVLqxJtQEPJD6aqxKmOHFoACNVrXL5CH+UfqYTT y3TYNBZgXJsaj8lgAn9aqLhYdRRfnRkQEqECjza3AE7ieebrN0zu9zSHUD+v51yObhDw Nlfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9xtb+ptQ+2FmtaEsBjHPl225W/jJkhKr+UDtc5NzbLQ=; b=r43pp5nX0tic9uAG/3QBPIMYF1MRgfUjdH+75UrHn8QJ83leIJMrD1DiHhffOLpANu pSf9XUCeJ49APqfGVe/7bFSxO0lAs9qYsHXKX0+KrGFcjAVCaYBoWCU35lnm/Vh3Sxzm N12GfJ3E7fbVnIew5gCOxAg4Jv78mnH7ke5Mi1IF4Y68r2Bn2zMvtNjYlr6xCJtVmw+c x7rCOFyoEMeTGfGcQPzZCfAmUm/mG3FR74TUKMjweh92ikeN7y1EbDMvTM4vs7FkG30E SirsKAvu6AYAROjDaBtIWHTKhF7r57Kx//kEZnzrDC0cTvu+mc+kmoLOKkldwfpQ5KeE YjVw== X-Gm-Message-State: AOAM53371Y29M9kY9HDgKHwqnjydXhuQsvx0rRLsogDhvPfRITRAul6/ w5orCOi1i0hP18LbOPnNgrS+2Q== X-Google-Smtp-Source: ABdhPJwNBr5n3mfEdioyA8LlN161AtvdbM64KxFCEUzpXu3QnRH3mx5w9eWfK66nTYvd0OLIdIdKDw== X-Received: by 2002:aa7:8d86:0:b029:19e:cb57:2849 with SMTP id i6-20020aa78d860000b029019ecb572849mr821632pfr.54.1610391695729; Mon, 11 Jan 2021 11:01:35 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Date: Mon, 11 Jan 2021 09:00:54 -1000 Message-Id: <20210111190113.303726-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:54 -0000 This is the only caller. Adjust some commentary to talk about SCTLR_B instead of the vanishing function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8e6f8dd57a..efcb393b99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) -{ - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { - tcg_gen_rotri_i64(val, val, 32); - } -} - static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); - gen_aa32_frob64(s, val); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); } @@ -4957,16 +4954,13 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); TCGv_i64 t64 = tcg_temp_new_i64(); - /* For AArch32, architecturally the 32-bit word at the lowest + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. That means we don't want to do a - * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if - * for an architecturally 64-bit access, but instead do a - * 64-bit access using MO_BE if appropriate and then split - * the two halves. - * This only makes a difference for BE32 user-mode, where - * frob64() must not flip the two halves of the 64-bit data - * but this code must treat BE32 user-mode like BE32 system. + * gen_aa32_ld_i64(), which checks SCTLR_B as if for an + * architecturally 64-bit access, but instead do a 64-bit access + * using MO_BE if appropriate and then split the two halves. */ TCGv taddr = gen_aa32_addr(s, addr, opc); @@ -5026,14 +5020,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i64 n64 = tcg_temp_new_i64(); t2 = load_reg(s, rt2); - /* For AArch32, architecturally the 32-bit word at the lowest + + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. Since we're going to treat this as a * single 64-bit BE store, we need to put the two halves in the * opposite order for BE to LE, so that they end up in the right - * places. - * We don't want gen_aa32_frob64() because that does the wrong - * thing for BE32 usermode. + * places. We don't want gen_aa32_st_i64, because that checks + * SCTLR_B as if for an architectural 64-bit access. */ if (s->be_data == MO_BE) { tcg_gen_concat_i32_i64(n64, t2, t1); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:01:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2Rz-0006EH-Cb for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:01:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Ru-00066c-E5 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:56 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:37839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rf-0006Rv-PB for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:51 -0500 Received: by mail-pl1-x62c.google.com with SMTP id be12so343022plb.4 for ; Mon, 11 Jan 2021 11:01:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jFhFnE5ZXuq9dWAVT2u9B69HDlRNyiFEVFvSvAG4Tcg=; b=lIpNzQmuxaYXUBXXW6RpE/j7sfGjRVTAZvHZdHCC7EnXk19y2ck/Y/R+9p6XugvIcg 8yOVrjjCNXdfOLTZjk0yE5XXajZ1S3T9spTPEcnvLuqxdsplrtjtci461SB67bBvbmFT TwehNfNHaSA1jyQSy7YxTMZEoLwOi/CMWS8wzCP/CBU51NZ9aRfwhSDpEveLzCTK2x1p cWxaFmco8IQLIX5lvLxG/Qwn/iW1KxUdbJ1vkv8w4RXoVVbVM6jWyumvNWsOGSXAXCit /3+nDqABSGvN0VO7SPFnVDRVfrv/uyc/VIC1d9GYQd0ZBUlgOeYCjKmX3z0yAyyfiyPr snug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jFhFnE5ZXuq9dWAVT2u9B69HDlRNyiFEVFvSvAG4Tcg=; b=jdS0b3tToU25sKaBDi7vcJSy6/Haxl1h1HuKpmclcCbBRDQ6yk5ZlD5jNCH9iORDNH R9OI9dJ+G/H6d56Gu4+reTYIxV3z7Lg8QZRhYYfIewkoHSFm91gCaiALzmAEZpwjbjB3 brM23vmUAsxGdmhQHAhnsvHNS1sAyKRmHTDGm/pBSKeybADeEbP0oSW4T/U4oSyq27Oa Loa+xtC+PRY0nh5MjExTDbDqJEyEnyGK5XP8S+8GX721MB6NiKNSFycsHkfg6qMP+/kw NkqYCOhg3NLIbLYS4WFupxgcsSwLv9K6WO19kATEej5bLa9OiAAU0wb6ReVjgUeMZFHG ZEAQ== X-Gm-Message-State: AOAM530xA1Ho7jN4+RP/mA00/QWQkwk9optvnLZsRytlcKOegrRvaxE/ sfdW64SDIPR1rJDCsAarpmMIXJACUlEhjQ== X-Google-Smtp-Source: ABdhPJyr1BhEZz6uJFQ5aKp2OdGltURHhLFte3ysz1oUB8c+V1E0Ry/uZOftGkxdQCL4Fz3doH3MNg== X-Received: by 2002:a17:90a:8c87:: with SMTP id b7mr313582pjo.158.1610391697398; Mon, 11 Jan 2021 11:01:37 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Date: Mon, 11 Jan 2021 09:00:55 -1000 Message-Id: <20210111190113.303726-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:56 -0000 Just because operating on a TCGv_i64 temporary does not mean that we're performing a 64-bit operation. Restrict the frobbing to actual 64-bit operations. This bug is not currently visible because all current users of these two functions always pass MO_64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index efcb393b99..bf1c0f7279 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, tcg_gen_qemu_ld_i64(val, addr, index, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { tcg_gen_rotri_i64(val, val, 32); } @@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, TCGv addr = gen_aa32_addr(s, a32, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_rotri_i64(tmp, val, 32); tcg_gen_qemu_st_i64(tmp, addr, index, opc); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2S0-0006GB-Mi for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rw-000673-Ch for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:56 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:39483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Ri-0006S9-Qb for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:54 -0500 Received: by mail-pj1-x102c.google.com with SMTP id u4so99108pjn.4 for ; Mon, 11 Jan 2021 11:01:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=er0y9ezqqbyOJmWiO77UDuXh1LDwUXfxwiIw3fI/ARQ=; b=KgM/Euv+WgmtG8KQcHjicOnLhSYY2oZEQ651khGcrNz8NLkDmcEOkIaKAhnpY0xmh8 s1g8lg99YD4cAJxvzVhQqPbIAKmsVtxlBAwYWNgaYBvDRff1FwQEKkyVxuxIn8rn/gBG Kbl989BzuHJcRd5ZmKjNsKw+DRObGiLie+N0b4FOM1Z/8d5lfqQzE7fS4a7PJau8NgbJ LM5i/sw4Xa83h5Amx1VbsmGJR0cyAx5RssUX1r73MjLPtd7nnIFr8fnuJWAPrdZ5ijtk IIfQFkVnuymPMhGPSuDiJTY8ZbxiBhrWsPDhrrZlrBGDXFMXzZb/q7fZTlkqpihBPMoM sHlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=er0y9ezqqbyOJmWiO77UDuXh1LDwUXfxwiIw3fI/ARQ=; b=lXm0cZr4aTNAaK3G7BpwAHSYpILjSN+nLrAFKVOIWrswYLJJ7cqt/rs6+jdJDdDwXT p2lGkiKNiSxVan+geeodBocgMTXkeJXZ7vqkqQD/53cVAZbZtn7cuDY0B4T8+/HdWzuA /65lKJfBwyolg9tXS69dqQYNRTe8fdDxBANWUmhoZXxX9Yk4084eRIQ1aG+XZlP02mT0 cEWLW5AJMhXDuUnsbyKU8SJQIjA0/WdYggm+C+eeoRSGX5XSAkd/MBxgZmXTkDDHmgNS Tq/XFWw0Bsp1RqFFBgS7ui/nSqIk0scMLJmrsaPG8XXCl90QE/FzH1tOQa1RVUdpd9+l ZoTg== X-Gm-Message-State: AOAM531WM0+moKNNNuKALriu0A/kPXxB5U1+oBQ/g3NutPJIS9zLMF/i PCy1vjrh6ejogJSVic3Tt6mi5g== X-Google-Smtp-Source: ABdhPJy6JIRyUtSiXPbEyagIB64u63RztBIgG7NabTtAIzQ9ggDr3e+Qo4pHgtFFpIaFk2IJI5mR2Q== X-Received: by 2002:a17:90a:a10e:: with SMTP id s14mr261105pjp.133.1610391699224; Mon, 11 Jan 2021 11:01:39 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Date: Mon, 11 Jan 2021 09:00:56 -1000 Message-Id: <20210111190113.303726-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:56 -0000 Adjust the interface to match what has been done to the TCGv_i32 load/store functions. This is less obvious, because at present the only user of these functions, trans_VLDST_multiple, also wants to manipulate the endianness to speed up loading multiple bytes. Thus we retain an "internal" interface which is identical to the current gen_aa32_{ld,st}_i64 interface. The "new" interface will gain users as we remove the legacy interfaces, gen_aa32_ld64 and gen_aa32_st64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 +++++++++++++++++++-------------- target/arm/translate-neon.c.inc | 6 ++- 2 files changed, 49 insertions(+), 35 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bf1c0f7279..f75987dac4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, tcg_temp_free(addr); } +static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + tcg_gen_qemu_ld_i64(val, addr, index, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_rotri_i64(tmp, val, 32); + tcg_gen_qemu_st_i64(tmp, addr, index, opc); + tcg_temp_free_i64(tmp); + } else { + tcg_gen_qemu_st_i64(val, addr, index, opc); + } + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { @@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } +static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + +static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + #define DO_GEN_LD(SUFF, OPC) \ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ @@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i64(val, addr, index, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - tcg_gen_rotri_i64(val, val, 32); - } - - tcg_temp_free(addr); -} - static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data); -} - -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_rotri_i64(tmp, val, 32); - tcg_gen_qemu_st_i64(tmp, addr, index, opc); - tcg_temp_free_i64(tmp); - } else { - tcg_gen_qemu_st_i64(val, addr, index, opc); - } - tcg_temp_free(addr); + gen_aa32_ld_i64(s, val, a32, index, MO_Q); } static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); + gen_aa32_st_i64(s, val, a32, index, MO_Q); } DO_GEN_LD(8u, MO_UB) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index c82aa1412e..18d9042130 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); } tcg_gen_add_i32(addr, addr, tmp); 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD Date: Mon, 11 Jan 2021 09:00:57 -1000 Message-Id: <20210111190113.303726-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:56 -0000 Buglink: https://bugs.launchpad.net/qemu/+bug/1905356 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f75987dac4..9cc6a9f83d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6475,13 +6475,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt + 1, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6504,13 +6504,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, a->rt + 1); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); op_addr_rr_post(s, a, addr, -4); @@ -6612,13 +6612,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); store_reg(s, rt2, tmp); /* LDRD w/ base writeback is undefined if the registers overlap. */ @@ -6651,13 +6651,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); tmp = load_reg(s, rt2); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); op_addr_ri_post(s, a, addr, -4); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2S2-0006Lm-LT for mharc-qemu-arm@gnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 20/30] target/arm: Enforce alignment for VLDR/VSTR Date: Mon, 11 Jan 2021 09:01:03 -1000 Message-Id: <20210111190113.303726-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:00 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index f50afb23e7..e20d9c7ba6 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1364,11 +1364,11 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1398,11 +1398,11 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1439,11 +1439,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2S3-0006N2-6K for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S1-0006JE-Q5 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:01 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:43198) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rw-0006Tw-4i for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes) Date: Mon, 11 Jan 2021 09:01:04 -1000 Message-Id: <20210111190113.303726-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:02 -0000 Signed-off-by: Richard Henderson --- v2: Fix alignment for n in {2, 4}. --- target/arm/translate.h | 1 + target/arm/translate.c | 15 +++++++++++++ target/arm/translate-neon.c.inc | 37 +++++++++++++++++++++++++-------- 3 files changed, 44 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 0c60b83b3d..ccf60c96d8 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,7 @@ void arm_test_cc(DisasCompare *cmp, int cc); void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); +MemOp pow2_align(unsigned i); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3057d102f2..8baa465a53 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -908,6 +908,21 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) #define IS_USER_ONLY 0 #endif +MemOp pow2_align(unsigned i) +{ + static const MemOp mop_align[] = { + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, + /* + * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such + * that 256-bit alignment (MO_ALIGN_32) cannot be supported: + * see get_alignment_bits(). Enforce only 128-bit alignment for now. + */ + MO_ALIGN_16 + }; + g_assert(i < ARRAY_SIZE(mop_align)); + return mop_align[i]; +} + /* * Abstractions of "generate code to do a guest load/store for * AArch32", where a vaddr is always 32 bits (and is zero diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 18d9042130..9c2b076027 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -522,6 +522,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) int size = a->size; int nregs = a->n + 1; TCGv_i32 addr, tmp; + MemOp mop, align; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -532,18 +533,33 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) return false; } + align = 0; if (size == 3) { if (nregs != 4 || a->a == 0) { return false; } /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ - size = 2; - } - if (nregs == 1 && a->a == 1 && size == 0) { - return false; - } - if (nregs == 3 && a->a == 1) { - return false; + size = MO_32; + align = MO_ALIGN_16; + } else if (a->a) { + switch (nregs) { + case 1: + if (size == 0) { + return false; + } + align = MO_ALIGN; + break; + case 2: + align = pow2_align(size + 1); + break; + case 3: + return false; + case 4: + align = pow2_align(size + 2); + break; + default: + g_assert_not_reached(); + } } if (!vfp_access_check(s)) { @@ -556,12 +572,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) */ stride = a->t ? 2 : 1; vec_size = nregs == 1 ? stride * 8 : 8; - + mop = size | align; tmp = tcg_temp_new_i32(); addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); if ((vd & 1) && vec_size == 16) { /* * We cannot write 16 bytes at once because the @@ -577,6 +593,9 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) } tcg_gen_addi_i32(addr, addr, 1 << size); vd += stride; + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2S9-0006Qr-7O for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S1-0006J6-LL for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:01 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:40441) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rw-0006T0-5Z for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:01 -0500 Received: by mail-pj1-x102b.google.com with SMTP id m5so95734pjv.5 for ; Mon, 11 Jan 2021 11:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3EgLd6X/0agUdbULg+xeQ+A6feCfdo22IS1O1cQHk+s=; b=W/912atkVSpxgETV5g5kzwGkqmDJ/rSYF0QyMHjRD0ee8kXwfitHLXkATfjMCrK7/f qw7oc8mZ4W7E8qnJy/tAG+oSV9DPrNvznHGeGjSnz+KcnOj0uFnWX96l4J4mb6nJRLnB njQ+f3CzXnlzmSJuDAH4XjOmUtL8bZMYTdWRaCUoKgt+o1xjZQUjFWfrF1MJhpJInA67 miC/Ax/gkMJN2KI3iPAIxvW+B86EjYW9Zf/3zQdfTismeMQU/uLnbZTyBmTzv3Plcvth jsuc1WtpWBIq/J7u3RmPky1O27F1dCXKj2d6veN7aBVEGfV9WgZCsVAfpHJ2jKBlg3h8 Z1xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3EgLd6X/0agUdbULg+xeQ+A6feCfdo22IS1O1cQHk+s=; b=XaoFzLFrrmqLAvkRO8Lq59kCGZdkLVo7iL2fBFZQmsHUwDjnRubMAuTSd6IG6lQD/6 ASiYlfGqhMuqjuRIYVJExoMAmzFVVJ7NM3bguckHVUIBVZAh59cnNe9o1wki9nJ52yKb A7O77VZxc2nz4zyMTjpxVgk5vU+4twZnKjZ1D4GLyO8NMQJZUemI6pWzzf4csWRUj7/n wlUael687dlqblHnMkWK7UUL+LepIOvL0BGy1gS3vnXRVXPoR23ksrGRmD9Ei2tgT+KW iqpj/mOPha32MoJX5mjNi/B7TR4TElRoIPMUMWYG9jrfMeUsPy8SOacSGcwMyj++bIzN kw2w== X-Gm-Message-State: AOAM532MGYI7kcqIrRLuDMm6xd19V5iOAVNoTQDta3rVF2vYzxFqOcUg Wq08PI+q9jVDU/oGly/c2I0SOw== X-Google-Smtp-Source: ABdhPJyWq9mCDaK9z3RNY9hnLtwzlX5O8/z70RXQvNYv8vFwbUPGjqoWOKf98QXA5cjxzj6aUzqf5w== X-Received: by 2002:a17:90b:338d:: with SMTP id ke13mr317770pjb.48.1610391706203; Mon, 11 Jan 2021 11:01:46 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 17/30] target/arm: Enforce alignment for RFE Date: Mon, 11 Jan 2021 09:01:00 -1000 Message-Id: <20210111190113.303726-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:02 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dbe74e2c34..a0d543ec1f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8304,10 +8304,10 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a) /* Load PC into tmp and CPSR into tmp2. */ t1 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t1, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_gen_addi_i32(addr, addr, 4); t2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t2, addr, get_mem_index(s), MO_UL | MO_ALIGN); if (a->w) { /* Base writeback. */ -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2S9-0006RN-DO for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rz-0006DZ-3A for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:59 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:34106) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rs-0006TA-IV for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:58 -0500 Received: by mail-pl1-x62a.google.com with SMTP id t6so355067plq.1 for ; Mon, 11 Jan 2021 11:01:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+VZ34zw/gJ5eF9hiq6PjNGF/Zdf/LyRPrp4QbqxhsNY=; b=UTkxvt+qVNsEy8H580vKPZh1VXl1wdWywnr8powCEkGoe29AC2yEk1/q69xuBFW3GI bnh0eRwEWMGCOppsK5LDYWjMUwIpMR2v4ey9M4L8yD9VPTBYGd5UTC8C4iuZUrWNJFjK RkPfbJO9GoQsqU6QOIaTJdUAqYX5NAR/Aj6pbhOIiump9a1yAZXdFMHpwgqR+pKY0VrG nwR8ESLfRU2vNvSY964iAr7OfPtM4fbIEBelPnUplBSUHBiOj4onzlRwPhau2tZkm1bF YAUdrjV1C4JEo3hc++LZQm1fv1aQZWq7aAwPpGwuQHLkDazyss5C2fYb3sgNeXqmmRvt b8lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+VZ34zw/gJ5eF9hiq6PjNGF/Zdf/LyRPrp4QbqxhsNY=; b=B5il7EmFQEHqx0wbyma0BJkj/ZzV48sbm+wEtZ/x8Y37A2aG66r6b5+fjouR0sS/Gr zDwjMhpiczDH9ZG/BBETIDufYlYDQXoBHx8JRntxJJLfdvNrvhVCJnEy9owGbnP+iQqV rSu845Mt9Dam7ypQmk8Kjj5hgGChCwH0GITtVFGKDdEsoh67SzALWoNHG+XuYWOeQ3fz X89u48c9PolQszoU2f0XMPtE0aJkg/5NvRxgM6XrOvq8RXezal/KnAXq5/BQquo7vyG/ kvrKh4audYudMeSgcdf0XjEhvIX5hu9XLL4gmv7p5L2FoBKoHA74I5QDNyNn6kOU4A8R 1j0A== X-Gm-Message-State: AOAM530mujAo6W/i5b3btKtKyNqGLeDtPKFZjmNaICC6N78cE6Z0KAY6 sEv2LpxqXzj1bgxD0WJG7yk6qg== X-Google-Smtp-Source: ABdhPJyk6GCakzYN06H9LtDcfp+0yaaTC1IVVbQkJ0+5kVWi87mego8Rzdu7E7rr4zbdSv3QWPxB5w== X-Received: by 2002:a17:90a:eacf:: with SMTP id ev15mr309212pjb.174.1610391707934; Mon, 11 Jan 2021 11:01:47 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 18/30] target/arm: Enforce alignment for SRS Date: Mon, 11 Jan 2021 09:01:01 -1000 Message-Id: <20210111190113.303726-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:59 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a0d543ec1f..3057d102f2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5170,11 +5170,11 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tmp = load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SI-0006VI-0E for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S3-0006NV-L8 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:04 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:36573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rx-0006VD-VW for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:03 -0500 Received: by mail-pf1-x431.google.com with SMTP id t22so505274pfl.3 for ; Mon, 11 Jan 2021 11:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZxTe0vrdv36w4KUhkfdQi48uXdXMfkmKMdEHX8Xoc08=; b=aNNkL5kpHsitk+eokZ5wfjXV25BmxKQCerYTYVQndR6s82frYIutzN3vtQHwxsoJpI t91Hh74HJXBBn8kguYjZ8G78BeFJy9vl0HEXUJ6i61VRwUvhXSm6zlYp13gGkRDMEw0d aND7xadZR00v+WNIZRecqTLNOU+yMpLZ3kTrvJHjq4WM07oJ2wtR96rgR03VU85Y5AkS HWFVbEVtwdh5S1+1+bL3j7S6tV7mTS5MkISjRSPEpv5Q5S94pehbjFdOZUo8E47+q9fs MTAMkGY4U+NvDcEIoQ14LvJ/rHqRpOetS17CnD03IrUAZMi/KUMTvc64DduYIR6kQ6TK 8/8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZxTe0vrdv36w4KUhkfdQi48uXdXMfkmKMdEHX8Xoc08=; b=LBjzqs4SJ4CrKLhKqVpjCfonf5S7mF2M4D+bZOxSYZMd7GEcJu8wAgtBQi+ug5RSEz MW/wUJBz/ZW2o8RVTHJAsACGojjglv1fcjSuQaqmFSSdesNEToaPaDEVALB3HF174P4w myDA5Eip568OlokQHoEu4DK3jwwMCD5OLfQFbNqfNt4DBU7FeHJhXhqUdM5Dkw+CScVv U2UpW/M7LHEnAO/hBtsSZXf3Z5sOmjb0Ov+gw9/+rNLb6ngAHzyRmDxXrY25IneBuinJ SJiTra/Leu64QnnseVgtoHfaFOKjgKZjOkdooAaS0vJD6i9C7hwWtCXJ2XYMwEJFqIII X2Jw== X-Gm-Message-State: AOAM532OXIYeutnhaQ5RYhE5l8ESJ5yWkw/I2/8E32pmZ5vkMgtZZ6l5 q5XTKIXFO4sd614TlvFtbKbhSQ== X-Google-Smtp-Source: ABdhPJyjkCCVTiJ52SczjCei7M3fKRowvz84I2+lZkkEbr/CXo8TP8ecqxxlbtEpsQZpPfWcYSL79Q== X-Received: by 2002:a62:7857:0:b029:19d:fe6a:3069 with SMTP id t84-20020a6278570000b029019dfe6a3069mr805550pfc.3.1610391716595; Mon, 11 Jan 2021 11:01:56 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Date: Mon, 11 Jan 2021 09:01:06 -1000 Message-Id: <20210111190113.303726-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:04 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 48 ++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index e706c37c80..a02b8369a1 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -629,6 +629,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) int nregs = a->n + 1; int vd = a->vd; TCGv_i32 addr, tmp; + MemOp mop; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -678,23 +679,58 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) return true; } + /* Pick up SCTLR settings */ + mop = finalize_memop(s, a->size); + + if (a->align) { + MemOp align_op; + + switch (nregs) { + case 1: + /* For VLD1, use natural alignment. */ + align_op = MO_ALIGN; + break; + case 2: + /* For VLD2, use double alignment. */ + align_op = pow2_align(a->size + 1); + break; + case 4: + if (a->size == MO_32) { + /* + * For VLD4.32, align = 1 is double alignment, align = 2 is + * quad alignment; align = 3 is rejected above. + */ + align_op = pow2_align(a->size + a->align); + } else { + /* For VLD4.8 and VLD.16, we want quad alignment. */ + align_op = pow2_align(a->size + 2); + } + break; + default: + /* For VLD3, the alignment field is zero and rejected above. */ + g_assert_not_reached(); + } + + mop = (mop & ~MO_AMASK) | align_op; + } + tmp = tcg_temp_new_i32(); addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); - /* - * TODO: if we implemented alignment exceptions, we should check - * addr against the alignment encoded in a->align here. - */ + for (reg = 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_ld_internal_i32(s, tmp, addr, get_mem_index(s), mop); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size); + gen_aa32_st_internal_i32(s, tmp, addr, get_mem_index(s), mop); } vd += a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } tcg_temp_free_i32(addr); tcg_temp_free_i32(tmp); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SJ-0006WS-6z for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2SB-0006Sg-DA for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:02:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Date: Mon, 11 Jan 2021 09:01:11 -1000 Message-Id: <20210111190113.303726-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:13 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 296cd430ab..7765c15e0c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3606,7 +3606,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) bool is_postidx = extract32(insn, 23, 1); bool is_q = extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; - MemOp endian = s->be_data; + MemOp endian, align, mop; int total; /* total bytes */ int elements; /* elements per vector */ @@ -3674,6 +3674,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) } /* For our purposes, bytes are always little-endian. */ + endian = s->be_data; if (size == 0) { endian = MO_LE; } @@ -3692,11 +3693,17 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ + align = MO_ALIGN; if (selem == 1 && endian == MO_LE) { + align = pow2_align(size); size = 3; } - elements = (is_q ? 16 : 8) >> size; + if (!s->align_mem) { + align = 0; + } + mop = endian | size | align; + elements = (is_q ? 16 : 8) >> size; tcg_ebytes = tcg_const_i64(1 << size); for (r = 0; r < rpt; r++) { int e; @@ -3705,9 +3712,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) for (xs = 0; xs < selem; xs++) { int tt = (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size | endian); + do_vec_st(s, tt, e, clean_addr, mop); } else { - do_vec_ld(s, tt, e, clean_addr, size | endian); + do_vec_ld(s, tt, e, clean_addr, mop); } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SJ-0006X7-Cj for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2SF-0006Tx-Gj for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:16 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:41299) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2S5-0006Xc-6m for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:15 -0500 Received: by mail-pf1-x433.google.com with SMTP id q20so490262pfu.8 for ; Mon, 11 Jan 2021 11:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mcXjxlPWR8jTh0X8knptdL/K1lbgLUw3V3hljuNtlzU=; b=OH62gf8sUx9GXYA4RfAtUsMcj/cmC3IkrfbUG0YhYv0v75VIngnAw38uOzWnyMB3IH aF6+g2m7jh7vXfvuUJVIgUJcGrXtCYRQGZ5ow2CA83oE6QS1A9J3on5A5+84Qoisbfnf QB5cPIxfgYSkIMQjj6FDmIaD2pZ+JuybseO64bqIuoXtndr6xT0S0AL9UTd1F0wEYpYV 3dFshtAjYC4j0ZSAQFeaISJzmaIBE3Jy/mmC9mF5dk71Tca5YWl8CAEFzhT849Ozfryk W0Kb5iOCk7/Gn9KaqgOgwmhXXqtcbHIf6bv0XoAfpzY3wSKFJsG+LwYuCIsE2p4AIGlZ C2Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mcXjxlPWR8jTh0X8knptdL/K1lbgLUw3V3hljuNtlzU=; b=NCR1O7Xc04MQze4FI6B1Yr2SIhfCAi77qX0jW8+VfYHjCiZnlv+k6zX9xQkLsUO+eL ZrzOcelpJjYP2UV65G/5Z5wEBazEdsPj0bNJnuZ5JxHDgoplSXvqBoXnIyXCxFMwHXM8 3c38Qc99T4lmYqRQtf4ccOfNxhyzVfALFoqGPRh8LXF82xyhfb4QOoJSczw4EDUTxm/K syAbCxFkEtQpQ6pjpjVxuH/e7OBUNkJgHY5SUeP/iipNPZjb6PDVFGiOG77gWk5y+InC 7eFDmsMXhONjVe2Je2H6L4/T24g/1wThZ2uE3JVBIhMaDENTsxga9VkJsD8WMBcktfwE OQUA== X-Gm-Message-State: AOAM531c8y0/av9lCkSOUA6iAkdYCE/XXjaz1ar2ehAUU4nub0J1cRhP hHZ0LHelWYINAijV2dp1r7nr1w== X-Google-Smtp-Source: ABdhPJxQ+qJxvZkFs5mZNYKwgetBzkq9feJ+KlQ+X+Njkf3Yu58UCvy2QDheGvnkjVNm1aBJznTOXw== X-Received: by 2002:a65:6249:: with SMTP id q9mr967283pgv.82.1610391723980; Mon, 11 Jan 2021 11:02:03 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:02:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Date: Mon, 11 Jan 2021 09:01:10 -1000 Message-Id: <20210111190113.303726-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:16 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7f37f8bb12..296cd430ab 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1140,24 +1140,24 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - read_vec_element(s, tcg_tmp, srcidx, element, size); - tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); + read_vec_element(s, tcg_tmp, srcidx, element, mop & MO_SIZE); + tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); tcg_temp_free_i64(tcg_tmp); } /* Load from memory to vector register */ static void do_vec_ld(DisasContext *s, int destidx, int element, - TCGv_i64 tcg_addr, int size, MemOp endian) + TCGv_i64 tcg_addr, MemOp mop) { TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size); - write_vec_element(s, tcg_tmp, destidx, element, size); + tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); + write_vec_element(s, tcg_tmp, destidx, element, mop & MO_SIZE); tcg_temp_free_i64(tcg_tmp); } @@ -3705,9 +3705,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) for (xs = 0; xs < selem; xs++) { int tt = (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, clean_addr, size, endian); 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 16/30] target/arm: Enforce alignment for LDM/STM Date: Mon, 11 Jan 2021 09:00:59 -1000 Message-Id: <20210111190113.303726-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:01 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ba68d4d7f4..dbe74e2c34 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7831,7 +7831,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) } else { tmp = load_reg(s, i); } - gen_aa32_st32(s, tmp, addr, mem_idx); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); /* No need to add after the last transfer. */ @@ -7906,7 +7906,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) } tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, mem_idx); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { tmp2 = tcg_const_i32(i); gen_helper_set_user_reg(cpu_env, tmp2, tmp); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SM-0006fM-P2 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S7-0006QF-Fy for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:08 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:47090) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2S3-0006X2-F3 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:07 -0500 Received: by mail-pl1-x62a.google.com with SMTP id v3so315575plz.13 for ; Mon, 11 Jan 2021 11:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lAlv71XV4SKUNxt7geYws+zgzPBGM/IzIZrTaZWAMU4=; b=q2uySl2J4wtk/YcI7vLoMM8s8/yTn1lxkCvT9/kIfY6w2RDzxyue/Y0l1k+SpuzBUg KE9R2TnDn6yNJXxXOphsVG6Dj62wyIJ5X27Gzn5McmevJCQ5obhMPElX7+v+rgU/V26t hQ5Eb9OL4gkCZAfXU4uIvcXuuOAB9aw6OKWIlNFfGUSrafwk9M27Iu52ogZVQsSA5lJr PK9JBxoLlJ8iMu0IDI3d4BR/WpLThJKr1VbjgsDoNGYtijulhWrTVIjH3lVyf7/aaNL+ KFGe3m1Z62L9hPXK2SLKXbCcFYeWgkYHLCjPicBqrBXtnXteIjGJ8Aq5NAVFGjQ8K4TE UP2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lAlv71XV4SKUNxt7geYws+zgzPBGM/IzIZrTaZWAMU4=; b=EyWnuugRj2IrAItoq0cr7a/6Vh42BN7tPGtDlSrdMqlnKO2Rivj5MsCEB/rrdFU/Gy kUHOCpE+pGBmcqgcPn+5+DTfOu5m1ZVeGc61a2e9ZaK4E30v+EfwXo4xRzKL3gfjgh8w U0c65LU1Ict1JoypwEucSfz6PDLxvv3A8/f/Ifr4gOd2KBTEQ9qSskArZXDpmcbLC8Pv M/E1HgeqqH+ef9Z4fDhlxb1vVEDq3kqo7ObUgeTR+a8WiR6lwwwShzFsPAh79LX4w9MG xhym1g94zPpCRgPKBxbVBUMBEGPtsgChNi54ktgoh3O1qbMJ4GA8uuPcxi0BVZDVX5PA W+vQ== X-Gm-Message-State: AOAM533+EbpK/EPwBFUPB8MT8THwfX0vbIHSk2kT5C5xWAGn6x4ReLw3 Kw+nGbV5lUhYjOeo3MPRdHPIzw== X-Google-Smtp-Source: ABdhPJyAEtmlNFJSNcp01/AfGlPsYQP4DnV84Vbsktk7x/wxfhzS8Fe54o01HbfsYw7WAlpBi9zyLw== X-Received: by 2002:a17:902:ee02:b029:db:c0d6:57f9 with SMTP id z2-20020a170902ee02b02900dbc0d657f9mr1132017plb.65.1610391722178; Mon, 11 Jan 2021 11:02:02 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:02:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Date: Mon, 11 Jan 2021 09:01:09 -1000 Message-Id: <20210111190113.303726-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:09 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9255763ea7..7f37f8bb12 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2669,7 +2669,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, size); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2686,8 +2687,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, true, + rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3476,15 +3478,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) int size = extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; bool is_store = false; - bool is_signed = false; bool extend = false; bool iss_sf; + MemOp mop; if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + mop = size | MO_ALIGN; + switch (opc) { case 0: /* STLURB */ is_store = true; @@ -3496,21 +3501,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - is_signed = true; + mop |= MO_SIGN; break; case 3: /* LDAPURS* 32-bit variant */ if (size > 1) { unallocated_encoding(s); return; } - is_signed = true; + mop |= MO_SIGN; extend = true; /* zero-extend 32->64 after signed load */ break; default: g_assert_not_reached(); } - iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); + iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc); if (rn == 31) { gen_check_sp_alignment(s); @@ -3523,13 +3528,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) if (is_store) { /* Store-Release semantics */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.02.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:02:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 30/30] target/arm: Enforce alignment for sve LD1R Date: Mon, 11 Jan 2021 09:01:13 -1000 Message-Id: <20210111190113.303726-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:19 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0c3a6d2121..6125e734af 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5011,7 +5011,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) clean_addr = gen_mte_check1(s, temp, false, true, msz); tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - s->be_data | dtype_mop[a->dtype]); + finalize_memop(s, dtype_mop[a->dtype])); /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SN-0006j2-Ty for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2Rx-00069e-8E for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:57 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:41997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rj-0006ST-Og for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:01:57 -0500 Received: by mail-pl1-x62c.google.com with SMTP id s15so328287plr.9 for ; Mon, 11 Jan 2021 11:01:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4n1qdCl4BSNX+je6zlGPHDmT7d0/KM39fnJLGgL3o+g=; b=vZ52RXzvCu8qZKS3gNUC0ZhUVPiUGm1kQvwfR0adFZP12XhQ8sF4v2bX24OhwJsaa9 vMouhEHvs8Dzu1ysfuOU+iLwetQ43Z1Jmg75i+YlFsABxntnV6xabFYxSg+zCJjtAe6E IYnhx3jkXldfZ9YNMbmwF15mOGFgE7G0aZJF/81yEQZX66pu2E5geBMooG3fWfagu+WU cmqcobp+P8w5u4N9dW1QSLdXG2eWV2mgs+FIY98KfAng3x3iCU70IgVymygS7EG9x36l jvUr6+ElJy3FlfLqJmv+c+Fq99wF5cumyGj8ZtotpbDeQoZ3T7dWtJpiT7EIifk4nLSO 8I2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4n1qdCl4BSNX+je6zlGPHDmT7d0/KM39fnJLGgL3o+g=; b=IVuL5tBKmT1VR16ihwxllETOleJfZl8tqDKC6gjP3Uvb9QK+KuFu1hAl5nfelX2lNj /USVM2sBxn63sYgq5fRn8ymgAgP/LbuN2wJxtMVdbChZFW/P2C+nW2I9IY6a0pCE/j9J wbQVMtQfkAEuz7+tBOXaU34597LlYCg/YoGE+45y23ccsKJFxL+ydN7kE1pnXEhCITn+ zOlfyRqg6Z2qG3wj/SvemOfCOYw4uT45rW0KR4NyvJ8+LsBliBdjKN3x+2orLtcy+cRZ Y+Y9V9UnYD64+Zh2C05MlrHrfSXE+qYc+51u3QtXTsKwVcSmRMunMvsQ3Ywck8aham6I V4Aw== X-Gm-Message-State: AOAM530mD3BWWo0/d9hH4mHZT/IGuI8rkTpBWRUKEU39t3JEDryILKEb BCDmOLmJC3mg4QhSLRnj62Bkug== X-Google-Smtp-Source: ABdhPJyY6Rvj+Pk9FcDJexDPFwu+QrFcHIn4SN9FKlvl/aRum1i+vVx1eTmKkIWUI9UpwsVj4o7bDw== X-Received: by 2002:a17:90a:1057:: with SMTP id y23mr268737pjd.97.1610391702604; Mon, 11 Jan 2021 11:01:42 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Date: Mon, 11 Jan 2021 09:00:58 -1000 Message-Id: <20210111190113.303726-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:01:57 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cc6a9f83d..ba68d4d7f4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6883,7 +6883,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) addr = load_reg(s, a->rn); tmp = load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); tcg_temp_free_i32(tmp); @@ -7039,7 +7039,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) addr = load_reg(s, a->rn); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); tcg_temp_free_i32(addr); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SO-0006lK-Kb for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S2-0006MD-Rx for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:02 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:51273) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Ru-0006TO-3w for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:02 -0500 Received: by mail-pj1-x1034.google.com with SMTP id y12so103008pji.1 for ; Mon, 11 Jan 2021 11:01:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KALA1eSooGUfBo7CGQXBooa38v23DHVbjR3um2cG8+w=; b=yTYN5j5PV/Sn4apB7FQIwW7cOCtXtWz/RYzpgF/tzc61sWSU1ZFFYfjuSBFHLGwYBi koHarkKTbwK0cNa1oZDWdP1AWuaTvLvNGz3pWlBle0IxnS1vuxq6erpm5gBI2vVXbFSL VgDDtnKZbxs5nFq7bdo6Zc4Tdw7XcfnTVQAxfmubReyxeWCA3HAcWBzM66lUbXbyKYgS 56DIMIdri+7gNlwc+k9ABCcGT3Dpp89fGfD+szgglAm0FTE1uLyj00sWJxcMQ6nF/Q0b Q5P5bXdlUuS3ldxBy0Erst7kTmlR4ioDxJglPj2mopMKN7PQcrDGLvjUakBlmq+ZwlyV Hy0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KALA1eSooGUfBo7CGQXBooa38v23DHVbjR3um2cG8+w=; b=S2mGaWbNnGrF9aFB9IydQ7no6/ED40+aM+aBjjzaSz31FTcD0qugO3QjyN4CxbI6GL XDglrIGfPAe2padDCdWV9qlNNbQv0LDSONXFMrxiKQitmoUc/ztxQfZfi67xt0lMEqb4 H9+GPfKCe5FkAroqy22zxIm3kBPb0oLw13iA7YTiQpuwhb2Ei6CRAHlw9TLKX9xC99Rc e3ad6qMzDTZhXudNxnariAGSlmgWTCNrH3NcjFj2oBIzBplKs0uhglyATKWAQlGgYZAg wlOql1JzToBAwoie2KK1ayKw3PvPYyMvZoz6L4bnYXXls2qsX9a3u7aEMAk+jQnF5uBj ZO1Q== X-Gm-Message-State: AOAM533NjQFr1AhSSja2T6MgEY39ik+edjdAZJ3AcTlpcBWals5ijpSL MLRvz71TrcWT+vDzVnF5sHmsqw== X-Google-Smtp-Source: ABdhPJykhtsQdq5zrfLQwZBgccYT6grNv/tgb7cBtRZunOVB1KVJqa0RcBBrf+CNl7L4UcPKmiR6Iw== X-Received: by 2002:a17:90a:674c:: with SMTP id c12mr304733pjm.98.1610391709680; Mon, 11 Jan 2021 11:01:49 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 19/30] target/arm: Enforce alignment for VLDM/VSTM Date: Mon, 11 Jan 2021 09:01:02 -1000 Message-Id: <20210111190113.303726-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:03 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 10766f210c..f50afb23e7 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1503,12 +1503,12 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); vfp_store_reg32(tmp, a->vd + i); } else { /* store */ vfp_load_reg32(tmp, a->vd + i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } tcg_gen_addi_i32(addr, addr, offset); } @@ -1586,12 +1586,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4); } tcg_gen_addi_i32(addr, addr, offset); } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SO-0006m1-RE for mharc-qemu-arm@gnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Date: Mon, 11 Jan 2021 09:01:05 -1000 Message-Id: <20210111190113.303726-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:04 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 9c2b076027..e706c37c80 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -429,7 +429,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) { /* Neon load/store multiple structures */ int nregs, interleave, spacing, reg, n; - MemOp endian = s->be_data; + MemOp mop, align, endian; int mmu_idx = get_mem_index(s); int size = a->size; TCGv_i64 tmp64; @@ -473,20 +473,36 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) } /* For our purposes, bytes are always little-endian. */ + endian = s->be_data; if (size == 0) { endian = MO_LE; } + + /* Enforce alignment requested by the instruction */ + if (a->align) { + align = pow2_align(a->align + 2); /* 4 ** a->align */ + } else { + align = s->align_mem ? MO_ALIGN : 0; + } + /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ if (interleave == 1 && endian == MO_LE) { + /* Retain any natural alignment. */ + if (align == MO_ALIGN) { + align = pow2_align(size); + } size = 3; } + tmp64 = tcg_temp_new_i64(); addr = tcg_temp_new_i32(); tmp = tcg_const_i32(1 << size); load_reg_var(s, addr, a->rn); + + mop = endian | size | align; for (reg = 0; reg < nregs; reg++) { for (n = 0; n < 8 >> size; n++) { int xs; @@ -494,15 +510,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, - endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); } tcg_gen_add_i32(addr, addr, tmp); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } } } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SP-0006o3-I5 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S4-0006OM-Sn for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:05 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:44443) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2Rz-0006Vn-TM for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:04 -0500 Received: by mail-pl1-x631.google.com with SMTP id r4so322255pls.11 for ; Mon, 11 Jan 2021 11:01:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JO2WcIYwslNZr+KcGb+B6wNh5fkUzsQjVxh2FB2A4YQ=; b=CysioAwzI1YOBXgBK0uPZr2POaWjV7SWKpmHV9AtW70gdpNt5kdBmNOAH3XiAWbCl5 jwYBp335qiTLGyK71p2GsE6+KHfgjVCU/ikxAOEXViumX6dxvZoIeFdw/VAuei2rQEQV J7h12+lbzloip4gdv8Ugp010N5kr6tyqyAEvDJbKTDKCX9FjfKvPN1Kpy/0s3aPmDx0P BdZo8RoswXrSPHyOwZtNinQHXBUmF6GuS/qJNzzdDWgGMfLnSct+G/GzVNQ8Hg9mxAiQ 1ibgNvpyV4JTzacYtpVj0kUrSxFVxvEGiQp4A0nnimzcMC9I1iJcdSOkQMvIDN6/HwAW tUZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JO2WcIYwslNZr+KcGb+B6wNh5fkUzsQjVxh2FB2A4YQ=; b=gk733pRPIfYyQs3qI8ImfjR8tvin6j4+62J0X28DL0yV1ZIBmxF7hOKob2UrrqGdQ2 U5dE8QMp2TXamFwiitSaMZ1V53HlQvB2CKtNe+ZqiynqjUNAokO4O+0SINY/erfEiOFn B7KH21ri1s6qRY9eEVOoeg4djkBv9CwlPYHUvLuOTHM7cHwmWBSSatLFiXnERd9fZRrX VjmpyrziN+X6wFNzFKl5lOo7DWq0zKnGsfcbpNOPKdN0BtXSgCQfQDRf4f1WCKkjXTOK gkoowaZl76K3FCxCVgqz+bNpRDaF2wIApYOtFG/XZKyyKXkd8+q5FDTODPwj7/wJq85F /Ijw== X-Gm-Message-State: AOAM530whICop8bviJtXpe3cBovHDCxthhd3H3yEpnLNM7+ft50RF69W LzdcDzb93m6zR42PTTLlfrG3aQ== X-Google-Smtp-Source: ABdhPJw0y1gMXF8NmKjPNXfjJQuHug6yw8/zLVqVTOQ1eC0/s6lnKmodFrtUdlssd6pQ0KtNvr1Jkw== X-Received: by 2002:a17:902:8c85:b029:dc:2f27:c684 with SMTP id t5-20020a1709028c85b02900dc2f27c684mr1180231plo.44.1610391718381; Mon, 11 Jan 2021 11:01:58 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Date: Mon, 11 Jan 2021 09:01:07 -1000 Message-Id: <20210111190113.303726-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:05 -0000 In the case of gpr load, merge the size and is_signed arguments; otherwise, simply convert size to memop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 78 ++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 45 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 69d401da21..5d93fcf25b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -880,19 +880,19 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) * Store from GPR register to memory. */ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, int memidx, + TCGv_i64 tcg_addr, MemOp memop, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - g_assert(size <= 3); - tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); + memop = finalize_memop(s, memop); + tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); if (iss_valid) { uint32_t syn; syn = syn_data_abort_with_iss(0, - size, + (memop & MO_SIZE), false, iss_srt, iss_sf, @@ -903,37 +903,28 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, } static void do_gpr_st(DisasContext *s, TCGv_i64 source, - TCGv_i64 tcg_addr, int size, + TCGv_i64 tcg_addr, MemOp memop, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), + do_gpr_st_memidx(s, source, tcg_addr, memop, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } /* * Load from memory to GPR register */ -static void do_gpr_ld_memidx(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, - bool extend, int memidx, +static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, + MemOp memop, bool extend, int memidx, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - MemOp memop = s->be_data + size; - - g_assert(size <= 3); - - if (is_signed) { - memop += MO_SIGN; - } - + memop = finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); - if (extend && is_signed) { - g_assert(size < 3); + if (extend && (memop & MO_SIGN)) { + g_assert((memop & MO_SIZE) <= MO_32); tcg_gen_ext32u_i64(dest, dest); } @@ -941,8 +932,8 @@ static void do_gpr_ld_memidx(DisasContext *s, uint32_t syn; syn = syn_data_abort_with_iss(0, - size, - is_signed, + (memop & MO_SIZE), + (memop & MO_SIGN) != 0, iss_srt, iss_sf, iss_ar, @@ -951,14 +942,12 @@ static void do_gpr_ld_memidx(DisasContext *s, } } -static void do_gpr_ld(DisasContext *s, - TCGv_i64 dest, TCGv_i64 tcg_addr, - int size, bool is_signed, bool extend, +static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, + MemOp memop, bool extend, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, - get_mem_index(s), + do_gpr_ld_memidx(s, dest, tcg_addr, memop, extend, get_mem_index(s), iss_valid, iss_srt, iss_sf, iss_ar); } @@ -2687,7 +2676,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn != 31, size); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2800,8 +2789,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf = opc != 0; - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + false, true, rt, iss_sf, false); } tcg_temp_free_i64(clean_addr); } @@ -2960,11 +2949,11 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) /* Do not modify tcg_rt before recognizing any exception * from the second load. */ - do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, - false, 0, false, false); + do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, + false, false, 0, false, false); tcg_gen_mov_i64(tcg_rt, tmp); tcg_temp_free_i64(tmp); @@ -3095,8 +3084,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, - is_signed, is_extended, memidx, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, memidx, iss_valid, rt, iss_sf, false); } } @@ -3200,9 +3189,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, - is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3285,8 +3273,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, - true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + is_extended, true, rt, iss_sf, false); } } } @@ -3373,7 +3361,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, * full load-acquire (we only need "load-acquire processor consistent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3446,7 +3434,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, is_wback || rn != 31, size); tcg_rt = cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, + do_gpr_ld(s, tcg_rt, clean_addr, size, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); @@ -3531,8 +3519,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) * Load-AcquirePC semantics; we implement as the slightly more * restrictive Load-Acquire. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, - true, rt, iss_sf, true); + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN, + extend, true, rt, iss_sf, true); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SP-0006oi-PP for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2S5-0006OT-5c for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:01:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Date: Mon, 11 Jan 2021 09:01:08 -1000 Message-Id: <20210111190113.303726-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:05 -0000 For 128-bit load/store, use 16-byte alignment. This requires that we perform the two operations in the correct order so that we generate the alignment fault before modifying memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 42 +++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5d93fcf25b..9255763ea7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -957,25 +957,33 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + TCGv_i64 tmplo = tcg_temp_new_i64(); + MemOp mop; + + tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + if (size < 4) { - tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), - s->be_data + size); + mop = finalize_memop(s, size); + tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be = s->be_data == MO_BE; TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); + TCGv_i64 tmphi = tcg_temp_new_i64(); + tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + + mop = s->be_data | MO_Q; + tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), - s->be_data | MO_Q); - tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); - tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), - s->be_data | MO_Q); + tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); + tcg_temp_free_i64(tcg_hiaddr); + tcg_temp_free_i64(tmphi); } - tcg_temp_free_i64(tmp); + tcg_temp_free_i64(tmplo); } /* @@ -986,10 +994,11 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo = tcg_temp_new_i64(); TCGv_i64 tmphi = NULL; + MemOp mop; if (size < 4) { - MemOp memop = s->be_data + size; - tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); + mop = finalize_memop(s, size); + tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { bool be = s->be_data == MO_BE; TCGv_i64 tcg_hiaddr; @@ -997,11 +1006,12 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) tmphi = tcg_temp_new_i64(); tcg_hiaddr = tcg_temp_new_i64(); + mop = s->be_data | MO_Q; + tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), + mop | (s->align_mem ? MO_ALIGN_16 : 0)); tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), - s->be_data | MO_Q); - tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), - s->be_data | MO_Q); + tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, + get_mem_index(s), mop); tcg_temp_free_i64(tcg_hiaddr); } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:02:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2SQ-0006pU-0J for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:02:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2SF-0006Th-5s for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:16 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:33833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz2S8-0006YU-Sx for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:02:14 -0500 Received: by mail-pj1-x1036.google.com with SMTP id n3so335059pjm.1 for ; Mon, 11 Jan 2021 11:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6T/o1lhn6aSUmH+RBGXbRyAbXaPSiwSZ8/GJte4+zxA=; b=veqUcAfEKkOdgtGBmuxzfqqRywgKTkPGA58D/I4uIREHkWRTNhXWIbQdVsaYk7Weso BTI5skZEBoGn6csTSbu4mPIDOoODq5MlKNpz+HNSh+aZWXcGXHjK86pCUXTyILN2dVoG d854M+WbOVXI0QIoeJi+9ns8uFNrH1akYRqTKX32cY+N0g9h4QuHwecHT7iOpn7ulc70 hUrcdVm3m44YH0yK+FYUVwmHcKuk4LcEfxQbsf1TPhbxPqEguzwBTXGC7FWzyt/6YEAs MBiQPYY+G367ZDMGeosMICT/xKDIwv+4sOfUK9trWKHspzcCLoSnGTmdiQWcC5acCUzd 06OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6T/o1lhn6aSUmH+RBGXbRyAbXaPSiwSZ8/GJte4+zxA=; b=uO4u86xaHNuEghQ2cXEGJxttozEdB/77USK81FBZE7HqKZ7eDquzAarRiZXNGRlYrR aWIdmfCs+FR18Z8U3UyW+odgWN7pCX4qq28cnuutzKVa4pXseEYk9FKXvJA4uEScojcD 2Ta/IGD8P+tIyjlkdIyEYm68oT2yHzyD78VI7ZKvl3xZdmeQF+jcdq40MiS/gYEk5fSc vzIpu4NctocfXgsgjEtLCSVM7T7BMQ30pUUtcMCocX0KPu2VitnJPUwad94yPldcsoaQ LA3ELioD58FQYFAUZFcAQA8vgVdZm0bFEEqc7L2ykzFld35Qrouf8rlV2vqtdjDI29hp 7sbg== X-Gm-Message-State: AOAM5303aPY+2ogYVKgoS6Nws0GvkPEMnT5m98xaJMN0p+Vfiv3AyXFR yDkF7Qa3qSvmZks1cYwhyt4TZtOAnVBm7w== X-Google-Smtp-Source: ABdhPJzxjOFqnwtZKkTHgisAQ1bQ24qktjgMkz05EFN4qGckejJs4QDefyIS5bV1Vd1kEXCGSp9DdQ== X-Received: by 2002:a17:90a:e64e:: with SMTP id ep14mr279189pjb.5.1610391727352; Mon, 11 Jan 2021 11:02:07 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id n195sm350395pfd.169.2021.01.11.11.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 11:02:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Date: Mon, 11 Jan 2021 09:01:12 -1000 Message-Id: <20210111190113.303726-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org> References: <20210111190113.303726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:02:16 -0000 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7765c15e0c..ec8e488b11 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3786,6 +3786,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) int index = is_q << 3 | S << 2 | size; int xs, total; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; if (extract32(insn, 31, 1)) { unallocated_encoding(s); @@ -3847,6 +3848,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31, scale, total); + mop = finalize_memop(s, scale); tcg_ebytes = tcg_const_i64(1 << scale); for (xs = 0; xs < selem; xs++) { @@ -3854,8 +3856,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) /* Load and replicate to all elements */ TCGv_i64 tcg_tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, - get_mem_index(s), s->be_data + scale); + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), tcg_tmp); @@ -3863,9 +3864,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, clean_addr, scale | s->be_data); + do_vec_ld(s, rt, index, clean_addr, mop); } else { - do_vec_st(s, rt, index, clean_addr, scale | s->be_data); + do_vec_st(s, rt, index, clean_addr, mop); } } tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); -- 2.25.1 From MAILER-DAEMON Mon Jan 11 14:23:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2nF-000061-SU for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:23:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2f4-00020h-EK for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:15:32 -0500 Received: from mout3.freenet.de ([2001:748:100:40::2:5]:52356) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1kz2ev-0008Ma-Nl for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:15:26 -0500 Received: from [195.4.92.127] (helo=sub8.freenet.de) by mout3.freenet.de with esmtpa (ID andschlick@freenet.de) (port 25) (Exim 4.92 #3) id 1kz2en-0005ID-S9 for qemu-arm@nongnu.org; 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Mon, 11 Jan 2021 20:15:13 +0100 X-Abuse: 000000 / 84.149.233.20 X-Originated-At: 84.149.233.20!1234 User-Agent: freenet-api2 MIME-Version: 1 Date: Mon, 11 Jan 2021 19:15:13 GMT Message-Id: <71df6296a8a7133097d6e0eda7168a2a@api.mail.freenet.de> Content-Type: multipart/alternative; boundary="------------000706050306000208060103" X-Priority: 3 Subject: qemu-system-aarch64 error From: andschlick@freenet.de Reply-To: andschlick@freenet.de To: qemu-arm@nongnu.org X-FNSign: v=2 s=2D0C065C46E01C2E7A70251AC7006BF19577A31FBEBFFBEBA2A6162051B632B8 X-Scan-TS: Mon, 11 Jan 2021 20:15:13 +0100 Received-SPF: pass client-ip=2001:748:100:40::2:5; envelope-from=andschlick@freenet.de; helo=mout3.freenet.de X-Spam_score_int: 7 X-Spam_score: 0.7 X-Spam_bar: / X-Spam_report: (0.7 / 5.0 requ) BAYES_00=-1.9, BOGUS_MIME_VERSION=3.499, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 11 Jan 2021 14:23:57 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:15:37 -0000 --------------000706050306000208060103 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8; format=flowed Hello,=0A I installed qemu on a windows 10 laptop an= d wanted to start and install opensuse aarch64 version under qemu-system-ar= ch64.de and I get the following error message.=0AC: \ qemu \ qemu-system-aa= rch64.exe: No machine specified, and there is no default Use -machine help = to list supported machines Is it no longer possible to use aarch64?=0Agreet= ings=0AAndreas =0A=0A=0A --------------000706050306000208060103 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Hello,

=0A

I installed qemu on a win= dows 10 laptop and wanted to start and install opensuse aarch64 version und= er qemu-system-arch64.de and I get the following error message.

=0A

C: \ qemu \ qemu-system-aa= rch64.exe: No machine specified, and there is no default Use -machine help to list supp= orted machines Is it no longer possible to use aarch64?

=0A

greetings

=0A

Andreas



=0A --------------000706050306000208060103-- From MAILER-DAEMON Mon Jan 11 14:24:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz2no-0000iw-0h for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 14:24:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz2ng-0000gS-19 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:24:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:36271) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kz2nb-00019J-WD for qemu-arm@nongnu.org; Mon, 11 Jan 2021 14:24:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610393044; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r2mxFIi3v4zgPeSdBudHxaoU/iLZxzphoG7C1sMttQQ=; b=VRO3gcU+3EjMN1e3BT41SCf4rDZKC9oRRsA/76JTbmM2P5zgvlKMqxWfmETF+oMFc8kXzD jx0k+tA5EaOKkBO1sUsaN1LWxgqnIzg+K5LGH9VvJKR15/Jf6hb9USnSM/00AnpKmFEC8p fEfy3Cl3cLz06aBvtw31TKIx4h7aYo8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-304-N8Z_Ud21OaqTBB9j-nxZVQ-1; Mon, 11 Jan 2021 14:24:01 -0500 X-MC-Unique: N8Z_Ud21OaqTBB9j-nxZVQ-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 17D02AFA83; Mon, 11 Jan 2021 19:23:59 +0000 (UTC) Received: from localhost (unknown [10.40.208.23]) by smtp.corp.redhat.com (Postfix) with ESMTP id 48F6B60854; Mon, 11 Jan 2021 19:23:48 +0000 (UTC) Date: Mon, 11 Jan 2021 20:23:47 +0100 From: Igor Mammedov To: Marian Posteuca Cc: Peter Maydell , Eduardo Habkost , Sergio Lopez , "Michael S. Tsirkin" , Ben Warren , Richard Henderson , qemu-devel@nongnu.org, Dongjiu Geng , Shannon Zhao , Xiang Zheng , qemu-arm@nongnu.org, Paolo Bonzini , Xiao Guangrong Subject: Re: [PATCH v3] acpi: Permit OEM ID and OEM table ID fields to be changed Message-ID: <20210111202347.41b65fd5@redhat.com> In-Reply-To: <87bldvldsl.fsf@mutex.one> References: <20201230221302.26800-1-posteuca@mutex.one> <20210106182430.6bf1823a@redhat.com> <87bldvldsl.fsf@mutex.one> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 19:24:26 -0000 On Mon, 11 Jan 2021 16:59:54 +0200 Marian Posteuca wrote: > Igor Mammedov writes: > > > overall looks good. > > Please add a test case for it, see > > tests/qtest/bios-tables-test.c for description how to do it > > an/or at > > "[PATCH v3 08/12] tests/acpi: allow updates for expected data files" > > and follow up patches on the list. > When you say add a test case, do you mean only updating the binary > files in tests/data/acpi/{microvm,pc,q35,virt} according to the steps > at the start of the file bios-tables-test.c? Or do you also mean an actual > test case to be added in bios-tables-test.c? an new test in bios-tables-test.c, which will test that new option works as expected. > Also the step 6 described in bios-tables-test.c mentions that the diff of > the ACPI table must be added to the commit log, but my change touches > all the tables for all architectures so that would mean that I would > have to create a huge commit log. How should I approach this? I don't think that large commit message is problem, it helps reviewer to see expected changes (if|before one actually tests) From MAILER-DAEMON Mon Jan 11 16:24:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz4gJ-0000Vf-9B for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 16:24:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz4gE-0000VT-N9 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 16:24:50 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:44464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz4gD-0000Fr-35 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 16:24:50 -0500 Received: by mail-ej1-x630.google.com with SMTP id w1so403407ejf.11 for ; Mon, 11 Jan 2021 13:24:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NDeCplexsmi2i9OtFBCI+zVOd3728SvyLhwvRHptbVs=; b=saqHMcnw0ZgaHoigAWBhLGGPgFn7ZNoJRuHgDi9P1ltfB9MGG/d4AFttyYWVq1L2cY 4ZrsFoFOcxWJRCq3J4bDOAxwAA2ev03wJrZSOZ3NXNSe8B9SgoUTMoMVY7CDMeer3lw/ Six4Ve1ejXa9pWH4T07iNJzdT7bBm0Q0xolIgba+Gv/Q+NZRqzTRmbA7qozdxp/Wmt3W raWYCjfcX5GbWEPXDo4CNaPCI9MDX86wO8q0xuJeF22CFqiMO4AuRRCiqZZ9Ftw1GmpV YoeeSTKe/r3jwvXjm/OVPJC4qYKVbXGsRAzZvpL6GnzhSXnS0UJZNp7lgzHcs+SvDW4X d/KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NDeCplexsmi2i9OtFBCI+zVOd3728SvyLhwvRHptbVs=; b=ckV7PAyPDRSzsCoCuDo5XQxZ1ctxzQH1WX7q2y15LxfJq9aGbCZ9+pdaVZftKmVObC uV0HvHjoiHhaF5NZRUQ1Y22h+BXCQ0TqkhlHNfVLjbLoUC01bduDwukfOj3CvAgqt41d 4dovKst+VVtzffdYQzg8yE4CpT0jp9zwenI69RwHdAw6gTWHG+5tzzXcl1OFJzE46GfM NVupaR8AsPmpvM5496Fa+1cgD4oNrNXstDOD1sfwaId2s/sOAk9FjbCnafksN0En0Iue aK/xeC2kux57yQW45vlvWO13ryACP895HfApRlMX9cU9WFYybCaOiEUbIRJlx9gUbbG3 +OwQ== X-Gm-Message-State: AOAM532Tgrqw7CPB1YzJwslXhbImQa88F4bwB/Wb4HaZ8PQOrncbW4O2 H1AoT6GZeCQAUlei/4Xg79rSfFk3hFIk1MLuVO/a9Q== X-Google-Smtp-Source: ABdhPJztFVwlGnEyK3CwdJla4iIR9Jde1PD6OLAvIPxVEOJn6EDcJStMNrBndfg6VTNrUhnFLfmU9Va8Mb0dUp6w6F0= X-Received: by 2002:a17:906:1151:: with SMTP id i17mr979239eja.250.1610400287148; Mon, 11 Jan 2021 13:24:47 -0800 (PST) MIME-Version: 1.0 References: <71df6296a8a7133097d6e0eda7168a2a@api.mail.freenet.de> In-Reply-To: <71df6296a8a7133097d6e0eda7168a2a@api.mail.freenet.de> From: Peter Maydell Date: Mon, 11 Jan 2021 21:24:35 +0000 Message-ID: Subject: Re: qemu-system-aarch64 error To: andschlick@freenet.de Cc: qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 21:24:50 -0000 On Mon, 11 Jan 2021 at 19:50, wrote: > I installed qemu on a windows 10 laptop and wanted to start and install opensuse aarch64 version under qemu-system-arch64.de and I get the following error message. > > C: \ qemu \ qemu-system-aarch64.exe: No machine specified, and there is no default > Use -machine help to list supported machines Is it no longer possible to use aarch64? The message tells you what the problem is: you did not specify a machine type to emulate. You need to do that, because (unlike x86-64) there is no default machine type which QEMU will choose if you don't tell it which machine you meant. You can specify a machine type with the -machine option. "-machine help" will give you your choices. Probably you want 'virt': see the guidance at https://www.qemu.org/docs/master/system/target-arm.html#choosing-a-board-model Note that you *cannot* simply pass QEMU, eg, a distro CDROM image via the -cdrom option and expect to boot from it on anything really other than the x86 PC machine type. For AArch64 you will want to find a tutorial on how to boot a Linux distro on the virt board, because that's easier than trying to figure out how to do it from scratch. (You have two choices -- pass QEMU a UEFI bios image, which can then boot a CDROM, or pass QEMU a Linux kernel image file and initrd directly: decide which you want to do and pick a tutorial accordingly.) thanks -- PMM From MAILER-DAEMON Mon Jan 11 18:11:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz6LH-0004d9-EZ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:11:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz6LF-0004bH-Ep for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:17 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41172) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz6LC-0006Bx-24 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:17 -0500 Received: by mail-pg1-x530.google.com with SMTP id i7so153837pgc.8 for ; Mon, 11 Jan 2021 15:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UWP41LldK9nkC6LBfZA8LR7R7rGfju6ns2oORRKgk08=; b=FSLNrW1Kgta0djg85U/FyKXbFjN1eJBZqUBL/OF2GFGzjnuXsw5ttqXM+yYZhEJ3d3 zb402Nl1fh/heIol+wy3iYvHc+4lWzBIlIC6Kq17zIiTJX2s+7381D+ZXreD6SK/t0AO 7cBRQBt2tV/1k+72kUItZjpfvlvzfdx2rW8vNJYwCCQ/WFNK8+T1641q5TY2Q9BoeXxw P9a7pj5dR+MKBSoOlrgDU4UKCK9+xyTQmN5LcT/8nmuzILBs9fBHVWbCj/keKuevNn65 yHGW23UHlrGLnFIyHRBwDvTim4p8LdjVGJfpjpXZFtWub6vUC9UbceOuljwqopx5mh5s U43w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UWP41LldK9nkC6LBfZA8LR7R7rGfju6ns2oORRKgk08=; b=WT8BZgoXQKUm7tP5q/ZrO2GUwss1uLWMOi5ufJMHK11CZx3JM1b/6HDgJpnUkUs+Z1 2k1UrQ2weY0+ZwNuAJEQ5w+6XgMM4YkLSmQ3ksj/IZNhyOBK/3qMLTaN/ouzgKoG9MTj q+TeautD0sY2TnkuC8BIKZ65dYTDdHTOuCuJ4bWgD3gPfilUl99Eg3EfhP8ZT2luulHj SoLLIoAHYlx4w1EkFDwn0op+FjoQqz22nmLzA3NncNoxMHI3X/BmmQFo+zXtGIyzHqj9 4+3l+NNGPreazKUZXbsnVi3ebAlAnSCfTRAJLyj3/7jUjiCLw6YYB11hy3ZzN06GZp21 oCxA== X-Gm-Message-State: AOAM531sPXlae0D1kusuMhWV6FNzZ0oN1mgzl7TIxeOZKJU41GwsM//i bq2cmgLedzMyM+kyyf3oA9kdMw== X-Google-Smtp-Source: ABdhPJxIRsqbXDFSJDKQmpRLY43U3h1Njkr9CiB/YLGW0P88DE+Aw4X0hPZksuvGdToTvkD6MBJ7Dg== X-Received: by 2002:a63:4e44:: with SMTP id o4mr1774714pgl.46.1610406671500; Mon, 11 Jan 2021 15:11:11 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm658105pfb.196.2021.01.11.15.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:11:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v6 0/3] target/arm: Implement an IMPDEF pauth algorithm Date: Mon, 11 Jan 2021 13:11:05 -1000 Message-Id: <20210111231108.461088-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:11:17 -0000 The architected pauth algorithm is quite slow without hardware support, and boot times for kernels that enable use of the feature have been significantly impacted. Version 6 changes: * Rearrange xxhash64 (pmm). * Add documentation (pmm). r~ Richard Henderson (3): target/arm: Implement an IMPDEF pauth algorithm target/arm: Add cpu properties to control pauth target/arm: Use object_property_add_bool for "sve" property docs/system/arm/cpu-features.rst | 21 +++++++ include/qemu/xxhash.h | 98 ++++++++++++++++++++++++++++++++ target/arm/cpu.h | 25 ++++++-- target/arm/cpu.c | 13 +++++ target/arm/cpu64.c | 64 +++++++++++++++------ target/arm/monitor.c | 3 +- target/arm/pauth_helper.c | 27 +++++++-- tests/qtest/arm-cpu-features.c | 13 +++++ 8 files changed, 236 insertions(+), 28 deletions(-) -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:11:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz6LJ-0004fA-MG for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:11:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz6LH-0004dS-JF for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:20 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:45158) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz6LE-0006C6-9r for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:19 -0500 Received: by mail-pg1-x52a.google.com with SMTP id v19so141746pgj.12 for ; Mon, 11 Jan 2021 15:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMumzk4fm+ReubqkvThPEU9TX17+RjW08bNhr8jJ4Ok=; b=VCrGfXHdYTeywmvh5VGW2sEx6OlZELG+v45spTTE/O3ULFc0t2XrzIG8G9ePgrDfZb o+NXuANfJ/Tweh8fuFCt+FOIIbVHlUm2I6gjGL8nV8+pVFSEqULhqzHAJQjJS0/p7hj0 PWreKt/TrbLSfdDzD0bDVWuQi+cX2ATNwMitHCJ2FwRDF99NBgIKVSVIAQ+20908WdBB pn1Pw33uxzfNZDTQR6Z/qRreb6uzdiaGKthDWKYktS+9lbvayz7lMUZSp9rkDjBjnSu8 B+Uxzd8LyQ8bM0cHq7IjbMfAK2JV2d/uh5Nvi0C42FcpppbX9Qry23Ee0KMcB7QLVsRm Li4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMumzk4fm+ReubqkvThPEU9TX17+RjW08bNhr8jJ4Ok=; b=OIdKzeuc9ELIcCdCJJQNvxSaXFt2YdGNV5N5bt9ckDXJcy6m/ZP7V+TPjFuZmkRIHq 2MIPLHAQg7EOmHLKFR9CIYlgudkiOiYxcvaCvche4TEDdOBC/MhW9VkaQ5nAgwIKPTuF j+xqhp1qBSLioN7GKPCQy+zJ0nmRr4mxHYcHhFJdB2xkk+ymdz0uAg+KCFefwrJZ0+Z5 68kx5kH1s5Voeu26UrEfmr1urgg70Zyvr7S3kdglTY/5WQWWhphGIAmbk9JYtwVStOqh lvvX59VBKH9MTA34fBpiKbZtMHSJWEKTRlY2WW0ltCoX582Es+go/KIZdqd4cWQZp+9j Vjzg== X-Gm-Message-State: AOAM530gIyMdY9YrZeKQwf+MBYbtCwc78yN6LabeWb17aQSvopmHYPy4 LFtqp7a5nRqygIS1tTw2QOeN1dVqsYRIaQ== X-Google-Smtp-Source: ABdhPJz1scyzdw/c4TI6y6To5NxUfkxKa1wd+wsCIV2vifecWBWrrVGqaKkfzwLG82wDdeU92JJ4ZA== X-Received: by 2002:a63:1110:: with SMTP id g16mr1698073pgl.357.1610406673397; Mon, 11 Jan 2021 15:11:13 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm658105pfb.196.2021.01.11.15.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:11:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Mark Rutland Subject: [PATCH v6 1/3] target/arm: Implement an IMPDEF pauth algorithm Date: Mon, 11 Jan 2021 13:11:06 -1000 Message-Id: <20210111231108.461088-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111231108.461088-1-richard.henderson@linaro.org> References: <20210111231108.461088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:11:20 -0000 Without hardware acceleration, a cryptographically strong algorithm is too expensive for pauth_computepac. Even with hardware accel, we are not currently expecting to link the linux-user binaries to any crypto libraries, and doing so would generally make the --static build fail. So choose XXH64 as a reasonably quick and decent hash. Tested-by: Mark Rutland Signed-off-by: Richard Henderson --- v2: Move the XXH64 bits to xxhash.h (ajb). Create isar_feature_aa64_pauth_arch and fixup a comment in isar_feature_aa64_pauth that no longer applies. v6: Introduce qemu_xxhash64_4 (pmm). --- include/qemu/xxhash.h | 98 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 15 ++++-- target/arm/pauth_helper.c | 27 +++++++++-- 3 files changed, 131 insertions(+), 9 deletions(-) diff --git a/include/qemu/xxhash.h b/include/qemu/xxhash.h index 076f1f6054..c2dcccadbf 100644 --- a/include/qemu/xxhash.h +++ b/include/qemu/xxhash.h @@ -119,4 +119,102 @@ static inline uint32_t qemu_xxhash6(uint64_t ab, uint64_t cd, uint32_t e, return qemu_xxhash7(ab, cd, e, f, 0); } +/* + * Component parts of the XXH64 algorithm from + * https://github.com/Cyan4973/xxHash/blob/v0.8.0/xxhash.h + * + * The complete algorithm looks like + * + * i = 0; + * if (len >= 32) { + * v1 = seed + XXH_PRIME64_1 + XXH_PRIME64_2; + * v2 = seed + XXH_PRIME64_2; + * v3 = seed + 0; + * v4 = seed - XXH_PRIME64_1; + * do { + * v1 = XXH64_round(v1, get64bits(input + i)); + * v2 = XXH64_round(v2, get64bits(input + i + 8)); + * v3 = XXH64_round(v3, get64bits(input + i + 16)); + * v4 = XXH64_round(v4, get64bits(input + i + 24)); + * } while ((i += 32) <= len); + * h64 = XXH64_mergerounds(v1, v2, v3, v4); + * } else { + * h64 = seed + XXH_PRIME64_5; + * } + * h64 += len; + * + * for (; i + 8 <= len; i += 8) { + * h64 ^= XXH64_round(0, get64bits(input + i)); + * h64 = rol64(h64, 27) * XXH_PRIME64_1 + XXH_PRIME64_4; + * } + * for (; i + 4 <= len; i += 4) { + * h64 ^= get32bits(input + i) * PRIME64_1; + * h64 = rol64(h64, 23) * XXH_PRIME64_2 + XXH_PRIME64_3; + * } + * for (; i < len; i += 1) { + * h64 ^= get8bits(input + i) * XXH_PRIME64_5; + * h64 = rol64(h64, 11) * XXH_PRIME64_1; + * } + * + * return XXH64_avalanche(h64) + * + * Exposing the pieces instead allows for simplified usage when + * the length is a known constant and the inputs are in registers. + */ +#define XXH_PRIME64_1 0x9E3779B185EBCA87ULL +#define XXH_PRIME64_2 0xC2B2AE3D27D4EB4FULL +#define XXH_PRIME64_3 0x165667B19E3779F9ULL +#define XXH_PRIME64_4 0x85EBCA77C2B2AE63ULL +#define XXH_PRIME64_5 0x27D4EB2F165667C5ULL + +static inline uint64_t XXH64_round(uint64_t acc, uint64_t input) +{ + return rol64(acc + input * XXH_PRIME64_2, 31) * XXH_PRIME64_1; +} + +static inline uint64_t XXH64_mergeround(uint64_t acc, uint64_t val) +{ + return (acc ^ XXH64_round(0, val)) * XXH_PRIME64_1 + XXH_PRIME64_4; +} + +static inline uint64_t XXH64_mergerounds(uint64_t v1, uint64_t v2, + uint64_t v3, uint64_t v4) +{ + uint64_t h64; + + h64 = rol64(v1, 1) + rol64(v2, 7) + rol64(v3, 12) + rol64(v4, 18); + h64 = XXH64_mergeround(h64, v1); + h64 = XXH64_mergeround(h64, v2); + h64 = XXH64_mergeround(h64, v3); + h64 = XXH64_mergeround(h64, v4); + + return h64; +} + +static inline uint64_t XXH64_avalanche(uint64_t h64) +{ + h64 ^= h64 >> 33; + h64 *= XXH_PRIME64_2; + h64 ^= h64 >> 29; + h64 *= XXH_PRIME64_3; + h64 ^= h64 >> 32; + return h64; +} + +static inline uint64_t qemu_xxhash64_4(uint64_t a, uint64_t b, + uint64_t c, uint64_t d) +{ + uint64_t v1 = QEMU_XXHASH_SEED + XXH_PRIME64_1 + XXH_PRIME64_2; + uint64_t v2 = QEMU_XXHASH_SEED + XXH_PRIME64_2; + uint64_t v3 = QEMU_XXHASH_SEED + 0; + uint64_t v4 = QEMU_XXHASH_SEED - XXH_PRIME64_1; + + v1 = XXH64_round(v1, a); + v2 = XXH64_round(v2, b); + v3 = XXH64_round(v3, c); + v4 = XXH64_round(v4, d); + + return XXH64_avalanche(XXH64_mergerounds(v1, v2, v3, v4)); +} + #endif /* QEMU_XXHASH_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..70e9618d13 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3852,10 +3852,8 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) { /* - * Note that while QEMU will only implement the architected algorithm - * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation - * defined algorithms, and thus API+GPI, and this predicate controls - * migration of the 128-bit keys. + * Return true if any form of pauth is enabled, as this + * predicate controls migration of the 128-bit keys. */ return (id->id_aa64isar1 & (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | @@ -3864,6 +3862,15 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; } +static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA algorithm. + * QEMU will always set APA+GPA to the same value. + */ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 564c48faa6..cd6df18150 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -24,6 +24,7 @@ #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" +#include "qemu/xxhash.h" static uint64_t pac_cell_shuffle(uint64_t i) @@ -207,8 +208,8 @@ static uint64_t tweak_inv_shuffle(uint64_t i) return o; } -static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, - ARMPACKey key) +static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, + ARMPACKey key) { static const uint64_t RC[5] = { 0x0000000000000000ull, @@ -272,6 +273,22 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, return workingval; } +static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier, + ARMPACKey key) +{ + return qemu_xxhash64_4(data, modifier, key.lo, key.hi); +} + +static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, + uint64_t modifier, ARMPACKey key) +{ + if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) { + return pauth_computepac_architected(data, modifier, key); + } else { + return pauth_computepac_impdef(data, modifier, key); + } +} + static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { @@ -292,7 +309,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, bot_bit = 64 - param.tsz; ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); - pac = pauth_computepac(ext_ptr, modifier, *key); + pac = pauth_computepac(env, ext_ptr, modifier, *key); /* * Check if the ptr has good extension bits and corrupt the @@ -341,7 +358,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t pac, orig_ptr, test; orig_ptr = pauth_original_ptr(ptr, param); - pac = pauth_computepac(orig_ptr, modifier, *key); + pac = pauth_computepac(env, orig_ptr, modifier, *key); bot_bit = 64 - param.tsz; top_bit = 64 - 8 * param.tbi; @@ -442,7 +459,7 @@ uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) uint64_t pac; pauth_check_trap(env, arm_current_el(env), GETPC()); - pac = pauth_computepac(x, y, env->keys.apga); + pac = pauth_computepac(env, x, y, env->keys.apga); return pac & 0xffffffff00000000ull; } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:11:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz6LN-0004iy-3m for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:11:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz6LJ-0004ex-EH for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:22 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:40225) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz6LF-0006CN-1h for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm658105pfb.196.2021.01.11.15.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:11:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Mark Rutland , Andrew Jones Subject: [PATCH v6 2/3] target/arm: Add cpu properties to control pauth Date: Mon, 11 Jan 2021 13:11:07 -1000 Message-Id: <20210111231108.461088-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111231108.461088-1-richard.henderson@linaro.org> References: <20210111231108.461088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:11:23 -0000 The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland Reviewed-by: Andrew Jones Signed-off-by: Richard Henderson --- v2: Use boolean properties instead of an enum (drjones). v3: Add tests (drjones). v6: Add documentation (pmm). --- docs/system/arm/cpu-features.rst | 21 +++++++++++++++++ target/arm/cpu.h | 10 ++++++++ target/arm/cpu.c | 13 +++++++++++ target/arm/cpu64.c | 40 ++++++++++++++++++++++++++++---- target/arm/monitor.c | 3 ++- tests/qtest/arm-cpu-features.c | 13 +++++++++++ 6 files changed, 95 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index 35196a6b75..70e0e4ef78 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -211,6 +211,27 @@ the list of KVM VCPU features and their descriptions. influence the guest scheduler behavior and/or be exposed to the guest userspace. +TCG VCPU Features +================= + +TCG VCPU features are CPU features that are specific to TCG. +Below is the list of TCG VCPU features and their descriptions. + + pauth Enable or disable `FEAT_Pauth`, pointer + authentication. By default, the feature is + enabled with `-cpu max`. + + pauth-impdef When `FEAT_Pauth` is enabled, either the + *impdef* (Implementation Definined) algorithm + is enabled or the *architected* QARMA algorithm + is enabled. By default the impdef algorithm + is disabled, and QARMA is enabled. + + The architected QARMA algorithm has good + cryptographic properties, but can be quite slow + to emulate. The impdef algorithm is + non-cryptographic but significantly faster. + SVE CPU Properties ================== diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 70e9618d13..06f5169f45 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -197,9 +197,11 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } +static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } #endif typedef struct ARMVectorReg { @@ -947,6 +949,14 @@ struct ARMCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + + /* + * Intermediate values used during property parsing. + * Once finalized, the values should be read from ID_AA64ISAR1. + */ + bool prop_pauth; + bool prop_pauth_impdef; + /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; uint64_t rvbar; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..be18df5464 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1320,6 +1320,19 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) error_propagate(errp, local_err); return; } + + /* + * KVM does not support modifications to this feature. + * We have not registered the cpu properties when KVM + * is in use, so the user will not be able to set them. + */ + if (!kvm_enabled()) { + arm_cpu_pauth_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } } if (kvm_enabled()) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc6..d9feaa9cdb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,8 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "qapi/visitor.h" +#include "hw/qdev-properties.h" + #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -572,6 +574,36 @@ void aarch64_add_sve_properties(Object *obj) } } +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + int arch_val = 0, impdef_val = 0; + uint64_t t; + + /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ + if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef) { + impdef_val = 1; + } else { + arch_val = 1; + } + } else if (cpu->prop_pauth_impdef) { + error_setg(errp, "cannot enable pauth-impdef without pauth"); + error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); + } + + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); + t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); + cpu->isar.id_aa64isar1 = t; +} + +static Property arm_cpu_pauth_property = + DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); +static Property arm_cpu_pauth_impdef_property = + DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -627,10 +659,6 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ - t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); - t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); @@ -720,6 +748,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + + /* Default to PAUTH on, with the architected algorithm. */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); } aarch64_add_sve_properties(obj); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 198b14e95e..1fdb965eb8 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -94,7 +94,8 @@ static const char *cpu_model_advertised_features[] = { "sve128", "sve256", "sve384", "sve512", "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", - "kvm-no-adjvtime", "kvm-steal-time", + "kvm-no-adjvtime", + "pauth", "pauth-impdef", NULL }; diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bc681a95d5..8252b85bb8 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -427,6 +427,18 @@ static void sve_tests_sve_off_kvm(const void *data) qtest_quit(qts); } +static void pauth_tests_default(QTestState *qts, const char *cpu_type) +{ + assert_has_feature_enabled(qts, cpu_type, "pauth"); + assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); + assert_set_feature(qts, cpu_type, "pauth", false); + assert_set_feature(qts, cpu_type, "pauth", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", false); + assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth", + "{ 'pauth': false, 'pauth-impdef': true }"); +} + static void test_query_cpu_model_expansion(const void *data) { QTestState *qts; @@ -462,6 +474,7 @@ static void test_query_cpu_model_expansion(const void *data) assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); sve_tests_default(qts, "max"); + pauth_tests_default(qts, "max"); /* Test that features that depend on KVM generate errors without. */ assert_error(qts, "max", -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:11:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz6LN-0004jR-Aw for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:11:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz6LL-0004hI-LO for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:23 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:34448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz6LG-0006Ce-Gu for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:11:23 -0500 Received: by mail-pj1-x1035.google.com with SMTP id n3so607749pjm.1 for ; Mon, 11 Jan 2021 15:11:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm658105pfb.196.2021.01.11.15.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:11:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Andrew Jones Subject: [PATCH v6 3/3] target/arm: Use object_property_add_bool for "sve" property Date: Mon, 11 Jan 2021 13:11:08 -1000 Message-Id: <20210111231108.461088-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111231108.461088-1-richard.henderson@linaro.org> References: <20210111231108.461088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:11:24 -0000 The interface for object_property_add_bool is simpler, making the code easier to understand. Reviewed-by: Andrew Jones Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d9feaa9cdb..8e1fad00bb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -488,6 +488,12 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, cpu->sve_max_vq = max_vq; } +/* + * Note that cpu_arm_get/set_sve_vq cannot use the simpler + * object_property_add_bool interface because they make use + * of the contents of "name" to determine which bit on which + * to operate. + */ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -529,26 +535,17 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, set_bit(vq - 1, cpu->sve_vq_init); } -static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static bool cpu_arm_get_sve(Object *obj, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); - bool value = cpu_isar_feature(aa64_sve, cpu); - - visit_type_bool(v, name, &value, errp); + return cpu_isar_feature(aa64_sve, cpu); } -static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); - bool value; uint64_t t; - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { error_setg(errp, "'sve' feature not supported by KVM on this host"); return; @@ -563,8 +560,7 @@ void aarch64_add_sve_properties(Object *obj) { uint32_t vq; - object_property_add(obj, "sve", "bool", cpu_arm_get_sve, - cpu_arm_set_sve, NULL, NULL); + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { char name[8]; -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:53:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz701-0002gH-O5 for mharc-qemu-arm@gnu.org; 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Mon, 11 Jan 2021 18:53:15 -0500 X-MC-Unique: ApFKNQarMg-XLP9hk2ZCoQ-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E520E1005D4C; Mon, 11 Jan 2021 23:53:13 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-115-146.rdu2.redhat.com [10.10.115.146]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D83B84F3C6; Mon, 11 Jan 2021 23:53:12 +0000 (UTC) Date: Mon, 11 Jan 2021 18:53:10 -0500 From: Andrew Jones To: Richard Henderson Cc: qemu-devel@nongnu.org, Mark Rutland , peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: Re: [PATCH v6 2/3] target/arm: Add cpu properties to control pauth Message-ID: <20210111235310.bbeis2rh25kud2kz@kamzik.brq.redhat.com> References: <20210111231108.461088-1-richard.henderson@linaro.org> <20210111231108.461088-3-richard.henderson@linaro.org> MIME-Version: 1.0 In-Reply-To: <20210111231108.461088-3-richard.henderson@linaro.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:53:23 -0000 On Mon, Jan 11, 2021 at 01:11:07PM -1000, Richard Henderson wrote: > The crypto overhead of emulating pauth can be significant for > some workloads. Add two boolean properties that allows the > feature to be turned off, on with the architected algorithm, > or on with an implementation defined algorithm. > > We need two intermediate booleans to control the state while > parsing properties lest we clobber ID_AA64ISAR1 into an invalid > intermediate state. > > Tested-by: Mark Rutland > Reviewed-by: Andrew Jones > Signed-off-by: Richard Henderson > --- > v2: Use boolean properties instead of an enum (drjones). > v3: Add tests (drjones). > v6: Add documentation (pmm). > --- > docs/system/arm/cpu-features.rst | 21 +++++++++++++++++ > target/arm/cpu.h | 10 ++++++++ > target/arm/cpu.c | 13 +++++++++++ > target/arm/cpu64.c | 40 ++++++++++++++++++++++++++++---- > target/arm/monitor.c | 3 ++- > tests/qtest/arm-cpu-features.c | 13 +++++++++++ > 6 files changed, 95 insertions(+), 5 deletions(-) > > diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst > index 35196a6b75..70e0e4ef78 100644 > --- a/docs/system/arm/cpu-features.rst > +++ b/docs/system/arm/cpu-features.rst > @@ -211,6 +211,27 @@ the list of KVM VCPU features and their descriptions. > influence the guest scheduler behavior and/or be > exposed to the guest userspace. > > +TCG VCPU Features > +================= > + > +TCG VCPU features are CPU features that are specific to TCG. > +Below is the list of TCG VCPU features and their descriptions. > + > + pauth Enable or disable `FEAT_Pauth`, pointer > + authentication. By default, the feature is > + enabled with `-cpu max`. > + > + pauth-impdef When `FEAT_Pauth` is enabled, either the > + *impdef* (Implementation Definined) algorithm > + is enabled or the *architected* QARMA algorithm > + is enabled. By default the impdef algorithm > + is disabled, and QARMA is enabled. > + > + The architected QARMA algorithm has good > + cryptographic properties, but can be quite slow > + to emulate. The impdef algorithm is > + non-cryptographic but significantly faster. > + Doc updates look good. > SVE CPU Properties > ================== > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 70e9618d13..06f5169f45 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -197,9 +197,11 @@ typedef struct { > #ifdef TARGET_AARCH64 > # define ARM_MAX_VQ 16 > void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); > +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); > #else > # define ARM_MAX_VQ 1 > static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } > +static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } > #endif > > typedef struct ARMVectorReg { > @@ -947,6 +949,14 @@ struct ARMCPU { > uint64_t reset_cbar; > uint32_t reset_auxcr; > bool reset_hivecs; > + > + /* > + * Intermediate values used during property parsing. > + * Once finalized, the values should be read from ID_AA64ISAR1. > + */ > + bool prop_pauth; > + bool prop_pauth_impdef; > + > /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ > uint32_t dcz_blocksize; > uint64_t rvbar; > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 8387e94b94..be18df5464 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1320,6 +1320,19 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) > error_propagate(errp, local_err); > return; > } > + > + /* > + * KVM does not support modifications to this feature. > + * We have not registered the cpu properties when KVM > + * is in use, so the user will not be able to set them. > + */ > + if (!kvm_enabled()) { > + arm_cpu_pauth_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + } > } > > if (kvm_enabled()) { > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 7cf9fc4bc6..d9feaa9cdb 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -28,6 +28,8 @@ > #include "sysemu/kvm.h" > #include "kvm_arm.h" > #include "qapi/visitor.h" > +#include "hw/qdev-properties.h" > + > > #ifndef CONFIG_USER_ONLY > static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) > @@ -572,6 +574,36 @@ void aarch64_add_sve_properties(Object *obj) > } > } > > +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) > +{ > + int arch_val = 0, impdef_val = 0; > + uint64_t t; > + > + /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ > + if (cpu->prop_pauth) { > + if (cpu->prop_pauth_impdef) { > + impdef_val = 1; > + } else { > + arch_val = 1; > + } > + } else if (cpu->prop_pauth_impdef) { > + error_setg(errp, "cannot enable pauth-impdef without pauth"); > + error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); > + } > + > + t = cpu->isar.id_aa64isar1; > + t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); > + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); > + t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); > + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); > + cpu->isar.id_aa64isar1 = t; > +} > + > +static Property arm_cpu_pauth_property = > + DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); > +static Property arm_cpu_pauth_impdef_property = > + DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); > + > /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); > * otherwise, a CPU with as many features enabled as our emulation supports. > * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; > @@ -627,10 +659,6 @@ static void aarch64_max_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); > t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); > - t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ > - t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); > - t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); > - t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); > t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); > @@ -720,6 +748,10 @@ static void aarch64_max_initfn(Object *obj) > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > #endif > + > + /* Default to PAUTH on, with the architected algorithm. */ > + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); > + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); > } > > aarch64_add_sve_properties(obj); > diff --git a/target/arm/monitor.c b/target/arm/monitor.c > index 198b14e95e..1fdb965eb8 100644 > --- a/target/arm/monitor.c > +++ b/target/arm/monitor.c > @@ -94,7 +94,8 @@ static const char *cpu_model_advertised_features[] = { > "sve128", "sve256", "sve384", "sve512", > "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", > "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", > - "kvm-no-adjvtime", "kvm-steal-time", > + "kvm-no-adjvtime", Looks like a rebase error; kvm-steal-time is getting dropped. > + "pauth", "pauth-impdef", > NULL > }; > > diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c > index bc681a95d5..8252b85bb8 100644 > --- a/tests/qtest/arm-cpu-features.c > +++ b/tests/qtest/arm-cpu-features.c > @@ -427,6 +427,18 @@ static void sve_tests_sve_off_kvm(const void *data) > qtest_quit(qts); > } > > +static void pauth_tests_default(QTestState *qts, const char *cpu_type) > +{ > + assert_has_feature_enabled(qts, cpu_type, "pauth"); > + assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); > + assert_set_feature(qts, cpu_type, "pauth", false); > + assert_set_feature(qts, cpu_type, "pauth", true); > + assert_set_feature(qts, cpu_type, "pauth-impdef", true); > + assert_set_feature(qts, cpu_type, "pauth-impdef", false); > + assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth", > + "{ 'pauth': false, 'pauth-impdef': true }"); > +} > + > static void test_query_cpu_model_expansion(const void *data) > { > QTestState *qts; > @@ -462,6 +474,7 @@ static void test_query_cpu_model_expansion(const void *data) > assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); > > sve_tests_default(qts, "max"); > + pauth_tests_default(qts, "max"); > > /* Test that features that depend on KVM generate errors without. */ > assert_error(qts, "max", > -- > 2.25.1 > > Thanks, drew From MAILER-DAEMON Mon Jan 11 18:54:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz71M-0003cA-EQ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:54:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz71I-0003aI-5Z for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:54:45 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:34552) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz71D-00037t-UM for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:54:43 -0500 Received: by mail-pl1-x633.google.com with SMTP id t6so401096plq.1 for ; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id b11sm543050pjl.41.2021.01.11.15.54.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 15:54:37 -0800 (PST) Subject: Re: [PATCH v6 2/3] target/arm: Add cpu properties to control pauth To: Andrew Jones Cc: qemu-devel@nongnu.org, Mark Rutland , peter.maydell@linaro.org, qemu-arm@nongnu.org References: <20210111231108.461088-1-richard.henderson@linaro.org> <20210111231108.461088-3-richard.henderson@linaro.org> <20210111235310.bbeis2rh25kud2kz@kamzik.brq.redhat.com> From: Richard Henderson Message-ID: <80b2ff9f-3614-07d1-88a2-686854d55555@linaro.org> Date: Mon, 11 Jan 2021 13:54:33 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210111235310.bbeis2rh25kud2kz@kamzik.brq.redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:54:46 -0000 On 1/11/21 1:53 PM, Andrew Jones wrote: >> - "kvm-no-adjvtime", "kvm-steal-time", >> + "kvm-no-adjvtime", > Looks like a rebase error; kvm-steal-time is getting dropped. > Whoops. Will fix. r~ From MAILER-DAEMON Mon Jan 11 18:57:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz74G-0005S9-Pk for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:57:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz74E-0005Pn-OU for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:46 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:33178) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz74D-0003Uv-2L for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:46 -0500 Received: by mail-pg1-x533.google.com with SMTP id n25so238995pgb.0 for ; Mon, 11 Jan 2021 15:57:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=zatfyXOxSXAm72pAS+OrSbicSsn0LfrDrs51sewnb54=; b=Frk1CPUujx4N30J9g24nO3Nim0kcrYUFCfyGK12O+bxMTwKx99ZWIkbJq3SkajgOgS N4Noo0C50FhowCOK4ZMaFhzP+HRmUhrRIlCenQKNiNx1r9wEZJjKw33V1gQusgs17iGD DLTOu7uSEG4P/jDS7zH3drazljXe7fGNfKkI2ypzfx4paxfedkIgUGfgOo9C3rgx6X5l kY9X3fEVHs84ZK+D3G5J3c0Qa989loUgErBc2CPs+hM0pH9HbMMk7kd+iNBwpjugyI3f W1SCKOmn8gJrNvai/JmPnHFlGvhHY4EHKIXkNLTg3rXJhKzzw5pL6ZojjrmNLJNVfdYg lN6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=zatfyXOxSXAm72pAS+OrSbicSsn0LfrDrs51sewnb54=; b=BMgIh0n5Mhv/JL3O/IqdJsiVlEHIJ/GRyFGyab4Ysr5ds1xnuKhRqosvRhKrbYkAar uVJk269i20vBDOS1VcPyyA5ULu41O/X5LSn4UgdYVkkZ/SrEq+7hG277e+3JwmmtyOgy wv2InzXi/MW8EE2MzRwG43vM53TyGd/sXue7UgZUeHHe9C4o4FQcQ7hePb5gvI+sImdG nJ0vAh/4vv/K3F9xrZC5IHvFMsEIhT7Ak4/RgaAvP6jVVJ8eXh7Nn2COyS9lq+Oqb5pD dsNwyQJgmxCCvJXQQmyPtdc8NpBpGnH0lYwdRpNL2nTl3/0FkGcVaBOt1UF0RqTFZRJw rL2w== X-Gm-Message-State: AOAM533gXS0oAy6UYDOK0sKmz1b3UIsOi5QNyfr6n6EAjHtjEcmeb2cV zexBnL1hdScAFF/3vqSMV/HDsA== X-Google-Smtp-Source: ABdhPJzn3bMna8qhMfzwrektrzzWWIh4B6fK5NX9QW4AnZ6fhzcbivfjZ5T96lpefxDnoWSlNtfRMA== X-Received: by 2002:a63:d246:: with SMTP id t6mr1844270pgi.283.1610409463690; Mon, 11 Jan 2021 15:57:43 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s67sm872220pgb.60.2021.01.11.15.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:57:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v7 0/3] target/arm: Implement an IMPDEF pauth algorithm Date: Mon, 11 Jan 2021 13:57:37 -1000 Message-Id: <20210111235740.462469-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:57:47 -0000 The architected pauth algorithm is quite slow without hardware support, and boot times for kernels that enable use of the feature have been significantly impacted. Version 7 changes: * Fix rebase error (drjones). Version 6 changes: * Rearrange xxhash64 (pmm). * Add documentation (pmm). r~ Richard Henderson (3): target/arm: Implement an IMPDEF pauth algorithm target/arm: Add cpu properties to control pauth target/arm: Use object_property_add_bool for "sve" property docs/system/arm/cpu-features.rst | 21 +++++++ include/qemu/xxhash.h | 98 ++++++++++++++++++++++++++++++++ target/arm/cpu.h | 25 ++++++-- target/arm/cpu.c | 13 +++++ target/arm/cpu64.c | 64 +++++++++++++++------ target/arm/monitor.c | 1 + target/arm/pauth_helper.c | 27 +++++++-- tests/qtest/arm-cpu-features.c | 13 +++++ 8 files changed, 235 insertions(+), 27 deletions(-) -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:57:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz74Q-0005Vx-K3 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:57:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz74H-0005SU-7x for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:50 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38453) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz74E-0003V7-Mv for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:49 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d2so266735pfq.5 for ; Mon, 11 Jan 2021 15:57:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMumzk4fm+ReubqkvThPEU9TX17+RjW08bNhr8jJ4Ok=; b=Z6nuiMud4Et4m4CNVFkYDEcvv5wp7NPEFXi0gyAdzzBVeQJGh/GzpZE+8QLcJi20oF CLCSl5XOpy7NQiO8neA+kiTXLnDCB4s8pH/fmyghYQKtuRQvs6fS+MI+oq3YUR6VlEGb mieW0FPOGrtwsJhNzwThadP1yCgaynCH6ZjRAHYB6gHuJDaKcyBWdaHzdlNJ6idjS87Z k+o3tli6j12Jsnsi9F8aeXdQ1+k259uvOnYHTzsyFXslDDBo7fhHgMFNhq1uFjo9gT4U BIMHaps19wtvDmEls9MH1SlACIZzp/CcEQ9HndR7fMOPBlwgCo74Mzbhg206hy+qmx3p P5bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMumzk4fm+ReubqkvThPEU9TX17+RjW08bNhr8jJ4Ok=; b=A0ivFx8imbSLuF7g5SDH5Yym0WfGDrORsL9Zk4lXXD5BVXQXht9w4KSAZhEf3LLf4Q cYL+I+MK9s5mq02l8rWLMGI5JzSuRb0oWSLzrTHwB1J8HyEJ9l7lUbDduyKj9GDziqTZ dF/eSPLlMuSTOXnferse2O82Kvo72Ef/b8TIY3s13y7vzp5UDhyvjmULi5npubo5Hms2 BYktIbd9T5n44sMXMp3PkooAkUv57640QSfjjSdFkup58aOxQpvZjuXDvvOYWMsHwb/5 iaC/NHPH336f8B38VJNk2UuwS0kSQe5lgOvnAF0RctS/UZXgf+fJw8mfNgje7njw7Z+I skxw== X-Gm-Message-State: AOAM531Qh0fYWVtMKv2jluFEBjkDSDij2srsdXMORWlosokNvtv+QMR1 IWy+7zl+Q8dCrW/44Pg6+WTR9bYtImj9mQ== X-Google-Smtp-Source: ABdhPJxnrsFOQsdk4NjUuErVSzep8DE0/Wn91vYtPsecRZ02kivzq+gCbjTWQ//y9zAXWj7xJA0Rfg== X-Received: by 2002:a63:d041:: with SMTP id s1mr1846099pgi.249.1610409465473; Mon, 11 Jan 2021 15:57:45 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s67sm872220pgb.60.2021.01.11.15.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:57:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Mark Rutland Subject: [PATCH v7 1/3] target/arm: Implement an IMPDEF pauth algorithm Date: Mon, 11 Jan 2021 13:57:38 -1000 Message-Id: <20210111235740.462469-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111235740.462469-1-richard.henderson@linaro.org> References: <20210111235740.462469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:57:52 -0000 Without hardware acceleration, a cryptographically strong algorithm is too expensive for pauth_computepac. Even with hardware accel, we are not currently expecting to link the linux-user binaries to any crypto libraries, and doing so would generally make the --static build fail. So choose XXH64 as a reasonably quick and decent hash. Tested-by: Mark Rutland Signed-off-by: Richard Henderson --- v2: Move the XXH64 bits to xxhash.h (ajb). Create isar_feature_aa64_pauth_arch and fixup a comment in isar_feature_aa64_pauth that no longer applies. v6: Introduce qemu_xxhash64_4 (pmm). --- include/qemu/xxhash.h | 98 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 15 ++++-- target/arm/pauth_helper.c | 27 +++++++++-- 3 files changed, 131 insertions(+), 9 deletions(-) diff --git a/include/qemu/xxhash.h b/include/qemu/xxhash.h index 076f1f6054..c2dcccadbf 100644 --- a/include/qemu/xxhash.h +++ b/include/qemu/xxhash.h @@ -119,4 +119,102 @@ static inline uint32_t qemu_xxhash6(uint64_t ab, uint64_t cd, uint32_t e, return qemu_xxhash7(ab, cd, e, f, 0); } +/* + * Component parts of the XXH64 algorithm from + * https://github.com/Cyan4973/xxHash/blob/v0.8.0/xxhash.h + * + * The complete algorithm looks like + * + * i = 0; + * if (len >= 32) { + * v1 = seed + XXH_PRIME64_1 + XXH_PRIME64_2; + * v2 = seed + XXH_PRIME64_2; + * v3 = seed + 0; + * v4 = seed - XXH_PRIME64_1; + * do { + * v1 = XXH64_round(v1, get64bits(input + i)); + * v2 = XXH64_round(v2, get64bits(input + i + 8)); + * v3 = XXH64_round(v3, get64bits(input + i + 16)); + * v4 = XXH64_round(v4, get64bits(input + i + 24)); + * } while ((i += 32) <= len); + * h64 = XXH64_mergerounds(v1, v2, v3, v4); + * } else { + * h64 = seed + XXH_PRIME64_5; + * } + * h64 += len; + * + * for (; i + 8 <= len; i += 8) { + * h64 ^= XXH64_round(0, get64bits(input + i)); + * h64 = rol64(h64, 27) * XXH_PRIME64_1 + XXH_PRIME64_4; + * } + * for (; i + 4 <= len; i += 4) { + * h64 ^= get32bits(input + i) * PRIME64_1; + * h64 = rol64(h64, 23) * XXH_PRIME64_2 + XXH_PRIME64_3; + * } + * for (; i < len; i += 1) { + * h64 ^= get8bits(input + i) * XXH_PRIME64_5; + * h64 = rol64(h64, 11) * XXH_PRIME64_1; + * } + * + * return XXH64_avalanche(h64) + * + * Exposing the pieces instead allows for simplified usage when + * the length is a known constant and the inputs are in registers. + */ +#define XXH_PRIME64_1 0x9E3779B185EBCA87ULL +#define XXH_PRIME64_2 0xC2B2AE3D27D4EB4FULL +#define XXH_PRIME64_3 0x165667B19E3779F9ULL +#define XXH_PRIME64_4 0x85EBCA77C2B2AE63ULL +#define XXH_PRIME64_5 0x27D4EB2F165667C5ULL + +static inline uint64_t XXH64_round(uint64_t acc, uint64_t input) +{ + return rol64(acc + input * XXH_PRIME64_2, 31) * XXH_PRIME64_1; +} + +static inline uint64_t XXH64_mergeround(uint64_t acc, uint64_t val) +{ + return (acc ^ XXH64_round(0, val)) * XXH_PRIME64_1 + XXH_PRIME64_4; +} + +static inline uint64_t XXH64_mergerounds(uint64_t v1, uint64_t v2, + uint64_t v3, uint64_t v4) +{ + uint64_t h64; + + h64 = rol64(v1, 1) + rol64(v2, 7) + rol64(v3, 12) + rol64(v4, 18); + h64 = XXH64_mergeround(h64, v1); + h64 = XXH64_mergeround(h64, v2); + h64 = XXH64_mergeround(h64, v3); + h64 = XXH64_mergeround(h64, v4); + + return h64; +} + +static inline uint64_t XXH64_avalanche(uint64_t h64) +{ + h64 ^= h64 >> 33; + h64 *= XXH_PRIME64_2; + h64 ^= h64 >> 29; + h64 *= XXH_PRIME64_3; + h64 ^= h64 >> 32; + return h64; +} + +static inline uint64_t qemu_xxhash64_4(uint64_t a, uint64_t b, + uint64_t c, uint64_t d) +{ + uint64_t v1 = QEMU_XXHASH_SEED + XXH_PRIME64_1 + XXH_PRIME64_2; + uint64_t v2 = QEMU_XXHASH_SEED + XXH_PRIME64_2; + uint64_t v3 = QEMU_XXHASH_SEED + 0; + uint64_t v4 = QEMU_XXHASH_SEED - XXH_PRIME64_1; + + v1 = XXH64_round(v1, a); + v2 = XXH64_round(v2, b); + v3 = XXH64_round(v3, c); + v4 = XXH64_round(v4, d); + + return XXH64_avalanche(XXH64_mergerounds(v1, v2, v3, v4)); +} + #endif /* QEMU_XXHASH_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..70e9618d13 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3852,10 +3852,8 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) { /* - * Note that while QEMU will only implement the architected algorithm - * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation - * defined algorithms, and thus API+GPI, and this predicate controls - * migration of the 128-bit keys. + * Return true if any form of pauth is enabled, as this + * predicate controls migration of the 128-bit keys. */ return (id->id_aa64isar1 & (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | @@ -3864,6 +3862,15 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; } +static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA algorithm. + * QEMU will always set APA+GPA to the same value. + */ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 564c48faa6..cd6df18150 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -24,6 +24,7 @@ #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" +#include "qemu/xxhash.h" static uint64_t pac_cell_shuffle(uint64_t i) @@ -207,8 +208,8 @@ static uint64_t tweak_inv_shuffle(uint64_t i) return o; } -static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, - ARMPACKey key) +static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, + ARMPACKey key) { static const uint64_t RC[5] = { 0x0000000000000000ull, @@ -272,6 +273,22 @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier, return workingval; } +static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier, + ARMPACKey key) +{ + return qemu_xxhash64_4(data, modifier, key.lo, key.hi); +} + +static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, + uint64_t modifier, ARMPACKey key) +{ + if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) { + return pauth_computepac_architected(data, modifier, key); + } else { + return pauth_computepac_impdef(data, modifier, key); + } +} + static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { @@ -292,7 +309,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, bot_bit = 64 - param.tsz; ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); - pac = pauth_computepac(ext_ptr, modifier, *key); + pac = pauth_computepac(env, ext_ptr, modifier, *key); /* * Check if the ptr has good extension bits and corrupt the @@ -341,7 +358,7 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, uint64_t pac, orig_ptr, test; orig_ptr = pauth_original_ptr(ptr, param); - pac = pauth_computepac(orig_ptr, modifier, *key); + pac = pauth_computepac(env, orig_ptr, modifier, *key); bot_bit = 64 - param.tsz; top_bit = 64 - 8 * param.tbi; @@ -442,7 +459,7 @@ uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) uint64_t pac; pauth_check_trap(env, arm_current_el(env), GETPC()); - pac = pauth_computepac(x, y, env->keys.apga); + pac = pauth_computepac(env, x, y, env->keys.apga); return pac & 0xffffffff00000000ull; } -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:58:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz74S-0005XL-D6 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:58:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz74K-0005Sw-B7 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:54 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:46784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz74H-0003Vd-2p for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s67sm872220pgb.60.2021.01.11.15.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:57:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Mark Rutland , Andrew Jones Subject: [PATCH v7 2/3] target/arm: Add cpu properties to control pauth Date: Mon, 11 Jan 2021 13:57:39 -1000 Message-Id: <20210111235740.462469-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111235740.462469-1-richard.henderson@linaro.org> References: <20210111235740.462469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:57:54 -0000 The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland Reviewed-by: Andrew Jones Signed-off-by: Richard Henderson --- v2: Use boolean properties instead of an enum (drjones). v3: Add tests (drjones). v6: Add documentation (pmm). --- docs/system/arm/cpu-features.rst | 21 +++++++++++++++++ target/arm/cpu.h | 10 ++++++++ target/arm/cpu.c | 13 +++++++++++ target/arm/cpu64.c | 40 ++++++++++++++++++++++++++++---- target/arm/monitor.c | 1 + tests/qtest/arm-cpu-features.c | 13 +++++++++++ 6 files changed, 94 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index 35196a6b75..70e0e4ef78 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -211,6 +211,27 @@ the list of KVM VCPU features and their descriptions. influence the guest scheduler behavior and/or be exposed to the guest userspace. +TCG VCPU Features +================= + +TCG VCPU features are CPU features that are specific to TCG. +Below is the list of TCG VCPU features and their descriptions. + + pauth Enable or disable `FEAT_Pauth`, pointer + authentication. By default, the feature is + enabled with `-cpu max`. + + pauth-impdef When `FEAT_Pauth` is enabled, either the + *impdef* (Implementation Definined) algorithm + is enabled or the *architected* QARMA algorithm + is enabled. By default the impdef algorithm + is disabled, and QARMA is enabled. + + The architected QARMA algorithm has good + cryptographic properties, but can be quite slow + to emulate. The impdef algorithm is + non-cryptographic but significantly faster. + SVE CPU Properties ================== diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 70e9618d13..06f5169f45 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -197,9 +197,11 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } +static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } #endif typedef struct ARMVectorReg { @@ -947,6 +949,14 @@ struct ARMCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + + /* + * Intermediate values used during property parsing. + * Once finalized, the values should be read from ID_AA64ISAR1. + */ + bool prop_pauth; + bool prop_pauth_impdef; + /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; uint64_t rvbar; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..be18df5464 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1320,6 +1320,19 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) error_propagate(errp, local_err); return; } + + /* + * KVM does not support modifications to this feature. + * We have not registered the cpu properties when KVM + * is in use, so the user will not be able to set them. + */ + if (!kvm_enabled()) { + arm_cpu_pauth_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } } if (kvm_enabled()) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc6..d9feaa9cdb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,8 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "qapi/visitor.h" +#include "hw/qdev-properties.h" + #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -572,6 +574,36 @@ void aarch64_add_sve_properties(Object *obj) } } +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + int arch_val = 0, impdef_val = 0; + uint64_t t; + + /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ + if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef) { + impdef_val = 1; + } else { + arch_val = 1; + } + } else if (cpu->prop_pauth_impdef) { + error_setg(errp, "cannot enable pauth-impdef without pauth"); + error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); + } + + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); + t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); + t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); + t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); + cpu->isar.id_aa64isar1 = t; +} + +static Property arm_cpu_pauth_property = + DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); +static Property arm_cpu_pauth_impdef_property = + DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -627,10 +659,6 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ - t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); - t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); @@ -720,6 +748,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + + /* Default to PAUTH on, with the architected algorithm. */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); } aarch64_add_sve_properties(obj); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 198b14e95e..80c64fa355 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -95,6 +95,7 @@ static const char *cpu_model_advertised_features[] = { "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", "kvm-no-adjvtime", "kvm-steal-time", + "pauth", "pauth-impdef", NULL }; diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bc681a95d5..8252b85bb8 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -427,6 +427,18 @@ static void sve_tests_sve_off_kvm(const void *data) qtest_quit(qts); } +static void pauth_tests_default(QTestState *qts, const char *cpu_type) +{ + assert_has_feature_enabled(qts, cpu_type, "pauth"); + assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); + assert_set_feature(qts, cpu_type, "pauth", false); + assert_set_feature(qts, cpu_type, "pauth", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", true); + assert_set_feature(qts, cpu_type, "pauth-impdef", false); + assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth", + "{ 'pauth': false, 'pauth-impdef': true }"); +} + static void test_query_cpu_model_expansion(const void *data) { QTestState *qts; @@ -462,6 +474,7 @@ static void test_query_cpu_model_expansion(const void *data) assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); sve_tests_default(qts, "max"); + pauth_tests_default(qts, "max"); /* Test that features that depend on KVM generate errors without. */ assert_error(qts, "max", -- 2.25.1 From MAILER-DAEMON Mon Jan 11 18:58:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz74T-0005Xi-Oi for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 18:58:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz74M-0005TV-CC for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:55 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:33172) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz74K-0003W0-3J for qemu-arm@nongnu.org; Mon, 11 Jan 2021 18:57:54 -0500 Received: by mail-pg1-x52c.google.com with SMTP id n25so239134pgb.0 for ; Mon, 11 Jan 2021 15:57:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s67sm872220pgb.60.2021.01.11.15.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jan 2021 15:57:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, Andrew Jones Subject: [PATCH v7 3/3] target/arm: Use object_property_add_bool for "sve" property Date: Mon, 11 Jan 2021 13:57:40 -1000 Message-Id: <20210111235740.462469-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210111235740.462469-1-richard.henderson@linaro.org> References: <20210111235740.462469-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jan 2021 23:57:56 -0000 The interface for object_property_add_bool is simpler, making the code easier to understand. Reviewed-by: Andrew Jones Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d9feaa9cdb..8e1fad00bb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -488,6 +488,12 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, cpu->sve_max_vq = max_vq; } +/* + * Note that cpu_arm_get/set_sve_vq cannot use the simpler + * object_property_add_bool interface because they make use + * of the contents of "name" to determine which bit on which + * to operate. + */ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -529,26 +535,17 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, set_bit(vq - 1, cpu->sve_vq_init); } -static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static bool cpu_arm_get_sve(Object *obj, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); - bool value = cpu_isar_feature(aa64_sve, cpu); - - visit_type_bool(v, name, &value, errp); + return cpu_isar_feature(aa64_sve, cpu); } -static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); - bool value; uint64_t t; - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { error_setg(errp, "'sve' feature not supported by KVM on this host"); return; @@ -563,8 +560,7 @@ void aarch64_add_sve_properties(Object *obj) { uint32_t vq; - object_property_add(obj, "sve", "bool", cpu_arm_get_sve, - cpu_arm_set_sve, NULL, NULL); + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { char name[8]; -- 2.25.1 From MAILER-DAEMON Mon Jan 11 19:01:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz77x-00014A-SU for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:01:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz77r-000118-0k for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:01:31 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:38433) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz77o-0003zg-7w for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:01:30 -0500 Received: by mail-pl1-x62d.google.com with SMTP id 4so395003plk.5 for ; Mon, 11 Jan 2021 16:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=B/xCcpZT7AUXqjxug7629sTOGA9CVKu7LttJVCOlUIA=; b=kVCWLw2+wCRJL/4onzNH51iZQ2xzoRexl/IIRwQ52OEk6ZbCOi1QY+OEUZQbKDRk8l wh4Pn0yY9rahV9TXsAwseZdXGKYaUzd3emfQ6SXsU1pZQuSkweh4JAUBmLrymDmB3bnD 27l9//Nu8KSuV0xWQhatDOk0fHDmoxhrJzl/pbUS83v4p0xDELlFT5bYImTzyHLDyS+l 4ymu/fIcWNesA3TfuYJMtriPqs5hRxUcmB3bbxyhwFLJEEIIli7vZ0F+N9fmPUcgdACt H/Jh+g7WdKMqPSofDBohnjh0RYNJqtMvoE/mLd/n9dMPYBWsZKU7oXN8tkMVYoasMD6+ lAIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=B/xCcpZT7AUXqjxug7629sTOGA9CVKu7LttJVCOlUIA=; b=sT4D/tn42YlFy2q2VVAkURcOmPctgVboqPIsRvDKPUrcbpc0EZi/cAIN9yzniIsHVZ iVi9cjtxi/ke2D13zVVCkTbovR6kXFud/tNk1clB2MHNOc+OR2Ek9KKnZYru49w2tLyT iL2JZ2DfIr2jmUuu8CZik65VI0aFib8rjTHsat6S79yTcvd5Xjfy5sD3OGAbX5gRYfXh 6VBvBDy0LJxHU0Se67q8wsbLol2sLTU8x6yv4DUO98I30AYHRYpenIEqCemR7AABtzMk +FT0sCpwT3WAREZugp50K84fbjfGJhfVQnLQfOgvgOiBDOJ3vp9SgxQu1bPO6j2hkk/q YSBA== X-Gm-Message-State: AOAM533oejD5KDtzN9iH9QKi8/tsqkCN3OvOvAnazLBCvfhwxYabZT8j oyQcnUjq7P072npjB1QnsybS0w== X-Google-Smtp-Source: ABdhPJzqtTJH7X57WLgowfBQ4x3RPQW3RO4/73cLmmLOmintCEhwe+DkNZMYy9o5FISDktmSR7Xy6Q== X-Received: by 2002:a17:90a:ba88:: with SMTP id t8mr1364626pjr.229.1610409686410; Mon, 11 Jan 2021 16:01:26 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id b11sm778926pfr.38.2021.01.11.16.01.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:01:25 -0800 (PST) Subject: Re: [PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel , Peter Maydell References: <20210108090817.6127-2-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <8c89d84f-ae3f-d888-51ad-ed01cdcdd833@linaro.org> Date: Mon, 11 Jan 2021 14:01:22 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108090817.6127-2-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:01:31 -0000 On 1/7/21 11:08 PM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:02:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz78g-0001kA-KJ for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:02:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz78f-0001hk-9M for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:02:21 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:36771) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz78a-00042W-Co for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:02:21 -0500 Received: by mail-pg1-x534.google.com with SMTP id c132so234222pga.3 for ; Mon, 11 Jan 2021 16:02:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=xjvLBrHeF+JCsVH9axuUq0DIVfH9q/a3MGYMon8ZpGY=; b=U6fi7A0+faosF40L0HO+4wWL7GKTWQxIdiWIkG/Wtl9UfKgmwSl7u7NjFmQ5SuWTtq SEs8Fk7cOs7e0PuqRzF+rxRmVtpo4/9yCk5RIyo09VENqeECfYYsXcnDa7xQiXrjTnPj 4qXCh4y35VZgVyi2Hf+7cv7TP1ALO/Ca7KO+oveD254ISQ5v4Ngi5skGQQ6Wuj7LonO1 gOoQb0NfVcpmMve6tBjTqktXkWGA49EksTvb80Oz3xDM4mBvJteDa5CnRpU/KijMqK2c keJR29mjIKFLFmu4+YMAoc9kHqEz1tbGqKLp3ziMV8+IgBrzi/s8XndMrrprx1PP0p+E +8Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=xjvLBrHeF+JCsVH9axuUq0DIVfH9q/a3MGYMon8ZpGY=; b=AasJvvhfKrmYQP6W9RPJYXQud7ZUaGKSEHprwS/4oZBtDSS6equLtIzsE5cUl7bfUv 3PYYfSzRMgXgbC7gABgfiRdvfJDJeFzDBC90Xqz55rPLobWuXGuFu5zPfCMl0N9LYdrq raYB/g06HDjECg9knbQ7kclgWgxKImXOYRmfvpcj4L3XisoeU82DjvBU17YAUQINFaFY 8UKo/TcDGpyuhcilBFZaPZglQmNAerCtKHNLcmNG22E7cIhiDsNAg/lpqsRurDYSSQNJ zUX7wwLB2x3nfOufRoyfVUPc9kVWIB7mWoJFq3EgzqgzacI5Ztiah7zs1bMnCsrpcj+N VlRQ== X-Gm-Message-State: AOAM532DOsDzB4+wFwO8qZhsU4GUJE7ouIEF4ic7+AwA3v5mIf03alpG fb6TOQlScx6IQLREgeHMT4ffKA== X-Google-Smtp-Source: ABdhPJw4Kvisy4MN6k+g9CSwpFeooW2erk2h1xHH9FhQr5zR9n5b5j8Nwv2sf9S56MEs90rUeqy+Ew== X-Received: by 2002:a65:4785:: with SMTP id e5mr1929953pgs.0.1610409734619; Mon, 11 Jan 2021 16:02:14 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id ay21sm601298pjb.1.2021.01.11.16.02.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:02:14 -0800 (PST) Subject: Re: [PATCHv2 1/2] target/arm: ARMv8.4-TTST extension To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <20210108090817.6127-1-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Mon, 11 Jan 2021 14:02:10 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210108090817.6127-1-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:02:21 -0000 On 1/7/21 11:08 PM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > This adds for the Small Translation tables extension in AArch64 state. > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/cpu.h | 5 +++++ > target/arm/helper.c | 15 +++++++++++++-- > 2 files changed, 18 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:04:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7As-000475-Q4 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:04:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7Ar-00044t-4I for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:04:37 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:53780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7Ap-0004AA-HU for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:04:36 -0500 Received: by mail-pj1-x1031.google.com with SMTP id iq13so508775pjb.3 for ; Mon, 11 Jan 2021 16:04:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=LJNA0ymU8hi3RERfT9NjYqnA2IoQ4wFCQxB8JLyAW/Q=; b=M1q6X9dSodIo6VLP26CmHfkuNU2smANxSU/9Z9xJNiKUhnaWDjT0LllzRfsm89/Q/w 9AQXQzTyyoB1JQ0gXebFAvTeEdBZc/mwrBkW1SJN72h3HU8eksdvhXaoVT2nHVpeH14v 9vEYBD1rqSBUjOttPVNtg6ZY+xrjjWYSCGuWRUFTCWVDVtixEX/yEI7vGiHbakp9QPUl twzK5TipXTlfq16q9TUDPTYnYXB+dIi04qan37y0Nm+4TRiwsTdj9J5L2aDKiMlRXy6q EcVnA1U6/Q/flG4helwSHvSzm2qXdsK09mG5t55IRcnr0RSHHIYPQpJzbjtjG4wjy2CX Rr3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LJNA0ymU8hi3RERfT9NjYqnA2IoQ4wFCQxB8JLyAW/Q=; b=c9lxmLusVAx3pVaUHGjz2vo5CfATmFFnSwULWfuhgI0xhiVBARQOGyolpVnwItCmkz aJYqYwftrgL7mSK+w8ub3pHcOC9JgW7bAgBNXPq1NvI3u/4CsOlrrLTGHJkMIcU/TSh8 KEwem+sApeX0ymtJ+HmN5yGUf25AoUSvZEbaq5lnqza7EviGw8NaLtShahv6PG2bQIWU VOIm3zJzAmvMtkpzx0ZcaCutwdtnl6rXWNKjYQuxBm1bbpHX3fI63k0lFag2GhoRsDaN bQErOPEFiuqaimYEHebh3Y6Vn8W1olq810dLUpzji/q5OlFkdqi0P480KF78QbAcjkBe TegA== X-Gm-Message-State: AOAM533pFD03tnfLAwGsEsyK5+iCfasm992/52B1NCGkFhMPcP8gl5qI m5zYo3kF6MeFS4iKJif3erEJkQ== X-Google-Smtp-Source: ABdhPJwou5BEYWSd/xUxT2GeNB16rp4kcBoAqcHUIvEKaNQ2yShNSPgWx+KoP9xDhXk68ZK2YTAcEg== X-Received: by 2002:a17:90a:414d:: with SMTP id m13mr1398726pjg.229.1610409874174; Mon, 11 Jan 2021 16:04:34 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id i10sm924251pgt.85.2021.01.11.16.04.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:04:33 -0800 (PST) Subject: Re: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-7-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <6e1eec7e-35de-4276-68ec-7e12cb73a699@linaro.org> Date: Mon, 11 Jan 2021 14:04:30 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-7-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:04:37 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in > secure mode, though it can only be AArch64. > > This patch adds the target EL for exceptions from 64-bit S-EL2. > > It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure > mode. Those values were never used in practice as the effective value of > HCR was always 0 in secure mode. > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/helper.c | 10 +++++----- > target/arm/op_helper.c | 4 ++-- > 2 files changed, 7 insertions(+), 7 deletions(-) At some point I think it would be worthwhile to convert that target_el_table back to code. It is really hard to follow with 6 indicies. Not your fault. Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:05:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7Bs-00053l-C2 for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:05:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7Br-000525-A5 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:05:39 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:39690) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7Bp-0004Ec-HC for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:05:39 -0500 Received: by mail-pg1-x532.google.com with SMTP id 30so229587pgr.6 for ; Mon, 11 Jan 2021 16:05:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ulNC+wVGmUmcJ5b/YZvDBl+z1bvwMpgx0vSChiFkux0=; b=lXt8gsepYT6nura0aTzs6RE3ABWLYv0Km8GmGBiCogpFfpHO+0z5JkDOp5r/61bzdC 8O6Osupb12v/geKOY+kiV4OWWUSWLpwrDkAwYMagvUGZXBMHIxl6nVMjlmXcZKkZ961m CLbMsEtV9s8khVj0g1ptsQpAkDoh+CdVU90XsKcYKnF9n2q8uEiDVx5StVmqaOFmIo5g eUjLYgpzUw6xF8OwVYf0fWnXTDyL1iKXOfg5YnzOeNitHpkx7GrLJb4Hlf2X3vfXbaGk ZeObHLlVuk0YbUVRxl/NSpl6xYaJbZ9eUngAC643q4nU8iKRjm9ND6fRcAALWT/r+4J5 zH2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ulNC+wVGmUmcJ5b/YZvDBl+z1bvwMpgx0vSChiFkux0=; b=UjIzU5EvHo/HzVmNsuqaulXYF0qynIT7F1xuxdzOKoj2Pl0cqqxWOSLJJstBNzvcW+ NXWHPZMJZ8k9I3VJ9efai/MxZ9CCpRj9AnkSIZbLRen0MM5za0T0gUl+atm/gVlFHEAa lOJzkui4yFpTJCwGmlPrs9X9yV7wWO/2joywC5hR2yrLDCSuzpcpQKs7lxJN6OemJLcw 0ghUJx0hO/fScYyqLTaQHZocGlatJKgxZhNSOGiOZnLVXzstGHjaRGbYGyP7KRbCnIXs vupk/SyYuu7K6oX/Er4uBJuy/9gKhTAssBeLn0QAISHKVEusUbUdhNbddQSqIFEhoao/ /BVQ== X-Gm-Message-State: AOAM530lnin5rf0SUGPDkQgxVRbevB3khyGa+VoeP6iKIiZQ1bY5LSF0 nG0oDWeuQ1FKXdqPqEeDiisvxw== X-Google-Smtp-Source: ABdhPJyPEH8JkdwOtOytQKQJ1fIl7VbRc/kM+F1udWXNkgeysDNiGKAA3xpaxdHMQTYWVp/5vB0psw== X-Received: by 2002:a65:488d:: with SMTP id n13mr1828443pgs.315.1610409935972; Mon, 11 Jan 2021 16:05:35 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id a131sm810273pfd.171.2021.01.11.16.05.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:05:35 -0800 (PST) Subject: Re: [PATCH 09/18] target/arm: add ARMv8.4-SEL2 system registers To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-9-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <7179fb23-01b9-83d3-3aac-64ed3d4649d1@linaro.org> Date: Mon, 11 Jan 2021 14:05:32 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-9-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:05:39 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/cpu.h | 7 +++++++ > target/arm/helper.c | 24 ++++++++++++++++++++++++ > 2 files changed, 31 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:06:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7Cn-0005jq-Su for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:06:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7Cm-0005hX-V2 for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:06:36 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:45391) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7Cl-0004U3-BA for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:06:36 -0500 Received: by mail-pg1-x529.google.com with SMTP id v19so214864pgj.12 for ; Mon, 11 Jan 2021 16:06:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=n5FZap7gAE9g9CaJLrmxs5NNKN4tivOtO8uV3BqCazA=; b=oUDSGYbqwvbd/AGuVhBI5b9EHnBFmXCLv/Zm9FcJqO9sF9enE1f4kQXEM5YhlWeaHL pRku1S/YZGTPwgB8PiyRoJ2aCNavkAaexP0Ft9nXn//bYNl6mDMB5F9WXu1IA1c6lQK/ /8Kq9hoTiC6Umt5Qicgz4c5k8nM2j3MwhRGi7JIm6l7MhjTeRk0UUrmd8EBVNAccpqp5 hbcey7p1yEBRxPhsIoTdJ3y/yRJbsufPq3eNEhkK2ndsOJEGRx3r/TWEC+7VHwG5S1L/ 0cPtLL1onsUgtxxWpgwpMlUk1u4HPnP+lB62gZaryx2FvQ0wHgquH32QBTnX5Avw/qZ6 N+vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=n5FZap7gAE9g9CaJLrmxs5NNKN4tivOtO8uV3BqCazA=; b=Tcu4W9xZp6EcJjH6Jo8uXnQWCPaya2lGhPcXUUGKQ7tYcz7Hp/6eJPCZy69b5EEOqd EZwWBTQUFfLJYrSdQQgxA4zuZiXXrgFigBa9D8KJbIFDpL7BtUCJWChQdsTa2f5UWeNQ SG5UFyWVDjRJAAza6K3xVSuypXAerJYCwVwa/lCi+Pe+sUnFhpUuS0JUyfYwTAZSgcOG QNQ4xSBnPEM5TIASYuUVJkLJYVUoJFR9UfmrwET4zO8gFPpqfL3FHd9bC6jDXEAahxGV 9ncveldhCKC+Nm2CT0RUw8yB1gvTvATmPp3U7OePmNyO929NXp0NlUufh2gET5j+cGf2 sotA== X-Gm-Message-State: AOAM531In4Spr/nkFio/DJ8ZBpO3TYYlREYckBSAqftfa4CxysSkv+mG zjRvjwnYjzQdJU2MZzXv7nDGAg== X-Google-Smtp-Source: ABdhPJxQbq2YrRsU+AaOOMlbRu23EY6lnoju/rb8ECuAxHp8YpqMzc1RDBbiuA381gmVVmlpRzhWwQ== X-Received: by 2002:a63:1c1d:: with SMTP id c29mr1953624pgc.94.1610409993979; Mon, 11 Jan 2021 16:06:33 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id 22sm603390pjw.19.2021.01.11.16.06.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:06:33 -0800 (PST) Subject: Re: [PATCH 12/18] target/arm: translate NS bit in page-walks To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-12-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Mon, 11 Jan 2021 14:06:30 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-12-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:06:37 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/helper.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:08:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7E8-00074v-Be for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:08:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7E3-00071u-GR for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:07:57 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:37238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7E0-0004Zk-1e for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:07:55 -0500 Received: by mail-pg1-x531.google.com with SMTP id z21so237988pgj.4 for ; Mon, 11 Jan 2021 16:07:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=B4R9c4QGGtVFWzG5gQIOM9OZ64Swp1/U+9Tebu3m9Rg=; b=lj25ddbbf1k3byjAibmah1THDxMzi+F4XrQB6wgzMc2y7jT2j3vsO5ktjpL8btfMKg M7hfz2Fz0X98aYBwhd4/zC7Z8er2fto5Wm4bwLkmWRS1OTc/Y5WhR7DynLpBrlzWnDqH BJZpQKjzc4/GkTISLEPtNGQp1UyXSdrsKjYomEkgQvi9CyW9r+v+qF2El+//pQ3hzfc9 1D48QYa6dslhcv7NwcO1zY4eKdFaCaY+oCGlZnC7HsODRY/zrjETQest4pO8tpSshEwr 1Ps4gKqJZpogergUPRtlesJ9ex6xj3NeWNEECfqfz0u27wMKbhHtyDUbSLe9t+1ubxmK n2Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=B4R9c4QGGtVFWzG5gQIOM9OZ64Swp1/U+9Tebu3m9Rg=; b=qVpKrQdhbkGlqqs31RricS+Ox9onR+BioIDtOjbQV4p/MRo5OSleMuTmDVMuXMDYwd G2CgQx78Po5a9H84wPtf9UVggAOPdVtdk/EyyGtcja8ErEeQ8j7VO3nl46vQWJf7+zVk Ji/KbQOBqRoq6IEros3YsNTtAc/wACOgC37qogBJ9l1+sD28ce/4wOJC+y/b0t3RFzZF +pZzzDIDKvRvjMkhpJMoqR8g8x/Jd0WF7uYv6m9W9bElVi18BQPPts4ZbqE66a0L2b1H 6NQ8LbX4YaxM5T7VZzPCgsELQaZiW7hlUhIelJstnmscL6q/9dqhaGbuqR0YGoP6PWqC kICA== X-Gm-Message-State: AOAM531n1WHZRgblWqb2noW+uKwVpXi9dqCIwuc4i9+y0yHjyI1/ES4+ svstJG3mHSngI8JBPkCbepSUXA== X-Google-Smtp-Source: ABdhPJzMuu2hE5MYH43BlTdw5laD+vz23jzLkLF9MJ+Bzq5Q3XCWusvWQe9TCSW+Qaw5bf9pMyUpog== X-Received: by 2002:a62:e314:0:b029:19e:4cc:dc6f with SMTP id g20-20020a62e3140000b029019e04ccdc6fmr1785969pfh.33.1610410070704; Mon, 11 Jan 2021 16:07:50 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id b17sm581477pjz.44.2021.01.11.16.07.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:07:49 -0800 (PST) Subject: Re: [PATCH 13/18] target/arm: generalize 2-stage page-walk condition To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-13-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Mon, 11 Jan 2021 14:07:46 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-13-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:07:57 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > The stage_1_mmu_idx() already effectively keeps track of which > translation regimes have two stages. Don't hard-code another test. > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/helper.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:10:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7Gh-0000Km-7z for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:10:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7Ge-0000IV-IS for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:10:37 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:55022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7GU-0004sF-KE for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:10:36 -0500 Received: by mail-pj1-x1035.google.com with SMTP id cq1so330337pjb.4 for ; Mon, 11 Jan 2021 16:10:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Dd62GxI47Qg5ur99WgAfy8RqqlPGaSImffJfdafuMuA=; b=dkE5bz/C1E8YU1xyVaO/99esRZ4rd2Mdrn+pCdZBch2dWww+V1E9vac5Ga8B31A9+2 BRxw3/bMnbliYw4M8CIdCylXnSb5XteWmoW8oeZT8bliYjweW7lTclGm8aFMliA06d3s FzL01vQiCLHKrJzhhf489UJsOwFPmpTMkG/QrG1cqA04X02tb/0tcpfBtyxC22wUx3wp 5uuWlatHoF9/YOOeUxEIzKbKQ5mzcM7kxAR/bqSrEhgCaq5MgnkKOQO3slc0KpvOuROx pfRIJMZ3sw6ZMAnHi2yRL60TmBkALerlGloyVyf3Jk1QYUGuKoTmXVxI9sckuBo/nzb3 QQvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Dd62GxI47Qg5ur99WgAfy8RqqlPGaSImffJfdafuMuA=; b=PHiN2+ga/VYVdgSudHX47/ieSCHnZoz+MHuSCoPKMSq/oMuURW0VBfqHmcuUzZHQGR kbqeBucZvfljjCx7xKPsMegQ3lua/pCr5XK9kYXYeBx2NutWYfN03/UqcJUJ+J28bfqJ LebAThoKIRVW5BxIbFeZeAx78svkeWFjQrOkaZbThLgSaoofyJepoVQdbbSgLvuOi752 xzMrRdukqOrjWRgGobIxt+HSJttx2Sd5nDsNkvIBIdSyNlzyQkoSGcfTynsJn4SXLVKn v0iltKyqCsKxea2JnAk2+hBFgbk058iLLwZ0QnW09Qwg/UdkC3avGKVCT31o6LDZ0Tk5 dAeA== X-Gm-Message-State: AOAM531Qh5kutpXbeWEJ5AZlIoHxzfOf06IKM+6LOW1pC59r9ItqojSM sXMiVsgijXdte3dD/YCy4QdOtg== X-Google-Smtp-Source: ABdhPJxUnQdQa15z2moPjm0Xv8MfY9zX01mWzyJ/fu3aX6MIlzC+6Vs9iBR+ZPH2TpFrQCxmeFafMQ== X-Received: by 2002:a17:90a:49c5:: with SMTP id l5mr1449165pjm.116.1610410224798; Mon, 11 Jan 2021 16:10:24 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id y15sm625420pju.13.2021.01.11.16.10.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:10:24 -0800 (PST) Subject: Re: [PATCH 15/18] target/arm: set HPFAR_EL2.NS on secure stage 2 faults To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-15-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <9b4e8adb-168c-34fa-2ed3-89b883a93295@linaro.org> Date: Mon, 11 Jan 2021 14:10:21 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-15-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:10:37 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/cpu.h | 2 ++ > target/arm/helper.c | 6 ++++++ > target/arm/internals.h | 2 ++ > target/arm/tlb_helper.c | 3 +++ > 4 files changed, 13 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:13:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7Je-0002Bo-VD for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:13:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7Jb-00029C-HG for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:13:40 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:41148) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7JW-0005KQ-UL for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:13:39 -0500 Received: by mail-pl1-x635.google.com with SMTP id y8so401881plp.8 for ; Mon, 11 Jan 2021 16:13:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=FGz41Yi7w1wzxoCAn+MLhQyAagGUSJEur9OPosgee14=; b=rJA9lSUYJGhpn7UhRnszTOviey4gGX5UrbnsL/yBCid3Uj6g35E23rTwoaNxlPk6Hs AuSeBNyemKBWuN7ykAofGP6eapYftUoEsVyV6g+64vg7rV8ABUuZTc67udqqu/iXcpS6 S+mScWVURnKo9555uJPrvhXqFb1AGdRE6BZ4edfCuA4RUXrgpbVPATk6+EQIvLwSJDxm Q10n4rlM5wPJ4/cxwxztcwSF6+Mh0jbCO6GlCXkZ/QKJzunMfcUw/9b/51noRVXXeVnO nebu3m/05XnBXpZMAjjw9IJgtF67Zc3BAThYOdQ9UThSOwjy7kA56ZVeNxNHCRDJyccv XHhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=FGz41Yi7w1wzxoCAn+MLhQyAagGUSJEur9OPosgee14=; b=SEMH0eayiD5giZ16duIIZbnhICd6XXr81g/5KLunp8/zffPLOzjHjFRrW6sC31fnMi RKCFmlGCwZQb73nXony8S1RJbzGxksFgXmKj5GPUnQZChs+PZBrpr5gvD19R1WLiedY+ rJBL10lCZqzGT+K2TGUBDIGiOBU4id4XbUHKriKAbuu65/2Izm5ocxuYNHYhTlMVqKr4 9y4HF6w8FIJm3EM5ZjEJ1gpZpDiC9j4OLQwb4Js1zsuYFu3YCwAKQKTLBK3NDAtt8wm7 qN7iqwD+wqSGsu22f5wxzov062eE35b/2J9v/yW+PSAIRA0aBAy+XwONR+O7ldBzQTN7 cqdg== X-Gm-Message-State: AOAM532gGInVfqkBX+4RJs0gXh6mezHTkrtfAwlxFH7CVTe9EwmRl6cm bayuW1HcqiF02+5Nghjkv/AxFQ== X-Google-Smtp-Source: ABdhPJyWNW1GRrKrC7md9Eu+rW4LZImu3e9XEykBJ+NOaX72HJJZKiUNnLH5/8QjkZb1WfOyQXcVZQ== X-Received: by 2002:a17:90a:fe86:: with SMTP id co6mr589886pjb.96.1610410413039; Mon, 11 Jan 2021 16:13:33 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id d6sm611060pjh.24.2021.01.11.16.13.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:13:32 -0800 (PST) Subject: Re: [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-16-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <4e32ca89-51aa-85d1-0a8f-e9aa7e037be4@linaro.org> Date: Mon, 11 Jan 2021 14:13:29 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-16-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:13:40 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > @@ -3297,7 +3301,7 @@ typedef ARMCPU ArchCPU; > * We put flags which are shared between 32 and 64 bit mode at the top > * of the word, and flags which apply to only one mode at the bottom. > * > - * 31 20 18 14 9 0 > + * 31 20 19 14 9 0 > * +--------------+-----+-----+----------+--------------+ > * | | | TBFLAG_A32 | | > * | | +-----+----------+ TBFLAG_AM32 | > @@ -3346,6 +3350,7 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) > * the same thing as the current security state of the processor! > */ > FIELD(TBFLAG_A32, NS, 17, 1) > +FIELD(TBFLAG_A32, EEL2, 18, 1) Note that via other in-flight patch sets we have run out of bits here. I've rearranged them in https://patchew.org/QEMU/20210111190113.303726-1-richard.henderson@linaro.org/ This should be nothing but a minor confict to fix up. r~ From MAILER-DAEMON Mon Jan 11 19:14:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7K4-0002jl-9u for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:14:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7K2-0002gT-9e for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:14:06 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:37346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kz7K0-0005NP-QL for qemu-arm@nongnu.org; Mon, 11 Jan 2021 19:14:06 -0500 Received: by mail-pj1-x1034.google.com with SMTP id b5so553878pjk.2 for ; Mon, 11 Jan 2021 16:14:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=RLBeLmNm4wbSY3ku5Iqz7J1SWOX3iUZ4RuiRWaCWtO4=; b=MKxI0yHb5zJXOT3KjRg1u889VmA3axTZAEL2ph/bNWmvyiunHO1nQzOK0phohNrOeU 0vl+Qt7tig1kAqurQmoeFePVJOcxPbdVMgInNHXgjEWyEt0mhi9zfIlmsCa29o6Fv/r0 PAQjkEzXSSmPKITgXvjO/1VLs1zFkSO75mBSD0yJhvlHChdMngLFcxvS8jrSvolVmA4V i2UmHWZBKVVokDgw6O3sYY5QdorA5mzhs6ezWlS5N8TK8pgGzy0Pi4gvSTpcx0iIKn6f Kn03rihFg2Kdk+i42YDLdMgPiZ8XnBg+h4MsdDUOwkjm5cobuT2DH00Qy48Xh9QqtgYc VzvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=RLBeLmNm4wbSY3ku5Iqz7J1SWOX3iUZ4RuiRWaCWtO4=; b=q9hSorp2feWuzhZ1/YzgAy4JL1rgmTHGWEyBV/3wocG4DzL0qRSNm5x90j14RSeagm z1sAtpqlOqdXkFdrebZqx7itmgNGr+d53xN8gB4U9usR2ZJhq2qjmqqEbP5BxDGil8Ok xqi4YcZRvGgCZR8OnSWsGwNETGlhGjTO2fCZ9DgvPBnVPB3LLW9vfAfgiZ0gI7YysiAE 6+zxnuFrYwMwoRgd1q2NgMzBpjTqZIzUlmDDihk0Sad8cU4AZz6uBGGEotl8WKleftCR 2oYLcWAfcaWDqAa1ySJA+9FMeFFKAg/7+6BTRNMEh+5j8LVlZcsorxc045Z0NCMS5+WN KNGg== X-Gm-Message-State: AOAM532PNxo71XZ5nHruWWW11xepapY8znSltU5bmkxHZs6LU/A92phB Aupl46R8NSBBUk1vGqZY5xE1RwkhUJcDkQ== X-Google-Smtp-Source: ABdhPJwj6jZ1GuGL9nWRShCpa/j9ggpDHDIEDc4pSIZ0mO5HDdEeO5qGHr7qn9unxInIhilL6wLSlw== X-Received: by 2002:a17:90a:bb8c:: with SMTP id v12mr1427521pjr.227.1610410443624; Mon, 11 Jan 2021 16:14:03 -0800 (PST) Received: from [10.25.18.119] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id gb9sm585357pjb.40.2021.01.11.16.14.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:14:03 -0800 (PST) Subject: Re: [PATCH 18/18] target/arm: refactor vae1_tlbmask() To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-18-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Mon, 11 Jan 2021 14:14:00 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-18-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:14:06 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/helper.c | 25 +++++++++++-------------- > 1 file changed, 11 insertions(+), 14 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 11 19:17:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kz7Na-0005lZ-JO for mharc-qemu-arm@gnu.org; Mon, 11 Jan 2021 19:17:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7NS-0005kN-US; Mon, 11 Jan 2021 19:17:39 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:37217 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kz7NN-0005tf-WC; Mon, 11 Jan 2021 19:17:37 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4DFB3Y1MXYz9sXL; Tue, 12 Jan 2021 11:17:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1610410649; bh=1m9CFUJWDc1K3efCRtER5BXji20nMK9ORxssP08gPOI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=EmK8yFmNjhty2H8d/TeTkv4G2pYqTYgSKL2CctRvWlQ2XQQqINNr8LJh7iorythyL qVp/iW0DudL/a0N6ucE1Lzl1KphdI0wDdkF5OEhrZuSqxCkg7jDVC7u0OaTL71N9Bv RdXim3HExE/tugdoXsGjR/mPpghdmgIEIrVqVY2U= Date: Tue, 12 Jan 2021 11:17:20 +1100 From: David Gibson To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?iso-8859-1?Q?C=E9dric?= Le Goater , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , Richard Henderson , Alex =?iso-8859-1?Q?Benn=E9e?= , Laurent Vivier , Thomas Huth , Stefan Hajnoczi , Jiaxun Yang Subject: Re: [PATCH 2/2] sysemu: Let VMChangeStateHandler take boolean 'running' argument Message-ID: <20210112001720.GH3051@yekko.fritz.box> References: <20210111152020.1422021-1-philmd@redhat.com> <20210111152020.1422021-3-philmd@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="+QwZB9vYiNIzNXIj" Content-Disposition: inline In-Reply-To: <20210111152020.1422021-3-philmd@redhat.com> Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:17:39 -0000 --+QwZB9vYiNIzNXIj Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jan 11, 2021 at 04:20:20PM +0100, Philippe Mathieu-Daud=E9 wrote: > The 'running' argument from VMChangeStateHandler does not require > other value than 0 / 1. Make it a plain boolean. >=20 > Signed-off-by: Philippe Mathieu-Daud=E9 ppc parts Acked-by: David Gibson > --- > include/sysemu/runstate.h | 10 ++++++++-- > target/arm/kvm_arm.h | 2 +- > target/ppc/cpu-qom.h | 2 +- > accel/xen/xen-all.c | 2 +- > audio/audio.c | 2 +- > block/block-backend.c | 2 +- > gdbstub.c | 2 +- > hw/block/pflash_cfi01.c | 2 +- > hw/block/virtio-blk.c | 2 +- > hw/display/qxl.c | 2 +- > hw/i386/kvm/clock.c | 2 +- > hw/i386/kvm/i8254.c | 2 +- > hw/i386/kvmvapic.c | 2 +- > hw/i386/xen/xen-hvm.c | 2 +- > hw/ide/core.c | 2 +- > hw/intc/arm_gicv3_its_kvm.c | 2 +- > hw/intc/arm_gicv3_kvm.c | 2 +- > hw/intc/spapr_xive_kvm.c | 2 +- > hw/misc/mac_via.c | 2 +- > hw/net/e1000e_core.c | 2 +- > hw/nvram/spapr_nvram.c | 2 +- > hw/ppc/ppc.c | 2 +- > hw/ppc/ppc_booke.c | 2 +- > hw/s390x/tod-kvm.c | 2 +- > hw/scsi/scsi-bus.c | 2 +- > hw/usb/hcd-ehci.c | 2 +- > hw/usb/host-libusb.c | 2 +- > hw/usb/redirect.c | 2 +- > hw/vfio/migration.c | 2 +- > hw/virtio/virtio-rng.c | 2 +- > hw/virtio/virtio.c | 2 +- > net/net.c | 2 +- > softmmu/memory.c | 2 +- > softmmu/runstate.c | 2 +- > target/arm/kvm.c | 2 +- > target/i386/kvm/kvm.c | 2 +- > target/i386/sev.c | 2 +- > target/i386/whpx/whpx-all.c | 2 +- > target/mips/kvm.c | 4 ++-- > ui/gtk.c | 2 +- > ui/spice-core.c | 2 +- > 41 files changed, 49 insertions(+), 43 deletions(-) >=20 > diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h > index 3ab35a039a0..a5356915734 100644 > --- a/include/sysemu/runstate.h > +++ b/include/sysemu/runstate.h > @@ -10,7 +10,7 @@ bool runstate_is_running(void); > bool runstate_needs_reset(void); > bool runstate_store(char *str, size_t size); > =20 > -typedef void VMChangeStateHandler(void *opaque, int running, RunState st= ate); > +typedef void VMChangeStateHandler(void *opaque, bool running, RunState s= tate); > =20 > VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandle= r *cb, > void *opaque); > @@ -20,7 +20,13 @@ VMChangeStateEntry *qdev_add_vm_change_state_handler(D= eviceState *dev, > VMChangeStateHandle= r *cb, > void *opaque); > void qemu_del_vm_change_state_handler(VMChangeStateEntry *e); > -void vm_state_notify(int running, RunState state); > +/** > + * vm_state_notify: Notify the state of the VM > + * > + * @running: whether the VM is running or not. > + * @state: the #RunState of the VM. > + */ > +void vm_state_notify(bool running, RunState state); > =20 > static inline bool shutdown_caused_by_guest(ShutdownCause cause) > { > diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h > index eb81b7059eb..68ec970c4f4 100644 > --- a/target/arm/kvm_arm.h > +++ b/target/arm/kvm_arm.h > @@ -352,7 +352,7 @@ void kvm_arm_get_virtual_time(CPUState *cs); > */ > void kvm_arm_put_virtual_time(CPUState *cs); > =20 > -void kvm_arm_vm_state_change(void *opaque, int running, RunState state); > +void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); > =20 > int kvm_arm_vgic_probe(void); > =20 > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index 63b9e8632ca..118baf8d41f 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -218,7 +218,7 @@ extern const VMStateDescription vmstate_ppc_timebase; > .offset =3D vmstate_offset_value(_state, _field, PPCTimebase), \ > } > =20 > -void cpu_ppc_clock_vm_state_change(void *opaque, int running, > +void cpu_ppc_clock_vm_state_change(void *opaque, bool running, > RunState state); > #endif > =20 > diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c > index 878a4089d97..3756aca27be 100644 > --- a/accel/xen/xen-all.c > +++ b/accel/xen/xen-all.c > @@ -122,7 +122,7 @@ static void xenstore_record_dm_state(struct xs_handle= *xs, const char *state) > } > =20 > =20 > -static void xen_change_state_handler(void *opaque, int running, > +static void xen_change_state_handler(void *opaque, bool running, > RunState state) > { > if (running) { > diff --git a/audio/audio.c b/audio/audio.c > index b48471bb3f6..f2d56e7e57d 100644 > --- a/audio/audio.c > +++ b/audio/audio.c > @@ -1549,7 +1549,7 @@ static int audio_driver_init(AudioState *s, struct = audio_driver *drv, > } > } > =20 > -static void audio_vm_change_state_handler (void *opaque, int running, > +static void audio_vm_change_state_handler (void *opaque, bool running, > RunState state) > { > AudioState *s =3D opaque; > diff --git a/block/block-backend.c b/block/block-backend.c > index ce78d30794a..9175eb237a2 100644 > --- a/block/block-backend.c > +++ b/block/block-backend.c > @@ -163,7 +163,7 @@ static const char *blk_root_get_name(BdrvChild *child) > return blk_name(child->opaque); > } > =20 > -static void blk_vm_state_changed(void *opaque, int running, RunState sta= te) > +static void blk_vm_state_changed(void *opaque, bool running, RunState st= ate) > { > Error *local_err =3D NULL; > BlockBackend *blk =3D opaque; > diff --git a/gdbstub.c b/gdbstub.c > index d99bc0bf2ea..9f2998f8d03 100644 > --- a/gdbstub.c > +++ b/gdbstub.c > @@ -2691,7 +2691,7 @@ void gdb_set_stop_cpu(CPUState *cpu) > } > =20 > #ifndef CONFIG_USER_ONLY > -static void gdb_vm_state_change(void *opaque, int running, RunState stat= e) > +static void gdb_vm_state_change(void *opaque, bool running, RunState sta= te) > { > CPUState *cpu =3D gdbserver_state.c_cpu; > g_autoptr(GString) buf =3D g_string_new(NULL); > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index ccf326793db..badcbccf012 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -1014,7 +1014,7 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, Dri= veInfo *dinfo) > loc_pop(&loc); > } > =20 > -static void postload_update_cb(void *opaque, int running, RunState state) > +static void postload_update_cb(void *opaque, bool running, RunState stat= e) > { > PFlashCFI01 *pfl =3D opaque; > =20 > diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c > index bac2d6fa2b2..5207ef617f0 100644 > --- a/hw/block/virtio-blk.c > +++ b/hw/block/virtio-blk.c > @@ -870,7 +870,7 @@ static void virtio_blk_dma_restart_bh(void *opaque) > virtio_blk_process_queued_requests(s, true); > } > =20 > -static void virtio_blk_dma_restart_cb(void *opaque, int running, > +static void virtio_blk_dma_restart_cb(void *opaque, bool running, > RunState state) > { > VirtIOBlock *s =3D opaque; > diff --git a/hw/display/qxl.c b/hw/display/qxl.c > index 431c1070967..d22e84ba13e 100644 > --- a/hw/display/qxl.c > +++ b/hw/display/qxl.c > @@ -1992,7 +1992,7 @@ static void qxl_dirty_surfaces(PCIQXLDevice *qxl) > } > } > =20 > -static void qxl_vm_change_state_handler(void *opaque, int running, > +static void qxl_vm_change_state_handler(void *opaque, bool running, > RunState state) > { > PCIQXLDevice *qxl =3D opaque; > diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c > index 2d8a3663693..51872dd84c0 100644 > --- a/hw/i386/kvm/clock.c > +++ b/hw/i386/kvm/clock.c > @@ -162,7 +162,7 @@ static void do_kvmclock_ctrl(CPUState *cpu, run_on_cp= u_data data) > } > } > =20 > -static void kvmclock_vm_state_change(void *opaque, int running, > +static void kvmclock_vm_state_change(void *opaque, bool running, > RunState state) > { > KVMClockState *s =3D opaque; > diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c > index c73254e8866..c558893961b 100644 > --- a/hw/i386/kvm/i8254.c > +++ b/hw/i386/kvm/i8254.c > @@ -239,7 +239,7 @@ static void kvm_pit_irq_control(void *opaque, int n, = int enable) > kvm_pit_put(pit); > } > =20 > -static void kvm_pit_vm_state_change(void *opaque, int running, > +static void kvm_pit_vm_state_change(void *opaque, bool running, > RunState state) > { > KVMPITState *s =3D opaque; > diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c > index 2c1898032e4..46315445d22 100644 > --- a/hw/i386/kvmvapic.c > +++ b/hw/i386/kvmvapic.c > @@ -748,7 +748,7 @@ static void do_vapic_enable(CPUState *cs, run_on_cpu_= data data) > s->state =3D VAPIC_ACTIVE; > } > =20 > -static void kvmvapic_vm_state_change(void *opaque, int running, > +static void kvmvapic_vm_state_change(void *opaque, bool running, > RunState state) > { > MachineState *ms =3D MACHINE(qdev_get_machine()); > diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c > index 68821d90f52..7ce672e5a5c 100644 > --- a/hw/i386/xen/xen-hvm.c > +++ b/hw/i386/xen/xen-hvm.c > @@ -1235,7 +1235,7 @@ static void xen_main_loop_prepare(XenIOState *state) > } > =20 > =20 > -static void xen_hvm_change_state_handler(void *opaque, int running, > +static void xen_hvm_change_state_handler(void *opaque, bool running, > RunState rstate) > { > XenIOState *state =3D opaque; > diff --git a/hw/ide/core.c b/hw/ide/core.c > index b49e4cfbc6c..b5c6e967b2e 100644 > --- a/hw/ide/core.c > +++ b/hw/ide/core.c > @@ -2677,7 +2677,7 @@ static void ide_restart_bh(void *opaque) > } > } > =20 > -static void ide_restart_cb(void *opaque, int running, RunState state) > +static void ide_restart_cb(void *opaque, bool running, RunState state) > { > IDEBus *bus =3D opaque; > =20 > diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c > index 057cb53f13c..b554d2ede0a 100644 > --- a/hw/intc/arm_gicv3_its_kvm.c > +++ b/hw/intc/arm_gicv3_its_kvm.c > @@ -71,7 +71,7 @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t = value, uint16_t devid) > * > * The tables get flushed to guest RAM whenever the VM gets stopped. > */ > -static void vm_change_state_handler(void *opaque, int running, > +static void vm_change_state_handler(void *opaque, bool running, > RunState state) > { > GICv3ITSState *s =3D (GICv3ITSState *)opaque; > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > index d040a5d1e99..65a4c880a35 100644 > --- a/hw/intc/arm_gicv3_kvm.c > +++ b/hw/intc/arm_gicv3_kvm.c > @@ -743,7 +743,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { > * > * The tables get flushed to guest RAM whenever the VM gets stopped. > */ > -static void vm_change_state_handler(void *opaque, int running, > +static void vm_change_state_handler(void *opaque, bool running, > RunState state) > { > GICv3State *s =3D (GICv3State *)opaque; > diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c > index acc8c3650c4..c0083311607 100644 > --- a/hw/intc/spapr_xive_kvm.c > +++ b/hw/intc/spapr_xive_kvm.c > @@ -504,7 +504,7 @@ static int kvmppc_xive_get_queues(SpaprXive *xive, Er= ror **errp) > * runs again. If an interrupt was queued while the VM was stopped, > * simply generate a trigger. > */ > -static void kvmppc_xive_change_state_handler(void *opaque, int running, > +static void kvmppc_xive_change_state_handler(void *opaque, bool running, > RunState state) > { > SpaprXive *xive =3D opaque; > diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c > index 488d086a17c..ca2f939dd58 100644 > --- a/hw/misc/mac_via.c > +++ b/hw/misc/mac_via.c > @@ -1098,7 +1098,7 @@ static void mac_via_init(Object *obj) > TYPE_ADB_BUS, DEVICE(obj), "adb.0"); > } > =20 > -static void postload_update_cb(void *opaque, int running, RunState state) > +static void postload_update_cb(void *opaque, bool running, RunState stat= e) > { > MacVIAState *m =3D MAC_VIA(opaque); > =20 > diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c > index 4dcb92d966b..b75f2ab8fc1 100644 > --- a/hw/net/e1000e_core.c > +++ b/hw/net/e1000e_core.c > @@ -3298,7 +3298,7 @@ e1000e_autoneg_resume(E1000ECore *core) > } > =20 > static void > -e1000e_vm_state_change(void *opaque, int running, RunState state) > +e1000e_vm_state_change(void *opaque, bool running, RunState state) > { > E1000ECore *core =3D opaque; > =20 > diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c > index 9e51bc82ae4..01f77520146 100644 > --- a/hw/nvram/spapr_nvram.c > +++ b/hw/nvram/spapr_nvram.c > @@ -217,7 +217,7 @@ static int spapr_nvram_pre_load(void *opaque) > return 0; > } > =20 > -static void postload_update_cb(void *opaque, int running, RunState state) > +static void postload_update_cb(void *opaque, bool running, RunState stat= e) > { > SpaprNvram *nvram =3D opaque; > =20 > diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c > index 5cbbff1f8d0..bf28d6bfc8d 100644 > --- a/hw/ppc/ppc.c > +++ b/hw/ppc/ppc.c > @@ -1059,7 +1059,7 @@ static void timebase_load(PPCTimebase *tb) > } > } > =20 > -void cpu_ppc_clock_vm_state_change(void *opaque, int running, > +void cpu_ppc_clock_vm_state_change(void *opaque, bool running, > RunState state) > { > PPCTimebase *tb =3D opaque; > diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c > index 652a21b8064..974c0c8a752 100644 > --- a/hw/ppc/ppc_booke.c > +++ b/hw/ppc/ppc_booke.c > @@ -317,7 +317,7 @@ static void ppc_booke_timer_reset_handle(void *opaque) > * action will be taken. To avoid this we always clear the watchdog stat= e when > * state changes to running. > */ > -static void cpu_state_change_handler(void *opaque, int running, RunState= state) > +static void cpu_state_change_handler(void *opaque, bool running, RunStat= e state) > { > PowerPCCPU *cpu =3D opaque; > CPUPPCState *env =3D &cpu->env; > diff --git a/hw/s390x/tod-kvm.c b/hw/s390x/tod-kvm.c > index 6e21d83181d..0b944774861 100644 > --- a/hw/s390x/tod-kvm.c > +++ b/hw/s390x/tod-kvm.c > @@ -78,7 +78,7 @@ static void kvm_s390_tod_set(S390TODState *td, const S3= 90TOD *tod, Error **errp) > } > } > =20 > -static void kvm_s390_tod_vm_state_change(void *opaque, int running, > +static void kvm_s390_tod_vm_state_change(void *opaque, bool running, > RunState state) > { > S390TODState *td =3D opaque; > diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c > index c349fb7f2d1..f990d5b3b03 100644 > --- a/hw/scsi/scsi-bus.c > +++ b/hw/scsi/scsi-bus.c > @@ -181,7 +181,7 @@ void scsi_req_retry(SCSIRequest *req) > req->retry =3D true; > } > =20 > -static void scsi_dma_restart_cb(void *opaque, int running, RunState stat= e) > +static void scsi_dma_restart_cb(void *opaque, bool running, RunState sta= te) > { > SCSIDevice *s =3D opaque; > =20 > diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c > index aca018d8b5f..98d08c325ea 100644 > --- a/hw/usb/hcd-ehci.c > +++ b/hw/usb/hcd-ehci.c > @@ -2436,7 +2436,7 @@ static int usb_ehci_post_load(void *opaque, int ver= sion_id) > return 0; > } > =20 > -static void usb_ehci_vm_state_change(void *opaque, int running, RunState= state) > +static void usb_ehci_vm_state_change(void *opaque, bool running, RunStat= e state) > { > EHCIState *ehci =3D opaque; > =20 > diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c > index b950501d100..ecbf3f66f42 100644 > --- a/hw/usb/host-libusb.c > +++ b/hw/usb/host-libusb.c > @@ -1755,7 +1755,7 @@ type_init(usb_host_register_types) > static QEMUTimer *usb_auto_timer; > static VMChangeStateEntry *usb_vmstate; > =20 > -static void usb_host_vm_state(void *unused, int running, RunState state) > +static void usb_host_vm_state(void *unused, bool running, RunState state) > { > if (running) { > usb_host_auto_check(unused); > diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c > index 7e9e3fecbfe..17f06f34179 100644 > --- a/hw/usb/redirect.c > +++ b/hw/usb/redirect.c > @@ -1395,7 +1395,7 @@ static void usbredir_chardev_event(void *opaque, QE= MUChrEvent event) > * init + destroy > */ > =20 > -static void usbredir_vm_state_change(void *priv, int running, RunState s= tate) > +static void usbredir_vm_state_change(void *priv, bool running, RunState = state) > { > USBRedirDevice *dev =3D priv; > =20 > diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c > index 00daa50ed81..134bdccc4f8 100644 > --- a/hw/vfio/migration.c > +++ b/hw/vfio/migration.c > @@ -727,7 +727,7 @@ static SaveVMHandlers savevm_vfio_handlers =3D { > =20 > /* ---------------------------------------------------------------------= - */ > =20 > -static void vfio_vmstate_change(void *opaque, int running, RunState stat= e) > +static void vfio_vmstate_change(void *opaque, bool running, RunState sta= te) > { > VFIODevice *vbasedev =3D opaque; > VFIOMigration *migration =3D vbasedev->migration; > diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c > index 76ce9376931..cc8e9f775d8 100644 > --- a/hw/virtio/virtio-rng.c > +++ b/hw/virtio/virtio-rng.c > @@ -133,7 +133,7 @@ static uint64_t get_features(VirtIODevice *vdev, uint= 64_t f, Error **errp) > return f; > } > =20 > -static void virtio_rng_vm_state_change(void *opaque, int running, > +static void virtio_rng_vm_state_change(void *opaque, bool running, > RunState state) > { > VirtIORNG *vrng =3D opaque; > diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c > index b308026596f..38dc623c89e 100644 > --- a/hw/virtio/virtio.c > +++ b/hw/virtio/virtio.c > @@ -3208,7 +3208,7 @@ void virtio_cleanup(VirtIODevice *vdev) > qemu_del_vm_change_state_handler(vdev->vmstate); > } > =20 > -static void virtio_vmstate_change(void *opaque, int running, RunState st= ate) > +static void virtio_vmstate_change(void *opaque, bool running, RunState s= tate) > { > VirtIODevice *vdev =3D opaque; > BusState *qbus =3D qdev_get_parent_bus(DEVICE(vdev)); > diff --git a/net/net.c b/net/net.c > index e1035f21d18..8a85d1e3f7b 100644 > --- a/net/net.c > +++ b/net/net.c > @@ -1341,7 +1341,7 @@ void qmp_set_link(const char *name, bool up, Error = **errp) > } > } > =20 > -static void net_vm_change_state_handler(void *opaque, int running, > +static void net_vm_change_state_handler(void *opaque, bool running, > RunState state) > { > NetClientState *nc; > diff --git a/softmmu/memory.c b/softmmu/memory.c > index 333e1ed7b05..ab7f2e5aa07 100644 > --- a/softmmu/memory.c > +++ b/softmmu/memory.c > @@ -2675,7 +2675,7 @@ static void memory_global_dirty_log_do_stop(void) > MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse); > } > =20 > -static void memory_vm_change_state_handler(void *opaque, int running, > +static void memory_vm_change_state_handler(void *opaque, bool running, > RunState state) > { > if (running) { > diff --git a/softmmu/runstate.c b/softmmu/runstate.c > index c7a67147d17..cb07a65925c 100644 > --- a/softmmu/runstate.c > +++ b/softmmu/runstate.c > @@ -316,7 +316,7 @@ void qemu_del_vm_change_state_handler(VMChangeStateEn= try *e) > g_free(e); > } > =20 > -void vm_state_notify(int running, RunState state) > +void vm_state_notify(bool running, RunState state) > { > VMChangeStateEntry *e, *next; > =20 > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index ffe186de8d1..53d6c4a17eb 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -844,7 +844,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm= _run *run) > return MEMTXATTRS_UNSPECIFIED; > } > =20 > -void kvm_arm_vm_state_change(void *opaque, int running, RunState state) > +void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) > { > CPUState *cs =3D opaque; > ARMCPU *cpu =3D ARM_CPU(cs); > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > index 6dc1ee052d5..170ad55c09c 100644 > --- a/target/i386/kvm/kvm.c > +++ b/target/i386/kvm/kvm.c > @@ -690,7 +690,7 @@ static int kvm_inject_mce_oldstyle(X86CPU *cpu) > return 0; > } > =20 > -static void cpu_update_state(void *opaque, int running, RunState state) > +static void cpu_update_state(void *opaque, bool running, RunState state) > { > CPUX86State *env =3D opaque; > =20 > diff --git a/target/i386/sev.c b/target/i386/sev.c > index 15466068118..e7890f61906 100644 > --- a/target/i386/sev.c > +++ b/target/i386/sev.c > @@ -670,7 +670,7 @@ sev_launch_finish(SevGuestState *sev) > } > =20 > static void > -sev_vm_state_change(void *opaque, int running, RunState state) > +sev_vm_state_change(void *opaque, bool running, RunState state) > { > SevGuestState *sev =3D opaque; > =20 > diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c > index 3b824fc9d7c..850dfe72e75 100644 > --- a/target/i386/whpx/whpx-all.c > +++ b/target/i386/whpx/whpx-all.c > @@ -1318,7 +1318,7 @@ void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) > =20 > static Error *whpx_migration_blocker; > =20 > -static void whpx_cpu_update_state(void *opaque, int running, RunState st= ate) > +static void whpx_cpu_update_state(void *opaque, bool running, RunState s= tate) > { > CPUX86State *env =3D opaque; > =20 > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > index 477692566a4..09945ad2455 100644 > --- a/target/mips/kvm.c > +++ b/target/mips/kvm.c > @@ -37,7 +37,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[= ] =3D { > KVM_CAP_LAST_INFO > }; > =20 > -static void kvm_mips_update_state(void *opaque, int running, RunState st= ate); > +static void kvm_mips_update_state(void *opaque, bool running, RunState s= tate); > =20 > unsigned long kvm_arch_vcpu_id(CPUState *cs) > { > @@ -552,7 +552,7 @@ static int kvm_mips_restore_count(CPUState *cs) > /* > * Handle the VM clock being started or stopped > */ > -static void kvm_mips_update_state(void *opaque, int running, RunState st= ate) > +static void kvm_mips_update_state(void *opaque, bool running, RunState s= tate) > { > CPUState *cs =3D opaque; > int ret; > diff --git a/ui/gtk.c b/ui/gtk.c > index a752aa22be0..a5bf8ed8429 100644 > --- a/ui/gtk.c > +++ b/ui/gtk.c > @@ -672,7 +672,7 @@ static const DisplayChangeListenerOps dcl_egl_ops =3D= { > =20 > /** QEMU Events **/ > =20 > -static void gd_change_runstate(void *opaque, int running, RunState state) > +static void gd_change_runstate(void *opaque, bool running, RunState stat= e) > { > GtkDisplayState *s =3D opaque; > =20 > diff --git a/ui/spice-core.c b/ui/spice-core.c > index 5746d0aae7c..22c77c04151 100644 > --- a/ui/spice-core.c > +++ b/ui/spice-core.c > @@ -622,7 +622,7 @@ static int add_channel(void *opaque, const char *name= , const char *value, > return 0; > } > =20 > -static void vm_change_state_handler(void *opaque, int running, > +static void vm_change_state_handler(void *opaque, bool running, > RunState state) > { > if (running) { --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id j3sm602656pjs.50.2021.01.11.16.19.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:19:59 -0800 (PST) Subject: Re: [PATCH 14/18] target/arm: secure stage 2 translation regime To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-14-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <785079cf-fb1f-a380-00bc-783126090a07@linaro.org> Date: Mon, 11 Jan 2021 14:19:55 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-14-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:20:04 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > @@ -11286,8 +11299,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, > > ap = extract32(attrs, 4, 2); > > - if (mmu_idx == ARMMMUIdx_Stage2) { > - ns = true; > + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { > + if (mmu_idx == ARMMMUIdx_Stage2) { > + ns = true; > + } > xn = extract32(attrs, 11, 2); Does this want an unconditional ns = mmu_idx == ARMMMUIdx_Stage2; When can ns be true and mmu_idx == ARMMMUIdx_Stage2_S? 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id 5sm768987pff.125.2021.01.11.16.20.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 16:20:33 -0800 (PST) Subject: Re: [PATCH 14/18] target/arm: secure stage 2 translation regime To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-14-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Mon, 11 Jan 2021 14:20:31 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201218103759.19929-14-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 00:20:40 -0000 On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > @@ -3586,10 +3586,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > /* fall through */ > case 1: > if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { > - mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN > + mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN > : ARMMMUIdx_Stage1_E1_PAN); > } else { > - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; > + mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; > } > break; Was this a bug that we weren't treating SE10 properly vs two-stage lookup? If so, it warrants mentioning in the patch description. r~ From MAILER-DAEMON Tue Jan 12 02:28:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzE69-0001IP-Mx for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 02:28:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzE66-0001Ht-37; Tue, 12 Jan 2021 02:28:11 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:54768 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzE5y-0003rw-CI; Tue, 12 Jan 2021 02:28:08 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id 7CAC75FCEF; Tue, 12 Jan 2021 08:27:57 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 14/18] target/arm: secure stage 2 translation regime Date: Tue, 12 Jan 2021 09:27:54 +0200 Message-ID: <11670958.O9o76ZdvQC@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: <785079cf-fb1f-a380-00bc-783126090a07@linaro.org> References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-14-remi.denis.courmont@huawei.com> <785079cf-fb1f-a380-00bc-783126090a07@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 07:28:11 -0000 Le tiistaina 12. tammikuuta 2021, 2.19.55 EET Richard Henderson a =C3=A9cri= t : > On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > > @@ -11286,8 +11299,10 @@ static bool get_phys_addr_lpae(CPUARMState *en= v, > > uint64_t address,>=20 > > ap =3D extract32(attrs, 4, 2); > >=20 > > - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { > > - ns =3D true; > > + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { > > + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { > > + ns =3D true; > > + } > >=20 > > xn =3D extract32(attrs, 11, 2); >=20 > Does this want an unconditional >=20 > ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; >=20 > When can ns be true and mmu_idx =3D=3D ARMMMUIdx_Stage2_S? Actually there's a bug. ns is not set at all in secure state 2. =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Tue Jan 12 02:29:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzE7k-00022U-1M for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 02:29:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzE7g-000218-1X; Tue, 12 Jan 2021 02:29:49 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:54780 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzE7e-0004Nf-EP; Tue, 12 Jan 2021 02:29:47 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id 0D8A75FCEF; Tue, 12 Jan 2021 08:29:44 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 14/18] target/arm: secure stage 2 translation regime Date: Tue, 12 Jan 2021 09:29:43 +0200 Message-ID: <5671680.lOV4Wx5bFT@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-14-remi.denis.courmont@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 07:29:49 -0000 Le tiistaina 12. tammikuuta 2021, 2.20.31 EET Richard Henderson a =C3=A9cri= t : > On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > > @@ -3586,10 +3586,10 @@ static void ats_write(CPUARMState *env, const > > ARMCPRegInfo *ri, uint64_t value)>=20 > > /* fall through */ > > =20 > > case 1: > > if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { > >=20 > > - mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN > > + mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN > >=20 > > : ARMMMUIdx_Stage1_E1_PAN); > > =20 > > } else { > >=20 > > - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : > > ARMMMUIdx_Stage1_E1; > > + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : > > ARMMMUIdx_Stage1_E1; > > >=20 > > } > > break; >=20 > Was this a bug that we weren't treating SE10 properly vs two-stage lookup= ?=20 > If so, it warrants mentioning in the patch description. I don't think so. There was no Stage1_SE1 before this patch in the first pl= ace. =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Tue Jan 12 02:34:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzEBp-0003kf-6V for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 02:34:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzEBn-0003jb-3i; Tue, 12 Jan 2021 02:34:03 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:54816 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzEBl-0005sJ-CU; Tue, 12 Jan 2021 02:34:02 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id A13DC5FCEF; Tue, 12 Jan 2021 08:33:58 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension Date: Tue, 12 Jan 2021 09:33:58 +0200 Message-ID: <4284205.LvFx2qVVIh@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: <4e32ca89-51aa-85d1-0a8f-e9aa7e037be4@linaro.org> References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-16-remi.denis.courmont@huawei.com> <4e32ca89-51aa-85d1-0a8f-e9aa7e037be4@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 07:34:03 -0000 Le tiistaina 12. tammikuuta 2021, 2.13.29 EET Richard Henderson a =C3=A9cri= t : > On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > > @@ -3297,7 +3301,7 @@ typedef ARMCPU ArchCPU; > >=20 > > * We put flags which are shared between 32 and 64 bit mode at the top > > * of the word, and flags which apply to only one mode at the bottom. > > * > >=20 > > - * 31 20 18 14 9 0 > > + * 31 20 19 14 9 0 > >=20 > > * +--------------+-----+-----+----------+--------------+ > > * | | | TBFLAG_A32 | | > > * | | +-----+----------+ TBFLAG_AM32 | > >=20 > > @@ -3346,6 +3350,7 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) > >=20 > > * the same thing as the current security state of the processor! > > */ > > =20 > > FIELD(TBFLAG_A32, NS, 17, 1) > >=20 > > +FIELD(TBFLAG_A32, EEL2, 18, 1) >=20 > Note that via other in-flight patch sets we have run out of bits here. I= 've > rearranged them in >=20 > https://patchew.org/QEMU/20210111190113.303726-1-richard.henderson@linaro= =2Eor > g/ >=20 > This should be nothing but a minor confict to fix up. I think we should get rid of that flag that's hardly if at all ever going t= o be=20 used. It should be possible to bypass gen_exception*() straight to=20 gen_helper_exception_with_syndrome(), so that the target EL can be computed= at=20 run-time. =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Tue Jan 12 04:04:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzFb7-0004So-6m for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 04:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzFb4-0004S5-LZ; Tue, 12 Jan 2021 04:04:14 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55344 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzFb2-0002zG-Ad; Tue, 12 Jan 2021 04:04:14 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id ADF4F5FCEF; Tue, 12 Jan 2021 10:04:07 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table Date: Tue, 12 Jan 2021 11:04:05 +0200 Message-ID: <4589283.GXAFRqVoOG@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: <6e1eec7e-35de-4276-68ec-7e12cb73a699@linaro.org> References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-7-remi.denis.courmont@huawei.com> <6e1eec7e-35de-4276-68ec-7e12cb73a699@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 09:04:15 -0000 Le tiistaina 12. tammikuuta 2021, 2.04.30 EET Richard Henderson a =C3=A9cri= t : > On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > > From: R=C3=A9mi Denis-Courmont > >=20 > > With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in > > secure mode, though it can only be AArch64. > >=20 > > This patch adds the target EL for exceptions from 64-bit S-EL2. > >=20 > > It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure > > mode. Those values were never used in practice as the effective value of > > HCR was always 0 in secure mode. > >=20 > > Signed-off-by: R=C3=A9mi Denis-Courmont > > --- > >=20 > > target/arm/helper.c | 10 +++++----- > > target/arm/op_helper.c | 4 ++-- > > 2 files changed, 7 insertions(+), 7 deletions(-) >=20 > At some point I think it would be worthwhile to convert that target_el_ta= ble > back to code. It is really hard to follow with 6 indicies. Not your > fault. I don't have an opinion. I suspect that it will be hard to follow either wa= y.=20 This patch does not add complexity per se. In particular, it does not add y= et=20 another dimension. It just fills missing/unused entries. =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Tue Jan 12 04:56:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzGPM-0002CW-Q0 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 04:56:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzGPJ-0002Al-5O for qemu-arm@nongnu.org; Tue, 12 Jan 2021 04:56:09 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:41670) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzGPH-0003to-0Y for qemu-arm@nongnu.org; Tue, 12 Jan 2021 04:56:08 -0500 Received: by mail-ej1-x62f.google.com with SMTP id g12so448957ejf.8 for ; Tue, 12 Jan 2021 01:56:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=19cL4wojbQuqSJ16gyCwngGtDBfXVS72TXpqKpEjZRU=; b=ATDN9zGmQvQlTZm/zMUTAsNYsYuBX7oeaMLyeiPPoVPoW2TgLIL2jdwc4yMt1PHbHF 3tkcrdG2uJ6Uhsam31xwmHzfW6PZHfOF6m3EnJEBEBugQPfLRty8oLQTDsyYLepJx5Kp BwtgCBRdv+UvNk3fIEV16Js7U1xjHEmnvFo1C8Un5OTs3v/3ORXmvAcUc2o0MFXxlA/6 czIr3a07cgyXs2AZGZxW7bHs0uaVfaFl9ca/xUWH7ZFgcltLmb5TN2UumV5qGefVloJr AtOQtkYAg+pSOi1benl+xjNQdczKBHgBFPqp5ZS9bZmvaD/4exjRg5/9CVq/SHrK+tGX CCFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=19cL4wojbQuqSJ16gyCwngGtDBfXVS72TXpqKpEjZRU=; b=mFgLCkkEHuJxwO+DJhwjoDlm2uPsXBxLhhV8zk6IM675r40UOGMtiOSEDJjQcEvedy 79RePKxvKobnUdsmW5ceavjuxVBEnwswTuCCEEwut9Aqvc7aIhO9NOHtth3qFX1k7iG5 1712NBqmhQ46hYr6wSB12vb2v9kxuYFRd3bNZeLu78f4M6UGbGeC2x/na3kDfsMBT2Nk jb4Zy865isWHwiphYEp3FNHdTJ3AQR8F0CAXI1LMXAnVKR8qvhFzFSnf5E5xApShkig3 XLenQcxJGcnzp70AvQY5q4pkYnCTOP+ccF9AMdSuIM7SPSX4QMq3picA43HFMb5BVw8C +/9g== X-Gm-Message-State: AOAM531Rj8+umtFk4yRzVNLq7LdMOTV6k+RAYMDrvl0fHiDcw7H/1sWL tV1KSiJRt1p7W6Ao8hNQCrm+tdXi/Dd26dQlo2GdQA== X-Google-Smtp-Source: ABdhPJwuneTGFDLmGP33I92J052VvOfiPyDnJKVRpexRqXqqlsCoMLG8aT27I7XA9gg3rjGUKsN701aFhBMlRpGVaaA= X-Received: by 2002:a17:906:6b88:: with SMTP id l8mr2674759ejr.482.1610445365645; Tue, 12 Jan 2021 01:56:05 -0800 (PST) MIME-Version: 1.0 References: <3337797.iIbC2pHGDl@basile.remlab.net> <20201218103759.19929-7-remi.denis.courmont@huawei.com> <6e1eec7e-35de-4276-68ec-7e12cb73a699@linaro.org> In-Reply-To: <6e1eec7e-35de-4276-68ec-7e12cb73a699@linaro.org> From: Peter Maydell Date: Tue, 12 Jan 2021 09:55:54 +0000 Message-ID: Subject: Re: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table To: Richard Henderson Cc: =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= , qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 09:56:10 -0000 On Tue, 12 Jan 2021 at 00:04, Richard Henderson wrote: > > On 12/18/20 12:37 AM, remi.denis.courmont@huawei.com wrote: > > From: R=C3=A9mi Denis-Courmont > > > > With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in > > secure mode, though it can only be AArch64. > > > > This patch adds the target EL for exceptions from 64-bit S-EL2. > > > > It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure > > mode. Those values were never used in practice as the effective value o= f > > HCR was always 0 in secure mode. > > > > Signed-off-by: R=C3=A9mi Denis-Courmont > > --- > > target/arm/helper.c | 10 +++++----- > > target/arm/op_helper.c | 4 ++-- > > 2 files changed, 7 insertions(+), 7 deletions(-) > > At some point I think it would be worthwhile to convert that target_el_ta= ble > back to code. It is really hard to follow with 6 indicies. Not your fau= lt. I think that there's value in having it be expressed as data rather than code because then it can be compared with the equivalent tables in the Arm ARM. I agree that a 6-index array is getting a bit unreadable, but maybe there's a more readable data format we could find ? -- PMM From MAILER-DAEMON Tue Jan 12 05:08:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzGbg-0007dC-QU for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:08:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzGbe-0007YB-BO for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:08:54 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:41869) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzGbc-0007vA-2e for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:08:54 -0500 Received: by mail-ej1-x631.google.com with SMTP id g12so502892ejf.8 for ; Tue, 12 Jan 2021 02:08:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=5q8bAIKPF4oNGobaAtHavlBxUXPUiqP1WlLtWRoD35M=; b=VgAuUyzCLX1cCD2bgtbLSFfP7xWXD4asi9Sq1tpKH6UKGTKENiWYNvDS67aTTO5d85 Oom2dWWs5Ix3EQ1bg37R/CrkVOHlh4vzpSAJNoNpqjWclb9LRQMiXNnu8eQfUmHKY3E8 NDjahwQKRAX59lwoF76rsL3U3ef28fCUOZo+hIQpeiM/hhG+XxYf7wu+cYeOh4HCszcv 5dwWTHCNU0a0k5BSF3y7+tbYEdtPlGrzGcayJmDgDchBhQE7FMD7WuEv+RiDQIiyK/bG 6iZDN6U3QWeFdAd3IPYLa12z7dGL+gTi72uZgc8Kt8Sq+c5xhFQtlEYbfifKJuZ2mptk hUpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=5q8bAIKPF4oNGobaAtHavlBxUXPUiqP1WlLtWRoD35M=; b=SUqaFHci7npvjbmUcTI0fqUFb627fSZHHmPHiP3COkwJUkoDgzKtYLKuqFbSet9YXN hnnV++JYUWNbpsb4SnwmVr1+84xWMM0ltrRoWvWLFVXlQ/SbZX+l4F9sX30tUBTIHEsK o15U8d390gxqM8RE9pSIH4GZayIz6rQTPa72oVGLclTz733B0Tn6dwNqwUPg+mu0KnCf Y7jVcsZ6q/O2YP1dkDYaj7JDh7C2DwUrJLkQ/br8fM8RPKUWO2lmohxjFE5KhhfzbQrT K98oFfxo8A+nLQ0Q0pDf1KF7HTsZ8Mn9W93rsptA+FBkQU4v3s2AMEC8pSG4Mq+hVblS vPpQ== X-Gm-Message-State: AOAM531ehAmgWM0Mh0P4H9BjEE95KLwQTO4DS6l1PA2LYN/xrOowwhYu GDnfSAzwupQ2yjRsovLVTw5lUw569HZgtiMJCZqunQ== X-Google-Smtp-Source: ABdhPJwWDY1VHgwTduFlD06AiML7kTY5AVltEzX95ILR2K8LRmxJAEq7fSXm9xh+XTdt6xtOq/uSfZMIDtwtTpAbWS0= X-Received: by 2002:a17:906:e94c:: with SMTP id jw12mr2774046ejb.56.1610446130316; Tue, 12 Jan 2021 02:08:50 -0800 (PST) MIME-Version: 1.0 References: <20210108090817.6127-2-remi.denis.courmont@huawei.com> In-Reply-To: <20210108090817.6127-2-remi.denis.courmont@huawei.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:08:39 +0000 Message-ID: Subject: Re: [PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU To: =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= Cc: qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:08:54 -0000 On Fri, 8 Jan 2021 at 09:08, wrote: > > From: R=C3=A9mi Denis-Courmont > > Signed-off-by: R=C3=A9mi Denis-Courmont > --- > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 7cf9fc4bc6..da24f94baa 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) > t =3D cpu->isar.id_aa64mmfr2; > t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); > t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ > + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ > cpu->isar.id_aa64mmfr2 =3D t; I've applied this series to target-arm.next; thanks. It looks like you forgot to send the series as a threaded set of emails with a cover letter email. This confuses our tools which find patches in the mailing list (so your series doesn't show up on patchew or in the 'patches' tool's list of patches), and it also means I'm likely to miss it when I go through my emails manually. I dealt with this one manually, but it's a lot more work for me to do so and it was only really feasible because there were only two patches in the series. For future submissions, please can you make sure you send multi-patch series with a 00/nn cover letter email and with all the patches in the series being followups to that cover letter. git send-email will get all the threading details right for you. (Single standalone patches don't need a cover letter.) https://wiki.qemu.org/Contribute/SubmitAPatch has more info on our patch submission recommendations. thanks -- PMM From MAILER-DAEMON Tue Jan 12 05:12:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzGfO-0004lg-Jz for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:12:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzGfH-0004is-4w for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:12:39 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:42571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzGfE-0000hx-V9 for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:12:38 -0500 Received: by mail-ej1-x633.google.com with SMTP id d17so2663321ejy.9 for ; Tue, 12 Jan 2021 02:12:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3/Y7ppQtuS3fpbvTdFYBXtOH/K4xhXeo13718pbsi7w=; b=T2Lo5AapG/JU9dByJ+7LcCJwR3tSTlaWBFWfDclNmZTqg0IqKwQo3xES1dRlZzd224 Zngzfo76MS5hrKPz0IHSrpU0iJBy8r986grm17/l552Mwr7Q1Y9F4sgOf00fYJ7OsKHt ZUbMuJUqRqXc1V8wm2hFvwvYUlcE52BytT+3uMQu7VJrfE8WmFn3fblL8D9Nh+TNlEev g0W7CpiSD8B/GL6YvN7FX0pJIPO7AoaiDVXG8lLiTNF4XP5y796FGGMWkgS5kWLcxKys DdqmceMd7zce7LLcMz7c9ARhIEJQzlRB20NbtDjKEE3h4rZ0qCXPoF9kSm0ZD5LX68Sr yyPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3/Y7ppQtuS3fpbvTdFYBXtOH/K4xhXeo13718pbsi7w=; b=ca1f1b9KTj1+DrnkSFbcakNklZ4cHWiqoPPJcyt6JK2lLONN5l+MxKXTRj6smVJdfN eD2vcB1mTvOV8tI8ptBSAmM6p2F4wDpkWoZsE2s19tHds0Yd1RVO2QWQ7sUDLIYwc6Gf tjrYtMjrtQVLfgs1wtzN3ah31xuVCKpkAhk3vHihNo5ybcmIAVtmoc4nJC2IsBPKjjEv VQSo5yh2igOI+A3qWBn5cxnzCnSWilhPMvU/XetXV0GwZfuRc7pcn9Xf+0RDHXCNBWE2 67FPLkXlz8qxh23owzBuSbe+GSL9O/5wtpOoaI95Xz1UqXwNdDVC1W3kvSLnefQN3oJA 9aRw== X-Gm-Message-State: AOAM530Eaii7cG6+zsPaTar2WPPtX7p8EqBE3IYSo3kYoIO0YlEbQQsv iFAikJy3DehshMTC90C37wMduPwnJKU4X9vJ6vPtZQ== X-Google-Smtp-Source: ABdhPJxIEqPc+S6f5Mix5z88ll5pR/5CINYN/VWV6LUZgNtzRfsfQQOeTHd2tKp94CBp8D5oRScMADJ95pV0en/tkqQ= X-Received: by 2002:a17:906:31d2:: with SMTP id f18mr2622714ejf.407.1610446355490; Tue, 12 Jan 2021 02:12:35 -0800 (PST) MIME-Version: 1.0 References: <20210108185154.8108-1-leif@nuviainc.com> In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:12:24 +0000 Message-ID: Subject: Re: [PATCH v3 0/6] target/arm: various changes to cpu.h To: Leif Lindholm Cc: QEMU Developers , qemu-arm , Laurent Desnogues Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:12:39 -0000 On Fri, 8 Jan 2021 at 18:51, Leif Lindholm wrote: > > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS). > > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined > by the ARM ARM. > > Third, add field definitions for CLIDR (excepting the Ttype fields, since > I was unsure of prefererred naming - Ttype7-Ttype1?). > > Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c, > > Lastly, add all ID_ (aarch32) registers/fields. > > Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be > submitting shortly, and some of those features also exist for aarch32. Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Tue Jan 12 05:30:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzGwu-0001hz-IZ for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:30:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzGwo-0001fm-Ix for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:30:46 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:52103) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzGwg-0006nu-2C for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:30:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610447435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=YtAVZx/m5M42/sCrHG4e0vHzuv3Z13YDXpEzXvGlnvs=; b=YjnSOg3jzcgDk3pKzvV3zMlScciAKIgxzGWXA2EP6qz4UU0YbVv5LU4HLJ7aw5O56FWSZe eMPcfifqqVuOhPA+trqr0eoRtmgLszjJne1+iW1X1aUSbMgtigEBez19flQSwZZaJZ54VP haWtEIq+4n2EjSlXNA4sQZDDcGA8bpc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-361-yZM83J6cMXCpTgcubcTk1A-1; Tue, 12 Jan 2021 05:30:33 -0500 X-MC-Unique: yZM83J6cMXCpTgcubcTk1A-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 07D87AFA81; Tue, 12 Jan 2021 10:30:29 +0000 (UTC) Received: from localhost (ovpn-115-99.ams2.redhat.com [10.36.115.99]) by smtp.corp.redhat.com (Postfix) with ESMTP id 978DF10023B5; Tue, 12 Jan 2021 10:30:15 +0000 (UTC) Date: Tue, 12 Jan 2021 10:30:14 +0000 From: Stefan Hajnoczi To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Huacai Chen , Greg Kurz , "Michael S. Tsirkin" , qemu-trivial@nongnu.org, Amit Shah , Dmitry Fleytman , qemu-arm@nongnu.org, John Snow , qemu-s390x@nongnu.org, Paul Durrant , Anthony Perard , Eduardo Habkost , Gerd Hoffmann , Kevin Wolf , Marcelo Tosatti , Max Reitz , Alex Williamson , Aurelien Jarno , Aleksandar Rikalo , Marcel Apfelbaum , Jason Wang , Peter Maydell , =?iso-8859-1?Q?C=E9dric?= Le Goater , Halil Pasic , Fam Zheng , qemu-ppc@nongnu.org, Paolo Bonzini , kvm@vger.kernel.org, Stefano Stabellini , xen-devel@lists.xenproject.org, Cornelia Huck , David Hildenbrand , qemu-block@nongnu.org, Christian Borntraeger , Sunil Muthuswamy , David Gibson , Richard Henderson , Alex =?iso-8859-1?Q?Benn=E9e?= , Laurent Vivier , Thomas Huth , Jiaxun Yang Subject: Re: [PATCH 0/2] sysemu: Let VMChangeStateHandler take boolean 'running' argument Message-ID: <20210112103014.GB194658@stefanha-x1.localdomain> References: <20210111152020.1422021-1-philmd@redhat.com> MIME-Version: 1.0 In-Reply-To: <20210111152020.1422021-1-philmd@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=stefanha@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="b5gNqxB1S1yM7hjW" Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=stefanha@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:30:46 -0000 --b5gNqxB1S1yM7hjW Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jan 11, 2021 at 04:20:18PM +0100, Philippe Mathieu-Daud=E9 wrote: > Trivial prototype change to clarify the use of the 'running' > argument of VMChangeStateHandler. >=20 > Green CI: > https://gitlab.com/philmd/qemu/-/pipelines/239497352 >=20 > Philippe Mathieu-Daud=E9 (2): > sysemu/runstate: Let runstate_is_running() return bool > sysemu: Let VMChangeStateHandler take boolean 'running' argument >=20 > include/sysemu/runstate.h | 12 +++++++++--- > target/arm/kvm_arm.h | 2 +- > target/ppc/cpu-qom.h | 2 +- > accel/xen/xen-all.c | 2 +- > audio/audio.c | 2 +- > block/block-backend.c | 2 +- > gdbstub.c | 2 +- > hw/block/pflash_cfi01.c | 2 +- > hw/block/virtio-blk.c | 2 +- > hw/display/qxl.c | 2 +- > hw/i386/kvm/clock.c | 2 +- > hw/i386/kvm/i8254.c | 2 +- > hw/i386/kvmvapic.c | 2 +- > hw/i386/xen/xen-hvm.c | 2 +- > hw/ide/core.c | 2 +- > hw/intc/arm_gicv3_its_kvm.c | 2 +- > hw/intc/arm_gicv3_kvm.c | 2 +- > hw/intc/spapr_xive_kvm.c | 2 +- > hw/misc/mac_via.c | 2 +- > hw/net/e1000e_core.c | 2 +- > hw/nvram/spapr_nvram.c | 2 +- > hw/ppc/ppc.c | 2 +- > hw/ppc/ppc_booke.c | 2 +- > hw/s390x/tod-kvm.c | 2 +- > hw/scsi/scsi-bus.c | 2 +- > hw/usb/hcd-ehci.c | 2 +- > hw/usb/host-libusb.c | 2 +- > hw/usb/redirect.c | 2 +- > hw/vfio/migration.c | 2 +- > hw/virtio/virtio-rng.c | 2 +- > hw/virtio/virtio.c | 2 +- > net/net.c | 2 +- > softmmu/memory.c | 2 +- > softmmu/runstate.c | 4 ++-- > target/arm/kvm.c | 2 +- > target/i386/kvm/kvm.c | 2 +- > target/i386/sev.c | 2 +- > target/i386/whpx/whpx-all.c | 2 +- > target/mips/kvm.c | 4 ++-- > ui/gtk.c | 2 +- > ui/spice-core.c | 2 +- > 41 files changed, 51 insertions(+), 45 deletions(-) >=20 > --=20 > 2.26.2 >=20 >=20 Reviewed-by: Stefan Hajnoczi --b5gNqxB1S1yM7hjW Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAl/9ejYACgkQnKSrs4Gr c8idIAf/Yau6DdIvJYo0z1xlPWikqBBVOuHPdp3bLO0cxM4ShsmyJBcHVcXht/F5 2dJf4d3ieWtl1MiBHI7VlWPtxfZXjcKLN8TT6wS7IUQOKMUTj7U+kZeplVOeHdJ5 FaBCr4SCux3oJdDYz0V0oYxyZotxXpgV6QcnecOQ8z+3syVSKdPf5ZIDIEEJm9g8 1ZI/HkBoJ6k2glUM83ohVS2K8gQ/eJqANxgKCFqGX2AFcIuQfD2ESotgaq263A0m WvGwEXcLV6ALMAANVoYBDIPACb3dJFGK4Z9HZnUoV5Cqq14MmTjsIaDCRI7ekmtl iifLGCKlWmb5Y8rX5WFdfJfWQf/ufg== =R44D -----END PGP SIGNATURE----- --b5gNqxB1S1yM7hjW-- From MAILER-DAEMON Tue Jan 12 05:44:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHAP-000302-M3 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:44:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHAN-0002tO-73; Tue, 12 Jan 2021 05:44:47 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56696 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAL-0003Az-1Q; Tue, 12 Jan 2021 05:44:46 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id C06225FCEF; Tue, 12 Jan 2021 11:44:41 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCHv5 00/19] ARMv8.4-A Secure EL2 Date: Tue, 12 Jan 2021 12:44:39 +0200 Message-ID: <12681824.uLZWGnKmhe@basile.remlab.net> Organization: Huawei Technologies, Finland MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:44:47 -0000 Hi, This adds Secure EL2. Changes since version 4: =2D Fix NS unitialised in secure state stage 2 translation. =2D Remove EEL2 translation block flag in 32-bit mode. =2D Clarify comments on arm_is_el2_enabled(). =2D--------------------------------------------------------------- R=C3=A9mi Denis-Courmont (19): target/arm: remove redundant tests target/arm: add arm_is_el2_enabled() helper target/arm: use arm_is_el2_enabled() where applicable target/arm: use arm_hcr_el2_eff() where applicable target/arm: factor MDCR_EL2 common handling target/arm: declare new AA64PFR0 bit-fields target/arm: add 64-bit S-EL2 to EL exception table target/arm: add MMU stage 1 for Secure EL2 target/arm: add ARMv8.4-SEL2 system registers target/arm: handle VMID change in secure state target/arm: do S1_ptw_translate() before address space lookup target/arm: translate NS bit in page-walks target/arm: generalize 2-stage page-walk condition target/arm: secure stage 2 translation regime target/arm: set HPFAR_EL2.NS on secure stage 2 faults target/arm: revector to run-time pick target EL target/arm: add ARMv8.4-SEL2 extension target/arm: enable Secure EL2 in max CPU target/arm: refactor vae1_tlbmask() target/arm/cpu-param.h | 2 +- target/arm/cpu.c | 10 +- target/arm/cpu.h | 90 ++++++++-- target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 8 +- target/arm/helper.c | 414 ++++++++++++++++++++++++++++++-----------= =2D--- target/arm/internals.h | 36 ++++ target/arm/op_helper.c | 4 +- target/arm/tlb_helper.c | 3 + target/arm/translate-a64.c | 4 + target/arm/translate.c | 35 +++- 11 files changed, 430 insertions(+), 177 deletions(-) =2D-=20 =E9=9B=B7=E7=B1=B3=E2=80=A7=E5=BE=B7=E5=B0=BC-=E5=BA=93=E5=B0=94=E8=92=99 http://www.remlab.net/ From MAILER-DAEMON Tue Jan 12 05:45:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHB2-0003cy-Tp for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHAy-0003bF-Gb; Tue, 12 Jan 2021 05:45:27 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56706 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAr-0003LV-8m; Tue, 12 Jan 2021 05:45:22 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id D97565FE7F; Tue, 12 Jan 2021 11:45:11 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 02/19] target/arm: add arm_is_el2_enabled() helper Date: Tue, 12 Jan 2021 12:44:54 +0200 Message-Id: <20210112104511.36576-2-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:28 -0000 From: Rémi Denis-Courmont This checks if EL2 is enabled (meaning EL2 registers take effects) in the current security context. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad37ff61c6..0881e0157d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2072,6 +2072,18 @@ static inline bool arm_is_secure(CPUARMState *env) return arm_is_secure_below_el3(env); } +/* + * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. + * This corresponds to the pseudocode EL2Enabled() + */ +static inline bool arm_is_el2_enabled(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL2)) { + return !arm_is_secure_below_el3(env); + } + return false; +} + #else static inline bool arm_is_secure_below_el3(CPUARMState *env) { @@ -2082,6 +2094,11 @@ static inline bool arm_is_secure(CPUARMState *env) { return false; } + +static inline bool arm_is_el2_enabled(CPUARMState *env) +{ + return false; +} #endif /** -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBF-0003ij-N2 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHAy-0003bD-FA; Tue, 12 Jan 2021 05:45:27 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56704 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAq-0003LS-IM; Tue, 12 Jan 2021 05:45:21 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 87D665FCEF; Tue, 12 Jan 2021 11:45:11 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 01/19] target/arm: remove redundant tests Date: Tue, 12 Jan 2021 12:44:53 +0200 Message-Id: <20210112104511.36576-1-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:28 -0000 From: Rémi Denis-Courmont In this context, the HCR value is the effective value, and thus is zero in secure mode. The tests for HCR.{F,I}MO are sufficient. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 10 ++++------ 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..5530874686 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -451,14 +451,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, break; case EXCP_VFIQ: - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_I); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ab3f5ace3..dabe1b32bb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2083,13 +2083,11 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = env_cpu(env); - uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool el1 = arm_current_el(env) == 1; + uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; uint64_t ret = 0; - bool allow_virt = (arm_current_el(env) == 1 && - (!arm_is_secure_below_el3(env) || - (env->cp15.scr_el3 & SCR_EEL2))); - if (allow_virt && (hcr_el2 & HCR_IMO)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } @@ -2099,7 +2097,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - if (allow_virt && (hcr_el2 & HCR_FMO)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBG-0003it-4C for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHAy-0003bE-G7; Tue, 12 Jan 2021 05:45:27 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56712 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAr-0003Lh-A5; Tue, 12 Jan 2021 05:45:23 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id B639760228; Tue, 12 Jan 2021 11:45:12 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 05/19] target/arm: factor MDCR_EL2 common handling Date: Tue, 12 Jan 2021 12:44:57 +0200 Message-Id: <20210112104511.36576-5-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:28 -0000 From: Rémi Denis-Courmont This adds a common helper to compute the effective value of MDCR_EL2. That is the actual value if EL2 is enabled in the current security context, or 0 elsewise. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2676d227bb..7860ccd7ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -538,6 +538,11 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, return CP_ACCESS_TRAP_UNCATEGORIZED; } +static uint64_t arm_mdcr_el2_eff(CPUARMState *env) +{ + return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; +} + /* Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA */ @@ -545,11 +550,11 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { int el = arm_current_el(env); - bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); + bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || (arm_hcr_el2_eff(env) & HCR_TGE); - if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdosa) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { @@ -565,11 +570,11 @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { int el = arm_current_el(env); - bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); + bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || (arm_hcr_el2_eff(env) & HCR_TGE); - if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdra) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -585,11 +590,11 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { int el = arm_current_el(env); - bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); + bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || (arm_hcr_el2_eff(env) & HCR_TGE); - if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tda) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -605,9 +610,9 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { int el = arm_current_el(env); + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { @@ -1347,12 +1352,12 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, * trapping to EL2 or EL3 for other accesses. */ int el = arm_current_el(env); + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { return CP_ACCESS_TRAP; } - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { @@ -1431,7 +1436,8 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) bool enabled, prohibited, filtered; bool secure = arm_is_secure(env); int el = arm_current_el(env); - uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); + uint8_t hpmn = mdcr_el2 & MDCR_HPMN; if (!arm_feature(env, ARM_FEATURE_PMU)) { return false; @@ -1441,13 +1447,13 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) (counter < hpmn || counter == 31)) { e = env->cp15.c9_pmcr & PMCRE; } else { - e = env->cp15.mdcr_el2 & MDCR_HPME; + e = mdcr_el2 & MDCR_HPME; } enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); if (!secure) { if (el == 2 && (counter < hpmn || counter == 31)) { - prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; + prohibited = mdcr_el2 & MDCR_HPMD; } else { prohibited = false; } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBI-0003jl-01 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003bi-Bf; Tue, 12 Jan 2021 05:45:28 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56708 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAr-0003LY-9R; Tue, 12 Jan 2021 05:45:24 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 2DE71600A6; Tue, 12 Jan 2021 11:45:12 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 03/19] target/arm: use arm_is_el2_enabled() where applicable Date: Tue, 12 Jan 2021 12:44:55 +0200 Message-Id: <20210112104511.36576-3-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:28 -0000 From: Rémi Denis-Courmont Do not assume that EL2 is available in and only in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/helper-a64.c | 8 +------- target/arm/helper.c | 33 +++++++++++++-------------------- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0881e0157d..7afa26e08a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2134,7 +2134,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } - if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { + if (arm_is_el2_enabled(env)) { aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); } @@ -3078,7 +3078,7 @@ static inline int arm_debug_target_el(CPUARMState *env) bool secure = arm_is_secure(env); bool route_to_el2 = false; - if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { + if (arm_is_el2_enabled(env)) { route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || env->cp15.mdcr_el2 & MDCR_TDE; } diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 30b2ad119f..c426c23d2c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -972,8 +972,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) if (new_el == -1) { goto illegal_return; } - if (new_el > cur_el - || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + if (new_el > cur_el || (new_el == 2 && !arm_is_el2_enabled(env))) { /* Disallow return to an EL which is unimplemented or higher * than the current one. */ @@ -985,11 +984,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) goto illegal_return; } - if (new_el == 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } diff --git a/target/arm/helper.c b/target/arm/helper.c index dabe1b32bb..26dcafbee1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1048,8 +1048,8 @@ static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, { if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ - if (arm_current_el(env) == 1 && - (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { + if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && + (env->cp15.cptr_el[2] & CPTR_TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && @@ -2519,7 +2519,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, bool isread) { unsigned int cur_el = arm_current_el(env); - bool secure = arm_is_secure(env); + bool has_el2 = arm_is_el2_enabled(env); uint64_t hcr = arm_hcr_el2_eff(env); switch (cur_el) { @@ -2543,8 +2543,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, } } else { /* If HCR_EL2. == 0: check CNTHCTL_EL2.EL1PCEN. */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx == GTIMER_PHYS && !secure && + if (has_el2 && timeridx == GTIMER_PHYS && !extract32(env->cp15.cnthctl_el2, 1, 1)) { return CP_ACCESS_TRAP_EL2; } @@ -2553,8 +2552,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, case 1: /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx == GTIMER_PHYS && !secure && + if (has_el2 && timeridx == GTIMER_PHYS && (hcr & HCR_E2H ? !extract32(env->cp15.cnthctl_el2, 10, 1) : !extract32(env->cp15.cnthctl_el2, 0, 1))) { @@ -2569,7 +2567,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, bool isread) { unsigned int cur_el = arm_current_el(env); - bool secure = arm_is_secure(env); + bool has_el2 = arm_is_el2_enabled(env); uint64_t hcr = arm_hcr_el2_eff(env); switch (cur_el) { @@ -2590,8 +2588,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, /* fall through */ case 1: - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx == GTIMER_PHYS && !secure) { + if (has_el2 && timeridx == GTIMER_PHYS) { if (hcr & HCR_E2H) { /* If HCR_EL2. == '10': check CNTHCTL_EL2.EL1PTEN. */ if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { @@ -4247,11 +4244,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = env_archcpu(env); unsigned int cur_el = arm_current_el(env); - bool secure = arm_is_secure(env); - if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { + if (arm_is_el2_enabled(env) && cur_el == 1) { return env->cp15.vpidr_el2; } return raw_read(env, ri); @@ -4278,9 +4273,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { unsigned int cur_el = arm_current_el(env); - bool secure = arm_is_secure(env); - if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { + if (arm_is_el2_enabled(env) && cur_el == 1) { return env->cp15.vmpidr_el2; } return mpidr_read_val(env); @@ -5347,7 +5341,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) { uint64_t ret = env->cp15.hcr_el2; - if (arm_is_secure_below_el3(env)) { + if (!arm_is_el2_enabled(env)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -6144,7 +6138,7 @@ int sve_exception_el(CPUARMState *env, int el) /* CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ - if (el <= 2 && !arm_is_secure_below_el3(env)) { + if (el <= 2 && arm_is_el2_enabled(env)) { if (env->cp15.cptr_el[2] & CPTR_TZ) { return 2; } @@ -8719,8 +8713,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) } return 0; case ARM_CPU_MODE_HYP: - return !arm_feature(env, ARM_FEATURE_EL2) - || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); + return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; case ARM_CPU_MODE_MON: return arm_current_el(env) < 3; default: @@ -12646,7 +12639,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) /* CPTR_EL2 : present in v7VE or v8 */ if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && !arm_is_secure_below_el3(env)) { + && arm_is_el2_enabled(env)) { /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ return 2; } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBJ-0003kd-0a for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB6-0003db-Au; Tue, 12 Jan 2021 05:45:32 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56722 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003Sw-Hc; Tue, 12 Jan 2021 05:45:31 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 1BDC46040D; Tue, 12 Jan 2021 11:45:14 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 10/19] target/arm: handle VMID change in secure state Date: Tue, 12 Jan 2021 12:45:02 +0200 Message-Id: <20210112104511.36576-10-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:32 -0000 From: Rémi Denis-Courmont The VTTBR write callback so far assumes that the underlying VM lies in non-secure state. This handles the secure state scenario. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7f84662dfa..3e6b1c548b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4017,10 +4017,15 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * the combined stage 1&2 tlbs (EL10_1 and EL10_0). */ if (raw_read(env, ri) != value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + uint16_t mask = ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBJ-0003lK-Ar for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB6-0003de-Cc; Tue, 12 Jan 2021 05:45:32 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56714 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003Ss-JN; Tue, 12 Jan 2021 05:45:30 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 0124960283; Tue, 12 Jan 2021 11:45:12 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 06/19] target/arm: declare new AA64PFR0 bit-fields Date: Tue, 12 Jan 2021 12:44:58 +0200 Message-Id: <20210112104511.36576-6-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:32 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7afa26e08a..fecdd642c9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1881,6 +1881,12 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, SEL2, 36, 4) +FIELD(ID_AA64PFR0, MPAM, 40, 4) +FIELD(ID_AA64PFR0, AMU, 44, 4) +FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) @@ -3928,6 +3934,11 @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; } +static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBM-0003pF-3g for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003bh-AS; Tue, 12 Jan 2021 05:45:28 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56710 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHAr-0003Lc-AR; Tue, 12 Jan 2021 05:45:24 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 7711B601B4; Tue, 12 Jan 2021 11:45:12 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 04/19] target/arm: use arm_hcr_el2_eff() where applicable Date: Tue, 12 Jan 2021 12:44:56 +0200 Message-Id: <20210112104511.36576-4-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:28 -0000 From: Rémi Denis-Courmont This will simplify accessing HCR conditionally in secure state. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 26dcafbee1..2676d227bb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4432,16 +4432,16 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, static int vae1_tlbmask(CPUARMState *env) { - /* Since we exclude secure first, we may read HCR_EL2 directly. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) - == (HCR_E2H | HCR_TGE)) { + uint64_t hcr = arm_hcr_el2_eff(env); + + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; + } else if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | @@ -9964,6 +9964,8 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { + uint64_t hcr_el2; + if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { @@ -9982,19 +9984,21 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } + hcr_el2 = arm_hcr_el2_eff(env); + if (mmu_idx == ARMMMUIdx_Stage2) { /* HCR.DC means HCR.VM behaves as 1 */ - return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; + return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; } - if (env->cp15.hcr_el2 & HCR_TGE) { + if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { return true; } } - if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -10345,7 +10349,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ptw = true; return ~0; } - if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) { + if ((arm_hcr_el2_eff(env) & HCR_PTW) && + (cacheattrs.attrs & 0xf0) == 0) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -10778,7 +10783,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) uint8_t hihint = 0, lohint = 0; if (hiattr != 0) { /* normal memory */ - if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ + if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ hiattr = loattr = 1; /* non-cacheable */ } else { if (hiattr != 1) { /* Write-through or write-back */ @@ -12111,7 +12116,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } /* Combine the S1 and S2 cache attributes. */ - if (env->cp15.hcr_el2 & HCR_DC) { + if (arm_hcr_el2_eff(env) & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBN-0003sf-Sh for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB6-0003e6-Ft; Tue, 12 Jan 2021 05:45:34 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56724 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003T1-NS; Tue, 12 Jan 2021 05:45:32 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 58F9360413; Tue, 12 Jan 2021 11:45:14 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 11/19] target/arm: do S1_ptw_translate() before address space lookup Date: Tue, 12 Jan 2021 12:45:03 +0200 Message-Id: <20210112104511.36576-11-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:34 -0000 From: Rémi Denis-Courmont In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW bits can invert the secure flag for pagetable walks. This patchset allows S1_ptw_translate() to change the non-secure bit. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3e6b1c548b..7d96897f9a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10392,7 +10392,7 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, MemTxAttrs txattrs, + hwaddr addr, bool *is_secure, ARMMMUFaultInfo *fi) { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && @@ -10402,6 +10402,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, int s2prot; int ret; ARMCacheAttrs cacheattrs = {}; + MemTxAttrs txattrs = {}; + + assert(!*is_secure); /* TODO: S-EL2 */ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2, false, @@ -10442,9 +10445,9 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, AddressSpace *as; uint32_t data; + addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); attrs.secure = is_secure; as = arm_addressspace(cs, attrs); - addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } @@ -10471,9 +10474,9 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, AddressSpace *as; uint64_t data; + addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); attrs.secure = is_secure; as = arm_addressspace(cs, attrs); - addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBR-0003ti-MC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB6-0003dc-CL; Tue, 12 Jan 2021 05:45:32 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56718 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003Sv-NT; Tue, 12 Jan 2021 05:45:31 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 82CAD603C3; Tue, 12 Jan 2021 11:45:13 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 08/19] target/arm: add MMU stage 1 for Secure EL2 Date: Tue, 12 Jan 2021 12:45:00 +0200 Message-Id: <20210112104511.36576-8-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:32 -0000 From: Rémi Denis-Courmont This adds the MMU indices for EL2 stage 1 in secure state. To keep code contained, which is largelly identical between secure and non-secure modes, the MMU indices are reassigned. The new assignments provide a systematic pattern with a non-secure bit. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 37 +++++++---- target/arm/helper.c | 127 ++++++++++++++++++++++++------------- target/arm/internals.h | 12 ++++ target/arm/translate-a64.c | 4 ++ 5 files changed, 124 insertions(+), 58 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6321385b46..00e7d9e937 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif -#define NB_MMU_MODES 11 +#define NB_MMU_MODES 15 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fecdd642c9..085dc9cc54 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2979,6 +2979,9 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ +/* Meanings of the bits for A profile mmu idx values */ +#define ARM_MMU_IDX_A_NS 0x8 + /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2992,20 +2995,22 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, - - ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, - - ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, + + ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, /* * These are not allocated TLBs and are used only for AT system @@ -3052,8 +3057,12 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE20_0), TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE20_2), TO_CORE_BIT(SE10_1_PAN), + TO_CORE_BIT(SE20_2_PAN), + TO_CORE_BIT(SE2), TO_CORE_BIT(SE3), TO_CORE_BIT(MUser), diff --git a/target/arm/helper.c b/target/arm/helper.c index bc228e070f..fde95cb97e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2861,6 +2861,9 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2873,6 +2876,9 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3576,7 +3582,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_SE3; break; case 2: - g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { @@ -3672,7 +3678,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx = ARMMMUIdx_E2; + mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_SE3; @@ -3987,10 +3993,15 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, */ if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { - tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0); + uint16_t mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); } @@ -4441,9 +4452,15 @@ static int vae1_tlbmask(CPUARMState *env) uint64_t hcr = arm_hcr_el2_eff(env); if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; + uint16_t mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + return mask; } else if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_1_PAN | @@ -4468,17 +4485,20 @@ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, static int vae1_tlbbits(CPUARMState *env, uint64_t addr) { + uint64_t hcr = arm_hcr_el2_eff(env); ARMMMUIdx mmu_idx; /* Only the regime of the mmu_idx below is significant. */ - if (arm_is_secure_below_el3(env)) { - mmu_idx = ARMMMUIdx_SE10_0; - } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) - == (HCR_E2H | HCR_TGE)) { + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { mmu_idx = ARMMMUIdx_E20_0; } else { mmu_idx = ARMMMUIdx_E10_0; } + + if (arm_is_secure_below_el3(env)) { + mmu_idx &= ~ARM_MMU_IDX_A_NS; + } + return tlbbits_for_regime(env, mmu_idx, addr); } @@ -4524,11 +4544,17 @@ static int alle1_tlbmask(CPUARMState *env) static int e2_tlbmask(CPUARMState *env) { - /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE20_0 | + ARMMMUIdxBit_SE20_2 | + ARMMMUIdxBit_SE20_2_PAN | + ARMMMUIdxBit_SE2; + } else { + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; + } } static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4648,10 +4674,12 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, { CPUState *cs = env_cpu(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); - int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); + bool secure = arm_is_secure_below_el3(env); + int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, + pageaddr); - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -9953,7 +9981,8 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el == 0) { ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); - el = (mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1); + el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) + ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -10082,6 +10111,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -12675,6 +12705,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -12684,6 +12715,9 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -12701,6 +12735,9 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { + ARMMMUIdx idx; + uint64_t hcr; + if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } @@ -12708,40 +12745,43 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) /* See ARM pseudo-function ELIsInHost. */ switch (el) { case 0: - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdx_SE10_0; - } - if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE) - && arm_el_is_aa64(env, 2)) { - return ARMMMUIdx_E20_0; + hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { + idx = ARMMMUIdx_E20_0; + } else { + idx = ARMMMUIdx_E10_0; } - return ARMMMUIdx_E10_0; + break; case 1: - if (arm_is_secure_below_el3(env)) { - if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_SE10_1_PAN; - } - return ARMMMUIdx_SE10_1; - } if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_E10_1_PAN; + idx = ARMMMUIdx_E10_1_PAN; + } else { + idx = ARMMMUIdx_E10_1; } - return ARMMMUIdx_E10_1; + break; case 2: - /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ - if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (arm_hcr_el2_eff(env) & HCR_E2H) { if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_E20_2_PAN; + idx = ARMMMUIdx_E20_2_PAN; + } else { + idx = ARMMMUIdx_E20_2; } - return ARMMMUIdx_E20_2; + } else { + idx = ARMMMUIdx_E2; } - return ARMMMUIdx_E2; + break; case 3: return ARMMMUIdx_SE3; default: g_assert_not_reached(); } + + if (arm_is_secure_below_el3(env)) { + idx &= ~ARM_MMU_IDX_A_NS; + } + + return idx; } ARMMMUIdx arm_mmu_idx(CPUARMState *env) @@ -12906,7 +12946,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is * gated by HCR_EL2. == '11', and so is LDTR. diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..e4e6afef19 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -860,6 +860,9 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -890,6 +893,10 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_SE2: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -907,6 +914,7 @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -917,10 +925,14 @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: + case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ef63edfc68..ffc060e5d7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -118,6 +118,10 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_SE10_1_PAN: useridx = ARMMMUIdx_SE10_0; break; + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + useridx = ARMMMUIdx_SE20_0; + break; default: g_assert_not_reached(); } -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:45:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBS-0003uv-Bw for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:45:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHB6-0003df-Dk; Tue, 12 Jan 2021 05:45:32 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56720 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHB2-0003Su-IV; Tue, 12 Jan 2021 05:45:31 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id D1DA1603F4; Tue, 12 Jan 2021 11:45:13 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 09/19] target/arm: add ARMv8.4-SEL2 system registers Date: Tue, 12 Jan 2021 12:45:01 +0200 Message-Id: <20210112104511.36576-9-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:34 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 085dc9cc54..b6685f3746 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -168,6 +168,11 @@ typedef struct { uint32_t base_mask; } TCR; +#define VTCR_NSW (1u << 29) +#define VTCR_NSA (1u << 30) +#define VSTCR_SW VTCR_NSW +#define VSTCR_SA VTCR_NSA + /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -323,9 +328,11 @@ typedef struct CPUARMState { uint64_t ttbr1_el[4]; }; uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ + uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; TCR vtcr_el2; /* Virtualization Translation Control. */ + TCR vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register diff --git a/target/arm/helper.c b/target/arm/helper.c index fde95cb97e..7f84662dfa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5721,6 +5721,27 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = { REGINFO_SENTINEL }; +static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static const ARMCPRegInfo el2_sec_cp_reginfo[] = { + { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, + .access = PL2_RW, .accessfn = sel2_access, + .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, + { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, + .access = PL2_RW, .accessfn = sel2_access, + .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, + REGINFO_SENTINEL +}; + static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -7733,6 +7754,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, el2_v8_cp_reginfo); } + if (cpu_isar_feature(aa64_sel2, cpu)) { + define_arm_cp_regs(cpu, el2_sec_cp_reginfo); + } /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3)) { ARMCPRegInfo rvbar = { -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBh-00041g-Hl for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBT-0003vB-Nd; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56716 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBM-0003St-V5; Tue, 12 Jan 2021 05:45:54 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 445D0602C8; Tue, 12 Jan 2021 11:45:13 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 07/19] target/arm: add 64-bit S-EL2 to EL exception table Date: Tue, 12 Jan 2021 12:44:59 +0200 Message-Id: <20210112104511.36576-7-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:57 -0000 From: Rémi Denis-Courmont With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in secure mode, though it can only be AArch64. This patch adds the target EL for exceptions from 64-bit S-EL2. It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure mode. Those values were never used in practice as the effective value of HCR was always 0 in secure mode. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 10 +++++----- target/arm/op_helper.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7860ccd7ae..bc228e070f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9001,13 +9001,13 @@ static const int8_t target_el_table[2][2][2][2][2][4] = { {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, - {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, - {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, - {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, + {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, + {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, + {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, - {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, - {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, + {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, + {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, }; /* diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ff91fe6121..5e0f123043 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -652,10 +652,10 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = exception_target_el(env); break; case CP_ACCESS_TRAP_EL2: - /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is + /* Requesting a trap to EL2 when we're in EL3 is * a bug in the access function. */ - assert(!arm_is_secure(env) && arm_current_el(env) != 3); + assert(arm_current_el(env) != 3); target_el = 2; break; case CP_ACCESS_TRAP_EL3: -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBk-00045g-FW for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003vp-MD; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56718 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBR-0003Sv-0g; Tue, 12 Jan 2021 05:45:56 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 67CCB60808; Tue, 12 Jan 2021 11:45:16 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 19/19] target/arm: refactor vae1_tlbmask() Date: Tue, 12 Jan 2021 12:45:11 +0200 Message-Id: <20210112104511.36576-19-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 32fc72d9ed..c07850c7ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4469,26 +4469,23 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, static int vae1_tlbmask(CPUARMState *env) { uint64_t hcr = arm_hcr_el2_eff(env); + uint16_t mask; if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - uint16_t mask = ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>= ARM_MMU_IDX_A_NS; - } - - return mask; - } else if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; + mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | + mask = ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + return mask; } /* Return 56 if TBI is enabled, 64 otherwise. */ -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBk-00046O-Mp for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003vv-ME; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56722 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBQ-0003Sw-UU; Tue, 12 Jan 2021 05:45:57 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id DFF9B60605; Tue, 12 Jan 2021 11:45:15 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension Date: Tue, 12 Jan 2021 12:45:09 +0200 Message-Id: <20210112104511.36576-17-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont This adds handling for the SCR_EL3.EEL2 bit. Signed-off-by: Rémi Denis-Courmont --- target/arm/cpu.c | 2 +- target/arm/cpu.h | 8 ++++++-- target/arm/helper.c | 19 ++++++++++++++++--- target/arm/translate.c | 14 ++++++++++++-- 4 files changed, 35 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5530874686..b85b644941 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -480,7 +480,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * masked from Secure state. The HCR and SCR settings * don't affect the masking logic, only the interrupt routing. */ - if (target_el == 3 || !secure) { + if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { unmasked = true; } } else { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e605791e47..df510114f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2094,7 +2094,10 @@ static inline bool arm_is_secure(CPUARMState *env) static inline bool arm_is_el2_enabled(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL2)) { - return !arm_is_secure_below_el3(env); + if (arm_is_secure_below_el3(env)) { + return (env->cp15.scr_el3 & SCR_EEL2) != 0; + } + return true; } return false; } @@ -2141,7 +2144,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } - if (arm_feature(env, ARM_FEATURE_EL3)) { + if (arm_feature(env, ARM_FEATURE_EL3) && + ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7648f6fb97..32fc72d9ed 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -532,6 +532,9 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, return CP_ACCESS_OK; } if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } return CP_ACCESS_TRAP_EL3; } /* This will be EL1 NS and EL2 NS, which just UNDEF */ @@ -2029,6 +2032,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_sel2, cpu)) { + valid_mask |= SCR_EEL2; + } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |= SCR_ATA; } @@ -3387,13 +3393,16 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 if executed in + /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in * Secure EL1 (which can only happen if EL3 is AArch64). * They are simply UNDEF if executed from NS EL1. * They function normally from EL2 or EL3. */ if (arm_current_el(env) == 1) { if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; + } return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; } return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -3656,7 +3665,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { + if (arm_current_el(env) == 3 && + !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -5755,12 +5765,15 @@ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. - * At Secure EL1 it traps to EL3. + * At Secure EL1 it traps to EL3 or EL2. */ if (arm_current_el(env) == 3) { return CP_ACCESS_OK; } if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } return CP_ACCESS_TRAP_EL3; } /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 8b6b7355c9..688cd41684 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, } if (s->current_el == 1) { /* If we're in Secure EL1 (which implies that EL3 is AArch64) - * then accesses to Mon registers trap to EL3 + * then accesses to Mon registers trap to Secure EL2, if it exists, + * otherwise EL3. */ - TCGv_i32 tcg_el = tcg_const_i32(3); + TCGv_i32 tcg_el; + + if (dc_isar_feature(aa64_sel2, s)) { + /* Target EL is EL<3 minus SCR_EL3.EEL2> */ + tcg_el = load_cpu_field(cp15.scr_el3); + tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); + tcg_gen_addi_i32(tcg_el, tcg_el, 3); + } else { + tcg_el = tcg_const_i32(3); + } gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBk-00047Q-TU for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003vs-Mz; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56732 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBO-0003UK-7G; Tue, 12 Jan 2021 05:45:56 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 6294960573; Tue, 12 Jan 2021 11:45:15 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 15/19] target/arm: set HPFAR_EL2.NS on secure stage 2 faults Date: Tue, 12 Jan 2021 12:45:07 +0200 Message-Id: <20210112104511.36576-15-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 6 ++++++ target/arm/internals.h | 2 ++ target/arm/tlb_helper.c | 3 +++ 4 files changed, 13 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f90c772d7..e605791e47 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1482,6 +1482,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) +#define HPFAR_NS (1ULL << 63) + #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index f451f281f6..7648f6fb97 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3444,6 +3444,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, target_el = 3; } else { env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi.s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } target_el = 2; } take_exc = true; @@ -10426,6 +10429,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; + fi->s1ns = !*is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -10438,6 +10442,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; + fi->s1ns = !*is_secure; return ~0; } @@ -11355,6 +11360,7 @@ do_fault: /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S); + fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; return true; } diff --git a/target/arm/internals.h b/target/arm/internals.h index 3aec10263e..27cc93f15a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -593,6 +593,7 @@ typedef enum ARMFaultType { * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk + * @s1ns: True if we faulted on a non-secure IPA while in secure state * @ea: True if we should set the EA (external abort type) bit in syndrome */ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; @@ -603,6 +604,7 @@ struct ARMMMUFaultInfo { int domain; bool stage2; bool s1ptw; + bool s1ns; bool ea; }; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b35dc8a011..df85079d9f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -63,6 +63,9 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, if (fi->stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } } same_el = (arm_current_el(env) == target_el); -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBl-00048Q-2m for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003vr-N4; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56728 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBO-0003UG-5m; Tue, 12 Jan 2021 05:45:55 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id D74C2604F8; Tue, 12 Jan 2021 11:45:14 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 13/19] target/arm: generalize 2-stage page-walk condition Date: Tue, 12 Jan 2021 12:45:05 +0200 Message-Id: <20210112104511.36576-13-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fe95c2965d..d889a6cd17 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12159,11 +12159,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_E10_0 || - mmu_idx == ARMMMUIdx_E10_1 || - mmu_idx == ARMMMUIdx_E10_1_PAN) { + ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + + if (mmu_idx != s1_mmu_idx) { /* Call ourselves recursively to do the stage 1 and then stage 2 - * translations. + * translations if mmu_idx is a two-stage regime. */ if (arm_feature(env, ARM_FEATURE_EL2)) { hwaddr ipa; @@ -12171,9 +12171,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, int ret; ARMCacheAttrs cacheattrs2 = {}; - ret = get_phys_addr(env, address, access_type, - stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fi, cacheattrs); + ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, + attrs, prot, page_size, fi, cacheattrs); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBl-0004AV-MW for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBT-0003vA-Nl; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56730 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBN-0003UF-Ix; Tue, 12 Jan 2021 05:45:55 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 2182460513; Tue, 12 Jan 2021 11:45:15 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 14/19] target/arm: secure stage 2 translation regime Date: Tue, 12 Jan 2021 12:45:06 +0200 Message-Id: <20210112104511.36576-14-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:57 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont --- target/arm/cpu.h | 6 +++- target/arm/helper.c | 78 +++++++++++++++++++++++++++++------------- target/arm/internals.h | 22 ++++++++++++ 3 files changed, 81 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b6685f3746..0f90c772d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3026,6 +3026,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -3033,7 +3036,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, /* * M-profile. diff --git a/target/arm/helper.c b/target/arm/helper.c index d889a6cd17..f451f281f6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3429,7 +3429,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, uint32_t syn, fsr, fsc; bool take_exc = false; - if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) + if (fi.s1ptw && current_el == 1 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the @@ -3586,10 +3586,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN); } else { - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; } break; default: @@ -3603,10 +3603,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_SE10_0; break; case 2: + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3671,10 +3672,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN); } else { - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ @@ -3688,7 +3689,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; @@ -10050,7 +10051,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, hcr_el2 = arm_hcr_el2_eff(env); - if (mmu_idx == ARMMMUIdx_Stage2) { + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; } @@ -10083,6 +10084,9 @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, if (mmu_idx == ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; } + if (mmu_idx == ARMMMUIdx_Stage2_S) { + return env->cp15.vsttbr_el2; + } if (ttbrn == 0) { return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; } else { @@ -10098,6 +10102,12 @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + return ARMMMUIdx_Stage1_SE0; + case ARMMMUIdx_SE10_1: + return ARMMMUIdx_Stage1_SE1; + case ARMMMUIdx_SE10_1_PAN: + return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -10142,6 +10152,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_E20_0: case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -10307,6 +10318,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, int wxn = 0; assert(mmu_idx != ARMMMUIdx_Stage2); + assert(mmu_idx != ARMMMUIdx_Stage2_S); user_rw = simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { @@ -10401,13 +10413,12 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; + ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; ARMCacheAttrs cacheattrs = {}; MemTxAttrs txattrs = {}; - assert(!*is_secure); /* TODO: S-EL2 */ - - ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2, - false, + ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, &s2pa, &txattrs, &s2prot, &s2size, fi, &cacheattrs); if (ret) { @@ -10883,7 +10894,7 @@ static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 37, 2); - } else if (mmu_idx == ARMMMUIdx_Stage2) { + } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { return 0; /* VTCR_EL2 */ } else { /* Replicate the single TBI bit so we always have 2 bits. */ @@ -10895,7 +10906,7 @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 51, 2); - } else if (mmu_idx == ARMMMUIdx_Stage2) { + } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { return 0; /* VTCR_EL2 */ } else { /* Replicate the single TBID bit so we always have 2 bits. */ @@ -10925,7 +10936,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, tsz = extract32(tcr, 0, 6); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); - if (mmu_idx == ARMMMUIdx_Stage2) { + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { /* VTCR_EL2 */ hpd = false; } else { @@ -10990,6 +11001,8 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, int select, tsz; bool epd, hpd; + assert(mmu_idx != ARMMMUIdx_Stage2_S); + if (mmu_idx == ARMMMUIdx_Stage2) { /* VTCR */ bool sext = extract32(tcr, 4, 1); @@ -11155,7 +11168,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, goto do_fault; } - if (mmu_idx != ARMMMUIdx_Stage2) { + if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { /* The starting level depends on the virtual address size (which can * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to @@ -11263,7 +11276,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, attrs = extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); - if (mmu_idx == ARMMMUIdx_Stage2) { + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { /* Stage 2 table descriptors do not include any attribute fields */ break; } @@ -11293,8 +11306,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, ap = extract32(attrs, 4, 2); - if (mmu_idx == ARMMMUIdx_Stage2) { - ns = true; + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + ns = mmu_idx == ARMMMUIdx_Stage2; xn = extract32(attrs, 11, 2); *prot = get_S2prot(env, ap, xn, s1_is_el0); } else { @@ -11321,7 +11334,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, arm_tlb_bti_gp(txattrs) = true; } - if (mmu_idx == ARMMMUIdx_Stage2) { + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4)); } else { /* Index into MAIR registers for cache attributes */ @@ -11340,7 +11353,8 @@ do_fault: fi->type = fault_type; fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2); + fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || + mmu_idx == ARMMMUIdx_Stage2_S); return true; } @@ -12170,6 +12184,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, int s2_prot; int ret; ARMCacheAttrs cacheattrs2 = {}; + ARMMMUIdx s2_mmu_idx; + bool is_el0; ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, attrs, prot, page_size, fi, cacheattrs); @@ -12180,9 +12196,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; + /* S1 is done. Now do S2 translation. */ - ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2, - mmu_idx == ARMMMUIdx_E10_0, + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, phys_ptr, attrs, &s2_prot, page_size, fi, &cacheattrs2); fi->s2addr = ipa; @@ -12209,6 +12227,18 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, cacheattrs->shareability = 0; } *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (arm_is_secure_below_el3(env)) { + if (attrs->secure) { + attrs->secure = + !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); + } else { + attrs->secure = + !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); + } + } return 0; } else { /* @@ -12277,7 +12307,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.TranslateAddressS1Off. */ - if (mmu_idx != ARMMMUIdx_Stage2) { + if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { int r_el = regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax = arm_pamax(env_archcpu(env)); diff --git a/target/arm/internals.h b/target/arm/internals.h index e4e6afef19..3aec10263e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -851,6 +851,9 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -896,7 +899,11 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE20_0: case ARMMMUIdx_SE20_2: case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -911,6 +918,7 @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_1_PAN: @@ -932,18 +940,22 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; case ARMMMUIdx_SE10_0: + case ARMMMUIdx_Stage1_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -967,6 +979,13 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) if (mmu_idx == ARMMMUIdx_Stage2) { return &env->cp15.vtcr_el2; } + if (mmu_idx == ARMMMUIdx_Stage2_S) { + /* + * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but + * those are not currently used by QEMU, so just return VSTCR_EL2. + */ + return &env->cp15.vstcr_el2; + } return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } @@ -1169,6 +1188,9 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: return true; default: return false; -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBl-0004B7-Uo for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBT-0003vD-O5; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56726 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBO-0003UH-6G; Tue, 12 Jan 2021 05:45:54 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 9845B604F4; Tue, 12 Jan 2021 11:45:14 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 12/19] target/arm: translate NS bit in page-walks Date: Tue, 12 Jan 2021 12:45:04 +0200 Message-Id: <20210112104511.36576-12-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:57 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d96897f9a..fe95c2965d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10429,6 +10429,18 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ptw = true; return ~0; } + + if (arm_is_secure_below_el3(env)) { + /* Check if page table walk is to secure or non-secure PA space. */ + if (*is_secure) { + *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!*is_secure); + } + addr = s2pa; } return addr; -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBm-0004By-6H for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003vq-N7; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56714 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBR-0003Ss-0H; Tue, 12 Jan 2021 05:45:56 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 2AAE760705; Tue, 12 Jan 2021 11:45:16 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 18/19] target/arm: enable Secure EL2 in max CPU Date: Tue, 12 Jan 2021 12:45:10 +0200 Message-Id: <20210112104511.36576-18-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index da24f94baa..8d3473db3e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -641,6 +641,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBm-0004Ca-CV for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBV-0003w5-OS; Tue, 12 Jan 2021 05:45:57 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:56720 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzHBQ-0003Su-VH; Tue, 12 Jan 2021 05:45:56 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id A087B60604; Tue, 12 Jan 2021 11:45:15 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org Subject: [PATCH 16/19] target/arm: revector to run-time pick target EL Date: Tue, 12 Jan 2021 12:45:08 +0200 Message-Id: <20210112104511.36576-16-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> References: <12681824.uLZWGnKmhe@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:45:58 -0000 From: Rémi Denis-Courmont On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to the upper (64-bit) EL. With Secure EL2 support, we can no longer assume that that is always EL3, so make room for the value to be computed at run-time. Signed-off-by: Rémi Denis-Courmont --- target/arm/translate.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76..8b6b7355c9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,6 +1094,22 @@ static void unallocated_encoding(DisasContext *s) default_exception_el(s)); } +static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, + TCGv_i32 tcg_el) +{ + TCGv_i32 tcg_excp; + TCGv_i32 tcg_syn; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + tcg_excp = tcg_const_i32(excp); + tcg_syn = tcg_const_i32(syn); + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el); + tcg_temp_free_i32(tcg_syn); + tcg_temp_free_i32(tcg_excp); + s->base.is_jmp = DISAS_NORETURN; +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -2818,8 +2834,11 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, /* If we're in Secure EL1 (which implies that EL3 is AArch64) * then accesses to Mon registers trap to EL3 */ - exc_target = 3; - goto undef; + TCGv_i32 tcg_el = tcg_const_i32(3); + + gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); + tcg_temp_free_i32(tcg_el); + return false; } break; case ARM_CPU_MODE_HYP: -- 2.30.0 From MAILER-DAEMON Tue Jan 12 05:46:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHBy-0004Wy-Ni for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:46:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHBw-0004SC-OV for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:46:24 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:43159) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzHBu-0003mm-TM for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:46:24 -0500 Received: by mail-ed1-x52f.google.com with SMTP id by27so1533606edb.10 for ; Tue, 12 Jan 2021 02:46:22 -0800 (PST) DKIM-Signature: v=1; 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Tue, 12 Jan 2021 02:46:21 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-7-bmeng.cn@gmail.com> In-Reply-To: <20210110081429.10126-7-bmeng.cn@gmail.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:46:09 +0000 Message-ID: Subject: Re: [PATCH v4 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Bin Meng Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:46:25 -0000 On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > From: Bin Meng > > The endianness of data exchange between tx and rx fifo is incorrect. > Earlier bytes are supposed to show up on MSB and later bytes on LSB, > ie: in big endian. The manual does not explicitly say this, but the > U-Boot and Linux driver codes have a swap on the data transferred > to tx fifo and from rx fifo. > > With this change, U-Boot read from / write to SPI flash tests pass. > > => sf test 1ff000 1000 > SPI flash test: > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > Test passed > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - Simplify the tx fifo endianness handling > > hw/ssi/imx_spi.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 47c8a0f572..b5124a6426 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -171,7 +171,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > while (!fifo32_is_empty(&s->tx_fifo)) { > int tx_burst = 0; > - int index = 0; > > if (s->burst_length <= 0) { > s->burst_length = imx_spi_burst_length(s); > @@ -192,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > rx = 0; > > while (tx_burst > 0) { > - uint8_t byte = tx & 0xff; > + uint8_t byte = tx >> (tx_burst - 8); > > DPRINTF("writing 0x%02x\n", (uint32_t)byte); > > @@ -201,13 +200,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > DPRINTF("0x%02x read\n", (uint32_t)byte); > > - tx = tx >> 8; > - rx |= (byte << (index * 8)); > + rx = (rx << 8) | byte; > > /* Remove 8 bits from the actual burst */ > tx_burst -= 8; > s->burst_length -= 8; > - index++; > } This version of the loop definitely looks a lot neater. However, looking at the code I don't think there's anything that forces the guest to set a burst length that's a multiple of 8, so you need to handle that somehow. Otherwise on the last time through the loop (tx_burst - 8) can be negative, which is undefined behaviour when you try to shift by it. I think just rounding tx_burst up to a multiple of 8 before the start of the loop would do the right thing ? thanks -- PMM From MAILER-DAEMON Tue Jan 12 05:49:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHEh-0007yq-HG for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 05:49:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHEf-0007ue-EM for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:49:13 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:37598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzHEc-0004Z6-M9 for qemu-arm@nongnu.org; Tue, 12 Jan 2021 05:49:13 -0500 Received: by mail-ej1-x633.google.com with SMTP id ga15so2855637ejb.4 for ; Tue, 12 Jan 2021 02:49:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; 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Tue, 12 Jan 2021 02:49:08 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> In-Reply-To: <20210110081429.10126-3-bmeng.cn@gmail.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:48:57 +0000 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 10:49:13 -0000 On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > From: Bin Meng > > Usually the approach is that the device on the other end of the line > is going to reset its state anyway, so there's no need to actively > signal an irq line change during the reset hook. > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > imx_spi_hard_reset() that is called when the controller is disabled. > > Signed-off-by: Bin Meng > > --- > > Changes in v4: > - adujst the patch 2,3 order > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > Changes in v3: > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > hw/ssi/imx_spi.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index e605049a21..2c4c5ec1b8 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > imx_spi_rxfifo_reset(s); > imx_spi_txfifo_reset(s); > > - imx_spi_update_irq(s); > - > s->burst_length = 0; > } > > +static void imx_spi_hard_reset(IMXSPIState *s) > +{ > + imx_spi_reset(DEVICE(s)); > + > + imx_spi_update_irq(s); > +} > + > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > { > uint32_t value = 0; > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > s->regs[ECSPI_CONREG] = value; > > if (!imx_spi_is_enabled(s)) { > - /* device is disabled, so this is a reset */ > - imx_spi_reset(DEVICE(s)); > + /* device is disabled, so this is a hard reset */ > + imx_spi_hard_reset(s); > + > return; > } The function of the code is correct, but you seem to have the function naming backwards here. Generally: * soft reset == the reset triggered by the register write * hard reset == power-on reset == the dc->reset function I think this is what Philippe was trying to say. thanks -- PMM From MAILER-DAEMON Tue Jan 12 06:30:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHsH-0004mx-J0 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 06:30:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHsE-0004jf-40 for qemu-arm@nongnu.org; Tue, 12 Jan 2021 06:30:06 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:42770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzHs8-0001Rg-0s for qemu-arm@nongnu.org; Tue, 12 Jan 2021 06:30:05 -0500 Received: by mail-ej1-x636.google.com with SMTP id d17so2982074ejy.9 for ; Tue, 12 Jan 2021 03:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Q/fRAJM1ajfNwQd5upbxc/igAiZlzPCEuC0QiXaTWaI=; b=z3V/2afBjagaqzONjYB9cmQBojWCWLmj6w8hpySF5No9Jkiw4LXWsEuErh9joXeSAl c8kTkR/AamYBRuzflismdda8rgcsdKtFRTFN03GhW8AmjrR8MMyvk9+mGRo3g1sQx7qI hI6lKZteUAN42LJoRtb2KYggvDqKYZlJc/aWTAKbgKNKaLSsRYYND1Zi4c+OpV7G7FYH 6ExRIkoNKHq/Q86jB5ngKKoteAoYDTHzs1cepXgEQRrwo3cFsOpO1DQTY0MR7MTAZAjs hRaxCKEz/rYBTW3g7UBNpOJStCiw4Elj03rzjdilATbhF2ON2kOoDGR923Cd/LtnxWt0 JJew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Q/fRAJM1ajfNwQd5upbxc/igAiZlzPCEuC0QiXaTWaI=; b=dLMMMlEwWB03ZSc3QySWEAAOAKUrdZzO7ASpahAK+qA+p6td8V3DfSMLsRsReLZKOf vgMomMYFpT+8Bso+RD7Ht5Ft91mWN5I0S1TWVhK1R10qv9a+2d+A6PovYNgQkEjEdcJZ 5GZj0zg9yko0Q0QAefhp74Ma5z+iJQIAepUqDdNIC1ZCv52qUngeG3kjrWunmU9IHKra G0ar9ffac7G6pRKvrJpQFs3IhM3VycqT54GQi825t39Px0zUHh0fPy3lFJ7WaT3aGADM bnWgRrTtmkBUwumgJbmR/OpBSEHCNebQ2jYYQsfiMbj4XdRFor1RSOq2mYJNdL77leWX /4IA== X-Gm-Message-State: AOAM5317oZWITb57SdUgw3ox/SxrQCQ13jTr2ARmPJMaaPMXE+gEwwDZ 0fSfD1RXtFnEEK7YUHVC7qliGLWL6QWEn0t1b/lrxQ== X-Google-Smtp-Source: ABdhPJw4eMYSiv8BN0ZFKMfV0Ak99x6j7RISLBBhNH3pY76s6gX0+MsdbkOY8rADDVFChgDBdUtABTaXOKwlhjHzl4E= X-Received: by 2002:a17:906:3d4a:: with SMTP id q10mr2907537ejf.85.1610450998050; Tue, 12 Jan 2021 03:29:58 -0800 (PST) MIME-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> <20210108190945.949196-4-wuhaotsh@google.com> In-Reply-To: <20210108190945.949196-4-wuhaotsh@google.com> From: Peter Maydell Date: Tue, 12 Jan 2021 11:29:46 +0000 Message-ID: Subject: Re: [PATCH v5 3/6] hw/adc: Add an ADC module for NPCM7XX To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 11:30:06 -0000 On Fri, 8 Jan 2021 at 19:10, Hao Wu wrote: > > The ADC is part of NPCM7XX Module. Its behavior is controled by the > ADC_CON register. It converts one of the eight analog inputs into a > digital input and stores it in the ADC_DATA register when enabled. > > Users can alter input value by using qom-set QMP command. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu > --- > docs/system/arm/nuvoton.rst | 2 +- > hw/adc/meson.build | 1 + > hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++ > hw/adc/trace-events | 5 + > hw/arm/npcm7xx.c | 24 ++- > include/hw/adc/npcm7xx_adc.h | 69 ++++++ > include/hw/arm/npcm7xx.h | 2 + > meson.build | 1 + > tests/qtest/meson.build | 3 +- > tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++ Adding trace events to a directory for the first time requires also adding the hw/adc/trace.h file (which just has a single line '#include "trace/trace-hw_adc.h"'), otherwise this doesn't compile. I think that's the only issue with this patchset, though, so I'll just fix it up locally. (Stefan is going to send a patch fixing docs/devel/tracing.txt, which failed to mention the need for this step when adding a new subdir to tracing.) thanks -- PMM From MAILER-DAEMON Tue Jan 12 06:31:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzHtp-00060V-U3 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 06:31:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzHto-0005wK-88 for qemu-arm@nongnu.org; Tue, 12 Jan 2021 06:31:44 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:44169) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzHtl-000260-NE for qemu-arm@nongnu.org; Tue, 12 Jan 2021 06:31:43 -0500 Received: by mail-ej1-x62f.google.com with SMTP id w1so2973520ejf.11 for ; Tue, 12 Jan 2021 03:31:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Z4yU4z7LjBbWtwDVWg9Fzy18EUDDU7JBdYr1lPxZwyQ=; b=vgrI7LmZukUVpIY0MlLqDNn2zEkeAbj6j6Nw5alh2nf/on4Z4fFDauRNAuLSJJMell 24plVha/x4SvYfIJj9jdbn+3LxnAevavUnTfO8wgcQTpLcvBhdP6rsmzJ/1KEvIc+GQU GdTvGK4qyxnOyCskdmVpYjjVTp3dKWOUZdqBB6B1PaTZ70mkctIdyywB9eQE65zhMYks +bE7aviWqzZUXLMujbEbMhoR7Ld26OBGi0o7ZyucSPywDUCZNT+av2Wqo7hQJqE9SaIg ykbPtcwXgmp8U+trkba21B6aEUuY3AV5q12QknzqcAisI7zZJDFNlKGnTLkHzzgr2L9C jkjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Z4yU4z7LjBbWtwDVWg9Fzy18EUDDU7JBdYr1lPxZwyQ=; b=bN41WmTmSou+YFwx9vw6d2tyWNkn1n+tgymiICG47WvmdqcwfjQTP7AwUMFrAJVMan jgj7W17wXNl0NR6DH0YxyJFTBeJh9FCsLM0LpsXP9sHtjMBuL27TJVqo/o7r/XQmhrPK tVQi1rmBdMUrxKbQ5ZLWAOamCoSEF3/tn463tC6oFt2LbTNFgywj87AuykdUswjklF6O lsnLlgA/NQ03ywwrX6cMfGxKrENbthN9MyRONgCyo6wc/tuZK/WSRMQZDmC6v+ku4nxw KSp0HTpqH6F14Mz0GhCa+M7ae2bvQ2Ny1mZ5S8EWA7m4jdzx7Dwpna4QsLLUS19olEjf aFBA== X-Gm-Message-State: AOAM531wd8G4rg/ZelGnYzfhlmXTjgOl5kCTuziLIZKwahniRM3fIhpC zoW7KGNcS0bQZty8jg4gPlNj34GOiBs6lJsJkp9vaQ== X-Google-Smtp-Source: ABdhPJz/A/y51JXwVtsHicvKL1YY4w2ZYCNzH/iMEq6g6qpoirQRYydYdY7vl5X3Dh4ZZbfzQPF7CMRtoo6PPFQ9nzc= X-Received: by 2002:a17:906:e94c:: with SMTP id jw12mr3005813ejb.56.1610451100135; Tue, 12 Jan 2021 03:31:40 -0800 (PST) MIME-Version: 1.0 References: <20210108190945.949196-1-wuhaotsh@google.com> In-Reply-To: <20210108190945.949196-1-wuhaotsh@google.com> From: Peter Maydell Date: Tue, 12 Jan 2021 11:31:29 +0000 Message-ID: Subject: Re: [PATCH v5 0/6] Additional NPCM7xx devices To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Corey Minyard , Havard Skinnemoen , Patrick Venture , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 11:31:44 -0000 On Fri, 8 Jan 2021 at 19:10, Hao Wu wrote: > > This patch series include a few more NPCM7XX devices including > > - Analog Digital Converter (ADC) > - Pulse Width Modulation (PWM) > > We also modified the CLK module to generate clock values using qdev_clock. > These clocks are used to determine various clocks in NPCM7XX devices. > > Thank you for your review. Applied to target-arm.next with a fixup to the ADC patch for the missing trace.h file. thanks -- PMM From MAILER-DAEMON Tue Jan 12 07:48:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzJ6L-0001Vd-6f for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 07:48:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJ6K-0001UG-1h; Tue, 12 Jan 2021 07:48:44 -0500 Received: from mail-yb1-xb36.google.com ([2607:f8b0:4864:20::b36]:34514) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzJ6H-000388-OG; Tue, 12 Jan 2021 07:48:43 -0500 Received: by mail-yb1-xb36.google.com with SMTP id x6so1591042ybr.1; Tue, 12 Jan 2021 04:48:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9POOe9Uv0dP1f0gRGFIKg+L5i1Fh268DrexSVAThGAc=; b=R0HCgg5g0o7UXktJCq3bf8od7RrFGGfPfVrbszzg5smSi6au/Ln+YlWG/YOPmBnPbc 7fAX35itlFUx9pMlmcREj7/p9ydry4sSfDUyq7wnfro0x0tChzNahgW/QYo/+n4LjTGj BhAqvufKWT+Dn4Bg/b0b/AA3oH7r7d0x1RHcEqNI4tznriPAl56/HgS/RaALrbwRNbii 18DQw2ESdI0qKzxSpSPs0nycuPJuV0TxQ8fJy96E7ygjrh37OgdinSREgIBECTtSoeki 57t8gInkvECtxdZPRqkIvwvOSfFbqKt84AV/TFoYTw/Rb8Vw8a3gWymZBLcCF9sCH9LJ 9Zew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9POOe9Uv0dP1f0gRGFIKg+L5i1Fh268DrexSVAThGAc=; b=Bz0ZqBhSbwQ1mJrGgW0IaQnUMbj+8AVjF3rIiER4tHHYMitE4DS1RTDbbtwLibuo5C rTsJPE2G8LG8WcEoFqkf1SJ6/Xo6OiGOuBczU7t1CWa25CXU9g1CS8axVmuJfM+wQZBS o7Q9Zjrxji3G0EK+Y13ARU17XbClapCx7s8gk426i2aRIwyZHRug8QLWurMh7XlEFdut EVbFsHby73yfnORdLHe7/D1PileuxoT75zHJdE38+2ELiNwySYswvS6oBQuRswx6IOYZ 1MiwJrbLVVTh/e/bd1Kh9uWWXfxxiG3c41HDkQDjuYjHisbNTe/Zq6McoAWA5+5MACfW MR7g== X-Gm-Message-State: AOAM531h51cA9IqGFa9ABtLoYhnnogP5CXj0up9Y5+ISPQy57hz1zsU7 pabIdb9w96ce20ho7iMXeCMH5/D2eeFW5DBkRA4= X-Google-Smtp-Source: ABdhPJy7sytdeT5R+ROamT5uavKdjkg1ompZLPf3BRjMa+t21mwp1yeCqUzYbq7Y6V6CLFsrdhQIrMWMO5Fx8tdn1PE= X-Received: by 2002:a25:3bc5:: with SMTP id i188mr3259533yba.332.1610455720151; Tue, 12 Jan 2021 04:48:40 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-7-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Tue, 12 Jan 2021 20:48:29 +0800 Message-ID: Subject: Re: [PATCH v4 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Peter Maydell Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b36; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 12:48:44 -0000 On Tue, Jan 12, 2021 at 6:46 PM Peter Maydell wrote: > > On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > > > From: Bin Meng > > > > The endianness of data exchange between tx and rx fifo is incorrect. > > Earlier bytes are supposed to show up on MSB and later bytes on LSB, > > ie: in big endian. The manual does not explicitly say this, but the > > U-Boot and Linux driver codes have a swap on the data transferred > > to tx fifo and from rx fifo. > > > > With this change, U-Boot read from / write to SPI flash tests pass. > > > > => sf test 1ff000 1000 > > SPI flash test: > > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > Test passed > > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > > Signed-off-by: Bin Meng > > > > --- > > > > (no changes since v3) > > > > Changes in v3: > > - Simplify the tx fifo endianness handling > > > > hw/ssi/imx_spi.c | 7 ++----- > > 1 file changed, 2 insertions(+), 5 deletions(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index 47c8a0f572..b5124a6426 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -171,7 +171,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > > > while (!fifo32_is_empty(&s->tx_fifo)) { > > int tx_burst = 0; > > - int index = 0; > > > > if (s->burst_length <= 0) { > > s->burst_length = imx_spi_burst_length(s); > > @@ -192,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > rx = 0; > > > > while (tx_burst > 0) { > > - uint8_t byte = tx & 0xff; > > + uint8_t byte = tx >> (tx_burst - 8); > > > > DPRINTF("writing 0x%02x\n", (uint32_t)byte); > > > > @@ -201,13 +200,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > > > DPRINTF("0x%02x read\n", (uint32_t)byte); > > > > - tx = tx >> 8; > > - rx |= (byte << (index * 8)); > > + rx = (rx << 8) | byte; > > > > /* Remove 8 bits from the actual burst */ > > tx_burst -= 8; > > s->burst_length -= 8; > > - index++; > > } > > This version of the loop definitely looks a lot neater. However, > looking at the code I don't think there's anything that forces the > guest to set a burst length that's a multiple of 8, so you need > to handle that somehow. Otherwise on the last time through the > loop (tx_burst - 8) can be negative, which is undefined behaviour > when you try to shift by it. Yes, that's why I added a patch to log the unimplemented behavior to notify the user. > I think just rounding tx_burst up to a multiple of 8 before > the start of the loop would do the right thing ? Probably. Given all flash transfers are normally multiple of 8-bits I am not sure what the real hardware behavior is when it is not multiple of 8, but I will try to add something in the next version. Regards, Bin From MAILER-DAEMON Tue Jan 12 07:54:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzJBm-0005rS-DV for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 07:54:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJBl-0005qy-57; Tue, 12 Jan 2021 07:54:21 -0500 Received: from mail-yb1-xb2b.google.com ([2607:f8b0:4864:20::b2b]:41295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzJBj-0005M9-Ip; Tue, 12 Jan 2021 07:54:20 -0500 Received: by mail-yb1-xb2b.google.com with SMTP id w127so2047895ybw.8; Tue, 12 Jan 2021 04:54:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+V9p+fDZKLSr4OjbB1jdKf4hhGBIxJJobfGwO2itWTY=; b=Ao49IdWdnADQjgMqngoiBjUqE+JPTv9BE9GK+9Q2itm2OOXJ8WD4wzdGm4aDbLk6v5 DAxcJBn2tmUWJ9riR4Wp6fM1RR1JkIsYWEYSEhXPqQ+HEVIjyF9oO/+9i7aUairvfRCR Y9bVXJ6g3MgCK/Ujt2BRX9se8ts/wh1iEVergiE+iNiQrBuaRbBIyNu46tmi//nomt+3 4Hdran5oeSr8VT9x5NUSGoOOeJ0BsMO5wNnOWQF7ELDUAWp4WlMDpZN6djZkfzwPfPjU /Z2kOM57mjsVXmJCEdWJRSaJmOUE53xNVlJYr307+8s+lWhwpYeHThhg+XKGzTALjJtY H+NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+V9p+fDZKLSr4OjbB1jdKf4hhGBIxJJobfGwO2itWTY=; b=bmGgiqxIOUjie2bf5Cr4lXbjA/3nTx6Si8nH2LdbDOkUfyty7kbx3ONjeOBwNpqxej 9nJlZmsRB+iwKFtJEi3gSjoCgpy7ZFrlrxJAWor87ziJLIHp0vnjkh/EWpns9Jr5t3TZ UFOULRsCJNKdub5+Af9rx1JKkGK/dQvNwwF/LB+QYShHgZMfhX8W+Ka/InuurJ63lnQy 2iZ8E4u9HMAvsVMes4YQ/O4uhVpsVnFwrT8BRhX/dKKWvcQiGXr7kvRakwrrIxLFIf3z C5Q60cXY+aTMqhH5/VKiImx7eq0sizlexkVb1RKIV/LurZrN8WmvM6cG9pj+6CSQCIk4 CVYg== X-Gm-Message-State: AOAM531Xp9ePi75asXbq6YNe6GUyVSXhFj8ZcpNQguOyQt6Z0zxLcHQF 6p1o8IvPrY2mpiaEPWtjn30brI9sNi66Ul2iebI= X-Google-Smtp-Source: ABdhPJxLo++A+5/7DZ2t+kTXFA5/IFYGg+Q6xfzVt2c7e9+G48xMdwysEKSi+zIUu32vcnQ0Hr8IiVf1Yn69XECkQso= X-Received: by 2002:a25:690b:: with SMTP id e11mr6418052ybc.314.1610456058206; Tue, 12 Jan 2021 04:54:18 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Tue, 12 Jan 2021 20:54:07 +0800 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Peter Maydell Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2b; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 12:54:21 -0000 On Tue, Jan 12, 2021 at 6:49 PM Peter Maydell wrote: > > On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > > > From: Bin Meng > > > > Usually the approach is that the device on the other end of the line > > is going to reset its state anyway, so there's no need to actively > > signal an irq line change during the reset hook. > > > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > > imx_spi_hard_reset() that is called when the controller is disabled. > > > > Signed-off-by: Bin Meng > > > > --- > > > > Changes in v4: > > - adujst the patch 2,3 order > > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > > > Changes in v3: > > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > > > hw/ssi/imx_spi.c | 14 ++++++++++---- > > 1 file changed, 10 insertions(+), 4 deletions(-) > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index e605049a21..2c4c5ec1b8 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > > imx_spi_rxfifo_reset(s); > > imx_spi_txfifo_reset(s); > > > > - imx_spi_update_irq(s); > > - > > s->burst_length = 0; > > } > > > > +static void imx_spi_hard_reset(IMXSPIState *s) > > +{ > > + imx_spi_reset(DEVICE(s)); > > + > > + imx_spi_update_irq(s); > > +} > > + > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > > { > > uint32_t value = 0; > > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > > s->regs[ECSPI_CONREG] = value; > > > > if (!imx_spi_is_enabled(s)) { > > - /* device is disabled, so this is a reset */ > > - imx_spi_reset(DEVICE(s)); > > + /* device is disabled, so this is a hard reset */ > > + imx_spi_hard_reset(s); > > + > > return; > > } > > The function of the code is correct, but you seem to have the function > naming backwards here. Generally: > * soft reset == the reset triggered by the register write > * hard reset == power-on reset == the dc->reset function > > I think this is what Philippe was trying to say. Philippe said: "Hmm usually hard reset include soft reset." Since we are moving imx_spi_update_irq() out of imx_spi_reset() to a new function called imx_spi_soft_reset() (what I did in v3), that confused him (and I felt the same thing), so I renamed imx_spi_soft_reset() to imx_spi_hard_reset() in v4.. Regards, Bin From MAILER-DAEMON Tue Jan 12 08:19:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzJaE-0000rA-3o for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 08:19:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJa8-0000pm-PO for qemu-arm@nongnu.org; Tue, 12 Jan 2021 08:19:32 -0500 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]:37287) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzJa5-0005Th-PS for qemu-arm@nongnu.org; Tue, 12 Jan 2021 08:19:32 -0500 Received: by mail-ed1-x52e.google.com with SMTP id cm17so2272031edb.4 for ; Tue, 12 Jan 2021 05:19:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=JV0fYik8m6jI9UqV5DS+cgAM+658ePS9bQ6bTpjmVVk=; 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Tue, 12 Jan 2021 05:19:27 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> In-Reply-To: From: Peter Maydell Date: Tue, 12 Jan 2021 13:19:16 +0000 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 13:19:33 -0000 On Tue, 12 Jan 2021 at 12:54, Bin Meng wrote: > > On Tue, Jan 12, 2021 at 6:49 PM Peter Maydell wrote: > > > > On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > Usually the approach is that the device on the other end of the line > > > is going to reset its state anyway, so there's no need to actively > > > signal an irq line change during the reset hook. > > > > > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > > > imx_spi_hard_reset() that is called when the controller is disabled. > > > > > > Signed-off-by: Bin Meng > > > > > > --- > > > > > > Changes in v4: > > > - adujst the patch 2,3 order > > > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > > > > > Changes in v3: > > > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > > > > > hw/ssi/imx_spi.c | 14 ++++++++++---- > > > 1 file changed, 10 insertions(+), 4 deletions(-) > > > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > > index e605049a21..2c4c5ec1b8 100644 > > > --- a/hw/ssi/imx_spi.c > > > +++ b/hw/ssi/imx_spi.c > > > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > > > imx_spi_rxfifo_reset(s); > > > imx_spi_txfifo_reset(s); > > > > > > - imx_spi_update_irq(s); > > > - > > > s->burst_length = 0; > > > } > > > > > > +static void imx_spi_hard_reset(IMXSPIState *s) > > > +{ > > > + imx_spi_reset(DEVICE(s)); > > > + > > > + imx_spi_update_irq(s); > > > +} > > > + > > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > > > { > > > uint32_t value = 0; > > > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > > > s->regs[ECSPI_CONREG] = value; > > > > > > if (!imx_spi_is_enabled(s)) { > > > - /* device is disabled, so this is a reset */ > > > - imx_spi_reset(DEVICE(s)); > > > + /* device is disabled, so this is a hard reset */ > > > + imx_spi_hard_reset(s); > > > + > > > return; > > > } > > > > The function of the code is correct, but you seem to have the function > > naming backwards here. Generally: > > * soft reset == the reset triggered by the register write > > * hard reset == power-on reset == the dc->reset function > > > > I think this is what Philippe was trying to say. > > Philippe said: "Hmm usually hard reset include soft reset." True in hardware, but for QEMU there are some things we don't want to do in what we would call a hard or power-on reset. > Since we are moving imx_spi_update_irq() out of imx_spi_reset() to a > new function called imx_spi_soft_reset() (what I did in v3), that > confused him (and I felt the same thing), so I renamed > imx_spi_soft_reset() to imx_spi_hard_reset() in v4.. thanks -- PMM From MAILER-DAEMON Tue Jan 12 08:22:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzJdM-0002lU-VJ for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 08:22:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJdI-0002k9-Ih; Tue, 12 Jan 2021 08:22:49 -0500 Received: from mail-yb1-xb32.google.com ([2607:f8b0:4864:20::b32]:46359) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzJdF-0006Y5-8L; Tue, 12 Jan 2021 08:22:48 -0500 Received: by mail-yb1-xb32.google.com with SMTP id f6so2101314ybq.13; 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Tue, 12 Jan 2021 05:22:43 -0800 (PST) MIME-Version: 1.0 References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Tue, 12 Jan 2021 21:22:32 +0800 Message-ID: Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Peter Maydell Cc: Jean-Christophe Dubois , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-arm , QEMU Developers , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 13:22:49 -0000 On Tue, Jan 12, 2021 at 9:19 PM Peter Maydell wrote: > > On Tue, 12 Jan 2021 at 12:54, Bin Meng wrote: > > > > On Tue, Jan 12, 2021 at 6:49 PM Peter Maydell wrote: > > > > > > On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: > > > > > > > > From: Bin Meng > > > > > > > > Usually the approach is that the device on the other end of the line > > > > is going to reset its state anyway, so there's no need to actively > > > > signal an irq line change during the reset hook. > > > > > > > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > > > > imx_spi_hard_reset() that is called when the controller is disabled. > > > > > > > > Signed-off-by: Bin Meng > > > > > > > > --- > > > > > > > > Changes in v4: > > > > - adujst the patch 2,3 order > > > > - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion > > > > > > > > Changes in v3: > > > > - new patch: remove imx_spi_update_irq() in imx_spi_reset() > > > > > > > > hw/ssi/imx_spi.c | 14 ++++++++++---- > > > > 1 file changed, 10 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > > > index e605049a21..2c4c5ec1b8 100644 > > > > --- a/hw/ssi/imx_spi.c > > > > +++ b/hw/ssi/imx_spi.c > > > > @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) > > > > imx_spi_rxfifo_reset(s); > > > > imx_spi_txfifo_reset(s); > > > > > > > > - imx_spi_update_irq(s); > > > > - > > > > s->burst_length = 0; > > > > } > > > > > > > > +static void imx_spi_hard_reset(IMXSPIState *s) > > > > +{ > > > > + imx_spi_reset(DEVICE(s)); > > > > + > > > > + imx_spi_update_irq(s); > > > > +} > > > > + > > > > static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) > > > > { > > > > uint32_t value = 0; > > > > @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, > > > > s->regs[ECSPI_CONREG] = value; > > > > > > > > if (!imx_spi_is_enabled(s)) { > > > > - /* device is disabled, so this is a reset */ > > > > - imx_spi_reset(DEVICE(s)); > > > > + /* device is disabled, so this is a hard reset */ > > > > + imx_spi_hard_reset(s); > > > > + > > > > return; > > > > } > > > > > > The function of the code is correct, but you seem to have the function > > > naming backwards here. Generally: > > > * soft reset == the reset triggered by the register write > > > * hard reset == power-on reset == the dc->reset function > > > > > > I think this is what Philippe was trying to say. > > > > Philippe said: "Hmm usually hard reset include soft reset." > > True in hardware, but for QEMU there are some things we don't > want to do in what we would call a hard or power-on reset. > OK, will revert to use imx_spi_soft_reset(). > > Since we are moving imx_spi_update_irq() out of imx_spi_reset() to a > > new function called imx_spi_soft_reset() (what I did in v3), that > > confused him (and I felt the same thing), so I renamed > > imx_spi_soft_reset() to imx_spi_hard_reset() in v4.. Regards, Bin From MAILER-DAEMON Tue Jan 12 08:27:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzJhk-0005mZ-N2 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 08:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJhj-0005ke-Kp; Tue, 12 Jan 2021 08:27:23 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2914) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzJgu-0007dj-07; Tue, 12 Jan 2021 08:27:23 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DFWXH2sT5z15s2h; Tue, 12 Jan 2021 21:25:03 +0800 (CST) Received: from [10.174.186.67] (10.174.186.67) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 21:25:56 +0800 Subject: Re: [RFC PATCH v3 10/13] target/arm/cpu: Add cpu cache description for arm To: Peter Maydell CC: QEMU Developers , qemu-arm , Andrew Jones , Igor Mammedov , Shannon Zhao , Alistair Francis , zhanghailiang , References: <20201109030452.2197-1-fangying1@huawei.com> <20201109030452.2197-11-fangying1@huawei.com> From: Ying Fang Message-ID: <41e9d848-c478-8873-769b-e1cc85253db7@huawei.com> Date: Tue, 12 Jan 2021 21:25:56 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.186.67] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.190; envelope-from=fangying1@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 13:27:23 -0000 On 11/30/2020 9:00 PM, Peter Maydell wrote: > On Mon, 9 Nov 2020 at 03:05, Ying Fang wrote: >> >> Add the CPUCacheInfo structure to hold cpu cache information for ARM cpus. >> A classic three level cache topology is used here. The default cache >> capacity is given and userspace can overwrite these values. >> >> Signed-off-by: Ying Fang >> --- >> target/arm/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ >> target/arm/cpu.h | 27 +++++++++++++++++++++++++++ >> 2 files changed, 69 insertions(+) >> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 056319859f..f1bac7452c 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -27,6 +27,7 @@ >> #include "qapi/visitor.h" >> #include "cpu.h" >> #include "internals.h" >> +#include "qemu/units.h" >> #include "exec/exec-all.h" >> #include "hw/qdev-properties.h" >> #if !defined(CONFIG_USER_ONLY) >> @@ -997,6 +998,45 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) >> return (Aff1 << ARM_AFF1_SHIFT) | Aff0; >> } >> >> +static CPUCaches default_cache_info = { >> + .l1d_cache = &(CPUCacheInfo) { >> + .type = DATA_CACHE, >> + .level = 1, >> + .size = 64 * KiB, >> + .line_size = 64, >> + .associativity = 4, >> + .sets = 256, >> + .attributes = 0x02, >> + }, > > Would it be possible to populate this structure from the > CLIDR/CCSIDR ID register values, rather than having to > specify the same thing in two places? Sorry I missed this reply. I had tried to fetch CLIDR/CCSID ID register values of host cpu from KVM, however I did not get the value expected. May I made some mistakes in KVM side. Thanks for your guide, I'll try to populate them again. > > thanks > -- PMM > . > Thanks. Ying. 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Tue, 12 Jan 2021 06:31:01 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, Maxim Uvarov Subject: [PATCHv4 0/2] arm-virt: add secure pl061 for reset/power down Date: Tue, 12 Jan 2021 17:30:56 +0300 Message-Id: <20210112143058.12159-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:31:08 -0000 v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/dd4401d8eb8e0f3018b335b81ce7a96d6cb16d0f Previus discussion for reboot issue was here: https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html Maxim Uvarov (2): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: add secure pl061 for reset/power down hw/arm/Kconfig | 1 + hw/arm/virt.c | 40 +++++++++++++++++++++++++ hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 3 ++ 6 files changed, 118 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Tue Jan 12 09:31:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzKhZ-0006Fa-GE for mharc-qemu-arm@gnu.org; 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Tue, 12 Jan 2021 06:31:03 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, Maxim Uvarov Subject: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down Date: Tue, 12 Jan 2021 17:30:58 +0300 Message-Id: <20210112143058.12159-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112143058.12159-1-maxim.uvarov@linaro.org> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:31:11 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 3 +++ 3 files changed, 44 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..19605390c2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, + [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, @@ -864,6 +865,32 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } +#define ATF_GPIO_POWEROFF 3 +#define ATF_GPIO_REBOOT 4 + +static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) +{ + DeviceState *gpio_pwr_dev; + SysBusDevice *s; + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; + DeviceState *pl061_dev; + + /* Secure pl061 */ + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); +} + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -1993,6 +2020,10 @@ static void machvirt_init(MachineState *machine) create_gpio(vms); } + if (vms->secure && vms->secure_gpio) { + create_gpio_secure(vms, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2567,6 +2598,12 @@ static void virt_instance_init(Object *obj) vms->its = true; } + if (vmc->no_secure_gpio) { + vms->secure_gpio = false; + } else { + vms->secure_gpio = true; + } + /* Default disallows iommu instantiation */ vms->iommu = VIRT_IOMMU_NONE; @@ -2608,8 +2645,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..a140e75444 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { @@ -136,6 +138,7 @@ struct VirtMachineState { FWCfgState *fw_cfg; PFlashCFI01 *flash[2]; bool secure; + bool secure_gpio; bool highmem; bool highmem_ecam; bool its; -- 2.17.1 From MAILER-DAEMON Tue Jan 12 09:31:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzKha-0006Ia-MZ for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:31:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzKhT-0006E0-6Z for qemu-arm@nongnu.org; Tue, 12 Jan 2021 09:31:11 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]:33412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzKhO-0004ff-Eq for qemu-arm@nongnu.org; Tue, 12 Jan 2021 09:31:10 -0500 Received: by mail-lj1-x234.google.com with SMTP id u21so3093415lja.0 for ; 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Tue, 12 Jan 2021 06:31:03 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id c24sm365499ljn.116.2021.01.12.06.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:31:02 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, Maxim Uvarov Subject: [PATCHv4 1/2] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Tue, 12 Jan 2021 17:30:57 +0300 Message-Id: <20210112143058.12159-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210112143058.12159-1-maxim.uvarov@linaro.org> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:31:11 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..8ed8d5d24f --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Tue Jan 12 09:55:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5F-0007mc-NC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5E-0007l9-FS; Tue, 12 Jan 2021 09:55:44 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:55195) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5B-0004j5-Ou; Tue, 12 Jan 2021 09:55:44 -0500 Received: by mail-pj1-x102e.google.com with SMTP id cq1so1540862pjb.4; Tue, 12 Jan 2021 06:55:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6JkyBkYAckjgDlGoWxaUiUStT7GzBw8f+Vd8Us2poEQ=; b=RktSvR9thgQCq59D/Uxp3WROn6CZ09IZDh7WG2lSKjEV3i9I/BAk4tnmJeZ90WOKgw /GFtfnQCrerqS5rbQ6rdSdqy2LTAozypY2gkbPciDcyjsEa84NxhONdm52zVn1dl8RqD Ip+NtMLWXlIfREfCYTBzmieAN2HaBPaTK8j8USIi8ynS/eGfcIYhrQjKFnNBjaQIlVJD EnjjMWuv3OiUadcjoc9qZfFeXnjaoG0R5U9f2vNY7k+NCu2DCMv6Vt04ziKKAkNTE2UM P5p/2iGYq34w/7Lyv8U2AnLh0gfzQyWSNzl/Z68wusAmbOyZDhaEQ2/1eIpYAls38NmS F3iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6JkyBkYAckjgDlGoWxaUiUStT7GzBw8f+Vd8Us2poEQ=; b=KDwtLqZmkEpXAaoH6w+8wWlsaubkFI/jqHawo9IMBUffBvH3rTBUf2arOOkEM2wSaX i5fddN36504s8ovjqWpLRQVt2aE5SGblPKxlBno74D16gClML7RXsErqzL8v62G230u4 lXsZD4pVYRdjpGDgH6MBfAJz2PVbe0dSp8swYS6Eahp8cMHZgdE1O8tCPsJF5mLO14b9 wdLWAxontBigut0thchWJetIemQsj/BQluZ+aJjoJ9g8ydMGsDXZDRc95MJG9MXTLwe8 qmst+ViEGdmMoKiPidCY1NOTjHgIau9ouhUa5s2xO+OzJP+RkVmSQzhQrwcm9dswk+oW G+QA== X-Gm-Message-State: AOAM532bR0+qCeyxCwFXeWAGv/sdRun28h8ry2Si+v/c6Rf6WJ4MtOhC eJYfRRI4w+JnklxpLm0YCdI= X-Google-Smtp-Source: ABdhPJxouh1w1J4FT1OWPI+/KHOKk2bZNs9RKletchAolCTesmfVn/Bg80CPsdb+N/XJOXvBAOrWRA== X-Received: by 2002:a17:90a:de94:: with SMTP id n20mr5206727pjv.196.1610463340191; Tue, 12 Jan 2021 06:55:40 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:39 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 0/6] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Tue, 12 Jan 2021 22:55:20 +0800 Message-Id: <20210112145526.31095-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:44 -0000 From: Bin Meng This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is disabled - remove imx_spi_update_irq() in imx_spi_reset() - round up the tx burst length to be multiple of 8 - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() - round up the burst length to be multiple of 8 Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 46 +++++++++++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 13 deletions(-) -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:55:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5I-0007sL-4A for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5G-0007ov-6h; Tue, 12 Jan 2021 09:55:46 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:41068) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5E-0004jg-M9; Tue, 12 Jan 2021 09:55:45 -0500 Received: by mail-pl1-x631.google.com with SMTP id y8so1515580plp.8; Tue, 12 Jan 2021 06:55:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yiZYra9gqHUl+N2i47qt4AFi/fzPb5dHXFPbEQlB07k=; b=qpTNeDom9OndziOM8Iave2+BUhH8o3fvOOWa/Py2FermWKpLJ69KABqAVe//vZM3zQ izUHgLIWTZjqfAiSBm/hk7NtH+xfXHuqZfuXX8k4Ubc/9Frzb8tO5yNiP4gJnk77DKsG WGFfkjlwsfy+W+waFFaCA2Xme/Iy9XwPHQLUsXD0+p/4AdMs/4/nF+Im8EvagEgyDO1T IJFvun4fVSc4Jb/XNDC6PIofrGqQqthVFzWu+rX647cDxT4BBthpjSuUDfkHZFUtLfxq OHUpfVT4S95VU4LhRJm+3uxCphaasH/JlpBXJGcNwPO+gqgCwEU5Rcr0uK49fePk4m40 Iz4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yiZYra9gqHUl+N2i47qt4AFi/fzPb5dHXFPbEQlB07k=; b=asmidGtrslWyrb+SJX7ijSXrMStQtnobm68ZyadCbfa7rKffOKjyGatX7fZt1AWixt bYICDY6r65lDzLgFG7LOkQpMESecXJJUYvO0M3wVcvG8G0zQFl9YNnRYGo/p74niPyCx ot25xZi5iS9RgVAKQhnTwdXAoFrqwmwNkqUrfJngjysZBySDAvzLSSoNvDTV1cwV0t0Y B7HveEYW4BjlDL7YAN0wDwhF4+W0Ev9zTS9yW/WMbJQm5GipTPWLm5MJwStH0iq44hgs aFEWoahw+WGogK0et48z+MQjzMcNer6IC3AdYzvoRL3C9cpvDHsbFIC+kh2QgsWeKaZe 0SlA== X-Gm-Message-State: AOAM532E3FDj3vHlPtlk4ksHFKTfz1kmuUpvCw4d0ibfeFoqsEU377Yr DO/i9wQrYoU0NyF9LlvRu+k= X-Google-Smtp-Source: ABdhPJzm6TKiyUE3LbQbYwygNqbDcQPDHslCXq01UVmBRE0f9BdEk/PEle9pMSzc9ZUOhdrGTr7kXw== X-Received: by 2002:a17:90a:d48f:: with SMTP id s15mr5023862pju.137.1610463343194; Tue, 12 Jan 2021 06:55:43 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:42 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 1/6] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Tue, 12 Jan 2021 22:55:21 +0800 Message-Id: <20210112145526.31095-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:46 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:55:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5L-0007zc-AJ for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5J-0007va-Ch; Tue, 12 Jan 2021 09:55:49 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:46621) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5H-0004lk-Nh; Tue, 12 Jan 2021 09:55:49 -0500 Received: by mail-pl1-x62e.google.com with SMTP id v3so1502678plz.13; Tue, 12 Jan 2021 06:55:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OreTe0I+MY0/iL4Hv+5CUEoSzihVcjTr7+kKPCAh6xY=; b=M7PHrdJLxAwSCjCSdNgybgvJ7+OQkrW0HECrC0XDj0OCoR8Mjgc6sojeC2X+5jk9og ekFLG5X704D2fSEeUrurqmq/e7gf7bTDa8L4JLZaIV5Knbc7670yGjbOBLKkHjLLABwN PzwrGfWEdW25a+2sbZeURvkFF3/YwKJsJu+CR1OMIV6IUSdk1o98nKzJ1EKEDPpRtWLE ISJdSgkFwapQjQMRwg4HmfoVBo5+rh4PyVAvY3NPq5vqmsJJuLLZauu+xTvJMX1JHJLc zyYwJdYCBwk1pL4658vXCaWVOcGuk5hgkxgSj6O/n8SjCqeBVUuqXUTy6z64bXq4lyvG 9mOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OreTe0I+MY0/iL4Hv+5CUEoSzihVcjTr7+kKPCAh6xY=; b=rbvyWAxhsUEsWmANfKwA43AYdoTxLU/LcqyBHYZ/ImIb/ljtgtuaVw1nCVQRL7rGhb K8Xbi2I1Jhy1MqnBPTqey2pV3bO/h/TXDdXWT4TBrAAmtHlE7oKFbNokoeTuUysPS/fZ +UIM0ob9ozlBVQwbFLpU9c5is937lLrZInUi6ijZf9x0M8g3rniXEL5q3404jmoJ9kjx WB5kYXknIfHpAOYtYbtqPYb1sFrvYhK+Sn5uUtMtiPTZecTU0u9vaUORQZzYWd6BcR8R RkNFCJZTqWf/+jrC0bcP/Rr3zwdQT90fD57avE61sPdhQlnRI4jIQu+KhrBQjWqytJeZ Bt0w== X-Gm-Message-State: AOAM5333UwZF8iqfihl35xFJj8SS1zQBLSjP6KvL1nu0l0UdotGIukyB zcjtbXKD+6e6RbXzUs9sK3U= X-Google-Smtp-Source: ABdhPJwnCL1OVrfgqLtbi6DsZZ37TT5vV4SZap4qdDIOz39J2RYiCLg8ob30MhygIgf1a3Plxk1FrQ== X-Received: by 2002:a17:90b:1987:: with SMTP id mv7mr5109881pjb.66.1610463346029; Tue, 12 Jan 2021 06:55:46 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:45 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Tue, 12 Jan 2021 22:55:22 +0800 Message-Id: <20210112145526.31095-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:49 -0000 From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng --- Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..4d488b159a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); - imx_spi_update_irq(s); - s->burst_length = 0; } +static void imx_spi_soft_reset(IMXSPIState *s) +{ + imx_spi_reset(DEVICE(s)); + + imx_spi_update_irq(s); +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); + return; } -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:55:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5O-00087Y-Nc for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5M-00082n-IT; Tue, 12 Jan 2021 09:55:52 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:55618) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5K-0004mj-TA; Tue, 12 Jan 2021 09:55:52 -0500 Received: by mail-pj1-x1029.google.com with SMTP id p12so1718363pju.5; Tue, 12 Jan 2021 06:55:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+Mb3Gb3M8mku4NpiAEdzwbwGDJi9TG7kc1WGZbG7wr8=; b=AiA0hsFItQRCKYjjo3cYdF38rHmLaN9uBdkzN37njizg3WBWHJe11s5AgXum8IQkow GpQHNNpRuWXc3j8Wim0/7nEFNSAbkJl93AM4qWHk5wpLCjBmvPeI9wMcAfzkwSaE/4a0 IxiY2+pbIDqMPSHYmP4nsJ63jFz//E7Ewrq+q1WxCeh9OuvULevQRXc2KGmShvUObR33 22sOq8C61RKunQwdr7kmyEcWplqqXxwVJK83H1yGdZiUwk3i7Tez9aTgPRsNmXRfcKvk R4GVJffOcd65GlYGz6Kzuz5pr1V5jTEp/CF0P8pdu65kzexoe2GLY33DTBwMmrRxCgjj JVCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+Mb3Gb3M8mku4NpiAEdzwbwGDJi9TG7kc1WGZbG7wr8=; b=KU6AGGNzJ1ZEz0T82+iLclAMhVnFEuOfuqKpkNmqkvJf+zWUn9PTe9ONiLRrWIMkjt l+ZRRUV5GDwNpjwmL6tLpfl2mMg6iX9wCEgB4UUyFQlH04Jq5uXRZ8xKqD5FIFCBMfBk h7ldclEqaFAn5MDuGJdMh+E10USacsaRDC4ks90xb4s15N0GIvgIaPIiprQYv0AmxGIY or7ahmB/z0KNPgCTtLX7BSjufXn9F7606rb0awB2LXCkw6awWr3BKB24EsWNopGQ8cOR /uZ63/+q05yruDn0D/2QMNzC/VeOru2dG0c3Z3zbYB1U6+IsUgGwMUr6HKfPkYpJmDfN mCGw== X-Gm-Message-State: AOAM532g+dQOAoWIzuJawRVNKKypksE35iT1np4L3p6gJ1Gm1cuB5NWI Jom0PXojgOtIQ+/OpmZ0rsA= X-Google-Smtp-Source: ABdhPJxGw0hbeByYHLOMKZSRiBsuEz7yg10pbML/YRrDZbi5c0WJys+c4Oo0mP2pb0vT8BP73JAwZA== X-Received: by 2002:a17:902:a711:b029:da:f065:1315 with SMTP id w17-20020a170902a711b02900daf0651315mr5552623plq.36.1610463349100; Tue, 12 Jan 2021 06:55:49 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:48 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng Subject: [PATCH v5 3/6] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 12 Jan 2021 22:55:23 +0800 Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:52 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4d488b159a..880939f595 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -246,9 +246,15 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:55:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5R-0008E7-4n for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5P-00088i-21; Tue, 12 Jan 2021 09:55:55 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:40396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5N-0004nn-Hg; Tue, 12 Jan 2021 09:55:54 -0500 Received: by mail-pg1-x536.google.com with SMTP id 15so1606163pgx.7; Tue, 12 Jan 2021 06:55:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dUq4A654ZKmWVdTONfz5D26WNlkMJCt4bN5UkLrjKbg=; b=jSkw+6YEVqEEyeQ0O3nuUZ9msOUgFm3uzG1/Toks1srZfR2JWS8nJtKkekVfx1ypa1 ume9rwehUhm+WVDcUS49xti1N7yFAkDXPVpRSnHEA8KdPZsWzQejwujF3XuiQYxcWJQN Gil0Cv0KP+OG3O8OFJsA374WKvuFB2PQWTmeevfnJlSGr/4MwkongIKHbF13Jog5m9yn vazZIYNCeVvtdXN2jJl7/7JlGf9gPpogIb4x0WwSeVqJ/zlvd0rsTTzOE1yuPQPR88vm xkPdVQ/qP4l6natwU/zzPM4g2YXi4tOo+5Xg6w4mU1t5KuvVQnYTrq/SKGSdDgSSRriI nT4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dUq4A654ZKmWVdTONfz5D26WNlkMJCt4bN5UkLrjKbg=; b=ryHbSwhExyBsyqG8BCSwv32sy825R7o1vJRyFijRgM+yZHZiGeAfdT98DyfCIhoR9l oG2Ae/Gck0qvXcmasRoFSsqcWKMeLrWbNAunRRY5U/JRKC7YEdIUx9rUv+t8tuaR0js9 s+qV1qFy4tJuZnX1pj4ch6f+vDo9oGbWLnGlOR7Ntga8ThpQgtm7t5MU7VH1Yb4TbJad CIea9KiI0yca82X+R1b9qsftyOxSOoLn+OYvYBu7dKFJMXY3hfrER3OEE5z2OMFX8TEb y1ahSP76nc+G4OzIlwfiEQJtRd4aEqvEq6wJTCzYEXRFdokKJO/TScXKiPJj735GcfHr HqdA== X-Gm-Message-State: AOAM531bXMhYVWcxkDDAZVxGKgKNxTfcBEC8PctDPF5Bi9NWDuacz8ma A+AGWJntfBOq2O72iZ+HPm4= X-Google-Smtp-Source: ABdhPJyPWmCUc8IKTLSJeKabospcV+9a3w3RoWd34wr7VUHEIKxpWrcE7CyvHmKAaZYXnMaFX3XFPQ== X-Received: by 2002:aa7:947c:0:b029:1a5:dece:c07f with SMTP id t28-20020aa7947c0000b02901a5decec07fmr4843278pfq.47.1610463351971; Tue, 12 Jan 2021 06:55:51 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:51 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 4/6] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Tue, 12 Jan 2021 22:55:24 +0800 Message-Id: <20210112145526.31095-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:55 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng --- Changes in v5: - round up the burst length to be multiple of 8 Changes in v4: - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 880939f595..b7456de065 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + burst = ROUND_UP(burst, 8); + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length rounded up to %d; this may not work.\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:55:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5T-0008Kd-KZ for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:55:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5S-0008Gi-1s; Tue, 12 Jan 2021 09:55:58 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:35561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5Q-0004ov-CF; Tue, 12 Jan 2021 09:55:57 -0500 Received: by mail-pj1-x1035.google.com with SMTP id b5so1839183pjl.0; Tue, 12 Jan 2021 06:55:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1ox0W7mH3xZCkBWcpn4x9chA6DFhj8PXgPUX2LxAJf0=; b=gnZT+vHDI4/dYMVRewbDoBUr7VHRmvZNpjOS2NC8/2eKMVCxf5q/gcBVROfIdLcU8U w3bpsnSFPBD9vsQaQWHV8CI/zWyckaI1PSSLIjtoVzKWGY00rgKgyvQcGYOw7JFxfjcI UwfqAfIujXXpY4+LVphii+L8CvK7euys0kl/NiEIIcpHWiv0kjbY4b9gK0RP21m9XwFf Ktv/guUB1IrLyIO/H0wnyraUR78QGZTk4WtZvsqDmDHWquiOioNuJnLl178NSTyFZ9H8 SgAl6gMCrlHh1NdDJnqPHUQt5N9FjxAMKhmggTkcqKDGKgjO3IVRkJzTWdATTdOVOHgZ w8tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ox0W7mH3xZCkBWcpn4x9chA6DFhj8PXgPUX2LxAJf0=; b=JUWelC3cO3h0AB0pU48BVCubgnWGoAtn0ICj/FwcQAd6ZWVNQBw8aMWOAJgEZ5Ho71 Qv+XN94yr0zQnOwrdfXtPZAOtwxtUsrLBW5Had4NH3WIal7PoWV7B8q01qD6GFOz1ga5 vNvb3biT0mBPTU1CP8XWu9uqJ/i/1BJYyl0yIfgFRQxEFgXs/u4bgiTUcud79eazIBfD vPSQlG5cAVmRT5CcofMSS7DvadVZWW+9HA58FmNe6F85+4wj1HKrUNR9iau/hmUy0mm3 p+894K7ZJSsJD10K59wm6NNU3690Bm4Swy5oK8Y0jx1GAX0Op8zCNdAckl+GYbtGFdvF ursA== X-Gm-Message-State: AOAM533s6pkNXpZvsMgshMnVLDn0ZQMtnvjHW+4cV7V70iXbxgKahsKw cY+ETOR3wg6nIFzna5kBG1I= X-Google-Smtp-Source: ABdhPJz8LGvx9/AZWYLAbbf+lCuHXC31x+NTvAfO/faps0zncFMZlsOZefTrh80GBN9sTbyy4hKbow== X-Received: by 2002:a17:902:9a03:b029:dc:31af:8dc2 with SMTP id v3-20020a1709029a03b02900dc31af8dc2mr5097814plp.39.1610463354871; Tue, 12 Jan 2021 06:55:54 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:54 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 5/6] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Tue, 12 Jan 2021 22:55:25 +0800 Message-Id: <20210112145526.31095-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:55:58 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index b7456de065..5c2d818560 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -191,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.25.1 From MAILER-DAEMON Tue Jan 12 09:56:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzL5W-0008Ss-SE for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 09:56:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzL5V-0008O7-50; Tue, 12 Jan 2021 09:56:01 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:36867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzL5T-0004ps-Dk; Tue, 12 Jan 2021 09:56:00 -0500 Received: by mail-pg1-x52a.google.com with SMTP id z21so1611864pgj.4; Tue, 12 Jan 2021 06:55:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PdFwrdJNlHNeKN1ZR3AWcNlXHaUv5kTriH28HT1ONsE=; b=jzBdg7mmfA4x01sDM2alMcCvuxxVAACStuygbnWbFw+cSnyMTQpfltBRIlnl/D9KSO 1Exe58GomaponQIuV/1Dp/ag8g8/ykYsO1CWVVsm4FiIaQHOr2NofeJmtkr+Pr0aQxN8 pSRJVDB8cGX05CjovOpEdwDwBllZbr8guxcD+p1GvQ4e2vY1OQSpkbT+XUdK97+sxCnj V+ps3noiNU/tPhVLV7GcSPDtI9p3hxk8/kZRjsG6HoAaOew85XdBfj9C17SxbM8hIyss SgPmycYt2bLzqQaDpnW3bJAduMc2MRa5SO/ttN4aI0Tj1cg+xQKtuYff4pNOFAAxARUa 3AZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PdFwrdJNlHNeKN1ZR3AWcNlXHaUv5kTriH28HT1ONsE=; b=T4728BjMgnLK4kFHbqM3PU6AmsEqyhAu8lNxR818UCgdhqSiaemf9nd1cxiSC3BIAW r4ZHE3YtOVPO/gurcQcUUVWDSaJWkhsxy9s5+nYc4InqR+84aXwK9jtwVarYryJHuGms Qy9ICONhYjS8EoPCO1JInAjf2JrpdTe+tmV81BU+TxCy4YjiMpMMmKCyeJqLxdfDS6L1 KlSl97hwSvTEjPeA27up+YVsrlQLjLKupjw4nInDjVnhRtuR83o7lEZdXlAVTvCncw+d 178+1P6RmZJD5ZhgSEXU78EcgqtNw28fwkgvuTaDHgbRx88sBbyMCZTcfLmBTXQlly0p cuMA== X-Gm-Message-State: AOAM533Z+AhOCz9cjtqeDhp+kCTCTjJek6twtSDYWj4es+C9upVl5Gqh 5GHXel6Pr4s51fo6qIvTI08= X-Google-Smtp-Source: ABdhPJzjI9LVG8I8JlJqCPCsqMiEke6YLXhmSYUbBGY7/g9rj9P0hjBACEXjTHhla+uM4sgyQhVSuA== X-Received: by 2002:a62:14c4:0:b029:19d:d3f5:c304 with SMTP id 187-20020a6214c40000b029019dd3f5c304mr5069333pfu.55.1610463357711; Tue, 12 Jan 2021 06:55:57 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id l141sm3593938pfd.124.2021.01.12.06.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 06:55:57 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v5 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Tue, 12 Jan 2021 22:55:26 +0800 Message-Id: <20210112145526.31095-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112145526.31095-1-bmeng.cn@gmail.com> References: <20210112145526.31095-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 14:56:01 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 5c2d818560..bbbf6afce5 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -175,7 +175,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -196,7 +195,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -205,13 +204,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.25.1 From MAILER-DAEMON Tue Jan 12 10:06:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzLFt-0002aG-QW for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 10:06:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzLFp-0002ZQ-CQ; Tue, 12 Jan 2021 10:06:42 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]:43316) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzLFn-0008IN-9q; Tue, 12 Jan 2021 10:06:40 -0500 Received: by mail-ed1-x533.google.com with SMTP id by27so2434661edb.10; Tue, 12 Jan 2021 07:06:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ejGy+n6I7cO4B2hnJmdcOlqpJpKcpw9gc9h9k+fJcrw=; b=CAgnz/+SdneqLFgD+tF1yzXyEezGN+78V963GGmo0XON+Vbt4pbnYmyjT9badF+pV+ Jr/a0YOHvhBrp4kU4q0BgAVB5gPMJ+CiYIKS7OhGKiY31XwwpAaO2eb/m52SOBjoBCFa 7PFtV9MHAb3PviE79KfxfJLIAOJPjlS03z5UM9zeccKRTEZXK746x3NtzpFS/1HiyMY/ 8Ig08z/NNXz33YcELJY3Q4VNLpIU1AfnggvWa/JOgGV5XhBpCwPZLQKSRenaxGgA/IKM 2JUBjl+6di33zwDoV+bdxthwKkJjL725bi/JzUf9xViqgZYgK6f4PqT/oHayluPayGng fZyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ejGy+n6I7cO4B2hnJmdcOlqpJpKcpw9gc9h9k+fJcrw=; b=YQLVCI5ZNXGxc2JgWQvXnGsR0OPwfRY4zmbWN257puu8jghUi9EQrU5BENKuGvCcwR MJsn0nGiCpz30NE/6IuOLBrNq3PJEFzNJhUMxhFoBlaZrjCu0ejvDcxdGrTmXG2mvGGs vhl8GdZpnh0k4tDwEWI3mq8TbAP0fl8YeNlErm2zDK5Ose4Fl73LvYyj/SkY/QaBKTms qpTJsqrHYT37ZLn3AyYwo7FJrOz6TVNSgJLUgoouCbagxNOjfc2Tq4O30T7W7+HCl0ag i3EZ1gf+j1Y3HhFxQngyoEEVdKSx0NpVNRGfSTPZngKnYQKQVQs6cfHnUhh8NC0j7RBi 7Q3A== X-Gm-Message-State: AOAM533jCN0AwjogePu5iG2Ov4yVB4YcImTbgxXl6Evzoh7ZKBioFyRn XG62DUcCXvVTLMeLGLJgrak= X-Google-Smtp-Source: ABdhPJzH6I+GyiTQhodghRNaK/z2c9sZEo0KDySnLosjIEXOy2QqEC/5rhG43OAMW7HtgzAwtBKZ8A== X-Received: by 2002:a05:6402:2553:: with SMTP id l19mr3693672edb.326.1610463997445; Tue, 12 Jan 2021 07:06:37 -0800 (PST) Received: from [192.168.1.36] (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id q17sm1547221edr.83.2021.01.12.07.06.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 07:06:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v4 2/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng , Peter Maydell Cc: Bin Meng , QEMU Developers , qemu-arm , Alistair Francis , Jean-Christophe Dubois References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-3-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 12 Jan 2021 16:06:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 15:06:42 -0000 Hi Ben, On 1/12/21 2:22 PM, Bin Meng wrote: > On Tue, Jan 12, 2021 at 9:19 PM Peter Maydell wrote: >> >> On Tue, 12 Jan 2021 at 12:54, Bin Meng wrote: >>> >>> On Tue, Jan 12, 2021 at 6:49 PM Peter Maydell wrote: >>>> >>>> On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: >>>>> >>>>> From: Bin Meng >>>>> >>>>> Usually the approach is that the device on the other end of the line >>>>> is going to reset its state anyway, so there's no need to actively >>>>> signal an irq line change during the reset hook. >>>>> >>>>> Move imx_spi_update_irq() out of imx_spi_reset(), to a new function >>>>> imx_spi_hard_reset() that is called when the controller is disabled. >>>>> >>>>> Signed-off-by: Bin Meng >>>>> >>>>> --- >>>>> >>>>> Changes in v4: >>>>> - adujst the patch 2,3 order >>>>> - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion >>>>> >>>>> Changes in v3: >>>>> - new patch: remove imx_spi_update_irq() in imx_spi_reset() >>>>> >>>>> hw/ssi/imx_spi.c | 14 ++++++++++---- >>>>> 1 file changed, 10 insertions(+), 4 deletions(-) >>>>> >>>>> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >>>>> index e605049a21..2c4c5ec1b8 100644 >>>>> --- a/hw/ssi/imx_spi.c >>>>> +++ b/hw/ssi/imx_spi.c >>>>> @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) >>>>> imx_spi_rxfifo_reset(s); >>>>> imx_spi_txfifo_reset(s); >>>>> >>>>> - imx_spi_update_irq(s); >>>>> - >>>>> s->burst_length = 0; >>>>> } >>>>> >>>>> +static void imx_spi_hard_reset(IMXSPIState *s) >>>>> +{ >>>>> + imx_spi_reset(DEVICE(s)); >>>>> + >>>>> + imx_spi_update_irq(s); >>>>> +} >>>>> + >>>>> static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) >>>>> { >>>>> uint32_t value = 0; >>>>> @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, >>>>> s->regs[ECSPI_CONREG] = value; >>>>> >>>>> if (!imx_spi_is_enabled(s)) { >>>>> - /* device is disabled, so this is a reset */ >>>>> - imx_spi_reset(DEVICE(s)); >>>>> + /* device is disabled, so this is a hard reset */ >>>>> + imx_spi_hard_reset(s); >>>>> + >>>>> return; >>>>> } >>>> >>>> The function of the code is correct, but you seem to have the function >>>> naming backwards here. Generally: >>>> * soft reset == the reset triggered by the register write >>>> * hard reset == power-on reset == the dc->reset function >>>> >>>> I think this is what Philippe was trying to say. >>> >>> Philippe said: "Hmm usually hard reset include soft reset." >> >> True in hardware, but for QEMU there are some things we don't >> want to do in what we would call a hard or power-on reset. Sorry for the confusion. I guess you understood me well, but I was wrong. Anyhow I'll try to sort this discussion out with my English teacher so the next time such confusion doesn't happen again. Thanks, Phil. > OK, will revert to use imx_spi_soft_reset(). > >>> Since we are moving imx_spi_update_irq() out of imx_spi_reset() to a >>> new function called imx_spi_soft_reset() (what I did in v3), that >>> confused him (and I felt the same thing), so I renamed >>> imx_spi_soft_reset() to imx_spi_hard_reset() in v4.. > > Regards, > Bin > From MAILER-DAEMON Tue Jan 12 10:36:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzLiD-0002T9-CC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 10:36:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzLi7-0002Ox-HN for qemu-arm@nongnu.org; Tue, 12 Jan 2021 10:35:55 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:48888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzLi3-0001pI-Ui for qemu-arm@nongnu.org; Tue, 12 Jan 2021 10:35:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610465750; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=shRKZOsGBDKnF5+mPp6qoYOYQbusDRRVbTBRQ6QZmeA=; b=CIo+02JG7XXHk4cxxIGtf8o5x2kxb/OJHemITt8Jadg6ggxnDiIQeGraqriHpSzjFCFEGS IBv7zc6bEiPr9aTX3OusXAZYpgxKLRl9IAnAbvPq/z1tnTBXRWu1VNesjyYF+EXXeXx4v8 a0jc4K11lcm25Z5DP0ULjaHTZPrjUM4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-266-d3jkmsInPWaTYCenk9e2qQ-1; Tue, 12 Jan 2021 10:35:47 -0500 X-MC-Unique: d3jkmsInPWaTYCenk9e2qQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 461EC1012EA9; Tue, 12 Jan 2021 15:35:46 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-115-10.rdu2.redhat.com [10.10.115.10]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D81275C257; Tue, 12 Jan 2021 15:35:44 +0000 (UTC) Date: Tue, 12 Jan 2021 10:35:42 -0500 From: Andrew Jones To: Maxim Uvarov Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, f4bug@amsat.org, Jose.Marinho@arm.com, tf-a@lists.trustedfirmware.org Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down Message-ID: <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> MIME-Version: 1.0 In-Reply-To: <20210112143058.12159-3-maxim.uvarov@linaro.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 15:35:55 -0000 On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). Connect it > with gpio-pwr driver. > > Signed-off-by: Maxim Uvarov > --- > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 40 ++++++++++++++++++++++++++++++++++++++++ > include/hw/arm/virt.h | 3 +++ > 3 files changed, 44 insertions(+) > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 0a242e4c5d..13cc42dcc8 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -17,6 +17,7 @@ config ARM_VIRT > select PL011 # UART > select PL031 # RTC > select PL061 # GPIO > + select GPIO_PWR > select PLATFORM_BUS > select SMBIOS > select VIRTIO_MMIO > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 96985917d3..19605390c2 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] = { > [VIRT_RTC] = { 0x09010000, 0x00001000 }, > [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, > [VIRT_GPIO] = { 0x09030000, 0x00001000 }, > + [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, Does secure world require 4K pages? > [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, > [VIRT_SMMU] = { 0x09050000, 0x00020000 }, > [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, > @@ -864,6 +865,32 @@ static void create_gpio(const VirtMachineState *vms) > g_free(nodename); > } > > +#define ATF_GPIO_POWEROFF 3 > +#define ATF_GPIO_REBOOT 4 > + > +static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) > +{ > + DeviceState *gpio_pwr_dev; > + SysBusDevice *s; > + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; > + DeviceState *pl061_dev; > + > + /* Secure pl061 */ > + pl061_dev = qdev_new("pl061"); > + s = SYS_BUS_DEVICE(pl061_dev); > + sysbus_realize_and_unref(s, &error_fatal); > + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); > + > + /* gpio-pwr */ > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); > + > + /* connect secure pl061 to gpio-pwr */ > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); I don't know anything about secure world, but it seems odd that we don't need to add anything to the DTB. > +} > + > static void create_virtio_devices(const VirtMachineState *vms) > { > int i; > @@ -1993,6 +2020,10 @@ static void machvirt_init(MachineState *machine) > create_gpio(vms); > } > > + if (vms->secure && vms->secure_gpio) { > + create_gpio_secure(vms, secure_sysmem); > + } > + > /* connect powerdown request */ > vms->powerdown_notifier.notify = virt_powerdown_req; > qemu_register_powerdown_notifier(&vms->powerdown_notifier); > @@ -2567,6 +2598,12 @@ static void virt_instance_init(Object *obj) > vms->its = true; > } > > + if (vmc->no_secure_gpio) { > + vms->secure_gpio = false; > + } else { > + vms->secure_gpio = true; > + } nit: vms->secure_gpio = !vmc->no_secure_gpio But do we even need vms->secure_gpio? Why not just do if (vms->secure && !vmc->no_secure_gpio) { create_gpio_secure(vms, secure_sysmem); } in machvirt_init() ? > + > /* Default disallows iommu instantiation */ > vms->iommu = VIRT_IOMMU_NONE; > > @@ -2608,8 +2645,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) > > static void virt_machine_5_2_options(MachineClass *mc) > { > + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); > + > virt_machine_6_0_options(mc); > compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); > + vmc->no_secure_gpio = true; > } > DEFINE_VIRT_MACHINE(5, 2) > > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index abf54fab49..a140e75444 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -81,6 +81,7 @@ enum { > VIRT_GPIO, > VIRT_SECURE_UART, > VIRT_SECURE_MEM, > + VIRT_SECURE_GPIO, > VIRT_PCDIMM_ACPI, > VIRT_ACPI_GED, > VIRT_NVDIMM_ACPI, > @@ -127,6 +128,7 @@ struct VirtMachineClass { > bool kvm_no_adjvtime; > bool no_kvm_steal_time; > bool acpi_expose_flash; > + bool no_secure_gpio; > }; > > struct VirtMachineState { > @@ -136,6 +138,7 @@ struct VirtMachineState { > FWCfgState *fw_cfg; > PFlashCFI01 *flash[2]; > bool secure; > + bool secure_gpio; > bool highmem; > bool highmem_ecam; > bool its; > -- > 2.17.1 > > Thanks, drew From MAILER-DAEMON Tue Jan 12 11:00:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzM64-0005qS-O1 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 11:00:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzM63-0005oq-AJ for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:00:39 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:46330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzM60-0002AY-Et for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:00:39 -0500 Received: by mail-ej1-x62d.google.com with SMTP id t16so4178374ejf.13 for ; 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Tue, 12 Jan 2021 08:00:34 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> In-Reply-To: <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> From: Peter Maydell Date: Tue, 12 Jan 2021 16:00:23 +0000 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Andrew Jones Cc: Maxim Uvarov , qemu-arm , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jose.Marinho@arm.com, tf-a@lists.trustedfirmware.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 16:00:39 -0000 On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote: > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > > the secure world (Arm Trusted Firmware). Connect it > > with gpio-pwr driver. > > + /* connect secure pl061 to gpio-pwr */ > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > I don't know anything about secure world, but it seems odd that we don't > need to add anything to the DTB. We should be adding something to the DTB, yes. Look at how create_uart() does this -- you set the 'status' and 'secure-status' properties to indicate that the device is secure-world only. > > + if (vmc->no_secure_gpio) { > > + vms->secure_gpio = false; > > + } else { > > + vms->secure_gpio = true; > > + } > > nit: vms->secure_gpio = !vmc->no_secure_gpio > > But do we even need vms->secure_gpio? Why not just do > > if (vms->secure && !vmc->no_secure_gpio) { > create_gpio_secure(vms, secure_sysmem); > } > > in machvirt_init() ? We're just following the same pattern as vmc->no_its/vms->its, aren't we ? thanks -- PMM From MAILER-DAEMON Tue Jan 12 11:25:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzMUJ-0004AE-CT for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 11:25:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMUF-00048x-Dv for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:25:39 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:58588) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzMUB-0003Po-Fd for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:25:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610468733; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wyQXJM0qz40sCwA/MHJ4EUEzKOyoFh5FbZaw7u1eSr8=; b=hS5jhz7nSHQvSc+/KzX9/Rr5YJkz5O16Gc6epARgmTR5onD8dIvA7dKvF9x+rbCRS0th/6 goMu2RoyUn9AzNJZPyCNH3nqXRzaRoA3oyG2a4zJ4loDEYzPFPwAIXYycKmiUmCBCTm8jc JBrVJ8eb7OtBsT7HN6As/PdwmCBUhik= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-388-3PDR9FtePtW-FgOh8lV1oQ-1; Tue, 12 Jan 2021 11:25:32 -0500 X-MC-Unique: 3PDR9FtePtW-FgOh8lV1oQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A667A801E70; Tue, 12 Jan 2021 16:25:30 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-115-10.rdu2.redhat.com [10.10.115.10]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C801219716; Tue, 12 Jan 2021 16:25:28 +0000 (UTC) Date: Tue, 12 Jan 2021 11:25:26 -0500 From: Andrew Jones To: Peter Maydell Cc: Maxim Uvarov , Jose.Marinho@arm.com, QEMU Developers , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down Message-ID: <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 16:25:39 -0000 On Tue, Jan 12, 2021 at 04:00:23PM +0000, Peter Maydell wrote: > On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote: > > > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > > > Add secure pl061 for reset/power down machine from > > > the secure world (Arm Trusted Firmware). Connect it > > > with gpio-pwr driver. > > > > + /* connect secure pl061 to gpio-pwr */ > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > > > I don't know anything about secure world, but it seems odd that we don't > > need to add anything to the DTB. > > We should be adding something to the DTB, yes. Look at > how create_uart() does this -- you set the 'status' and > 'secure-status' properties to indicate that the device is > secure-world only. > > > > > > + if (vmc->no_secure_gpio) { > > > + vms->secure_gpio = false; > > > + } else { > > > + vms->secure_gpio = true; > > > + } > > > > nit: vms->secure_gpio = !vmc->no_secure_gpio > > > > But do we even need vms->secure_gpio? Why not just do > > > > if (vms->secure && !vmc->no_secure_gpio) { > > create_gpio_secure(vms, secure_sysmem); > > } > > > > in machvirt_init() ? > > We're just following the same pattern as vmc->no_its/vms->its, > aren't we ? > 'its' is a property that can be changed on the command line. Unless we want to be able to manage 'secure-gpio' separately from 'secure', then I think vmc->its plus 'secure' should be sufficient. We don't always need both vmc and vms state, see 'no_ged'. Thanks, drew From MAILER-DAEMON Tue Jan 12 11:28:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzMXS-0005fu-56 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 11:28:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzMXQ-0005eG-Ji for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:28:56 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:27640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzMXP-0004ta-2z for qemu-arm@nongnu.org; Tue, 12 Jan 2021 11:28:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610468933; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=o9GpoQowO6JHIejzAlGKrwY/elTVTuK4f+4ngW7ZPG4=; b=C+YwM6NU7TVdP3j0m5MN58RCZMGeptvWdt7R1YO8uM3SuLsFS9nd28iAVJptgNhxBJHAXK lbtfeFHFas+T8rZceVlsThQsFnweS0JXE3W8uo7/55qc/ZFoBleEwSyRmDfkDT80n/UarA pCQNp6Jes51+BG8fJN5QgkxvZlOvEs0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-351-GH3nz7f1NsS6rX2b6yHiVA-1; Tue, 12 Jan 2021 11:28:51 -0500 X-MC-Unique: GH3nz7f1NsS6rX2b6yHiVA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4078A801F9A; Tue, 12 Jan 2021 16:28:50 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-115-10.rdu2.redhat.com [10.10.115.10]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3838260862; Tue, 12 Jan 2021 16:28:49 +0000 (UTC) Date: Tue, 12 Jan 2021 11:28:47 -0500 From: Andrew Jones To: Peter Maydell Cc: Maxim Uvarov , Jose.Marinho@arm.com, QEMU Developers , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down Message-ID: <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 16:28:56 -0000 On Tue, Jan 12, 2021 at 11:25:30AM -0500, Andrew Jones wrote: > On Tue, Jan 12, 2021 at 04:00:23PM +0000, Peter Maydell wrote: > > On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote: > > > > > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > > > > Add secure pl061 for reset/power down machine from > > > > the secure world (Arm Trusted Firmware). Connect it > > > > with gpio-pwr driver. > > > > > > + /* connect secure pl061 to gpio-pwr */ > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > > > > > I don't know anything about secure world, but it seems odd that we don't > > > need to add anything to the DTB. > > > > We should be adding something to the DTB, yes. Look at > > how create_uart() does this -- you set the 'status' and > > 'secure-status' properties to indicate that the device is > > secure-world only. > > > > > > > > > > + if (vmc->no_secure_gpio) { > > > > + vms->secure_gpio = false; > > > > + } else { > > > > + vms->secure_gpio = true; > > > > + } > > > > > > nit: vms->secure_gpio = !vmc->no_secure_gpio > > > > > > But do we even need vms->secure_gpio? Why not just do > > > > > > if (vms->secure && !vmc->no_secure_gpio) { > > > create_gpio_secure(vms, secure_sysmem); > > > } > > > > > > in machvirt_init() ? > > > > We're just following the same pattern as vmc->no_its/vms->its, > > aren't we ? > > > > 'its' is a property that can be changed on the command line. Unless > we want to be able to manage 'secure-gpio' separately from 'secure', > then I think vmc->its plus 'secure' should be sufficient. We don't I meant to write 'vmc->no_secure_gpio and vms->secure' here. Thanks, drew > always need both vmc and vms state, see 'no_ged'. > > Thanks, > drew From MAILER-DAEMON Tue Jan 12 12:56:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzNu6-0001Aa-TC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 12:56:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzNu4-00016b-OX for qemu-arm@nongnu.org; Tue, 12 Jan 2021 12:56:24 -0500 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]:34746) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzNu2-0002p3-Hy for qemu-arm@nongnu.org; Tue, 12 Jan 2021 12:56:24 -0500 Received: by mail-lf1-x130.google.com with SMTP id o19so4721682lfo.1 for ; Tue, 12 Jan 2021 09:56:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KO6qDQIbEVkoF4M7Euju23RL8XH28UtY0vMBbtDUReM=; b=hCmYdERKuPZ7R/+6QpEFUdRydSaiWz5cEUp4TIG6b6oovl0vXZF8K4CeXaNNGb2DwG cSEqqT191373odWbZhVZp72WOL6yxg9bXKssFc3pquGy1cgFyxSGByfyK0lHFsE+Oglg GMtLtdSjh/fXOXgUnXTKFr5AECdydygoW9gHF/+YZx8NZ9c8/xgs/XsSzcRjINoezsh1 5ueadS44s+KCiMSanreOfIrPTyr40dn53pO28US67neCP2WvrDbYsmktY1b76GgT3mpY i9jVgbIn4G8R3by+7ZwlKiJg8NfX8YiYkrpRQA8J+F6emNqxWHmTnbLhPpK5TaWy8krR DnoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KO6qDQIbEVkoF4M7Euju23RL8XH28UtY0vMBbtDUReM=; b=Aodqlo0vrktu8NEjGowhsXblT4scKRs8x2SzmDrhA/dPQV5ym3GhjlRilrs4+W7poM S7E/iIteYzchqeGDEmBpFH0GnHRqg7Y5aEAzAxqSWDof/7kB3X0GyLLoAzdrPtNLJctH VbxukyuDlM0rvtA1NHKy/NLKYzFI0Sc0fdiOMQJ2HAwnm0CMl6XUO3yJb8qTR41rhjUT 3vhuCn92dQvux3dYCPrHrnC+jg/eFRB4t0Rj/FqnpN6pQpXr+C+mtxFPluZrapY0be2g WKL0nXxlxNfHTvBTyF7XUyY7pmZj+yCX7KpcRtIBCYYTyNRXUHT8cBxJC+90ufFl7HYb B8ag== X-Gm-Message-State: AOAM530yD0nzY9JHxIo8IY0KU6szmNrAcmHrqlj5F/jxG+qf1grC/YjC Dx8MXHPUO2lUndamTs+RyI78cobtggfhvih2r1hRsg== X-Google-Smtp-Source: ABdhPJykji0NDh7S1S1HcRqwfKA+FoIidauZvzWV8HkRzpwMiuekXGL0LBcY+fkjil7gnq+P7ebQfuV6VLOt8XSRirg= X-Received: by 2002:ac2:5689:: with SMTP id 9mr45549lfr.175.1610474178824; Tue, 12 Jan 2021 09:56:18 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-2-maxim.uvarov@linaro.org> In-Reply-To: <20210112143058.12159-2-maxim.uvarov@linaro.org> From: Hao Wu Date: Tue, 12 Jan 2021 09:56:05 -0800 Message-ID: Subject: Re: [PATCHv4 1/2] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , Peter Maydell , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jose.Marinho@arm.com, tf-a@lists.trustedfirmware.org Content-Type: multipart/alternative; boundary="00000000000059a4a205b8b7bd8f" Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x130.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 17:56:25 -0000 --00000000000059a4a205b8b7bd8f Content-Type: text/plain; charset="UTF-8" On Tue, Jan 12, 2021 at 6:36 AM Maxim Uvarov wrote: > Implement gpio-pwr driver to allow reboot and poweroff machine. > This is simple driver with just 2 gpios lines. Current use case > is to reboot and poweroff virt machine in secure mode. Secure > pl066 gpio chip is needed for that. > > Signed-off-by: Maxim Uvarov > Reviewed-by: Hao Wu > --- > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > 3 files changed, 74 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c > > diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig > index b6fdaa2586..f0e7405f6e 100644 > --- a/hw/gpio/Kconfig > +++ b/hw/gpio/Kconfig > @@ -8,5 +8,8 @@ config PL061 > config GPIO_KEY > bool > > +config GPIO_PWR > + bool > + > config SIFIVE_GPIO > bool > diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c > new file mode 100644 > index 0000000000..8ed8d5d24f > --- /dev/null > +++ b/hw/gpio/gpio_pwr.c > @@ -0,0 +1,70 @@ > +/* > + * GPIO qemu power controller > + * > + * Copyright (c) 2020 Linaro Limited > + * > + * Author: Maxim Uvarov > + * > + * Virtual gpio driver which can be used on top of pl061 > + * to reboot and shutdown qemu virtual machine. One of use > + * case is gpio driver for secure world application (ARM > + * Trusted Firmware.). > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or > later. > + * See the COPYING file in the top-level directory. > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +/* > + * QEMU interface: > + * two named input GPIO lines: > + * 'reset' : when asserted, trigger system reset > + * 'shutdown' : when asserted, trigger system shutdown > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "sysemu/runstate.h" > + > +#define TYPE_GPIOPWR "gpio-pwr" > +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) > + > +struct GPIO_PWR_State { > + SysBusDevice parent_obj; > +}; > + > +static void gpio_pwr_reset(void *opaque, int n, int level) > +{ > + if (!level) { > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); > + } > +} > + > +static void gpio_pwr_shutdown(void *opaque, int n, int level) > +{ > + if (!level) { > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); > + } > +} > + > +static void gpio_pwr_init(Object *obj) > +{ > + DeviceState *dev = DEVICE(obj); > + > + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); > + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); > +} > + > +static const TypeInfo gpio_pwr_info = { > + .name = TYPE_GPIOPWR, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(GPIO_PWR_State), > + .instance_init = gpio_pwr_init, > +}; > + > +static void gpio_pwr_register_types(void) > +{ > + type_register_static(&gpio_pwr_info); > +} > + > +type_init(gpio_pwr_register_types) > diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build > index 5c0a7d7b95..79568f00ce 100644 > --- a/hw/gpio/meson.build > +++ b/hw/gpio/meson.build > @@ -1,5 +1,6 @@ > softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) > softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) > +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) > softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) > softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) > softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) > -- > 2.17.1 > > > --00000000000059a4a205b8b7bd8f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Jan 12, 2021 at 6:36 AM Maxim= Uvarov <maxim.uvarov@linaro.= org> wrote:
Implement gpio-pwr driver to allow reboot and poweroff machine.
This is simple driver with just 2 gpios lines. Current use case
is to reboot and poweroff virt machine in secure mode. Secure
pl066 gpio chip is needed for that.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Revi= ewed-by: Hao Wu <wuhaotsh@google.= com>=C2=A0
---
=C2=A0hw/gpio/Kconfig=C2=A0 =C2=A0 =C2=A0|=C2=A0 3 ++
=C2=A0hw/gpio/gpio_pwr.c=C2=A0 | 70 +++++++++++++++++++++++++++++++++++++++= ++++++
=C2=A0hw/gpio/meson.build |=C2=A0 1 +
=C2=A03 files changed, 74 insertions(+)
=C2=A0create mode 100644 hw/gpio/gpio_pwr.c

diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index b6fdaa2586..f0e7405f6e 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -8,5 +8,8 @@ config PL061
=C2=A0config GPIO_KEY
=C2=A0 =C2=A0 =C2=A0bool

+config GPIO_PWR
+=C2=A0 =C2=A0 bool
+
=C2=A0config SIFIVE_GPIO
=C2=A0 =C2=A0 =C2=A0bool
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
new file mode 100644
index 0000000000..8ed8d5d24f
--- /dev/null
+++ b/hw/gpio/gpio_pwr.c
@@ -0,0 +1,70 @@
+/*
+ * GPIO qemu power controller
+ *
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * Author: Maxim Uvarov <maxim.uvarov@linaro.org>
+ *
+ * Virtual gpio driver which can be used on top of pl061
+ * to reboot and shutdown qemu virtual machine. One of use
+ * case is gpio driver for secure world application (ARM
+ * Trusted Firmware.).
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or late= r.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * QEMU interface:
+ * two named input GPIO lines:
+ *=C2=A0 =C2=A0'reset' : when asserted, trigger system reset
+ *=C2=A0 =C2=A0'shutdown' : when asserted, trigger system shutdown=
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "sysemu/runstate.h"
+
+#define TYPE_GPIOPWR "gpio-pwr"
+OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR)
+
+struct GPIO_PWR_State {
+=C2=A0 =C2=A0 SysBusDevice parent_obj;
+};
+
+static void gpio_pwr_reset(void *opaque, int n, int level)
+{
+=C2=A0 =C2=A0 if (!level) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST= _RESET);
+=C2=A0 =C2=A0 }
+}
+
+static void gpio_pwr_shutdown(void *opaque, int n, int level)
+{
+=C2=A0 =C2=A0 if (!level) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST= _SHUTDOWN);
+=C2=A0 =C2=A0 }
+}
+
+static void gpio_pwr_init(Object *obj)
+{
+=C2=A0 =C2=A0 DeviceState *dev =3D DEVICE(obj);
+
+=C2=A0 =C2=A0 qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset&quo= t;, 1);
+=C2=A0 =C2=A0 qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdo= wn", 1);
+}
+
+static const TypeInfo gpio_pwr_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_GPIOPWR, +=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEVICE,<= br> +=C2=A0 =C2=A0 .instance_size =3D sizeof(GPIO_PWR_State),
+=C2=A0 =C2=A0 .instance_init =3D gpio_pwr_init,
+};
+
+static void gpio_pwr_register_types(void)
+{
+=C2=A0 =C2=A0 type_register_static(&gpio_pwr_info);
+}
+
+type_init(gpio_pwr_register_types)
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 5c0a7d7b95..79568f00ce 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -1,5 +1,6 @@
=C2=A0softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8x= xx.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('g= pio_key.c'))
+softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_p= wr.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('ma= x7310.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl06= 1.c'))
=C2=A0softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_= gpio.c'))
--
2.17.1


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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id d8sm1822878edm.75.2021.01.12.10.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Tue, 12 Jan 2021 19:35:18 +0100 Message-Id: <20210112183529.2011863-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:35:36 -0000 Hi,=0D =0D As it is sometimes harder for me to express myself in plain=0D English, I found it easier to write the patches I was thinking=0D about. I know this doesn't scale.=0D =0D So this is how I understand the ecSPI reset works, after=0D looking at the IMX6DQRM.pdf datasheet.=0D =0D This is a respin of Ben's v5 series [*].=0D Tagged RFC because I have not tested it :)=0D =0D Sometimes changing device reset to better match hardware gives=0D trouble when using '-kernel ...' because there is no bootloader=0D setting the device in the state Linux expects it.=0D =0D Copy of Ben's v5 cover:=0D =0D This series fixes a bunch of bugs in current implementation of the imx=0D spi controller, including the following issues:=0D =0D - chip select signal was not lower down when spi controller is disabled=0D - remove imx_spi_update_irq() in imx_spi_reset()=0D - round up the tx burst length to be multiple of 8=0D - transfer incorrect data when the burst length is larger than 32 bit=0D - spi controller tx and rx fifo endianness is incorrect=0D =0D [*] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg02333.html=0D =0D Diff with Ben's v5:=0D =0D Key:=0D [----] : patches are identical=0D [####] : number of functional differences between upstream/downstream patch= =0D [down] : patch is downstream-only=0D The flags [FC] indicate (F)unctional and (C)ontextual differences, respecti= ve=3D=0D ly=0D =0D 001/11:[----] [--] 'hw/ssi: imx_spi: Use a macro for number of chip selects= s=3D=0D upported'=0D 002/11:[down] 'hw/ssi: imx_spi: Remove pointless variable initialization'=0D 003/11:[down] 'hw/ssi: imx_spi: Convert some debug printf()s to trace event= s'=0D 004/11:[down] 'hw/ssi: imx_spi: Reduce 'change_mask' variable scope'=0D 005/11:[down] 'hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG regis= te=3D=0D r value'=0D 006/11:[down] 'hw/ssi: imx_spi: Rework imx_spi_read() to handle block disab= le=3D=0D d'=0D 007/11:[down] 'hw/ssi: imx_spi: Rework imx_spi_write() to handle block disa= bl=3D=0D ed'=0D 008/11:[0004] [FC] 'hw/ssi: imx_spi: Disable chip selects when controller i= s =3D=0D disabled'=0D 009/11:[----] [--] 'hw/ssi: imx_spi: Round up the burst length to be multip= le=3D=0D of 8'=0D 010/11:[----] [--] 'hw/ssi: imx_spi: Correct the burst length > 32 bit tran= sf=3D=0D er logic'=0D 011/11:[----] [--] 'hw/ssi: imx_spi: Correct tx and rx fifo endianness'=0D =0D Bin Meng (4):=0D hw/ssi: imx_spi: Use a macro for number of chip selects supported=0D hw/ssi: imx_spi: Round up the burst length to be multiple of 8=0D hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic=0D hw/ssi: imx_spi: Correct tx and rx fifo endianness=0D =0D Philippe Mathieu-Daud=3DC3=3DA9 (6):=0D hw/ssi: imx_spi: Remove pointless variable initialization=0D hw/ssi: imx_spi: Convert some debug printf()s to trace events=0D hw/ssi: imx_spi: Reduce 'change_mask' variable scope=0D hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value=0D hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled=0D hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled=0D =0D Xuzhou Cheng (1):=0D hw/ssi: imx_spi: Disable chip selects when controller is disabled=0D =0D include/hw/ssi/imx_spi.h | 5 +-=0D hw/ssi/imx_spi.c | 147 +++++++++++++++++++++++----------------=0D hw/ssi/trace-events | 7 ++=0D 3 files changed, 97 insertions(+), 62 deletions(-)=0D =0D --=3D20=0D 2.26.2=0D =0D From MAILER-DAEMON Tue Jan 12 13:35:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWG-0000xM-D6 for mharc-qemu-arm@gnu.org; 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[83.57.173.190]) by smtp.gmail.com with ESMTPSA id w17sm839127ejk.124.2021.01.12.10.35.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Tue, 12 Jan 2021 19:35:19 +0100 Message-Id: <20210112183529.2011863-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:35:48 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-2-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f3643..eeaf49bbac3 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454e..e605049a213 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:35:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWJ-00011l-Ls for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:35:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWH-0000y5-78; Tue, 12 Jan 2021 13:35:53 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:44378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWE-0007F9-Ew; Tue, 12 Jan 2021 13:35:52 -0500 Received: by mail-ej1-x633.google.com with SMTP id w1so4885077ejf.11; Tue, 12 Jan 2021 10:35:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZanZiJ3tTZSMBujs+F1bLNbZeY/v2F63RmtFKqnRXj4=; b=dUoqNviw/pjbxVL7TjynR6A/+y579dM8g8u+tMtPz5fQKSBztKWEBI65tCRom+hNZg oijQ3NMQuMtbqnWixlyHuKiXVl7ctkHdWR3mkl4limigjVmNPQ1dP+o+vCm4AINfqTFM OwoYnNBXYUKlO+HrMvdwAjHpZz1Elkn8zMkJ6WAWlEGb7xdQFaNSgC7Yj8fbGVxxnnl1 TEc9ZK4FVs8xRxYBHwAfRR1q3CFBWXKrDDJzdfKJ/2lQjsewJ9pha7GJi43E94CnBcyx ZChaVjTEoUy0Ujb/AcUHZlQS/vcw78KtaeViYaaO4Nyi1xYxK+L4wjGlks+Gns47KNo+ nbNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZanZiJ3tTZSMBujs+F1bLNbZeY/v2F63RmtFKqnRXj4=; b=bme45xCW6FJFlbaYULaw22IOeNMRAkfNXMdYJs30kpnp/KykUCt/5laXMypZTUdKk+ o3VrPTHAo2ZJMxQbVllkO6yUYRVhIWoEzbeqemMK/zbjJXm7rP7RtuGnDIcgF7Y16T0t 4/SzBxgih68HR46yTJ8HPqwop5abH7Ua7fnMbaNN0Te3ncoBhCk17SackLZr6SRuaVwe SIn0PxnJ+zqyMryYcOYPuMsfraKYfvfOJAcb3oM4Hd2wepxvSA0IrMnkSgcV11C/T6Xy voHOrBPPgi8WY1yBxvqWIJWPdj6CEuj9EUHbzsY3B4NVZ/RilPQeGOeGA0jb6vqI4W4a KQig== X-Gm-Message-State: AOAM533uGt67gffzF9DBrLuOy9YJVWTvbvAnq6PVZszM09O0oHrerWT7 54hXzQw6fBwtRWWmZfyh0B4= X-Google-Smtp-Source: ABdhPJysWxc+TAlm+ctgH1Xuw3U+dIcY2JoBnCZcJOfWq19ss3KHzzKDrTCH6LUMvGYcbq/pkumZmw== X-Received: by 2002:a17:906:653:: with SMTP id t19mr138235ejb.44.1610476548916; Tue, 12 Jan 2021 10:35:48 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id qn4sm1510593ejb.50.2021.01.12.10.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization Date: Tue, 12 Jan 2021 19:35:20 +0100 Message-Id: <20210112183529.2011863-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:35:53 -0000 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a213..40f72c36b61 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -428,8 +428,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWT-0001Ed-Hj for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWQ-0001A4-Sw; Tue, 12 Jan 2021 13:36:03 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:38817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWP-0007IV-D3; Tue, 12 Jan 2021 13:36:02 -0500 Received: by mail-ed1-x534.google.com with SMTP id w10so2536878edu.5; Tue, 12 Jan 2021 10:36:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cIbTTFaWqBlw1RG7hwtN0wXtBq0CsVDSjfCtHIelito=; b=oa8ugs1bbQImjYGvzrrC9iWH7/IjBH8mPKKCZ8C05gGEOlFpRWPXcWH4bujSXJxR8L vfdcmn6vRw7g3PkYOqWmlzTbHMNuY1Ph7Irgfxri+atvvyZtQN/41RqW7jM5djB97iUw ir2MPcYNIOm8vAX8c5zUSTIwz5ikhwBjsvnKdgbCuC0y4NzD7nqrrEtLK84qtCfZ9Pyy d857Hx/cImqGReyN6V3IacfHN0VmVMQ+ng/9uFA/GNnDlGZU9qHodYNM8iiS86lZhSKa qFSarRoX10B9uNaB6TRZJbBqeVfKG70WV+My3vz1aGTACF3yp615ysOW/t8kmLyR+2WT c7/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cIbTTFaWqBlw1RG7hwtN0wXtBq0CsVDSjfCtHIelito=; b=Tns69vjJxrRWRbAb8MMQ/0keXswoxC6n/Ox0pFXMTthbwVysSp7k4OFHgP1j7S1wWY N1zyaIQvfW2yxWmlb65ORsIevkxcs++Q2no9ulqoHMxdwNMC3wBGKY/XxjessMJncmeQ dageGtA/yMZm74y+fXli5fKDWkbiL5u2O99i2pjUUNH8uoUUU/CjTtmundgJmdVSwXkQ xbYdRJtU3c97gC3byOdslFkG/1vHW5iuVlY4Yh3Pvuw3eY1z2g4LSKn5/ilWtoxbgd0s N4/SjAu6STgD2/NWLGgO31uj214yusy3muioOR5OAwwqcD/qK4UvQNLxotpc0zm9WIeJ lTyg== X-Gm-Message-State: AOAM5305MBO8W3RAUIV9o0yQ6EjOJAKq/IlAS2z38z7QIDBnaY45/px6 lLOefOCISYDpDsDDX4u3i6M= X-Google-Smtp-Source: ABdhPJwXzxR76AAx/y9vRklqRXPWNY6DAT3STKdSWqBWNiTOJe5HoaMnC6gcmQVmIM/ugRNI5omFog== X-Received: by 2002:a50:f745:: with SMTP id j5mr384426edn.92.1610476559715; Tue, 12 Jan 2021 10:35:59 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id x16sm1526282ejb.38.2021.01.12.10.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:35:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events Date: Tue, 12 Jan 2021 19:35:21 +0100 Message-Id: <20210112183529.2011863-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:03 -0000 Convert some DPRINTF() to trace events. Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 8 ++++---- hw/ssi/trace-events | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 40f72c36b61..35ab33c0511 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "trace.h" #ifndef DEBUG_IMX_SPI #define DEBUG_IMX_SPI 0 @@ -232,7 +233,7 @@ static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); - DPRINTF("\n"); + trace_imx_spi_reset(); memset(s->regs, 0, sizeof(s->regs)); @@ -290,7 +291,7 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) break; } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); + trace_imx_spi_read(index, imx_spi_reg_name(index), value); imx_spi_update_irq(s); @@ -310,8 +311,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, return; } - DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), - (uint32_t)value); + trace_imx_spi_write(index, imx_spi_reg_name(index), value); change_mask = s->regs[index] ^ value; diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 612d3d6087a..20fcaf32df6 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -1,3 +1,5 @@ +# See docs/devel/tracing.txt for syntax documentation. + # aspeed_smc.c aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]" @@ -10,6 +12,11 @@ aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" +# imx_spi.c +imx_spi_reset(void) "" +imx_spi_read(uint32_t index, const char *name, uint32_t value) "index:%u (%s) value:0x%08x" +imx_spi_write(uint32_t index, const char *name, uint32_t value) "index:%u (%s) value:0x%08x" + # npcm7xx_fiu.c npcm7xx_fiu_enter_reset(const char *id, int reset_type) "%s reset type: %d" -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWX-0001Me-PC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWW-0001Kt-Ka; Tue, 12 Jan 2021 13:36:08 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:40521) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWV-0007Ma-4N; Tue, 12 Jan 2021 13:36:08 -0500 Received: by mail-ed1-x529.google.com with SMTP id h16so3452689edt.7; Tue, 12 Jan 2021 10:36:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R0MM0ZvXm81S3gxFhlsST007qT204dpEehr2O4ofqxQ=; b=KjFZd81utKeR/XF08XMBeTVS9v7vUehzuq1k00/ZDOdHUVHbexNITTyQzD8t9rnSLI RU3252frLzqIYQB3voniiNW+NJfI7NA+68e3c+ZcpPtOaPF1ZIZmJnFc5EreipzHs0KN AS3PvI/ukfRcgkE9gWQrBOQxMVr0+QCOJq295MUREv8TEqcc8FeKat9gvYfYffg+jmW8 t/sBZJ6GcEvlTZlr2J34IO1VJ+OwAoxpGa2MKlHTfGy5nngPsbyBncpSzC/qZnm4BlUr 9fWVahkQ+b3s2mPXWn8Ck5TNSd8IP4euMjv8w47TNvIkKtPUTWWALx2fTOvk1jftc3TY tA8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R0MM0ZvXm81S3gxFhlsST007qT204dpEehr2O4ofqxQ=; b=MbdwDwYPma1NPjjv1qggLE2fL6BjmwJDSYHAN6+WLXmztJXuUUMt+gmidvrBWPMEH2 GGEH4U8u7MH2Z+jLlQF3C8gmJKEZxzk7uF1at75EMqcE9uvJNT23zzj5L5wE1zb1s6ZN mTxv/nkxZx884ythKHvMo59to1n79u0RknBLAGpI0YXOXLnHotsC9oyxSiH/7O9JS+kv VJ3rCXobWswvGIT7o3hNcL7eEZt8HlDS+TviksPIThlkcKP67AQKUUvyGDOD0YVivWry Yaed8Yl+XA5Xa+QTV+UxF+gGvpTSxIvNdGfEWgBRLTwixOnD4dyM0c2e3uFtgVpp7R/H uLDQ== X-Gm-Message-State: AOAM532M9Mj2VVCcW0chPhy55vY3tfFUePPwun1LKBG7/qzk1zN3RlKs +FUtszERGJtRaMAJXjJrMEcJaxmF77Q= X-Google-Smtp-Source: ABdhPJx3CqJDao2pbNTliZ/mlAU1Sgl2f2xIQ2UdeyLer7cPCC4f/IRYkdl/W7uAQA+9WD6KPU/pcA== X-Received: by 2002:a50:8a90:: with SMTP id j16mr364550edj.334.1610476565506; Tue, 12 Jan 2021 10:36:05 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id bo20sm1862004edb.1.2021.01.12.10.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:04 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope Date: Tue, 12 Jan 2021 19:35:22 +0100 Message-Id: <20210112183529.2011863-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:09 -0000 Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 35ab33c0511..bcc535f2893 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, { IMXSPIState *s = opaque; uint32_t index = offset >> 2; - uint32_t change_mask; if (index >= ECSPI_MAX) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, trace_imx_spi_write(index, imx_spi_reg_name(index), value); - change_mask = s->regs[index] ^ value; switch (index) { case ECSPI_RXDATA: @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, } if (imx_spi_channel_is_master(s)) { + uint32_t change_mask = s->regs[index] ^ value; int i; /* We are in master mode */ -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWd-0001aU-M8 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWc-0001XF-6P; Tue, 12 Jan 2021 13:36:14 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:38446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWa-0007RU-Kg; Tue, 12 Jan 2021 13:36:13 -0500 Received: by mail-ej1-x62f.google.com with SMTP id 6so4937015ejz.5; Tue, 12 Jan 2021 10:36:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sTf/aemsAO2NtfPs8v4zrOflI4yUb4IKKFkIlDtQdrA=; b=nt3Sr93wmoNyIKcCz30xibARHh/Rs7H3fHH6D446KnXhwTyWIkulJq7KfkrYodKvru aXDJt50D9ItyavdSgWtYPl7yFpSNv2eF7V/MuiMFrZwZZkOPbndH9iryksotchCc+8F/ TOEbXjMKvj45tc74hvq5C1imH7Q9FJFvFzBTXtnFEgMk0TMOxXQGHQHDjOK6XvGEodVd 8BuSpizxXUtxillHfEMKT5BmMdhEmCGeoP0pVo0AMXBL+/vaqJy9gCJStJ9fgfODvBBk NgpIAB00M16eVPPiKuFDFGYCuPLCQx1t4945XaqZtfKyVMm4rBvnUmIX/+Zkfpo1Nwnc Kk3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sTf/aemsAO2NtfPs8v4zrOflI4yUb4IKKFkIlDtQdrA=; b=r0bJ2rakuVu7A7nuSuFEDvhsQ3C3Ks6t4FCFDJVW4g1vG50dxuC73vWo2jK5s1WeMd ia4npmxvZ1AetBjpVhaUGjEFDkTMi5r5umK2w1J2XcHChIgMiTy6UWNc15uepXpkENM8 lMbPDQnqYdPQ0cH64Dd8Zu6Yv0D5/NixI1rgqz2sTCrrZDrtoBV6OsRSpHxz9xDUfusl nwlA/2YzMG0BpsqP1b5bw5ozOR2NBbROeNVTfHPbV/lVQNoOUqx7/D0dX9kGEaoqgZy2 PEDuYwPBKmq+JZaXeEbGiVVQXUQ2eCBm0RtFIcayDKhXc0QbkFGmaMHMf1mfkK5igdYq xDDA== X-Gm-Message-State: AOAM530HGW1UOD+Bcq2+LJSBgURyHxd1eJnaGQVADlORXETlRMuGhSd0 eKenE0EawOVhVkoOqHUzMtI= X-Google-Smtp-Source: ABdhPJyTLFYq815QTQiMct9wfSoFn3sulj1+mU2xMypZG7hgK72rzLWTWoiZ7LNFLtGEt9U8PIJUPw== X-Received: by 2002:a17:907:206a:: with SMTP id qp10mr124370ejb.432.1610476571090; Tue, 12 Jan 2021 10:36:11 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id d8sm1823526edm.75.2021.01.12.10.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Tue, 12 Jan 2021 19:35:23 +0100 Message-Id: <20210112183529.2011863-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:14 -0000 When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index bcc535f2893..96aecc8fa28 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -232,12 +232,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + unsigned i; trace_imx_spi_reset(); - memset(s->regs, 0, sizeof(s->regs)); - - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWm-0001lo-A6 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWi-0001kJ-3C; Tue, 12 Jan 2021 13:36:20 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:36991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWg-0007TJ-EO; Tue, 12 Jan 2021 13:36:19 -0500 Received: by mail-ed1-x52a.google.com with SMTP id cm17so3471897edb.4; Tue, 12 Jan 2021 10:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s5mgKFMjtxL8UOIPFrajTKd7ASiN1mJ6g35FLNPKpAg=; b=APEjyaBzm/Du1d/Ys5l2VuIvlSxTisLqbzBMDlXcYC/JYhgqGXvmketuAr9kV2yaK+ LUCSHVoMmdD8itt2tRm0Ws9w6PUvVszR6gFABsvuhAZ0NV3YJeK0VOKkwRA/YAQpInAn L8EgFn10Q7FP1TJzVIfU+j7OWy7k1IJF97B9sQOCSoCPDBDGQ7UuTHuky7avtHvEnI4J ZfvV/2Xk21tvefzXWJ3fI3Q5LJInvAs/h4z3x8Ii3XIQyuFcWA+05V0PI8HSzbROcTFu z7lo7G+7KNY6aiEM18l3OnvtU8gcX+Jth4Q8olBJvjMfWPsMavzd+t1nm6V2+sl8bq48 JW/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=s5mgKFMjtxL8UOIPFrajTKd7ASiN1mJ6g35FLNPKpAg=; b=TDYbyQZCUVYLtv3LEBv4git8Stw9pQf8KwD11tuz6fPtX/XwGsuzyR4CZD+NdLvYzI O9reD7s4KJEus9gTh5MshlvbTm4AjPAdw9ukWAWqLSjpwIQcx2ZbXG1/wL09oXurPsWr pR8KeI4BhVZGbPjo19KNOvFVl/CHA1qW3UWGFym4VYHlOy6ThzSUYB8tglQUIUTLr9YU OipU5HaB2V6kYSoMpCOXtVt1P0+Rc3sjUTAXPu6LrJnVjRPMj79wphVJ2O1hQDm7t6AT E/FSXIpXJatSGFN/Fs4nWGzt6xhAtZGikN99c1LuGMFC3FsC4aUt9npX2jmhKLU0FzLS tmIg== X-Gm-Message-State: AOAM530ix4UnBaRnVyA/ES4IT11Y04yrKmD1oobCTQGYrpJWx/tE5r4y MZ0PSXLbak5ph0MohT8HNRI= X-Google-Smtp-Source: ABdhPJwkjhG+m1UD4DrA6ECTXBpnxlTrl3X3ceYmb4EKbWvuQJLDMsFTmrgQEqnuto2LXLKicYFZ5w== X-Received: by 2002:a50:d80c:: with SMTP id o12mr364538edj.338.1610476576862; Tue, 12 Jan 2021 10:36:16 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id j9sm1801373eds.66.2021.01.12.10.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Tue, 12 Jan 2021 19:35:24 +0100 Message-Id: <20210112183529.2011863-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:22 -0000 When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 96aecc8fa28..7ac9da0f1d2 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -270,42 +270,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); + + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; } - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from MSGDATA gives 0 */ - - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - trace_imx_spi_read(index, imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWu-0001ra-GR for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWq-0001oR-Bv; Tue, 12 Jan 2021 13:36:28 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:40595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWm-0007UX-Et; Tue, 12 Jan 2021 13:36:27 -0500 Received: by mail-ej1-x629.google.com with SMTP id f4so3840454ejx.7; Tue, 12 Jan 2021 10:36:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UUrqq49b0H8vT1YH+cv+uaCjRkYF+aPQPM0uhg4pceE=; b=EJJMRxbbJxh8UJwD7/C898SYLP5gBXoO4/wgs1dvDaZnTWJuXj2ATH9mQEW4gy7pAW EsE4BG1osS3BWvEDnKmmVpsJlm5PkjrhCkD8pNTcHfG8MpleSoWlNBrG7/fYEuuOkayV p5CGVDXtiB/MWb0JF2hkkau8XqI7lTFAc+TyMJJ5Fwv2XPOR6Skpt3o41isDM7Xt2ztt Egkchq+1lLr1RLF+K7HD/ajsyudnSufvwgtHHm8CqrvXh+r8DgkZ0UdL46srdnOj49lg HHPsdVpRc3tNSz5doC4fHaFD51nIVYrlYbXMJEoM8kWt/Diroi3njSvErLYqO1/0y2iO kujg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UUrqq49b0H8vT1YH+cv+uaCjRkYF+aPQPM0uhg4pceE=; b=qiseRPbuUMHtXZkeDooCq3ZC9EX02ZQx1GRxfdM3zipWFYbHkPxu3zuXl7qL/cNoQL gU/9IQOjsfXUJVeeUTsOyN/X3dCaWrY0/HIjNb0wbgB4s24vIqHoh23xdYNmdRMNr47n ScgT0eiM8Q68fY1aOV11BV07SH+7p+zqrv4aTfLtDx8V6ozthHOPWhDbniLZ5NRHhTns D3yLKyKZGtK6B7kM6+KpHt8uptOYvlSCvKA4AAq9tcDFx921luHkttDIkx7BzAKFYj1/ PjuphdqB630QyzEBKV0yM+t73u+SqzmpzvTZiZJ+etQzJeatVlaJCGSrPNQ3JJqw1eUg 2Xcg== X-Gm-Message-State: AOAM531V9k3VnXxRnK08C2ca/xo6aC5ZSzbdOcgVLQuTvOnlBWzfrfvV 6+eMuDQd6uawG1XqF1FqYPo= X-Google-Smtp-Source: ABdhPJznm2QYUQ6cpnSpv5X4F2y1tDvJrjYXJC9L5neUa8ZZ7s69gJ6ar8bMbCxEjjQ9D4bPIfPhWA== X-Received: by 2002:a17:906:878d:: with SMTP id za13mr98547ejb.395.1610476582574; Tue, 12 Jan 2021 10:36:22 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id r21sm1779423eds.91.2021.01.12.10.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Tue, 12 Jan 2021 19:35:25 +0100 Message-Id: <20210112183529.2011863-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:30 -0000 When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Move the imx_spi_is_enabled() check earlier. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 7ac9da0f1d2..801daa5cbfa 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -321,6 +321,20 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, trace_imx_spi_write(index, imx_spi_reg_name(index), value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + s->regs[ECSPI_CONREG] = value; + if (value & ECSPI_CONREG_EN) { + /* Keep disabled */ + return; + } + /* Enable the block */ + imx_spi_reset(DEVICE(s)); + } switch (index) { case ECSPI_RXDATA: @@ -328,10 +342,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } @@ -357,12 +368,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; - if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); - return; - } - if (imx_spi_channel_is_master(s)) { uint32_t change_mask = s->regs[index] ^ value; int i; -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOWz-0001wD-Cd for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWu-0001qp-4u; Tue, 12 Jan 2021 13:36:32 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:43323) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWr-0007WO-St; Tue, 12 Jan 2021 13:36:31 -0500 Received: by mail-ej1-x62d.google.com with SMTP id jx16so4892396ejb.10; Tue, 12 Jan 2021 10:36:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3oL8bC8x9VFwiA/xc6ZokDU2TIJ+D0ZdajpMhJAtRjE=; b=pzLiDzMgO2qqe2xY1cGknoalgMmhRxSV1G3RrQhEbCujzyXMOPbxqRLBBZh8ioK+QC JSOBJWrEv+/WfBDGtrj1o1uuMDav0IQXvK7K21u4+v2oY0ZivsHgnRik7wkYZsWRzazS AdWAY7UqPK2MnePUxrTKaZUP99Fhc1XAvhzraM52iOTf85rv9T2a0WlKugOgfoK2AGnO MEt/uV9mlP0iyoS0pLf/uf5qVldhU+eNCHg4khq7OuA6dddSVlDGrbm/pHqL3od20eY1 Dt4hKixGQrE9LYy/JTomthxBKyfCQ00mwDxYDtpU8NbRXfrNWuGkTYg4QfZriqo8VWXJ J6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3oL8bC8x9VFwiA/xc6ZokDU2TIJ+D0ZdajpMhJAtRjE=; b=JZAfOJzuhlMUAum/xVpZdUm/DEVXhvOh4hiplz6ykEa5co69bgD3Q/y50UJubHqJM0 V1c7kntjtyTsBUr+v4XMBrWOnPNV6QeI2hOg5ZjRo3SMZtkwAZj/d0GbyJGBlE36XgU5 TAdgxQy5ra0s5y8ssQgor2QByO0jf8i57WYFVBi44eHDERMNC5zH0nEWmg51ke5U6nyg r+Tt3em1Zwt7JXw9gqH5CyzED1r9nMvEVk6wG3QXERso+2STd4woQV77NGzm2V1zjkhT 9lf52ZjfsreRMyz8g0B22n0M2RCiUthyLpu1N8Yjdi5G4ddONogo8G+f7bj3+/l/Hz9H uXLw== X-Gm-Message-State: AOAM5317kOdhdIAofY1itsGUq/qBxXmO4Ia5KVB+Xx72enAcSfaD6yJS 8mpMlTsWVQyb/8NDcDRwehw= X-Google-Smtp-Source: ABdhPJzNVjPNHTWfdTDu4WsmxLITpifXl/wpM6+l3N1UEWB9deJNBPNSw+YabAM7dHGcuTVg3j30VQ== X-Received: by 2002:a17:906:90d6:: with SMTP id v22mr139279ejw.88.1610476588169; Tue, 12 Jan 2021 10:36:28 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id k15sm1503481ejc.79.2021.01.12.10.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , Xuzhou Cheng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 12 Jan 2021 19:35:26 +0100 Message-Id: <20210112183529.2011863-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:33 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 801daa5cbfa..2f9e800dd3a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -255,6 +255,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; } -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOX2-00022q-0V for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOWz-0001ws-J6; Tue, 12 Jan 2021 13:36:37 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:38444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOWy-0007Xb-4C; Tue, 12 Jan 2021 13:36:37 -0500 Received: by mail-ej1-x629.google.com with SMTP id 6so4938540ejz.5; Tue, 12 Jan 2021 10:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=URPw2976JZr7XRKyhMiAKOdcNTBQU8VnrnQ2GFeuE/U=; b=l20l7gwWIKPn32PIaaF39Dntbr9gVgUYcerX5b/rTYZA7TyEvIP8nd7HeayFeQK3ut uSpCBts9Krux9jifdRQf1QkakzQnlPS+kaCnIXyJD1M8islpFIJquKX+FaJzEbU13TrO WXb6rNpWZikweRuVb0O9R7GP2Sh5XUn98RmcBMHk8tpygi5E63ytZelumOVZsrCLx4F7 qR471FnxLEEhKy1b8mFjbll+c7yfIay1OmnLuxN8mQ9g5bJbOY7Yee06O1/3qonWxTIU YF053G4+farbNVdkrGKWKpatA1keGPDKMgZAC6GfkocEVaXfIKjdAAhgOtC6K4G2Tww1 2rZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=URPw2976JZr7XRKyhMiAKOdcNTBQU8VnrnQ2GFeuE/U=; b=iCEO1Rj+K3xI5lCDj0NkyP0Mi6Y4uCHG82E+TuZsj+AzPg1xNuuspoymzmJ8qaCVIC QX4LO0RfZO/gkzlXHyNYev8u/ZrhCWgtt4zqph2KOg4oQGjTkmgOGGCHoc1GCFrua8Ux oGDRQH0Zz6waF9bS2n+DAhhBxqcirnq0L5WtZzXxGjttCVYtcGheRZyqyojrioWmAkTt KIgNK3bslykUwx/37JNcG7+MROgKp3BC6rTBL6S/Rm24n1wotola7Kv+pdSiWcRstBt8 k9rN/BYv5PbCnUTp/8KIFH3VfiUcgHvyEayI3tacMnmAbB7w6CCiTtajNEOtwTeTZzW9 pehw== X-Gm-Message-State: AOAM5325PQEbyc0oN7P1fUtpiXEJrkqMhJj8RXaU+16FNoYfGHQ/cDTr FYh49Di+u+mlmXiLnZnnnqSvZLjoss8= X-Google-Smtp-Source: ABdhPJxVs7D+TeVRgmikig04ysNfEvpjXa9GxFu9bq1Fp9EL34h+nql5Lmf/X1Qb7jol/+mc9emwkg== X-Received: by 2002:a17:906:d8a1:: with SMTP id qc1mr125349ejb.294.1610476594097; Tue, 12 Jan 2021 10:36:34 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id k2sm1516490ejp.6.2021.01.12.10.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Tue, 12 Jan 2021 19:35:27 +0100 Message-Id: <20210112183529.2011863-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:38 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-5-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2f9e800dd3a..638959daa08 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -129,7 +129,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + burst = ROUND_UP(burst, 8); + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length rounded up to %d; this may not work.\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOX7-0002Fx-25 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOX5-0002Aw-1Z; Tue, 12 Jan 2021 13:36:43 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]:35528) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOX3-0007Zc-HC; Tue, 12 Jan 2021 13:36:42 -0500 Received: by mail-ed1-x52b.google.com with SMTP id u19so3485492edx.2; Tue, 12 Jan 2021 10:36:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xLLdvkIJe1l73eWOGFy35bKaZgGosmrQIeGMAiRhIRc=; b=GGdNkTjdD2SqUviwqnZEDqQkbcZq129V6FUHz6H1xgq8nZGAWREXGKd6RgQi5DoR3J pUGB0xdlbTctnsCfWeWpFuvl/7NFfHFOeVaHRVd5s322a7WN1zHZfMQmPJJjeJJLTFgA 74aZXkOrwvGpir5QiDW2Or2mLKmEloFYg/0z3KVMqXXhu3bZ/hO8mBlJp7LX/PAqTwLR awm6qogOKyv6w7up9vZ/VnOdX/hfex6EJEAuUMIG5b4IAPspKK3fD2V68VTSC4beSm4C nwBFDCIwtZTsfO0va8uwp76vkS8Ipwwm3V9pjZhwDGIM8K1JV6knoDDX1XJqveMDAXW3 4/Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xLLdvkIJe1l73eWOGFy35bKaZgGosmrQIeGMAiRhIRc=; b=cLMIfuuXxXWwjNTlzgQCaC1zFESk293U8FdRxBy6ZQcHcDnXdQ7eOkJ9HPx9/UaB2D esqSDzVHbwdugy67Mbm99u0cFW75bWbF+oO2ojnnCLQuO27UuEZ6D0i9aTwb5ekmQVzf sEUBKLCkYMUjvy8NJfQFC7HrGRgjp294wfs6J7AwvA7sVe675hOnKMQdGdwp6wiZq+7J 3p7ndDy9WVF867rvZblpDmr4cHb9EAjXz4tnz/XL7IeFruXVvcmMYkTy8UdFLxclWbZ/ 0q7IeLEUnO2tt1L/xzgalgOuQZS3SbA63rCPMXxVTmsND9z0EDMgDMlanL78aaVnxHlj ljaw== X-Gm-Message-State: AOAM533iAswEn2DhLWfO3zQrcr9Uw88zBZi0n7XZOwcmZeNYq5ggLRNk T6QHR4WAAzhZ4BF8JCDJl5TQfYwoTYQ= X-Google-Smtp-Source: ABdhPJy9RrAi0h8sC/vPap5Yg4VTQNuty1PJc6i07aUmQo+7XHcYfVaZj/YxXT/KfMOdPgGpD0w36Q== X-Received: by 2002:a05:6402:31bb:: with SMTP id dj27mr356816edb.285.1610476599942; Tue, 12 Jan 2021 10:36:39 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id x20sm1517322ejv.66.2021.01.12.10.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Tue, 12 Jan 2021 19:35:28 +0100 Message-Id: <20210112183529.2011863-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:43 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-6-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 638959daa08..c4e2d2e1c97 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -192,7 +192,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:36:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOXC-0002Sw-6s for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:36:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOXA-0002PW-Ni; Tue, 12 Jan 2021 13:36:48 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:36999) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOX9-0007bO-6D; Tue, 12 Jan 2021 13:36:48 -0500 Received: by mail-ed1-x52c.google.com with SMTP id cm17so3473335edb.4; Tue, 12 Jan 2021 10:36:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4l0kq3wxIJBsGcT12cxU3gmDmz9IWzR6E0aRKmJTUjQ=; b=mFaV7NYmXIn6g4HptlIczJ+2QraPAoku178SziHN3Ki75DJqHBhEvxiMUFN9Db/nBx +hpOdBPj375NjffcD1HiIAs4TLsQpAJ3SS+TswKMivRx88KPUJ9KDomUrY4NOxyYm9OP kkT0DnHoxyD3eW1DWDNDV9rr0qpNuOs0BbiHOSJgWV1M5i1nla/YhnCt/7M4qY777ylt vsU4V9oZXrS4cp5QMIaaIVzk6ftBVMGoMDQO+lq/WvOTP6vZkFIK2a4TuYCpUwyNxT+p KueS7vkMS0OWpht6FpjzH2EztTtYqkHyle3ThJksYEMhKjsC0pu3vmRcOhN5IanM1qDq ooog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4l0kq3wxIJBsGcT12cxU3gmDmz9IWzR6E0aRKmJTUjQ=; b=TAIIQKe6L76Dv5S4lgpRqrMW80V99szn2Okt033+pFGjjZNLztLbKC+JMJuhpwlpj0 Tts32xCoJZrh8XyYxWZKnmHrYAM+1g8dVGkCOy+5RlTHpb0667LAaO7Fn6MMTbD1JWMq jktMuijlZDKFFQitkNMIsIwOzEvxtIgskBo+pH+DbLD8AL3dVT7xLu5b3BYGSe05OkPR +kyNLT6nMsEzTofV4tl4vm9nYf84ZXNtCftDKuQh5nT+bEXb4HJzB6Ji4kNyIXZJ8pzQ lXUV06f7KMCfokf6aKkQ66Sc6hmvPNxgvwm0xemri9XR2V9rkb+RMJ7HVuk/tZPijYtX GTeg== X-Gm-Message-State: AOAM5308XKw6FFVqk9SNkyuFXiCt1oXQ5ww420V0BqYOHKXfuMJxJIao 947iIochQLjzwd/pFBKzYAw= X-Google-Smtp-Source: ABdhPJyJun8fhYKMg5tnrCY8tIgZG0kKJ/eXtJ11t71Z3aPw6nE1o0p+5vFfOBCZ9T7InoytwoVgVQ== X-Received: by 2002:a50:fe0e:: with SMTP id f14mr372860edt.159.1610476605633; Tue, 12 Jan 2021 10:36:45 -0800 (PST) Received: from x1w.redhat.com (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id k21sm1830660edq.26.2021.01.12.10.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 10:36:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Bin Meng , qemu-devel@nongnu.org, Bin Meng Cc: qemu-arm@nongnu.org, Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Tue, 12 Jan 2021 19:35:29 +0100 Message-Id: <20210112183529.2011863-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> References: <20210112183529.2011863-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:36:49 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-7-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index c4e2d2e1c97..38892698918 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -176,7 +176,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -197,7 +196,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -206,13 +205,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.26.2 From MAILER-DAEMON Tue Jan 12 13:44:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzOee-0001lK-HU for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 13:44:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzOeX-0001j7-69; Tue, 12 Jan 2021 13:44:25 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:39311) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzOeU-0001Ra-My; Tue, 12 Jan 2021 13:44:24 -0500 Received: by mail-wr1-x42a.google.com with SMTP id c5so3588743wrp.6; Tue, 12 Jan 2021 10:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Gafi+AcTSCB60SON0vhSVTavhCFJyfDgqwhbcMo1Q5o=; b=S0aMQrWx9eHTUGndIeFsPrp0Vvu8ZTsoFA8X0mtgNbfxcQLGlEwLSgL4dRNPOJLUga FmFMa7Q7aYyF/PpcGIcVM8A5Xjop4DD+Bi2F5e42j1N7kQv2ychbEBnVTAnftuDPTwN7 Q/Qh7dFljJMuBq3sNgV092Dy3s+2vnwL7F0u75+diFf5o/nGZA705kzyzHKwITn510ef nISCEWJJK9KUlHD55r5TlDjIjLH8qCHxM7+imCT7Z8aZjMUn40eSZeLiA7RxxmEEumwr M/g1+daH5c27NcDXiZwBRNXPVe/a3A+cgVooml6tkM5eWQPvuNMi7/wN2pJSyNyVTAn0 nhGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Gafi+AcTSCB60SON0vhSVTavhCFJyfDgqwhbcMo1Q5o=; b=mtz/cemP5r/ZC9R34UBYqDZzsvxjfYhgUkmaVZAg7NHBFa80pBVwfxMfjMsO5vgKfd Qndd62JyLuKP2SWrAJYcFht3KUjoodHLDhGB8/ELcQTbhw9UC5RyhDPz4GFx7RW0eYEG /8S1OVRJl40eV/fjBu9G9Or4AsywQEFJxQnzHY+xdWjoucQD9kWfobpI/cQKzASFOnzX aXI21UPAeHjsF9PRVu5i847hFyiUKnY6RwL6ewWpkt5HuW8rhO8t8esOjXJCgKMm14GY k0fPnaNpu3ILKsly1TynPAjjngd2kilK1wX7q/N85aeAXWvGwXiNPx9MwEanI+WGA7I0 QGtg== X-Gm-Message-State: AOAM530j+fJP7+zVoayY9L5S9SwmwpXloKi+tX6xzc0Kd0ImnyJ+huD0 FgaI0erHgTqVhj7LYOq6QOI= X-Google-Smtp-Source: ABdhPJwRrSd08XC8ezUjE0YCC4vvSAMOCK7YXGUjfVVLDBpS+i8GbEcUz7qc165fNAWWfbkp4z8FFg== X-Received: by 2002:adf:a543:: with SMTP id j3mr200307wrb.175.1610477060572; Tue, 12 Jan 2021 10:44:20 -0800 (PST) Received: from [192.168.1.36] (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id j9sm5985648wrm.14.2021.01.12.10.44.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 10:44:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v4 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Bin Meng , Peter Maydell Cc: Bin Meng , QEMU Developers , qemu-arm , Alistair Francis , Jean-Christophe Dubois References: <20210110081429.10126-1-bmeng.cn@gmail.com> <20210110081429.10126-7-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 12 Jan 2021 19:44:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 18:44:25 -0000 On 1/12/21 1:48 PM, Bin Meng wrote: > On Tue, Jan 12, 2021 at 6:46 PM Peter Maydell wrote: >> >> On Sun, 10 Jan 2021 at 08:15, Bin Meng wrote: >>> >>> From: Bin Meng >>> >>> The endianness of data exchange between tx and rx fifo is incorrect. >>> Earlier bytes are supposed to show up on MSB and later bytes on LSB, >>> ie: in big endian. The manual does not explicitly say this, but the >>> U-Boot and Linux driver codes have a swap on the data transferred >>> to tx fifo and from rx fifo. [...] >> >> This version of the loop definitely looks a lot neater. However, >> looking at the code I don't think there's anything that forces the >> guest to set a burst length that's a multiple of 8, so you need >> to handle that somehow. Otherwise on the last time through the >> loop (tx_burst - 8) can be negative, which is undefined behaviour >> when you try to shift by it. > > Yes, that's why I added a patch to log the unimplemented behavior to > notify the user. > >> I think just rounding tx_burst up to a multiple of 8 before >> the start of the loop would do the right thing ? > > Probably. Given all flash transfers are normally multiple of 8-bits I > am not sure what the real hardware behavior is when it is not multiple > of 8, but I will try to add something in the next version. FWIW not multiple of 8 use is not that uncommon, see: https://guruce.com/blogpost/freescale-imx53-and-imx6-ecspi-silicon-bug From MAILER-DAEMON Tue Jan 12 16:02:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzQoK-0004c6-DC for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 16:02:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzQoJ-0004a5-Dv for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:02:39 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:35456) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzQoH-00080F-KY for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:02:39 -0500 Received: by mail-pl1-x635.google.com with SMTP id g3so2103220plp.2 for ; Tue, 12 Jan 2021 13:02:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Ij1bGkqoJJMpf52GUDQp7vKgAGhOWr/gUxAAsGdkCpo=; b=Uyvk4PqfHzMci7of3y19jT+azlSpVLipBvD4VGZBzhj46723EYkoFDwW2ILo6mTIdt KCy9sS+FtW2uJvIghyjck37+MElZZF5ifM7yaWlb4W9llj7dJ50twY1VkfYwS0m14iap yPNg2ENOLspqXpZ4Hycv/X7MQ1Cs5U7plwFImPqL7Sky5ZN7DCGjss16M7xvL1fvlw3J F776ySf6vFD3XZNoaBm1SIGtVQSCT2oQrcHDsLx0tTsQsTww+eNeioujfbxOxkVqNxxc 69tv5q0XrSt7GYYtZwUQ92ImOPBTw2oTk1KZ8DathDtMppoubRgEMeFaeCS89H1T/F7W Y1vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Ij1bGkqoJJMpf52GUDQp7vKgAGhOWr/gUxAAsGdkCpo=; b=pUU4HEREBAWcfLVUWuP23fJwvpVokaqxo32sh/aLeOqPWFcuo2Pu1wIuYMxFK0XihV dYUcNOD3xmWhs5mpEjDBTqkM1DC3jrc1llwQM6F+eeF9xHU5g7gz6723mCXUoNXSYRIu EuOOnRrPTMWmhpk2ct6myEqk+Im5Q90miUQSWNB8Ie9Sl/7L550dNNZZmhlK3Pui3k6M Zj7G29fqlR150UCq4BKGzTFLw1ZR+4W0Gl/qaWVF4SZPrk/889IuA4+6lGaLIgQJJLr8 iM5Wi9wdTOh0f2w55knWVLLSScFd07FyS9SShDH02yCwYeczvGNEywv9M0vQ3Gona5ak emWQ== X-Gm-Message-State: AOAM5330IU7qAhwiNTWYM42Q28Z9CJZQaeBLyBFCYoEToH9o0nrdcyhb PAinvN5J6EtzFQ/rJIxdtLa8VA== X-Google-Smtp-Source: ABdhPJyBIE+eMHlkFiLE+csFjnIYycdbEglQw/1adv2MoNEEGm0e6b61OQ0ukX75y7zEP3CkoUG45g== X-Received: by 2002:a17:902:8ec1:b029:dc:8ae1:7a22 with SMTP id x1-20020a1709028ec1b02900dc8ae17a22mr1286320plo.6.1610485355982; Tue, 12 Jan 2021 13:02:35 -0800 (PST) Received: from [10.25.18.36] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id g202sm3971950pfb.196.2021.01.12.13.02.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 13:02:35 -0800 (PST) Subject: Re: [PATCH 14/19] target/arm: secure stage 2 translation regime To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <12681824.uLZWGnKmhe@basile.remlab.net> <20210112104511.36576-14-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <3a1c73a8-865f-f18d-ebf7-d736d5e7e2d0@linaro.org> Date: Tue, 12 Jan 2021 11:02:32 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210112104511.36576-14-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 21:02:39 -0000 On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Jan 12 16:04:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzQpt-00074l-T9 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 16:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzQps-00072h-Ik for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:04:16 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:52328) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzQpr-00006I-4Y for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:04:16 -0500 Received: by mail-pj1-x1031.google.com with SMTP id v1so2402234pjr.2 for ; Tue, 12 Jan 2021 13:04:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=QHWJqvdEGGlIyfckLRxXx1RAqWiM08vwqtkSa+jKPsw=; b=VHWbVERk3eASe+NY+azbQeG9Ji6JMY7RniVKQpTVEdaSS3PZTsLmb4w/dwqFMp/Cfa T4fLReQI1mWerWmMwb935OInX4KgTUoi4hpgrEm6wR1G4BARlrSf9JeHLWAhPYoOJ0YR /uE1F621uT2THzmHTAoTg83h2/ykrmL5t69dgqRTCnmXe2RoajH5bKOQ0COwC83vkabX uToWGsjPw9pdlAPxWkq1aIdG/+RvU4/WBNKrv1dQBzOHrS1Qb3Dk2gLnwhcKfMFSHfjp r+lgFb738cZc4wa0xoUyApC7NqfIZeudj35gMrbJg2tlTsrqDSN3Q5OhEUA9oQyFF+aE BPZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=QHWJqvdEGGlIyfckLRxXx1RAqWiM08vwqtkSa+jKPsw=; b=ZCIhsXSLWW7OQXjBScSWlLFUhs/bWl5uMiPjcDcpuTrJZgSjnqodn5qK9NRrBvA5l+ cG8M2l1CgvaU2pI4CFVRKZVthMl/WZ7PCuvYwwSuRgAxRDT934Cc0Jw2flbep+1QitVx IXSazRTCpyVCia22xmW2lIB3Ex3nuQXFTAD0kDpitsN8LxxqxPtMYJTq3byKRKv0+Bpl Xza1IBSC7Dc6FNY4i0fsIavxPHRW26IDhfJAdAWB53pIEw/H2bcEzEiTuFxzJ2yX6EI3 YabtLJnXjfuWZizPb1Ubp3s7+6LRF8Zj9mi8ob/fZ3xb6PwM1gFCmysgUYlxMR4AQGYH 2zuw== X-Gm-Message-State: AOAM530Jy0IyDuqZ59dcmdxrvar5bSCl3gi70CWtQxX9qGti3zKT+FRc e35bAA7misbT9fbXf1wSX/2Yhg== X-Google-Smtp-Source: ABdhPJwP9MqE39LtHCA4pypQdbguFUurujF/pS1UgBQjuN/HrfrBpzzlKhVk2JQ/uw34alv3Zi7KEQ== X-Received: by 2002:a17:90a:4209:: with SMTP id o9mr1047118pjg.75.1610485452844; Tue, 12 Jan 2021 13:04:12 -0800 (PST) Received: from [10.25.18.36] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id g2sm4962214pjd.18.2021.01.12.13.04.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 13:04:12 -0800 (PST) Subject: Re: [PATCH 16/19] target/arm: revector to run-time pick target EL To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <12681824.uLZWGnKmhe@basile.remlab.net> <20210112104511.36576-16-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: Date: Tue, 12 Jan 2021 11:04:09 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210112104511.36576-16-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 21:04:16 -0000 On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to > the upper (64-bit) EL. With Secure EL2 support, we can no longer assume > that that is always EL3, so make room for the value to be computed at > run-time. > > Signed-off-by: Rémi Denis-Courmont > --- > target/arm/translate.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Jan 12 16:30:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzRFZ-0004A2-E0 for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 16:30:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzRFX-00047k-MA for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:30:47 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:37268) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzRFU-00019e-Sb for qemu-arm@nongnu.org; Tue, 12 Jan 2021 16:30:47 -0500 Received: by mail-pf1-x433.google.com with SMTP id 11so2195561pfu.4 for ; Tue, 12 Jan 2021 13:30:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=D+IJXKt51oO51JsVzIZi+vzH4wq53fO63tV2KNuJKXI=; b=DhmvKZgtbyWO5yihuEuAIBg2qcfcZgsDikQG9BR51azGyKpwQMRwH3K0Tx0XJ9TCw7 bTgJ5cW+698ohsSBV7aXrC5yOJkab2qrI0SW/8l8KayH5c9s6b+YbAygJy7ZntPetUYX eMb82/zyHcdN4/mbA60/L34Wp5PqdnQhIfItkODAuEqzsiRMFwtuNakNoN6w4th/Dpxy oDyGmfKrHBMFwd8SUFD5Y8dJq9eEb92D8x7cHJ+AEqS0KgZdgq1PkjCR5sA9xPCpa8BH wSsibTvP0+dOLOb8+BdPRggBD/G3EeNvNjpc+JS2pAiXW9y/vQQAw1zZRhDddX/3G8mT S4BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=D+IJXKt51oO51JsVzIZi+vzH4wq53fO63tV2KNuJKXI=; b=bJKtq/8JtpPdPBDwppi5N3TOEQVwwz9SSHlATyFzokvLdMl77zJo1YYc+4LwkikfT5 9Qk1s26jYSugm//jF9GuMG+b9SesM7r5r8iFYKbURs0lGPrrXYrA2Jf74XUPinkHqNPf uP3h5XlryPrN0PnbJ/xl50JYJYX3voXzyPN+4QFv7M8ZkdQKJtEXi+7BChY+jeO20XMq BYv86s4iq6TJzjdWii7YqJ2st9lduxaMQ+OhUZ51BpAleJjS/ET7da+V59zOL+IijLxH 4dyxfh+skVt9Yfz94P4F95mbNM/T8aK9v8ws/lmWQL+zezUVTlNEfR/PUqjKmZIS26aC jZMQ== X-Gm-Message-State: AOAM5308E6uTBlinL+370w8NBXc+uAwzyQbvPosM9WiBiLtEUOm77LAl /o5HyRAoOGHX1yH95BG1lD59MA== X-Google-Smtp-Source: ABdhPJzcwVDT6HSHXoQWruGT82SQM02FZdERDMocIpPeBV0i5K4HRcwwKED28OXP5fuPfj3JSNRE8Q== X-Received: by 2002:a63:6806:: with SMTP id d6mr988527pgc.205.1610487043278; Tue, 12 Jan 2021 13:30:43 -0800 (PST) Received: from [10.25.18.36] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id c184sm49022pfb.11.2021.01.12.13.30.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 13:30:42 -0800 (PST) Subject: Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension To: remi.denis.courmont@huawei.com, qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <12681824.uLZWGnKmhe@basile.remlab.net> <20210112104511.36576-17-remi.denis.courmont@huawei.com> From: Richard Henderson Message-ID: <6ffaca60-2fa0-ac7d-b430-0bbaee18b25a@linaro.org> Date: Tue, 12 Jan 2021 11:30:39 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210112104511.36576-17-remi.denis.courmont@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jan 2021 21:30:48 -0000 On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote: > From: Rémi Denis-Courmont > > This adds handling for the SCR_EL3.EEL2 bit. > > Signed-off-by: Rémi Denis-Courmont The patch title seems to have gone awry. > @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode > } > if (s->current_el == 1) { > /* If we're in Secure EL1 (which implies that EL3 is AArch64) > - * then accesses to Mon registers trap to EL3 > + * then accesses to Mon registers trap to Secure EL2, if it exists, > + * otherwise EL3. > */ > - TCGv_i32 tcg_el = tcg_const_i32(3); > + TCGv_i32 tcg_el; > + > + if (dc_isar_feature(aa64_sel2, s)) { > + /* Target EL is EL<3 minus SCR_EL3.EEL2> */ > + tcg_el = load_cpu_field(cp15.scr_el3); > + tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); > + tcg_gen_addi_i32(tcg_el, tcg_el, 3); > + } else { > + tcg_el = tcg_const_i32(3); > + } You can't test an aa64 feature without verifying that the cpu has aa64 support (if the cpu is strictly aa32, the aa64 registers are undefined/uninitialized). So: if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && dc_isar_feature(aa64_sel2, s)) { ... With those things changed, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Jan 12 22:29:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzWqR-0006Ng-LB for mharc-qemu-arm@gnu.org; Tue, 12 Jan 2021 22:29:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzWqQ-0006NS-Ad; Tue, 12 Jan 2021 22:29:14 -0500 Received: from mail-yb1-xb2e.google.com ([2607:f8b0:4864:20::b2e]:43972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzWqO-0007aD-NU; Tue, 12 Jan 2021 22:29:14 -0500 Received: by mail-yb1-xb2e.google.com with SMTP id y128so827097ybf.10; Tue, 12 Jan 2021 19:29:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=L/xGhiAffFRK5UXRDej83VHjRmbOO4At1tkENfozVQk=; b=fsH/qh8RdZzXz7BWQMr0QUHUmPtu0EV8t3JzaGrcjsbewLvZzc3kLSO1e5Xg+FqhXI XSmFND5fFMMIMEcTwBzTYBmCAZYnWY21VqyIDpseQoOFLp8VFOkGdL82MmfK8IKOs8iW gv3fwwULgZgcz7dxVeJplMgORozW/px3+WxglkhD6N0NUg4M40DDjxXXIc6J9X7pkniv lbt60PUZdXxh+6PtDNHFDWdX8sDaZMtzQYKxENS5VWM/FkzlRiflqN3F7Uo2laiN1XTM j+oMVAEQcvX78kHA/orN+vQ+P5zDouEnus7d7geLv0HagD/bphshD5fl8MMS9MFFa9S2 5uXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=L/xGhiAffFRK5UXRDej83VHjRmbOO4At1tkENfozVQk=; b=nbCaX32L5dMK0z1c17MJE+2lh+f6rRp3mWvcjGVrW/Tz0TsvsZmJ4c+e8JASwG3qYN vQwzAt85Ok7/DE+XW15xbEOAJQZi3Rt3j6IVHoZ0s0AIG/FmKyxTZDFbMlbFUMGMsW4Y NJniJBw1EHfkaHXj5xZl/cl/6Y2bJL7KRP1aAv7geHfnqjeFbn+mDxaQDgA1Q07KUqan 4+wQ3OuOmJh6EDaps+zhDMRB2M/a+y7zViZQnxt/sdyAdVm1CJv+TNl5W62P0eQtXqTn F3eRgx+1GkTTBVSB+j69MoZ6l1gufeehNzy27GmhMNIO3iUou3JGSqEBwOspXWDeCdvt +r+A== X-Gm-Message-State: AOAM533MhgzGJQC3z0Geprjr+BlK9bYwLieQQJgZ1lcIi8VHDDNx2HG8 so4X9K4rLsY7/aSgbl/RY8dFcuWFVW85SYRspqI= X-Google-Smtp-Source: ABdhPJz+XwSZEsot9WSddIHt+Smjp2bQLw8QvwRq8Bbc8xy2jPjwL5LuD+MHb0dLZPVfW7XorV5QZMi8b9/ETRscW2U= X-Received: by 2002:a25:4744:: with SMTP id u65mr462730yba.239.1610508550965; Tue, 12 Jan 2021 19:29:10 -0800 (PST) MIME-Version: 1.0 References: <20210112183529.2011863-1-f4bug@amsat.org> In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org> From: Bin Meng Date: Wed, 13 Jan 2021 11:29:00 +0800 Message-ID: Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Bin Meng , "qemu-devel@nongnu.org Developers" , qemu-arm , Jean-Christophe Dubois , Peter Maydell , Alistair Francis , Peter Chubb , Xuzhou Cheng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 03:29:14 -0000 Hi Philippe, On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi, > > As it is sometimes harder for me to express myself in plain > English, I found it easier to write the patches I was thinking > about. I know this doesn't scale. > > So this is how I understand the ecSPI reset works, after > looking at the IMX6DQRM.pdf datasheet. > > This is a respin of Ben's v5 series [*]. > Tagged RFC because I have not tested it :) Unfortunately this series breaks SPI flash testing under both U-Boot and VxWorks 7. > Sometimes changing device reset to better match hardware gives > trouble when using '-kernel ...' because there is no bootloader > setting the device in the state Linux expects it. > Given most of the new changes in this RFC series are clean-ups, I suggest we apply the v5 series unless there is anything seriously wrong in v5, IOW, don't fix it unless it's broken. Thoughts? Regards, Bin From MAILER-DAEMON Wed Jan 13 01:27:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzZcS-0003wQ-3R for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 01:27:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzZcQ-0003ut-8i for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:26:58 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:52033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzZcN-0007DG-Vg for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:26:57 -0500 Received: by mail-pj1-x1036.google.com with SMTP id y12so498391pji.1 for ; Tue, 12 Jan 2021 22:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4MeLUJUM2UA6sEPX7Pauw8rYZ0ucS7Q7ySOaRCO+5jQ=; b=hGvfQEIIX7j8N49gvAruZWVahtHEnNu304TCy/1BaEFzVRtugthX8ITjCCCmnFl0fU 79i4QvPOzvEo9N2D84J6GFH6OcQOeyRN1LimAAtQAeFrowzCrbP1rc1lzQ9wy+pF1YT4 ogYccXR0FJHQ/tR8DyfXBnAGVvpP0OTAq+AAna80CIb4yXkZCoFgVygcsymrMMLPfaJI 6FNS9fXFYvHjXNHR6s7u2kJraMHpQ7AOdqLzSk+IEpdVB+tAW4R2R/8bZFtKOgwC6CA2 LnQGgrzbgiQBa+oLC3e8xiGT5bWTIASDNnpTfzq1jO3uLcYTrirgO2fUHIb0f08dltMT 5lWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4MeLUJUM2UA6sEPX7Pauw8rYZ0ucS7Q7ySOaRCO+5jQ=; b=SQm5AVJcijyQX8+X0MBlo+1icFu2c6wecmAJrvRsuyLXWhR34qcaJoCre23y2bt1gh aT1RD0Xr8Q0WRukwM1Ryzw2BtwRSKYQcFosj8qeRBnbys8OfzCLPpPnzaVpbw5uGZ1ds vGqSnGgyIxlMw8Z32WdsqjEPnUgQvA+Gv4BrHu4uiUhBekloct6EdwnEqz00Gg6y0Y8U 7TYqhxiX/Gfh90rzEsDs8Ohe/UGROmV8qh+NoSV0mQ0133xOdEcDDck2h8oG0IvOM4Zt /DlE7aqMaY85XuYEe8GFqHBA+32j91LDnrayuCFy57Ng8g8xIVCUcg4l5VdmeCjSPiFd ++eg== X-Gm-Message-State: AOAM530WaKnDDGjC+P7iP6bMbj66B18aw8ZDXcYTcj0e2fkkkpB52gE5 25j+mkw6nZBEwApG5IO54NLSew== X-Google-Smtp-Source: ABdhPJzVM8K9SqRkBkJTsngfKgDL4VmaVSYUQXiH7H8MNL+aHjQsM3ALrXO1gxyQkidZIfc39MlRFw== X-Received: by 2002:a17:90b:368b:: with SMTP id mj11mr601183pjb.79.1610519214310; Tue, 12 Jan 2021 22:26:54 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id k25sm1138241pfi.10.2021.01.12.22.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 22:26:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v2 0/4] target/arm: Fix sve pred_desc decoding Date: Tue, 12 Jan 2021 20:26:46 -1000 Message-Id: <20210113062650.593824-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 06:26:58 -0000 There was an inconsistency between encoding, which uses SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS. This happened to be ok, until e2e7168a214, which reduced the size of SIMD_OPRSZ_BITS, which lead to truncating all predicate vector lengths. Changes in v2: * Introduce and use PREDDESC field definitions, rather than abusing a different SIMD_* macro. r~ Richard Henderson (4): target/arm: Introduce PREDDESC field definitions target/arm: Update PFIRST, PNEXT for pred_desc target/arm: Update ZIP, UZP, TRN for pred_desc target/arm: Update REV, PUNPK for pred_desc target/arm/internals.h | 9 +++++++++ target/arm/sve_helper.c | 33 +++++++++++++++++---------------- target/arm/translate-sve.c | 31 +++++++++++-------------------- 3 files changed, 37 insertions(+), 36 deletions(-) -- 2.25.1 From MAILER-DAEMON Wed Jan 13 01:27:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzZcT-0003yc-AU for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 01:27:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzZcR-0003vJ-KC for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:26:59 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:33166) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzZcP-0007Dy-Po for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:26:59 -0500 Received: by mail-pl1-x635.google.com with SMTP id b8so515710plx.0 for ; Tue, 12 Jan 2021 22:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T7qIiA2TxHKspGb/1E//xY6dg2vkOf+MJQ6vthvW+io=; b=jJ6Ws/2w+p97yRAO18F8fzwrOqQQ6U4ayRQ1xdosoE51b9ptNJpM7p5cNKpPHd/Uaw iTKtxO7cjcceaLErOI3OJdGAv8vLmPaatOKufTaziBwKDNfucPj1TPsDtINPwc59Fk0p n6bl/g6vny2kgpSIy0elhzMF/6S8slJO2RgkKWv2Wf1CXD/1cO5KUwSgkYcQrcCL1RBZ UiTkzaOoEbVOSxaK7A+smRTJzrRbpoGTiQMRTcdH+q2Y9tscpgJ6awPjjZuRj5Ib8iFA v2Bf4wQOWP5A4Dd1rOo5dqtIsfrYPIjm051xp+bFYJrPdINZYfCe+ENPL4mwy6yM6M0m 2eDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T7qIiA2TxHKspGb/1E//xY6dg2vkOf+MJQ6vthvW+io=; b=EDIP7pXyVwmZAeaFtKGDGs+8m0jOQ8QLVASEDAMi39Rd6AX+6ZbGqnNKcAwGPilOsF QFjqqHlCMFxujjtGQnM6rk9O7dvgOf18CmEbQGkF6CB0UO8qLn1jL+cEhED1GU0E9Xd0 kR4vvl+GWsvV/kJSuWF+U1KWe0nw1kr3o1SLIVHUaXzSM++Si31O01hT5lrdJVVcsOpl buO6nlMuDdPUZucGORoKjwZRJoS4vln5ZvvHl7AGKxfqcYdtqe3jsDX9iyuF6uQMV7Th +YnYlJ2XLa/B9CKsiQ0HBXozOPynfwHr9EeGtR0BgDlKYeNLHS+AcG/2lxiOZmB01o5S wMLw== X-Gm-Message-State: AOAM530cP2AIwf+esqZLAswckcHnr14LjFVP4Zsx0JFAUkl6Nt52nAGW SuCg0anwo8C4SXRI9aALfUPnSw== X-Google-Smtp-Source: ABdhPJySOjoSdSkOddebQ9jRoh2vOew+nxXFmTuaY9O89tkQKiI5UR12RJ1uw7nTR59HoYsuuCJD9Q== X-Received: by 2002:a17:90b:128a:: with SMTP id fw10mr594858pjb.113.1610519216224; Tue, 12 Jan 2021 22:26:56 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id k25sm1138241pfi.10.2021.01.12.22.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 22:26:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v2 1/4] target/arm: Introduce PREDDESC field definitions Date: Tue, 12 Jan 2021 20:26:47 -1000 Message-Id: <20210113062650.593824-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113062650.593824-1-richard.henderson@linaro.org> References: <20210113062650.593824-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 06:26:59 -0000 SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/internals.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..73698587d6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1312,6 +1312,15 @@ void arm_log_exception(int idx); #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) +/* + * SVE predicates are 1/8 the size of SVE vectors, and cannot use + * the same simd_desc() encoding due to restrictions on size. + * Use these instead. + */ +FIELD(PREDDESC, OPRSZ, 0, 6) +FIELD(PREDDESC, ESZ, 6, 2) +FIELD(PREDDESC, DATA, 8, 24) + /* * The SVE simd_data field, for memory ops, contains either * rd (5 bits) or a shift count (2 bits). -- 2.25.1 From MAILER-DAEMON Wed Jan 13 01:27:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzZcU-00040N-23 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 01:27:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37360) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzZcT-0003yQ-44 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:01 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:41522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzZcR-0007Fi-Eu for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:00 -0500 Received: by mail-pl1-x634.google.com with SMTP id y8so498312plp.8 for ; Tue, 12 Jan 2021 22:26:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bymuml46Yty0XlvbocAimuoupZdaZklTevSIO7jJc+s=; b=SLvo5rb1waFxld5OxOq7nLR4coQIkwbEOsB7CG7Fchnh319qiSmJbHx9X6MgtCNS2A zKomWxBC6QjE8ytjGeCpJPUXVxrXj05Jllb84wuQdbM+1ELUeoF1/uSnwbtmGtuZRKK9 +MEQtFCGkKaVDKx1YGp5JjmwaUwYPTFB5VFriuhUuHujagT/Ust76mB+ziCq7kWRXbLh 5rtRFDCh2PHKoOc8n/5w/ZK1r78Pz/vXbHUwcQvEfBZei+8oXoPPBenQCaLWzQFTkKLJ SURrICOfrOSruaMQuRwyugYHKMsQaTJfKhb4djXeCjNU7koRE9X16QjWHK7MxmSqz9t2 ljXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bymuml46Yty0XlvbocAimuoupZdaZklTevSIO7jJc+s=; b=SyxsNaAHs+rjDtH3KDb1I1y3qTx+Ek3vQHtoaZLaVF5ME/4GOFj15gF5Ko3A7yS09P rzLQOCc5Bxlo9mWaxXJhFdVdsWacUDO+YUZWgUdIyxeDraXEYD46vf0URYSCH7FPYVpt kIba9ABNAFE6BhrESpAtqHd3R0NnO+lSYARhHhzAXQmFxcnaO6eFdTFJkulYetZ+MC64 U3EYU4hz1mZOiZpaI/YMqKUFljRtiO2HbLCpfhc0499YELa3oYNJ1SII6JYfXO4an7x9 9w+JHpiaN22s6DrDFlluvRpBO/o97zec36ay19umQIUniCGKnbAN2yzsBAavgadEL9da 30hg== X-Gm-Message-State: AOAM531n4L1gHLdEtAUX7XwUkuHrUFWgztFJJ7U+03TLjHr6/rfzn67t KSQkVt6YeGpSbIyi7ufbly/c8A== X-Google-Smtp-Source: ABdhPJxI9KXtJOV/Ozelg9E1nhe3CmtOiXU6WGaN1dmmo0Lw/n3+0uVUVqLWYSQ2s45SjSbx2i2qKw== X-Received: by 2002:a17:90a:4dcd:: with SMTP id r13mr652743pjl.74.1610519218183; Tue, 12 Jan 2021 22:26:58 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id k25sm1138241pfi.10.2021.01.12.22.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 22:26:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v2 2/4] target/arm: Update PFIRST, PNEXT for pred_desc Date: Tue, 12 Jan 2021 20:26:48 -1000 Message-Id: <20210113062650.593824-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113062650.593824-1-richard.henderson@linaro.org> References: <20210113062650.593824-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 06:27:01 -0000 These two were odd, in that do_pfirst_pnext passed the count of 64-bit words rather than bytes. Change to pass the standard pred_full_reg_size to avoid confusion. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 7 ++++--- target/arm/translate-sve.c | 6 +++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 5f037c3a8f..ff01851bf2 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -889,8 +889,9 @@ static intptr_t last_active_element(uint64_t *g, intptr_t words, intptr_t esz) return (intptr_t)-1 << esz; } -uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words) +uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t pred_desc) { + intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8); uint32_t flags = PREDTEST_INIT; uint64_t *d = vd, *g = vg; intptr_t i = 0; @@ -914,8 +915,8 @@ uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words) uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc) { - intptr_t words = extract32(pred_desc, 0, SIMD_OPRSZ_BITS); - intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8); + intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); uint32_t flags = PREDTEST_INIT; uint64_t *d = vd, *g = vg, esz_mask; intptr_t i, next; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0c3a6d2121..efcb646f72 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1494,10 +1494,10 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, TCGv_ptr t_pd = tcg_temp_new_ptr(); TCGv_ptr t_pg = tcg_temp_new_ptr(); TCGv_i32 t; - unsigned desc; + unsigned desc = 0; - desc = DIV_ROUND_UP(pred_full_reg_size(s), 8); - desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); + desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); -- 2.25.1 From MAILER-DAEMON Wed Jan 13 01:27:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzZcW-00047l-Nd for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 01:27:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzZcV-000440-6p for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:03 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:37456) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzZcT-0007GG-BI for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:02 -0500 Received: by mail-pl1-x62f.google.com with SMTP id be12so506551plb.4 for ; Tue, 12 Jan 2021 22:27:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x4WrRc9ij8plFlXKBhz8CZ+MgZnj8Yfv6pjE6AqRZ6g=; b=nJM4gqhYgtmaC3mmYOj0THdAIZ6sxtk2gDtMpmCvv9saWJ8axHkBLwuy05tR62vK6W 63x+Df30JNOouWr2GWWZ/RdNg4d9NpTeLif/hK/tXXPKnZQLwsQt95JFUzdUtAzsoPpJ J6t8FUKPdxliN1DChKYdt0B8yJLLRgVq3SzKyxBt7J31bc3ELg4XN0ZRtbryiq1xyPSe 0ehhpWHuwRzaHWn/MGMt0VDvYDLMRTdTpfbPQ/xVl6Hce6y/Um7Z1fk+HXFYCkOo4th1 vP+naLf/UFicY5yPbfP8g58GGBS4idSC1bBfweJVBEgqVE1TLF7AQ0hTQh58tRBXfD5A e7eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x4WrRc9ij8plFlXKBhz8CZ+MgZnj8Yfv6pjE6AqRZ6g=; b=bnDAo4mFyUhsuRRXCv0MxMGX1FvRtZU7Sh8eA2Gc9UcsYp8Kka8RfRVfNdjN8hV3j2 68vKThw3V1wTkm9ekIP6ZgiZjsbPK68d8m/gZF02xeIjd7i5j3B2o61TJsdjlEv4ihmZ +q+nEIluCHWUYok53fgxbjbh8bWsKuOIbELnQNffYBSXOtJ9rfAG4YaWa9iLyf2WGyMJ 94Es+o0EQ2YQyo8+6Pnkb6Xkix/pm3OWtzFFaABybS46IdChXf3CC0h1CtdwnR2KWKHN 7gVlZtfU2CkjRSComGViTfCZP7JpoDibBlrjdEz0Zkdnfhjew6TH4kgTGVyASFcAuj28 mUqg== X-Gm-Message-State: AOAM5325zg8DvDPm9lGXcsAky6GwS7CIwSOdVgBqQC1uE3IE1aWV49BW 7tcPWvV8DXeTqng5d2JDzH32rg== X-Google-Smtp-Source: ABdhPJxy0KsDEXRmX4mT65DbzB0XfknfDLfIsoxd5Rbdv868LMqBAZ8af3Ee8Jvqzoqz6eiLj4RNaQ== X-Received: by 2002:a17:90a:9304:: with SMTP id p4mr620365pjo.220.1610519220050; Tue, 12 Jan 2021 22:27:00 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id k25sm1138241pfi.10.2021.01.12.22.26.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 22:26:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v2 3/4] target/arm: Update ZIP, UZP, TRN for pred_desc Date: Tue, 12 Jan 2021 20:26:49 -1000 Message-Id: <20210113062650.593824-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113062650.593824-1-richard.henderson@linaro.org> References: <20210113062650.593824-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 06:27:03 -0000 Update all users of do_perm_pred3 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 18 +++++++++--------- target/arm/translate-sve.c | 12 ++++-------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ff01851bf2..7eec4b6b73 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1868,9 +1868,9 @@ static uint64_t compress_bits(uint64_t x, int n) void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); - intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); + intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA); uint64_t *d = vd; intptr_t i; @@ -1929,9 +1929,9 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); - int odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz; + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); + int odd = FIELD_EX32(pred_desc, PREDDESC, DATA) << esz; uint64_t *d = vd, *n = vn, *m = vm; uint64_t l, h; intptr_t i; @@ -1986,9 +1986,9 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - uintptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); - bool odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); + int odd = FIELD_EX32(pred_desc, PREDDESC, DATA); uint64_t *d = vd, *n = vn, *m = vm; uint64_t mask; int shr, shl; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index efcb646f72..0baca176a0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2110,19 +2110,15 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, unsigned vsz = pred_full_reg_size(s); - /* Predicate sizes may be smaller and cannot use simd_desc. - We cannot round up, as we do elsewhere, because we need - the exact size for ZIP2 and REV. We retain the style for - the other helpers for consistency. */ TCGv_ptr t_d = tcg_temp_new_ptr(); TCGv_ptr t_n = tcg_temp_new_ptr(); TCGv_ptr t_m = tcg_temp_new_ptr(); TCGv_i32 t_desc; - int desc; + uint32_t desc = 0; - desc = vsz - 2; - desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); - desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); + desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); + desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); + desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); -- 2.25.1 From MAILER-DAEMON Wed Jan 13 01:27:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzZcZ-0004Ez-5H for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 01:27:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzZcX-00049n-AK for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:05 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:41026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzZcV-0007I2-Am for qemu-arm@nongnu.org; Wed, 13 Jan 2021 01:27:05 -0500 Received: by mail-pg1-x52a.google.com with SMTP id i7so845765pgc.8 for ; Tue, 12 Jan 2021 22:27:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YbAy4KVm8LZdofZcsXyEMftLzbs/6FHl1IDz/kaEGZA=; b=giEqWeegyT3S3mL7WsKtn/HvThYJUn9jz6oSMART99yy/X+/8XiS47SFV8WBRJVsYc 1Vm4hMLZYqfikoNB3rCtI42MHrA5loVkfhMf7TFRI6GWzqcTfY0/wyAPrgZhpTTm/JLb gRaZGmIIgJhDMSnNAvY8XeLV8DlEisk31m7kQH+94HrfzByzLnrJ/X9UuNhtVryRQCZH J7ToapLEWf1CgCRLaxMaZTPlWacynJvtRHwFnjPOzkpmpK9mxOPhpPpQajE/uU7kBUjg tJknfaUWa9F4FE3TU4CCmzlpy2EnGomR0GLG2D2ZYEex6Z1mVt6JGY/b6XGeXwMQ3orU hLNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YbAy4KVm8LZdofZcsXyEMftLzbs/6FHl1IDz/kaEGZA=; b=uQ2/OkbWCr7Z9GGPBKAzrGk9cCQOYyxscO0XznQqCFrLaDNJ72zfBeAwoeAAM8slkO EvSwEKOiYYgctvtrqfjoCyl1i0WjRd2E2iOBegJCyHiork1DOdpiN9Ortg/UDbSS2G1q N9nHfBfC2hwgFEoIcnJmlf1yUU60dplkS5hFKmUrtlpmMKXMgUV1DdIdzVoKTcCPEkrz UiIR10Z9oF8XeAf7L4KRs05VrB7cGZ5CQQyrOhdqYUBxdiS7zlYNFVGVfnoa/TXJRxsK xQnKruKiPePI1c6reyC+iFgbV8yJIuBh8zduds34eU8Hta187nkvrAhyHYTg6rIqMFvN pd0Q== X-Gm-Message-State: AOAM531CWeOoTPoCSXDltsDz/VE5v81yNtIA0fNMTxSb+75xcufFDuJi UCl47vlrV45ITrnCQsJB4nduLQ== X-Google-Smtp-Source: ABdhPJy2pBBdBDSlTCgHd/B7yU/yWlMGb5HTUak/svwLAal8kfBk1Xw13vos9Uh16vlIVMfE5sTQ8Q== X-Received: by 2002:aa7:904b:0:b029:19e:c8a5:5154 with SMTP id n11-20020aa7904b0000b029019ec8a55154mr640584pfo.41.1610519221930; Tue, 12 Jan 2021 22:27:01 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id k25sm1138241pfi.10.2021.01.12.22.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jan 2021 22:27:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v2 4/4] target/arm: Update REV, PUNPK for pred_desc Date: Tue, 12 Jan 2021 20:26:50 -1000 Message-Id: <20210113062650.593824-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113062650.593824-1-richard.henderson@linaro.org> References: <20210113062650.593824-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 06:27:05 -0000 Update all users of do_perm_pred2 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Buglink: https://bugs.launchpad.net/bugs/1908551 Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 8 ++++---- target/arm/translate-sve.c | 13 ++++--------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 7eec4b6b73..844db08bd5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2036,8 +2036,8 @@ static uint8_t reverse_bits_8(uint8_t x, int n) void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); intptr_t i, oprsz_2 = oprsz / 2; if (oprsz <= 8) { @@ -2066,8 +2066,8 @@ void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA); uint64_t *d = vd; intptr_t i; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0baca176a0..27402af23c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2145,19 +2145,14 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, TCGv_ptr t_d = tcg_temp_new_ptr(); TCGv_ptr t_n = tcg_temp_new_ptr(); TCGv_i32 t_desc; - int desc; + uint32_t desc = 0; tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); - /* Predicate sizes may be smaller and cannot use simd_desc. - We cannot round up, as we do elsewhere, because we need - the exact size for ZIP2 and REV. We retain the style for - the other helpers for consistency. */ - - desc = vsz - 2; - desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); - desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); + desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); + desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); + desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); t_desc = tcg_const_i32(desc); fn(t_d, t_n, t_desc); -- 2.25.1 From MAILER-DAEMON Wed Jan 13 02:31:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzacZ-0003rg-D6 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 02:31:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzacS-0003qf-QO for qemu-arm@nongnu.org; Wed, 13 Jan 2021 02:31:06 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:53140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzacO-0002xF-DE for qemu-arm@nongnu.org; Wed, 13 Jan 2021 02:31:04 -0500 Received: by mail-pj1-x1030.google.com with SMTP id v1so585394pjr.2 for ; Tue, 12 Jan 2021 23:30:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=36m8pz5TZ5Bfe65O1IhCqd0gYUP+B+Tsz+AunDd5Ju4=; b=xF7IiyL4ZIuHsi81vo/VLwpDSOi3dpwel9dbOYfR+3pU8k0GoLyaIGy8/LwdF1iatr 7qQTsRJyr60EdkPHFKgY4V7xx13DWMYZJA3wo7QQP2poDUx2wwZVRibyjKHlQLhcrfHE BHX3iYt8dyC6AdPj9PpwKAmZ9Sg4aZMGRr9wD3Er/zy5Zp4r7D7edHagJC7rxxsmDw2Z d+ZnLahBOyyKOVx36UNNv6AqAC8bvId8jYWHFOxOqea04S9tWK++Dn53zba3jS3JOtuK KhJp6XtwHuimQ+v53APidKdj8AziEH/HZzOUZsosqkFxFThISzDnuYBn9NTbVMDs87cG M/7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=36m8pz5TZ5Bfe65O1IhCqd0gYUP+B+Tsz+AunDd5Ju4=; b=UrAgDaouQt/anfrLy7IUtFZ1xv3dSYDP6hw6Imk1ca7UCBr/NWrpwzFCgXOsjLUAzB baqybDQI/ZLzFAMEnJPDqh867TlYQ9Mu0l8O8uGzYTmA9XeYhbJUDSBgAnH/yG0WJUIq FqVse5lab+JmOHMW6SkBMJUf8+GMWn42vLKpxlsMuWNOVmF0Sycqb0Lqp4d2QlqTjlsv giIf2Tk+hvegklWBBzdivmJFZxECv51ra5f9LIMtle0DuSs5IGrp5pUI5wWe7zA5coNf IHikBAIvUxXcuHpPc069+L8V5hmPe1WDJaICAuHa6e0ifWeCaZP1hjArCLZn/zPJWkYo IC2A== X-Gm-Message-State: AOAM532/qQpAHqXMPigPdNH4aBXpo8wWHxiWX4ewsM93zxQeH7SIy+aC rCHsA1OvX/uB1IVc9SXQD4zp+u0dAXNdypCpk8jhjA== X-Google-Smtp-Source: ABdhPJyg5zEVsk2ezTbnKQlXgQHzlWqR5mbl+aILcp7/fEoeF/DDgdjqRmPCOcp6ZX/qk2Gxo6j/SEXaTYPxwohfVko= X-Received: by 2002:a17:90a:8a8b:: with SMTP id x11mr924820pjn.54.1610523058246; Tue, 12 Jan 2021 23:30:58 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> In-Reply-To: <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> From: Maxim Uvarov Date: Wed, 13 Jan 2021 10:30:47 +0300 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Andrew Jones Cc: Peter Maydell , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=maxim.uvarov@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 07:31:06 -0000 - the same size for secure and non secure gpio. Arm doc says that secure memory is also split on 4k pages. So one page here has to be ok. - will add dtb. - I think then less options is better. So I will remove vmc->secure_gpio flag and keep only vmc flag. Regards, Maxim. On Tue, 12 Jan 2021 at 19:28, Andrew Jones wrote: > > On Tue, Jan 12, 2021 at 11:25:30AM -0500, Andrew Jones wrote: > > On Tue, Jan 12, 2021 at 04:00:23PM +0000, Peter Maydell wrote: > > > On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote: > > > > > > > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > > > > > Add secure pl061 for reset/power down machine from > > > > > the secure world (Arm Trusted Firmware). Connect it > > > > > with gpio-pwr driver. > > > > > > > > + /* connect secure pl061 to gpio-pwr */ > > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > > > > > > > I don't know anything about secure world, but it seems odd that we don't > > > > need to add anything to the DTB. > > > > > > We should be adding something to the DTB, yes. Look at > > > how create_uart() does this -- you set the 'status' and > > > 'secure-status' properties to indicate that the device is > > > secure-world only. > > > > > > > > > > > > > > + if (vmc->no_secure_gpio) { > > > > > + vms->secure_gpio = false; > > > > > + } else { > > > > > + vms->secure_gpio = true; > > > > > + } > > > > > > > > nit: vms->secure_gpio = !vmc->no_secure_gpio > > > > > > > > But do we even need vms->secure_gpio? Why not just do > > > > > > > > if (vms->secure && !vmc->no_secure_gpio) { > > > > create_gpio_secure(vms, secure_sysmem); > > > > } > > > > > > > > in machvirt_init() ? > > > > > > We're just following the same pattern as vmc->no_its/vms->its, > > > aren't we ? > > > > > > > 'its' is a property that can be changed on the command line. Unless > > we want to be able to manage 'secure-gpio' separately from 'secure', > > then I think vmc->its plus 'secure' should be sufficient. We don't > > I meant to write 'vmc->no_secure_gpio and vms->secure' here. > > Thanks, > drew > > > always need both vmc and vms state, see 'no_ged'. > > > > Thanks, > > drew > From MAILER-DAEMON Wed Jan 13 02:53:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzaxu-0001sV-Fz for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 02:53:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzaxr-0001s7-Lk; Wed, 13 Jan 2021 02:53:11 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzaxp-0004qW-Ki; Wed, 13 Jan 2021 02:53:11 -0500 Received: by mail-wm1-x32e.google.com with SMTP id e25so688394wme.0; Tue, 12 Jan 2021 23:53:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Y7TP/ToyRctzKrumSjXsq0lzD4QST81QsFkYS/qUk1M=; b=j92ieSnaEEvlHyUBI5mRV2vLmjSAcq2O8hXq4Dlyie3W1Llvkoxskfd0R4H1NtieuI 8ORFqT67mCkFv65Gv4fZ4qYGJ/4lETB9D2OT0e2IqjC0Tats3NaOOMNW8qFFhUIp4K4q PSnkVUNbcTEc9WF3f1bL3PGEe/+wDze5RMAxnBeBFBDAhrudmgIG7bRtkQ1OY7biC4Gm J9Q9SqU1wQq7pK0loOowk44fT+ukE1lKr0I4/MUjp1K0TUSU/JN3RKNWtU1AmcC+rbsJ 5JyQo0zo8WCXhIL93erhgqYbe9zeaJN5kfzSwpGLmiE+WKzkSpiQ6e1V8du3qyTLCmOM blJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Y7TP/ToyRctzKrumSjXsq0lzD4QST81QsFkYS/qUk1M=; b=TIGKDtg0o+EPKRH4Ez4z96zHOwP67aeX3n7ACxwXa6ucmq2/V4gJ6pSRy5LoAFq+Ea l/IlYMfoDzmy0eViCqDc3CDVbcTyLgpBj1KJBhV/mmSmqkT/xqFXKKXi4mbm1KFobM3e 2d8XskdJlbGIy4YG+CH506X/joh/680ABoRx3LkymRGlVXUFIygyuhPYhd0LhjL+zT2+ x3yJPTyqQagn0b8FjAFgt2a5SqtKo2LsHHrTZ1jhe3MGv1Q04nRkTm7XYQnM82K6ttbI 6cJV5jqBSgUnBo0pVeyt60DqdIpW9yJMnjFjfLisxARGk7P5ncuFFf5W5J52oJRkhO1H cbaA== X-Gm-Message-State: AOAM531XqBnwyQAAxSdVsX5LLrCxajRflLwXpCghmBARN/wWZenSLBTJ xi3peKWikiDempRn+53MK98= X-Google-Smtp-Source: ABdhPJz1BUdSbH/XaJVzG+NwJw9eAidwFoO46E20/hZU9Zr5twvFH6diyHW0+PuQWK5yq7bHeZbX8Q== X-Received: by 2002:a1c:6a10:: with SMTP id f16mr893542wmc.106.1610524387785; Tue, 12 Jan 2021 23:53:07 -0800 (PST) Received: from [192.168.1.36] (190.red-83-57-173.dynamicip.rima-tde.net. [83.57.173.190]) by smtp.gmail.com with ESMTPSA id g14sm1610957wrd.32.2021.01.12.23.53.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jan 2021 23:53:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Bin Meng Cc: Peter Maydell , Bin Meng , Xuzhou Cheng , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210112183529.2011863-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> Date: Wed, 13 Jan 2021 08:53:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 07:53:11 -0000 Hi Ben, On 1/13/21 4:29 AM, Bin Meng wrote: > On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daudé wrote: >> >> Hi, >> >> As it is sometimes harder for me to express myself in plain >> English, I found it easier to write the patches I was thinking >> about. I know this doesn't scale. >> >> So this is how I understand the ecSPI reset works, after >> looking at the IMX6DQRM.pdf datasheet. >> >> This is a respin of Ben's v5 series [*]. >> Tagged RFC because I have not tested it :) > > Unfortunately this series breaks SPI flash testing under both U-Boot > and VxWorks 7. Thanks for testing :) Can you provide the binary tested and the command line used? At least one, so I can have a look. >> Sometimes changing device reset to better match hardware gives >> trouble when using '-kernel ...' because there is no bootloader >> setting the device in the state Linux expects it. >> > > Given most of the new changes in this RFC series are clean-ups, I > suggest we apply the v5 series unless there is anything seriously > wrong in v5, IOW, don't fix it unless it's broken. > > Thoughts? Up to the maintainer :) The IMX6DQRM datasheet is available here: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6DQ-Reference-Manual-IMX6DQRM-R2-Part-1/ta-p/1115983 https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6DQ-Reference-Manual-IMX6DQRM-R2-Part-2/ta-p/1118510 Regards, Phil. From MAILER-DAEMON Wed Jan 13 04:34:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzcXt-0001D9-If for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 04:34:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzcXr-0001BI-2R for qemu-arm@nongnu.org; Wed, 13 Jan 2021 04:34:27 -0500 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]:47030) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzcXp-0004Gh-4H for qemu-arm@nongnu.org; Wed, 13 Jan 2021 04:34:26 -0500 Received: by mail-lf1-x136.google.com with SMTP id o10so1730525lfl.13 for ; Wed, 13 Jan 2021 01:34:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=62h8W8c/MHOTaJfr80jgkPG/YCUcGgeW9/I/zkhkDxM=; b=NisRE+eqax1f2DZOLE5wsMhO+ff1NkakrDlT0cAlWICNti3Smfh8X6hjFtm+W6d/r8 KY7EDWjgJOb/ggOPf5zGr2KruAQktC9bhUxurrpcbIKQnI3NfRDR6zF4ALE2GqcJ99uN uxOQJqxH5RQg5j0eiRlCljKxXi41Xcj/sJHfhrSM1WHoTxIsI9QmqtZ2cgER/6AwpQXf USXj+MHMnmbzB2njB2DI6oLjxHLEJi2W5L1RdoQ3fs+R/ek4aVSjybDf29awjNrKzKdY 7WXjJix63lPxLL/qQ/g+Y/S/0NlXtwCwP63vE/Khk1rss1+VuEBAtI80WINuveU936m6 GUIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=62h8W8c/MHOTaJfr80jgkPG/YCUcGgeW9/I/zkhkDxM=; b=Fc8dEkSry6C7lAD5NIVy7QPb3BXbdFdQMzIOpJVCqTD2HCBtAXyaJpMeMrIAHE/czD vD3Dfb1JbYlAHWUKn0hakg2n1Jytjks/HTWIol0QV8Digq6b8VMxXe6j6aPaf71yJz0L nF0gLeH9HDswhCA2gmd9vAOi/RS5DtDKEY2D4N7QtrBceqjY2NKl1OWFk0BbYhO8GnZs lhDrbtaZbHMM/5S+hLX7N4GMSHRUbQDQovVFdvZ5TczKyBB9kAxjFnnodqUKXSI+QfUO Ly5VRum6Fx3UQLUZuShSh8PDiXqrgGtrEyubgvp9epblm8gNYphZU9QzlukKYqZurzc7 pIQQ== X-Gm-Message-State: AOAM5316s4Gk6llh+WIZARCY1T47o1t0snu3GnoNe5PpN5uSfjTivNNJ Ajs9SpknEeFi12yPDT30/du4beoKempnKw== X-Google-Smtp-Source: ABdhPJyEGKCrplsp30jUVIWpMASr6Fa8A8+AvXH5Kr271Va7lq2w6Ugdc9o7sfUeVOMWJ3vlWWtNvQ== X-Received: by 2002:a19:770c:: with SMTP id s12mr467248lfc.367.1610530462723; Wed, 13 Jan 2021 01:34:22 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id c3sm127472ljk.88.2021.01.13.01.34.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 01:34:22 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv5 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Wed, 13 Jan 2021 12:34:15 +0300 Message-Id: <20210113093417.11606-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210113093417.11606-1-maxim.uvarov@linaro.org> References: <20210113093417.11606-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 09:34:27 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov Reviewed-by: Hao Wu --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..8ed8d5d24f --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Wed Jan 13 04:34:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzcXv-0001HP-0Y for mharc-qemu-arm@gnu.org; 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Wed, 13 Jan 2021 01:34:20 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv5 0/3] arm-virt: add secure pl061 for reset/power down Date: Wed, 13 Jan 2021 12:34:14 +0300 Message-Id: <20210113093417.11606-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 09:34:27 -0000 v5: - removed vms flag, added fdt (Andrew Jones) - added patch3 to combine secure and non secure pl061. It has to be more easy to review if this changes are in the separate patch. v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/dd4401d8eb8e0f3018b335b81ce7a96d6cb16d0f Previus discussion for reboot issue was here: https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html Maxim Uvarov (3): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: add secure pl061 for reset/power down arm-virt: combine code for secure and non secure pl061 hw/arm/Kconfig | 1 + hw/arm/virt.c | 118 +++++++++++++++++++++++++++++++++++------- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 2 + 6 files changed, 175 insertions(+), 20 deletions(-) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Wed Jan 13 04:34:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzcXv-0001IA-73 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 04:34:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzcXr-0001BK-D5 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 04:34:29 -0500 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]:39682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzcXp-0004Gt-PY for qemu-arm@nongnu.org; Wed, 13 Jan 2021 04:34:27 -0500 Received: by mail-lj1-x22f.google.com with SMTP id b10so1773680ljp.6 for ; Wed, 13 Jan 2021 01:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fFyVX6J1ILAOgA0Eulrp2aeUvo2NLh3SrrXtPKRjlKw=; b=SRuAK+UvGGY611lzwj/Yq2QDDWB7JD4IDOk3uNMol1xARqXT+7/ochCNJd5VkLfBF+ FeWJ7EsYFTt6wE84YSjfbS6rV4fJz6ZnvZFr6KlkcP8AylWmSR9hcKGCWOgEaCVrj2mt l2CWaOLO5nOa92C4LILviqDNurHJXRFrGNEMv3aYjDcLEVz+VxiSwI4EhG/20vbA+34X 28TO1juult7kci9UHqzA/HEG4sfmkedQRJUvibMa49w0orQUoeieFOMgSigD4oLVptZA jDR+zs7pnbquxj6Z9t5d/Kbf5tezOnWv4yYP7s9O94rruDceIGSp3Xm/3e0Y7Xbn+6nT pB9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fFyVX6J1ILAOgA0Eulrp2aeUvo2NLh3SrrXtPKRjlKw=; b=MFl4rZ9Q4Bw+lhJGAK5ClTJkrdRzelAGLtVcRScPauKNAd92l5oU4IDVW+gAsNKfN/ LM1YlGkmc8QSMrNMrKw7jSgtbiNo+0CAXNNAMkhjAwRuwBpFaGgndHf+e/QhKGB4i4tr rdzUtEhy/J+37Y7smFdUNCCZx1nHa/GcBSit9bh+9o1GApzqYlZBl4xhBxQqGNK/BBlw md0/1+2nxTrjwLIiVtZJmLTM4pbBdmIJnPwF8CZ4RsDPfbrmxvCQwaSZRznF77y0eBW0 jyybaYdz6+PzECun54ry3I89O538aCA4J7GV20VRyYBg1nyQQVg4zFVw/4LfxZTPhgxm ZA/w== X-Gm-Message-State: AOAM530w0NVKWU29vm70n22tctOdr+2DCVyN6LBeLUSsnWXnQx1NTix8 28n/TFi5pWybb6Q8dEClU2VVHxX7z5okxg== X-Google-Smtp-Source: ABdhPJyUXkhn4inSYJiYDhabNYnEpxh1Ho96ICBlLMkqiFOezYPahX+EHPxYOaRd/sUhh/gyHg/Fuw== X-Received: by 2002:a2e:9214:: with SMTP id k20mr539848ljg.45.1610530463883; Wed, 13 Jan 2021 01:34:23 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id c3sm127472ljk.88.2021.01.13.01.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 01:34:23 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv5 2/3] arm-virt: add secure pl061 for reset/power down Date: Wed, 13 Jan 2021 12:34:16 +0300 Message-Id: <20210113093417.11606-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210113093417.11606-1-maxim.uvarov@linaro.org> References: <20210113093417.11606-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 09:34:29 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 37 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..d38a7d5d2f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -147,6 +147,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, + [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, @@ -864,6 +865,32 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } +#define ATF_GPIO_POWEROFF 3 +#define ATF_GPIO_REBOOT 4 + +static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) +{ + DeviceState *gpio_pwr_dev; + SysBusDevice *s; + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; + DeviceState *pl061_dev; + + /* Secure pl061 */ + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); +} + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -1993,6 +2020,10 @@ static void machvirt_init(MachineState *machine) create_gpio(vms); } + if (vms->secure && !vmc->no_secure_gpio) { + create_gpio_secure(vms, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2608,8 +2639,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..6f6c85ffcf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { -- 2.17.1 From MAILER-DAEMON Wed Jan 13 04:34:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzcXv-0001Im-DX for mharc-qemu-arm@gnu.org; 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Wed, 13 Jan 2021 01:34:24 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv5 3/3] arm-virt: combine code for secure and non secure pl061 Date: Wed, 13 Jan 2021 12:34:17 +0300 Message-Id: <20210113093417.11606-4-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210113093417.11606-1-maxim.uvarov@linaro.org> References: <20210113093417.11606-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 09:34:30 -0000 Combine code for secure and non secure pl061 (gpio) with refining fdt creation. Signed-off-by: Maxim Uvarov --- hw/arm/virt.c | 122 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 83 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d38a7d5d2f..97b8d2fe9a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -821,35 +821,13 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms) +static void create_gpio_keys(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) { - char *nodename; - DeviceState *pl061_dev; - hwaddr base = vms->memmap[VIRT_GPIO].base; - hwaddr size = vms->memmap[VIRT_GPIO].size; - int irq = vms->irqmap[VIRT_GPIO]; - const char compat[] = "arm,pl061\0arm,primecell"; - - pl061_dev = sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); - - uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); - nodename = g_strdup_printf("/pl061@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", - 2, base, 2, size); - qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); - qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); - qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); - gpio_key_dev = sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); @@ -862,24 +840,16 @@ static void create_gpio(const VirtMachineState *vms) KEY_POWER); qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", "gpios", phandle, 3, 0); - g_free(nodename); } #define ATF_GPIO_POWEROFF 3 #define ATF_GPIO_REBOOT 4 -static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) +static void create_gpio_pwr(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) { DeviceState *gpio_pwr_dev; - SysBusDevice *s; - hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; - DeviceState *pl061_dev; - - /* Secure pl061 */ - pl061_dev = qdev_new("pl061"); - s = SYS_BUS_DEVICE(pl061_dev); - sysbus_realize_and_unref(s, &error_fatal); - memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); /* gpio-pwr */ gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); @@ -889,8 +859,82 @@ static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", + "label", "GPIO PWR Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", + ATF_GPIO_POWEROFF); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", + "gpios", phandle, 3, 0); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", + "label", "GPIO PWR Reboot"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", + ATF_GPIO_REBOOT); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", + "gpios", phandle, 3, 0); +} + +static void create_gpio_devices(const VirtMachineState *vms, int gpio, + MemoryRegion *mem) +{ + char *nodename; + DeviceState *pl061_dev; + hwaddr base = vms->memmap[gpio].base; + hwaddr size = vms->memmap[gpio].size; + int irq = vms->irqmap[gpio]; + const char compat[] = "arm,pl061\0arm,primecell"; + SysBusDevice *s; + + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); + + uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); + nodename = g_strdup_printf("/pl061@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); + qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); + + if (gpio == VIRT_GPIO) { + qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); + } else { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); + + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", + nodename); + } + g_free(nodename); + + /* Child gpio devices */ + if (gpio == VIRT_GPIO) { + create_gpio_keys(vms, pl061_dev, phandle); + } else { + create_gpio_pwr(vms, pl061_dev, phandle); + } } + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -2017,11 +2061,11 @@ static void machvirt_init(MachineState *machine) if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms); + create_gpio_devices(vms, VIRT_GPIO, sysmem); } if (vms->secure && !vmc->no_secure_gpio) { - create_gpio_secure(vms, secure_sysmem); + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); } /* connect powerdown request */ -- 2.17.1 From MAILER-DAEMON Wed Jan 13 05:20:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzdG3-0004t5-8l for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 05:20:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzdG1-0004ss-39; Wed, 13 Jan 2021 05:20:05 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:46774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzdFx-0000qv-SI; Wed, 13 Jan 2021 05:20:04 -0500 Received: from [192.168.1.83] (lfbn-lyo-1-486-109.w2-7.abo.wanadoo.fr [2.7.75.109]) by beetle.greensocs.com (Postfix) with ESMTPSA id 7AB7921E3B; Wed, 13 Jan 2021 10:19:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1610533196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aLXYeLa2qrtOGMEr8vI1KvyUS/2WSXxXaJJKCFM8uGY=; b=jctQhDap/PIC7T8feNjXle7ZfgxPWYLty85B77xo802RnJxTBmhKp4dPPPdse/h4pnNZAb dW2zkca0T7CSXS85oodRbF0b12GpmgFvjzW4BzzScRK69sR/K/FmUerAL+v/oFypD33iSA Xvf/WIsMZFvLPCP4ZYpTD+1uzOAiJJM= Subject: Re: [PATCH] Initialize Zynq7000 UART clocks on reset To: Peter Maydell , Michael Peter Cc: "Edgar E. Iglesias" , qemu-arm , "qemu-devel@nongnu.org" , Alistair Francis References: From: Damien Hedde Message-ID: <15fc51bf-1473-2808-583e-c58eb1620577@greensocs.com> Date: Wed, 13 Jan 2021 11:19:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US-large Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 10:20:05 -0000 This is ok but I'm afraid we may end up doing this kind of thing in a lot of devices. So maybe we should consider changing the behavior of device_is_in_reset() so that it returns false in the reset-exit case. What do you think ? (I've a patch for this, which make this one useless) But this patch does not harm so, anyway: Reviewed-by: Damien Hedde On 1/7/21 9:00 PM, Peter Maydell wrote: > Alistair/Edgar/Damien -- could I get a review from one of you > for this Xilinx clock-gen related patch, please? > > thanks > -- PMM > > On Tue, 24 Nov 2020 at 18:54, Michael Peter > wrote: >> >> Pass an additional argument to zynq_slcr_compute_clocks that indicates whether an reset-exit condition >> applies. If called from zynq_slcr_reset_exit, external clocks are assumed to be active, even if the >> device state indicates a reset state. >> >> Signed-off-by: Michael Peter >> --- >> hw/misc/zynq_slcr.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c >> index a2b28019e3..073122b934 100644 >> --- a/hw/misc/zynq_slcr.c >> +++ b/hw/misc/zynq_slcr.c >> @@ -269,12 +269,12 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], >> * But do not propagate them further. Connected clocks >> * will not receive any updates (See zynq_slcr_compute_clocks()) >> */ >> -static void zynq_slcr_compute_clocks(ZynqSLCRState *s) >> +static void zynq_slcr_compute_clocks(ZynqSLCRState *s, bool ignore_reset) >> { >> uint64_t ps_clk = clock_get(s->ps_clk); >> >> /* consider outputs clocks are disabled while in reset */ >> - if (device_is_in_reset(DEVICE(s))) { >> + if (!ignore_reset && device_is_in_reset(DEVICE(s))) { >> ps_clk = 0; >> } >> >> @@ -305,7 +305,7 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) >> static void zynq_slcr_ps_clk_callback(void *opaque) >> { >> ZynqSLCRState *s = (ZynqSLCRState *) opaque; >> - zynq_slcr_compute_clocks(s); >> + zynq_slcr_compute_clocks(s, false); >> zynq_slcr_propagate_clocks(s); >> } >> >> @@ -410,7 +410,7 @@ static void zynq_slcr_reset_hold(Object *obj) >> ZynqSLCRState *s = ZYNQ_SLCR(obj); >> >> /* will disable all output clocks */ >> - zynq_slcr_compute_clocks(s); >> + zynq_slcr_compute_clocks(s, false); >> zynq_slcr_propagate_clocks(s); >> } >> >> @@ -419,7 +419,7 @@ static void zynq_slcr_reset_exit(Object *obj) >> ZynqSLCRState *s = ZYNQ_SLCR(obj); >> >> /* will compute output clocks according to ps_clk and registers */ >> - zynq_slcr_compute_clocks(s); >> + zynq_slcr_compute_clocks(s, true); >> zynq_slcr_propagate_clocks(s); >> } >> >> @@ -558,7 +558,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, >> case R_ARM_PLL_CTRL: >> case R_DDR_PLL_CTRL: >> case R_UART_CLK_CTRL: >> - zynq_slcr_compute_clocks(s); >> + zynq_slcr_compute_clocks(s, false); >> zynq_slcr_propagate_clocks(s); >> break; >> } >> -- >> 2.17.1 > From MAILER-DAEMON Wed Jan 13 06:57:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzelt-00085m-A9 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 06:57:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzels-00084c-Ac for qemu-arm@nongnu.org; Wed, 13 Jan 2021 06:57:04 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:40788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzeln-00056S-90 for qemu-arm@nongnu.org; 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Wed, 13 Jan 2021 11:56:52 +0000 (UTC) Received: from lws.brq.redhat.com (unknown [10.40.195.31]) by smtp.corp.redhat.com (Postfix) with ESMTPS id DD40F60CE0; Wed, 13 Jan 2021 11:56:47 +0000 (UTC) Date: Wed, 13 Jan 2021 12:56:44 +0100 From: Miroslav Rezanina To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Aleksandar Rikalo , Cornelia Huck , qemu-riscv@nongnu.org, Stefan Weil , Huacai Chen , Richard Henderson , Thomas Huth , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Palmer Dabbelt , Aurelien Jarno Subject: Re: [PATCH 3/5] tcg/s390: Hoist common argument loads in tcg_out_op() Message-ID: <20210113115644.bemac6oxc5243t4f@lws.brq.redhat.com> References: <20210111150114.1415930-1-f4bug@amsat.org> <20210111150114.1415930-4-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20210111150114.1415930-4-f4bug@amsat.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mrezanin@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=mrezanin@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 11:57:04 -0000 On Mon, Jan 11, 2021 at 04:01:12PM +0100, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > tcg/s390/tcg-target.c.inc | 252 ++++++++++++++++++-------------------- > 1 file changed, 122 insertions(+), 130 deletions(-) > > diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc > index d7ef0790556..74b2314c78a 100644 > --- a/tcg/s390/tcg-target.c.inc > +++ b/tcg/s390/tcg-target.c.inc > @@ -1732,15 +1732,23 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, > case glue(glue(INDEX_op_,x),_i64) > > static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > - const TCGArg *args, const int *const_args) > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > S390Opcode op, op2; > TCGArg a0, a1, a2; > + int c2, c3, c4; > + > + a0 = args[0]; > + a1 = args[1]; > + a2 = args[2]; > + c2 = const_args[2]; > + c3 = const_args[3]; > + c4 = const_args[4]; > Hi Philippe, why isn't c1 declared? You are using it in the code? > switch (opc) { > case INDEX_op_exit_tb: > /* Reuse the zeroing that exists for goto_ptr. */ > - a0 = args[0]; > if (a0 == 0) { > tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); > } else { > @@ -1750,7 +1758,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_goto_tb: > - a0 = args[0]; > if (s->tb_jmp_insn_offset) { > /* > * branch displacement must be aligned for atomic patching; > @@ -1784,7 +1791,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_goto_ptr: > - a0 = args[0]; > if (USE_REG_TB) { > tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); > } > @@ -1794,45 +1800,43 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > OP_32_64(ld8u): > /* ??? LLC (RXY format) is only present with the extended-immediate > facility, whereas LLGC is always present. */ > - tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LLGC, a0, a1, TCG_REG_NONE, a2); > break; > > OP_32_64(ld8s): > /* ??? LB is no smaller than LGB, so no point to using it. */ > - tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LGB, a0, a1, TCG_REG_NONE, a2); > break; > > OP_32_64(ld16u): > /* ??? LLH (RXY format) is only present with the extended-immediate > facility, whereas LLGH is always present. */ > - tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LLGH, a0, a1, TCG_REG_NONE, a2); > break; > > case INDEX_op_ld16s_i32: > - tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, RX_LH, RXY_LHY, a0, a1, TCG_REG_NONE, a2); > break; > > case INDEX_op_ld_i32: > - tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); > + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); > break; > > OP_32_64(st8): > - tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], > - TCG_REG_NONE, args[2]); > + tcg_out_mem(s, RX_STC, RXY_STCY, a0, a1, TCG_REG_NONE, a2); > break; > > OP_32_64(st16): > - tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], > - TCG_REG_NONE, args[2]); > + tcg_out_mem(s, RX_STH, RXY_STHY, a0, a1, TCG_REG_NONE, a2); > break; > > case INDEX_op_st_i32: > - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); > + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); > break; > > case INDEX_op_add_i32: > - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; > - if (const_args[2]) { > + a2 = (int32_t)a2; > + if (c2) { > do_addi_32: > if (a0 == a1) { > if (a2 == (int16_t)a2) { > @@ -1852,8 +1856,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > case INDEX_op_sub_i32: > - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; > - if (const_args[2]) { > + a2 = (int32_t)a2; > + if (c2) { > a2 = -a2; > goto do_addi_32; > } else if (a0 == a1) { > @@ -1864,8 +1868,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_and_i32: > - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; > - if (const_args[2]) { > + a2 = (uint32_t)a2; > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I32, a0, a1); > tgen_andi(s, TCG_TYPE_I32, a0, a2); > } else if (a0 == a1) { > @@ -1875,8 +1879,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > case INDEX_op_or_i32: > - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; > - if (const_args[2]) { > + a2 = (uint32_t)a2; > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I32, a0, a1); > tgen_ori(s, TCG_TYPE_I32, a0, a2); > } else if (a0 == a1) { > @@ -1886,30 +1890,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > case INDEX_op_xor_i32: > - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; > - if (const_args[2]) { > + a2 = (uint32_t)a2; > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I32, a0, a1); > tgen_xori(s, TCG_TYPE_I32, a0, a2); > } else if (a0 == a1) { > - tcg_out_insn(s, RR, XR, args[0], args[2]); > + tcg_out_insn(s, RR, XR, a0, a2); > } else { > tcg_out_insn(s, RRF, XRK, a0, a1, a2); > } > break; > > case INDEX_op_neg_i32: > - tcg_out_insn(s, RR, LCR, args[0], args[1]); > + tcg_out_insn(s, RR, LCR, a0, a1); > break; > > case INDEX_op_mul_i32: > - if (const_args[2]) { > - if ((int32_t)args[2] == (int16_t)args[2]) { > - tcg_out_insn(s, RI, MHI, args[0], args[2]); > + if (c2) { > + if ((int32_t)a2 == (int16_t)a2) { > + tcg_out_insn(s, RI, MHI, a0, a2); > } else { > - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); > + tcg_out_insn(s, RIL, MSFI, a0, a2); > } > } else { > - tcg_out_insn(s, RRE, MSR, args[0], args[2]); > + tcg_out_insn(s, RRE, MSR, a0, a2); > } > break; > > @@ -1924,16 +1928,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > op = RS_SLL; > op2 = RSY_SLLK; > do_shift32: > - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; > + a2 = (int32_t)a2; > if (a0 == a1) { > - if (const_args[2]) { > + if (c2) { > tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); > } else { > tcg_out_sh32(s, op, a0, a2, 0); > } > } else { > /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ > - if (const_args[2]) { > + if (c2) { > tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); > } else { > tcg_out_sh64(s, op2, a0, a1, a2, 0); > @@ -1951,112 +1955,108 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > > case INDEX_op_rotl_i32: > /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ > - if (const_args[2]) { > - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); > + if (c2) { > + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, a2); > } else { > - tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); > + tcg_out_sh64(s, RSY_RLL, a0, a1, a2, 0); > } > break; > case INDEX_op_rotr_i32: > - if (const_args[2]) { > - tcg_out_sh64(s, RSY_RLL, args[0], args[1], > - TCG_REG_NONE, (32 - args[2]) & 31); > + if (c2) { > + tcg_out_sh64(s, RSY_RLL, a0, a1, > + TCG_REG_NONE, (32 - a2) & 31); > } else { > - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); > - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); > + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); > + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_TMP0, 0); > } > break; > > case INDEX_op_ext8s_i32: > - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); > + tgen_ext8s(s, TCG_TYPE_I32, a0, a1); > break; > case INDEX_op_ext16s_i32: > - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); > + tgen_ext16s(s, TCG_TYPE_I32, a0, a1); > break; > case INDEX_op_ext8u_i32: > - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); > + tgen_ext8u(s, TCG_TYPE_I32, a0, a1); > break; > case INDEX_op_ext16u_i32: > - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); > + tgen_ext16u(s, TCG_TYPE_I32, a0, a1); > break; > > OP_32_64(bswap16): > /* The TCG bswap definition requires bits 0-47 already be zero. > Thus we don't need the G-type insns to implement bswap16_i64. */ > - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); > - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); > + tcg_out_insn(s, RRE, LRVR, a0, a1); > + tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); > break; > OP_32_64(bswap32): > - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); > + tcg_out_insn(s, RRE, LRVR, a0, a1); > break; > > case INDEX_op_add2_i32: > - if (const_args[4]) { > - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); > + if (c4) { > + tcg_out_insn(s, RIL, ALFI, a0, args[4]); > } else { > - tcg_out_insn(s, RR, ALR, args[0], args[4]); > + tcg_out_insn(s, RR, ALR, a0, args[4]); > } > - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); > + tcg_out_insn(s, RRE, ALCR, a1, args[5]); > break; > case INDEX_op_sub2_i32: > - if (const_args[4]) { > - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); > + if (c4) { > + tcg_out_insn(s, RIL, SLFI, a0, args[4]); > } else { > - tcg_out_insn(s, RR, SLR, args[0], args[4]); > + tcg_out_insn(s, RR, SLR, a0, args[4]); > } > - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); > + tcg_out_insn(s, RRE, SLBR, a1, args[5]); > break; > > case INDEX_op_br: > - tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); > + tgen_branch(s, S390_CC_ALWAYS, arg_label(a0)); > break; > > case INDEX_op_brcond_i32: > - tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], > - args[1], const_args[1], arg_label(args[3])); > + tgen_brcond(s, TCG_TYPE_I32, a2, a0, a1, c1, arg_label(args[3])); This is the place os usage c1 - not defined before. > break; > case INDEX_op_setcond_i32: > - tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], > - args[2], const_args[2]); > + tgen_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, c2); > break; > case INDEX_op_movcond_i32: > - tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], > - args[2], const_args[2], args[3], const_args[3]); > + tgen_movcond(s, TCG_TYPE_I32, args[5], a0, a1, a2, c2, args[3], c3); > break; > > case INDEX_op_qemu_ld_i32: > /* ??? Technically we can use a non-extending instruction. */ > case INDEX_op_qemu_ld_i64: > - tcg_out_qemu_ld(s, args[0], args[1], args[2]); > + tcg_out_qemu_ld(s, a0, a1, a2); > break; > case INDEX_op_qemu_st_i32: > case INDEX_op_qemu_st_i64: > - tcg_out_qemu_st(s, args[0], args[1], args[2]); > + tcg_out_qemu_st(s, a0, a1, a2); > break; > > case INDEX_op_ld16s_i64: > - tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LGH, a0, a1, TCG_REG_NONE, a2); > break; > case INDEX_op_ld32u_i64: > - tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LLGF, a0, a1, TCG_REG_NONE, a2); > break; > case INDEX_op_ld32s_i64: > - tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); > + tcg_out_mem(s, 0, RXY_LGF, a0, a1, TCG_REG_NONE, a2); > break; > case INDEX_op_ld_i64: > - tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); > + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); > break; > > case INDEX_op_st32_i64: > - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); > + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); > break; > case INDEX_op_st_i64: > - tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); > + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); > break; > > case INDEX_op_add_i64: > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[2]) { > + if (c2) { > do_addi_64: > if (a0 == a1) { > if (a2 == (int16_t)a2) { > @@ -2084,8 +2084,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > case INDEX_op_sub_i64: > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[2]) { > + if (c2) { > a2 = -a2; > goto do_addi_64; > } else if (a0 == a1) { > @@ -2096,19 +2095,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_and_i64: > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[2]) { > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I64, a0, a1); > - tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); > + tgen_andi(s, TCG_TYPE_I64, a0, a2); > } else if (a0 == a1) { > - tcg_out_insn(s, RRE, NGR, args[0], args[2]); > + tcg_out_insn(s, RRE, NGR, a0, a2); > } else { > tcg_out_insn(s, RRF, NGRK, a0, a1, a2); > } > break; > case INDEX_op_or_i64: > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[2]) { > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I64, a0, a1); > tgen_ori(s, TCG_TYPE_I64, a0, a2); > } else if (a0 == a1) { > @@ -2118,8 +2115,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > } > break; > case INDEX_op_xor_i64: > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[2]) { > + if (c2) { > tcg_out_mov(s, TCG_TYPE_I64, a0, a1); > tgen_xori(s, TCG_TYPE_I64, a0, a2); > } else if (a0 == a1) { > @@ -2130,21 +2126,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > case INDEX_op_neg_i64: > - tcg_out_insn(s, RRE, LCGR, args[0], args[1]); > + tcg_out_insn(s, RRE, LCGR, a0, a1); > break; > case INDEX_op_bswap64_i64: > - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); > + tcg_out_insn(s, RRE, LRVGR, a0, a1); > break; > > case INDEX_op_mul_i64: > - if (const_args[2]) { > - if (args[2] == (int16_t)args[2]) { > - tcg_out_insn(s, RI, MGHI, args[0], args[2]); > + if (c2) { > + if (a2 == (int16_t)a2) { > + tcg_out_insn(s, RI, MGHI, a0, a2); > } else { > - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); > + tcg_out_insn(s, RIL, MSGFI, a0, a2); > } > } else { > - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); > + tcg_out_insn(s, RRE, MSGR, a0, a2); > } > break; > > @@ -2165,10 +2161,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > case INDEX_op_shl_i64: > op = RSY_SLLG; > do_shift64: > - if (const_args[2]) { > - tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); > + if (c2) { > + tcg_out_sh64(s, op, a0, a1, TCG_REG_NONE, a2); > } else { > - tcg_out_sh64(s, op, args[0], args[1], args[2], 0); > + tcg_out_sh64(s, op, a0, a1, a2, 0); > } > break; > case INDEX_op_shr_i64: > @@ -2179,87 +2175,83 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > goto do_shift64; > > case INDEX_op_rotl_i64: > - if (const_args[2]) { > - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], > - TCG_REG_NONE, args[2]); > + if (c2) { > + tcg_out_sh64(s, RSY_RLLG, a0, a1, > + TCG_REG_NONE, a2); > } else { > - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); > + tcg_out_sh64(s, RSY_RLLG, a0, a1, a2, 0); > } > break; > case INDEX_op_rotr_i64: > - if (const_args[2]) { > - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], > - TCG_REG_NONE, (64 - args[2]) & 63); > + if (c2) { > + tcg_out_sh64(s, RSY_RLLG, a0, a1, > + TCG_REG_NONE, (64 - a2) & 63); > } else { > /* We can use the smaller 32-bit negate because only the > low 6 bits are examined for the rotate. */ > - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); > - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); > + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); > + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_TMP0, 0); > } > break; > > case INDEX_op_ext8s_i64: > - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); > + tgen_ext8s(s, TCG_TYPE_I64, a0, a1); > break; > case INDEX_op_ext16s_i64: > - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); > + tgen_ext16s(s, TCG_TYPE_I64, a0, a1); > break; > case INDEX_op_ext_i32_i64: > case INDEX_op_ext32s_i64: > - tgen_ext32s(s, args[0], args[1]); > + tgen_ext32s(s, a0, a1); > break; > case INDEX_op_ext8u_i64: > - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); > + tgen_ext8u(s, TCG_TYPE_I64, a0, a1); > break; > case INDEX_op_ext16u_i64: > - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); > + tgen_ext16u(s, TCG_TYPE_I64, a0, a1); > break; > case INDEX_op_extu_i32_i64: > case INDEX_op_ext32u_i64: > - tgen_ext32u(s, args[0], args[1]); > + tgen_ext32u(s, a0, a1); > break; > > case INDEX_op_add2_i64: > - if (const_args[4]) { > + if (c4) { > if ((int64_t)args[4] >= 0) { > - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); > + tcg_out_insn(s, RIL, ALGFI, a0, args[4]); > } else { > - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); > + tcg_out_insn(s, RIL, SLGFI, a0, -args[4]); > } > } else { > - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); > + tcg_out_insn(s, RRE, ALGR, a0, args[4]); > } > - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); > + tcg_out_insn(s, RRE, ALCGR, a1, args[5]); > break; > case INDEX_op_sub2_i64: > - if (const_args[4]) { > + if (c4) { > if ((int64_t)args[4] >= 0) { > - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); > + tcg_out_insn(s, RIL, SLGFI, a0, args[4]); > } else { > - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); > + tcg_out_insn(s, RIL, ALGFI, a0, -args[4]); > } > } else { > - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); > + tcg_out_insn(s, RRE, SLGR, a0, args[4]); > } > - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); > + tcg_out_insn(s, RRE, SLBGR, a1, args[5]); > break; > > case INDEX_op_brcond_i64: > - tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], > - args[1], const_args[1], arg_label(args[3])); > + tgen_brcond(s, TCG_TYPE_I64, a2, a0, a1, c1, arg_label(args[3])); Another c1 usage. > break; > case INDEX_op_setcond_i64: > - tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], > - args[2], const_args[2]); > + tgen_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, c2); > break; > case INDEX_op_movcond_i64: > - tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], > - args[2], const_args[2], args[3], const_args[3]); > + tgen_movcond(s, TCG_TYPE_I64, args[5], a0, a1, a2, c2, args[3], c3); > break; > > OP_32_64(deposit): > - a0 = args[0], a1 = args[1], a2 = args[2]; > - if (const_args[1]) { > + if (c1) { Another c1 usage. > tgen_deposit(s, a0, a2, args[3], args[4], 1); > } else { > /* Since we can't support "0Z" as a constraint, we allow a1 in > @@ -2277,17 +2269,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > break; > > OP_32_64(extract): > - tgen_extract(s, args[0], args[1], args[2], args[3]); > + tgen_extract(s, a0, a1, a2, args[3]); > break; > > case INDEX_op_clz_i64: > - tgen_clz(s, args[0], args[1], args[2], const_args[2]); > + tgen_clz(s, a0, a1, a2, c2); > break; > > case INDEX_op_mb: > /* The host memory model is quite strong, we simply need to > serialize the instruction stream. */ > - if (args[0] & TCG_MO_ST_LD) { > + if (a0 & TCG_MO_ST_LD) { > tcg_out_insn(s, RR, BCR, > s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); > } > -- > 2.26.2 > > From MAILER-DAEMON Wed Jan 13 08:01:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzflv-00055H-LX for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:01:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzfls-00051x-2o for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:01:09 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:38295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzflb-0000aI-89 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610542849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=vhG+8z8PVXOrdsTr0N2TRncoAAfd8YjSpWqrnJxZs64=; b=J5tdjMy6c/9fi103Q6lTIEi15F2tZL6qw47zGNxf0YVbl/gBWHXIvjb9XaZae6PCUIXesi j3RlulKXN/u4VJZYAjo0H2gkDQVcOdv9r3roCQycOFG54cYiVx34o8aPHMasn0eYtQAVWC 0F9WbZydjImUPSUq9DquNYRhjVlymsg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-493-swu6iqdGMrGbFX1MZG0SPg-1; Wed, 13 Jan 2021 08:00:48 -0500 X-MC-Unique: swu6iqdGMrGbFX1MZG0SPg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1D60D1005D5F; Wed, 13 Jan 2021 13:00:45 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-112-172.ams2.redhat.com [10.36.112.172]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D082819CBA; Wed, 13 Jan 2021 13:00:25 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 33E4C11386A7; Wed, 13 Jan 2021 14:00:24 +0100 (CET) From: Markus Armbruster To: Eric Blake Cc: qemu-devel@nongnu.org, Peter Maydell , "Michael S. Tsirkin" , Jason Wang , Thomas Huth , Gerd Hoffmann , "open list:GLUSTER" , Juan Quintela , David Hildenbrand , Halil Pasic , Christian Borntraeger , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Aleksandar Rikalo , Jiri Pirko , Eduardo Habkost , Michael Roth , Richard Henderson , "Dr. David Alan Gilbert" , Greg Kurz , "open list:S390 KVM CPUs" , "open list:ARM TCG CPUs" , Stefan Hajnoczi , David Gibson , Kevin Wolf , "open list:GLUSTER" , Daniel P. =?utf-8?Q?Berr?= =?utf-8?Q?ang=C3=A9?= , Cornelia Huck , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Max Reitz , "open list:PowerPC TCG CPUs" , Paolo Bonzini , Aurelien Jarno Subject: Re: [PATCH v3 4/7] qapi: Use QAPI_LIST_PREPEND() where possible References: <20201223221102.390740-1-eblake@redhat.com> <20201223221102.390740-5-eblake@redhat.com> Date: Wed, 13 Jan 2021 14:00:24 +0100 In-Reply-To: <20201223221102.390740-5-eblake@redhat.com> (Eric Blake's message of "Wed, 23 Dec 2020 16:10:59 -0600") Message-ID: <87czy90z6f.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=216.205.24.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:01:09 -0000 Eric Blake writes: > Anywhere we create a list of just one item or by prepending items > (typically because order doesn't matter), we can use the > QAPI_LIST_PREPEND macro. But places where we must keep the list in > order by appending remain open-coded until later patches. > > Note that as a side effect, this also performs a cleanup of two minor > issues in qga/commands-posix.c: the old code was performing > new = g_malloc0(sizeof(*ret)); > which 1) is confusing because you have to verify whether 'new' and > 'ret' are variables with the same type, and 2) would conflict with C++ > compilation (not an actual problem for this file, but makes > copy-and-paste harder). > > Signed-off-by: Eric Blake > Reviewed-by: Markus Armbruster > Acked-by: Stefan Hajnoczi Already in master as commit 54aa3de72e, except for: > diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c > index 87f14140a381..156223a344ed 100644 > --- a/hw/core/machine-qmp-cmds.c > +++ b/hw/core/machine-qmp-cmds.c [...] > @@ -297,41 +293,31 @@ void qmp_set_numa_node(NumaOptions *cmd, Error **errp) > static int query_memdev(Object *obj, void *opaque) > { > MemdevList **list = opaque; > - MemdevList *m = NULL; > + Memdev *m; > QObject *host_nodes; > Visitor *v; > > if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { > m = g_malloc0(sizeof(*m)); > > - m->value = g_malloc0(sizeof(*m->value)); > + m->id = g_strdup(object_get_canonical_path_component(obj)); > + m->has_id = !!m->id; > > - m->value->id = g_strdup(object_get_canonical_path_component(obj)); > - m->value->has_id = !!m->value->id; > - > - m->value->size = object_property_get_uint(obj, "size", > - &error_abort); > - m->value->merge = object_property_get_bool(obj, "merge", > - &error_abort); > - m->value->dump = object_property_get_bool(obj, "dump", > - &error_abort); > - m->value->prealloc = object_property_get_bool(obj, > - "prealloc", > - &error_abort); > - m->value->policy = object_property_get_enum(obj, > - "policy", > - "HostMemPolicy", > - &error_abort); > + m->size = object_property_get_uint(obj, "size", &error_abort); > + m->merge = object_property_get_bool(obj, "merge", &error_abort); > + m->dump = object_property_get_bool(obj, "dump", &error_abort); > + m->prealloc = object_property_get_bool(obj, "prealloc", &error_abort); > + m->policy = object_property_get_enum(obj, "policy", "HostMemPolicy", > + &error_abort); > host_nodes = object_property_get_qobject(obj, > "host-nodes", > &error_abort); > v = qobject_input_visitor_new(host_nodes); > - visit_type_uint16List(v, NULL, &m->value->host_nodes, &error_abort); > + visit_type_uint16List(v, NULL, &m->host_nodes, &error_abort); > visit_free(v); > qobject_unref(host_nodes); > > - m->next = *list; > - *list = m; > + QAPI_LIST_PREPEND(*list, m); > } > > return 0; [...] From MAILER-DAEMON Wed Jan 13 08:12:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzfwg-0001kB-U3 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:12:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzfwd-0001ja-4y; Wed, 13 Jan 2021 08:12:15 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:45692 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzfwZ-0005TT-H6; Wed, 13 Jan 2021 08:12:14 -0500 Received: from basile.remlab.net (dzyqn8ypzhx7l91mxjsvy-3.rev.dnainternet.fi [IPv6:2001:14ba:a01a:be01:9434:f69e:d553:3be2]) (Authenticated sender: remi) by ns207790.ip-94-23-215.eu (Postfix) with ESMTPSA id B855C5FC25; Wed, 13 Jan 2021 14:12:05 +0100 (CET) From: =?ISO-8859-1?Q?R=E9mi?= Denis-Courmont To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Richard Henderson Subject: Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension Date: Wed, 13 Jan 2021 15:12:04 +0200 Message-ID: <4284476.LvFx2qVVIh@basile.remlab.net> Organization: Huawei Technologies, Finland In-Reply-To: <6ffaca60-2fa0-ac7d-b430-0bbaee18b25a@linaro.org> References: <12681824.uLZWGnKmhe@basile.remlab.net> <20210112104511.36576-17-remi.denis.courmont@huawei.com> <6ffaca60-2fa0-ac7d-b430-0bbaee18b25a@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:12:16 -0000 Le tiistaina 12. tammikuuta 2021, 23.30.39 EET Richard Henderson a =C3=A9cr= it : > On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote: > > From: R=C3=A9mi Denis-Courmont > >=20 > > This adds handling for the SCR_EL3.EEL2 bit. > >=20 > > Signed-off-by: R=C3=A9mi Denis-Courmont >=20 > The patch title seems to have gone awry. >=20 > > @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode > >=20 > > } > > if (s->current_el =3D=3D 1) { > > =20 > > /* If we're in Secure EL1 (which implies that EL3 is AArch= 64) > >=20 > > - * then accesses to Mon registers trap to EL3 > > + * then accesses to Mon registers trap to Secure EL2, if it > > exists, + * otherwise EL3. > >=20 > > */ > >=20 > > - TCGv_i32 tcg_el =3D tcg_const_i32(3); > > + TCGv_i32 tcg_el; > > + > > + if (dc_isar_feature(aa64_sel2, s)) { > > + /* Target EL is EL<3 minus SCR_EL3.EEL2> */ > > + tcg_el =3D load_cpu_field(cp15.scr_el3); > > + tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), = 1); > > + tcg_gen_addi_i32(tcg_el, tcg_el, 3); > > + } else { > > + tcg_el =3D tcg_const_i32(3); > > + } >=20 > You can't test an aa64 feature without verifying that the cpu has aa64 > support (if the cpu is strictly aa32, the aa64 registers are > undefined/uninitialized). So: >=20 > if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && > dc_isar_feature(aa64_sel2, s)) { > ... >=20 Hmm, yeah. Should this be an ifdef on TARGET_AARCH64 instead? Also do we need to revector the exception code, or leave it mostly duplicat= ed=20 as is? > With those things changed, > Reviewed-by: Richard Henderson >=20 >=20 > r~ =2D-=20 R=C3=A9mi Denis-Courmont From MAILER-DAEMON Wed Jan 13 08:28:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgBx-0001Df-N1 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:28:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgBv-0001Av-Fb; Wed, 13 Jan 2021 08:28:03 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:37394) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzgBt-00046s-6p; Wed, 13 Jan 2021 08:28:03 -0500 Received: by mail-yb1-xb30.google.com with SMTP id z1so2150848ybr.4; Wed, 13 Jan 2021 05:28:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=GsOJlZDnOmaLHm617iqZrqPSsYXYDwDHCB+ZhkydkIU=; b=duqbQgJywsdK6PGXC8LkIQ2sblz2UdLXIAMCNx3LTgdxxtHW8Tr2DIWtRRYsoXW8ex Rk070r2rxnZKFg5RJPuOG2gHP2uovFsB0rrIPR2UjeIU6vnEFgd4Dw7N31iXokH0FB3h xU4KIt/rlmwH4e69xwQbB/PyHnwhkxL/4JLUFZrAsvrqdzYxwDT3nFRLwQEQmhBOA7Lb GzNk3xZ7fqnJ+koG2awBCaoh9hfw372BTQ5RTELzmcipdhxZG5doF1/1QuGejok1PbkH GYEAZKt/+1sNFAVDAtCRR2fgFlgNjVndwJtTlNoKGZ0PE9dNaacs48/EYibFaNutgIyi eRnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=GsOJlZDnOmaLHm617iqZrqPSsYXYDwDHCB+ZhkydkIU=; b=ZB+T2vndPIQ33DBNnA6EBVtiMO2nDQ097u4aGF2u7z2LAjv/lU62hnLy/977Bq8nnt 9HoTkuZGPc7WP9tjfaAoBQeZjgjTZD5/69cqX060Kydn7rORE7ld4IdGs/zYyngXU46C imq/IgGLD+hrKQ4y+7YfzB0qS1xYm6+fs2C5v55e1JqWov8CRaC8HIUXOVCPMsR5WC8p 6mKkupddZ1KrbRdS0Bm4AUXNIYxzwzMAomo1UBKygV6tdG57WmwycwHUxD+rt9fNgtOc ycotChnlwZoKhKdISWwg80Op8L35XXwkB8Mf3NLr0mOf7HL54QnKgHa3kfDaIode+bab gsXg== X-Gm-Message-State: AOAM533ldSMzPPq0LtSorR6nFj4O3NSaFB3tN9Ehng01gUm1cxnYkxPd TwO+K+PMbPlJm1Lc6ktXeR5VJ7bsL0gN999IlzY= X-Google-Smtp-Source: ABdhPJxVgTgwprohUW1/gVUjhfCbS1cXOV+QRMeqkLuv1ynJ4kIMCKkE4MBuTtK6azc37eXV1qjFgytZRH7lozeMVXc= X-Received: by 2002:a25:5a43:: with SMTP id o64mr3407039ybb.387.1610544479772; Wed, 13 Jan 2021 05:27:59 -0800 (PST) MIME-Version: 1.0 References: <20210112183529.2011863-1-f4bug@amsat.org> <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> In-Reply-To: <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> From: Bin Meng Date: Wed, 13 Jan 2021 21:27:48 +0800 Message-ID: Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Bin Meng , Xuzhou Cheng , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:28:03 -0000 Hi Philippe, On Wed, Jan 13, 2021 at 3:53 PM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi Ben, > > On 1/13/21 4:29 AM, Bin Meng wrote: > > On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daud=C3=A9 wrote: > >> > >> Hi, > >> > >> As it is sometimes harder for me to express myself in plain > >> English, I found it easier to write the patches I was thinking > >> about. I know this doesn't scale. > >> > >> So this is how I understand the ecSPI reset works, after > >> looking at the IMX6DQRM.pdf datasheet. > >> > >> This is a respin of Ben's v5 series [*]. > >> Tagged RFC because I have not tested it :) > > > > Unfortunately this series breaks SPI flash testing under both U-Boot > > and VxWorks 7. > > Thanks for testing :) Can you provide the binary tested and the command > line used? At least one, so I can have a look. Sure, will send you offline. > > >> Sometimes changing device reset to better match hardware gives > >> trouble when using '-kernel ...' because there is no bootloader > >> setting the device in the state Linux expects it. > >> > > > > Given most of the new changes in this RFC series are clean-ups, I > > suggest we apply the v5 series unless there is anything seriously > > wrong in v5, IOW, don't fix it unless it's broken. > > > > Thoughts? > > Up to the maintainer :) > > The IMX6DQRM datasheet is available here: > https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6DQ-Refe= rence-Manual-IMX6DQRM-R2-Part-1/ta-p/1115983 > https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6DQ-Refe= rence-Manual-IMX6DQRM-R2-Part-2/ta-p/1118510 Regards, Bin From MAILER-DAEMON Wed Jan 13 08:37:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgKp-0005vN-69 for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:37:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgKa-0005sk-06 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:37:01 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:38226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzgKX-0007tb-47 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:36:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610545016; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ozCjCj0KoOgE4Zaz1sfJqi0oRDqpyppOnSMefLyC/cU=; b=YaSgPTtegEthDO5gQzzRasQbSNeCggUu0BTrRNHFnKKbdVcLk8IgtWvJCQIaGEr0pa0rBo 1ybp0pjzCY3vl1ZRoph2uElubYQicpoJydmsWmW+9yf/ENDqpTpH2E7rLUm6B1TrEcsvH6 M2GxIfIhZsSK3IR39dRoYIbNKrSh+W4= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-148-VpiulcFbN1a9QHVmlVpCgQ-1; Wed, 13 Jan 2021 08:36:54 -0500 X-MC-Unique: VpiulcFbN1a9QHVmlVpCgQ-1 Received: by mail-wr1-f72.google.com with SMTP id e12so976413wrp.10 for ; Wed, 13 Jan 2021 05:36:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references :user-agent:reply-to:date:message-id:mime-version :content-transfer-encoding; bh=4vGOXvngMiIHEkvOxc0i0Ro7ST82YJ/WLMStNoEm3DU=; b=j9dTECtvK3R9rQSaEMi0c71T8RCW9CtpjFHnSaK/CtmPnXZ2UMHu4udfS90DaX3d/P dA3Y1E8cMlsOUsxrVpp/spvZ5oJJ0tQf2K7uvOsrOYcfAkWJDDKRYkKwh/uzoRAs5VfJ BaLLGK8uL4LzWH2DAMO3dMVM40I06sdH9zsWlMZD7IhXSwao5/QtAKWuXGUJfBMxaTvs lXqDhcFz+mms/7AU4FVjr8+lI6qHv1Shtk2MiNl+GF2Ts1/gPfr8wC0XDhUJ0VO+sI6l pxUdgfcy34/FhefZrvOTIBEBJorjNnF5KHeg5vkmRXudEKGgIf83SQSwVSis1BZqpI0g +hUA== X-Gm-Message-State: AOAM533OygE6nqXnf00NAdnL6poleNj7mdqeY72PdVMLKVcfHiCycSK7 53rES9Bqe+HX4WUQGY7BrHvSDuN0vvsvM5M5OIflDoTqxESK1YQhCN2lSLgVnXuWe5nQTylXhps +Tql82351gOur X-Received: by 2002:a05:600c:21c8:: with SMTP id x8mr2248423wmj.146.1610545013346; Wed, 13 Jan 2021 05:36:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJziKLTKtR3aMg+YfxIw1PqJnlRcyuT7kiK8U4TP7hhEt08uFhqYq0ypSUAo59dT+YtD92mBaA== X-Received: by 2002:a05:600c:21c8:: with SMTP id x8mr2248404wmj.146.1610545013163; Wed, 13 Jan 2021 05:36:53 -0800 (PST) Received: from localhost (trasno.trasno.org. [83.165.45.250]) by smtp.gmail.com with ESMTPSA id l8sm4332932wrb.73.2021.01.13.05.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:36:52 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events In-Reply-To: <20210112183529.2011863-4-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:21 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-4-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:36:51 +0100 Message-ID: <87mtxdgdqk.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=63.128.21.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:37:01 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > Convert some DPRINTF() to trace events. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela > diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events > index 612d3d6087a..20fcaf32df6 100644 > --- a/hw/ssi/trace-events > +++ b/hw/ssi/trace-events > @@ -1,3 +1,5 @@ > +# See docs/devel/tracing.txt for syntax documentation. > + > # aspeed_smc.c > =20 > aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint6= 4_t end) "CS%d segreg=3D0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]" Not that I am against the comment, but it looks spurious on this patch. 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[83.165.45.250]) by smtp.gmail.com with ESMTPSA id y2sm2972736wma.6.2021.01.13.05.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:35:47 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization In-Reply-To: <20210112183529.2011863-3-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:20 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-3-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:35:46 +0100 Message-ID: <87r1mpgdsd.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:37:15 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > 'burst_length' is cleared in imx_spi_reset(), which is called > after imx_spi_realize(). Remove the initialization to simplify. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela From MAILER-DAEMON Wed Jan 13 08:37:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgKt-00061H-Fm for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:37:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgKp-0005vL-08 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:37:15 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:22119) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzgKj-0007w1-1w for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:37:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610545021; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=a8XwYsiGGHOPSJH7Yz5Tw5P2tfkHFb/+AReSQR2pzIQ=; b=UTW6EzCX3XwjovdzDIIzfmokDhOnOT+xXGV6dOKrwBupBPR2bGC0WO58hMsaRIcVEraRac YvRKjkDD/CSpC8+ivwUEbXNvxzywNj5N2fl3ePVPlXy4dAK4FXx1ZE7kZRxJiCG8pjJ7cR TloX4bopRILlK573NHjBmKcLR0P6iQw= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-418-jOPAZhPMN-iSDFWxdXxcrA-1; Wed, 13 Jan 2021 08:35:32 -0500 X-MC-Unique: jOPAZhPMN-iSDFWxdXxcrA-1 Received: by mail-wr1-f69.google.com with SMTP id v7so973880wra.3 for ; Wed, 13 Jan 2021 05:35:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references :user-agent:reply-to:date:message-id:mime-version :content-transfer-encoding; bh=a8XwYsiGGHOPSJH7Yz5Tw5P2tfkHFb/+AReSQR2pzIQ=; b=GZL6AYrQkTkO9TCZqE5rSq4Gen/xwMN8BHPUnw9ognudzCGp5z9sq7ix0CwhW2vXnn qkZ6beJ34sdZ0Zuz3hGBQhZqYF68YNMg2fyxzBperHlRT264GMB7ixc1hvVBIHMRI5vd lnle8GrKtUfGkahq0js6lUnk8UG/6Hljjbv0k7pZS1NNEjVoQs50o4UXKxqq/crox9kd lGy9Oy14r7u9RkZ/8YltFcOXwVsyEPeVH3rfCjLnhM0jc8y6I74YbB9qSvMkhA6GnJpX cq3PJ1MBrgAY3OMbgYITqPAMx3TW9/ftivIpfFe0XJscrztBvoifbm/78qWmoa8sZR58 73oA== X-Gm-Message-State: AOAM533Z5DuXK5dvLmi7rI59R+z2Qgpl6KmHvNU5WbVNHu7xLW23+onK uwAmpjxn/Gb0L8hqf1AVJMOXEM7r2lDsBnKx9GiBd3lWIbOv7JuzdE21teGpJ4tmEaTfpGYOnmU X4BE/PtZLln4R X-Received: by 2002:a05:6000:1043:: with SMTP id c3mr2646570wrx.34.1610544931705; Wed, 13 Jan 2021 05:35:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJzh09qX4HbYzYkFCUUIBYoh8QENkdc7M9A1J63YDMCVGSXOuLE+IW5iJAM+97X84lUll8OfXg== X-Received: by 2002:a05:6000:1043:: with SMTP id c3mr2646554wrx.34.1610544931506; Wed, 13 Jan 2021 05:35:31 -0800 (PST) Received: from localhost (trasno.trasno.org. [83.165.45.250]) by smtp.gmail.com with ESMTPSA id b14sm3242414wrx.77.2021.01.13.05.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:35:30 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Alistair Francis , Peter Chubb Subject: Re: [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported In-Reply-To: <20210112183529.2011863-2-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:19 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-2-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:35:29 +0100 Message-ID: <87v9c1gdsu.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:37:16 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > From: Bin Meng > > Avoid using a magic number (4) everywhere for the number of chip > selects supported. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Message-Id: <20210112145526.31095-2-bmeng.cn@gmail.com> > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela A fast search don't show what resets cs_lines, but that is independent of this patch. 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[83.165.45.250]) by smtp.gmail.com with ESMTPSA id n11sm3839020wra.9.2021.01.13.05.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:41:44 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope In-Reply-To: <20210112183529.2011863-5-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:22 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-5-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:41:43 +0100 Message-ID: <87im81gdig.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=63.128.21.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:41:52 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > Signed-off-by: Philippe Mathieu-Daud=C3=A9 I think this one is wrong. > --- > hw/ssi/imx_spi.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 35ab33c0511..bcc535f2893 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offset= , uint64_t value, > { > IMXSPIState *s =3D opaque; > uint32_t index =3D offset >> 2; > - uint32_t change_mask; > =20 > if (index >=3D ECSPI_MAX) { > qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0= x%" > @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offset= , uint64_t value, > =20 > trace_imx_spi_write(index, imx_spi_reg_name(index), value); > =20 > - change_mask =3D s->regs[index] ^ value; > =20 > switch (index) { > case ECSPI_RXDATA: > @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offset= , uint64_t value, > } > =20 > if (imx_spi_channel_is_master(s)) { > + uint32_t change_mask =3D s->regs[index] ^ value; > int i; > =20 > /* We are in master mode */ The code does: change_mask =3D s->regs[index] ^ value; switch (index) { ... case ECSPI_CONREG: s->regs[ECSPI_CONREG] =3D value; <<---- here if (!imx_spi_is_enabled(s)) { /* device is disabled, so this is a reset */ imx_spi_reset(DEVICE(s)); return; } if (imx_spi_channel_is_master(s)) { int i; >>>>> You are setting change_mask here. At this point, s->regs[index] has a new value in "here". Later, Juan. From MAILER-DAEMON Wed Jan 13 08:44:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgS0-0002Du-DT for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:44:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgRy-0002DQ-28 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:44:38 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:54086) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzgRB-0002M9-Lj for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:44:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610545424; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mC5y+NPr62yYqrU3YGwTiiHBkagQzXTh1WGcEASNq0o=; b=DUDyYXN1i/akVxsQqHoAM4JujKSfuxedDyHqkZO0Wa5WSwMS9rn52666GBPUGiRhY7XJGo uFF1wG/I5cmoffHJFx3Aolsg0UfvKo9doHAdfjChpcUTRkc5idcOI5vXJ7dnooNpbh8YNH Iz/wmHlT1JZcaDQotRedLNCOlU4T36A= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-471-6cfqq2PlOaSZMZ1aI8iMWQ-1; Wed, 13 Jan 2021 08:43:42 -0500 X-MC-Unique: 6cfqq2PlOaSZMZ1aI8iMWQ-1 Received: by mail-wm1-f71.google.com with SMTP id z188so1657054wme.1 for ; Wed, 13 Jan 2021 05:43:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references :user-agent:reply-to:date:message-id:mime-version :content-transfer-encoding; bh=mC5y+NPr62yYqrU3YGwTiiHBkagQzXTh1WGcEASNq0o=; b=oEny70y2+TpQWn6FrR5e1ePLGJ+RLqz13HaTbczYvleyLGdtpuHSBtYGzH5zH+WZ+Q Z18RbOEaPbFoew/g7IVtdDvKcudgzB9sdY906FVFv9+y4PXEj/71f8+aAaRUenrb02nC g5iZfrIw+Yb/Ap3jvcv+O1PyK47/iKW0oDdIfSoFNr+/Q0gRllQaw5m2+9L7HUkqgpfU aXJb5vq5P1YPHFNecJkcTByoAHcsv0TZSZ36ysW7/SpVf40vFa3VeouzVGnzQTrNxq3/ mYQcVWcoE9Z2iyeV2TbKswP4iIvtaIay89/FqHc76LOYyjX97dOF+cuUK1r62X6hsBuE uNJQ== X-Gm-Message-State: AOAM530WQR4Ug7I673F0H2CoIyVRyFRm1dOoW0v79/P16HjRrnlQIeUK CFe07VCoTaJeYl+xhwnSWF19uYvT8v7V7XJRuRE5EIugPDFJe/RFx3lVbkCMdgM+h5lleleLzpm WGEJf3+Z6m5Zw X-Received: by 2002:adf:ef8b:: with SMTP id d11mr2762432wro.156.1610545420905; Wed, 13 Jan 2021 05:43:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJxk3X9q9gGaCcDsjZwsiSKH5s2cRLy6R2Y3t2UaxlrcrOyCwFVLj2+RgtaxUrwBP9fhO9vy3w== X-Received: by 2002:adf:ef8b:: with SMTP id d11mr2762418wro.156.1610545420693; Wed, 13 Jan 2021 05:43:40 -0800 (PST) Received: from localhost (trasno.trasno.org. [83.165.45.250]) by smtp.gmail.com with ESMTPSA id t188sm3014743wmf.9.2021.01.13.05.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:43:40 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value In-Reply-To: <20210112183529.2011863-6-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:23 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-6-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:43:39 +0100 Message-ID: <87eeipgdf8.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:44:38 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > When the block is disabled, all registers are reset with the > exception of the ECSPI_CONREG. It is initialized to zero > when the instance is created. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela I trust your reading of the documentation O:-) From MAILER-DAEMON Wed Jan 13 08:46:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgU6-0003Ux-Lx for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:46:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgU4-0003Sy-LW for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:46:48 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:55332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzgU2-0003SJ-TS for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:46:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610545606; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=z4xSfq28ilhdS/dEKCCRIC+4nFcHCGo8hIdFUOMrRzE=; b=hPXh0lqg+jVOLaeN3SowmtxLIVaQwjPCSUvzhFcH+I40eIVajJKrk43f/BgnYkoBVbRN3w IHWLrRQufD6wJvYQh99dxL+0+4iUqiQxgLFS9HrzxTox4OSLjf2RVTWMzq/ux5sGrSM6vf 40p0r8Jipxs6LhyJZ1Id9Pro9iv/mT4= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-73-LmWhCuclPtCdL3QvWmllfA-1; Wed, 13 Jan 2021 08:46:43 -0500 X-MC-Unique: LmWhCuclPtCdL3QvWmllfA-1 Received: by mail-wm1-f71.google.com with SMTP id r1so844204wmn.8 for ; Wed, 13 Jan 2021 05:46:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references :user-agent:reply-to:date:message-id:mime-version :content-transfer-encoding; bh=z4xSfq28ilhdS/dEKCCRIC+4nFcHCGo8hIdFUOMrRzE=; b=Pbt6ZO8QDDhQnTCwLwQMDWflIWbzkhb6DIVaUddMG9gPxjot30mvEFkkG5+6PZ/yPc 0Ldcy+jG2reJyzx81mibCYg5+nYZ8l+OiftJ71K0sjAY4jiG7NihWutOsc7Efcf89zT7 ylKfjr5eTRqkefo7FhYh/rSsp+JK2zVjWWYXAbtownnu0XGVGlvucGr1bru/H/7gnu7H AHorMq8Etb1p11JHe36nkSlq+LaJnt9Sm0zgzJFVjXwrX7q3ZNubGcBpB0rg19aGRIyj tL5y5Xr+uifYInmkXPqVSksSo0ecpLbj6GjQS/5TX0PTNYUw5DAVOIdb4WNUmJIxV08m 0edA== X-Gm-Message-State: AOAM532R60kBNwcroiehocHoN1okf2XVdzNRB7iSTDUn2Nf9whUEQstU DiTJXz2PZ+GB7+nDAfS6SA/KNLtAXDbv8faSUwwVifCktx58saqQU9o4WsrNuFRqCOGDN8kD/HU 3C+wSJd0t0Paa X-Received: by 2002:a1c:6a02:: with SMTP id f2mr2359707wmc.36.1610545602483; Wed, 13 Jan 2021 05:46:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJzggH2McgS1Zryfa8X7Np46Hy6v7YGcf7DGqBT8x7BT3CMWOdML2UPq2lZh7Vicp0A6xsfnTQ== X-Received: by 2002:a1c:6a02:: with SMTP id f2mr2359688wmc.36.1610545602321; Wed, 13 Jan 2021 05:46:42 -0800 (PST) Received: from localhost (trasno.trasno.org. [83.165.45.250]) by smtp.gmail.com with ESMTPSA id c11sm2620625wmd.36.2021.01.13.05.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:46:41 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled In-Reply-To: <20210112183529.2011863-7-f4bug@amsat.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Tue, 12 Jan 2021 19:35:24 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-7-f4bug@amsat.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:46:40 +0100 Message-ID: <87a6tdgda7.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:46:49 -0000 Philippe Mathieu-Daud=C3=A9 wrote: > When the block is disabled, it stay it is 'internal reset logic' > (internal clocks are gated off). Reading any register returns > its reset value. Only update this value if the device is enabled. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela From MAILER-DAEMON Wed Jan 13 08:47:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgVA-00045B-9j for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 08:47:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgV8-000440-T2 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:47:54 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:40822) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kzgV7-0003om-4w for qemu-arm@nongnu.org; Wed, 13 Jan 2021 08:47:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610545672; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ymhsrLTpVqf+YV4UDp3pX1LEnr75n0cl4NCRaFGDRVs=; b=YKQAV7DWkhd2rwSn22HqISb+mRC+S30UUhOwf4y2VpEBdzBSDUYjCQktdTOasDqU9Aqit8 tbC2nh8rJOrER3HXGHN9+JLLf6lzVY2WyhUfof51GQ1bGdUURVri83wkJ628pAjfhlgCe9 7+/j2i/JKgr0Z4r8WBGsA/PMwA+sENE= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-399-K9tbAvfiOi-6CWMyV5C60Q-1; Wed, 13 Jan 2021 08:47:50 -0500 X-MC-Unique: K9tbAvfiOi-6CWMyV5C60Q-1 Received: by mail-wr1-f69.google.com with SMTP id v5so1002989wrr.0 for ; Wed, 13 Jan 2021 05:47:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:in-reply-to:references :user-agent:reply-to:date:message-id:mime-version :content-transfer-encoding; bh=KcI38j+Zh3rURT7LR1cI4qN+NHTumYNN/a/93hEfFGI=; b=FHXktgoS3bId3e+rcsbB81AnIhT6WGJT+G5h/SjXDS30OKtRgfGa7OwHnrZeKWfu8F Rhdre6u8SoUa6y4uiMhrcmy+oX+KaJiJ1EA+OD8n1ggm6k9NbGofmVypBhVq3HhAE+PM cwROCFB0qim359oO5OjBbYJCUV7ieOJIYhsVpcuSfr9L415CbUASqPtdBebYUImRuE5r PCODJOkfImQqEDkF8YoORZKQBNvEAxFZtsxDZCSI6aAf1/Y8g574WeUXhrXfCUYeVnXN Z0/hIfVEmCWVPNS/zBvBG/vz167eFvjOVqLBMebyNvfTlm9VIzwl0zXYmcZSPjkrTtA8 XIFw== X-Gm-Message-State: AOAM533+g03BWoue4ZmHIo89/VCvOuvVggBMc+4iYCX/WdMCBX/opekZ ZAbJsTzDEb9uh9CPZsU0qsi44y5aiT+T079qZpGgykhm/O35JoXOPf4QdhwXU7QXcBXNLD134Bl I5yGYfIX0cKoJ X-Received: by 2002:a1c:3206:: with SMTP id y6mr2240409wmy.127.1610545669443; Wed, 13 Jan 2021 05:47:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJzvqTnT8hcN8capifqTi9YCju/BfJs0gwNC+0Frx2go3YbQD8dgOOTWGXVbdy6s6qd4zOAG6A== X-Received: by 2002:a1c:3206:: with SMTP id y6mr2240394wmy.127.1610545669204; Wed, 13 Jan 2021 05:47:49 -0800 (PST) Received: from localhost (trasno.trasno.org. [83.165.45.250]) by smtp.gmail.com with ESMTPSA id l20sm3736801wrh.82.2021.01.13.05.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 05:47:48 -0800 (PST) From: Juan Quintela To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Bin Meng , qemu-devel@nongnu.org, Bin Meng , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb Subject: Re: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope In-Reply-To: <87im81gdig.fsf@secure.mitica> (Juan Quintela's message of "Wed, 13 Jan 2021 14:41:43 +0100") References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-5-f4bug@amsat.org> <87im81gdig.fsf@secure.mitica> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) Reply-To: quintela@redhat.com Date: Wed, 13 Jan 2021 14:47:47 +0100 Message-ID: <875z41gd8c.fsf@secure.mitica> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=quintela@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 13:47:55 -0000 Juan Quintela wrote: > Philippe Mathieu-Daud=C3=A9 wrote: >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 > > I think this one is wrong. Wrong is a strong word. I mean that it changes behaviour and the commit message don't talk about changing behaviour. Later, Juan. > > >> --- >> hw/ssi/imx_spi.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >> index 35ab33c0511..bcc535f2893 100644 >> --- a/hw/ssi/imx_spi.c >> +++ b/hw/ssi/imx_spi.c >> @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> { >> IMXSPIState *s =3D opaque; >> uint32_t index =3D offset >> 2; >> - uint32_t change_mask; >> =20 >> if (index >=3D ECSPI_MAX) { >> qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset = 0x%" >> @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> =20 >> trace_imx_spi_write(index, imx_spi_reg_name(index), value); >> =20 >> - change_mask =3D s->regs[index] ^ value; >> =20 >> switch (index) { >> case ECSPI_RXDATA: >> @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, >> } >> =20 >> if (imx_spi_channel_is_master(s)) { >> + uint32_t change_mask =3D s->regs[index] ^ value; >> int i; >> =20 >> /* We are in master mode */ > > The code does: > > change_mask =3D s->regs[index] ^ value; > > switch (index) { > > ... > > case ECSPI_CONREG: > s->regs[ECSPI_CONREG] =3D value; <<---- here > > if (!imx_spi_is_enabled(s)) { > /* device is disabled, so this is a reset */ > imx_spi_reset(DEVICE(s)); > return; > } > > if (imx_spi_channel_is_master(s)) { > int i; > >>>>> You are setting change_mask here. > > At this point, s->regs[index] has a new value in "here". > > Later, Juan. From MAILER-DAEMON Wed Jan 13 09:11:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgro-0007Ex-Mr for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 09:11:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgrk-0007Ax-0K; Wed, 13 Jan 2021 09:11:16 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:35843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzgrh-0005cp-JP; Wed, 13 Jan 2021 09:11:15 -0500 Received: by mail-ed1-x534.google.com with SMTP id b2so2060651edm.3; Wed, 13 Jan 2021 06:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=j/tzQYxcL9oPXA73zHHNehn2z9Rge6a9/KFC8AG2a48=; b=p+LdzPCwrMO54FN2vizwydvYz8ZgMxrW79QbxiLQoiPNjuPMAwU+q5V6sseXnj7ZME LnN6xPX3H+FlpyGiSWVTZoNTM59znEkyua6Q5eO4/a4Xv1G17tQRC7XdBNjEVd7kT0CL WiJwSsVmd7BXkzWTYfVbU6PiOHBmx1ZDS4iYy0VagxHP5MBdNc0UNRFv3Su70n5np4/q /ciNs8deNDbEDcOyxqInPBjyAxby7MY/kzub2UFTUmrOGVbGmUn53v6nePM5UvWMvVFb iKcwh/33lBemxf4MdApj9qnIKq1cm8IZyHl9+gQ0BndyJNYQdCE6XJEYkQTXJB0x3e+5 XHdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=j/tzQYxcL9oPXA73zHHNehn2z9Rge6a9/KFC8AG2a48=; b=pEH7lrKMP8bNrIr+WRw54LDjCAX+GZ8mbm8o91Z1pDRlq0vxIviy+vjruirHVoew8F UuIbsDjs1DpEHdBhDtP2gHLDgkkv+HFoFw2jYWyNliwdx59Ve/ul6M/QMat4QrJP0b3F 8okAec8x8HOfSUFQwOfhn6ABYjQCnBBGaXVQ3r2yVuYgwSi6Ete5+Xfb+lvj1dDnICK8 YdHuF+76bo4kLLljWEIbws/j7MDQqJ9SpS8kT0s4xuXs+QO6EFbQcGbLDXewzG0Y2B6v KJsO9g33o1/gJ3UNDn2zxgLcSFr6FA67SnZeemFed1NenYxQkg7WaL+CTbNOp2vXwe0K Xi8g== X-Gm-Message-State: AOAM533QvZQUebJmO9ym7q0x6aHLT/wcF1ymkynwW+pXSXxWPblElFzh lQ3eHRXERHwE6KnNRXrlMuKhar0SEJdMc7uWb3o= X-Google-Smtp-Source: ABdhPJxefOr3y01tjacVEapXUFFzLegCIKT5+Yx420gpEeSwztIhvx2aZpk7u84pTcxC7s8Dl32UbeZG43Y//kBQmp4= X-Received: by 2002:a05:6402:1714:: with SMTP id y20mr1925629edu.2.1610547070906; Wed, 13 Jan 2021 06:11:10 -0800 (PST) MIME-Version: 1.0 References: <15fc51bf-1473-2808-583e-c58eb1620577@greensocs.com> In-Reply-To: <15fc51bf-1473-2808-583e-c58eb1620577@greensocs.com> From: "Edgar E. Iglesias" Date: Wed, 13 Jan 2021 15:11:01 +0100 Message-ID: Subject: Re: [PATCH] Initialize Zynq7000 UART clocks on reset To: Damien Hedde Cc: Peter Maydell , Michael Peter , qemu-arm , "qemu-devel@nongnu.org" , Alistair Francis Content-Type: multipart/alternative; boundary="0000000000000e376905b8c8b6cc" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=edgar.iglesias@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 14:11:16 -0000 --0000000000000e376905b8c8b6cc Content-Type: text/plain; charset="UTF-8" On Wed, 13 Jan 2021, 11:19 Damien Hedde, wrote: > > This is ok but I'm afraid we may end up doing this kind of thing in a > lot of devices. So maybe we should consider changing the behavior of > device_is_in_reset() so that it returns false in the reset-exit case. > What do you think ? (I've a patch for this, which make this one useless) > Thanks Damien, IMO, a central fix for this would be better, I agree with you. Thanks, Edgar > But this patch does not harm so, anyway: > Reviewed-by: Damien Hedde > > On 1/7/21 9:00 PM, Peter Maydell wrote: > > Alistair/Edgar/Damien -- could I get a review from one of you > > for this Xilinx clock-gen related patch, please? > > > > thanks > > -- PMM > > > > On Tue, 24 Nov 2020 at 18:54, Michael Peter > > wrote: > >> > >> Pass an additional argument to zynq_slcr_compute_clocks that indicates > whether an reset-exit condition > >> applies. If called from zynq_slcr_reset_exit, external clocks are > assumed to be active, even if the > >> device state indicates a reset state. > >> > >> Signed-off-by: Michael Peter > >> --- > >> hw/misc/zynq_slcr.c | 12 ++++++------ > >> 1 file changed, 6 insertions(+), 6 deletions(-) > >> > >> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c > >> index a2b28019e3..073122b934 100644 > >> --- a/hw/misc/zynq_slcr.c > >> +++ b/hw/misc/zynq_slcr.c > >> @@ -269,12 +269,12 @@ static uint64_t zynq_slcr_compute_clock(const > uint64_t periods[], > >> * But do not propagate them further. Connected clocks > >> * will not receive any updates (See zynq_slcr_compute_clocks()) > >> */ > >> -static void zynq_slcr_compute_clocks(ZynqSLCRState *s) > >> +static void zynq_slcr_compute_clocks(ZynqSLCRState *s, bool > ignore_reset) > >> { > >> uint64_t ps_clk = clock_get(s->ps_clk); > >> > >> /* consider outputs clocks are disabled while in reset */ > >> - if (device_is_in_reset(DEVICE(s))) { > >> + if (!ignore_reset && device_is_in_reset(DEVICE(s))) { > >> ps_clk = 0; > >> } > >> > >> @@ -305,7 +305,7 @@ static void > zynq_slcr_propagate_clocks(ZynqSLCRState *s) > >> static void zynq_slcr_ps_clk_callback(void *opaque) > >> { > >> ZynqSLCRState *s = (ZynqSLCRState *) opaque; > >> - zynq_slcr_compute_clocks(s); > >> + zynq_slcr_compute_clocks(s, false); > >> zynq_slcr_propagate_clocks(s); > >> } > >> > >> @@ -410,7 +410,7 @@ static void zynq_slcr_reset_hold(Object *obj) > >> ZynqSLCRState *s = ZYNQ_SLCR(obj); > >> > >> /* will disable all output clocks */ > >> - zynq_slcr_compute_clocks(s); > >> + zynq_slcr_compute_clocks(s, false); > >> zynq_slcr_propagate_clocks(s); > >> } > >> > >> @@ -419,7 +419,7 @@ static void zynq_slcr_reset_exit(Object *obj) > >> ZynqSLCRState *s = ZYNQ_SLCR(obj); > >> > >> /* will compute output clocks according to ps_clk and registers */ > >> - zynq_slcr_compute_clocks(s); > >> + zynq_slcr_compute_clocks(s, true); > >> zynq_slcr_propagate_clocks(s); > >> } > >> > >> @@ -558,7 +558,7 @@ static void zynq_slcr_write(void *opaque, hwaddr > offset, > >> case R_ARM_PLL_CTRL: > >> case R_DDR_PLL_CTRL: > >> case R_UART_CLK_CTRL: > >> - zynq_slcr_compute_clocks(s); > >> + zynq_slcr_compute_clocks(s, false); > >> zynq_slcr_propagate_clocks(s); > >> break; > >> } > >> -- > >> 2.17.1 > > > --0000000000000e376905b8c8b6cc Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Wed, 13 Jan 2021, 11:19 Damien Hedde, <damien.hedde@greensocs.com> w= rote:

This is ok but I'm afraid we may end up doing this kind of thing in a lot of devices. So maybe we should consider changing the behavior of
device_is_in_reset() so that it returns false in the reset-exit case.
What do you think ? (I've a patch for this, which make this one useless= )

Thanks Damien,=C2=A0

IM= O, a central fix for this would be better, I agree with you.

Thanks,=C2=A0
= Edgar



But this patch does not harm so, anyway:
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
On 1/7/21 9:00 PM, Peter Maydell wrote:
> Alistair/Edgar/Damien -- could I get a review from one of you
> for this Xilinx clock-gen related patch, please?
>
> thanks
> -- PMM
>
> On Tue, 24 Nov 2020 at 18:54, Michael Peter
> <michael.peter@hensoldt-cyber.de> wrote:
>>
>> Pass an additional argument to zynq_slcr_compute_clocks that indic= ates whether an reset-exit condition
>> applies. If called from zynq_slcr_reset_exit, external clocks are = assumed to be active, even if the
>> device state indicates a reset state.
>>
>> Signed-off-by: Michael Peter <michael.peter@hensol= dt-cyber.de>
>> ---
>>=C2=A0 hw/misc/zynq_slcr.c | 12 ++++++------
>>=C2=A0 1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
>> index a2b28019e3..073122b934 100644
>> --- a/hw/misc/zynq_slcr.c
>> +++ b/hw/misc/zynq_slcr.c
>> @@ -269,12 +269,12 @@ static uint64_t zynq_slcr_compute_clock(cons= t uint64_t periods[],
>>=C2=A0 =C2=A0* But do not propagate them further. Connected clocks<= br> >>=C2=A0 =C2=A0* will not receive any updates (See zynq_slcr_compute_= clocks())
>>=C2=A0 =C2=A0*/
>> -static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
>> +static void zynq_slcr_compute_clocks(ZynqSLCRState *s, bool ignor= e_reset)
>>=C2=A0 {
>>=C2=A0 =C2=A0 =C2=A0 uint64_t ps_clk =3D clock_get(s->ps_clk); >>
>>=C2=A0 =C2=A0 =C2=A0 /* consider outputs clocks are disabled while = in reset */
>> -=C2=A0 =C2=A0 if (device_is_in_reset(DEVICE(s))) {
>> +=C2=A0 =C2=A0 if (!ignore_reset && device_is_in_reset(DEV= ICE(s))) {
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ps_clk =3D 0;
>>=C2=A0 =C2=A0 =C2=A0 }
>>
>> @@ -305,7 +305,7 @@ static void zynq_slcr_propagate_clocks(ZynqSLC= RState *s)
>>=C2=A0 static void zynq_slcr_ps_clk_callback(void *opaque)
>>=C2=A0 {
>>=C2=A0 =C2=A0 =C2=A0 ZynqSLCRState *s =3D (ZynqSLCRState *) opaque;=
>> -=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s);
>> +=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s, false);
>>=C2=A0 =C2=A0 =C2=A0 zynq_slcr_propagate_clocks(s);
>>=C2=A0 }
>>
>> @@ -410,7 +410,7 @@ static void zynq_slcr_reset_hold(Object *obj)<= br> >>=C2=A0 =C2=A0 =C2=A0 ZynqSLCRState *s =3D ZYNQ_SLCR(obj);
>>
>>=C2=A0 =C2=A0 =C2=A0 /* will disable all output clocks */
>> -=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s);
>> +=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s, false);
>>=C2=A0 =C2=A0 =C2=A0 zynq_slcr_propagate_clocks(s);
>>=C2=A0 }
>>
>> @@ -419,7 +419,7 @@ static void zynq_slcr_reset_exit(Object *obj)<= br> >>=C2=A0 =C2=A0 =C2=A0 ZynqSLCRState *s =3D ZYNQ_SLCR(obj);
>>
>>=C2=A0 =C2=A0 =C2=A0 /* will compute output clocks according to ps_= clk and registers */
>> -=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s);
>> +=C2=A0 =C2=A0 zynq_slcr_compute_clocks(s, true);
>>=C2=A0 =C2=A0 =C2=A0 zynq_slcr_propagate_clocks(s);
>>=C2=A0 }
>>
>> @@ -558,7 +558,7 @@ static void zynq_slcr_write(void *opaque, hwad= dr offset,
>>=C2=A0 =C2=A0 =C2=A0 case R_ARM_PLL_CTRL:
>>=C2=A0 =C2=A0 =C2=A0 case R_DDR_PLL_CTRL:
>>=C2=A0 =C2=A0 =C2=A0 case R_UART_CLK_CTRL:
>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 zynq_slcr_compute_clocks(s);
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 zynq_slcr_compute_clocks(s, false); >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 zynq_slcr_propagate_clocks(s); >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
>>=C2=A0 =C2=A0 =C2=A0 }
>> --
>> 2.17.1
>
--0000000000000e376905b8c8b6cc-- From MAILER-DAEMON Wed Jan 13 09:17:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzgxn-00053e-7b for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 09:17:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzgxa-0004yr-5C; Wed, 13 Jan 2021 09:17:18 -0500 Received: from mail-qk1-x72c.google.com ([2607:f8b0:4864:20::72c]:37966) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzgxS-0008Oc-TI; Wed, 13 Jan 2021 09:17:17 -0500 Received: by mail-qk1-x72c.google.com with SMTP id w79so1613542qkb.5; Wed, 13 Jan 2021 06:17:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LF1Fy4jeI0H7TalFf58EAHuobdYdkV3MVe+lGLmUtAk=; b=YPYu2gggyyHfhxJd+QrRnooSJwlI2CACv85zlw3qHkIq5kFwoJ4ou6dRNFLKgjSSVt nBr894jRJNbcb5jfDdMVpX+9dC/9y70cqJPJt0js+W9BafLBzU+hhDsgH+uahDc/FaVu nS0Vl26o57xhEj+PE6j98fGp+qGtn5hclQYUvlmIGQrAT2hGUm8IcuQxT+60Ivz+537+ HZGmAfbBKoxQXb5k77vu0LO0QN7+IphOW0VtNDGsBbb3R9rcVuPsnxGn/1wARD+p9uLU uOtNDzp3ZWJOeCjsmP9XdaO8wA4NVMuA/SOYrxmcIAIdWpuBk4hVAEQqL8DrFgfkED7L zoZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LF1Fy4jeI0H7TalFf58EAHuobdYdkV3MVe+lGLmUtAk=; b=D+uD+BJWs5ZYK+RrBhE8NxF2Jlxej0fp8KLkaXrOtw9j8Hw8CsW1FdX0oCepMR2nXh PNVqCUUvkhW3My0FCgRQhPe/RcMBI7YKjCYERwL6MqbLg00XkTQG046/spTp24ybvJch 6RVV5e/4pHTtvMqLndmKG8iw/6Iye7sbUa4j5Z7I3+2uLjyqEdzx296O+0WBvV79qehI t8rwXh+S27prGaoWPn9SW+6kpeKT3y81VMd4yonFjKgio0ARAaoEKqJYo0iMfP0+tOtD 6v50oP2Y5Vn15T3uEdGd8z7XtBHuhf6HsP2zGuRgOTtlA+YWF8Ht71zlZD/tTCFV7GT0 XjdQ== X-Gm-Message-State: AOAM533pJH2yHp/DOCkiEdWNO6qHKJahIT435+M3RSdYyCFbXSezY515 hfUerlnb5zHrPJ8NYPj5U9EqIBuvMOWTyvOQ7DY= X-Google-Smtp-Source: ABdhPJw0Zq5JpiynlCVTWhqx+/c7/NrlzM+/54ZapuUVZm9yO6aZGxZUiBnf9pfQeWWBf7l30NmdrlWqbYkpMmFR93E= X-Received: by 2002:a25:690b:: with SMTP id e11mr3414947ybc.314.1610547429104; Wed, 13 Jan 2021 06:17:09 -0800 (PST) MIME-Version: 1.0 References: <20210112183529.2011863-1-f4bug@amsat.org> <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> In-Reply-To: From: Bin Meng Date: Wed, 13 Jan 2021 22:16:58 +0800 Message-ID: Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Bin Meng , Xuzhou Cheng , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: multipart/mixed; boundary="000000000000686a6005b8c8cb41" Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=bmeng.cn@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 14:17:25 -0000 --000000000000686a6005b8c8cb41 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, On Wed, Jan 13, 2021 at 9:27 PM Bin Meng wrote: > > Hi Philippe, > > On Wed, Jan 13, 2021 at 3:53 PM Philippe Mathieu-Daud=C3=A9 wrote: > > > > Hi Ben, > > > > On 1/13/21 4:29 AM, Bin Meng wrote: > > > On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daud=C3=A9 wrote: > > >> > > >> Hi, > > >> > > >> As it is sometimes harder for me to express myself in plain > > >> English, I found it easier to write the patches I was thinking > > >> about. I know this doesn't scale. > > >> > > >> So this is how I understand the ecSPI reset works, after > > >> looking at the IMX6DQRM.pdf datasheet. > > >> > > >> This is a respin of Ben's v5 series [*]. > > >> Tagged RFC because I have not tested it :) > > > > > > Unfortunately this series breaks SPI flash testing under both U-Boot > > > and VxWorks 7. > > > > Thanks for testing :) Can you provide the binary tested and the command > > line used? At least one, so I can have a look. > > Sure, will send you offline. Please use attached u-boot image to test. You will also need the following additional QEMU patches: http://patchwork.ozlabs.org/project/qemu-devel/patch/1606704602-59435-1-git= -send-email-bmeng.cn@gmail.com/ http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D221754 $ qemu-system-arm -display none -serial null -serial stdio -M sabrelite -m 1G -kernel u-boot =3D> sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total = 2 MiB =3D> sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 2 ticks, 2000 KiB/s 16.000 Mbps 2 write: 187 ticks, 21 KiB/s 0.168 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 2 ticks, 2000 KiB/s 16.000 Mbps 2 write: 187 ticks, 21 KiB/s 0.168 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Regards, Bin --000000000000686a6005b8c8cb41 Content-Type: application/octet-stream; name=u-boot Content-Disposition: attachment; filename=u-boot Content-Transfer-Encoding: base64 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[79.178.32.166]) by smtp.gmail.com with ESMTPSA id u6sm3960698wrm.90.2021.01.13.06.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 06:17:22 -0800 (PST) Date: Wed, 13 Jan 2021 09:17:19 -0500 From: "Michael S. Tsirkin" To: Marian Posteuca Cc: Igor Mammedov , Peter Maydell , Eduardo Habkost , Sergio Lopez , Ben Warren , Richard Henderson , qemu-devel@nongnu.org, Dongjiu Geng , Shannon Zhao , Xiang Zheng , qemu-arm@nongnu.org, Paolo Bonzini , Xiao Guangrong Subject: Re: [PATCH v3] acpi: Permit OEM ID and OEM table ID fields to be changed Message-ID: <20210113091555-mutt-send-email-mst@kernel.org> References: <20201230221302.26800-1-posteuca@mutex.one> <20210106182430.6bf1823a@redhat.com> <87bldvldsl.fsf@mutex.one> MIME-Version: 1.0 In-Reply-To: <87bldvldsl.fsf@mutex.one> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 14:17:33 -0000 On Mon, Jan 11, 2021 at 04:59:54PM +0200, Marian Posteuca wrote: > Igor Mammedov writes: > > > overall looks good. > > Please add a test case for it, see > > tests/qtest/bios-tables-test.c for description how to do it > > an/or at > > "[PATCH v3 08/12] tests/acpi: allow updates for expected data files" > > and follow up patches on the list. > When you say add a test case, do you mean only updating the binary > files in tests/data/acpi/{microvm,pc,q35,virt} according to the steps > at the start of the file bios-tables-test.c? Or do you also mean an actual > test case to be added in bios-tables-test.c? > > Also the step 6 described in bios-tables-test.c mentions that the diff of > the ACPI table must be added to the commit log, but my change touches > all the tables for all architectures so that would mean that I would > have to create a huge commit log. How should I approach this? If the changes are the same, you can just write: the change is the same across all architectures, and show it. Something I just tripped over: make sure not to include "---" lines in the diff. Otherwise git am can not apply the resulting patch. -- MST From MAILER-DAEMON Wed Jan 13 10:07:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzhkE-0000xu-Qr for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 10:07:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzhkC-0000vj-OG; Wed, 13 Jan 2021 10:07:33 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:52098) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzhk9-0005I8-US; Wed, 13 Jan 2021 10:07:31 -0500 Received: by mail-wm1-x330.google.com with SMTP id h17so1707945wmq.1; Wed, 13 Jan 2021 07:07:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=JU0rEPktICofuJE6bNsBeUhhODIrPOx5iYAwhAA+TxA=; b=O/U7LFZyilzoQW4LIG4QWlrsUeChNs7uMCt67VW7rC88mfEE1aGGWSUucUzPBsEBqc QeQlirP7pVprIvpJZVSqt6St7L1bo3r54j9GfxX/hPjYrSKl7e2oJASgzWTZnnTYimt4 yiTvmnvjiOzFk2Bo69e2dVltdN9eVBOqEYSmRKzdb8yTuF2HUbGvPuL2qsw/5vzqSJUm 56BBSeLEW3jogwiX0eIZ38DrNcR/LLIO/DBW9AJFqcDsCn8l4YuI8grg2KDug/OqaT15 oGB+FMoFTs2BqvBoHpDQg40UD1b7P761FlwnegHA/M9oSVYgatm/1wK0T48AIoxtVhso 1Agg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=JU0rEPktICofuJE6bNsBeUhhODIrPOx5iYAwhAA+TxA=; b=IIwBcNfOlCJgyp7xYpIioya8VkpyBup6I+NVw5uI+FR7SZDqDHOM+kaisLMUlkMFsm +7kgksez4FarPf1/eplXXg2ORNOOWXebx2wPQ5R6J0ruEXDyQa0j05v5VtMSkzYJv5d0 GXwyS4IL9qT0+t5YOt9ElbZ0dyO/LfxXiNYUuTFwtGsvLqfKzWlGLIEYX8tq9dlX5FYs 80MQjng+M5q3Yed/wc1HzYpA++d0DWwa2QoIgUleK/Xvy10rYSdG3gAV8bhpPeM71G1O yuJijNYLk0fSlyjqg3NUSil1QlfMAKgOmUkZ8RSNgk5sainF5Xl3K4oqKulsZ0F3Hg4B 1RsA== X-Gm-Message-State: AOAM531CRAY+5RFjwgbVrCxvYgWdB4OjBS2ej0VF2YjIFadvLb0stWIv M2jrFux0l8ig15/ZAZ+On+0= X-Google-Smtp-Source: ABdhPJyqvVb9LeBE4Wjqu6s1VR1vsbimhpvAjgpfZ+EhLyjTHHm4lMNZABhyXBXDIaZG+hSwcgCu7Q== X-Received: by 2002:a05:600c:2292:: with SMTP id 18mr2652046wmf.181.1610550446101; Wed, 13 Jan 2021 07:07:26 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u26sm3244203wmm.24.2021.01.13.07.07.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 07:07:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements To: Richard Henderson , qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Cornelia Huck , qemu-riscv@nongnu.org, Stefan Weil , Huacai Chen , Thomas Huth , Jiaxun Yang , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Palmer Dabbelt , Andrzej Zaborowski , Aurelien Jarno References: <20210111150114.1415930-1-f4bug@amsat.org> <43f360be-af44-27ce-619b-7a2ad169aa2f@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 13 Jan 2021 16:07:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <43f360be-af44-27ce-619b-7a2ad169aa2f@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 15:07:33 -0000 On 1/11/21 6:22 PM, Richard Henderson wrote: > On 1/11/21 5:01 AM, Philippe Mathieu-Daudé wrote: >> Attempt to fix the warning reported by Miroslav using GCC 10: >> https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html >> >> Philippe Mathieu-Daudé (5): >> tcg/arm: Hoist common argument loads in tcg_out_op() >> tcg/ppc: Hoist common argument loads in tcg_out_op() >> tcg/s390: Hoist common argument loads in tcg_out_op() >> tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements >> tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements > > I've been trying to figure out a cleaner way to handle these, but this is > certainly ok for now, and avoids the Werror. > > Reviewed-by: Richard Henderson > > Will queue to tcg-next. Please hold on, Miroslav found a regression in the PPC patch. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id b132sm3659535wmh.21.2021.01.13.07.25.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 07:25:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op() To: Richard Henderson , Miroslav Rezanina Cc: qemu-devel@nongnu.org, Aleksandar Rikalo , Cornelia Huck , qemu-riscv@nongnu.org, Stefan Weil , Huacai Chen , Thomas Huth , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Palmer Dabbelt , Aurelien Jarno References: <20210111150114.1415930-1-f4bug@amsat.org> <20210111150114.1415930-3-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 13 Jan 2021 16:25:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210111150114.1415930-3-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 15:25:30 -0000 On 1/11/21 4:01 PM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > tcg/ppc/tcg-target.c.inc | 294 ++++++++++++++++++--------------------- > 1 file changed, 138 insertions(+), 156 deletions(-) ... > @@ -2818,10 +2805,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, > case INDEX_op_bswap32_i32: > case INDEX_op_bswap32_i64: > /* Stolen from gcc's builtin_bswap32 */ > - a1 = args[1]; > - a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; > + a0 = a0 == a1 ? TCG_REG_R0 : a0; Oops... Here is probably the regression reported by Miroslav, I shouldn't have changed this line, simply remove the a1 assignment: - a1 = args[1]; a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; > > - /* a1 = args[1] # abcd */ > + /* a1 = a1 # abcd */ > /* a0 = rotate_left (a1, 8) # bcda */ > tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); > /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ ... 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id o14sm3721342wri.48.2021.01.13.07.49.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 07:49:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 2/5] tcg/ppc: Hoist common argument loads in tcg_out_op() From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Richard Henderson , Miroslav Rezanina Cc: Aleksandar Rikalo , Huacai Chen , qemu-riscv@nongnu.org, Stefan Weil , Cornelia Huck , qemu-devel@nongnu.org, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Thomas Huth , Palmer Dabbelt , Aurelien Jarno References: <20210111150114.1415930-1-f4bug@amsat.org> <20210111150114.1415930-3-f4bug@amsat.org> Message-ID: <7baba218-340a-9426-6933-0024e0d4110d@amsat.org> Date: Wed, 13 Jan 2021 16:49:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 15:49:16 -0000 On 1/13/21 4:25 PM, Philippe Mathieu-Daudé wrote: > On 1/11/21 4:01 PM, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> tcg/ppc/tcg-target.c.inc | 294 ++++++++++++++++++--------------------- >> 1 file changed, 138 insertions(+), 156 deletions(-) > ... > >> @@ -2818,10 +2805,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, >> case INDEX_op_bswap32_i32: >> case INDEX_op_bswap32_i64: >> /* Stolen from gcc's builtin_bswap32 */ >> - a1 = args[1]; >> - a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; >> + a0 = a0 == a1 ? TCG_REG_R0 : a0; > > Oops... Here is probably the regression reported by Miroslav, > I shouldn't have changed this line, simply remove the a1 Oops^2, wrong hunk =) Following one... > >> >> - /* a1 = args[1] # abcd */ >> + /* a1 = a1 # abcd */ >> /* a0 = rotate_left (a1, 8) # bcda */ >> tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); >> /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ @@ -2830,12 +2816,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); Here, is the line I shouldn't have changed: if (a0 == TCG_REG_R0) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + tcg_out_mov(s, TCG_TYPE_REG, a0, a0); } break; (multiple occurrences). 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id h9sm4030774wre.24.2021.01.13.09.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 0/6] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Date: Wed, 13 Jan 2021 18:24:53 +0100 Message-Id: <20210113172459.2481060-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:07 -0000 Since v1:=0D - Redo the whole change, only hoisting when variable is used 10+ times=0D - Remove goto statement/label=0D - Take care of the following pattern:=0D =0D case INDEX_op_bswap64_i64:=0D a2 =3D3D TCG_REG_R0;=0D if (a0 =3D3D=3D3D a1) {=0D a0 =3D3D TCG_REG_R0;=0D a2 =3D3D a1;=0D }=0D ...=0D if (a0 =3D3D=3D3D 0) {=0D tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);=0D ^^^^ take original a[0]=0D }=0D =0D Attempt to fix the warning reported by Miroslav using GCC 10:=0D https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html=0D =0D Diff with v1:=0D =0D Key:=0D [----] : patches are identical=0D [####] : number of functional differences between upstream/downstream patch= =0D [down] : patch is downstream-only=0D The flags [FC] indicate (F)unctional and (C)ontextual differences, respecti= ve=3D=0D ly=0D =0D 001/6:[0063] [FC] 'tcg/arm: Hoist common argument loads in tcg_out_op()'=0D 002/6:[down] 'tcg/arm: Replace goto statement by fall through comment'=0D 003/6:[0190] [FC] 'tcg/ppc: Hoist common argument loads in tcg_out_op()'=0D 004/6:[0136] [FC] 'tcg/s390: Hoist common argument loads in tcg_out_op()'=0D 005/6:[----] [--] 'tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS = el=3D=0D ements'=0D 006/6:[----] [--] 'tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_A= RG=3D=0D S elements'=0D =0D Philippe Mathieu-Daud=3DC3=3DA9 (6):=0D tcg/arm: Hoist common argument loads in tcg_out_op()=0D tcg/arm: Replace goto statement by fall through comment=0D tcg/ppc: Hoist common argument loads in tcg_out_op()=0D tcg/s390: Hoist common argument loads in tcg_out_op()=0D tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements=0D tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements=0D =0D tcg/tcg.c | 19 +--=0D tcg/aarch64/tcg-target.c.inc | 3 +-=0D tcg/arm/tcg-target.c.inc | 196 +++++++++++++++----------------=0D tcg/i386/tcg-target.c.inc | 6 +-=0D tcg/mips/tcg-target.c.inc | 3 +-=0D tcg/ppc/tcg-target.c.inc | 191 ++++++++++++++----------------=0D tcg/riscv/tcg-target.c.inc | 3 +-=0D tcg/s390/tcg-target.c.inc | 222 +++++++++++++++++------------------=0D tcg/tci/tcg-target.c.inc | 5 +-=0D 9 files changed, 311 insertions(+), 337 deletions(-)=0D =0D --=3D20=0D 2.26.2=0D =0D From MAILER-DAEMON Wed Jan 13 12:25:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzjtR-0008JA-Ld for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id t16sm4002751wmi.3.2021.01.13.09.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 1/6] tcg/arm: Hoist common argument loads in tcg_out_op() Date: Wed, 13 Jan 2021 18:24:54 +0100 Message-Id: <20210113172459.2481060-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:12 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/arm/tcg-target.c.inc | 192 +++++++++++++++++++-------------------- 1 file changed, 92 insertions(+), 100 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0fd11264544..59bd196994f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1747,15 +1747,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) static void tcg_out_epilogue(TCGContext *s); -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2, a3, a4, a5; - int c; + int c, c2; + + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + a3 = args[3]; + c2 = const_args[2]; switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, a0); tcg_out_epilogue(s); break; case INDEX_op_goto_tb: @@ -1765,7 +1773,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGReg base = TCG_REG_PC; tcg_debug_assert(s->tb_jmp_insn_offset == 0); - ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + args[0]); + ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0); dif = tcg_pcrel_diff(s, (void *)ptr) - 8; dil = sextract32(dif, 0, 12); if (dif != dil) { @@ -1778,74 +1786,68 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi32(s, COND_AL, base, ptr - dil); } tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); } break; case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); + tcg_out_bx(s, COND_AL, a0); break; case INDEX_op_br: - tcg_out_goto_label(s, COND_AL, arg_label(args[0])); + tcg_out_goto_label(s, COND_AL, arg_label(a0)); break; case INDEX_op_ld8u_i32: - tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld8s_i32: - tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld8s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16u_i32: - tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16u(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld16s_i32: - tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld16s(s, COND_AL, a0, a1, a2); break; case INDEX_op_ld_i32: - tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); + tcg_out_ld32u(s, COND_AL, a0, a1, a2); break; case INDEX_op_st8_i32: - tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st8(s, COND_AL, a0, a1, a2); break; case INDEX_op_st16_i32: - tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st16(s, COND_AL, a0, a1, a2); break; case INDEX_op_st_i32: - tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_st32(s, COND_AL, a0, a1, a2); break; case INDEX_op_movcond_i32: /* Constraints mean that v2 is always in the same register as dest, * so we only need to do "if condition passed, move v1 to dest". */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a1, a2, c2); tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, - ARITH_MVN, args[0], 0, args[3], const_args[3]); + ARITH_MVN, a0, 0, a3, const_args[3]); break; case INDEX_op_add_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, a0, a1, a2, c2); break; case INDEX_op_sub_i32: if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + if (c2) { + tcg_out_movi32(s, COND_AL, a0, a1 - a2); } else { - tcg_out_dat_rI(s, COND_AL, ARITH_RSB, - args[0], args[2], args[1], 1); + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, a0, a2, a1, 1); } } else { - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, a0, a1, a2, c2); } break; case INDEX_op_and_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, a0, a1, a2, c2); break; case INDEX_op_andc_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, a0, a1, a2, c2); break; case INDEX_op_or_i32: c = ARITH_ORR; @@ -1854,11 +1856,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, c = ARITH_EOR; /* Fall through. */ gen_arith: - tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); + tcg_out_dat_rI(s, COND_AL, c, a0, a1, a2, c2); break; case INDEX_op_add2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; + a4 = args[4], a5 = args[5]; if (a0 == a3 || (a0 == a5 && !const_args[5])) { a0 = TCG_REG_TMP; } @@ -1866,15 +1867,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0, a2, a4, const_args[4]); tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, a1, a3, a5, const_args[5]); - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_sub2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; + a4 = args[4], a5 = args[5]; if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { a0 = TCG_REG_TMP; } - if (const_args[2]) { + if (c2) { if (const_args[4]) { tcg_out_movi32(s, COND_AL, a0, a4); a4 = a0; @@ -1884,7 +1884,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); } - if (const_args[3]) { + if (const_a3) { if (const_args[5]) { tcg_out_movi32(s, COND_AL, a1, a5); a5 = a1; @@ -1894,69 +1894,64 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, a1, a3, a5, const_args[5]); } - tcg_out_mov_reg(s, COND_AL, args[0], a0); + tcg_out_mov_reg(s, COND_AL, a0, a0); break; case INDEX_op_neg_i32: - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, a0, a1, 0); break; case INDEX_op_not_i32: - tcg_out_dat_reg(s, COND_AL, - ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_AL, ARITH_MVN, a0, 0, a1, SHIFT_IMM_LSL(0)); break; case INDEX_op_mul_i32: - tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); + tcg_out_mul32(s, COND_AL, a0, a1, a2); break; case INDEX_op_mulu2_i32: - tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_umull32(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_muls2_i32: - tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_smull32(s, COND_AL, a0, a1, a2, a3); break; - /* XXX: Perhaps args[2] & 0x1f is wrong */ + /* XXX: Perhaps a2 & 0x1f is wrong */ case INDEX_op_shl_i32: - c = const_args[2] ? - SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); + c = c2 ? SHIFT_IMM_LSL(a2 & 0x1f) : SHIFT_REG_LSL(a2); goto gen_shift32; case INDEX_op_shr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); + c = c2 ? (a2 & 0x1f) ? SHIFT_IMM_LSR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(a2); goto gen_shift32; case INDEX_op_sar_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); + c = c2 ? (a2 & 0x1f) ? SHIFT_IMM_ASR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(a2); goto gen_shift32; case INDEX_op_rotr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); + c = c2 ? (a2 & 0x1f) ? SHIFT_IMM_ROR(a2 & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(a2); /* Fall through. */ gen_shift32: - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, c); break; case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], - ((0x20 - args[2]) & 0x1f) ? - SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : + if (c2) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, + ((0x20 - a2) & 0x1f) ? + SHIFT_IMM_ROR((0x20 - a2) & 0x1f) : SHIFT_IMM_LSL(0)); } else { - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, a2, 0x20); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ROR(TCG_REG_TMP)); } break; case INDEX_op_ctz_i32: - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); + tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); a1 = TCG_REG_TMP; goto do_clz; case INDEX_op_clz_i32: - a1 = args[1]; do_clz: - a0 = args[0]; - a2 = args[2]; - c = const_args[2]; + c = c2; if (c && a2 == 32) { tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); break; @@ -1970,17 +1965,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_brcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[0], args[1], const_args[1]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], - arg_label(args[3])); + a0, a1, const_args[1]); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[a2], arg_label(a3)); break; case INDEX_op_setcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], - ARITH_MOV, args[0], 0, 0); + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a1, a2, c2); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[a3], + ARITH_MOV, a0, 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(a3)], + ARITH_MOV, a0, 0, 0); break; case INDEX_op_brcond2_i32: @@ -1989,9 +1982,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_setcond2_i32: c = tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, a0, 0, 1); tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], - ARITH_MOV, args[0], 0, 0); + ARITH_MOV, a0, 0, 0); break; case INDEX_op_qemu_ld_i32: @@ -2008,63 +2001,62 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, COND_AL, args[0], args[1]); + tcg_out_bswap16(s, COND_AL, a0, a1); break; case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, COND_AL, args[0], args[1]); + tcg_out_bswap32(s, COND_AL, a0, a1); break; case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, COND_AL, args[0], args[1]); + tcg_out_ext8s(s, COND_AL, a0, a1); break; case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, COND_AL, args[0], args[1]); + tcg_out_ext16s(s, COND_AL, a0, a1); break; case INDEX_op_ext16u_i32: - tcg_out_ext16u(s, COND_AL, args[0], args[1]); + tcg_out_ext16u(s, COND_AL, a0, a1); break; case INDEX_op_deposit_i32: - tcg_out_deposit(s, COND_AL, args[0], args[2], - args[3], args[4], const_args[2]); + tcg_out_deposit(s, COND_AL, a0, a2, a3, args[4], c2); break; case INDEX_op_extract_i32: - tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_extract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_sextract_i32: - tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); + tcg_out_sextract(s, COND_AL, a0, a1, a2, a3); break; case INDEX_op_extract2_i32: /* ??? These optimization vs zero should be generic. */ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); + if (c2) { + tcg_out_movi(s, TCG_TYPE_REG, a0, 0); } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a2, SHIFT_IMM_LSL(32 - a3)); } - } else if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[1], SHIFT_IMM_LSR(args[3])); + } else if (c2) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, + a1, SHIFT_IMM_LSR(a3)); } else { /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, - args[1], SHIFT_IMM_LSR(args[3])); + a2, SHIFT_IMM_LSL(32 - a3)); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, a0, TCG_REG_TMP, + a1, SHIFT_IMM_LSR(a3)); } break; case INDEX_op_div_i32: - tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_sdiv(s, COND_AL, a0, a1, a2); break; case INDEX_op_divu_i32: - tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + tcg_out_udiv(s, COND_AL, a0, a1, a2); break; case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ -- 2.26.2 From MAILER-DAEMON Wed Jan 13 12:25:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzjtV-0008Ss-Vc for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 12:25:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzjtT-0008OH-Tn; Wed, 13 Jan 2021 12:25:15 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:40120) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzjtS-000615-EV; Wed, 13 Jan 2021 12:25:15 -0500 Received: by mail-wm1-x333.google.com with SMTP id r4so2322142wmh.5; Wed, 13 Jan 2021 09:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=usrEFBYIAmEVHDsTWIk9Dyh2ylL3MFnazze4ohg6L4U=; b=n+uHkJVJ6i1JqI7gFzbPdWDu+Gn1CcBZWSKXZ5DOTJ1tjmIRSKgzh0QpZSY52pIMoS ya6tE0zpVGf9pYrBpM0V0gdY1hX3kdEEoswJi+UruZDj3KiM8COI3b2Cm+30zvTR1BjZ FdxVsiNedQOcHVP9Ar4qTOB3aEe7Ir+xc6wBRyu/nMFcVdqgDfTE03lT5MUILJXR20Nk EUnQu7A68Ae4Nb5iP2ZsRqhG8xh78+LEyCFLZF3j4qCJh56hI3SGnzKtTctLMDtVECfi 1AnBloHq2TlxGjNp3TKAZZUUOGp22B/CKFTdpb40d8wMSeXWG9N+qMQ/h+/6zl4OMqI0 oVsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=usrEFBYIAmEVHDsTWIk9Dyh2ylL3MFnazze4ohg6L4U=; b=MW8YCBMiXivJMZAo6BzYrDd1hVPVbdZ9N5zYW8tg+k8WGXZqbpgchF47K5bGVdR+U4 izVsVyPL+FIWWITLeYWb/Uw8X48h92Cc6GfxOZE0VBn+5U7vO0scQH4w9P3GmNrKiUvh T9lf0Ea/ip3D45kgY811D/SY8R9bGC+mIylPtjaUs8GOlR2nuiK2D0wF9JnOzn+tTVY1 na3XcP0JgHWYYngWvPujFhAgF6wlaRdzY2tXccfOAOUEJJKdZZpMRIbdqMIs7pbSVXBC Wmqw07asWKwKAV3YokzKsGas8Dk9wKShX8wmhedlb+VPdDJ9K8QjpwT9UTbtnK4LxoEo bE8g== X-Gm-Message-State: AOAM533GpR6Xb6i9APVnu7+p+/vkPMfcUjHA7EQ2KYJmTwyxtI51iAPc FKNyDPVc70IexY25dQ2cFycX4a/xypc= X-Google-Smtp-Source: ABdhPJyPlpkTHbnTw9WKTtial8bvcn3XXZzC0q06/RaW2FvQp3GMJGSSJImDnrHGCye7YlLnLFJjUw== X-Received: by 2002:a1c:98c7:: with SMTP id a190mr281162wme.184.1610558711983; Wed, 13 Jan 2021 09:25:11 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id o23sm4912400wro.57.2021.01.13.09.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 2/6] tcg/arm: Replace goto statement by fall through comment Date: Wed, 13 Jan 2021 18:24:55 +0100 Message-Id: <20210113172459.2481060-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:16 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/arm/tcg-target.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 59bd196994f..0ffb2b13d14 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1947,10 +1947,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ctz_i32: tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, a1, 0); a1 = TCG_REG_TMP; - goto do_clz; - + /* Fall through. */ case INDEX_op_clz_i32: - do_clz: c = c2; if (c && a2 == 32) { tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); -- 2.26.2 From MAILER-DAEMON Wed Jan 13 12:25:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzjtx-0000B6-EH for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 12:25:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzjta-00008A-U6; Wed, 13 Jan 2021 12:25:22 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:41523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzjtY-00063H-A2; Wed, 13 Jan 2021 12:25:22 -0500 Received: by mail-wr1-x430.google.com with SMTP id a12so2952710wrv.8; Wed, 13 Jan 2021 09:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cGAPxmq968bmJMMpj0rkaQPnnLWtPOzEXjKRRKbvSdA=; b=CjqDk99CHQvO8S5MphJazHsM3oTPO5KmXjVcAja4K50Zty9GvOr2KB4u7wbL51E5ad GJfXYHxpE22HSyWFbxgE3m7rRVTpLL8uYfn7FFBEDN67nueb2KDmxGgNSWbsLWS2o7uR p9iXqmHgErwQxWUO7oLtH7EIbn9U1xrUcua17cl55b3OO5Yk1gF6B5Tz4PsNQLzXfrGh j1ok/O9S/fT2yOwgFElA1zdtuN//KRzxAYn0RzbJW2RpuhcBXE2r05H+0xwBlTawl7jS OJaJMD3YzLA8z5UqjrSHJQFFr5eCwkGpVdrdh6pS8CTcI978zec7QiaKVp/CFcPXxC5i XVTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cGAPxmq968bmJMMpj0rkaQPnnLWtPOzEXjKRRKbvSdA=; b=VCIkCu77z2+8O0/uNgfZmkB55EWMS50J4wAJHJgqYsGVM+AApKQtLm7gKqBJd1SkCN 5JcOTiEtai4+iDAkZYWn5lQM1fzcwqJhqEeGD2anoVLBYzXzhEVwBPRzBUS810be5AD4 pR5nej3R9zo7eYrxJHQf0CW83MaGrmcN3CLdDrFyviUla/+RYuojTDKQQSRpSkH72lhQ RWqP7H0UyBI33grjJjFeO6PAfsx9Ug/FMp0Ip3aDa5HNZOO88V+NdBh9JNZvi/RxHqES Uhm95sghNM9zQ+GCBqbRjuWR2WQE1MC3/qNqbaebin96ywifr4Gs0iX2nif5Dem5MuQA AyKw== X-Gm-Message-State: AOAM530B5wQa9rTm/nn1cdN9l6rIbgtUUmtjwXxAucxxrH9IhfPTlIex +Zn40NUY+oSssJXa3+KUw+j3LVL7MFQ= X-Google-Smtp-Source: ABdhPJydaTS+KX3Igjbxc9bK8IoRQxNi+fARF+o7Od0eYSU9SbpR/y8panhJhZSYfLo+Qh23qCMLyg== X-Received: by 2002:a5d:53c9:: with SMTP id a9mr3605687wrw.188.1610558717338; Wed, 13 Jan 2021 09:25:17 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id l20sm4835123wrh.82.2021.01.13.09.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op() Date: Wed, 13 Jan 2021 18:24:56 +0100 Message-Id: <20210113172459.2481060-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:38 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/ppc/tcg-target.c.inc | 188 ++++++++++++++++++--------------------- 1 file changed, 85 insertions(+), 103 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 19a4a12f155..70b747a8a30 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2357,15 +2357,22 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCLR | BO_ALWAYS); } -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; - int c; + int c, c2; + + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c2 = const_args[2]; switch (opc) { case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, a0); tcg_out_b(s, 0, tcg_code_gen_epilogue); break; case INDEX_op_goto_tb: @@ -2389,11 +2396,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, /* Indirect jump. */ tcg_debug_assert(s->tb_jmp_insn_offset == NULL); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, - (intptr_t)(s->tb_jmp_insn_offset + args[0])); + (intptr_t)(s->tb_jmp_insn_offset + a0)); } tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, args[0]); + set_jmp_reset_offset(s, a0); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, @@ -2403,7 +2410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); @@ -2424,49 +2431,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); break; case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); break; case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i64: - tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHZ, LHZX, a0, a1, a2); break; case INDEX_op_ld16s_i32: case INDEX_op_ld16s_i64: - tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LHA, LHAX, a0, a1, a2); break; case INDEX_op_ld_i32: case INDEX_op_ld32u_i64: - tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWZ, LWZX, a0, a1, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LWA, LWAX, a0, a1, a2); break; case INDEX_op_ld_i64: - tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, LD, LDX, a0, a1, a2); break; case INDEX_op_st8_i32: case INDEX_op_st8_i64: - tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STB, STBX, a0, a1, a2); break; case INDEX_op_st16_i32: case INDEX_op_st16_i64: - tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STH, STHX, a0, a1, a2); break; case INDEX_op_st_i32: case INDEX_op_st32_i64: - tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STW, STWX, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); + tcg_out_mem_long(s, STD, STDX, a0, a1, a2); break; case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { do_addi_32: tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); @@ -2475,7 +2481,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[1]) { if (const_args[2]) { tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); @@ -2491,7 +2496,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, a2); } else { @@ -2499,7 +2503,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, a2); } else { @@ -2508,7 +2511,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_or_i64: case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_ori32(s, a0, a1, a2); } else { @@ -2517,7 +2519,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_xor_i64: case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_xori32(s, a0, a1, a2); } else { @@ -2525,7 +2526,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, ~a2); } else { @@ -2533,7 +2533,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, ~a2); } else { @@ -2542,57 +2541,52 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_orc_i32: if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); + tcg_out_ori32(s, a0, a1, ~args[2]); break; } /* FALLTHRU */ case INDEX_op_orc_i64: - tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + tcg_out32(s, ORC | SAB(args[1], a0, a2)); break; case INDEX_op_eqv_i32: if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); + tcg_out_xori32(s, a0, a1, ~args[2]); break; } /* FALLTHRU */ case INDEX_op_eqv_i64: - tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + tcg_out32(s, EQV | SAB(args[1], a0, a2)); break; case INDEX_op_nand_i32: case INDEX_op_nand_i64: - tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + tcg_out32(s, NAND | SAB(args[1], a0, a2)); break; case INDEX_op_nor_i32: case INDEX_op_nor_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + tcg_out32(s, NOR | SAB(args[1], a0, a2)); break; case INDEX_op_clz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, a0, a1, a2, const_args[2]); break; case INDEX_op_ctz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, a0, a1, a2, const_args[2]); break; case INDEX_op_ctpop_i32: - tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPW | SAB(args[1], a0, 0)); break; case INDEX_op_clz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, a0, a1, a2, const_args[2]); break; case INDEX_op_ctz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], - args[2], const_args[2]); + tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, a0, a1, a2, const_args[2]); break; case INDEX_op_ctpop_i64: - tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); + tcg_out32(s, CNTPOPD | SAB(args[1], a0, 0)); break; case INDEX_op_mul_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { @@ -2601,27 +2595,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_div_i32: - tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVW | TAB(args[0], a1, a2)); break; case INDEX_op_divu_i32: - tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVWU | TAB(args[0], a1, a2)); break; case INDEX_op_shl_i32: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli32(s, args[0], args[1], args[2] & 31); + tcg_out_shli32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLW | SAB(args[1], a0, a2)); } break; case INDEX_op_shr_i32: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri32(s, args[0], args[1], args[2] & 31); + tcg_out_shri32(s, a0, a1, a2 & 31); } else { - tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRW | SAB(args[1], a0, a2)); } break; case INDEX_op_sar_i32: @@ -2629,33 +2623,32 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, /* Limit immediate shift count lest we create an illegal insn. */ tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31)); } else { - tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAW | SAB(args[1], a0, a2)); } break; case INDEX_op_rotl_i32: if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); + tcg_out_rlw(s, RLWINM, a0, a1, a2, 0, 31); } else { - tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) + tcg_out32(s, RLWNM | SAB(args[1], a0, a2) | MB(0) | ME(31)); } break; case INDEX_op_rotr_i32: if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 0, 31); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); - tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) - | MB(0) | ME(31)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 32)); + tcg_out32(s, RLWNM | SAB(args[1], a0, TCG_REG_R0) | MB(0) | ME(31)); } break; case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + tcg_out_brcond(s, a2, a0, a1, const_args[1], arg_label(args[3]), TCG_TYPE_I32); break; case INDEX_op_brcond_i64: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + tcg_out_brcond(s, a2, a0, a1, const_args[1], arg_label(args[3]), TCG_TYPE_I64); break; case INDEX_op_brcond2_i32: @@ -2669,11 +2662,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_not_i32: case INDEX_op_not_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); + tcg_out32(s, NOR | SAB(args[1], a0, a1)); break; case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { do_addi_64: tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); @@ -2682,7 +2674,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[1]) { if (const_args[2]) { tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); @@ -2700,17 +2691,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_shl_i64: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli64(s, args[0], args[1], args[2] & 63); + tcg_out_shli64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SLD | SAB(args[1], a0, a2)); } break; case INDEX_op_shr_i64: if (const_args[2]) { /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri64(s, args[0], args[1], args[2] & 63); + tcg_out_shri64(s, a0, a1, a2 & 63); } else { - tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRD | SAB(args[1], a0, a2)); } break; case INDEX_op_sar_i64: @@ -2718,27 +2709,26 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); } else { - tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); + tcg_out32(s, SRAD | SAB(args[1], a0, a2)); } break; case INDEX_op_rotl_i64: if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); + tcg_out_rld(s, RLDICL, a0, a1, a2, 0); } else { - tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); + tcg_out32(s, RLDCL | SAB(args[1], a0, a2) | MB64(0)); } break; case INDEX_op_rotr_i64: if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 0); } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); - tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, a2, 64)); + tcg_out32(s, RLDCL | SAB(args[1], a0, TCG_REG_R0) | MB64(0)); } break; case INDEX_op_mul_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out32(s, MULLI | TAI(a0, a1, a2)); } else { @@ -2746,10 +2736,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_div_i64: - tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVD | TAB(args[0], a1, a2)); break; case INDEX_op_divu_i64: - tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, DIVDU | TAB(args[0], a1, a2)); break; case INDEX_op_qemu_ld_i32: @@ -2781,16 +2771,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, c | RS(args[1]) | RA(args[0])); break; case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); + tcg_out_ext32u(s, a0, a1); break; case INDEX_op_setcond_i32: - tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_setcond_i64: - tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], - const_args[2]); + tcg_out_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_setcond2_i32: tcg_out_setcond2(s, args, const_args); @@ -2798,7 +2786,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: - a0 = args[0], a1 = args[1]; /* a1 = abcd */ if (a0 != a1) { /* a0 = (a1 r<< 24) & 0xff # 000c */ @@ -2818,7 +2805,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i64: /* Stolen from gcc's builtin_bswap32 */ - a1 = args[1]; a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; /* a1 = args[1] # abcd */ @@ -2835,7 +2821,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_bswap64_i64: - a0 = args[0], a1 = args[1], a2 = TCG_REG_R0; + a2 = TCG_REG_R0; if (a0 == a1) { a0 = TCG_REG_R0; a2 = a1; @@ -2869,36 +2855,34 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_deposit_i32: if (const_args[2]) { uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi32(s, args[0], args[0], ~mask); + tcg_out_andi32(s, a0, a0, ~mask); } else { - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + tcg_out_rlw(s, RLWIMI, a0, a2, args[3], 32 - args[3] - args[4], 31 - args[3]); } break; case INDEX_op_deposit_i64: if (const_args[2]) { uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi64(s, args[0], args[0], ~mask); + tcg_out_andi64(s, a0, a0, ~mask); } else { - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + tcg_out_rld(s, RLDIMI, a0, a2, args[3], 64 - args[3] - args[4]); } break; case INDEX_op_extract_i32: - tcg_out_rlw(s, RLWINM, args[0], args[1], - 32 - args[2], 32 - args[3], 31); + tcg_out_rlw(s, RLWINM, a0, a1, 32 - a2, 32 - args[3], 31); break; case INDEX_op_extract_i64: - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); + tcg_out_rld(s, RLDICL, a0, a1, 64 - a2, 64 - args[3]); break; case INDEX_op_movcond_i32: - tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], + tcg_out_movcond(s, TCG_TYPE_I32, args[5], a0, a1, a2, args[3], args[4], const_args[2]); break; case INDEX_op_movcond_i64: - tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], + tcg_out_movcond(s, TCG_TYPE_I64, args[5], a0, a1, a2, args[3], args[4], const_args[2]); break; @@ -2910,14 +2894,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, /* Note that the CA bit is defined based on the word size of the environment. So in 64-bit mode it's always carry-out of bit 63. The fallback code using deposit works just as well for 32-bit. */ - a0 = args[0], a1 = args[1]; if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { a0 = TCG_REG_R0; } if (const_args[4]) { - tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); + tcg_out32(s, ADDIC | TAI(a0, a2, args[4])); } else { - tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); + tcg_out32(s, ADDC | TAB(a0, a2, args[4])); } if (const_args[5]) { tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); @@ -2934,14 +2917,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #else case INDEX_op_sub2_i32: #endif - a0 = args[0], a1 = args[1]; if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { a0 = TCG_REG_R0; } if (const_args[2]) { - tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); + tcg_out32(s, SUBFIC | TAI(a0, args[4], a2)); } else { - tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); + tcg_out32(s, SUBFC | TAB(a0, args[4], a2)); } if (const_args[3]) { tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); @@ -2954,20 +2936,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_muluh_i32: - tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHWU | TAB(args[0], a1, a2)); break; case INDEX_op_mulsh_i32: - tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHW | TAB(args[0], a1, a2)); break; case INDEX_op_muluh_i64: - tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHDU | TAB(args[0], a1, a2)); break; case INDEX_op_mulsh_i64: - tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); + tcg_out32(s, MULHD | TAB(args[0], a1, a2)); break; case INDEX_op_mb: - tcg_out_mb(s, args[0]); + tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ -- 2.26.2 From MAILER-DAEMON Wed Jan 13 12:26:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzjuJ-0000Mp-Kw for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 12:26:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzjtq-000099-MR; Wed, 13 Jan 2021 12:25:43 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:54171) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzjtl-0006AW-OA; Wed, 13 Jan 2021 12:25:35 -0500 Received: by mail-wm1-x32c.google.com with SMTP id k10so2301946wmi.3; Wed, 13 Jan 2021 09:25:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nbTY58aO/0J5mVZOizL8/L5H+yZ4rt3Ds459buh/Uo4=; b=uoa946qK+eG5eMCIzS2cz6yzKuNu/TbYio49p1yhcciT51de1vXX8hnCRTN6lZxLdh 2CPDKNODcNGqKK0ZMIUo3lLiFGnqCz95hUZSZdEggWPdpRPlKUlm/ccrw2XniCjE/cCo xWJyBtNpoYNy2Ro8lrTqpIF9QiRdAALofRFxiIVAqiiFUQT7Cw8NeZfu3yHdWoysQNB9 uIlLcQcfiMaxFiNjjkcXv3CU5tS4iiSi4+ZvpZO4VAnBtlxELdaNOFdMYqt4rlqFr+4u Mznwtep1Hp5wvKAA1Xukf28WicT5hAO2ARCgWEI8wAPIoLPN5D0AFijUCTjpAGivhv4b yAxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nbTY58aO/0J5mVZOizL8/L5H+yZ4rt3Ds459buh/Uo4=; b=LsRiI0A34qU9zVnjDAp8QzxlFPhobhvlk9cDmSlO8svxmqc5nvNcAX/aN7FmgZ9Jt9 n90oFeyQULTo6j/YVS0fCsWOP2/3iKYoq8O6CFtXcUa28eqwnMFli7T4/3AnJtZ1Ejcw 9kRcZ06wXyfJ3ElyFfN0DzvDSb/6QzFrt7GxnPh39sLHUHUVj1OQQC5g6ZH7ijBt0d8Z sfPgCL9/UUnoh3vwzOK8lJMLhpWrX3oOisJDQc1PoTnSkXqF0oZe8XH13J1hDgxkWgFw qjjNZZxom6QEbE8c7IQiJROfdZ58BmrLZ8A/EKdCJizssOTkSd1WPEqUMT6Rp5xQ36Zw VuWw== X-Gm-Message-State: AOAM533ZTiyRufhC1FQXiazDFCdyAK3WFvy12pxz4+REW7AlInufxAg3 CdDkuLQMpU2gX1btjJJexQhqgdzxg2A= X-Google-Smtp-Source: ABdhPJxR03gA0wrsFd/XfrZXq8/5cAsQbe8rZGIFSVwI83fvnhK3DyuI357dOUM4Sy7cVHORHVggqg== X-Received: by 2002:a1c:a583:: with SMTP id o125mr258893wme.91.1610558727675; Wed, 13 Jan 2021 09:25:27 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id 125sm3862219wmc.27.2021.01.13.09.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 5/6] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements Date: Wed, 13 Jan 2021 18:24:58 +0100 Message-Id: <20210113172459.2481060-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:45 -0000 tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. The Aarch64 target already does this since commit 8d8db193f25 ("tcg-aarch64: Hoist common argument loads in tcg_out_op"), SPARC since commit b357f902bff ("tcg-sparc: Hoist common argument loads in tcg_out_op"). RISCV missed it upon introduction in commit bdf503819ee ("tcg/riscv: Add the out op decoder"), MIPS since commit 22ee3a987d5 ("tcg-mips: Hoist args loads") and i386 since commit 42d5b514928 ("tcg/i386: Hoist common arguments in tcg_out_op"). Provide this information as a hint to the compiler in the function prototype, and update the funtion definitions. This fixes this warning (using GCC 11): tcg/aarch64/tcg-target.c.inc:1855:37: error: argument 3 of type 'const TCGArg[16]' {aka 'const long unsigned int[16]'} with mismatched bound [-Werror=array-parameter=] tcg/aarch64/tcg-target.c.inc:1856:34: error: argument 4 of type 'const int[16]' with mismatched bound [-Werror=array-parameter=] Reported-by: Miroslav Rezanina Reviewed-by: Miroslav Rezanina Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 5 +++-- tcg/i386/tcg-target.c.inc | 3 ++- tcg/mips/tcg-target.c.inc | 3 ++- tcg/riscv/tcg-target.c.inc | 3 ++- tcg/tci/tcg-target.c.inc | 5 +++-- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 472bf1755bf..97d074d8fab 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -110,8 +110,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args); +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 46e856f4421..d121dca8789 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2215,7 +2215,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) } static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0, a1, a2; int c, const_a2, vexop, rexw = 0; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index add157f6c32..b9bb54f0ecc 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1691,7 +1691,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, } static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c60b91ba58f..5bf0d069532 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1238,7 +1238,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGArg a0 = args[0]; TCGArg a1 = args[1]; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d5a4d9d37cf..60464524f3d 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -553,8 +553,9 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { uint8_t *old_code_ptr = s->code_ptr; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id s19sm1013485wrf.72.2021.01.13.09.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 4/6] tcg/s390: Hoist common argument loads in tcg_out_op() Date: Wed, 13 Jan 2021 18:24:57 +0100 Message-Id: <20210113172459.2481060-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:25:45 -0000 Signed-off-by: Philippe Mathieu-Daudé --- tcg/s390/tcg-target.c.inc | 222 ++++++++++++++++++-------------------- 1 file changed, 107 insertions(+), 115 deletions(-) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index d7ef0790556..ec202e79cfc 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1732,15 +1732,22 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, case glue(glue(INDEX_op_,x),_i64) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { S390Opcode op, op2; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a4; + int c2; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + a4 = args[4]; + c2 = const_args[2]; switch (opc) { case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ - a0 = args[0]; if (a0 == 0) { tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); } else { @@ -1750,7 +1757,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_tb: - a0 = args[0]; if (s->tb_jmp_insn_offset) { /* * branch displacement must be aligned for atomic patching; @@ -1784,7 +1790,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_ptr: - a0 = args[0]; if (USE_REG_TB) { tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } @@ -1794,44 +1799,42 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, OP_32_64(ld8u): /* ??? LLC (RXY format) is only present with the extended-immediate facility, whereas LLGC is always present. */ - tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGC, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(ld8s): /* ??? LB is no smaller than LGB, so no point to using it. */ - tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGB, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(ld16u): /* ??? LLH (RXY format) is only present with the extended-immediate facility, whereas LLGH is always present. */ - tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGH, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld16s_i32: - tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_LH, RXY_LHY, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); break; OP_32_64(st8): - tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STC, RXY_STCY, a0, a1, TCG_REG_NONE, a2); break; OP_32_64(st16): - tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_mem(s, RX_STH, RXY_STHY, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_st_i32: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + a2 = (int32_t)args[2]; if (const_args[2]) { do_addi_32: if (a0 == a1) { @@ -1852,9 +1855,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + a2 = (int32_t)args[2]; if (const_args[2]) { - a2 = -a2; + a2 = -args[2]; goto do_addi_32; } else if (a0 == a1) { tcg_out_insn(s, RR, SR, a0, a2); @@ -1864,7 +1867,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_andi(s, TCG_TYPE_I32, a0, a2); @@ -1875,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_ori(s, TCG_TYPE_I32, a0, a2); @@ -1886,45 +1889,45 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); tgen_xori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { - tcg_out_insn(s, RR, XR, args[0], args[2]); + tcg_out_insn(s, RR, XR, a0, a2); } else { tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; case INDEX_op_neg_i32: - tcg_out_insn(s, RR, LCR, args[0], args[1]); + tcg_out_insn(s, RR, LCR, a0, a1); break; case INDEX_op_mul_i32: if (const_args[2]) { if ((int32_t)args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MHI, args[0], args[2]); + tcg_out_insn(s, RI, MHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + tcg_out_insn(s, RRE, MSR, a0, a2); } break; case INDEX_op_div2_i32: - tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RR, DR, TCG_REG_R2, a4); break; case INDEX_op_divu2_i32: - tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DLR, TCG_REG_R2, a4); break; case INDEX_op_shl_i32: op = RS_SLL; op2 = RSY_SLLK; do_shift32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + a2 = (int32_t)args[2]; if (a0 == a1) { if (const_args[2]) { tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); @@ -1952,110 +1955,107 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_rotl_i32: /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLL, a0, a1, a2, 0); } break; case INDEX_op_rotr_i32: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], - TCG_REG_NONE, (32 - args[2]) & 31); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_REG_NONE, (32 - a2) & 31); } else { - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLL, a0, a1, TCG_TMP0, 0); } break; case INDEX_op_ext8s_i32: - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16s_i32: - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I32, a0, a1); break; case INDEX_op_ext16u_i32: - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I32, a0, a1); break; OP_32_64(bswap16): /* The TCG bswap definition requires bits 0-47 already be zero. Thus we don't need the G-type insns to implement bswap16_i64. */ - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); + tcg_out_insn(s, RRE, LRVR, a0, a1); + tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); break; OP_32_64(bswap32): - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVR, a0, a1); break; case INDEX_op_add2_i32: if (const_args[4]) { - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); + tcg_out_insn(s, RIL, ALFI, a0, a4); } else { - tcg_out_insn(s, RR, ALR, args[0], args[4]); + tcg_out_insn(s, RR, ALR, a0, a4); } - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCR, a1, args[5]); break; case INDEX_op_sub2_i32: if (const_args[4]) { - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); + tcg_out_insn(s, RIL, SLFI, a0, a4); } else { - tcg_out_insn(s, RR, SLR, args[0], args[4]); + tcg_out_insn(s, RR, SLR, a0, a4); } - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBR, a1, args[5]); break; case INDEX_op_br: - tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); + tgen_branch(s, S390_CC_ALWAYS, arg_label(a0)); break; case INDEX_op_brcond_i32: - tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I32, a2, a0, + a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i32: - tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I32, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_movcond_i32: - tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I32, args[5], a0, a1, + a2, const_args[2], args[3], const_args[3]); break; case INDEX_op_qemu_ld_i32: /* ??? Technically we can use a non-extending instruction. */ case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, a0, a1, a2); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, a0, a1, a2); break; case INDEX_op_ld16s_i64: - tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGH, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32u_i64: - tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LLGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld32s_i64: - tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_mem(s, 0, RXY_LGF, a0, a1, TCG_REG_NONE, a2); break; case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); break; case INDEX_op_st32_i64: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); break; case INDEX_op_st_i64: - tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); break; case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { do_addi_64: if (a0 == a1) { @@ -2084,7 +2084,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { a2 = -a2; goto do_addi_64; @@ -2096,18 +2095,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); + tgen_andi(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { - tcg_out_insn(s, RRE, NGR, args[0], args[2]); + tcg_out_insn(s, RRE, NGR, a0, a2); } else { tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_ori(s, TCG_TYPE_I64, a0, a2); @@ -2118,7 +2115,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_xor_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_xori(s, TCG_TYPE_I64, a0, a2); @@ -2130,21 +2126,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_neg_i64: - tcg_out_insn(s, RRE, LCGR, args[0], args[1]); + tcg_out_insn(s, RRE, LCGR, a0, a1); break; case INDEX_op_bswap64_i64: - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); + tcg_out_insn(s, RRE, LRVGR, a0, a1); break; case INDEX_op_mul_i64: if (const_args[2]) { - if (args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MGHI, args[0], args[2]); + if (a2 == (int16_t)args[2]) { + tcg_out_insn(s, RI, MGHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSGFI, a0, a2); } } else { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + tcg_out_insn(s, RRE, MSGR, a0, a2); } break; @@ -2153,10 +2149,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, into R3 with this definition, but as we do in fact always produce both quotient and remainder using INDEX_op_div_i64 instead requires jumping through even more hoops. */ - tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, a4); break; case INDEX_op_divu2_i64: - tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); + tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, a4); break; case INDEX_op_mulu2_i64: tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); @@ -2166,9 +2162,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, op = RSY_SLLG; do_shift64: if (const_args[2]) { - tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); + tcg_out_sh64(s, op, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, op, args[0], args[1], args[2], 0); + tcg_out_sh64(s, op, a0, a1, a2, 0); } break; case INDEX_op_shr_i64: @@ -2180,87 +2176,83 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_rotl_i64: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, args[2]); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_REG_NONE, a2); } else { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); + tcg_out_sh64(s, RSY_RLLG, a0, a1, a2, 0); } break; case INDEX_op_rotr_i64: if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, (64 - args[2]) & 63); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_REG_NONE, (64 - a2) & 63); } else { /* We can use the smaller 32-bit negate because only the low 6 bits are examined for the rotate. */ - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); + tcg_out_insn(s, RR, LCR, TCG_TMP0, a2); + tcg_out_sh64(s, RSY_RLLG, a0, a1, TCG_TMP0, 0); } break; case INDEX_op_ext8s_i64: - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16s_i64: - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16s(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: - tgen_ext32s(s, args[0], args[1]); + tgen_ext32s(s, a0, a1); break; case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext8u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_ext16u_i64: - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); + tgen_ext16u(s, TCG_TYPE_I64, a0, a1); break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: - tgen_ext32u(s, args[0], args[1]); + tgen_ext32u(s, a0, a1); break; case INDEX_op_add2_i64: if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); + if ((int64_t)a4 >= 0) { + tcg_out_insn(s, RIL, ALGFI, a0, a4); } else { - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, SLGFI, a0, -a4); } } else { - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); + tcg_out_insn(s, RRE, ALGR, a0, a4); } - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); + tcg_out_insn(s, RRE, ALCGR, a1, args[5]); break; case INDEX_op_sub2_i64: if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); + if ((int64_t)a4 >= 0) { + tcg_out_insn(s, RIL, SLGFI, a0, a4); } else { - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); + tcg_out_insn(s, RIL, ALGFI, a0, -a4); } } else { - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); + tcg_out_insn(s, RRE, SLGR, a0, a4); } - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); + tcg_out_insn(s, RRE, SLBGR, a1, args[5]); break; case INDEX_op_brcond_i64: - tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); + tgen_brcond(s, TCG_TYPE_I64, a2, a0, + a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i64: - tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], - args[2], const_args[2]); + tgen_setcond(s, TCG_TYPE_I64, args[3], a0, a1, a2, const_args[2]); break; case INDEX_op_movcond_i64: - tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + tgen_movcond(s, TCG_TYPE_I64, args[5], a0, a1, + a2, const_args[2], args[3], const_args[3]); break; OP_32_64(deposit): - a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[1]) { - tgen_deposit(s, a0, a2, args[3], args[4], 1); + tgen_deposit(s, a0, a2, args[3], a4, 1); } else { /* Since we can't support "0Z" as a constraint, we allow a1 in any register. Fix things up as if a matching constraint. */ @@ -2272,22 +2264,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } tcg_out_mov(s, type, a0, a1); } - tgen_deposit(s, a0, a2, args[3], args[4], 0); + tgen_deposit(s, a0, a2, args[3], a4, 0); } break; OP_32_64(extract): - tgen_extract(s, args[0], args[1], args[2], args[3]); + tgen_extract(s, a0, a1, a2, args[3]); break; case INDEX_op_clz_i64: - tgen_clz(s, args[0], args[1], args[2], const_args[2]); + tgen_clz(s, a0, a1, a2, const_args[2]); break; case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ - if (args[0] & TCG_MO_ST_LD) { + if (a0 & TCG_MO_ST_LD) { tcg_out_insn(s, RR, BCR, s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); } -- 2.26.2 From MAILER-DAEMON Wed Jan 13 12:26:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzjuK-0000Oa-1w for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 12:26:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzjtx-0000BN-NF; Wed, 13 Jan 2021 12:25:47 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:37064) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzjtr-0006Hs-Dl; Wed, 13 Jan 2021 12:25:45 -0500 Received: by mail-wm1-x333.google.com with SMTP id g10so2334698wmh.2; Wed, 13 Jan 2021 09:25:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CsrU5PzWJOqWBM621BtsUfkniXFxs+sJ0jZIwq4bvko=; b=tZYvrIRroKpXLJ5e/pihISRDSjdwOQ93ujRXBjbefwCHz1KbtyPkMV031mAsWRrJoc 7rwBIF0eyiQvMcOM1N0HRz2kO4jzmzxx7RMN/sVKOhNWbRucyuqoxpRAd9FGxs3rgVMa pMUVcxsUE87I3JT4F52vFREa6b+kPsymTRW5c2bHiJkdmi9PZBRxVLPpcsPwQC04kPxH pezV3qHV3zfAzqqf96lc4dc0SBIoeCxZx4JJI/sfWW8RzbmrWReU+T5yaGv+2dtnOL5w 3puQ833pgroSlrDZr8aavGBT1DdHiGuhEa9sh1+x50DBoLWaLmtbGwpW2Xbnhda7n+4a 4Nfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CsrU5PzWJOqWBM621BtsUfkniXFxs+sJ0jZIwq4bvko=; b=tgeEFaF/rkBnZHE38lbPHBi4BhzHgqDIDykV1g6Hv9FDSz62ngCdbpIDbNJFhrwU4o Rq/NpFaJjoU1IiZKQb6vO2xuDsRdLZR5i90cW7UKfbSb2qciCUl23iyRwhoAXLbLe2R2 327WipdkGDuA4C7YVeLJ7LM8NRGdfVeJfIqCZ1tixJ1sm/rBovFOgh1HCEdDXsBs5NBl CAZ7geuiesY6pqyABK59t1wLRlpd7bgom7H4t73a0uO4SYhFHj3Do296CUtYQAcoD2HD nk44/1pi8wb2hZgwqteGS6nwTGQNFdmMUxLCehjZ4lKgR3fjqIYMKMWuD9MkFYbAunCT MtOQ== X-Gm-Message-State: AOAM533+BpaTna7atrcjdxs50+z1NCdba9yD5UkDEhiT5zip0W0G0mGt bC0XouGC4zRhr0nxiFu81k0LzO7V4u4= X-Google-Smtp-Source: ABdhPJye576eM2Ebv7gU2u8PS2+2AyG7/UyRx2o3UsvGh7li2vvj1bw6ncnm9r8ciqfb2y4nUj3CDQ== X-Received: by 2002:a1c:40d6:: with SMTP id n205mr323192wma.0.1610558732781; Wed, 13 Jan 2021 09:25:32 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u83sm4066965wmu.12.2021.01.13.09.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 09:25:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Richard Henderson , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH v2 6/6] tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements Date: Wed, 13 Jan 2021 18:24:59 +0100 Message-Id: <20210113172459.2481060-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210113172459.2481060-1-f4bug@amsat.org> References: <20210113172459.2481060-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:26:02 -0000 tcg_reg_alloc_op() allocates arrays of TCG_MAX_OP_ARGS elements. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 14 ++++++++------ tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/i386/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 97d074d8fab..3a20327f9cb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -120,9 +120,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg); -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args); +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]); #else static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) @@ -139,9 +140,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, { g_assert_not_reached(); } -static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, - unsigned vece, const TCGArg *args, - const int *const_args) +static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { g_assert_not_reached(); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ab199b143f3..32811976e78 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2276,7 +2276,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const AArch64Insn cmp_insn[16] = { [TCG_COND_EQ] = I3616_CMEQ, diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d121dca8789..87bf75735a1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2654,7 +2654,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static int const add_insn[4] = { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 70b747a8a30..b8f5f8a53e1 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3137,7 +3137,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { static const uint32_t add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, -- 2.26.2 From MAILER-DAEMON Wed Jan 13 12:35:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzk3G-0000cy-Uo for mharc-qemu-arm@gnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v3sm3716764pjn.7.2021.01.13.09.35.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 09:35:13 -0800 (PST) Subject: Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension To: =?UTF-8?Q?R=c3=a9mi_Denis-Courmont?= , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <12681824.uLZWGnKmhe@basile.remlab.net> <20210112104511.36576-17-remi.denis.courmont@huawei.com> <6ffaca60-2fa0-ac7d-b430-0bbaee18b25a@linaro.org> <4284476.LvFx2qVVIh@basile.remlab.net> From: Richard Henderson Message-ID: <55d19894-4435-6ba0-69c1-b9078127128f@linaro.org> Date: Wed, 13 Jan 2021 07:35:09 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4284476.LvFx2qVVIh@basile.remlab.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:35:20 -0000 On 1/13/21 3:12 AM, Rémi Denis-Courmont wrote: >> if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && >> dc_isar_feature(aa64_sel2, s)) { >> ... >> > > Hmm, yeah. Should this be an ifdef on TARGET_AARCH64 instead? No, I don't think so. It's not performance critical that we avoid a single bit test. > Also do we need to revector the exception code, or leave it mostly duplicated > as is? If you see a way to tidy that, great, please. But I don't think it's required for this patch set. r~ From MAILER-DAEMON Wed Jan 13 12:56:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzkO3-0000or-3v for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 12:56:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzkNz-0000ny-Bm; Wed, 13 Jan 2021 12:56:47 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36071) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzkNx-0000XH-CW; Wed, 13 Jan 2021 12:56:47 -0500 Received: by mail-wr1-x432.google.com with SMTP id t16so3079081wra.3; Wed, 13 Jan 2021 09:56:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=KCk7TfTfwRCek4wOSD0IP+5auBOMydUqU5Lqt7Lsjo4=; b=GcO1E3t136W7ipN+PcgDa7+Uqb4U5X+hDR9H//PEZcl+f+6jLM/dmibSnbwmCzX5Ia ox/RG0oomu0Saa1GxAnsLvXlEKomo4pqcaQAZIl/wo2G8B821UupG5W8F3s1CgzeyEfh Bi+Fp96brtpuNRGpJ5YHgt7byvrZY7vKXAmRofEeAB9r5bxfosjTWYvy+wDsmo9FpZj9 slEcD5ZOGgaCbJYte51bVdt2nC0mUg7lK4OJz+e09M0/Qj34Wb9lkBAq+nxCtYoWoAnw IqQoqQAUPLpJrrCFgLwB5bIAwjY5VKlXqR55p1mI9j8RnxOrgxz0aJZcqoh/VtopuwRe g4jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=KCk7TfTfwRCek4wOSD0IP+5auBOMydUqU5Lqt7Lsjo4=; b=OCdny0MewH3N9IrRF4/ceYWDXQrXSzfqRVCuW/+/xrMV6sQLZoUdB0uUPpyagPDyGK Ay/4yZh9uc3Dvf6ks0DrcNK6uUVKY1nizdcJ8+Y9dAtLlrsJGFxs4Zy2TIcWIwigkqFi 17fkWO7NTNXtj1KFh8vyXUtcI5RKf9JOPYlgS3rxlaapxLWI79qk50uw7hDVV6ZbjHnN gQAdBXxxpiBlQQgqAYw6BLsgn4RgP7pxwr3CYT9kNeiUazEiBz6d9BFb55AnJZakN6lG WBPP/FagssU+xHPJe7DJ/Di9M+T5QwULJgO8aV4aIg8Dlhy0V6qP72b2S+rcgmeerBxG /OCw== X-Gm-Message-State: AOAM531hYhh8Xi0aUvDKaXVUR6NRemsB3uZeK9npcxZP5n+y2NRZIjHA iD94s9uz5wM3jD7csiy7dno= X-Google-Smtp-Source: ABdhPJx1Vry2G4B894Y/s8fAr0Ty26sskDp1PRgKmHf20cM2RlRzDIV6Hr2qQ6zM9YhF+8rkCw+FuA== X-Received: by 2002:adf:bb0e:: with SMTP id r14mr3870914wrg.159.1610560603560; Wed, 13 Jan 2021 09:56:43 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c20sm3795276wmb.38.2021.01.13.09.56.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 09:56:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Bin Meng Cc: Peter Maydell , Alistair Francis , Xuzhou Cheng , Bin Meng , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210112183529.2011863-1-f4bug@amsat.org> <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7c8e33c2-d86a-44ef-8d4c-0f6dcf9f7b2c@amsat.org> Date: Wed, 13 Jan 2021 18:56:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 17:56:48 -0000 On 1/13/21 2:27 PM, Bin Meng wrote: > Hi Philippe, > > On Wed, Jan 13, 2021 at 3:53 PM Philippe Mathieu-Daudé wrote: >> >> Hi Ben, >> >> On 1/13/21 4:29 AM, Bin Meng wrote: >>> On Wed, Jan 13, 2021 at 2:35 AM Philippe Mathieu-Daudé wrote: >>>> >>>> Hi, >>>> >>>> As it is sometimes harder for me to express myself in plain >>>> English, I found it easier to write the patches I was thinking >>>> about. I know this doesn't scale. >>>> >>>> So this is how I understand the ecSPI reset works, after >>>> looking at the IMX6DQRM.pdf datasheet. >>>> >>>> This is a respin of Ben's v5 series [*]. >>>> Tagged RFC because I have not tested it :) >>> >>> Unfortunately this series breaks SPI flash testing under both U-Boot >>> and VxWorks 7. >> >> Thanks for testing :) Can you provide the binary tested and the command >> line used? At least one, so I can have a look. > > Sure, will send you offline. Arf, stupid mistake in patch 7 :) With this diff I can run your test: -- >8 -- --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -343,7 +343,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, return; } s->regs[ECSPI_CONREG] = value; - if (value & ECSPI_CONREG_EN) { + if (!(value & ECSPI_CONREG_EN)) { /* Keep disabled */ return; } --- Regards, Phil. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id a31sm3024994pgb.93.2021.01.13.10.35.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 10:35:02 -0800 (PST) Subject: Re: [PATCH 0/5] tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Cornelia Huck , qemu-riscv@nongnu.org, Stefan Weil , Huacai Chen , Thomas Huth , Jiaxun Yang , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Palmer Dabbelt , Andrzej Zaborowski , Aurelien Jarno References: <20210111150114.1415930-1-f4bug@amsat.org> <43f360be-af44-27ce-619b-7a2ad169aa2f@linaro.org> From: Richard Henderson Message-ID: <7ba66bdc-c464-26c5-ef35-fdd6f2b538c9@linaro.org> Date: Wed, 13 Jan 2021 08:34:57 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jan 2021 18:35:09 -0000 On 1/13/21 5:07 AM, Philippe Mathieu-Daudé wrote: > On 1/11/21 6:22 PM, Richard Henderson wrote: >> On 1/11/21 5:01 AM, Philippe Mathieu-Daudé wrote: >>> Attempt to fix the warning reported by Miroslav using GCC 10: >>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg771520.html >>> >>> Philippe Mathieu-Daudé (5): >>> tcg/arm: Hoist common argument loads in tcg_out_op() >>> tcg/ppc: Hoist common argument loads in tcg_out_op() >>> tcg/s390: Hoist common argument loads in tcg_out_op() >>> tcg: Restrict tcg_out_op() to arrays of TCG_MAX_OP_ARGS elements >>> tcg: Restrict tcg_out_vec_op() to arrays of TCG_MAX_OP_ARGS elements >> >> I've been trying to figure out a cleaner way to handle these, but this is >> certainly ok for now, and avoids the Werror. >> >> Reviewed-by: Richard Henderson >> >> Will queue to tcg-next. > > Please hold on, Miroslav found a regression in the PPC patch. > I had found the trivial s390 one during regression and fixed it. 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Jan 2021 19:04:45 -0500 From: Andrew Jones To: Maxim Uvarov Cc: Peter Maydell , Jose Marinho , QEMU Developers , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down Message-ID: <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.25, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 00:04:56 -0000 On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote: > - the same size for secure and non secure gpio. Arm doc says that > secure memory is also split on 4k pages. So one page here has to be > ok. To be clear, does that means 4k pages must be used? I'm not concerned with the size, but the alignment. If it's possible to use larger page sizes with secure memory, then we need to align to the maximum page size that may be used. Thanks, drew > - will add dtb. > - I think then less options is better. So I will remove > vmc->secure_gpio flag and keep only vmc flag. > > Regards, > Maxim. > > On Tue, 12 Jan 2021 at 19:28, Andrew Jones wrote: > > > > On Tue, Jan 12, 2021 at 11:25:30AM -0500, Andrew Jones wrote: > > > On Tue, Jan 12, 2021 at 04:00:23PM +0000, Peter Maydell wrote: > > > > On Tue, 12 Jan 2021 at 15:35, Andrew Jones wrote: > > > > > > > > > > On Tue, Jan 12, 2021 at 05:30:58PM +0300, Maxim Uvarov wrote: > > > > > > Add secure pl061 for reset/power down machine from > > > > > > the secure world (Arm Trusted Firmware). Connect it > > > > > > with gpio-pwr driver. > > > > > > > > > > + /* connect secure pl061 to gpio-pwr */ > > > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > > > > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > > > > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > > > > > > > > > I don't know anything about secure world, but it seems odd that we don't > > > > > need to add anything to the DTB. > > > > > > > > We should be adding something to the DTB, yes. Look at > > > > how create_uart() does this -- you set the 'status' and > > > > 'secure-status' properties to indicate that the device is > > > > secure-world only. > > > > > > > > > > > > > > > > > > + if (vmc->no_secure_gpio) { > > > > > > + vms->secure_gpio = false; > > > > > > + } else { > > > > > > + vms->secure_gpio = true; > > > > > > + } > > > > > > > > > > nit: vms->secure_gpio = !vmc->no_secure_gpio > > > > > > > > > > But do we even need vms->secure_gpio? Why not just do > > > > > > > > > > if (vms->secure && !vmc->no_secure_gpio) { > > > > > create_gpio_secure(vms, secure_sysmem); > > > > > } > > > > > > > > > > in machvirt_init() ? > > > > > > > > We're just following the same pattern as vmc->no_its/vms->its, > > > > aren't we ? > > > > > > > > > > 'its' is a property that can be changed on the command line. Unless > > > we want to be able to manage 'secure-gpio' separately from 'secure', > > > then I think vmc->its plus 'secure' should be sufficient. We don't > > > > I meant to write 'vmc->no_secure_gpio and vms->secure' here. > > > > Thanks, > > drew > > > > > always need both vmc and vms state, see 'no_ged'. > > > > > > Thanks, > > > drew > > > From MAILER-DAEMON Wed Jan 13 19:29:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzqVb-0005Rc-5z for mharc-qemu-arm@gnu.org; Wed, 13 Jan 2021 19:29:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzqVa-0005RN-26 for qemu-arm@nongnu.org; Wed, 13 Jan 2021 19:29:02 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:41274) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzqVY-0000KS-4A for qemu-arm@nongnu.org; Wed, 13 Jan 2021 19:29:01 -0500 Received: by mail-pl1-x635.google.com with SMTP id y8so2018289plp.8 for ; Wed, 13 Jan 2021 16:28:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5nMYmMTdVYgu7E6Wqq3JcuqKHISmWZCZhp0OGnyFcyo=; b=HxR3kavm8p+Gx1nK94zFXnLNNG3rFoepgBl5PFPNVP0mu9+bUPJyMp6IZDytB8CVq4 Kbh+n9PEN35PW8bDBUgj6/zSGsZ7BZqbNzWzzW7m77F7bH53exJC4vgjBOAB2UszAfZs 4UTsodqy/exJZ3184PZ27sOxAoIJWONSAv5D8wJ6xiDXhei9xdErSexJtYKU49HFxaXh ygp7462j1+WPQXehY9tHL4O1c2xcsj3ya5sEgrHWaQ2TP0GQ/psWSNAZhFY6oOxABT6n U9W4yei/2zTEgfbtAv/jd49JEdi2yWxkeNV14y+ajq/8MpGJd2izDDV8GLIOFNFLXsdN u64Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5nMYmMTdVYgu7E6Wqq3JcuqKHISmWZCZhp0OGnyFcyo=; b=H6JV8aRKoxhqPxiJnKqUNCqRJrlsuf4+67RaKqyXMhnbqw3RUyoez2ZwCshYLEEI6u TOkG2O7bLtQq8Roi17qI3EQYoum2wY6hLeCR81euFcUJdBlJbKXOXpNuvxll6hPmjYjA EkrYcyH/KAGKT9zEzMTPTmvZ4evyOfkYNe3ZC6RlQ1PC4LdHnPWfykozZbQJkmaQfM29 kQirSahkWSdHB4d7p1iPJ6QW81ANp/OzI2OwY1kaw8MmMCvm7K79lhkkwhcsHXd19i9m cs4JhRQjHO5YxMOS5h6FD8eOhVXjIuF7ycUla3jodYAVkG6k/Cu6BtWZJTMtwcSgtH3s RmGw== X-Gm-Message-State: AOAM5321hUy0RdpLth9DiHw3IVzw0gSIQ+22Nan7tXDtCnxMJlxIOzEB 5EbFj9PyOOhdOpxH6d+C2WAghg== X-Google-Smtp-Source: ABdhPJx2FGpdG2pjT7DZMnjgfjwT3keDZBzf/+JnMxBxApbCQPB5I7ntLECVgdGWSUtRm3CeONDNMA== X-Received: by 2002:a17:90b:23d6:: with SMTP id md22mr1986058pjb.206.1610584137786; Wed, 13 Jan 2021 16:28:57 -0800 (PST) Received: from [10.25.18.3] (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id 8sm3427718pfz.93.2021.01.13.16.28.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Jan 2021 16:28:57 -0800 (PST) Subject: Re: [PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op() To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Aurelien Jarno , Cornelia Huck , qemu-arm@nongnu.org, Alistair Francis , Miroslav Rezanina , Thomas Huth , qemu-riscv@nongnu.org, Huacai Chen , Stefan Weil , Aleksandar Rikalo , Andrzej Zaborowski , Palmer Dabbelt , qemu-s390x@nongnu.org, Jiaxun Yang References: <20210113172459.2481060-1-f4bug@amsat.org> <20210113172459.2481060-4-f4bug@amsat.org> From: Richard Henderson Message-ID: Date: Wed, 13 Jan 2021 14:28:52 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210113172459.2481060-4-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 00:29:02 -0000 On 1/13/21 7:24 AM, Philippe Mathieu-Daudé wrote: > case INDEX_op_ld8s_i32: > case INDEX_op_ld8s_i64: > - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); > + tcg_out_mem_long(s, LBZ, LBZX, a0, a1, a2); > tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); Missed replacements. > - a0 = args[0], a1 = args[1], a2 = args[2]; > if (const_args[2]) { Missed replacement. > do_addi_32: > tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); > @@ -2475,7 +2481,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, > } > break; > case INDEX_op_sub_i32: > - a0 = args[0], a1 = args[1], a2 = args[2]; > if (const_args[1]) { > if (const_args[2]) { And again. Let's just drop the hoisting parts and only do the signature parts for now. I'd rather think of a way to split up this large function than waste time optimizing it. r~ From MAILER-DAEMON Thu Jan 14 04:50:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzzH1-0004MP-1v for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 04:50:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzzGo-0004Km-T2 for qemu-arm@nongnu.org; Thu, 14 Jan 2021 04:50:24 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:45496) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzzGm-0002kq-OE for qemu-arm@nongnu.org; Thu, 14 Jan 2021 04:50:22 -0500 Received: by mail-ej1-x630.google.com with SMTP id e18so7203491ejt.12 for ; Thu, 14 Jan 2021 01:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CzMKyU55RFUpOhw/+mqOGMS64vLPHedKvSKg42gyNqE=; b=bqDDjwnsqMY7xln0OBHIp3EBMBi0JpJGqv3jVkVoVfmKAad89HrPQ1whKV1DlLueBl jl9FTFRJZikcS8dP1vTIOCaOGVVLLLqLdR7/P9yOr9BK+r75gbbzboblDJ4ihnRi61lg +2uvUaa8whjp/+dkLqxaYXrABxKnrUtRAeSpQl1vuO0Xh9JxOZkpQaSlQp5XVh9X+WbT u5KTpAbsgbA2gjDNMoBDL4xTdYiuEm5GcgKNxq1/0fUq09Y4D8F9VwIBil58SxorJvPf y3qkqRJwnP17t2ykpZC6tIvlyes1xxFWd0h0RLwC+cbdycWw+EwTFycmoYN6xsJxL/vD JtSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CzMKyU55RFUpOhw/+mqOGMS64vLPHedKvSKg42gyNqE=; b=KcC1kyuf5FgYVgjrJ4+liEYRWdvV/R87KoLzKC33A40TaCzvc1RkivTWgd2MrLOtyz x/fx9UdlaWfjxTABL+7iRSLcQ2bHM0O74kDo16G6cx6igS32FEPAAl3m5b6GPPK9vaLr hXl+HjjLE5vg9zN/8Ud7EL+2ELwjd+F6io+AXXDGItIHurAuxj9qtifhFCZwOGX2tmcW VfK1hGKPgrOws3KKH73G7FnioaU7ZcXrA2FdZV5zMk8VYZrePm5nnIEdm7Ci1lal2MNy hpGIbuETYT7udA/6RCjMNifm6DjCaOC/iQcLCIaG8m+9hSyJvNgfiya4tZ82pVEga/Vy FeDg== X-Gm-Message-State: AOAM5336chKaAi9kDUFT3J2bAu8QYHSj99C7chXgGYZEKdR1iCQc8M/i mYKTuF8jiTJ8Nq3IAceLUIiO5RWP4lMaVCEsxdTJtA== X-Google-Smtp-Source: ABdhPJzsY5yWjC6jxaUGoczI5Rxbj+TbbD7EWRfHNz+i5nJp087bPU27hbJFUGCYLQIXKaywG23RljRYOAU3CFSO4mg= X-Received: by 2002:a17:906:6b88:: with SMTP id l8mr4728402ejr.482.1610617814708; Thu, 14 Jan 2021 01:50:14 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> In-Reply-To: <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> From: Peter Maydell Date: Thu, 14 Jan 2021 09:50:03 +0000 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Andrew Jones Cc: Maxim Uvarov , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 09:50:24 -0000 On Thu, 14 Jan 2021 at 00:04, Andrew Jones wrote: > > On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote: > > - the same size for secure and non secure gpio. Arm doc says that > > secure memory is also split on 4k pages. So one page here has to be > > ok. > > To be clear, does that means 4k pages must be used? I'm not concerned > with the size, but the alignment. If it's possible to use larger page > sizes with secure memory, then we need to align to the maximum page > size that may be used. I think we should just align on 64K, to be more future-proof. Even if secure software today uses 4K pages, it doesn't hurt to align the device such that some hypothetical future 64K page using secure software can use it. thanks -- PMM From MAILER-DAEMON Thu Jan 14 04:59:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kzzPS-0001KH-79 for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 04:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzzPP-0001JJ-4Y; Thu, 14 Jan 2021 04:59:15 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzzPN-0003s9-Ls; Thu, 14 Jan 2021 04:59:14 -0500 Received: by mail-wr1-x42c.google.com with SMTP id w5so5085194wrm.11; Thu, 14 Jan 2021 01:59:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=keVhnryVt2H0asSKa5VEmd8Dk4m45NkmEqSQuwlm0Hk=; b=Ec182EYlUvHqVCC5r/6klxDDKMQK9pqFzKx2WrVyXmfK3GGNqEuAlw5v4S7JM6kR4z s5Gc8jixFWkv4O6v+UUhUCDZO6cZ5WIrbrzs/OVmHHfU0TflQM5QT/fB6o/z1/katOrP LArVewL6zQTn4SSFHDSUq54iIP6ouzUu+X9CN767JyClTSlA0dlrdmnTq9EcvN03KUWq iqaXHQBsCP+dLxAoQiXIHWztwLZYAnD034GGAJwPDIJoRGdyelV16h1HHg1GRjDHg0dh 5vOmMAuO8dA+Ll8wExBP9kIxnzznARxLnvsBw6m6bsyVlOSkxzBafrVhW+rOTGeqG6V0 qsfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=keVhnryVt2H0asSKa5VEmd8Dk4m45NkmEqSQuwlm0Hk=; b=N8r6y2evqGH17REsEexjrwE1JUPS9+VfC7kzoBxlm5x7iR2S21mMiuUtmMY2BWi1MM oBPznvcWnxaiPGn/MapIc9jjvLyY8Secm6zbgG+CF5BuSgS25qZ7ArHeVlj0omV/0w3+ 03IJG41uvFODCNT83L1HVtyXN/os6sXV7AFeXPpOZYLsQT/wbKvC75AcoqOH/d5GWg7H J/NDoPW75p+RIxSdfahmKCM12NlGoGGt3Gfq+JJbpSTZ1TO3LRVHixMnqffcRe088dZi WFIHL4Pmrbl4/xCvqoyt5B/6avZ6RYoIZoNsregAOrJyzUIRDen6fPKgwiBjsPGRMB7Y ACFg== X-Gm-Message-State: AOAM530jZYXmOmpqPCILpJRKoouvoVAq2k7mBWysRZhaKGl9+4hCZbuy qq2zwj7t6ZTQlg9Y0kIt/C8= X-Google-Smtp-Source: ABdhPJxUMS5SGO/yUaYd3ZJf4skNUf5FqX0146FZ8+fXLNwuaFnu46DtLyZaaaMzsOwFmWQO6FP1Rg== X-Received: by 2002:adf:ffc8:: with SMTP id x8mr7022867wrs.158.1610618347131; Thu, 14 Jan 2021 01:59:07 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id 125sm7468040wmc.27.2021.01.14.01.59.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Jan 2021 01:59:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 3/6] tcg/ppc: Hoist common argument loads in tcg_out_op() To: Richard Henderson , qemu-devel@nongnu.org Cc: Thomas Huth , Huacai Chen , qemu-riscv@nongnu.org, Stefan Weil , Cornelia Huck , Aleksandar Rikalo , Jiaxun Yang , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Palmer Dabbelt , Miroslav Rezanina , Andrzej Zaborowski , Aurelien Jarno References: <20210113172459.2481060-1-f4bug@amsat.org> <20210113172459.2481060-4-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 14 Jan 2021 10:59:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 09:59:16 -0000 On 1/14/21 1:28 AM, Richard Henderson wrote: > > Let's just drop the hoisting parts and only do the signature parts for now. > I'd rather think of a way to split up this large function than waste time > optimizing it. Agreed :) Thanks! From MAILER-DAEMON Thu Jan 14 06:22:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l00hp-0002Mg-TS for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 06:22:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l00hn-0002Kw-Jh for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:22:19 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:46519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l00hj-0004T2-0H for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:22:18 -0500 Received: by mail-pl1-x630.google.com with SMTP id v3so2735235plz.13 for ; Thu, 14 Jan 2021 03:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bqSs6bnwUDFbPW03XDcbH3y2U5MUEU7ogRQ0wBGoRas=; b=JHkEy4y1YLdbGI+T8Szc3wHwKBYQNpye/EUdCRvHDp2nIktvm8eFVJKLTwbhKReQwh ldcRyGeIjIctyQ0Q1kRiHjvf7MW6lDAprhjdTL4+JTHA1GSx5tQ0CMj08EfQClykw3Bu /L/roXyesVO/qGgjcM5oeJ35GmnloqzS+QLpydQyaGQVF1r1hyVrZD8LA0URmCsATAli WHxXl1gT9OJh/wPkPKdq0G5HbaV6t5MyLAVOABfdYku8g4xv46Mo6AP5Ey9gfbpSoQj6 XwW4XluCOjYkx8bd5HSEEs8YFMsI6zCvWMjbUCoLJxjl09+ATRS4FwxgNhFLu8t+HG3D wyHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bqSs6bnwUDFbPW03XDcbH3y2U5MUEU7ogRQ0wBGoRas=; b=t1/xTVfmfrOwo1U+EvvNuUwSy6Zp8jpaOiMrVwmmbf1Tig2SsAAMAEmksC2awGsIa3 0kGynMGDiKttwmIHDvwW7CK7UVGJtsD0pbVvbDuF83xiqLICfBTy5WPw/MNH9MmmssKv hXAYfg18iQID1Nhzg65S0apDDDrHmVUdBxGDL48A4fx1b6xHMleDzWujV/uwx53K2vd6 ecubhQM98ilQDXDl+npi2nPl10azMiOtF+pUceO4c3HOwmNS3pZi4hBccd/rLuvsHlkD LC/0O8RpXE4Zabw2ZtlysJdOlJkP55hS+upc9TMkHHkEZe5YO93sjC0SH9ghAjaiPMPw eDPw== X-Gm-Message-State: AOAM532xQivvBdIjgNeXABRrmhY9RgIXqlGJpgpeKxxP7snu8g0QnClI jrWCNOOzbgWUfKFqGi9l4lvGKj2FhaF3yhhNDtCd1g== X-Google-Smtp-Source: ABdhPJzGSFb5RU/d8F0aPoE/VOP5yNMQuKaPaGbD4jqe9LrPcS4cjDLE+B0gX1XzUneLMqObCleN2EfPImtFN0IpTLg= X-Received: by 2002:a17:902:6b45:b029:de:2db8:fd34 with SMTP id g5-20020a1709026b45b02900de2db8fd34mr7104600plt.71.1610623330688; Thu, 14 Jan 2021 03:22:10 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> In-Reply-To: From: Maxim Uvarov Date: Thu, 14 Jan 2021 14:22:00 +0300 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Peter Maydell Cc: Andrew Jones , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=maxim.uvarov@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 11:22:19 -0000 On Thu, 14 Jan 2021 at 12:50, Peter Maydell wrote: > > On Thu, 14 Jan 2021 at 00:04, Andrew Jones wrote: > > > > On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote: > > > - the same size for secure and non secure gpio. Arm doc says that > > > secure memory is also split on 4k pages. So one page here has to be > > > ok. > > > > To be clear, does that means 4k pages must be used? I'm not concerned > > with the size, but the alignment. If it's possible to use larger page > > sizes with secure memory, then we need to align to the maximum page > > size that may be used. > > I think we should just align on 64K, to be more future-proof. > Even if secure software today uses 4K pages, it doesn't hurt > to align the device such that some hypothetical future 64K > page using secure software can use it. > > thanks > -- PMM Does that mean that in that case you need all regions to be 64k aligned? I mean secure and non-secure. Has anybody tested 64k pages under qemu? [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 } [VIRT_UART] = { 0x09000000, 0x00001000 }, [VIRT_RTC] = { 0x09010000, 0x00001000 }, [VIRT_GPIO] = { 0x09030000, 0x00001000 }, [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, Maxim. From MAILER-DAEMON Thu Jan 14 06:25:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l00kX-0004K6-JY for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 06:25:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l00kU-0004Io-IK for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:25:06 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:53023) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l00kK-0005dm-T5 for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:25:04 -0500 Received: by mail-pj1-x1036.google.com with SMTP id v1so2920507pjr.2 for ; Thu, 14 Jan 2021 03:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FB/a3IGlr2mNnBlsMB0LqU5ZoTWWDZ0tGkAmh0w7jB0=; b=n0B32szN6HO9QDzs8+Evr59u69+wPH8TbgEnzBAypFtRPmp2Cv44Iz1EtTfCFnJS8x wbaRSa5YvG2lZ89eOZ6inMukwuGoS3Mt05IwVppU7TEmZrQzg1sDP5yiyJRVlqBe8Voe xBxDeMotTz8DW+Yyc1VWZNRFYWFgOf8n2GyEpx/dyUca41xuPrHybR91wycqY7+cN0If oz8T7MmLQjhf91bd22aua8djTzg6I7mnY98h2Sg2aD2D9iLF3XyQlENAkud++Bvl8+++ tDwHlklbvnqZwjujRwj3nYUAPWqU4idGpgXhpt+6xDpbG1CHli/BSj7IhDBKI7zTPGa1 kAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FB/a3IGlr2mNnBlsMB0LqU5ZoTWWDZ0tGkAmh0w7jB0=; b=CYLOkSA9ZQBLgbYebxvVIo8hTgYLmuuVrxmlir48Gon5kBVnYvItvwS4j4BzKDcdz1 fSXh/LG0WI4BZ+dYAXpnZqcEnvxsI9cbkwFDpQMq66EVbIcL8QXywtmSQmykuk9vCy3E URn7/pjA8gT32OmW0XNwv856WV10us3AfFD1v8F/sOwDEM+2w5PEE6r1OWCM5oPjvbQz wJYvd+sOwoeEH8N2+hTwWxLi1dtSpCZ0/FcdTEB8bVY/bchdsQeC7DNWlJGuoBB7bRrU iEVe67MFqJHS0XSlGg4GfyRmvUsgujrSnXJYrfYEcGfmj+yfGS8cUYQnDXDmvjnrtXye bRBQ== X-Gm-Message-State: AOAM530deN/bo5faphcUQhtrqe5twBT3ygbTTBGH6ZmcIjQcT8rPGMDq Olhc5rm6U3oifd5/BMpQeAsDuAmPa87CNUc71CuJXg== X-Google-Smtp-Source: ABdhPJzOEy7fbRtbEdWVarYHqKmR1tOSbTWEITXIIEItkKfockhRbKiqFmxDLJR6Mefop1OoXiw55Z6JSl5vwlMKzgQ= X-Received: by 2002:a17:90a:ba88:: with SMTP id t8mr4489161pjr.229.1610623493993; Thu, 14 Jan 2021 03:24:53 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> In-Reply-To: From: Maxim Uvarov Date: Thu, 14 Jan 2021 14:24:43 +0300 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Peter Maydell Cc: Andrew Jones , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=maxim.uvarov@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 11:25:07 -0000 On Thu, 14 Jan 2021 at 14:22, Maxim Uvarov wrote: > > On Thu, 14 Jan 2021 at 12:50, Peter Maydell wrote: > > > > On Thu, 14 Jan 2021 at 00:04, Andrew Jones wrote: > > > > > > On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote: > > > > - the same size for secure and non secure gpio. Arm doc says that > > > > secure memory is also split on 4k pages. So one page here has to be > > > > ok. > > > > > > To be clear, does that means 4k pages must be used? I'm not concerned > > > with the size, but the alignment. If it's possible to use larger page > > > sizes with secure memory, then we need to align to the maximum page > > > size that may be used. > > > > I think we should just align on 64K, to be more future-proof. > > Even if secure software today uses 4K pages, it doesn't hurt > > to align the device such that some hypothetical future 64K > > page using secure software can use it. > > > > thanks > > -- PMM > > Does that mean that in that case you need all regions to be 64k > aligned? I mean secure and non-secure. > Has anybody tested 64k pages under qemu? > [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 } > [VIRT_UART] = { 0x09000000, 0x00001000 }, > [VIRT_RTC] = { 0x09010000, 0x00001000 }, > [VIRT_GPIO] = { 0x09030000, 0x00001000 }, > [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, > [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > Maxim. I.e. I see comment: * Note that devices should generally be placed at multiples of 0x10000, * to accommodate guests using 64K pages. */ but it's not clear why UART, RTC and GPIO is not aligned to 64k. From MAILER-DAEMON Thu Jan 14 06:48:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l017Q-0002sK-0I for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 06:48:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l017M-0002rV-VD for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:48:44 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:46613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l017K-0007Qu-BO for qemu-arm@nongnu.org; Thu, 14 Jan 2021 06:48:44 -0500 Received: by mail-ed1-x531.google.com with SMTP id dj23so2776301edb.13 for ; Thu, 14 Jan 2021 03:48:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=C+sesLtFIEUJvJejbtTvulbw9IeJhCwP1JS7j+Ki3e0=; b=UD/cn+xidaZQ0NxBesKmIeHvTCkhhmb6SXmEN1CDZNYXhJ9XQ4gO1sWSEqKrILBnOW WxgO+et1m3w3ODZuCSDbkJCtl9gAABajDdP2xSfYa2EOEt3rNalbP3ZNuMa0uacqRnhn uC/HSLkN88X8VkyUBeHeBYPTu93pAj1KGkdbEmOFGqtg+/VBf6khTbs8tfQgLSbCKmci DPQrqVsSkY44sSh6w8lv24SouOnqDAcYHfzPgx2ray9zddqMKAJQTkVoFUkUsEJNlS2R AQNoRDAcWt1DO9CyJWUcHbWpNkGMsZsS7fBwdsyojJaCjUWBuKcwb4U3jysZ7Rm2oOhE bAqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=C+sesLtFIEUJvJejbtTvulbw9IeJhCwP1JS7j+Ki3e0=; b=ZRny/J0qO9XVA/3zzM6yN93kjrmCQmNxUytwsBegl5kYSz3HWoc7EaNSq5EpEcp815 LIv28JICfJixhc6iGJ4XfdGP3EU4eybHBKTMbVfAAANPrv0vRPMVIhe2wLZMGSg+qGOA 9SI/3KmBB5Qti6/PGPuHB19JIEJwnjsCepEyTnWDDNaawnqLBQ3LAEs2m2NCXMqOpySb l40sbLhHgugvZdPKpexanqLdn8R6+MNpaMyRm1zVxw0i0tHu+s5u5hwNcAaM/iPbbZrZ GGRICaIFwU4nZBXWXGAB4eNQrF+mSPKj8EzbDvxVM7d7k4tFAS28wGUajGqDfUPNBY9T CW5Q== X-Gm-Message-State: AOAM532TFXytYA91Tz8Jf8XZ4gBUUct5HuJIZ4PBx1F3gLCxBdyqgXeE WJw9QBkF/pmhdtv2Ydb01jvo0yqzSs8IWxaw+n5txw== X-Google-Smtp-Source: ABdhPJwBdPdJktjjr1yHo2gL+Yj8yXHgQprXBNnNSeuTg8eFCf4/Hf+g5aE6ix2qe/lAVQsoduNLrCdSKlAcFuJW9Zs= X-Received: by 2002:aa7:cdc3:: with SMTP id h3mr5355613edw.52.1610624921067; Thu, 14 Jan 2021 03:48:41 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> In-Reply-To: From: Peter Maydell Date: Thu, 14 Jan 2021 11:48:29 +0000 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: Andrew Jones , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 11:48:45 -0000 On Thu, 14 Jan 2021 at 11:24, Maxim Uvarov wrote: > > On Thu, 14 Jan 2021 at 14:22, Maxim Uvarov wrote: > > Does that mean that in that case you need all regions to be 64k > > aligned? I mean secure and non-secure. > > Has anybody tested 64k pages under qemu? > > [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 } > > [VIRT_UART] = { 0x09000000, 0x00001000 }, > > [VIRT_RTC] = { 0x09010000, 0x00001000 }, > > [VIRT_GPIO] = { 0x09030000, 0x00001000 }, > > [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, > > [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > > > Maxim. > > I.e. I see comment: > * Note that devices should generally be placed at multiples of 0x10000, > * to accommodate guests using 64K pages. > */ > > but it's not clear why UART, RTC and GPIO is not aligned to 64k. Er, 0x09000000, 0x09010000 and 0x09030000 are all 64K aligned addresses. thanks -- PMM From MAILER-DAEMON Thu Jan 14 07:15:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l01XK-0001gH-AY for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 07:15:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l01XE-0001d9-U8 for qemu-arm@nongnu.org; Thu, 14 Jan 2021 07:15:28 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:41051) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l01XD-0002xX-7z for qemu-arm@nongnu.org; Thu, 14 Jan 2021 07:15:28 -0500 Received: by mail-pf1-x432.google.com with SMTP id q20so3230368pfu.8 for ; Thu, 14 Jan 2021 04:15:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7X+lubDSKfk7TLMh1SOru/tY8oaNpbVGrWzp2eEf4w0=; b=n+RnS3VWXTUwILu6vIoxx+b963jvhsaWN+C9HGRxLjqcEiJklyur8IEF2diYg9UJ5s akmKAIYS+8vI/SB/naQBAbwbTptwdn5QqOXmO57jp49ugv4kfp+JXPUDE/stLUOueHrn AoR1mOrFYi77U6kYweD3bJu5pd1mNMMZpXBS4Si5+ioLv/PCjcDKa7g0rCMhwU7fohuw 0WtfloxmVsb9uJ35MOQc+ta8qOW7KcA2tajUkl2ZVacRNN+qLmJoczFadOp5xg9wu+6T W8xu24O3nWpXBOzzFcFXb1f3qOlslwcPTIw/ymdn7AUsN2MRNKYtwVrVz2T5iPjLuymG UAtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7X+lubDSKfk7TLMh1SOru/tY8oaNpbVGrWzp2eEf4w0=; b=izZ6EeMich1pTOYEUi3JVRRypFuU2ve/NlCWXIo5GLNNYMSt92hOYIteQoh40QyAuT aDn87jCK7NSYQqnq1K9OSSxArtT1aZLRaPpszs+k0jD2eqqJ8YTYcUB/MRHlKH08SzrT irRcp53579DfF9RSfuhl9GmJp7fZI53FDqHqaFoa/SXygSds4mdYpZui55Y1BEAEK9yY vrXKFkJtBhX11+sMtLNCBOBZqolYLMMnvNcNn+jk2ybsl/ASa1kUDM7NRjNQ83PygPVQ yl2ijGB1upfWz3LIORX+vcpmmJ6e7MqBF9Vp1694HlKIGOjOTxydfpXFZx3669G8veuE V6UA== X-Gm-Message-State: AOAM5318jzexnA6WOt7r7Dm0KcIEsjdcJxcOTtUFNQTRiGehOfrCZ8jg BhjZsTMjk0dGzERWkAI/bIEAXfvzlqBjOFsebFdFkg== X-Google-Smtp-Source: ABdhPJxhbjgdDYDat2dx8ISpN6/uy0/Pn/bfdak1JEkySqw3RJeohHZcq0VtOzmbub4F9HEne5g1H5hZEE9jz9KKSJ8= X-Received: by 2002:a63:2d7:: with SMTP id 206mr7220626pgc.375.1610626525405; Thu, 14 Jan 2021 04:15:25 -0800 (PST) MIME-Version: 1.0 References: <20210112143058.12159-1-maxim.uvarov@linaro.org> <20210112143058.12159-3-maxim.uvarov@linaro.org> <20210112153542.oqahdubzeoipyvun@kamzik.brq.redhat.com> <20210112162526.ob7eroamrdlowfyr@kamzik.brq.redhat.com> <20210112162847.wik3h24isg4cmgyq@kamzik.brq.redhat.com> <20210114000445.mg3xq2nq7kccbvjy@kamzik.brq.redhat.com> In-Reply-To: From: Maxim Uvarov Date: Thu, 14 Jan 2021 15:15:14 +0300 Message-ID: Subject: Re: [PATCHv4 2/2] arm-virt: add secure pl061 for reset/power down To: Peter Maydell Cc: Andrew Jones , Jose Marinho , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , tf-a@lists.trustedfirmware.org, qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=maxim.uvarov@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 12:15:29 -0000 On Thu, 14 Jan 2021 at 14:48, Peter Maydell wrote: > > On Thu, 14 Jan 2021 at 11:24, Maxim Uvarov wrote: > > > > On Thu, 14 Jan 2021 at 14:22, Maxim Uvarov wrote: > > > Does that mean that in that case you need all regions to be 64k > > > aligned? I mean secure and non-secure. > > > Has anybody tested 64k pages under qemu? > > > [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 } > > > [VIRT_UART] = { 0x09000000, 0x00001000 }, > > > [VIRT_RTC] = { 0x09010000, 0x00001000 }, > > > [VIRT_GPIO] = { 0x09030000, 0x00001000 }, > > > [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, > > > [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, > > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > > > > > Maxim. > > > > I.e. I see comment: > > * Note that devices should generally be placed at multiples of 0x10000, > > * to accommodate guests using 64K pages. > > */ > > > > but it's not clear why UART, RTC and GPIO is not aligned to 64k. > > Er, 0x09000000, 0x09010000 and 0x09030000 are all 64K aligned addresses. > > thanks > -- PMM thanks, will send an updated version. From MAILER-DAEMON Thu Jan 14 09:50:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l03xV-0008L3-6n for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 09:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l03xT-0008IC-If for qemu-arm@nongnu.org; Thu, 14 Jan 2021 09:50:43 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:45308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l03xP-0003we-1P for qemu-arm@nongnu.org; Thu, 14 Jan 2021 09:50:43 -0500 Received: by mail-lf1-x131.google.com with SMTP id x20so8349628lfe.12 for ; Thu, 14 Jan 2021 06:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7anoKwBP87vLAvWcBLk7AZTOLxScckMQEoD5/U1zE7o=; b=dlsC61WJ6SmTN5scCL5r1LmlzI7M8vjlbgRFHSwngVPZMWwfK+CPH+YEA0nYQM7QIB N5Dxa70Ajnx21OedAMrvm1oVjuqDGrG/tV9wGHhwlQtt2SRHi7JS6IEkvAUhZqbhTmpJ LMLpmL2NZCzKWeB+oqbaUtRt1C7iaTten64LQ+I3kuUo7dSw6v3sqTHAET47zGsFgCAD DAERmnqJC/lAFTlH4vMsBbtG/MGQhy/8cUws5iZtPpivLf4xKmODCZxmNnSBsHCtVVIv jKwM8qbAzBGxtB8UqJ7rwIOM9vNCCeZbUdmHfx3J98IvPL/mEwPDRSsp62XWgF9Uuq0U nKGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7anoKwBP87vLAvWcBLk7AZTOLxScckMQEoD5/U1zE7o=; b=nMEjOX++p3zB0/abjjnvXXnK4+g5TaANlISNFohnR4g1CCHV5Yi+ZFAU3USliVHhyW q6wlHJf4EcjfYQpJ6112mk7JGabwl48CPYyL42XdVDQJoLtV1mKY3EVjuQo6MWYHPna8 ivke4DR3J6UR2iWlLMXZWGHaOd9bRA0z/A3z89lEE2MoxokHq3iEgCXFe3uRjCf4W1Dx EuT6vDwzF7JoYFjB0thzGZ6IzgMvFnV1RsAFHWVfZMKroG6q2AxOGSF15uoQ2t1GMZxY bedn08X32qh8PBbn66McZGiH4cA6RbqMNUhJSkUAwJo0aWF6shdZUxiyBdVexuOzEgI4 Ihhw== X-Gm-Message-State: AOAM532n+QnunXCGkud8B3bvmZa0z2V0lFZgRIiic7qvtNaBv9D53rvn pJ2IohkTSyipTpLq3ZQlKYdlPcu6ASCLqw== X-Google-Smtp-Source: ABdhPJwTQ34VgF9yuu9C2A1uizVGrax4Z5pztvXuYQ7ymIHYBXuBHk5lTMOkpLwKX9CDwIru2rgvjQ== X-Received: by 2002:a19:500a:: with SMTP id e10mr3420221lfb.193.1610635835331; Thu, 14 Jan 2021 06:50:35 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id p5sm567229lfj.295.2021.01.14.06.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 06:50:34 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv6 0/3] arm-virt: add secure pl061 for reset/power down Date: Thu, 14 Jan 2021 17:50:29 +0300 Message-Id: <20210114145032.8457-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 14:50:43 -0000 v6: - 64k align gpio memory region (Andrew Jones) - adjusted memory region to map this address in the corresponding atf patch v5: - removed vms flag, added fdt (Andrew Jones) - added patch3 to combine secure and non secure pl061. It has to be more easy to review if this changes are in the separate patch. v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/7556d07e87f755c602cd9d90359341bdd14d9d57 Previus discussion for reboot issue was here: https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html Maxim Uvarov (3): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: add secure pl061 for reset/power down arm-virt: combine code for secure and non secure pl061 hw/arm/Kconfig | 1 + hw/arm/virt.c | 118 +++++++++++++++++++++++++++++++++++------- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 2 + 6 files changed, 175 insertions(+), 20 deletions(-) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Thu Jan 14 09:50:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l03xY-0008RV-CE for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 09:50:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l03xT-0008HZ-3V for qemu-arm@nongnu.org; Thu, 14 Jan 2021 09:50:43 -0500 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]:40407) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l03xP-0003yH-Sg for qemu-arm@nongnu.org; Thu, 14 Jan 2021 09:50:42 -0500 Received: by mail-lf1-x129.google.com with SMTP id v24so1721225lfr.7 for ; Thu, 14 Jan 2021 06:50:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GLJ1M8gnJdgfUFe1l9HibzCxyIIEXe/s/L5DY+OCXTc=; b=yccVeNTkX7JqO7D2fwGTGVFNEGanxgpg12WMFY3+1xzD+iVzhSVASjIOQ1eAqoS0k1 WVwmrgVuQR1ZcX5BC21tfcN3Yzi2NBPqqppcvr4vURlmJh+7akNe/cCNxGHwiHIBK3bA WXS+dldLB4z+Ps63gSgR5Xpj1K+BPVG5jlrZIUuxXTxPwVnk6VutwzL0I0OxI8hzN1Yn /s8pILaPRJB+CCZVMCucfy7dKSpEYe+lo7Gi9CSj0CXnD2qPNvicC835UUJDNl4HHij+ uwVBowAiDAkIgkHu+bllk1oNr98eWJkhaNgBUAjHgoyu5VyZP33pX4hsfwmviYk0KvkN XBGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GLJ1M8gnJdgfUFe1l9HibzCxyIIEXe/s/L5DY+OCXTc=; b=Tn8WJqze1kv+/d9YHBdDBLy7AJQLAbewcoUu56dwOsSnlNmoRE95iGz7oSGbWbcwk/ PUYA5ijSnT4V5eLHxNw6dF0oVGywUVPCqpGSU3fsb0W3kAnwp3fRlQEI6KiUFE4C0VFn 2d02aRKXzHcbm6riEHrfONxL5nwdPObawKh64oA0T1OtXnZY5B+1hZgYmO0W20r0pbPT 2mBugXDPCbF6pPA/UYVVfOLf9YIPCXJPGxXHRIUfmYWuuoGiEZ1q2IBVMM5BUGw4zjmy DV9meW075IqtlrMKduLIuF4JebJJ9nywQWVGsJfoFtPGR4eaSxfEwmxCFQVfT5i/oMLU ZMTQ== X-Gm-Message-State: AOAM532MB04YnaHai8Sypdonk5eyoFfG9IxkOHLocgu1boHDJaeK0Cpi +4s7f2Guys9++dbigvlV3225rVhI7Q7gnA== X-Google-Smtp-Source: ABdhPJybY6boWnffnaxDt+buk0Fltf8GV924+jIBBKGl548wBkB+MLAvevSdc4gnZTZxAs4PKKDseg== X-Received: by 2002:a19:6a18:: with SMTP id u24mr3514564lfu.111.1610635837959; Thu, 14 Jan 2021 06:50:37 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id p5sm567229lfj.295.2021.01.14.06.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 06:50:37 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv6 2/3] arm-virt: add secure pl061 for reset/power down Date: Thu, 14 Jan 2021 17:50:31 +0300 Message-Id: <20210114145032.8457-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114145032.8457-1-maxim.uvarov@linaro.org> References: <20210114145032.8457-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 14:50:43 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 37 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..6f3ec15985 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -864,6 +865,32 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } +#define ATF_GPIO_POWEROFF 3 +#define ATF_GPIO_REBOOT 4 + +static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) +{ + DeviceState *gpio_pwr_dev; + SysBusDevice *s; + hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; + DeviceState *pl061_dev; + + /* Secure pl061 */ + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); +} + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -1993,6 +2020,10 @@ static void machvirt_init(MachineState *machine) create_gpio(vms); } + if (vms->secure && !vmc->no_secure_gpio) { + create_gpio_secure(vms, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2608,8 +2639,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..6f6c85ffcf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { -- 2.17.1 From MAILER-DAEMON Thu Jan 14 09:50:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l03xY-0008Rp-JM for mharc-qemu-arm@gnu.org; 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Thu, 14 Jan 2021 06:50:35 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv6 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Thu, 14 Jan 2021 17:50:30 +0300 Message-Id: <20210114145032.8457-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114145032.8457-1-maxim.uvarov@linaro.org> References: <20210114145032.8457-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 14:50:43 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov Reviewed-by: Hao Wu --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..8ed8d5d24f --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Thu Jan 14 09:50:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l03xY-0008SV-Pt for mharc-qemu-arm@gnu.org; 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Thu, 14 Jan 2021 06:50:38 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv6 3/3] arm-virt: combine code for secure and non secure pl061 Date: Thu, 14 Jan 2021 17:50:32 +0300 Message-Id: <20210114145032.8457-4-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114145032.8457-1-maxim.uvarov@linaro.org> References: <20210114145032.8457-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 14:50:45 -0000 Combine code for secure and non secure pl061 (gpio) with refining fdt creation. Signed-off-by: Maxim Uvarov --- hw/arm/virt.c | 122 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 83 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6f3ec15985..5317f32e3a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -821,35 +821,13 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms) +static void create_gpio_keys(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) { - char *nodename; - DeviceState *pl061_dev; - hwaddr base = vms->memmap[VIRT_GPIO].base; - hwaddr size = vms->memmap[VIRT_GPIO].size; - int irq = vms->irqmap[VIRT_GPIO]; - const char compat[] = "arm,pl061\0arm,primecell"; - - pl061_dev = sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); - - uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); - nodename = g_strdup_printf("/pl061@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", - 2, base, 2, size); - qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); - qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); - qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); - gpio_key_dev = sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); @@ -862,24 +840,16 @@ static void create_gpio(const VirtMachineState *vms) KEY_POWER); qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", "gpios", phandle, 3, 0); - g_free(nodename); } #define ATF_GPIO_POWEROFF 3 #define ATF_GPIO_REBOOT 4 -static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) +static void create_gpio_pwr(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) { DeviceState *gpio_pwr_dev; - SysBusDevice *s; - hwaddr base = vms->memmap[VIRT_SECURE_GPIO].base; - DeviceState *pl061_dev; - - /* Secure pl061 */ - pl061_dev = qdev_new("pl061"); - s = SYS_BUS_DEVICE(pl061_dev); - sysbus_realize_and_unref(s, &error_fatal); - memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); /* gpio-pwr */ gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); @@ -889,8 +859,82 @@ static void create_gpio_secure(const VirtMachineState *vms, MemoryRegion *mem) qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", + "label", "GPIO PWR Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", + ATF_GPIO_POWEROFF); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", + "gpios", phandle, 3, 0); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", + "label", "GPIO PWR Reboot"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", + ATF_GPIO_REBOOT); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", + "gpios", phandle, 3, 0); +} + +static void create_gpio_devices(const VirtMachineState *vms, int gpio, + MemoryRegion *mem) +{ + char *nodename; + DeviceState *pl061_dev; + hwaddr base = vms->memmap[gpio].base; + hwaddr size = vms->memmap[gpio].size; + int irq = vms->irqmap[gpio]; + const char compat[] = "arm,pl061\0arm,primecell"; + SysBusDevice *s; + + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); + + uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); + nodename = g_strdup_printf("/pl061@%" PRIx64, base); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); + qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); + + if (gpio == VIRT_GPIO) { + qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); + } else { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); + + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", + nodename); + } + g_free(nodename); + + /* Child gpio devices */ + if (gpio == VIRT_GPIO) { + create_gpio_keys(vms, pl061_dev, phandle); + } else { + create_gpio_pwr(vms, pl061_dev, phandle); + } } + static void create_virtio_devices(const VirtMachineState *vms) { int i; @@ -2017,11 +2061,11 @@ static void machvirt_init(MachineState *machine) if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms); + create_gpio_devices(vms, VIRT_GPIO, sysmem); } if (vms->secure && !vmc->no_secure_gpio) { - create_gpio_secure(vms, secure_sysmem); + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); } /* connect powerdown request */ -- 2.17.1 From MAILER-DAEMON Thu Jan 14 10:09:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04Fh-0005EQ-Ri for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:09:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04Ff-0005BL-PO; Thu, 14 Jan 2021 10:09:31 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:39713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04Fd-0003hn-P3; Thu, 14 Jan 2021 10:09:31 -0500 Received: by mail-pf1-x42b.google.com with SMTP id m6so3509067pfm.6; Thu, 14 Jan 2021 07:09:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=8UE5JTc8nfgwwuFsAclEJ0iZ4yiLi2DQhy02YDC7+JI=; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id w21sm5372051pfq.67.2021.01.14.07.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 07:09:26 -0800 (PST) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Francisco Iglesias Cc: Bin Meng , Marcin Krzeminski , Joe Komlodi , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Date: Thu, 14 Jan 2021 23:08:53 +0800 Message-Id: <20210114150902.11515-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:09:32 -0000 From: Bin Meng The m25p80 model uses s->needed_bytes to indicate how many follow-up bytes are expected to be received after it receives a command. For example, depending on the address mode, either 3-byte address or 4-byte address is needed. For fast read family commands, some dummy cycles are required after sending the address bytes, and the dummy cycles need to be counted in s->needed_bytes. This is where the mess began. As the variable name (needed_bytes) indicates, the unit is in byte. It is not in bit, or cycle. However for some reason the model has been using the number of dummy cycles for s->needed_bytes. The right approach is to convert the number of dummy cycles to bytes based on the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). Things get complicated when interacting with different SPI or QSPI flash controllers. There are major two cases: - Dummy bytes prepared by drivers, and wrote to the controller fifo. For such case, driver will calculate the correct number of dummy bytes and write them into the tx fifo. Fixing the m25p80 model will fix flashes working with such controllers. - Dummy bytes not prepared by drivers. Drivers just tell the hardware the dummy cycle configuration via some registers, and hardware will automatically generate dummy cycles for us. Fixing the m25p80 model is not enough, and we will need to fix the SPI/QSPI models for such controllers. This series fixes the mess in the m25p80 from the flash side first, followed by fixes to 3 known SPI controller models that fall into the 2nd case above. Please note, I have no way to verify patch 7/8/9 because: * There is no public datasheet available for the SoC / SPI controller * There is no QEMU docs, or details that tell people how to boot either U-Boot or Linux kernel to verify the functionality These 3 patches are very likely to be wrong. Hence I would like to ask help from the original author who wrote these SPI controller models to help testing, or completely rewrite these 3 patches to fix things. Thanks! Patch 6 is unvalidated with QEMU, mainly because there is no doc to tell people how to boot anything to test. But I have some confidence based on my read of the ZynqMP manual, as well as some experimental testing on a real ZCU102 board. Other flash patches can be tested with the SiFive SPI series: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=222391 Cherry-pick patch 16 and 17 from the series above, and switch to different flash model to test with the following command: $ qemu-system-riscv64 -nographic -M sifive_u -m 2G -smp 5 -kernel u-boot I've picked up two for testing: QEMU flash: "sst25vf032b" U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) CPU: rv64imafdcsu Model: SiFive HiFive Unleashed A00 DRAM: 2 GiB MMC: Loading Environment from SPIFlash... SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Net: failed to get gemgxl_reset reset Warning: ethernet@10090000 MAC addresses don't match: Address in DT is 52:54:00:12:34:56 Address in environment is 70:b3:d5:92:f0:01 eth0: ethernet@10090000 Hit any key to stop autoboot: 0 => sf probe SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, total 4 MiB => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 10 ticks, 400 KiB/s 3.200 Mbps 2 write: 170 ticks, 23 KiB/s 0.184 Mbps 3 read: 9 ticks, 444 KiB/s 3.552 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 10 ticks, 400 KiB/s 3.200 Mbps 2 write: 170 ticks, 23 KiB/s 0.184 Mbps 3 read: 9 ticks, 444 KiB/s 3.552 Mbps QEMU flash: "mx66u51235f" U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) CPU: rv64imafdcsu Model: SiFive HiFive Unleashed A00 DRAM: 2 GiB MMC: Loading Environment from SPIFlash... SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB *** Warning - bad CRC, using default environment In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Net: failed to get gemgxl_reset reset Warning: ethernet@10090000 MAC addresses don't match: Address in DT is 52:54:00:12:34:56 Address in environment is 70:b3:d5:92:f0:01 eth0: ethernet@10090000 Hit any key to stop autoboot: 0 => sf probe SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB => sf test 0 8000 SPI flash test: 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps 1 check: 80 ticks, 400 KiB/s 3.200 Mbps 2 write: 83 ticks, 385 KiB/s 3.080 Mbps 3 read: 79 ticks, 405 KiB/s 3.240 Mbps Test passed 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps 1 check: 80 ticks, 400 KiB/s 3.200 Mbps 2 write: 83 ticks, 385 KiB/s 3.080 Mbps 3 read: 79 ticks, 405 KiB/s 3.240 Mbps I am sure there will be bugs, and I have not tested all flashes affected. But I want to send out this series for an early discussion and comments. I will continue my testing. Bin Meng (9): hw/block: m25p80: Fix the number of dummy bytes needed for Windbond flashes hw/block: m25p80: Fix the number of dummy bytes needed for Numonyx/Micron flashes hw/block: m25p80: Fix the number of dummy bytes needed for Macronix flashes hw/block: m25p80: Fix the number of dummy bytes needed for Spansion flashes hw/block: m25p80: Support fast read for SST flashes hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command" Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic include/hw/ssi/aspeed_smc.h | 3 - hw/block/m25p80.c | 153 ++++++++++++++++++++++++++++-------- hw/ssi/aspeed_smc.c | 116 +-------------------------- hw/ssi/npcm7xx_fiu.c | 8 +- hw/ssi/xilinx_spips.c | 29 ++++++- 5 files changed, 153 insertions(+), 156 deletions(-) -- 2.25.1 From MAILER-DAEMON Thu Jan 14 10:10:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04Gm-0006Tq-HL for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:10:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04Gk-0006O1-3M; Thu, 14 Jan 2021 10:10:38 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:39918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04Ge-0004GC-Nl; Thu, 14 Jan 2021 10:10:37 -0500 Received: by mail-pj1-x1034.google.com with SMTP id u4so3346709pjn.4; Thu, 14 Jan 2021 07:10:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PiPI+CgLlpFSv2u7mJkxDRuWofaYNb842QPJItTkQ38=; b=VtN1Hex8SLAWi0tzmh4xr7xl5JyM2k2/LJjWGfFuytPyc/o87flnfDgp7c3PnHaGFa 2ohTFqIgnRx60iiiH9J2ivZyAWnE8X2+btWMopgm0ZuUWzDQOB4lyN8f0dkMU0cM5QBR YnzosbadCdLaeOVUoJ0Tew5x7LI4QIRKpw9AQ8ewC7vMroR7hihZSClW+EoYnEkLi+8O Oes+19Q+BgbKaIxoPbvcOTHgdkDkyHhXjw6FmzevH53UOlrUvcp+156lgWUCL5clfSGk J4rAEzfy//l3zbLhm6UeljMSkOiwyDCvdMzzRRYExN5rQ4QcjZOGnzpzUxzocALNrjxk CpXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PiPI+CgLlpFSv2u7mJkxDRuWofaYNb842QPJItTkQ38=; b=UJXhOTtVKQHdKSESRwVTurQ5oy725yMKy+ZU7QK5r+xgKPoy1cdtMB3dddvgR6Oi9S tWc0kmJqTMtNNN+sDZCthT5g6GGHGy+Hf/iVp+5IgsE7FIM5x5xrj5m69HAKj+0j1MT5 CJ6D33TK2P62lMwrw2fzYzF8Wmpmq9d/3Tn1ty0A25uF9GUbfuVDvedIW/ptBghqXFfs TdG2WfjK17nYrvzpOmWJg8Sju4PKxjHsnJGic3IMiMqBOjbPV8HyIe0wn9A2ZMF5P5jn 5w2rFj1Q8EsIks3IHcm/c8xvqMt2YTSnqQnhNpPrbnDqgPsDhgQwRpo7bYtamvr8a+VW Pzzg== X-Gm-Message-State: AOAM5337Tb+sC/ub9+zPoOW/92xZDawuEmr+kK6mpXfhntniFRVUNp5D ysYrhZP4vUtZphar7s9BmlV8QjS3ZC4= X-Google-Smtp-Source: ABdhPJzJWqjRCX51uPGs37ALsVHRkmRBaeMow6KAZv2IU598Yh3H238v6RnHptF0z6lcY0tYD33e5A== X-Received: by 2002:a17:90a:eac3:: with SMTP id ev3mr5290708pjb.27.1610637030962; Thu, 14 Jan 2021 07:10:30 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id w21sm5372051pfq.67.2021.01.14.07.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 07:10:30 -0800 (PST) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Francisco Iglesias Cc: Bin Meng , Xuzhou Cheng , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/9] hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling Date: Thu, 14 Jan 2021 23:08:59 +0800 Message-Id: <20210114150902.11515-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> References: <20210114150902.11515-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:10:38 -0000 From: Bin Meng The description of the genenic command fifo register says: When [receive, transmit, data_xfer] = [0,0,1], the [immediate_data] field represents the number of dummy cycle sent on the SPI interface. However we should not simply use the programmed value to determine how many times ssi_transfer() needs to be called to send the dummy bytes. ssi_transfer() is used to transfer a byte on the line, not a sigle bit. Previously the m25p80 flash model wronly implemented the dummy cycles for fast read command on some flashes. Now this mess is corrected and SPI flash controllers need to be updated to do the right thing. According to the example in the ZynqMP manual (ug1085, v2.2 [1]) we need to convert the number of dummy cycles to bytes according to the SPI mode being used, and transfer the bytes via ssi_transfer(). [1] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf table 24‐22, an example of Generic FIFO Contents for Quad I/O Read Command (EBh) Fixes: c95997a39de6 ("xilinx_spips: Add support for the ZynqMP Generic QSPI") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- hw/ssi/xilinx_spips.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a897034601..787de60f24 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -191,6 +191,10 @@ FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define GQSPI_GF_MODE_SPI 1 +#define GQSPI_GF_MODE_DSPI 2 +#define GQSPI_GF_MODE_QSPI 3 + #define R_GQSPI_MOD_ID (0x1fc / 4) #define R_GQSPI_MOD_ID_RESET (0x10a0000) @@ -492,7 +496,30 @@ static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) } s->regs[R_GQSPI_DATA_STS] = 1ul << imm; } else { - s->regs[R_GQSPI_DATA_STS] = imm; + /* + * When [receive, transmit, data_xfer] = [0,0,1], it represents + * the number of dummy cycle sent on the SPI interface. We need + * to convert the number of dummy cycles to bytes according to + * the SPI mode being used. + * + * Ref: ug1085 v2.2 (December 2020) table 24‐22, an example of + * Generic FIFO Contents for Quad I/O Read Command (EBh) + */ + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) && + !ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + uint8_t spi_mode = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, SPI_MODE); + if (spi_mode == GQSPI_GF_MODE_QSPI) { + s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 4, 8) / 8; + } else if (spi_mode == GQSPI_GF_MODE_DSPI) { + s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 2, 8) / 8; + } else if (spi_mode == GQSPI_GF_MODE_SPI) { + s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 1, 8) / 8; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "Unknown SPI MODE: 0x%x ", spi_mode); + } + } else { + s->regs[R_GQSPI_DATA_STS] = imm; + } } } /* Zero length transfer check */ -- 2.25.1 From MAILER-DAEMON Thu Jan 14 10:10:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04Gp-0006aE-1h for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:10:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04Gl-0006SH-SQ; Thu, 14 Jan 2021 10:10:39 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:40976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04Gk-0004IH-Bp; Thu, 14 Jan 2021 10:10:39 -0500 Received: by mail-pl1-x62e.google.com with SMTP id y8so3036730plp.8; Thu, 14 Jan 2021 07:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aqcTZr+UBuBY93y+f17AGADvFaFWY8Chw5yZcKTF3D0=; b=JKU55CeR1npS7xr1eJWnr1hhVThKFM4Ijo7B2CngTgj+MxyW4bqwMrAWCrbvTJX8An meQvHRssF3m6S3nymQzIjfDn29VTbhNZMyZ1zKV1t12jAH11YEOS6kjGbhgeiGTd9VWo tsMM479jNXSFDwuBTjUahXl/STQ245c3RHr7rVnTtOetR40zIwoaBoD8raWqZElQ0Uk2 MMM/CFA6OJ2q3WZdJyQswAcHz8p7aTclmkyMWGDV7sgE0fDO5oPvmsDBFSb7F1xqDXCe lPvuSlYJexAFjCv4z26m7q0DGtiKjZM+IevSaCJvuo9/NMTuycLICy/vqN58swB3IOjj hdmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aqcTZr+UBuBY93y+f17AGADvFaFWY8Chw5yZcKTF3D0=; b=hpNhRH0HZHumbrQ6ZEgve6DPAoHpvpbvLlOX/Kr+g6ZKUYSQBx4GNR7FecXWvOFgjC FpuC/lQF8VUqOXn+dc2dUiEpsbKtQM7BmfCw5ZIR8s8qJXjIjVXDfQjaa2F5sCCglBzw i3by5DyATqmhtmc8X/+9Qek9DDixC7M7S3w3b/X+Ad/QS2U1NyAD+dQABezUPOuYn4Mi Nk4a6LS3jNMPJTRzllK3Hnuyr6cPAZlE41tBU/2lN+f/lSBK/7qRHknG8uhCp7OvxS21 C5cURPks6C1p/XfHBrhiJjHD5DtPNwpjfhawTOj9FFe18VCZYrOa0+15rsHYEpQj2kKa 2FcQ== X-Gm-Message-State: AOAM53271X7Uj6c3RJGLgX5bXFx8onwi/3VbUSb3SGM+pb7YLA3OI4EI cG8RyEdXlkK7tsP1oDaYhqI= X-Google-Smtp-Source: ABdhPJxrZoAP9IB96M45BnxWp+3u/lnoA71AeQeoF8iWQb1yqrepe2PTTae+sFYFH3i44WBbJk3T2g== X-Received: by 2002:a17:902:9049:b029:da:efd6:4c12 with SMTP id w9-20020a1709029049b02900daefd64c12mr7862715plz.12.1610637036475; Thu, 14 Jan 2021 07:10:36 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id w21sm5372051pfq.67.2021.01.14.07.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 07:10:35 -0800 (PST) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Francisco Iglesias Cc: Bin Meng , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 7/9] Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command" Date: Thu, 14 Jan 2021 23:09:00 +0800 Message-Id: <20210114150902.11515-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> References: <20210114150902.11515-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:10:40 -0000 From: Bin Meng This reverts commit 7faf6f1790dddf9f3acf6ddd95f7bbc1b4a755d0. The incorrect implementation of dummy cycles in m25p80 model is now corrected. Revert this commit. Signed-off-by: Bin Meng --- hw/ssi/aspeed_smc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 16addee4dc..1e78b5232f 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -802,11 +802,11 @@ static int aspeed_smc_num_dummies(uint8_t command) case FAST_READ: case DOR: case QOR: - case FAST_READ_4: case DOR_4: case QOR_4: return 1; case DIOR: + case FAST_READ_4: case DIOR_4: return 2; case QIOR: -- 2.25.1 From MAILER-DAEMON Thu Jan 14 10:10:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04Gz-0006jx-Cq for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:10:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04Gs-0006fH-Nz; Thu, 14 Jan 2021 10:10:47 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:54333) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04Gp-0004LW-Dg; Thu, 14 Jan 2021 10:10:46 -0500 Received: by mail-pj1-x1034.google.com with SMTP id cq1so3230805pjb.4; Thu, 14 Jan 2021 07:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDI3Lg8zX7Mk9E+XiKTF8U/FUN1ufj38Nn84DY7D9Rg=; b=LvmPeXREe/DoGS3uPQpILVOB9giyOrwfc3z0kqGgCfcOOm/Z6ZJTpowkND+VrjA5r2 Ay4xDha+dF9O/CS7Bc9u/KTpMyzyZhMVBFvwKvyfg1NHh/yTv2QPX/441BN5vjDnnZFq 5t12+wmy1Qz+ThL71jwLR6Ut1gVUGCnIYxFFdkSoPQqyDlFiBQNG0Dyt9OdwgJAHrPuc C94S5QL1mjb9SnoGk8fom/WDi9uQdKZeOlByhlihl2WrK6p9mlsg94YJal/JEy1OGhar rsm1LlZuepUPGynuidFJkiqAvlnREuDeuyrwhhIN4q0i6CNMzO7S/fbgK0HeLHxi976e OmtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDI3Lg8zX7Mk9E+XiKTF8U/FUN1ufj38Nn84DY7D9Rg=; b=M0DEdLOznvyJJD/cqqunXWGz/N/GwYBb4ko5UoG1AMP/1e52oEpSOQTiklwHvFMJEQ x0x02aAsNo1wAXxxVfhCg912R6kEgT1h4Ecv/P3GV7NCB4Mb662CJn2S0yJ3BVlP0NHp zL9Mui+pH4Wwg4Yuknq7O0e0ExNjTOYUkBS79cW921bLl7qpyEZDmDJanY01O/MVROpm 5Zi4I7hgRa1eHEcGVmOxYcg769N9jeHPllLlAGXlD1QABKPYrXr9nx7BW5YmR3me4g9U /rYaAKA3jvatrmlsnuR0qwrktR0gSwzQhjcF474IsBwDcJWKbb6691zlMH3Kblm5oZey ZS9g== X-Gm-Message-State: AOAM532eKcGQfUo+gZTFbRqIvnCWhFec1FHvIvZwuKCeT5UuEQYwnpY4 UBWTsXjkOhQh3VEFQzha0mM= X-Google-Smtp-Source: ABdhPJwd8s1rQrbFIlXUOp+vVfbrBAxw6Rhp0DiXv+myD4YnzixKT6j3/Ym16AkbKV5y14V039QKRQ== X-Received: by 2002:a17:90a:5914:: with SMTP id k20mr5336869pji.199.1610637041843; Thu, 14 Jan 2021 07:10:41 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id w21sm5372051pfq.67.2021.01.14.07.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 07:10:41 -0800 (PST) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Francisco Iglesias Cc: Bin Meng , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 8/9] Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" Date: Thu, 14 Jan 2021 23:09:01 +0800 Message-Id: <20210114150902.11515-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> References: <20210114150902.11515-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:10:47 -0000 From: Bin Meng This reverts commit f95c4bffdc4c53b29f89762cab4adc5a43f95daf. The incorrect implementation of dummy cycles in m25p80 model is now corrected. Revert this commit. Signed-off-by: Bin Meng --- include/hw/ssi/aspeed_smc.h | 3 - hw/ssi/aspeed_smc.c | 116 +----------------------------------- 2 files changed, 2 insertions(+), 117 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 16c03fe64f..46f3abf2e7 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -111,9 +111,6 @@ struct AspeedSMCState { AddressSpace dram_as; AspeedSMCFlash *flashes; - - uint8_t snoop_index; - uint8_t snoop_dummies; }; #endif /* ASPEED_SMC_H */ diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 1e78b5232f..0df5d91d19 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -187,9 +187,6 @@ /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ -#define SNOOP_OFF 0xFF -#define SNOOP_START 0x0 - /* * Default segments mapping addresses and size for each peripheral per * controller. These can be changed when board is initialized with the @@ -771,104 +768,6 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) return ret; } -/* - * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a - * common include header. - */ -typedef enum { - READ = 0x3, READ_4 = 0x13, - FAST_READ = 0xb, FAST_READ_4 = 0x0c, - DOR = 0x3b, DOR_4 = 0x3c, - QOR = 0x6b, QOR_4 = 0x6c, - DIOR = 0xbb, DIOR_4 = 0xbc, - QIOR = 0xeb, QIOR_4 = 0xec, - - PP = 0x2, PP_4 = 0x12, - DPP = 0xa2, - QPP = 0x32, QPP_4 = 0x34, -} FlashCMD; - -static int aspeed_smc_num_dummies(uint8_t command) -{ - switch (command) { /* check for dummies */ - case READ: /* no dummy bytes/cycles */ - case PP: - case DPP: - case QPP: - case READ_4: - case PP_4: - case QPP_4: - return 0; - case FAST_READ: - case DOR: - case QOR: - case DOR_4: - case QOR_4: - return 1; - case DIOR: - case FAST_READ_4: - case DIOR_4: - return 2; - case QIOR: - case QIOR_4: - return 4; - default: - return -1; - } -} - -static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, - unsigned size) -{ - AspeedSMCState *s = fl->controller; - uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; - - trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies, - (uint8_t) data & 0xff); - - if (s->snoop_index == SNOOP_OFF) { - return false; /* Do nothing */ - - } else if (s->snoop_index == SNOOP_START) { - uint8_t cmd = data & 0xff; - int ndummies = aspeed_smc_num_dummies(cmd); - - /* - * No dummy cycles are expected with the current command. Turn - * off snooping and let the transfer proceed normally. - */ - if (ndummies <= 0) { - s->snoop_index = SNOOP_OFF; - return false; - } - - s->snoop_dummies = ndummies * 8; - - } else if (s->snoop_index >= addr_width + 1) { - - /* The SPI transfer has reached the dummy cycles sequence */ - for (; s->snoop_dummies; s->snoop_dummies--) { - ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); - } - - /* If no more dummy cycles are expected, turn off snooping */ - if (!s->snoop_dummies) { - s->snoop_index = SNOOP_OFF; - } else { - s->snoop_index += size; - } - - /* - * Dummy cycles have been faked already. Ignore the current - * SPI transfer - */ - return true; - } - - s->snoop_index += size; - return false; -} - static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { @@ -887,10 +786,6 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, switch (aspeed_smc_flash_mode(fl)) { case CTRL_USERMODE: - if (aspeed_smc_do_snoop(fl, data, size)) { - break; - } - for (i = 0; i < size; i++) { ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); } @@ -937,8 +832,6 @@ static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) s->regs[s->r_ctrl0 + fl->id] = value; - s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; - aspeed_smc_flash_do_select(fl, unselect); } @@ -981,9 +874,6 @@ static void aspeed_smc_reset(DeviceState *d) if (s->ctrl->segments == aspeed_segments_fmc) { s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); } - - s->snoop_index = SNOOP_OFF; - s->snoop_dummies = 0; } static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) @@ -1419,12 +1309,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) static const VMStateDescription vmstate_aspeed_smc = { .name = "aspeed.smc", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 1, + .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), - VMSTATE_UINT8(snoop_index, AspeedSMCState), - VMSTATE_UINT8(snoop_dummies, AspeedSMCState), VMSTATE_END_OF_LIST() } }; -- 2.25.1 From MAILER-DAEMON Thu Jan 14 10:10:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04H3-0006oT-VS for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:10:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04H1-0006lw-Bf; Thu, 14 Jan 2021 10:10:55 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04Gy-0004Pl-Rh; Thu, 14 Jan 2021 10:10:55 -0500 Received: by mail-pl1-x634.google.com with SMTP id y8so3037022plp.8; Thu, 14 Jan 2021 07:10:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nT1NO2oOvTRXnT4qmsBpHS5imQeak8IMZL/sVV5o5Vs=; b=LLUhAHpDznGtgVX4SwtAGTx6bIAskvxzSVPIaWOkK++VTLzFSiZFm/OjRDiPiQQbY3 rVf3iUKibyMo4IOQ8A5BoL1/UJoayktKfTcVoephxSxQO9Og1KoeQl86ZMY3J8MxpD96 wmRTv9DPc2RHJbVyefvmnKYOJq/IH6tVWD8pkC8fmNBOrH5Ky9ZS4qS00ZXOQqlLWZaa pqNAFwd7yAW1H5s8VO4vQHbrT1oVDryoXPUkQyWvUmTQHp7rTCnfYZ3nS6M7L3LCkB0A RyKgSV9oUq5lmW0weH43Gdn8RXY6i80T9jxPwgkJ6cgLdMslzukVNxkI858YT5awKjJS xx5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nT1NO2oOvTRXnT4qmsBpHS5imQeak8IMZL/sVV5o5Vs=; b=oE6hSv+OzO6/KqP//kL1kPCf3UIxVZf+57Y0xhmW0vFsD22xDf3uNkF2+gsr8MC7BC mRBWYPB0AZljhLlYTExUTaJ4khovgCiDGXtgbCy1B+XgFoZq8WFcN9jSl/LdQmbSMGbH MqCujo1KPwr0lZI4NmFIQwKbH/oPsVy17RMkAEo+KkQigKlpWU3P/6pVhZ/S45Ejgb+u alDL81Uu77zLM31JPRl+0vBhlwUOplXjpqfvR2XV9aRKKM7E78QZUTsjUiXm7+m5ioQD v77QmC1WV89d4vYIGz6HwG5En6Gbt/0P1OQjRgE0aYO4SnYtC0waPQo4LBb7jl2GaLNZ Jrlw== X-Gm-Message-State: AOAM531vQU4X1ZpXYc9vUcH2IIacWvQUJeQyhVC4DJmfTDT+Vy25kjyr gsrroGDrk6oRJk5MDOzi0fyAaNHU1MQ= X-Google-Smtp-Source: ABdhPJws17aYgRAZ8cQgSVDAQUn8sw7HD1ZSvPycsplWpThXUQF8EQPu1JB9eTQ1zlO7iSZ3/zs8NA== X-Received: by 2002:a17:90a:6401:: with SMTP id g1mr5273691pjj.165.1610637048889; Thu, 14 Jan 2021 07:10:48 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id w21sm5372051pfq.67.2021.01.14.07.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 07:10:48 -0800 (PST) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Francisco Iglesias Cc: Bin Meng , Havard Skinnemoen , Tyrone Ting , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 9/9] hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic Date: Thu, 14 Jan 2021 23:09:02 +0800 Message-Id: <20210114150902.11515-10-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> References: <20210114150902.11515-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:10:56 -0000 From: Bin Meng I believe send_dummy_bits() should also be fixed, but I really don't know how based on my pure read/guess of the codes since there is no public datasheet available for this NPCM7xx SoC. Signed-off-by: Bin Meng --- hw/ssi/npcm7xx_fiu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 5040132b07..e76fb5ad9f 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -150,7 +150,7 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, NPCM7xxFIUState *fiu = f->fiu; uint64_t value = 0; uint32_t drd_cfg; - int dummy_cycles; + int dummy_bytes; int i; if (fiu->active_cs != -1) { @@ -180,10 +180,8 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, break; } - /* Flash chip model expects one transfer per dummy bit, not byte */ - dummy_cycles = - (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg); - for (i = 0; i < dummy_cycles; i++) { + dummy_bytes = FIU_DRD_CFG_DBW(drd_cfg) >> FIU_DRD_CFG_ACCTYPE(drd_cfg); + for (i = 0; i < dummy_bytes; i++) { ssi_transfer(fiu->spi, 0); } -- 2.25.1 From MAILER-DAEMON Thu Jan 14 10:49:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l04s1-0000cQ-10 for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 10:49:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l04s0-0000aC-1N; Thu, 14 Jan 2021 10:49:08 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:33714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l04rx-0004rD-4L; Thu, 14 Jan 2021 10:49:06 -0500 Received: by mail-wr1-x434.google.com with SMTP id t30so6297719wrb.0; Thu, 14 Jan 2021 07:49:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=3x0O8sPNXEDYftnuGsjOeZIu2Ubh3rhs2GG4FkkBl5M=; b=BRtb84e0mahJhjpESPiR25z/dIoIswKCdGQlfDurjL7ceaB23gSSfX3pirb8BpgtLi Z0M0jcwu6yXQQE8F8B4kNK3CKCZGHe5M5Cc9uW7gHUEgPUpRVylzZAzohwqXq5aDySqu gCN8RXTdEm7HAQ/cpQCA+CxG3+gP3hiZkrlSEsjGR1dnTLZla6p6KdvPYd9ePf8g746B XwUfa8srWqcAE+IncAIVKG//AmeRStnAbcf0v3MQSqU1YhAa5T75zNT2GGgpUqY5W0x2 tCEjojaiCj+t9ho3vWMneSYvEuuDdI0eYo+1UeZt0Wyv32huf0gJavDz/hY/BeSMuZfk 8LvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3x0O8sPNXEDYftnuGsjOeZIu2Ubh3rhs2GG4FkkBl5M=; b=GNJ6Tsx7XObq3tSD0FpJhDXrt8AbjCkWAVUdQjsFkZCKH31N5OCLldGpjGOL3mXH75 iOO/2zpUD11HgFnHr57m7pw2KnYS4ik4aV6nMKoRhNSv2zkfD8W4rSRnvbA5Ivuwn76Y u/Ru6UXJx2Kz4Nxx8sWtchxf+8rEa/q3hQEITIJS7h5zbkzivBtxdi1pg2e07Z1YFWUG yNuIlCqo53piFuMJIFiLgUJb8kPhVseFfPaxUjDV5RDmW3TuGKy2HUZR4Ra4C7/St+pR XKuAbrmg17LsQPn0UiAQX4gBdBH0TIo5H9aqnJvd4meyocITf+MY4WLt12f1relSXLWA HeRQ== X-Gm-Message-State: AOAM530WiQjCExWFXZtLmx1TO0Kt37E8d6pBi6q/6x9KkP+6/HxFTDIv 0dzQncV8/qtUXwUQv+aRe+c= X-Google-Smtp-Source: ABdhPJxTetp2r5RZzf3ZoUqszMuaWnagUi5z6kNXw3xapm69Q1iSA/EoT0ofiVPgoEpQX5n7FPdCLw== X-Received: by 2002:a5d:43ce:: with SMTP id v14mr8551968wrr.342.1610639343004; Thu, 14 Jan 2021 07:49:03 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id h187sm9015911wmf.30.2021.01.14.07.49.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Jan 2021 07:49:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 00/18] hw: Mark the device with no migratable fields To: Peter Maydell , Eduardo Habkost , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Paolo Bonzini , Laurent Vivier , Gerd Hoffmann Cc: QEMU Developers , Artyom Tarasenko , "Dr . David Alan Gilbert" , qemu-arm , Marcel Apfelbaum , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Andrew Baumann , Joel Stanley , Subbaraya Sundeep , Mark Cave-Ayland , Andrew Jeffery , Juan Quintela References: <20200703201911.26573-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <17a5ddc4-c7d9-08f3-5260-f17e1bd48dac@amsat.org> Date: Thu, 14 Jan 2021 16:49:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.237, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 15:49:08 -0000 On 7/9/20 9:19 PM, Peter Maydell wrote: > On Fri, 3 Jul 2020 at 21:19, Philippe Mathieu-Daudé wrote: >> >> This is a proof-of-concept after chatting with Peter Maydell >> on IRC earlier. >> >> Introduce the vmstate_no_state_to_migrate structure, and >> a reference to it: vmstate_qdev_no_state_to_migrate. >> Use this reference in devices with no fields to migrate. >> >> This is useful to catch devices missing vmstate, such: >> - ads7846 >> - mcf-uart >> - mcf-fec >> - versatile_i2c >> - ... >> >> I am not sure about: >> - gpex-pcihost > > I think it's correct that this has no internal state: > the only interesting state is in the GPEXRootState, which > is a TYPE_GPEX_ROOT_DEVICE which migrates itself. > > I made some comments on the "meaty" bits of the patchset, > and reviewed one or two of the "mark this device as > having no migration state" patches, but it doesn't seem > worth reviewing all of them until the migration submaintainers > have a chance to weigh in on whether they like the concept > (I expect they're busy right now with freeze-related stuff :-)) Now that we are far from freeze-date is a good time to ping again on this concept :) Most of the devices are ARM except: - cpu-cluster (Eduardo/Marcel) - hcd-ohci (Gerd) - mac-nubus-bridge (Laurent) - generic QOM (Daniel, Paolo) Is someone against this proposal? Regards, Phil. From MAILER-DAEMON Thu Jan 14 11:00:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l052h-00021o-AO for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 11:00:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l052f-0001za-MZ for qemu-arm@nongnu.org; Thu, 14 Jan 2021 11:00:09 -0500 Received: from 9.mo52.mail-out.ovh.net ([87.98.180.222]:36839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l052c-00018G-An for qemu-arm@nongnu.org; Thu, 14 Jan 2021 11:00:09 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.108.16.128]) by mo52.mail-out.ovh.net (Postfix) with ESMTPS id 4C695231676; Thu, 14 Jan 2021 16:59:59 +0100 (CET) Received: from kaod.org (37.59.142.100) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2044.4; Thu, 14 Jan 2021 16:59:57 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-100R00388bc89b7-cbe8-4be9-8d74-fcfb2ec391f6, 7B7BC4A7E5590C2C5C4BA269602926DB4F481435) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Bin Meng , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell , Francisco Iglesias CC: Bin Meng , Marcin Krzeminski , Joe Komlodi , Andrew Jeffery , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , , , References: <20210114150902.11515-1-bmeng.cn@gmail.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <78a12882-1303-dd6d-6619-96c5e2cbf531@kaod.org> Date: Thu, 14 Jan 2021 16:59:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [37.59.142.100] X-ClientProxiedBy: DAG4EX1.mxp5.local (172.16.2.31) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 267b0d79-ded8-4c90-968c-87e917200ef6 X-Ovh-Tracer-Id: 7673570815610620743 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -83 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduledrtddtgdehlecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenfghrlhcuvffnffculddujedmnecujfgurhepuffvfhfhkffffgggjggtgfhisehtjeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepgefgueeflefgfefgjeeffffhgeeufeduiedtkeekheduveeffeeuhedutdeglefhnecuffhomhgrihhnpehgihhthhhusgdrtghomhdpqhgvmhhurdhorhhgpdhophgvnhhpohifvghrrdighiiipdhoiihlrggsshdrohhrghenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddruddttdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehmgihplhgrnhehrdhmrghilhdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepsghmvghnghdrtghnsehgmhgrihhlrdgtohhm Received-SPF: pass client-ip=87.98.180.222; envelope-from=clg@kaod.org; helo=9.mo52.mail-out.ovh.net X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.237, PDS_OTHER_BAD_TLD=1.997, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 16:00:10 -0000 On 1/14/21 4:08 PM, Bin Meng wrote: > From: Bin Meng > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > bytes are expected to be received after it receives a command. For > example, depending on the address mode, either 3-byte address or > 4-byte address is needed. > > For fast read family commands, some dummy cycles are required after > sending the address bytes, and the dummy cycles need to be counted > in s->needed_bytes. This is where the mess began. > > As the variable name (needed_bytes) indicates, the unit is in byte. > It is not in bit, or cycle. However for some reason the model has > been using the number of dummy cycles for s->needed_bytes. The right > approach is to convert the number of dummy cycles to bytes based on > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > Things get complicated when interacting with different SPI or QSPI > flash controllers. There are major two cases: > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > For such case, driver will calculate the correct number of dummy > bytes and write them into the tx fifo. Fixing the m25p80 model will > fix flashes working with such controllers. > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > the dummy cycle configuration via some registers, and hardware will > automatically generate dummy cycles for us. Fixing the m25p80 model > is not enough, and we will need to fix the SPI/QSPI models for such > controllers. > > This series fixes the mess in the m25p80 from the flash side first, > followed by fixes to 3 known SPI controller models that fall into > the 2nd case above. > > Please note, I have no way to verify patch 7/8/9 because: > > * There is no public datasheet available for the SoC / SPI controller > * There is no QEMU docs, or details that tell people how to boot either > U-Boot or Linux kernel to verify the functionality The Linux drivers are available in mainline but these branches are more up to date since not everything is merged : https://github.com/openbmc/linux u-boot : https://github.com/openbmc/u-boot/tree/v2016.07-aspeed-openbmc (ast2400/ast2500) https://github.com/openbmc/u-boot/tree/v2019.04-aspeed-openbmc (ast2600) A quick intro : https://www.qemu.org/docs/master/system/arm/aspeed.html > > These 3 patches are very likely to be wrong. Hence I would like to ask > help from the original author who wrote these SPI controller models > to help testing, or completely rewrite these 3 patches to fix things. > Thanks! A quick test shows that all Aspeed machines are broken with this patchset. Please try these command lines : wget https://openpower.xyz/job/openbmc-build/lastSuccessfulBuild/distro=ubuntu,label=builder,target=palmetto/artifact/deploy/images/palmetto/flash-palmetto wget https://openpower.xyz/job/openbmc-build/lastSuccessfulBuild/distro=ubuntu,label=builder,target=romulus/artifact/deploy/images/romulus/flash-romulus wget https://openpower.xyz/job/openbmc-build/lastSuccessfulBuild/distro=ubuntu,label=builder,target=witherspoon/artifact/deploy/images/witherspoon/obmc-phosphor-image-witherspoon.ubi.mtd qemu-system-arm -M witherspoon-bmc -nic user -drive file=obmc-phosphor-image-witherspoon.ubi.mtd,format=raw,if=mtd -nographic qemu-system-arm -M romulus-bmc -nic user -drive file=flash-romulus,format=raw,if=mtd -nographic qemu-system-arm -M palmetto-bmc -nic user -drive file=flash-palmetto,format=raw,if=mtd -nographic The Aspeed SMC model has traces to help you in the task. Thanks, C. > Patch 6 is unvalidated with QEMU, mainly because there is no doc to > tell people how to boot anything to test. But I have some confidence > based on my read of the ZynqMP manual, as well as some experimental > testing on a real ZCU102 board. > > Other flash patches can be tested with the SiFive SPI series: > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=222391 > > Cherry-pick patch 16 and 17 from the series above, and switch to > different flash model to test with the following command: > > $ qemu-system-riscv64 -nographic -M sifive_u -m 2G -smp 5 -kernel u-boot > > I've picked up two for testing: > > QEMU flash: "sst25vf032b" > > U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) > > CPU: rv64imafdcsu > Model: SiFive HiFive Unleashed A00 > DRAM: 2 GiB > MMC: > Loading Environment from SPIFlash... SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, total 4 MiB > *** Warning - bad CRC, using default environment > > In: serial@10010000 > Out: serial@10010000 > Err: serial@10010000 > Net: failed to get gemgxl_reset reset > > Warning: ethernet@10090000 MAC addresses don't match: > Address in DT is 52:54:00:12:34:56 > Address in environment is 70:b3:d5:92:f0:01 > eth0: ethernet@10090000 > Hit any key to stop autoboot: 0 > => sf probe > SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, > total 4 MiB > => sf test 1ff000 1000 > SPI flash test: > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 10 ticks, 400 KiB/s 3.200 Mbps > 2 write: 170 ticks, 23 KiB/s 0.184 Mbps > 3 read: 9 ticks, 444 KiB/s 3.552 Mbps > Test passed > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 10 ticks, 400 KiB/s 3.200 Mbps > 2 write: 170 ticks, 23 KiB/s 0.184 Mbps > 3 read: 9 ticks, 444 KiB/s 3.552 Mbps > > QEMU flash: "mx66u51235f" > > U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) > > CPU: rv64imafdcsu > Model: SiFive HiFive Unleashed A00 > DRAM: 2 GiB > MMC: > Loading Environment from SPIFlash... SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB > *** Warning - bad CRC, using default environment > > In: serial@10010000 > Out: serial@10010000 > Err: serial@10010000 > Net: failed to get gemgxl_reset reset > > Warning: ethernet@10090000 MAC addresses don't match: > Address in DT is 52:54:00:12:34:56 > Address in environment is 70:b3:d5:92:f0:01 > eth0: ethernet@10090000 > Hit any key to stop autoboot: 0 > => sf probe > SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB > => sf test 0 8000 > SPI flash test: > 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps > 1 check: 80 ticks, 400 KiB/s 3.200 Mbps > 2 write: 83 ticks, 385 KiB/s 3.080 Mbps > 3 read: 79 ticks, 405 KiB/s 3.240 Mbps > Test passed > 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps > 1 check: 80 ticks, 400 KiB/s 3.200 Mbps > 2 write: 83 ticks, 385 KiB/s 3.080 Mbps > 3 read: 79 ticks, 405 KiB/s 3.240 Mbps > > I am sure there will be bugs, and I have not tested all flashes affected. > But I want to send out this series for an early discussion and comments. > I will continue my testing. > > > Bin Meng (9): > hw/block: m25p80: Fix the number of dummy bytes needed for Windbond > flashes > hw/block: m25p80: Fix the number of dummy bytes needed for > Numonyx/Micron flashes > hw/block: m25p80: Fix the number of dummy bytes needed for Macronix > flashes > hw/block: m25p80: Fix the number of dummy bytes needed for Spansion > flashes > hw/block: m25p80: Support fast read for SST flashes > hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling > Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 > command" > Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" > hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic > > include/hw/ssi/aspeed_smc.h | 3 - > hw/block/m25p80.c | 153 ++++++++++++++++++++++++++++-------- > hw/ssi/aspeed_smc.c | 116 +-------------------------- > hw/ssi/npcm7xx_fiu.c | 8 +- > hw/ssi/xilinx_spips.c | 29 ++++++- > 5 files changed, 153 insertions(+), 156 deletions(-) > From MAILER-DAEMON Thu Jan 14 11:00:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0534-0002HW-Ki for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 11:00:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l052u-0002Fc-6y; Thu, 14 Jan 2021 11:00:26 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:53435) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l052p-0001Gv-EU; Thu, 14 Jan 2021 11:00:22 -0500 Received: by mail-wm1-x330.google.com with SMTP id k10so4969511wmi.3; Thu, 14 Jan 2021 08:00:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=5XT/S1rmYl0aWz2RdxT7IxZAvLzn8PyBUJ4yxYv5shI=; b=BT8rT0TyBSUawHM+bnX+b+enr+CCK8H5JsispZcM83yBu7JIwgg563RdExVPTylEJ7 k8qy1SFEYyAtSnF/b8U6f+20Y5JwpuI9Ecv05/Z8FMdePDsz1WoyjpWC2vpOqdA8VtpB k1g90Z8jEDVAbTMsVCB0oekZgDhzH4JoS5bccGXWjT+HrGTGy5KCRyubeCrVNZcL4zYp 3LYXXDH9fTeEAkfHnLF4+kdZCvdM/QL1dAIQe4HYdEJsZWBCjLftriMF3KNCBjt5T22m d2gvXxe+hSssQ7oExRlKlNePNVN1oLUGhlqjeGnzUz4GDwVKzOmgpT6vzQWQkCkaEzCD OFtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:from:to:cc:references:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=5XT/S1rmYl0aWz2RdxT7IxZAvLzn8PyBUJ4yxYv5shI=; b=uJnb4jChu02SjBzpXUbT9fAB/CFsNy/hqPyY9QVK5CJLCClUkmoE5rtp2gLnpr2rGn 3y+0Mns6uc/ji6gH/1roLKpzRKuPFoNJLqSrfDEy8wgo08VsalHgFd0YCO2qGGKd6pFy UrBSLdUFV5c8BABJNxzVvoXFMUOetvK2zPUn4HmCdsazHIFBjirESGmCv5StDmeG/6+P +YKIgmjnrZoh8PRI7uQVyNOytgRkyd7D4yrhM3+HmuFjVsCl0VmELSxj/tCNba7oL19c bTPFtk9MfITRtSNcc1lqJA9ucJRf2SR1A2Z50q3m/OkQSTGDhXUYVdeJ0YAPz4m5AT/N C0tA== X-Gm-Message-State: AOAM531e8jLWohCWU/eFHWifvmdlLmYg97ZlZmxt1E8LQaMeHGIXfSVc 9N88VUgm5bLuq0LsDV6dmDk= X-Google-Smtp-Source: ABdhPJziXEgOFCA2hXbICC05y4iYG6fN8J9F7joacO9vFAlu1/gMVI+LWcXeSIodBoctmKm4XPlOiQ== X-Received: by 2002:a1c:220b:: with SMTP id i11mr4671626wmi.8.1610640017531; Thu, 14 Jan 2021 08:00:17 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id a24sm2979691wmj.17.2021.01.14.08.00.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Jan 2021 08:00:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Bin Meng Cc: Peter Maydell , Alistair Francis , Xuzhou Cheng , Bin Meng , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210112183529.2011863-1-f4bug@amsat.org> <74a2566b-cd32-743f-8088-c59e992be755@amsat.org> <7c8e33c2-d86a-44ef-8d4c-0f6dcf9f7b2c@amsat.org> Message-ID: Date: Thu, 14 Jan 2021 17:00:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <7c8e33c2-d86a-44ef-8d4c-0f6dcf9f7b2c@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.237, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 16:00:28 -0000 Hi Ben, On 1/13/21 6:56 PM, Philippe Mathieu-Daudé wrote: > On 1/13/21 2:27 PM, Bin Meng wrote: >> Hi Philippe, >> >>>> Unfortunately this series breaks SPI flash testing under both U-Boot >>>> and VxWorks 7. >>> >>> Thanks for testing :) Can you provide the binary tested and the command >>> line used? At least one, so I can have a look. >> >> Sure, will send you offline. > > Arf, stupid mistake in patch 7 :) With this diff I can run your > test: > > -- >8 -- > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -343,7 +343,7 @@ static void imx_spi_write(void *opaque, hwaddr > offset, uint64_t value, > return; > } > s->regs[ECSPI_CONREG] = value; > - if (value & ECSPI_CONREG_EN) { > + if (!(value & ECSPI_CONREG_EN)) { > /* Keep disabled */ > return; > } > --- Could you have a try at this? Do you prefer I resubmit the whole series? Thanks, Phil. From MAILER-DAEMON Thu Jan 14 11:03:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l056K-0003s2-CA for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 11:03:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l056I-0003r7-IC for qemu-arm@nongnu.org; Thu, 14 Jan 2021 11:03:54 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:51707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l056F-0002ew-CO for qemu-arm@nongnu.org; Thu, 14 Jan 2021 11:03:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610640226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZLCvurpnBG5U2vJ3uC0YnZuSpg2DuU2aBar4wPu5hl8=; b=aOHZomdeSM1ra+seMg1gpWNIacpkwQx0DFBrHMtIZD7MF+YI7L4i6j0CjfvVriypaTAjIv Yu4LRKToAUH5fNxpEB8v0coH7xLBVCEBQ1vh32+V7nJs7sCR2NQVV3zd76AlJnd3Z6weuY O3cafQt4TSNORnLcVI7IwlOMxEhUxmI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-491-ViwbLcTkPxqfjLd_vJJRNQ-1; Thu, 14 Jan 2021 11:03:42 -0500 X-MC-Unique: ViwbLcTkPxqfjLd_vJJRNQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 00C74EC1A5; Thu, 14 Jan 2021 16:03:41 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-112-154.rdu2.redhat.com [10.10.112.154]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C98A0100AE40; Thu, 14 Jan 2021 16:03:38 +0000 (UTC) Date: Thu, 14 Jan 2021 11:03:35 -0500 From: Andrew Jones To: Maxim Uvarov Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org Subject: Re: [PATCHv6 0/3] arm-virt: add secure pl061 for reset/power down Message-ID: <20210114160335.hvqdh7mqmm3vff52@kamzik.brq.redhat.com> References: <20210114145032.8457-1-maxim.uvarov@linaro.org> MIME-Version: 1.0 In-Reply-To: <20210114145032.8457-1-maxim.uvarov@linaro.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.248, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 16:03:54 -0000 On Thu, Jan 14, 2021 at 05:50:29PM +0300, Maxim Uvarov wrote: > v6: - 64k align gpio memory region (Andrew Jones) > - adjusted memory region to map this address in the corresponding atf patch > v5: - removed vms flag, added fdt (Andrew Jones) > - added patch3 to combine secure and non secure pl061. It has to be I think you should do non-functional change refactoring in patch 2 and then add the device with the DTB updates in patch 3. Thanks, drew > more easy to review if this changes are in the separate patch. > v4: rework patches accodring to Peter Maydells comments: > - split patches on gpio-pwr driver and arm-virt integration. > - start secure gpio only from virt-6.0. > - rework qemu interface for gpio-pwr to use 2 named gpio. > - put secure gpio to secure name space. > v3: added missed include qemu/log.h for qemu_log(.. > v2: replace printf with qemu_log (Philippe Mathieu-Daudé) > > This patch works together with ATF patch: > https://github.com/muvarov/arm-trusted-firmware/commit/7556d07e87f755c602cd9d90359341bdd14d9d57 > > Previus discussion for reboot issue was here: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html > > Maxim Uvarov (3): > hw: gpio: implement gpio-pwr driver for qemu reset/poweroff > arm-virt: add secure pl061 for reset/power down > arm-virt: combine code for secure and non secure pl061 > > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 118 +++++++++++++++++++++++++++++++++++------- > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > include/hw/arm/virt.h | 2 + > 6 files changed, 175 insertions(+), 20 deletions(-) > create mode 100644 hw/gpio/gpio_pwr.c > > -- > 2.17.1 > From MAILER-DAEMON Thu Jan 14 11:50:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l05pb-00053T-R4 for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 11:50:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l05pL-0004u8-89; Thu, 14 Jan 2021 11:50:28 -0500 Resent-Date: Thu, 14 Jan 2021 11:50:27 -0500 Resent-Message-Id: Received: from sender4-of-o52.zoho.com ([136.143.188.52]:21279) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l05pD-0001tl-OA; Thu, 14 Jan 2021 11:50:26 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1610642973; cv=none; d=zohomail.com; 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[PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <161064076471.14770.17331806238218537829@73fb1a5943b8> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Resent-From: From: no-reply@patchew.org To: bmeng.cn@gmail.com Cc: alistair.francis@wdc.com, f4bug@amsat.org, peter.maydell@linaro.org, frasse.iglesias@gmail.com, kwolf@redhat.com, qemu-devel@nongnu.org, qemu-block@nongnu.org, marcin.krzeminski@nokia.com, andrew@aj.id.au, bin.meng@windriver.com, hskinnemoen@google.com, mreitz@redhat.com, kfting@nuvoton.com, qemu-arm@nongnu.org, clg@kaod.org, komlodi@xilinx.com, joel@jms.id.au Date: Thu, 14 Jan 2021 08:12:47 -0800 (PST) X-ZohoMailClient: External Received-SPF: pass client-ip=136.143.188.52; envelope-from=no-reply@patchew.org; helo=sender4-of-o52.zoho.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, 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h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qi9+F5K/4kbWAdzeSzPjCTkIDLkSfOKn9XAu1INEErU=; b=CBJCglbOg1ZzkN2oOd+oargykW76CmiV8V6EAOF3Ms/9Tahdt/G+YB04yQLW9s//Af VBIZlVWM+Uu7yc88FqX+tx/LhQxvcnwjRh3rkvCqISbuyOG64ECsFnu5hE6XiXiTHdFd Z0Qb5u9X52qFk59maTVjD1fSrG174ScIZMzCrsL9mnE5mVhEt4Y20+mdJqPTFfy//TjY xDnCrSiVomi/LcGsRwN5Xhi77JfUzuG+jhPDeiFu3z6RQL7RdptscshG041roSCCZZRf jh6ZBFrx1ifojRrC/8ULbgJsocW4RHL4kq1PPIYvLHoh4g82BjycG5AWg4kisqu7QIx0 gNKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qi9+F5K/4kbWAdzeSzPjCTkIDLkSfOKn9XAu1INEErU=; b=nOPXVqIAwD5vWM6sJHpFv9oOMftiiwB2WpxU4KoB3t9tgi/E2o3+fQdDUBt7k3/3yc XYOySrHtr+BYHJqxNYd4Fhy5DtmOlPjdD4eKnI1SwcS62seMxYAt6RBRIE5E3Eq45GK9 uB5kWkH7BkfF1hWxx3/CvnjKWoyOp5kbubHvrzfBNInFmZNlb1FpTMtWZX1b+z+xxQKf wFkp1NgM7nQ3IdguMSnOaAR18aXBAn+1QvnTXRuOWknYnoDbmjSyPGLfY52UUCsGurJ1 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client-ip=2a00:1450:4864:20::435; envelope-from=hskinnemoen@google.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 17:12:38 -0000 On Thu, Jan 14, 2021 at 7:10 AM Bin Meng wrote: > > From: Bin Meng > > I believe send_dummy_bits() should also be fixed, but I really don't > know how based on my pure read/guess of the codes since there is no > public datasheet available for this NPCM7xx SoC. > > Signed-off-by: Bin Meng Just a quick comment before I look at the rest of the patch series: The emulated dummy bits behavior has a lot more to do with what the m25p80 emulator seemed to expect than the actual NPCM7xx behavior. If the m25p behavior now interprets the dummy cycles the same way as the rest of the cycles, this change seems correct, but you're right that send_dummy_bits probably needs some attention as well. I _think_ it's just a matter of turning this: for (j = 0; j < 8; j += bits_per_clock) { ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock)); } into this: ssi_transfer(spi, extract32(uma_cmd, field, BITS_PER_BYTE)); which might have the very nice side effect of speeding up SPI flash access quite a bit. Thanks a lot for looking into this. > > --- > > hw/ssi/npcm7xx_fiu.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c > index 5040132b07..e76fb5ad9f 100644 > --- a/hw/ssi/npcm7xx_fiu.c > +++ b/hw/ssi/npcm7xx_fiu.c > @@ -150,7 +150,7 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, > NPCM7xxFIUState *fiu = f->fiu; > uint64_t value = 0; > uint32_t drd_cfg; > - int dummy_cycles; > + int dummy_bytes; > int i; > > if (fiu->active_cs != -1) { > @@ -180,10 +180,8 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, > break; > } > > - /* Flash chip model expects one transfer per dummy bit, not byte */ > - dummy_cycles = > - (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg); > - for (i = 0; i < dummy_cycles; i++) { > + dummy_bytes = FIU_DRD_CFG_DBW(drd_cfg) >> FIU_DRD_CFG_ACCTYPE(drd_cfg); > + for (i = 0; i < dummy_bytes; i++) { > ssi_transfer(fiu->spi, 0); > } > > -- > 2.25.1 > From MAILER-DAEMON Thu Jan 14 13:13:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l077P-0008Kw-3J for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 13:13:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l077N-0008GY-34; Thu, 14 Jan 2021 13:13:09 -0500 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]:33494) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l077K-0007lE-Gf; Thu, 14 Jan 2021 13:13:08 -0500 Received: by mail-lj1-x232.google.com with SMTP id u21so7553076lja.0; Thu, 14 Jan 2021 10:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=yGs2ETkcarv3wjydbJzBfNoeJ9RIOo/NS00PvXo94ZI=; b=aBevwnU1IR9YWcz08fAgDO5lbltWsSEsCKEPCxKc/l694QfPfk+RWkd0vSG/zInL3j ct/GShsgo37AfkCrkFOfv7+GfHh0eDurSZ1Avte7wAyrx4LmknyHJ1QoarISdK4MhFAI hrNyYky0A9kqtcE8ppnY6XcwtP95Uubm5nRJna0xkwGLHH7ZyxTirULqC3fbr4xC41s4 CXdFPFK9fEallZX/g2b31NhD6+A1xbh1wPhLAwxi7QKB+j26N99hAIpdkAY6HymcXgID m5ETNrzsvJpFfWoeQknDHN62pjl84NYQd8jbnv9MjTFy8tc3EyN4u0gknMll7RBa6VvU VCTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=yGs2ETkcarv3wjydbJzBfNoeJ9RIOo/NS00PvXo94ZI=; b=SGj/ekOwkn8RYIXiqZsGXHfhZaJxPc9O7BJRVAbWdxbr+h70CiCQjdGt6msoiyy+Hn bqM0RN76eQrE6krhrq5Agpg7hHHk6kgwpWqiIXWsgxbbuIvics7e693oI/ea/DmgRs5Q GXe29rr6DMT7wRlIVwIp2FIc+yBd149arqMIa4l4b7pFtAuBVHUt4Vuqp015Wgkf7kvH HjfRv6MUmN1l96/7Xf7TeWVhECYEkQ9CRg5WQ61FE2F32SyTkBZBUB2M1xtkRaUen8ub I0L5a8yVy4BHOjU6x7sgS07ViGa6PK1grhLFUlSykmMxBS22EA9DYbTv4va1MiWBf/93 ztDw== X-Gm-Message-State: AOAM530MSZv23kGdspLq/hZjGQAZbeSp0uKlzDEo2cP5eSZ4YpULtFeV cAl5cslFjcXQWNz+vjCyeGs= X-Google-Smtp-Source: ABdhPJw3uPB+af3jSYF2Ag66OcE32sgWcF1gFJ5Yr+7GgvxucoHZ2xp52EiCN4sunES+koUR1pBMmg== X-Received: by 2002:a2e:8113:: with SMTP id d19mr3409578ljg.303.1610647983211; Thu, 14 Jan 2021 10:13:03 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id m83sm617881lfa.113.2021.01.14.10.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 10:13:02 -0800 (PST) Date: Thu, 14 Jan 2021 19:13:00 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Marcin Krzeminski , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm@nongnu.org, qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210114181300.GA29923@fralle-msi> References: <20210114150902.11515-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210114150902.11515-1-bmeng.cn@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=frasse.iglesias@gmail.com; helo=mail-lj1-x232.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jan 2021 18:13:09 -0000 Hi Bin, On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > From: Bin Meng > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > bytes are expected to be received after it receives a command. For > example, depending on the address mode, either 3-byte address or > 4-byte address is needed. > > For fast read family commands, some dummy cycles are required after > sending the address bytes, and the dummy cycles need to be counted > in s->needed_bytes. This is where the mess began. > > As the variable name (needed_bytes) indicates, the unit is in byte. > It is not in bit, or cycle. However for some reason the model has > been using the number of dummy cycles for s->needed_bytes. The right > approach is to convert the number of dummy cycles to bytes based on > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). While not being the original implementor I must assume that above solution was considered but not chosen by the developers due to it is inaccuracy (it wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, meaning that if the controller is wrongly programmed to generate 7 the error wouldn't be caught and the controller will still be considered "correct"). Now that we have this detail in the implementation I'm in favor of keeping it, this also because the detail is already in use for catching exactly above error. > > Things get complicated when interacting with different SPI or QSPI > flash controllers. There are major two cases: > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > For such case, driver will calculate the correct number of dummy > bytes and write them into the tx fifo. Fixing the m25p80 model will > fix flashes working with such controllers. Above can be fixed while still keeping the detailed dummy cycle implementation inside m25p80. Perhaps one of the following could be looked into: configurating the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting some functionality handling this in the SPI controller. Or a mixture of above. > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > the dummy cycle configuration via some registers, and hardware will > automatically generate dummy cycles for us. Fixing the m25p80 model > is not enough, and we will need to fix the SPI/QSPI models for such > controllers. > > This series fixes the mess in the m25p80 from the flash side first, Considering the problems solved by the solution in tree I find m25p80 pretty clean, at least I don't see any clearly better way for accurately modeling the dummy clock cycles. Counting bits instead of bytes would for example still force the controllers to mark which bits to count (when transmitting one dummy byte from a txfifo on four lines (Quad command) it generates 2 dummy clock cycles since it takes two cycles to transfer 8 bits). Best regards, Francisco Iglesias > followed by fixes to 3 known SPI controller models that fall into > the 2nd case above. > > Please note, I have no way to verify patch 7/8/9 because: > > * There is no public datasheet available for the SoC / SPI controller > * There is no QEMU docs, or details that tell people how to boot either > U-Boot or Linux kernel to verify the functionality > > These 3 patches are very likely to be wrong. Hence I would like to ask > help from the original author who wrote these SPI controller models > to help testing, or completely rewrite these 3 patches to fix things. > Thanks! > > Patch 6 is unvalidated with QEMU, mainly because there is no doc to > tell people how to boot anything to test. But I have some confidence > based on my read of the ZynqMP manual, as well as some experimental > testing on a real ZCU102 board. > > Other flash patches can be tested with the SiFive SPI series: > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=222391 > > Cherry-pick patch 16 and 17 from the series above, and switch to > different flash model to test with the following command: > > $ qemu-system-riscv64 -nographic -M sifive_u -m 2G -smp 5 -kernel u-boot > > I've picked up two for testing: > > QEMU flash: "sst25vf032b" > > U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) > > CPU: rv64imafdcsu > Model: SiFive HiFive Unleashed A00 > DRAM: 2 GiB > MMC: > Loading Environment from SPIFlash... SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, total 4 MiB > *** Warning - bad CRC, using default environment > > In: serial@10010000 > Out: serial@10010000 > Err: serial@10010000 > Net: failed to get gemgxl_reset reset > > Warning: ethernet@10090000 MAC addresses don't match: > Address in DT is 52:54:00:12:34:56 > Address in environment is 70:b3:d5:92:f0:01 > eth0: ethernet@10090000 > Hit any key to stop autoboot: 0 > => sf probe > SF: Detected sst25vf032b with page size 256 Bytes, erase size 4 KiB, > total 4 MiB > => sf test 1ff000 1000 > SPI flash test: > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 10 ticks, 400 KiB/s 3.200 Mbps > 2 write: 170 ticks, 23 KiB/s 0.184 Mbps > 3 read: 9 ticks, 444 KiB/s 3.552 Mbps > Test passed > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 10 ticks, 400 KiB/s 3.200 Mbps > 2 write: 170 ticks, 23 KiB/s 0.184 Mbps > 3 read: 9 ticks, 444 KiB/s 3.552 Mbps > > QEMU flash: "mx66u51235f" > > U-Boot 2020.10 (Jan 14 2021 - 21:55:59 +0800) > > CPU: rv64imafdcsu > Model: SiFive HiFive Unleashed A00 > DRAM: 2 GiB > MMC: > Loading Environment from SPIFlash... SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB > *** Warning - bad CRC, using default environment > > In: serial@10010000 > Out: serial@10010000 > Err: serial@10010000 > Net: failed to get gemgxl_reset reset > > Warning: ethernet@10090000 MAC addresses don't match: > Address in DT is 52:54:00:12:34:56 > Address in environment is 70:b3:d5:92:f0:01 > eth0: ethernet@10090000 > Hit any key to stop autoboot: 0 > => sf probe > SF: Detected mx66u51235f with page size 256 Bytes, erase size 4 KiB, total 64 MiB > => sf test 0 8000 > SPI flash test: > 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps > 1 check: 80 ticks, 400 KiB/s 3.200 Mbps > 2 write: 83 ticks, 385 KiB/s 3.080 Mbps > 3 read: 79 ticks, 405 KiB/s 3.240 Mbps > Test passed > 0 erase: 1 ticks, 32000 KiB/s 256.000 Mbps > 1 check: 80 ticks, 400 KiB/s 3.200 Mbps > 2 write: 83 ticks, 385 KiB/s 3.080 Mbps > 3 read: 79 ticks, 405 KiB/s 3.240 Mbps > > I am sure there will be bugs, and I have not tested all flashes affected. > But I want to send out this series for an early discussion and comments. > I will continue my testing. > > > Bin Meng (9): > hw/block: m25p80: Fix the number of dummy bytes needed for Windbond > flashes > hw/block: m25p80: Fix the number of dummy bytes needed for > Numonyx/Micron flashes > hw/block: m25p80: Fix the number of dummy bytes needed for Macronix > flashes > hw/block: m25p80: Fix the number of dummy bytes needed for Spansion > flashes > hw/block: m25p80: Support fast read for SST flashes > hw/ssi: xilinx_spips: Fix generic fifo dummy cycle handling > Revert "aspeed/smc: Fix number of dummy cycles for FAST_READ_4 > command" > Revert "aspeed/smc: snoop SPI transfers to fake dummy cycles" > hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic > > include/hw/ssi/aspeed_smc.h | 3 - > hw/block/m25p80.c | 153 ++++++++++++++++++++++++++++-------- > hw/ssi/aspeed_smc.c | 116 +-------------------------- > hw/ssi/npcm7xx_fiu.c | 8 +- > hw/ssi/xilinx_spips.c | 29 ++++++- > 5 files changed, 153 insertions(+), 156 deletions(-) > > -- > 2.25.1 > From MAILER-DAEMON Thu Jan 14 21:08:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0EX5-0007V3-Rw for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 21:08:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0EX4-0007Sv-L8; Thu, 14 Jan 2021 21:08:10 -0500 Received: from mail-yb1-xb2e.google.com ([2607:f8b0:4864:20::b2e]:44910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0EX0-0006ur-9w; Thu, 14 Jan 2021 21:08:10 -0500 Received: by mail-yb1-xb2e.google.com with SMTP id g4so3653173ybo.11; Thu, 14 Jan 2021 18:08:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6ytTcU+ACdDlta92LVwOejJs4RVgArWGyGwqbmbKEt8=; b=MN4KN0+vId7zqjcI+qAjtxlnAeI10lmNJ2uYba2MvXE0lrin6tPo44ETrRAeiVUlzH +3BiPFeWYH8/NEhwr7gQAnCIuzRtbSFtLU8Q0/nIZ2ryjGEbIQVpiEHwMDYkzZ+1mhB8 pHQjF2OW9M5SJ8Cm3F6H0/nCrkNZI6bZlIw01a+uYN1gunGPuiuWHtSnH1q/6lbpuvVq rrK/tsCoxhNyzBwFVngHaTAaLRy24rIeeuozDVgimab7HJpS1uw3BGbDd3M21UouhYAf VyTg0Y9ZjF9bNc2Ac2WU7EA5Pi0ak4YtKZYLZA/nfL1wanGKkjB8CjJjETzqxQttJQjH 5gCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6ytTcU+ACdDlta92LVwOejJs4RVgArWGyGwqbmbKEt8=; b=BH+mtRiMp/LkpDCwnFrjxbBusuMJ27onmiq0v8zmu8LLCLX8FCMcGBpATcbs6U6Jkh lgz/FjIDjYl4fqq3TWF3YDkeUDdHXI2ZuzB8ZIiT8JKsjzc9S9u0W9kx0GVgnSPJqduz 6n6XoytBNzk9Fjk664Wk7FhvKKowC8tiYVGfHdC4lcp09kNKb1qVt5E1Cfot91AFwMn+ m9Tc/zrGzxR3Hd7Y9/cKhVIAvVly6bQPOcHc0YqPcefTOwoaEi3c4XY7VIMsY/1/8/Xj pJvDhgt5QqA8KdnAy7UdAwqaoRZDd4eTgYxmmDJ/9kQv5dvMcdsA8VTIHDDQD81ZK53p d85A== X-Gm-Message-State: AOAM530njL7KYom24wcpGSHdqKe/aQGzmXWLn6EPnuIKIMVwTRhC6ow0 u6wFhrzIzevSCc6cMvkCvIxgHjUdKMCmR63BZgU= X-Google-Smtp-Source: ABdhPJzKwerT6pjKGERBWAb7oQljL6eYTxoudycR0zltGOOQbqvc5exQQ3LmosFuAsDK55MAuPr/nF3K/qI1bWBIfwQ= X-Received: by 2002:a25:2041:: with SMTP id g62mr15432022ybg.152.1610676484692; Thu, 14 Jan 2021 18:08:04 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> In-Reply-To: <20210114181300.GA29923@fralle-msi> From: Bin Meng Date: Fri, 15 Jan 2021 10:07:52 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Francisco Iglesias Cc: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 02:08:10 -0000 Hi Francisco, On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias wrote: > > Hi Bin, > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > From: Bin Meng > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > bytes are expected to be received after it receives a command. For > > example, depending on the address mode, either 3-byte address or > > 4-byte address is needed. > > > > For fast read family commands, some dummy cycles are required after > > sending the address bytes, and the dummy cycles need to be counted > > in s->needed_bytes. This is where the mess began. > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > It is not in bit, or cycle. However for some reason the model has > > been using the number of dummy cycles for s->needed_bytes. The right > > approach is to convert the number of dummy cycles to bytes based on > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > While not being the original implementor I must assume that above solution was > considered but not chosen by the developers due to it is inaccuracy (it > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > meaning that if the controller is wrongly programmed to generate 7 the error > wouldn't be caught and the controller will still be considered "correct"). Now > that we have this detail in the implementation I'm in favor of keeping it, this > also because the detail is already in use for catching exactly above error. > I found no clue from the commit message that my proposed solution here was ever considered, otherwise all SPI controller models supporting software generation should have been found out seriously broken long time ago! The issue you pointed out that we require the total number of dummy bits should be multiple of 8 is true, that's why I added the unimplemented log message in this series (patch 2/3/4) to warn users if this expectation is not met. However this will not cause any issue when running U-Boot or Linux, because both spi-nor drivers expect the same assumption as we do here. See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), there is a logic to calculate the dummy bytes needed for fast read command: /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; Note the default dummy cycles configuration for all flashes I have looked into as of today, meets the multiple of 8 assumption. On some flashes the dummy cycle number is configurable, and if it's been configured to be an odd value, it would not work on U-Boot/Linux in the first place. > > > > Things get complicated when interacting with different SPI or QSPI > > flash controllers. There are major two cases: > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > For such case, driver will calculate the correct number of dummy > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > fix flashes working with such controllers. > > Above can be fixed while still keeping the detailed dummy cycle implementation > inside m25p80. Perhaps one of the following could be looked into: configurating > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > some functionality handling this in the SPI controller. Or a mixture of above. Please send patches to explain this in detail how this is going to work. I am open to all possible solutions. > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > the dummy cycle configuration via some registers, and hardware will > > automatically generate dummy cycles for us. Fixing the m25p80 model > > is not enough, and we will need to fix the SPI/QSPI models for such > > controllers. > > > > This series fixes the mess in the m25p80 from the flash side first, > > Considering the problems solved by the solution in tree I find m25p80 pretty > clean, at least I don't see any clearly better way for accurately modeling the > dummy clock cycles. Counting bits instead of bytes would for example still > force the controllers to mark which bits to count (when transmitting one dummy > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > cycles since it takes two cycles to transfer 8 bits). > SPI is a bit based protocol, not bytes. If you insist on bit modeling with the dummy cycles then you should also suggest we change all cycles (including command/addr/dummy/data phases) to be modeled with bits. That way we can accurately emulate everything, for example one potential problem like transferring 9 bit in the data phase. However modeling everything with bit is super inefficient. My view is that we should avoid trying to support uncommon use cases (like not multiple of 8 for dummy bits) in QEMU. Regards, Bin From MAILER-DAEMON Thu Jan 14 22:29:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Fo3-0000qZ-LP for mharc-qemu-arm@gnu.org; Thu, 14 Jan 2021 22:29:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Fo2-0000oR-0p for qemu-arm@nongnu.org; Thu, 14 Jan 2021 22:29:46 -0500 Received: from mail-io1-xd32.google.com ([2607:f8b0:4864:20::d32]:40096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Fnz-0001Rr-Gf for qemu-arm@nongnu.org; Thu, 14 Jan 2021 22:29:45 -0500 Received: by mail-io1-xd32.google.com with SMTP id r9so15612494ioo.7 for ; Thu, 14 Jan 2021 19:29:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vTg5XIEa4QeiPR4ZfaI1WcYrbmhHRCA65ExSp5eNi1A=; b=mNdWhQxA8r1w/CSi9l7vq33r+VF5E2aGBTJ8WOtcPna/tYroPPP2b9ZVfqFirsh01u fwikxMSW7oyDoPPA5hS/x8I4umLd7VZtogGt2nl/htwU5n6iHuOLg4hqCfKVjKbKBCvX GpprpZ6UcoNUue3Mb9koXKCnmQTFdz7Ta/R3/oWk2U195auPUqCGmwBfmbZHo01o7yfi AbbuZT3jIODcJWpy7baHpgbXPgIF5cHNxwJmZtmTsP16H3l4Q+uRkiWWUXW9ruS0MgkP xTjcL9jgDsvwRFgcfmAZv+drIZoVJNK/zMmsLKpLM0aIxvw11AWbpNglNNQXnbkECx5Q FtcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vTg5XIEa4QeiPR4ZfaI1WcYrbmhHRCA65ExSp5eNi1A=; b=gLNzRp0yZm9cxFkDNiCE6XheGBgFUynuJlP+3Kq7KhDda5PwoAUiJEtdxE5KhP3VKa u9ieupaVmSkYHUAurZ8jiPzflV0kilMxX5+ikIYHNZpke7UXEI+b7/3Mlcp9qZeDO8Fu 8pMhpOuV2MiQJGYWBfZIXf981X9WaNCjDV8Rp8uRFdESURWnvt7iXv1KZFVls/nWmLit UA6OvIhNBL5JeEb9x5KbPHRNMaFlcSiwB331TGg5UrUspZgQSf7ReKni6y/HKhU1+Uge seg9XYHSa4mtA9EuosOcZefnVB67jgCMw71IuB9yKsEKQ2b+i/bqR6OU0Bv60p8t5uEc dwTg== X-Gm-Message-State: AOAM531BknrF4h4KJSdP8qxkwQKssEdOoovxGd3tkAwNDvrjUbSk6tJL 5ShamxrNq53OPVhxa3ZArXMWCEjgxuDzqv/Xd+DGKw== X-Google-Smtp-Source: ABdhPJxgBGDbQAM3tNlExTfhJCcoatt89ck+2NLTWubsn7kHtcc+bDHdK0zWZBt6f9ybxeGQG7baEM1ZVaWIwfqdiyc= X-Received: by 2002:a92:9a42:: with SMTP id t63mr9290569ili.176.1610681382114; Thu, 14 Jan 2021 19:29:42 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> In-Reply-To: From: Havard Skinnemoen Date: Thu, 14 Jan 2021 19:29:27 -0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Bin Meng Cc: Francisco Iglesias , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=hskinnemoen@google.com; helo=mail-io1-xd32.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 03:29:46 -0000 Hi Bin, On Thu, Jan 14, 2021 at 6:08 PM Bin Meng wrote: > > Hi Francisco, > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > wrote: > > > > Hi Bin, > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > From: Bin Meng > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > bytes are expected to be received after it receives a command. For > > > example, depending on the address mode, either 3-byte address or > > > 4-byte address is needed. > > > > > > For fast read family commands, some dummy cycles are required after > > > sending the address bytes, and the dummy cycles need to be counted > > > in s->needed_bytes. This is where the mess began. > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > It is not in bit, or cycle. However for some reason the model has > > > been using the number of dummy cycles for s->needed_bytes. The right > > > approach is to convert the number of dummy cycles to bytes based on > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > While not being the original implementor I must assume that above solution was > > considered but not chosen by the developers due to it is inaccuracy (it > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > meaning that if the controller is wrongly programmed to generate 7 the error > > wouldn't be caught and the controller will still be considered "correct"). Now > > that we have this detail in the implementation I'm in favor of keeping it, this > > also because the detail is already in use for catching exactly above error. > > > > I found no clue from the commit message that my proposed solution here > was ever considered, otherwise all SPI controller models supporting > software generation should have been found out seriously broken long > time ago! > > The issue you pointed out that we require the total number of dummy > bits should be multiple of 8 is true, that's why I added the > unimplemented log message in this series (patch 2/3/4) to warn users > if this expectation is not met. However this will not cause any issue > when running U-Boot or Linux, because both spi-nor drivers expect the > same assumption as we do here. > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > there is a logic to calculate the dummy bytes needed for fast read > command: > > /* convert the dummy cycles to the number of bytes */ > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > Note the default dummy cycles configuration for all flashes I have > looked into as of today, meets the multiple of 8 assumption. On some > flashes the dummy cycle number is configurable, and if it's been > configured to be an odd value, it would not work on U-Boot/Linux in > the first place. > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > flash controllers. There are major two cases: > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > For such case, driver will calculate the correct number of dummy > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > fix flashes working with such controllers. > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > inside m25p80. Perhaps one of the following could be looked into: configurating > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > some functionality handling this in the SPI controller. Or a mixture of above. > > Please send patches to explain this in detail how this is going to > work. I am open to all possible solutions. > > > > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > > the dummy cycle configuration via some registers, and hardware will > > > automatically generate dummy cycles for us. Fixing the m25p80 model > > > is not enough, and we will need to fix the SPI/QSPI models for such > > > controllers. > > > > > > This series fixes the mess in the m25p80 from the flash side first, > > > > Considering the problems solved by the solution in tree I find m25p80 pretty > > clean, at least I don't see any clearly better way for accurately modeling the > > dummy clock cycles. Counting bits instead of bytes would for example still > > force the controllers to mark which bits to count (when transmitting one dummy > > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > > cycles since it takes two cycles to transfer 8 bits). > > > > SPI is a bit based protocol, not bytes. If you insist on bit modeling > with the dummy cycles then you should also suggest we change all > cycles (including command/addr/dummy/data phases) to be modeled with > bits. That way we can accurately emulate everything, for example one > potential problem like transferring 9 bit in the data phase. I agree with this. There's really nothing special about dummy cycles. Making them special makes it super painful to implement SPI controller emulation because you have to anticipate when ssi_transfer changes semantics from byte-at-a-time to bit-at-a-time. I doubt all the SPI controllers in the tree gets it right all the time. > However modeling everything with bit is super inefficient. My view is > that we should avoid trying to support uncommon use cases (like not > multiple of 8 for dummy bits) in QEMU. Perhaps ssi_transfer could take an additional bits parameter? That should make it possible to transfer any number of bits up to 32, while keeping the common case simple on both sides. And it would work for any SPI transfer, not just dummy cycles. Havard From MAILER-DAEMON Fri Jan 15 05:11:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0M4t-00044H-GE for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 05:11:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0M4r-00043o-UU for qemu-arm@nongnu.org; Fri, 15 Jan 2021 05:11:33 -0500 Received: from mail-lj1-x22b.google.com ([2a00:1450:4864:20::22b]:35646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0M4q-0001xs-6o for qemu-arm@nongnu.org; Fri, 15 Jan 2021 05:11:33 -0500 Received: by mail-lj1-x22b.google.com with SMTP id p13so9811185ljg.2 for ; Fri, 15 Jan 2021 02:11:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dI3m5apsFpRzkZoJU0PtHodMAshsYUKsXH+0XXCFfFM=; b=MHyD8mGnSVVB1d36yaC+ardXR4WaRHkCgqUNiOafXFgC1UMzHzoMkQ+OOaTNkw43v1 TljI25K/B/u9lfjL7iV04wpADD6sWCk3SORQ0c5uLxk26jf+4SX51m5jqdZNegtcw9gX UZhlQ/1itisx7/+05hAiI2w0EJkvRivfkL+fcJD63DrKEeIO/2RLyv451erS1niumvRb QY9N4B1pMtYRk1KLB885Qzbo2q7jn9sKo/7zXzyf1pAocszo5pqDPstz14qs4FfvtBYI 57d5CuGSyqRt2WidoSqoU5jcq1asaT+42PORfVi+zzTLvHOq/G4Fjd4/2RzIaEs11UTb gk6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dI3m5apsFpRzkZoJU0PtHodMAshsYUKsXH+0XXCFfFM=; b=dgg7hwmRetCSFSsIn18w9aIM635FdoxS0PP4L79VpaPHpENlPIup8eLNmMT873oO4h 3FDnH89l3Y3WMvNlmWyVImS3nxDu8NNDkhsvlGMNaEwP2dG2qMLxpCxSTtN0nbXiPa+b 0qMp6ivdN6Aw69eSHO0bnTSOyQSdl4141I5ONJ/kLLyZH2OfIhxDicI//qIM3Lh5cOW/ sQu8eqKAWaEJaau+fCiU92Fcf48JgcZAOP9zHCjYi8twtp/DRCnjDl6nwG3tWIvvKGPx qrFyUUEpazDsK1LJRqfOdRjjuob5DwAjhh//PI2OPZX1yJTwdRwGqiGK5WY7kLf/UtG9 QHJw== X-Gm-Message-State: AOAM532ShtJsY4LzKtD+YLiHtEnj7P2qM1WwddAavOUDBV1hVeM0jgaJ y1AXvbsL+Ac2kPbH/AR72jkvHQ10iJS2tg== X-Google-Smtp-Source: ABdhPJyVXYNtdF6AgCPMMyKLMwqYEVcQGgwfvlM7P94Eg65N3P5KWqrX+X5NzOvgt63fcrlrFF/s2Q== X-Received: by 2002:a2e:95d5:: with SMTP id y21mr5262677ljh.477.1610705489942; Fri, 15 Jan 2021 02:11:29 -0800 (PST) Received: from localhost.localdomain ([91.193.178.207]) by smtp.gmail.com with ESMTPSA id a15sm731886lji.105.2021.01.15.02.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 02:11:29 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv7 0/3] arm-virt: add secure pl061 for reset/power down Date: Fri, 15 Jan 2021 13:11:23 +0300 Message-Id: <20210115101126.4259-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 10:11:34 -0000 v7: - same as v6, but resplit patches: patch 2 no function changes and refactor gpio setup for virt platfrom and patch 3 adds secure gpio. v6: - 64k align gpio memory region (Andrew Jones) - adjusted memory region to map this address in the corresponding atf patch v5: - removed vms flag, added fdt (Andrew Jones) - added patch3 to combine secure and non secure pl061. It has to be more easy to review if this changes are in the separate patch. v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/7556d07e87f755c602cd9d90359341bdd14d9d57 Previus discussion for reboot issue was here: https://www.mail-archive.com/qemu-devel@nongnu.org/msg757705.html Maxim Uvarov (3): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: refactor gpios creation arm-virt: add secure pl061 for reset/power down hw/arm/Kconfig | 1 + hw/arm/virt.c | 117 ++++++++++++++++++++++++++++++++++-------- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 2 + 6 files changed, 174 insertions(+), 20 deletions(-) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Fri Jan 15 05:11:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0M4v-00047R-Sw for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 05:11:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0M4u-00046E-Tb for qemu-arm@nongnu.org; Fri, 15 Jan 2021 05:11:36 -0500 Received: from mail-lj1-x22c.google.com ([2a00:1450:4864:20::22c]:37526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0M4r-0001yf-Lm for qemu-arm@nongnu.org; Fri, 15 Jan 2021 05:11:36 -0500 Received: by mail-lj1-x22c.google.com with SMTP id w26so9782870ljo.4 for ; Fri, 15 Jan 2021 02:11:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=62h8W8c/MHOTaJfr80jgkPG/YCUcGgeW9/I/zkhkDxM=; b=GyH5cAgj8gBMOB9g6vIMa6uul6ha6L4Hbw0pM98N6O6QoRwupKRoSEWMK3VhHkcSU+ GFcID6kPoUleGXhzGnEiVX42tI5PRV2bBqUFenMiAjPyYwJlDbooDaLyjpThj/Sz6sVv +eB1y7EUlSTZhe7+7DNcNl9EilDhQyZ3SK0DHhfgegaPFQViVjNdUBvpj/LR+Hkk4jN6 8/OA8ZAsdQYYEe1uqeqQj7TJrbLIC+ocejMh5G8zYo7lL3vps5epBzAeFokqYeswfrmQ IiW5L5wHBYuJH4OKlVWY1C4Zkgyl9qDIsOR4uuZoRVAjsg8x+SN4nE6uNEyCC6TpyVwv d9Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=62h8W8c/MHOTaJfr80jgkPG/YCUcGgeW9/I/zkhkDxM=; b=oLxzErGTG/RJazlvv3GMNd1uLV6QZTd4eZuvXyUPu2V7X5eqCrLCiIksmlwmh41sf6 zbLV2Zy8DvX+2d0rSbEirpsjoa/PZ+kxpZlRE3h3OV0c68BREg3zRCZFyoiBRbpW89ko SssiGyyR8egO9qloD8xvYk52ilc3zAQcfpnXC6JkNUx3QT+chBNkOoAnRJubTLM/tG2Y Pepjc+xvtoQzN7xLz5/QX4idtTrBxxAfWoskv5/gBf8h/GNGXEyt5LeOkRKpj7xH0goF PVDc/qQ8pPB+EOwEoV1oMl5s1u5eWqF1s7IfEgx81s8p7+/QVWLUbJC9Y33OYkVR8Qxi uBYQ== X-Gm-Message-State: AOAM532F31UZzL+tiNrR3b+2PwkXm5JFkz6ADCiAIZY6rXcTkLjCGnA2 rK68cE3CZeIXtKgAwRVZuEaPNTMuboxqMA== X-Google-Smtp-Source: ABdhPJxTOoSDvPspimR2HWD86UNGYuebaMsHI0egy88hhupHFW67lrCf2R34Zp7LZIqplv37DU88Og== X-Received: by 2002:a05:651c:383:: with SMTP id e3mr4970599ljp.422.1610705491760; Fri, 15 Jan 2021 02:11:31 -0800 (PST) Received: from localhost.localdomain ([91.193.178.207]) by smtp.gmail.com with ESMTPSA id a15sm731886lji.105.2021.01.15.02.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 02:11:31 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv7 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Fri, 15 Jan 2021 13:11:24 +0300 Message-Id: <20210115101126.4259-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115101126.4259-1-maxim.uvarov@linaro.org> References: <20210115101126.4259-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 10:11:37 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov Reviewed-by: Hao Wu --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..8ed8d5d24f --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (!level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Fri Jan 15 05:11:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0M4y-0004D9-Az for mharc-qemu-arm@gnu.org; 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Fri, 15 Jan 2021 02:11:33 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv7 2/3] arm-virt: refactor gpios creation Date: Fri, 15 Jan 2021 13:11:25 +0300 Message-Id: <20210115101126.4259-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115101126.4259-1-maxim.uvarov@linaro.org> References: <20210115101126.4259-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 10:11:37 -0000 No functional change. Just refactor code to better support secure and normal world gpios. Signed-off-by: Maxim Uvarov --- hw/arm/virt.c | 67 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 47 insertions(+), 20 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..26bb66e8e1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -820,17 +820,43 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms) +static void create_gpio_keys(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + gpio_key_dev = sysbus_create_simple("gpio-key", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", + "label", "GPIO Key Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", + KEY_POWER); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", + "gpios", phandle, 3, 0); +} + +static void create_gpio_devices(const VirtMachineState *vms, int gpio, + MemoryRegion *mem) { char *nodename; DeviceState *pl061_dev; - hwaddr base = vms->memmap[VIRT_GPIO].base; - hwaddr size = vms->memmap[VIRT_GPIO].size; - int irq = vms->irqmap[VIRT_GPIO]; + hwaddr base = vms->memmap[gpio].base; + hwaddr size = vms->memmap[gpio].size; + int irq = vms->irqmap[gpio]; const char compat[] = "arm,pl061\0arm,primecell"; + SysBusDevice *s; - pl061_dev = sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); nodename = g_strdup_printf("/pl061@%" PRIx64, base); @@ -847,21 +873,22 @@ static void create_gpio(const VirtMachineState *vms) qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); - gpio_key_dev = sysbus_create_simple("gpio-key", -1, - qdev_get_gpio_in(pl061_dev, 3)); - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); + if (gpio == VIRT_GPIO) { + qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); + } else { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", - "label", "GPIO Key Poweroff"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", - KEY_POWER); - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", - "gpios", phandle, 3, 0); + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", + nodename); + } g_free(nodename); + + /* Child gpio devices */ + if (gpio == VIRT_GPIO) { + create_gpio_keys(vms, pl061_dev, phandle); + } } static void create_virtio_devices(const VirtMachineState *vms) @@ -1990,7 +2017,7 @@ static void machvirt_init(MachineState *machine) if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms); + create_gpio_devices(vms, VIRT_GPIO, sysmem); } /* connect powerdown request */ -- 2.17.1 From MAILER-DAEMON Fri Jan 15 05:11:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0M4z-0004Gv-Qk for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 05:11:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0M4x-0004B4-6V for qemu-arm@nongnu.org; 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Fri, 15 Jan 2021 02:11:34 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv7 3/3] arm-virt: add secure pl061 for reset/power down Date: Fri, 15 Jan 2021 13:11:26 +0300 Message-Id: <20210115101126.4259-4-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115101126.4259-1-maxim.uvarov@linaro.org> References: <20210115101126.4259-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 10:11:39 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 53 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 26bb66e8e1..436ae894c9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -841,6 +842,46 @@ static void create_gpio_keys(const VirtMachineState *vms, "gpios", phandle, 3, 0); } +#define ATF_GPIO_POWEROFF 3 +#define ATF_GPIO_REBOOT 4 + +static void create_gpio_pwr(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + DeviceState *gpio_pwr_dev; + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", + "label", "GPIO PWR Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", + ATF_GPIO_POWEROFF); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", + "gpios", phandle, 3, 0); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", + "label", "GPIO PWR Reboot"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", + ATF_GPIO_REBOOT); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", + "gpios", phandle, 3, 0); +} + static void create_gpio_devices(const VirtMachineState *vms, int gpio, MemoryRegion *mem) { @@ -888,6 +929,8 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio, /* Child gpio devices */ if (gpio == VIRT_GPIO) { create_gpio_keys(vms, pl061_dev, phandle); + } else { + create_gpio_pwr(vms, pl061_dev, phandle); } } @@ -2020,6 +2063,10 @@ static void machvirt_init(MachineState *machine) create_gpio_devices(vms, VIRT_GPIO, sysmem); } + if (vms->secure && !vmc->no_secure_gpio) { + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2635,8 +2682,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..6f6c85ffcf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { -- 2.17.1 From MAILER-DAEMON Fri Jan 15 07:26:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0OBg-00065W-VI for mharc-qemu-arm@gnu.org; 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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id a15sm769719lji.105.2021.01.15.04.26.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 04:26:30 -0800 (PST) Date: Fri, 15 Jan 2021 13:26:28 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210115122627.GB29923@fralle-msi> References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=frasse.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 12:26:37 -0000 Hi Bin, On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > Hi Francisco, > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > wrote: > > > > Hi Bin, > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > From: Bin Meng > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > bytes are expected to be received after it receives a command. For > > > example, depending on the address mode, either 3-byte address or > > > 4-byte address is needed. > > > > > > For fast read family commands, some dummy cycles are required after > > > sending the address bytes, and the dummy cycles need to be counted > > > in s->needed_bytes. This is where the mess began. > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > It is not in bit, or cycle. However for some reason the model has > > > been using the number of dummy cycles for s->needed_bytes. The right > > > approach is to convert the number of dummy cycles to bytes based on > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > While not being the original implementor I must assume that above solution was > > considered but not chosen by the developers due to it is inaccuracy (it > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > meaning that if the controller is wrongly programmed to generate 7 the error > > wouldn't be caught and the controller will still be considered "correct"). Now > > that we have this detail in the implementation I'm in favor of keeping it, this > > also because the detail is already in use for catching exactly above error. > > > > I found no clue from the commit message that my proposed solution here > was ever considered, otherwise all SPI controller models supporting > software generation should have been found out seriously broken long > time ago! The controllers you are referring to might lack support for commands requiring dummy clock cycles but I really hope they work with the other commands? If so I don't think it is fair to call them 'seriously broken' (and else we should probably let the maintainers know about it). Most likely the lack of support for the commands is because no request has been made for them. Also there is one controller that has support. > > The issue you pointed out that we require the total number of dummy > bits should be multiple of 8 is true, that's why I added the > unimplemented log message in this series (patch 2/3/4) to warn users > if this expectation is not met. However this will not cause any issue > when running U-Boot or Linux, because both spi-nor drivers expect the > same assumption as we do here. > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > there is a logic to calculate the dummy bytes needed for fast read > command: > > /* convert the dummy cycles to the number of bytes */ > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > Note the default dummy cycles configuration for all flashes I have > looked into as of today, meets the multiple of 8 assumption. On some > flashes the dummy cycle number is configurable, and if it's been > configured to be an odd value, it would not work on U-Boot/Linux in > the first place. > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > flash controllers. There are major two cases: > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > For such case, driver will calculate the correct number of dummy > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > fix flashes working with such controllers. > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > inside m25p80. Perhaps one of the following could be looked into: configurating > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > some functionality handling this in the SPI controller. Or a mixture of above. > > Please send patches to explain this in detail how this is going to > work. I am open to all possible solutions. In that case I suggest that you instead try with a device property 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle count to dummy bytes inside m25p80. Below is an example on how to modify the decode_fast_read_cmd function (the other commands requiring dummy clock cycles can follow a similar pattern). This way the fifo mode will be able to work the way you desire while also keeping the current functionality intact. Suddenly removing functionality (features) will take users by surprise. static void decode_fast_read_cmd(Flash *s) { uint8_t dummy_clk_cycles = 0; uint8_t extra_bytes; s->needed_bytes = get_addr_length(s); /* Obtain the number of dummy clock cycles needed */ switch (get_man(s)) { case MAN_WINBOND: dummy_clk_cycles += 8; break; case MAN_NUMONYX: dummy_clk_cycles += numonyx_extract_cfg_num_dummies(s); break; case MAN_MACRONIX: if (extract32(s->volatile_cfg, 6, 2) == 1) { dummy_clk_cycles += 6; } else { dummy_clk_cycles += 8; } break; case MAN_SPANSION: dummy_clk_cycles += extract32(s->spansion_cr2v, SPANSION_DUMMY_CLK_POS, SPANSION_DUMMY_CLK_LEN ); break; default: break; } if (s->model_dummy_bytes) { int lines = 1; /* * Expect dummy bytes from the controller so convert the dummy * clock cycles to dummy_bytes. */ extra_bytes = convert_to_dummy_bytes(dummy_clk_count, lines); } else { /* Model individual dummy clock cycles as byte writes */ extra_bytes = dummy_clk_cycles; } s->needed_bytes += extra_bytes; s->pos = 0; s->len = 0; s->state = STATE_COLLECTING_DATA; } Best regards, Francisco Iglesias > > > > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > > the dummy cycle configuration via some registers, and hardware will > > > automatically generate dummy cycles for us. Fixing the m25p80 model > > > is not enough, and we will need to fix the SPI/QSPI models for such > > > controllers. > > > > > > This series fixes the mess in the m25p80 from the flash side first, > > > > Considering the problems solved by the solution in tree I find m25p80 pretty > > clean, at least I don't see any clearly better way for accurately modeling the > > dummy clock cycles. Counting bits instead of bytes would for example still > > force the controllers to mark which bits to count (when transmitting one dummy > > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > > cycles since it takes two cycles to transfer 8 bits). > > > > SPI is a bit based protocol, not bytes. If you insist on bit modeling > with the dummy cycles then you should also suggest we change all > cycles (including command/addr/dummy/data phases) to be modeled with > bits. That way we can accurately emulate everything, for example one > potential problem like transferring 9 bit in the data phase. > > However modeling everything with bit is super inefficient. My view is > that we should avoid trying to support uncommon use cases (like not > multiple of 8 for dummy bits) in QEMU. > > Regards, > Bin From MAILER-DAEMON Fri Jan 15 08:18:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0P05-0005DL-1M for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 08:18:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Ozz-00059b-Al for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:18:43 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:55969) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Ozx-0002JL-6S for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:18:43 -0500 Received: by mail-wm1-x32e.google.com with SMTP id c124so7319972wma.5 for ; Fri, 15 Jan 2021 05:18:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hLZqIajkzEU/c6xTrzrj0aRppNL63M3pKJrQ+36KQfM=; b=oBnPKmepx1QARKHePO3lKcGt++ogSRSGjIWUGy9NHzDe2kuNi4fup2+433FgrZR1NT ajEul0PcBNbfWdl6ACMVJ1wgL6L8Hwxu8dOsUW/jDcA72AXfOVYIjfvTU3Oxl62jIUag a9OB7F404h4WcI54fA78QCRCBnA25OamU1MNMnMQLsj13W62i35fm0Kwpz5aGj2jCNrC 7twJzmH0qwLlLkhngaUGzEKh8NocAU4Y3HXZtw1O1hwl56sSorZZ1rAV1l6hpp3XjtLF dHoRku+xY5lqT7xT4QfsSU/E+3yOr5XlbMo4sEQfVuaiH42KPl07I1TgCUyDiiWxzmBD nkaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hLZqIajkzEU/c6xTrzrj0aRppNL63M3pKJrQ+36KQfM=; b=jNZIIA177ZBQQK9DS0DgICLF1apLmNOdhl3g72Ha9WYCDiAit85hn5lxYOt2B35Kt0 g62QxRJh63HSv5rj9GL5pd0MmumyuHA7ax29j4D963HEtL7n167xy1ilCSswKl9zj5yH O8MDilC015VFZKzUVnUmFH3Bw3WOfleSnV0zsBrHmMcZADCsY/wLGgjz7qI1qTkUB3h2 ihzXYPhDNVIYn6zsHQSLIdehi1IttwmC6Bs2Vn+JrlVX1mlSBjri/WaQAm3pIo8GdMMu N3Omyq91cPuwGQPR/aZ2lEz10bsRceDECAEV1XIEduTnzy8Vv/UR/P1OZj7dxBGZLTj1 jbNg== X-Gm-Message-State: AOAM5320HFYQd5vOXuSQd1sL0oJQrCys2d0tU/DQOeXunsrbkH9NypUQ EZpE/LlNx0pTZBg++ZzhqNejAg== X-Google-Smtp-Source: ABdhPJxr/HWWqQ65gmiRPBanhh3bP1uEE0yUA8GQkrFuZxim32hCUDylcPYzYyfsC6PrFd3Dy4R/zA== X-Received: by 2002:a7b:c395:: with SMTP id s21mr6786112wmj.97.1610716719626; Fri, 15 Jan 2021 05:18:39 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r20sm17140997wrg.66.2021.01.15.05.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 05:18:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3EDFA1FFAA; Fri, 15 Jan 2021 13:08:33 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Luis Machado , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Date: Fri, 15 Jan 2021 13:08:19 +0000 Message-Id: <20210115130828.23968-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:18:43 -0000 While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée Reviewed-by: Luis Machado Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 866595b4f1..a8fff2a3d0 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { { "uint128", 128, 'q', 'u' }, { "int128", 128, 'q', 's' }, /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, { "uint64", 64, 'd', 'u' }, { "int64", 64, 'd', 's' }, - { "ieee_double", 64, 'd', 'f' }, /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, { "uint32", 32, 's', 'u' }, { "int32", 32, 's', 's' }, - { "ieee_single", 32, 's', 'f' }, /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, { "uint16", 16, 'h', 'u' }, { "int16", 16, 'h', 's' }, - /* - * TODO: currently there is no reliable way of telling - * if the remote gdb actually understands ieee_half so - * we don't expose it in the target description for now. - * { "ieee_half", 16, 'h', 'f' }, - */ /* bytes */ { "uint8", 8, 'b', 'u' }, { "int8", 8, 'b', 's' }, @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; g_autoptr(GString) ts = g_string_new(""); - int i, bits, reg_width = (cpu->sve_max_vq * 128); + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); info->num = 0; g_string_printf(s, ""); g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + g_string_append_printf(s, ""); /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "vq%d%c%c", count, - vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); g_string_append_printf(s, "", ts->str, vec_lanes[i].gdb_type, count); @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) * signed and potentially float versions of each size from 128 to * 8 bits. */ - for (bits = 128; bits >= 8; bits /= 2) { - int count = reg_width / bits; - g_string_append_printf(s, "", count); - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - if (vec_lanes[i].size == bits) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - count, - vec_lanes[i].sz, vec_lanes[i].suffix); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", suf[i]); + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { + if (vec_lanes[j].size == bits) { + g_string_append_printf(s, "", + vec_lanes[j].suffix, + vec_lanes[j].sz, vec_lanes[j].suffix); } } g_string_append(s, ""); } /* And now the final union of unions */ - g_string_append(s, ""); - for (bits = 128; bits >= 8; bits /= 2) { - int count = reg_width / bits; - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - if (vec_lanes[i].size == bits) { - g_string_append_printf(s, "", - vec_lanes[i].sz, count); - break; - } - } + g_string_append(s, ""); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", + suf[i], suf[i]); } g_string_append(s, ""); + /* Finally the sve prefix type */ + g_string_append_printf(s, + "", + reg_width / 8); + /* Then define each register in parts for each vq */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", + " regnum=\"%d\" type=\"svev\"/>", i, reg_width, base_reg++); info->num++; } @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) " regnum=\"%d\" group=\"float\"" " type=\"int\"/>", base_reg++); info->num += 2; - /* - * Predicate registers aren't so big they are worth splitting up - * but we do need to define a type to hold the array of quad - * references. - */ - g_string_append_printf(s, - "", - cpu->sve_max_vq); + for (i = 0; i < 16; i++) { g_string_append_printf(s, "", + " regnum=\"%d\" type=\"svep\"/>", i, cpu->sve_max_vq * 16, base_reg++); info->num++; } g_string_append_printf(s, "", + " type=\"svep\"/>", cpu->sve_max_vq * 16, base_reg++); g_string_append_printf(s, "", + " regnum=\"%d\" type=\"int\"/>", base_reg++); info->num += 2; g_string_append_printf(s, ""); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ab3f5ace3..8a492465d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg32(buf, vq * 2); + return gdb_get_reg64(buf, vq * 2); } default: /* gdbstub asked for something out our range */ diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py index 972cf73c31..b9ef169c1a 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): except gdb.error: report(False, "checking zregs (out of range)") + # Check the aliased V registers are set and GDB has correctly + # created them for us having recognised and handled SVE. + try: + for i in range(0, 16): + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) + report(int(val_z) == int(val_v), + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) + except gdb.error: + report(False, "checking vregs (out of range)") + def run_test(): "Run through the tests one by one" -- 2.20.1 From MAILER-DAEMON Fri Jan 15 08:19:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0P0i-0005Nz-9Q for mharc-qemu-arm@gnu.org; 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Fri, 15 Jan 2021 05:18:46 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1BCCD1FF9E; Fri, 15 Jan 2021 13:08:32 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 16/30] gdbstub: implement a softmmu based test Date: Fri, 15 Jan 2021 13:08:14 +0000 Message-Id: <20210115130828.23968-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:19:17 -0000 This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to: - add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org> diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index 0c4f5c3808..8b91ff95af 100755 --- a/tests/guest-debug/run-test.py +++ b/tests/guest-debug/run-test.py @@ -16,6 +16,7 @@ import subprocess import shutil import shlex import os +from time import sleep from tempfile import TemporaryDirectory def get_args(): @@ -27,10 +28,21 @@ def get_args(): required=True) parser.add_argument("--test", help="GDB test script", required=True) - parser.add_argument("--gdb", help="The gdb binary to use", default=None) + parser.add_argument("--gdb", help="The gdb binary to use", + default=None) + parser.add_argument("--output", help="A file to redirect output to") return parser.parse_args() + +def log(output, msg): + if output: + output.write(msg + "\n") + output.flush() + else: + print(msg) + + if __name__ == '__main__': args = get_args() @@ -42,18 +54,25 @@ if __name__ == '__main__': if not args.gdb: print("We need gdb to run the test") exit(-1) + if args.output: + output = open(args.output, "w") + else: + output = None socket_dir = TemporaryDirectory("qemu-gdbstub") socket_name = os.path.join(socket_dir.name, "gdbstub.socket") # Launch QEMU with binary if "system" in args.qemu: - cmd = "%s %s %s -s -S" % (args.qemu, args.qargs, args.binary) + cmd = "%s %s %s -gdb unix:path=%s,server" % (args.qemu, + args.qargs, + args.binary, + socket_name) else: cmd = "%s %s -g %s %s" % (args.qemu, args.qargs, socket_name, args.binary) - print("QEMU CMD: %s" % (cmd)) + log(output, "QEMU CMD: %s" % (cmd)) inferior = subprocess.Popen(shlex.split(cmd)) # Now launch gdb with our test and collect the result @@ -63,16 +82,15 @@ if __name__ == '__main__': # disable prompts in case of crash gdb_cmd += " -ex 'set confirm off'" # connect to remote - if "system" in args.qemu: - gdb_cmd += " -ex 'target remote localhost:1234'" - else: - gdb_cmd += " -ex 'target remote %s'" % (socket_name) + gdb_cmd += " -ex 'target remote %s'" % (socket_name) # finally the test script itself gdb_cmd += " -x %s" % (args.test) - print("GDB CMD: %s" % (gdb_cmd)) - result = subprocess.call(gdb_cmd, shell=True); + sleep(1) + log(output, "GDB CMD: %s" % (gdb_cmd)) + + result = subprocess.call(gdb_cmd, shell=True, stdout=output) # A negative result is the result of an internal gdb failure like # a crash. We force a return of 0 so we don't fail the test on diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 1057a8ac49..a7286ac295 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -15,6 +15,7 @@ CRT_PATH=$(AARCH64_SYSTEM_SRC) LINK_SCRIPT=$(AARCH64_SYSTEM_SRC)/kernel.ld LDFLAGS=-Wl,-T$(LINK_SCRIPT) TESTS+=$(AARCH64_TESTS) $(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index b14e94f332..e190b1efa6 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -197,6 +197,7 @@ __start: bl main /* pass return value to sys exit */ +_exit: mov x1, x0 ldr x0, =0x20026 /* ADP_Stopped_ApplicationExit */ stp x0, x1, [sp, #-16]! diff --git a/tests/tcg/i386/Makefile.softmmu-target b/tests/tcg/i386/Makefile.softmmu-target index 1c8790eecd..5266f2335a 100644 --- a/tests/tcg/i386/Makefile.softmmu-target +++ b/tests/tcg/i386/Makefile.softmmu-target @@ -19,6 +19,7 @@ CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc TESTS+=$(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) # building head blobs .PRECIOUS: $(CRT_OBJS) diff --git a/tests/tcg/i386/system/boot.S b/tests/tcg/i386/system/boot.S index 90aa174908..794c2cb0ad 100644 --- a/tests/tcg/i386/system/boot.S +++ b/tests/tcg/i386/system/boot.S @@ -76,7 +76,7 @@ _start: */ call main - /* output any non-zero result in eax to isa-debug-exit device */ +_exit: /* output any non-zero result in eax to isa-debug-exit device */ test %al, %al jz 1f out %ax, $0xf4 diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gdbstub/memory.py new file mode 100644 index 0000000000..67864ad902 --- /dev/null +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -0,0 +1,130 @@ +from __future__ import print_function +# +# Test some of the softmmu debug features with the multiarch memory +# test. It is a port of the original vmlinux focused test case but +# using the "memory" test instead. +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb +import sys + +failcount = 0 + + +def report(cond, msg): + "Report success/fail of test" + if cond: + print("PASS: %s" % (msg)) + else: + print("FAIL: %s" % (msg)) + global failcount + failcount += 1 + + +def check_step(): + "Step an instruction, check it moved." + start_pc = gdb.parse_and_eval('$pc') + gdb.execute("si") + end_pc = gdb.parse_and_eval('$pc') + + return not (start_pc == end_pc) + + +# +# Currently it's hard to create a hbreak with the pure python API and +# manually matching PC to symbol address is a bit flaky thanks to +# function prologues. However internally QEMU's gdbstub treats them +# the same as normal breakpoints so it will do for now. +# +def check_break(sym_name): + "Setup breakpoint, continue and check we stopped." + sym, ok = gdb.lookup_symbol(sym_name) + bp = gdb.Breakpoint(sym_name, gdb.BP_BREAKPOINT) + + gdb.execute("c") + + # hopefully we came back + end_pc = gdb.parse_and_eval('$pc') + report(bp.hit_count == 1, + "break @ %s (%s %d hits)" % (end_pc, sym.value(), bp.hit_count)) + + bp.delete() + + +def do_one_watch(sym, wtype, text): + + wp = gdb.Breakpoint(sym, gdb.BP_WATCHPOINT, wtype) + gdb.execute("c") + report_str = "%s for %s" % (text, sym) + + if wp.hit_count > 0: + report(True, report_str) + wp.delete() + else: + report(False, report_str) + + +def check_watches(sym_name): + "Watch a symbol for any access." + + # Should hit for any read + do_one_watch(sym_name, gdb.WP_ACCESS, "awatch") + + # Again should hit for reads + do_one_watch(sym_name, gdb.WP_READ, "rwatch") + + # Finally when it is written + do_one_watch(sym_name, gdb.WP_WRITE, "watch") + + +def run_test(): + "Run through the tests one by one" + + print("Checking we can step the first few instructions") + step_ok = 0 + for i in range(3): + if check_step(): + step_ok += 1 + + report(step_ok == 3, "single step in boot code") + + # If we get here we have missed some of the other breakpoints. + print("Setup catch-all for _exit") + cbp = gdb.Breakpoint("_exit", gdb.BP_BREAKPOINT) + + check_break("main") + check_watches("test_data[128]") + + report(cbp.hit_count == 0, "didn't reach backstop") + +# +# This runs as the script it sourced (via -x, via run-test.py) +# +try: + inferior = gdb.selected_inferior() + arch = inferior.architecture() + print("ATTACHED: %s" % arch.name()) +except (gdb.error, AttributeError): + print("SKIPPING (not connected)", file=sys.stderr) + exit(0) + +if gdb.parse_and_eval('$pc') == 0: + print("SKIP: PC not set") + exit(0) + +try: + # These are not very useful in scripts + gdb.execute("set pagination off") + + # Run the actual tests + run_test() +except (gdb.error): + print("GDB Exception: %s" % (sys.exc_info()[0])) + failcount += 1 + pass + +# Finally kill the inferior and exit gdb with a count of failures +gdb.execute("kill") +exit(failcount) diff --git a/tests/tcg/multiarch/system/Makefile.softmmu-target b/tests/tcg/multiarch/system/Makefile.softmmu-target index db4bbeda44..4657f6e4cf 100644 --- a/tests/tcg/multiarch/system/Makefile.softmmu-target +++ b/tests/tcg/multiarch/system/Makefile.softmmu-target @@ -7,8 +7,25 @@ # complications of building. # -MULTIARCH_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/multiarch/system +MULTIARCH_SRC=$(SRC_PATH)/tests/tcg/multiarch +MULTIARCH_SYSTEM_SRC=$(MULTIARCH_SRC)/system VPATH+=$(MULTIARCH_SYSTEM_SRC) MULTIARCH_TEST_SRCS=$(wildcard $(MULTIARCH_SYSTEM_SRC)/*.c) MULTIARCH_TESTS = $(patsubst $(MULTIARCH_SYSTEM_SRC)/%.c, %, $(MULTIARCH_TEST_SRCS)) + +ifneq ($(HAVE_GDB_BIN),) +GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py + +run-gdbstub-memory: memory + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(HAVE_GDB_BIN) \ + --qemu $(QEMU) \ + --output $<.gdb.out \ + --qargs \ + "-monitor none -display none -chardev file$(COMMA)path=$<.out$(COMMA)id=output $(QEMU_OPTS)" \ + --bin $< --test $(MULTIARCH_SRC)/gdbstub/memory.py, \ + "softmmu gdbstub support") + +MULTIARCH_RUNS += run-gdbstub-memory +endif diff --git a/tests/tcg/x86_64/Makefile.softmmu-target b/tests/tcg/x86_64/Makefile.softmmu-target index df252e761c..1bd763f2e6 100644 --- a/tests/tcg/x86_64/Makefile.softmmu-target +++ b/tests/tcg/x86_64/Makefile.softmmu-target @@ -19,6 +19,7 @@ CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc TESTS+=$(MULTIARCH_TESTS) +EXTRA_RUNS+=$(MULTIARCH_RUNS) # building head blobs .PRECIOUS: $(CRT_OBJS) diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S index 73b19a2bda..f8a2fcc839 100644 --- a/tests/tcg/x86_64/system/boot.S +++ b/tests/tcg/x86_64/system/boot.S @@ -124,7 +124,7 @@ _start: /* don't worry about stack frame, assume everthing is garbage when we return */ call main - /* output any non-zero result in eax to isa-debug-exit device */ +_exit: /* output any non-zero result in eax to isa-debug-exit device */ test %al, %al jz 1f out %ax, $0xf4 -- 2.20.1 From MAILER-DAEMON Fri Jan 15 08:19:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0P0k-0005R7-72 for mharc-qemu-arm@gnu.org; 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Fri, 15 Jan 2021 05:18:56 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A537A1FFA5; Fri, 15 Jan 2021 13:08:32 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Chris Wulff , Marek Vasut , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 18/30] gdbstub: drop CPUEnv from gdb_exit() Date: Fri, 15 Jan 2021 13:08:16 +0000 Message-Id: <20210115130828.23968-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:19:20 -0000 gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org> diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 94d8f83e92..492db0f512 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -46,7 +46,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...); void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va); int use_gdb_syscalls(void); void gdb_set_stop_cpu(CPUState *cpu); -void gdb_exit(CPUArchState *, int); +void gdb_exit(int); #ifdef CONFIG_USER_ONLY /** * gdb_handlesig: yield control to gdb diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index d38ec7a162..adc3d21b54 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -333,7 +333,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); @@ -435,7 +435,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); @@ -514,7 +514,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1, #ifdef CONFIG_GPROF _mcleanup(); #endif - gdb_exit(cpu_env, arg1); + gdb_exit(arg1); qemu_plugin_atexit_cb(); /* XXX: should free thread stack and CPU env */ _exit(arg1); diff --git a/gdbstub.c b/gdbstub.c index 15d3a8e1f5..afa553e8fc 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -3068,7 +3068,7 @@ static void gdb_read_byte(uint8_t ch) } /* Tell the remote gdb that the process has exited. */ -void gdb_exit(CPUArchState *env, int code) +void gdb_exit(int code) { char buf[4]; diff --git a/linux-user/exit.c b/linux-user/exit.c index 1594015444..70b344048c 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -34,6 +34,6 @@ void preexit_cleanup(CPUArchState *env, int code) #ifdef CONFIG_GCOV __gcov_dump(); #endif - gdb_exit(env, code); + gdb_exit(code); qemu_plugin_atexit_cb(); } diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index f7b7bff522..93360e28c7 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -1101,7 +1101,7 @@ target_ulong do_arm_semihosting(CPUARMState *env) */ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 27600e0cc0..d919245e4f 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -195,7 +195,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) args = env->dregs[1]; switch (nr) { case HOSTED_EXIT: - gdb_exit(env, env->dregs[0]); + gdb_exit(env->dregs[0]); exit(env->dregs[0]); case HOSTED_OPEN: GET_ARG(0); diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index d7a80dd303..e508b2fafc 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -215,7 +215,7 @@ void do_nios2_semihosting(CPUNios2State *env) args = env->regs[R_ARG1]; switch (nr) { case HOSTED_EXIT: - gdb_exit(env, env->regs[R_ARG0]); + gdb_exit(env->regs[R_ARG0]); exit(env->regs[R_ARG0]); case HOSTED_OPEN: GET_ARG(0); -- 2.20.1 From MAILER-DAEMON Fri Jan 15 08:33:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0PEW-000184-Nh for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 08:33:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0PEV-00015J-FB for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:33:43 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:46090) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0PES-00083y-3m for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:33:43 -0500 Received: by mail-wr1-x42c.google.com with SMTP id d13so9271294wrc.13 for ; Fri, 15 Jan 2021 05:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 15 Jan 2021 05:33:38 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id u83sm12813287wmu.12.2021.01.15.05.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 05:33:33 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 006961FFAC; Fri, 15 Jan 2021 13:08:34 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, Keith Packard , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , Laurent Vivier , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 23/30] semihosting: Change common-semi API to be architecture-independent Date: Fri, 15 Jan 2021 13:08:21 +0000 Message-Id: <20210115130828.23968-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:33:43 -0000 From: Keith Packard The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org> diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3bca73d98..84cc2de3b1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/hw/semihosting/arm-compat-semi.c b/hw/semihosting/arm-compat-semi.c index 93360e28c7..2e959aba08 100644 --- a/hw/semihosting/arm-compat-semi.c +++ b/hw/semihosting/arm-compat-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright © 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -373,12 +377,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ @@ -675,10 +679,10 @@ static const GuestFDFunctions guestfd_fns[] = { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = env_cpu(env); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b56ef..cadfb7fa43 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a492465d6..c5377e7ecb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9875,13 +9876,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 643dcafb83..6176003029 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2306,7 +2307,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] = do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] = do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: -- 2.20.1 From MAILER-DAEMON Fri Jan 15 08:33:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0PEY-0001DX-On for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 08:33:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0PEW-00018R-TF for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:33:44 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:33605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0PEU-00085O-4T for qemu-arm@nongnu.org; Fri, 15 Jan 2021 08:33:44 -0500 Received: by mail-wr1-x42a.google.com with SMTP id 7so2059650wrz.0 for ; Fri, 15 Jan 2021 05:33:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tuoacA6ETpiSNAlNzO7Jo0J8CYkUv6GuPz2V5DgQzqM=; b=WzjqJ7a3B/DXUEwygRJwChspjb0Wex5U8T3j03LBXHypMq0RUn/vNiHkuxm1gknrqd OnB9FSUWSUVj1bGBVOuauzjw39cXhWpMuwW8qfymyt/UIy2OcWS7D+dE4DhpQWB6bI2v NJwLkL2g8jyrP/9v6aGOBN28tYfNyrKOrVlJe+UHoFnCqFGAk9Nhh6QaCvZWaH+VwJpa LEuFNbalTKA2oViK8OXG1ecwdQSfLoqCGVQPBef3NQBBZG/HahJz3+chbC8xyVMR4bA2 W9+jKF76+wHSGOXjjXXqpYa+i2QCELpp2a/B3hYlWd2PH7AgtLdeJzd6xyqwumfkkRlx cd9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tuoacA6ETpiSNAlNzO7Jo0J8CYkUv6GuPz2V5DgQzqM=; b=YUfaXUui9VE1tkQfFPl5C9ZzI6zRhZVrQtgQtP5fzyzO7seQAahLoUecBPa+wxMJDT Gp41Cqw5QHhI9zU7ZoC3ZV+44/ruxFHHmrJF7cX2+q6jlfO0xpJpAM5H+dvivDxJLZ+v USG76umbH7+BhNwuTDQo+uU3mVd6wFAf+hR+1RtxVHAbVm5Ti81Spd9Wmn60ROdJNGpo ybBsatA4UTG8XyhGskav9LbroLhEE8CcvCvBqF7o44RprJh+aWe5gG+OJyq66ZeuL96o Qm8DJfebpArKuhstDBO2mP7T+1yOnZr90NqZt0YdpzfrbO1ZdX4CcqL9zEF5uYgPJUbf 5cug== X-Gm-Message-State: AOAM53085JIaN3eIeGe+HI8myOpZ7lJO5zo/vmTUAtRs9YLQdHjAT23C QKaIxFiBO2xfjJrjKJh+6wKWrw== X-Google-Smtp-Source: ABdhPJyztIgRBVw2xEW5o/7viBWyElT2AR/ZPyF/WZdDr7XanCeXQGuvHt/oH2gLYD0Cn36odbNJwA== X-Received: by 2002:a5d:6cd4:: with SMTP id c20mr13244276wrc.57.1610717620697; Fri, 15 Jan 2021 05:33:40 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m21sm12231414wml.13.2021.01.15.05.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 05:33:40 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AB1EB1FFAB; Fri, 15 Jan 2021 13:08:33 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, Keith Packard , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 22/30] semihosting: Move ARM semihosting code to shared directories Date: Fri, 15 Jan 2021 13:08:20 +0000 Message-Id: <20210115130828.23968-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115130828.23968-1-alex.bennee@linaro.org> References: <20210115130828.23968-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:33:45 -0000 From: Keith Packard This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org> diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-configs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/aarch64_be-linux-user.mak b/default-configs/targets/aarch64_be-linux-user.mak index 4c953cf8c5..fae831558d 100644 --- a/default-configs/targets/aarch64_be-linux-user.mak +++ b/default-configs/targets/aarch64_be-linux-user.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=arm TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/targets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=common,oabi TARGET_SYSTBL=syscall.tbl TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/armeb-linux-user.mak b/default-configs/targets/armeb-linux-user.mak index 79bf10e99b..255e44e8b0 100644 --- a/default-configs/targets/armeb-linux-user.mak +++ b/default-configs/targets/armeb-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=syscall.tbl TARGET_WORDS_BIGENDIAN=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/arm-semi.c b/hw/semihosting/arm-compat-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/arm-compat-semi.c diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..eaf3a20ef5 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,7 @@ config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool + select SEMIHOSTING diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..ea8090abe3 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('arm-compat-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.20.1 From MAILER-DAEMON Fri Jan 15 08:55:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0PZD-0003H0-0J for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 08:55:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0PYy-0003Cm-FQ; Fri, 15 Jan 2021 08:54:54 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:38145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0PYu-0000BM-Ki; Fri, 15 Jan 2021 08:54:52 -0500 Received: by mail-yb1-xb30.google.com with SMTP id r63so5088760ybf.5; Fri, 15 Jan 2021 05:54:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ixNEZN1pFQbixJvXzSJWe23RlLp2otnpJ4+txpnch/o=; b=F1Iq4pDKrn3IOwon2r2rmwNT32Sw1mjR67TxXwpbZfAz1GSeZ7RI+JxQnW8Ji3yOpx 9OJo5MGZnBjesiU1amQHo+4jMf4Ny0xo/F/kvnbB0whGtsnQ4YOjP+A+j5XdeIdliQCn gspjLruVKlPfgWgo60211Bur9mykT2lv/GVxLjr+u7zAm3c/UnJWEOrGiwvRlXmZ83YU 7Uqi/q2HROjfivDavAjmQRRnbZarrkt2eOeYDSyYuiCGnubSIV/OE7eWTVrf1OWLlKSa x856/kQPYrkG1SLTJzQNt8o83p8vvHuIyHOGBVK50/v7Ewb1msxJVS/6qAI7GuogdcrH zZsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ixNEZN1pFQbixJvXzSJWe23RlLp2otnpJ4+txpnch/o=; b=pDllgeoKufoKcLsCJy5Kjw6HY7Io5aHwWSqlXzVrC5aq1B+ZfC0xKPMMmJBd2fdl7e fwgq+Mr8Aik0BPwr+JIboDdTsirA1F4kRw/MgcGCG3sYnL5yXtfjr29iC1S70RfJS+4J VLOA+/80lsQS2SuPJjMFJdRhpCrgL7cK1NfnehQMxIEP93kz1V6m+MK1UPLK01f011AF 6LMazjoT8jfGRdVtm7qIiZSO9de8aOybn6aBwI94wDls8k626opp7C2DJ1lLuAaGD79b yiEJO6Yv2TcSY3THZFfP1EiNcFat9RwKDMYSJD5B9fLxBHpOjSLCv4TY0Vci9vs8uDEB W0rg== X-Gm-Message-State: AOAM531pGZk02hyvZgFQA9fDCG6sXpQC1QKcMD23g+qjLFPJDL/5oQz4 4O3Rjd8jYY/+E8Qm0kj8EIl7oU6uFhCQuesWNGY= X-Google-Smtp-Source: ABdhPJwJl9gl7UUtMNtIqIwkwP4MuugcTobNwEkOmATZgTk9ak+ImMVdV49SKs49FugTitD9Ixjd1zwslxllmuaJmp0= X-Received: by 2002:a05:6902:210:: with SMTP id j16mr18907535ybs.122.1610718886727; Fri, 15 Jan 2021 05:54:46 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> In-Reply-To: From: Bin Meng Date: Fri, 15 Jan 2021 21:54:34 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Havard Skinnemoen Cc: Francisco Iglesias , Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 13:54:57 -0000 Hi Havard, On Fri, Jan 15, 2021 at 11:29 AM Havard Skinnemoen wrote: > > Hi Bin, > > On Thu, Jan 14, 2021 at 6:08 PM Bin Meng wrote: > > > > Hi Francisco, > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > wrote: > > > > > > Hi Bin, > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > From: Bin Meng > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > bytes are expected to be received after it receives a command. For > > > > example, depending on the address mode, either 3-byte address or > > > > 4-byte address is needed. > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > sending the address bytes, and the dummy cycles need to be counted > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > It is not in bit, or cycle. However for some reason the model has > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > approach is to convert the number of dummy cycles to bytes based on > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > While not being the original implementor I must assume that above solution was > > > considered but not chosen by the developers due to it is inaccuracy (it > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > also because the detail is already in use for catching exactly above error. > > > > > > > I found no clue from the commit message that my proposed solution here > > was ever considered, otherwise all SPI controller models supporting > > software generation should have been found out seriously broken long > > time ago! > > > > The issue you pointed out that we require the total number of dummy > > bits should be multiple of 8 is true, that's why I added the > > unimplemented log message in this series (patch 2/3/4) to warn users > > if this expectation is not met. However this will not cause any issue > > when running U-Boot or Linux, because both spi-nor drivers expect the > > same assumption as we do here. > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > there is a logic to calculate the dummy bytes needed for fast read > > command: > > > > /* convert the dummy cycles to the number of bytes */ > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > Note the default dummy cycles configuration for all flashes I have > > looked into as of today, meets the multiple of 8 assumption. On some > > flashes the dummy cycle number is configurable, and if it's been > > configured to be an odd value, it would not work on U-Boot/Linux in > > the first place. > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > flash controllers. There are major two cases: > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > For such case, driver will calculate the correct number of dummy > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > fix flashes working with such controllers. > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > Please send patches to explain this in detail how this is going to > > work. I am open to all possible solutions. > > > > > > > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > > > the dummy cycle configuration via some registers, and hardware will > > > > automatically generate dummy cycles for us. Fixing the m25p80 model > > > > is not enough, and we will need to fix the SPI/QSPI models for such > > > > controllers. > > > > > > > > This series fixes the mess in the m25p80 from the flash side first, > > > > > > Considering the problems solved by the solution in tree I find m25p80 pretty > > > clean, at least I don't see any clearly better way for accurately modeling the > > > dummy clock cycles. Counting bits instead of bytes would for example still > > > force the controllers to mark which bits to count (when transmitting one dummy > > > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > > > cycles since it takes two cycles to transfer 8 bits). > > > > > > > SPI is a bit based protocol, not bytes. If you insist on bit modeling > > with the dummy cycles then you should also suggest we change all > > cycles (including command/addr/dummy/data phases) to be modeled with > > bits. That way we can accurately emulate everything, for example one > > potential problem like transferring 9 bit in the data phase. > > I agree with this. There's really nothing special about dummy cycles. > Making them special makes it super painful to implement SPI controller > emulation because you have to anticipate when ssi_transfer changes > semantics from byte-at-a-time to bit-at-a-time. I doubt all the SPI > controllers in the tree gets it right all the time. > Yep, it's not just painful for SPI controllers, and for the case 1 SPI controller it's impossible to snoop the data to distinguish when the dummy cycles begin. > > However modeling everything with bit is super inefficient. My view is > > that we should avoid trying to support uncommon use cases (like not > > multiple of 8 for dummy bits) in QEMU. > > Perhaps ssi_transfer could take an additional bits parameter? That > should make it possible to transfer any number of bits up to 32, while > keeping the common case simple on both sides. And it would work for > any SPI transfer, not just dummy cycles. This sounds like a good tradeoff from the emulator perspective. But I am not sure we should do this to solve the dummy cycle mess given all the default dummy cycle configurations so far match the multiple of 8 assumption. Regards, Bin From MAILER-DAEMON Fri Jan 15 09:38:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0QFI-0004Rj-8D for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 09:38:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0QFG-0004Q0-Q1; Fri, 15 Jan 2021 09:38:34 -0500 Received: from mail-yb1-xb2b.google.com ([2607:f8b0:4864:20::b2b]:39914) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0QFE-0002OP-CF; Fri, 15 Jan 2021 09:38:34 -0500 Received: by mail-yb1-xb2b.google.com with SMTP id k4so5216518ybp.6; Fri, 15 Jan 2021 06:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/VvweCqDZRlAevjUrDbgsRM1GiPcEDvH69lmfCC89iY=; b=QfpeyqQn17DAW6rncpyCAwX5bA2P01iogNSVos6anQyiyVM6mvHE0Svi1uF7MicKC0 ndApnzlwltigtoZbHzYXBLpeiaU8Xdme2jvsHqCHGmMd4cr0gUjFApZtVXDkReqbp2xw eI+vyOnF4/Qql+pKhPu9V6741ynwT6c+K6Q4oj07/fk7TkGoTJCK8LNeSnmtjmEqxh1y 0fvk9bQG5BFgK+wTX1z898S8CjSVLskQxy4lIkURPyizTpzx+AJus3vDNBtMNcjQpFym un4zwyeV7ALWSkUyY9HGwawdGl8H5uGqV9a9iAOJoy27aYSFTKzUGakj4edXSRZRBbZH /EqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/VvweCqDZRlAevjUrDbgsRM1GiPcEDvH69lmfCC89iY=; b=FJGN9yWjsloOr4DqSEG8T00HL+K0SG3oAcAZnLif98Fcin6OnB+En+gNJn68hdBtlP g2Zolye6NZdVAL4L0Rmuy3yMMXCqUYIRDG057PK5Ul108gEHCTbWzyNT3Hu1f0xIki7r csTvuvqBWNVMyhPm8ik3AQORpxOn3gBn2vCta35JTELOVNsk+4NmlE7AIyzWjiqmJT5Y D1beszO/8p49AYlwJs8IvQabmAPFkl1rmL0DHO04XT/lrNSs610QOIqXk6+I4xLFFOJ6 ykL9iaSf/8GWeDrx5CuxoBkPCaZjEN3sn/eCT4tifdnhh6pXW+khQ6GrU4gW49iTfKv3 iQyg== X-Gm-Message-State: AOAM532e6LmwGmxPFNLZ1q/7PiSeQzESFB1PkQuSCsFrjAKxSU3Yt5dN 4vLAM50tWDne4tcM8o4Yne86BiWUf+SAYtCdyQA= X-Google-Smtp-Source: ABdhPJxd/BwKs+JS+9wOwD/d/k3E0ZiiM7YPehUfOsn//E66TIahN6CC/FHlE9NWlUKSSI1CcHBsAPfIPkvcvw+6BNs= X-Received: by 2002:a25:2a86:: with SMTP id q128mr13724478ybq.387.1610721510468; Fri, 15 Jan 2021 06:38:30 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> In-Reply-To: <20210115122627.GB29923@fralle-msi> From: Bin Meng Date: Fri, 15 Jan 2021 22:38:18 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Francisco Iglesias Cc: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2b; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 14:38:35 -0000 Hi Francisco, On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias wrote: > > Hi Bin, > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > Hi Francisco, > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > wrote: > > > > > > Hi Bin, > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > From: Bin Meng > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > bytes are expected to be received after it receives a command. For > > > > example, depending on the address mode, either 3-byte address or > > > > 4-byte address is needed. > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > sending the address bytes, and the dummy cycles need to be counted > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > It is not in bit, or cycle. However for some reason the model has > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > approach is to convert the number of dummy cycles to bytes based on > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > While not being the original implementor I must assume that above solution was > > > considered but not chosen by the developers due to it is inaccuracy (it > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > also because the detail is already in use for catching exactly above error. > > > > > > > I found no clue from the commit message that my proposed solution here > > was ever considered, otherwise all SPI controller models supporting > > software generation should have been found out seriously broken long > > time ago! > > > The controllers you are referring to might lack support for commands requiring > dummy clock cycles but I really hope they work with the other commands? If so I I am not sure why you view dummy clock cycles as something special that needs some special support from the SPI controller. For the case 1 controller, it's nothing special from the controller perspective, just like sending out a command, or address bytes, or data. The controller just shifts data bit by bit from its tx fifo and that's it. In the Xilinx GQSPI controller case, the dummy cycles can either be sent via a regular data (the case 1 controller) in the tx fifo, or automatically generated (case 2 controller) by the hardware. > don't think it is fair to call them 'seriously broken' (and else we should > probably let the maintainers know about it). Most likely the lack of support I called it "seriously broken" because current implementation only considered one type of SPI controllers while completely ignoring the other type. > for the commands is because no request has been made for them. Also there is > one controller that has support. Definitely it's not "no request". Nearly all SPI flashes support the Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is "seriously broken" for those case 1 type controllers because they cannot read anything from the m25p80 model at all. Unless the guest software being tested only uses Read (03h) command which is not affected. But I can't find a software that uses Read instead of Fast Read. > > The issue you pointed out that we require the total number of dummy > > bits should be multiple of 8 is true, that's why I added the > > unimplemented log message in this series (patch 2/3/4) to warn users > > if this expectation is not met. However this will not cause any issue > > when running U-Boot or Linux, because both spi-nor drivers expect the > > same assumption as we do here. > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > there is a logic to calculate the dummy bytes needed for fast read > > command: > > > > /* convert the dummy cycles to the number of bytes */ > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > Note the default dummy cycles configuration for all flashes I have > > looked into as of today, meets the multiple of 8 assumption. On some > > flashes the dummy cycle number is configurable, and if it's been > > configured to be an odd value, it would not work on U-Boot/Linux in > > the first place. > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > flash controllers. There are major two cases: > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > For such case, driver will calculate the correct number of dummy > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > fix flashes working with such controllers. > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > Please send patches to explain this in detail how this is going to > > work. I am open to all possible solutions. > > In that case I suggest that you instead try with a device property > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > count to dummy bytes inside m25p80. Below is an example on how to modify the No this is wrong in my view. This is not like a DMA vs. PIO handling. > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > can follow a similar pattern). This way the fifo mode will be able to work the > way you desire while also keeping the current functionality intact. Suddenly > removing functionality (features) will take users by surprise. I don't think we are removing any features. This is a fix to make the model to be used by any SPI controllers. As I pointed out, both U-Boot and Linux have the multiple of 8 assumption for the dummy bit, which is the default configuration for all flashes I have looked into so far. Can you please comment what use case you want to support? I requested a U-Boot/Linux kernel testing in the previous SST thread [1] against Xilinx GQSPI but there was no response. [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1606704602-59435-1-git-send-email-bmeng.cn@gmail.com/ > > static void decode_fast_read_cmd(Flash *s) > { > uint8_t dummy_clk_cycles = 0; > uint8_t extra_bytes; > > s->needed_bytes = get_addr_length(s); > > /* Obtain the number of dummy clock cycles needed */ > switch (get_man(s)) { > case MAN_WINBOND: > dummy_clk_cycles += 8; > break; > case MAN_NUMONYX: > dummy_clk_cycles += numonyx_extract_cfg_num_dummies(s); > break; > case MAN_MACRONIX: > if (extract32(s->volatile_cfg, 6, 2) == 1) { > dummy_clk_cycles += 6; > } else { > dummy_clk_cycles += 8; > } > break; > case MAN_SPANSION: > dummy_clk_cycles += extract32(s->spansion_cr2v, > SPANSION_DUMMY_CLK_POS, > SPANSION_DUMMY_CLK_LEN > ); > break; > default: > break; > } > > if (s->model_dummy_bytes) { > int lines = 1; > > /* > * Expect dummy bytes from the controller so convert the dummy > * clock cycles to dummy_bytes. > */ > extra_bytes = convert_to_dummy_bytes(dummy_clk_count, lines); > } else { > /* Model individual dummy clock cycles as byte writes */ > extra_bytes = dummy_clk_cycles; > } > > s->needed_bytes += extra_bytes; > s->pos = 0; > s->len = 0; > s->state = STATE_COLLECTING_DATA; > } > > Best regards, > Francisco Iglesias > > > > > > > > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > > > the dummy cycle configuration via some registers, and hardware will > > > > automatically generate dummy cycles for us. Fixing the m25p80 model > > > > is not enough, and we will need to fix the SPI/QSPI models for such > > > > controllers. > > > > > > > > This series fixes the mess in the m25p80 from the flash side first, > > > > > > Considering the problems solved by the solution in tree I find m25p80 pretty > > > clean, at least I don't see any clearly better way for accurately modeling the > > > dummy clock cycles. Counting bits instead of bytes would for example still > > > force the controllers to mark which bits to count (when transmitting one dummy > > > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > > > cycles since it takes two cycles to transfer 8 bits). > > > > > > > SPI is a bit based protocol, not bytes. If you insist on bit modeling > > with the dummy cycles then you should also suggest we change all > > cycles (including command/addr/dummy/data phases) to be modeled with > > bits. That way we can accurately emulate everything, for example one > > potential problem like transferring 9 bit in the data phase. > > > > However modeling everything with bit is super inefficient. My view is > > that we should avoid trying to support uncommon use cases (like not > > multiple of 8 for dummy bits) in QEMU. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id q20sm3701495eju.1.2021.01.15.07.24.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Jan 2021 07:24:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope To: quintela@redhat.com Cc: Peter Maydell , Alistair Francis , Bin Meng , qemu-devel@nongnu.org, Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Bin Meng References: <20210112183529.2011863-1-f4bug@amsat.org> <20210112183529.2011863-5-f4bug@amsat.org> <87im81gdig.fsf@secure.mitica> <875z41gd8c.fsf@secure.mitica> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <21102f76-d7b1-0b98-ad66-d8d76348aaef@amsat.org> Date: Fri, 15 Jan 2021 16:24:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <875z41gd8c.fsf@secure.mitica> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:24:47 -0000 On 1/13/21 2:47 PM, Juan Quintela wrote: > Juan Quintela wrote: >> Philippe Mathieu-Daudé wrote: >>> Signed-off-by: Philippe Mathieu-Daudé >> >> I think this one is wrong. > > Wrong is a strong word. I mean that it changes behaviour and the commit > message don't talk about changing behaviour. Indeed. Well I'll simply drop this patch as it is not essential. Thanks for reviewing the series! Phil. From MAILER-DAEMON Fri Jan 15 10:31:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R45-0005eF-NU for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R41-0005Xw-2I; Fri, 15 Jan 2021 10:31:02 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:39743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R3u-0000xH-P3; Fri, 15 Jan 2021 10:30:56 -0500 Received: by mail-ej1-x62c.google.com with SMTP id n26so13839419eju.6; Fri, 15 Jan 2021 07:30:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=uiFGIlAxUu4JOJhVYdjndEVzVqFiiMzibebdemylKWc=; b=SmLOaRcNu35hmJxclAkpq/Z2zfsTp3xq16m9aSBrEvCu4FTaet74EH1C46B8PkjM87 sQiV1D9fOSG78UGvFdezNOZ2hyIYV7F1iVLeMVgL8Su/nlR8DEKiYKAdBfaD/8dX4rzG tfzb+bx6E085mzcsc/RO8uv+TAvOjqdGdjFcpdq1ia+q5FvH24m92rFEdsF4LzATePIu v92PDJCdFkfr9O1JOrg10fm+IG4zWNPt3L9t/vmpQXnYU/BFUEqJX1s7eE5gocN3AGLq 5JyHJcOHIr40D0O9VLE1yB2Rm21el8Dzx1zpg6RyGydaGFLsZu+itOh8VMcY2Q+vzh/2 N2Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=uiFGIlAxUu4JOJhVYdjndEVzVqFiiMzibebdemylKWc=; b=loLgq0wmHsg4A6I00FGe1JAyOdIHHPNzkhZDH5/e3nBrcX5H+eKazLu4ReR6JiEtyo DWbDGxhtjqy1Za4W3UjwPLT812PS/oQUk05hBdvcMTo8uz3OwvwUFKzt1EazUyPKF28q HDf0ErW4GL5fMNT6bqHsO9Sv0E3D+0t/dGwx87fNN/gIATGMVQxioM4r6nTbGcAjaykK ZNoBhZKlPFFkeBd1yQHkw7pH807aI/n/Jq3iXqZnRm0yB10h540kA8gcPJ/cA1MFJ8J8 A2n+AU4Zds1Wjapjeku7tKNTK2Ku8Z8GOm8RWQUyFS/06UTRix80hq3TFWiW3vrZV2tq mTqg== X-Gm-Message-State: AOAM532z5FYdhc5N1Ag3NtEUAnIxr0p98FbsNyInmuyTN/arSxKtNaK5 smOXBsd7BReGQjbXXclncsEgJ7jCJX0= X-Google-Smtp-Source: ABdhPJz+SELq/tgKJRbXYPqq96EQjxJjXEQIWGf52pq+7rP3wqlOsvG5MCGBL4+yGfesghburUs1YQ== X-Received: by 2002:a17:907:3f29:: with SMTP id hq41mr9334716ejc.227.1610724651944; Fri, 15 Jan 2021 07:30:51 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id k22sm4261481edv.33.2021.01.15.07.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:30:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Fri, 15 Jan 2021 16:30:40 +0100 Message-Id: <20210115153049.3353008-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:03 -0000 Hi,=0D =0D This is how I understand the ecSPI reset works, after=0D looking at the IMX6DQRM.pdf datasheet.=0D =0D This is a respin of Ben's v5 series [*].=0D =0D Since v6:=0D - Dropped "Reduce 'change_mask' variable scope" patch=0D - Fixed inverted reset logic=0D - Added Juan R-b tags=0D - Removed 'RFC' tag as tests pass=0D =0D Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com>=0D (queued on riscv-next).=0D =0D Copy of Ben's v5 cover:=0D =0D This series fixes a bunch of bugs in current implementation of the imx=0D spi controller, including the following issues:=0D =0D - chip select signal was not lower down when spi controller is disabled=0D - remove imx_spi_update_irq() in imx_spi_reset()=0D - round up the tx burst length to be multiple of 8=0D - transfer incorrect data when the burst length is larger than 32 bit=0D - spi controller tx and rx fifo endianness is incorrect=0D =0D [*] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg02333.html=0D =0D Diff with v6:=0D =0D Key:=0D [----] : patches are identical=0D [####] : number of functional differences between upstream/downstream patch= =0D [down] : patch is downstream-only=0D The flags [FC] indicate (F)unctional and (C)ontextual differences, respecti= ve=3D=0D ly=0D =0D 001/9:[----] [--] 'hw/ssi: imx_spi: Use a macro for number of chip selects = su=3D=0D pported'=0D 002/9:[----] [--] 'hw/ssi: imx_spi: Remove pointless variable initializatio= n'=0D 003/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG r= eg=3D=0D ister value'=0D 004/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_read() to handle block d= is=3D=0D abled'=0D 005/9:[0003] [FC] 'hw/ssi: imx_spi: Rework imx_spi_write() to handle block = di=3D=0D sabled'=0D 006/9:[----] [--] 'hw/ssi: imx_spi: Disable chip selects when controller is= d=3D=0D isabled'=0D 007/9:[----] [--] 'hw/ssi: imx_spi: Round up the burst length to be multipl= e =3D=0D of 8'=0D 008/9:[----] [--] 'hw/ssi: imx_spi: Correct the burst length > 32 bit trans= fe=3D=0D r logic'=0D 009/9:[----] [--] 'hw/ssi: imx_spi: Correct tx and rx fifo endianness'=0D =0D Bin Meng (4):=0D hw/ssi: imx_spi: Use a macro for number of chip selects supported=0D hw/ssi: imx_spi: Round up the burst length to be multiple of 8=0D hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic=0D hw/ssi: imx_spi: Correct tx and rx fifo endianness=0D =0D Philippe Mathieu-Daud=3DC3=3DA9 (4):=0D hw/ssi: imx_spi: Remove pointless variable initialization=0D hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value=0D hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled=0D hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled=0D =0D Xuzhou Cheng (1):=0D hw/ssi: imx_spi: Disable chip selects when controller is disabled=0D =0D include/hw/ssi/imx_spi.h | 5 +-=0D hw/ssi/imx_spi.c | 137 +++++++++++++++++++++++----------------=0D 2 files changed, 86 insertions(+), 56 deletions(-)=0D =0D --=3D20=0D 2.26.2=0D =0D From MAILER-DAEMON Fri Jan 15 10:31:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R45-0005ex-VC for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42322) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R43-0005Ya-2W; Fri, 15 Jan 2021 10:31:03 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:36140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R40-00010t-MR; Fri, 15 Jan 2021 10:31:02 -0500 Received: by mail-ej1-x629.google.com with SMTP id l9so8130181ejx.3; Fri, 15 Jan 2021 07:30:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xdTpIDS65/IfYybVOuMbzhHG9RGib9cm8VYJpYoGsWk=; b=OW95yZ/cB5wcvzWT38Vd+zNLll5JxteBr2Myl5hn64k+oxwwMBwXONmMWjNH/tgUxR W7G++IlKXLQidpJhUWQit6bL5Hsam6lpizDuqULcqTIS3Awm5+VmbVemJIzNf2wEEmL+ oO/bju/QmaiqCcJtO0VhIv06U+MQbN/BSkOShK/jE3YO81a8LSDCXMio9uqHWV/51Zsw SMKDbd4GTAkV61z5YREDml8FrQ52Fc5614qtqUXSJGp2RAOMq84wZAqtGqvUoeJbIwSy pgpFf/hHnHpth+GArvrNRY+suSIqEzEoWfxi89CdtBlR9l7MV1QWnmqncMA2ymASxWpC gBVA== X-Google-DKIM-Signature: v=1; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id i13sm4072081edu.22.2021.01.15.07.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:30:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Bin Meng , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Juan Quintela Subject: [PATCH v7 1/9] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Fri, 15 Jan 2021 16:30:41 +0100 Message-Id: <20210115153049.3353008-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:03 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-2-bmeng.cn@gmail.com> Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé --- include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f3643..eeaf49bbac3 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454e..e605049a213 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R48-0005jl-Uv for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R46-0005gx-Kr; Fri, 15 Jan 2021 10:31:06 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:45614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R45-00011q-1p; Fri, 15 Jan 2021 10:31:06 -0500 Received: by mail-ed1-x531.google.com with SMTP id r5so9917881eda.12; Fri, 15 Jan 2021 07:31:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x6oAR5xhjstTwMmnbU+HOg/xOa5AqlizhCQtpQ411WY=; b=I5so5R5h4jTlYCFgTINKkP8J9Q2SPHRcmlQhNC1ob2FWgMVtX/9XOz2TxGkE95X2iq vaU12bDKLSYByGhVGJA0OjIIGZ6pqq7wAHIMYUQQrJmMPTWWjhXm22QlbKonfG6i8gl1 LQC0t03UM+5yy/gZom6ZsFsPLpCtKuvEJDCllviMlzjWaLq74J3sHsS9jbTT+3gur99L 4Mh3k9IYK9iGG8WiExKeyMd4qM13aYwMU4C+/7ENjaJNKs0fW9GxV+sPad0Jj6L1CBSD HMbg+k5yAoj5GdXYJCRUNlGZSLlmvxfkhCeNTtU7KZg1zdpXXh352PBqeUQj+O0KkCCB LuLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x6oAR5xhjstTwMmnbU+HOg/xOa5AqlizhCQtpQ411WY=; b=fqrIgYffc5WwhEgQAn0LndND9TYtBbqgMOOr1mmH/kTyzz8Kd+y3aep09weBqtCj7C 5Mpw2x+8XWBrgzD2KKaqLGM1CfZccvWlXn7N2ZktVnD2jTWeQQC8TPTO7efOnt7eZxVp 2QQAaJgy7GQmg8KShQ9VI1qaDk8XGCnM1OwAh5tcFk9aOhEU63/smE8V4INF91CYNojL kPlSdFBR+iXDYZAHPrhRTXyD1bGchoNA6WH2jx2H0YwYcLsSiqfMo76bd9rCT5/mq2C1 xklxOBK0s0+wgj5qtjkH10/azIsJV8xeZPsvE0HKK6uBthtEME7pndUH3/bk8VebewHg LHMw== X-Gm-Message-State: AOAM532mW9E5VNS9/f6HbEiO2ggN64MPRhs/ikuaHqxpeQRIRlPnR2eo Kx2+JHMCAqv4iqqOixMXN9OvRh68TbQ= X-Google-Smtp-Source: ABdhPJxnlWvzTn9arvw1kgCAs2/AkLEZWMl8Bbc65xTcJMNFi3N3gA8rSK29/s3T7v9eCeK3qQFtAA== X-Received: by 2002:a05:6402:41:: with SMTP id f1mr9819779edu.286.1610724662967; Fri, 15 Jan 2021 07:31:02 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id m24sm3679721ejo.52.2021.01.15.07.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Juan Quintela Subject: [PATCH v7 2/9] hw/ssi: imx_spi: Remove pointless variable initialization Date: Fri, 15 Jan 2021 16:30:42 +0100 Message-Id: <20210115153049.3353008-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:07 -0000 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a213..40f72c36b61 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -428,8 +428,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4G-0005nx-E3 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4D-0005lc-A2; Fri, 15 Jan 2021 10:31:13 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:33748) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4A-00014D-78; Fri, 15 Jan 2021 10:31:12 -0500 Received: by mail-ed1-x530.google.com with SMTP id c6so2816336ede.0; Fri, 15 Jan 2021 07:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z4qy97PFtHKZ/41ys7UAdQh2nrLy+ZugZUPugDx4O98=; b=AKI5uBOzblTOtH+Y7blzK5kUzm7yX4uP4lOKG2Q6F2ycmw3FsO++nnhUxzXdfA5XJG XZYZ85YCskXvpMe8rpnC4HrptdTt3GjMUclmZY/RyqkolB1AblsypnQ2pYKXeZXVmTyB e+/yXhRrPtzGfkuwxMOwv/AfHd8rHcZSpwsCpIwJMTy09UaREP7jYC915+nl5LCJjOc1 5EVlz0Fig/u5Xvg7U9QqOXRcj377Qjd1MaH5onD7vpHLYEhWdKjjgInQiY2nL58GFiPC tulis2+2sfRpwolfN/pbgkBw9WrsVO8Kx+gswt0NiwGUBL8yR2kgA4AIfX35TIGdYnKy N5dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Z4qy97PFtHKZ/41ys7UAdQh2nrLy+ZugZUPugDx4O98=; b=eI7LylLZn1yXdRzgzQbTX1ze5xehZIokZZKaBm1cEHvokGSbOEMjkNeuohV5pskbSd pGkRgPhqlWJrYEHguap7kf9YBDdSbtApTiOjKrGEAWuXwmYnkKuPDvq681GQ+IwlkzC+ ka79eCVIDRw1Uc37nY5S3qhuZFvk9uR/HHhGiZ2fRUOD/tAsMfD2A092WJEqtqQ0/HkH K3Z43VWge3HsAWUj171vrFQHOsUT1V4T8oj9+t/L6nYVSng1C3K3h7Pgh3bnh8eugSYz 6u70bOaideps/MWqwHUe7sOKxxF21X/iUQ/ntHIjVqg36i2EG2uXQF1XmNNT3e15pyZM Sa5Q== X-Gm-Message-State: AOAM531jP0lHWrmaoSlrh7asw8g9NTOt4nFuTsl3ysEFQcITa3EWK13d QeuTIJ14NpXMdNPpCFGfkQOUUKgWJmQ= X-Google-Smtp-Source: ABdhPJxHD291RM+cDSzyoPG+y1Ffmdg+MFamJVee5CPxbE0/XGtkUPwwimZP+IE2KD8yhhdl0B0yqA== X-Received: by 2002:a05:6402:40c4:: with SMTP id z4mr9862256edb.233.1610724668346; Fri, 15 Jan 2021 07:31:08 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id d4sm4147193edq.36.2021.01.15.07.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Juan Quintela Subject: [PATCH v7 3/9] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Fri, 15 Jan 2021 16:30:43 +0100 Message-Id: <20210115153049.3353008-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:13 -0000 When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 40f72c36b61..78b19c2eb91 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + unsigned i; DPRINTF("\n"); - memset(s->regs, 0, sizeof(s->regs)); - - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4M-0005sv-M5 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4J-0005px-3H; Fri, 15 Jan 2021 10:31:20 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:45616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4H-00015w-7f; Fri, 15 Jan 2021 10:31:18 -0500 Received: by mail-ed1-x530.google.com with SMTP id r5so9918587eda.12; Fri, 15 Jan 2021 07:31:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xaRka/hjNrCEM8MOc6Ojwmtdv4ln3LXGXICzD6KNu+w=; b=akQZ1cNzBHC6RT1phVrotIUQdcMJNnHFhcCoTMLOJ4hzoaMy/wkdmCoK7sBc+PeCdg VvsyZQShYUAiQKsgF4NG7ZJamEQ4fqI1CTk+nAO2hItPncA1KHmf8sWNSjUhNoSNceap yj5PgoyOW2QIbIVtWXIm3ReViebPtPri9ZV/VVecXicoxfJIagqCDFx9ya+/cFdTqtqB cQhEZj0NZjX/v64uwTaPfwqD98dldbtQI1Tp6o3wu3g7QiSKl0QOSVKCT89bMyPKj498 nFHKahVcrHz5OwQIP2TaVJoViD9N1jvTiSAnCpvEEcA6G1i1N3GoYdIZfaFPI5Iznj8z 9e/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xaRka/hjNrCEM8MOc6Ojwmtdv4ln3LXGXICzD6KNu+w=; b=qm0/n1sX+WFOA9FJX11Sl3n8NDQ6qTmS1ueveGAuqDdxq8K3UA3C5lDF4zjQUn0xxd 1nTgO8fDcYi+dyGJM8rHDBdVhQ8j43cKFVpWaWbvHlArqrvvWyp21vnyDW5xpcpH6cnk vW/PxM0zDJ3Y/+hp9uaMdo/CzuJQAVaaseP+RgvYZCCpUXd7lDRpXtQYxTE8bzv21q58 8b6Nf+9bQauCrg7JlJxJJUoDGCj30dd8ueRr0zkjrBUlz4SGx4CPRtj6r1t2+YR8kkN+ j72GoWGxbvwoFmeyEOxZ8gBf74lxZV+mksrszlhoKPq803Gfphmx9DGQy1FoB6NVAKmM zTeg== X-Gm-Message-State: AOAM530obG/M0unyio4AegnOQbENYCF2WDdqZM1/CJP2iY1u0Zy1xPbV 1esKbmBSTISMB9/FW0NC2/CDQn6htVY= X-Google-Smtp-Source: ABdhPJxLOhS1el156e/Sn/ZRkIPL9pLiKbbdEmQ1sxu0hWilZ5vH3VlKDgLkZOEh9mrt1nm329OoGQ== X-Received: by 2002:a05:6402:2207:: with SMTP id cq7mr6445345edb.272.1610724673877; Fri, 15 Jan 2021 07:31:13 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u9sm1113506ejc.57.2021.01.15.07.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Juan Quintela Subject: [PATCH v7 4/9] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Fri, 15 Jan 2021 16:30:44 +0100 Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:21 -0000 When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 78b19c2eb91..ba7d3438d87 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -269,42 +269,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); + + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; } - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from MSGDATA gives 0 */ - - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4R-0005wD-Ti for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4O-0005ua-Nw; Fri, 15 Jan 2021 10:31:25 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:34303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4L-00018Q-87; Fri, 15 Jan 2021 10:31:23 -0500 Received: by mail-ej1-x62f.google.com with SMTP id hs11so11525743ejc.1; Fri, 15 Jan 2021 07:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SxhCah3PmIN+C/eYAy1fbYSX9RyZywJv9Y2BedeIMA4=; b=B7Ew6UQ0RIIhXfw5JWZyCgyfv6JzI0u8GkIUkbS2Tavn72KrWeWPPGr54aSfMiqIFO Tw+8qE0JZ9UeMYEcmR5xQ9B9z58yyP9gPyj1cmWSJtnO+8ZWWmW4R9uJc/0BuvmCJpTX XKLPC4enAEkyiDnwQEc4ep8diYjiPGvpkj6+acZKC3pirPA7gGC9qmy1GhALebI43zRU emzN/iFh+dzjTjjjtJ6hWb/2wG0N1/NhuDSnnxAyERvmZPVSDgIgpidx8jkVIXgBuuzt okPFgDjmzfSP1jsUFq/z0iQEgUCdUJYmw9W4KvFSeW3v/dycXvGPsQjKvQCR5OkNe0ay VdbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SxhCah3PmIN+C/eYAy1fbYSX9RyZywJv9Y2BedeIMA4=; b=gASe99hTLrgMavSkNiv/6Vg4+tMjCdsu621WKs/kkfsY+TD3qLtN7kbLCeyDVMtOim wmYqxVa/AQlvfI40oEr4p6cB0crdTH2KfmyaEmkTaJmv0KmfZmfhVwZQ7P2DJT8Byx6y 0mOMlzHO+RpJectk1EqC0D+YGeXyt+GdI0114nukk0SuDop22OTvkaX3PuRap5zO1yHh O7DK3D1Q71XomWrJwyvvcf304RC8gVvjEs+RHy+S2naXTXI1QhYGDKj0wqHzin17JCvE oBrrWDVoF+rUqmT+Jop5Tkj9ERl0tAQoGd5K9RN1mGOuE2PFjtbKUNTjbEPz3YVHvWb4 qvSQ== X-Gm-Message-State: AOAM533Q3S12KCNP9iei1O+94X7JKpFft4OgVALavC2yYA2N5VW/cLib 0hQWglc+ALIoTwDrTgYifDYgPqxBDXQ= X-Google-Smtp-Source: ABdhPJxXYhqdUdkvzzKw92zvZjxCWt45x8RkhUoVXTm82QO+bxKujJljmA7/W7DUvRL3IFF4WYbdUA== X-Received: by 2002:a17:906:d98:: with SMTP id m24mr5373690eji.428.1610724679246; Fri, 15 Jan 2021 07:31:19 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id r23sm3672540ejd.56.2021.01.15.07.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Fri, 15 Jan 2021 16:30:45 +0100 Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:26 -0000 When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Move the imx_spi_is_enabled() check earlier. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index ba7d3438d87..f06bbf317e2 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + s->regs[ECSPI_CONREG] = value; + if (!(value & ECSPI_CONREG_EN)) { + /* Keep disabled */ + return; + } + /* Enable the block */ + imx_spi_reset(DEVICE(s)); + } + change_mask = s->regs[index] ^ value; switch (index) { @@ -330,10 +345,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } @@ -359,12 +371,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; - if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); - return; - } - if (imx_spi_channel_is_master(s)) { int i; -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4Z-0005zW-O6 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4T-0005xT-1M; Fri, 15 Jan 2021 10:31:29 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:37238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4Q-0001DG-Qg; Fri, 15 Jan 2021 10:31:28 -0500 Received: by mail-ed1-x52c.google.com with SMTP id g1so9299394edu.4; Fri, 15 Jan 2021 07:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=55dYkHbl/cwpKN2kA/sZVcE4jjUL5RKiblFskzBR/GA=; b=LM0eThwHGM0htSwCiVS/1dNHnUU8+1cGq4s8BGwylgNVjgcWSt5LgHY+ANj3HSh8yJ sFHFdSdOVu6gssGcdGEt5YlPL17YTgZA4gSelQA79xe1koS7V4kxV+3oSimEOhuimGRK OC2VTHB7UJMCHxfrZMJxM+EBp+KfZil1kT9EVpflQGueoWWsKbcpCZMDXHSZRAMmw0jK edKC4TF80SwELmBR98tVjXs72Eti4ePqPeR7UIu28YaNj8w1KbpHHZ9JFSHhqd+44V0S KX0q2hm+ZwtJfd8zLvvHzD8M4cfPs9ESKBuXh0W2pypiSjKltD83HP7VrEmL/2VV4DMk 705A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=55dYkHbl/cwpKN2kA/sZVcE4jjUL5RKiblFskzBR/GA=; b=Y0DhnxU6p0RDBAEmRRDzP1hEeezUNojIwMlMvrP3J8y8HbCz0xMNEI7EqXrscokkUw KXkayATRKVSQfBVMkNhAHtxjY/iV9DKmQVcN1yp78dDO5garL4PDACM7TB3fPrmta8ya geo4rHVvytdaU3w6QB/fdX/u/DQ3Q6KvjCOhSZ6vj73/PKUN1Vm0sjGeR5dRE6eW2RGm X/4r1ERaoPYy8pKDedz5Q19YYBOc1byRPgv1c/N9TtUk/itUj807pM8WFPN0Q7SHLSXn yFXC8jRWpfvrMLvzbqQ9aKuU+8vwz1zMX4YpTd2Eii4AUN1DxHRQEq4tg/Y2ldPiutvm cClA== X-Gm-Message-State: AOAM532ZxcXWodL5aep2iXIqmLTX6YarTpWb/VX8wLe89h/lqTpf0HEn zawfkiGbPt7/3ztriAtVpeTS0F+a8yY= X-Google-Smtp-Source: ABdhPJzE2HLxi/PzuMR3uNE6yeTL2wjXoccf9fn/f7hQDo//uPoqL92nPqvIKAuqAzK+coYdt/O/RQ== X-Received: by 2002:a05:6402:5246:: with SMTP id t6mr10038334edd.62.1610724684744; Fri, 15 Jan 2021 07:31:24 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id rl7sm3713330ejb.107.2021.01.15.07.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Xuzhou Cheng , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Fri, 15 Jan 2021 16:30:46 +0100 Message-Id: <20210115153049.3353008-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:31 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index f06bbf317e2..c132f99ba5b 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,6 +254,10 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_update_irq(s); + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } + s->burst_length = 0; } -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4c-00062K-W7 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4Y-0005zN-7T; Fri, 15 Jan 2021 10:31:35 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:44533) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4W-0001Ht-SS; Fri, 15 Jan 2021 10:31:34 -0500 Received: by mail-ed1-x52f.google.com with SMTP id p22so9932719edu.11; Fri, 15 Jan 2021 07:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1U/j+ZtYgfFfpgAROYFKnmLYCujF8T7WZdISgEWGF4o=; b=rMwBWqIzVt3I/l8dUwpO+TYimrJXQgUTXfMjnd3gOs6/4DDOByCFnAZ66nlO/ks2XT hsoRqneIpiELEUs+c+ady7xLwY76RlGSgPs5lBILFIZexFsXVNI1+5ZX54h/gLeF3nFt RKXhib8ZPWY++jCONbb5MOcohFKp841DWXiVLW83Wjytj53fyb7w0M6U9BAIETjmKn7L bjP9C/SzylWb6YSxvAzJS3/qOQInecjBe5Zr6wnyuhN7t7sbwEYlvSU7i2Ov3YIygvri 4aYyW3Mzw3k4AUcnuTzIjiSCz0Vm6o3uPca36BQ0jcFi4/vr/dw2yb+O9ACpsVuCLMUV 09yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1U/j+ZtYgfFfpgAROYFKnmLYCujF8T7WZdISgEWGF4o=; b=aaXcjKd1cZ3ZPsyuWLelz+1LN2ycJNX8chLBy4aPNqaMJN0GeM5lqf0L6kHUMnqCiI GgwWZbR1Wu/fr2LG35WSWfW7F9CIlOmXRNMHbRtXDiD6FiwWJbMGTnwLnIZm/gF0gB2N I3End4xXZFzfv2IP3pasdntELUlT8kCI0ho+FmyCCDcKfrKo9cDCCPDaY/8wEJAoMSeL IldAJ15sEHivBT4fFXz3KDSMVUIgY26ew/PMqKIt0nQWM8GT9pRarAh4fNZLYvHVbWkQ OTyMd+VVlRmWDDkUAjwFQ42xoqrQdCtRInt7a1VL/pe3947EleB4Fm1gNRyjrQrpfJUz 7jsA== X-Gm-Message-State: AOAM531PsA4Ub9mHnfVvjyMdIGeLk6KIWv1+aWNNLHhg11wtB9HgqvyF 3Pc+4TeY8idvKWT1hkAdEkGFQU+eS6A= X-Google-Smtp-Source: ABdhPJwvPNw1PpawidvPh70/KgK2odiJeatFn6FpbsJE2PuwoTR8CR61rfI2jkZfst/+1ZJzcPQxZw== X-Received: by 2002:a50:cf02:: with SMTP id c2mr646495edk.333.1610724690193; Fri, 15 Jan 2021 07:31:30 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id t15sm4147361eds.38.2021.01.15.07.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 7/9] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Fri, 15 Jan 2021 16:30:47 +0100 Message-Id: <20210115153049.3353008-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:36 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-5-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index c132f99ba5b..b79304d93d9 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + burst = ROUND_UP(burst, 8); + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length rounded up to %d; this may not work.\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4i-00068C-3c for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4d-00062N-06; Fri, 15 Jan 2021 10:31:39 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:39756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4b-0001Kq-DB; Fri, 15 Jan 2021 10:31:38 -0500 Received: by mail-ej1-x62f.google.com with SMTP id n26so13842961eju.6; Fri, 15 Jan 2021 07:31:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4fJWv7T8ni1UgNw8omgysewBjnwqG7EbsoSKPeXsii8=; b=lzifNm3cJxOPtWGXFvfLqIGNzR8hJHhy9rToFJfvGcE97KyWAgQnlDexulLCWYSjEd VwA/bcttwCqYYJJryfLNGVtyqGdV6xPaQdcNr+8nzKNHCO6nLojpqsQfim9mzsajXUbu xJ1Vrj1eA1P8YHHic+Enie56T79CIK6NjSGD5ET3CYWg3bp5sY4UZaXji23E3cEBMgG7 zIa3zouHEIDt0k+A0UIgPlJ31r//wokYZmx+cHEyAlPXl5uWi3OBj5froQzEff3RphoK mPH20NWxM4UClN5VoxzPwIW5eshFDV3TD8dQapL1/MD7AWvlflknqFyarNdQT1IoFY8C gvlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4fJWv7T8ni1UgNw8omgysewBjnwqG7EbsoSKPeXsii8=; b=P/D6r2SaDkSKZEFdG5OBKwBxxMiB5B0DoVRKq7OcprSQ75XFlr0Ar171AZm1ahQ5+B oBBGgc1FDqSmYof7BOVtHUjgTAiaUxP8U5+nNq+mJTXc6bKwHthURoHnSkXlaF+yvCIF MFZ0NI3z6AN2n539wxDZ4uhFIl+QQjcgdCJ7e4fi2bZLuWWcASSy3EUr5chH5TCpvgPF 2UHjDzUgf7JPkfIsaufkMCdHpdtdvdzXejsvKcEdHCi0RtZjKwuQgs90fa+33Qu0zUAc mNSeB4zyml5S9sApOrVmVyQNUqmVR7PeqNvs6FK4PMHaRjcz4ckI7LAwfvxV1pac3FTy hyug== X-Gm-Message-State: AOAM5302pLvjy+914/SBUfWTeWTtx4jeo5yvY8jHBLp6CO+upfapZbSG F6Ejz9dpy7oWxbfQ0hh/ZunUY0AFRVc= X-Google-Smtp-Source: ABdhPJzZmXzxRol0w1xttkBVBhbTSTguYFnzG3SCxDBpOO2WQ86RWctTz2Zm/N0EmMRnnqpg8G7UKA== X-Received: by 2002:a17:906:aec6:: with SMTP id me6mr9090264ejb.542.1610724695528; Fri, 15 Jan 2021 07:31:35 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id k6sm3681616ejb.84.2021.01.15.07.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 8/9] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Fri, 15 Jan 2021 16:30:48 +0100 Message-Id: <20210115153049.3353008-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:41 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210112145526.31095-6-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index b79304d93d9..707defb8b3f 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -191,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.26.2 From MAILER-DAEMON Fri Jan 15 10:31:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0R4k-0006Cr-Ad for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 10:31:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0R4i-00069X-Hg; Fri, 15 Jan 2021 10:31:44 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:46131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0R4g-0001NU-VY; Fri, 15 Jan 2021 10:31:44 -0500 Received: by mail-ej1-x630.google.com with SMTP id t16so13793852ejf.13; Fri, 15 Jan 2021 07:31:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aEe4vTMLP9auxSgIg50YIr5kL7dVLhmpX4y+OZIHpwk=; b=ASpgClg+JRP/ky8FIiFta/JZigSt9d0hu6L3+YKSl+b6Psm5H6Nz66j9blO/MsG5Uh TigbpTMoukHoTNLLmqBtnefgiOpNl12IXY+pkIuAfTdFNgAPjLd27taOHQS9FSEt2FOA KwRO7jJghfcqIa0DfRUUVHTpCD02SIx3M3Qt4uZRA2gtBh1ru6lKkkFmBhYuDVY28ea8 oDzaTG4wvpuhKKcnjze5bEBvaMhBkTgAOsTv/PslY2Qqlt1nY7epEUnKObPKkXt3eFkG rB18BjOeFcdh93Yo7/avKPEIe6KWGvbLVa9VqPcFyn22urzdvrlJ0ACjO2DM6sWdrvuh B5VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aEe4vTMLP9auxSgIg50YIr5kL7dVLhmpX4y+OZIHpwk=; b=qYpvyWlJ3+F+9VTd4oCqNupIYi6ThkbCGPXnVSAbci1mslmG5/I+UVlFoQ5g2EZo2X PVQmJbkYQQBxFMaBeIJoF4obmkkYWYiF3y2jg4M/NdUfwb9XEENWiYDEX9sDoL1BXmrP xrww6/mmsVxFgPUcIA1nxSndv2sR0SLAyIgC/KXAWIpq5RAoc0KAPJpFAGdomIAknBoE OGTp5z+15f1FV5sM35rQKsmEmtt2VwTkOC4Wx68GPfoPPnNUPJEMaVZ4X6Ug8AZu2+f5 L6pdCxH+k0+vd2F8eJglqYVcqzzSlU9BfQ5ucrJ9TNigRdGp70FPiRugOwEaBSNJbSsq lLYg== X-Gm-Message-State: AOAM532NWRyS60VvrONbQM9SdIqWrvu9vOFbu0wN1p+Jec0FTAQ1IdtA ZROw+bBs3f5dU/T4xmBmOaqQEzanUeU= X-Google-Smtp-Source: ABdhPJzv3vkO37wk3vhcrLrdJw6BuyJyGc4fTtVXoe0XV4v2Ls8bhk+3nXEvkzgq44c31BnOJPRSbg== X-Received: by 2002:a17:906:fa85:: with SMTP id lt5mr9330813ejb.344.1610724700940; Fri, 15 Jan 2021 07:31:40 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id oq7sm3872991ejb.63.2021.01.15.07.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 07:31:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Peter Maydell , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 9/9] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Fri, 15 Jan 2021 16:30:49 +0100 Message-Id: <20210115153049.3353008-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210115153049.3353008-1-f4bug@amsat.org> References: <20210115153049.3353008-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 15:31:45 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Message-Id: <20210112145526.31095-7-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 707defb8b3f..081b7e464ff 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -175,7 +175,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -196,7 +195,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -205,13 +204,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.26.2 From MAILER-DAEMON Fri Jan 15 17:46:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xrq-0003VC-U2 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:46:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xrp-0003Ue-0n for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:53 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:36028) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xrm-0005AC-NH for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:52 -0500 Received: by mail-pl1-x62a.google.com with SMTP id e9so1286966plh.3 for ; Fri, 15 Jan 2021 14:46:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pILtCL3+WOm9enm51rY0JFGFgNs8LZRCjkNlG93rpNA=; b=W3vq9ozSZ255uAJRfsRNCK1EHdnjZPBsiN71XY2PMGdxkttPVUfvVFaZJXW9qH9+8M 1lguNXyPerolwKYRjTSXNS3OLXbWJP5CeqREWLEeqgq2dj4EPhAGim+LRuWds2LKoLME q18nPaJOj2GsSadHNfY9pVDxcHR+WTqAPEAbcxetM0HapurKC+qa/Na6DXYtdBRoOy5R Nqnp8piu0bBelGwUquuaYZxRIkeAYghF4HvVbauM9ijF21gAoYxPmYWyO5PX44mJFmP/ 6W+ys/dg22LUfoW4GcynMwcQz1CjoZF0j53enhSAIVTPfrYwQZ+3iDRSIY8uDYV2WOUt fqvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pILtCL3+WOm9enm51rY0JFGFgNs8LZRCjkNlG93rpNA=; b=pilUP81hP1ZXjhUblKK5lB29esZClkqzIJSFt1RKSsWoFGXoMbQ9iY76V3ex1SQPm0 s6JuLzUCYkL73n6SxS+FBZE5DUKbgedPffhQewEtKjVoSxUrydKR7324GVRgCElMio+L iLSq3EtyMVSQ6ohvyJ803ZiKt3IBpX3nWYLEydxMOAp4MLNGRbOgxTAREpW4ereaf1Dh YASKu4wqPo9mT49e06fwKBv1M68PhK3VysHBrBxjKKHjU5W4c0FwsFPT02svARuGr6qE /aXflhCGFxwsDufoNiQ8FtmBACPdNQw5eXBH2VsQy3h7bcGxh5AYwqLefPS7qVr0MW7k ITHQ== X-Gm-Message-State: AOAM533kc3XhyGGfsL+CJEXFDHjYJ3gjPb5n9n65KNn6YsrDzgC/jIWi Oheogqx7VbnqIRouQTBjYjR9Wg== X-Google-Smtp-Source: ABdhPJyZCr+loFoofn2cQ90wzf97f/x07++6nTNXjl0OAmUjwrPHVwZm6IZWxHe9eFqNPUAjmyuANg== X-Received: by 2002:a17:902:b717:b029:dc:3e69:80e8 with SMTP id d23-20020a170902b717b02900dc3e6980e8mr14707442pls.40.1610750809022; Fri, 15 Jan 2021 14:46:49 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Date: Fri, 15 Jan 2021 12:46:24 -1000 Message-Id: <20210115224645.1196742-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:46:53 -0000 The kernel abi was finally merged into 5.10. Changes for v3: * Split out type changes to separate patches. * Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. * Do not overlap PAGE_TARGET_2 with PAGE_RESERVED. * Use syndrome.h, arm_deliver_fault. r~ v1: https://patchew.org/QEMU/20191015163254.12041-1-richard.henderson@linaro.org/ v2: https://patchew.org/QEMU/20200605041733.415188-1-richard.henderson@linaro.org/ Richard Henderson (21): tcg: Introduce target-specific page data for user-only linux-user: Introduce PAGE_ANON exec: Use uintptr_t for guest_base exec: Use uintptr_t in cpu_ldst.h exec: Improve types for guest_addr_valid linux-user: Check for overflow in access_ok linux-user: Tidy VERIFY_READ/VERIFY_WRITE bsd-user: Tidy VERIFY_READ/VERIFY_WRITE linux-user: Do not use guest_addr_valid for h2g_valid linux-user: Fix guest_addr_valid vs reserved_va exec: Add support for TARGET_TAGGED_ADDRESSES linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG linux-user/aarch64: Implement PROT_MTE target/arm: Split out syndrome.h from internals.h linux-user/aarch64: Pass syndrome to EXC_*_ABORT linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error target/arm: Add allocation tag storage for user mode target/arm: Enable MTE for user-only tests/tcg/aarch64: Add mte smoke tests bsd-user/qemu.h | 9 +- include/exec/cpu-all.h | 47 ++++- include/exec/cpu_ldst.h | 42 +++-- linux-user/aarch64/target_signal.h | 3 + linux-user/aarch64/target_syscall.h | 13 ++ linux-user/qemu.h | 19 +- linux-user/syscall_defs.h | 1 + target/arm/cpu-param.h | 3 + target/arm/cpu.h | 24 +++ target/arm/internals.h | 245 +------------------------ target/arm/syndrome.h | 273 ++++++++++++++++++++++++++++ tests/tcg/aarch64/mte.h | 53 ++++++ accel/tcg/translate-all.c | 28 +++ bsd-user/main.c | 2 +- linux-user/aarch64/cpu_loop.c | 61 +++++-- linux-user/main.c | 2 +- linux-user/mmap.c | 29 ++- linux-user/syscall.c | 73 +++++++- target/arm/cpu.c | 19 ++ target/arm/mte_helper.c | 39 +++- target/arm/tlb_helper.c | 15 +- tests/tcg/aarch64/mte-1.c | 25 +++ tests/tcg/aarch64/mte-2.c | 42 +++++ tests/tcg/aarch64/mte-3.c | 47 +++++ tests/tcg/aarch64/mte-4.c | 42 +++++ tests/tcg/aarch64/Makefile.target | 6 + tests/tcg/configure.sh | 4 + 27 files changed, 856 insertions(+), 310 deletions(-) create mode 100644 target/arm/syndrome.h create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xrw-0003X9-Kz for mharc-qemu-arm@gnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 01/21] tcg: Introduce target-specific page data for user-only Date: Fri, 15 Jan 2021 12:46:25 -1000 Message-Id: <20210115224645.1196742-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:46:54 -0000 This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Signed-off-by: Richard Henderson --- v3: Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. --- include/exec/cpu-all.h | 42 +++++++++++++++++++++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++ linux-user/mmap.c | 4 +++- linux-user/syscall.c | 4 ++-- 4 files changed, 69 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4b5408c341..99a09ee137 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -264,15 +264,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying code) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -287,6 +293,30 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); + +/** + * page_alloc_target_data(address, size) + * @address: guest virtual address + * @size: size of data to allocate + * + * Allocate @size bytes of out-of-band data to associate with the + * guest page at @address. If the page is not mapped, NULL will + * be returned. If there is existing data associated with @address, + * no new memory will be allocated. + * + * The memory will be freed when the guest page is deallocated, + * e.g. with the munmap system call. + */ +void *page_alloc_target_data(target_ulong address, size_t size); + +/** + * page_get_target_data(address) + * @address: guest virtual address + * + * Return any out-of-bound memory assocated with the guest page + * at @address, as per page_alloc_target_data. + */ +void *page_get_target_data(target_ulong address); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e9de6ff9dd..7bcb6663f1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -113,6 +113,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2740,6 +2741,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2754,6 +2756,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2767,10 +2771,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p->flags & PAGE_VALID) { + ret = p->target_data; + if (!ret) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 810653c503..c693505b60 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -792,7 +793,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = h2g(host_addr); prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d182890ff0..bec2ab7769 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4625,8 +4625,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xs3-0003Xf-TV for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xrr-0003VV-4X for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:55 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33338) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xrp-0005Bd-Cz for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:54 -0500 Received: by mail-pl1-x636.google.com with SMTP id b8so5462499plx.0 for ; Fri, 15 Jan 2021 14:46:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kyzjq96nH0KWrOiii6echH6ofV70lplGMBMMhcVo2Uo=; b=NZ6mpl9ggtqxYOyKpx6AdJI2gAJf/R0znj6EoKUUuG9paOIxhpcg7T4sB1yAWe/V7Z IoUtTj8vvt2RTaVTsybm0o7IDQZcx0nKTs8oPVac9c4UW0dIZqqCKo5u9KBILg1Fvz5j uZkoLbN7RGAbn0umx2kmhRdVdByPHJURB91sIt74Js+4/uZS0RmeN6KZWXItCJ9f2eWQ s09YPG7CPAwFMW44echC5/bzf9e1izzo/1+XojkzBTzu/8nu121jLUHyHG+s6SwevA0K wxQBYmkwzxIcbwud1/2nHRHh+eMFATw5Ads8Q0NLm3EjC1X2qTQjpv2IakiTH2jIFJzO UrEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kyzjq96nH0KWrOiii6echH6ofV70lplGMBMMhcVo2Uo=; b=kogQO8M0KxdHbTfoaPGzRPiBThUXUf8DTyRAjmlEr+7S5DYym05hnzfh1wAL5j2s4I qkqmtR8kaZAQ8SZ68WI/zUwwvucEJG9ooH1DIjQllvMl0hUXxjJ+Y6kQ5X7DGnbGDo/P bUvEv2jxyEZxkYUOktrrM5uLCcpLsYCtT5auuSKHKdjKbZJ/ZyjqmmjUVKUDMLHabl2N o6LeDf67KG/hTgX7GhYoaO+1JVLLCD/eH7uSXwohUiQEJeer84ffDCVXvxhMQM/k46ml b9r/QgXj5OP8jvjxmnUe9BuAN398RgcKBljNThaavSik4FMgDpuREtzfpDwM96yxHrFn DBhw== X-Gm-Message-State: AOAM532e7hOqZnrmwFsQRDwAc5ROz3hHlUHsfGg8VMggYaAI2/uWpaTd NPvatm/QGB0uJJfydMJLuRqaIg== X-Google-Smtp-Source: ABdhPJznzaXIC2NbX86/26pXEE79LmI62CMzc96YyvgrR+IOoSh/iFz7gP1yAbYIo475rF/1h3s3+g== X-Received: by 2002:a17:902:8642:b029:de:2bf1:b061 with SMTP id y2-20020a1709028642b02900de2bf1b061mr14643592plt.10.1610750812180; Fri, 15 Jan 2021 14:46:52 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 02/21] linux-user: Introduce PAGE_ANON Date: Fri, 15 Jan 2021 12:46:26 -1000 Message-Id: <20210115224645.1196742-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:46:55 -0000 Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 99a09ee137..c23c77589b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -275,6 +275,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleared. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index c693505b60..7fb4c628e1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |= PAGE_ANON; + } page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsE-0003ay-Ij for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xru-0003WD-C1 for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:59 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:46252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xrr-0005Cb-0i for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:46:58 -0500 Received: by mail-pl1-x62b.google.com with SMTP id u11so1155204plg.13 for ; Fri, 15 Jan 2021 14:46:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q6Vn8EuRt3zWEIGcR+Vsso1EpzS5NZb4Sjnv0xY+IUE=; b=PaMRsJ4AsTRmfgunMw9G8wCbtxV4VxB1Y1z9QfOjPTRXIaAdiK3IdR+RcWr7+RQjVV +5NEQMFyR4LvlAwjdEjoQ97GxyFyzv+Igw+PjGZnPtWaKBdm2i2I62Lt3mhEShKDLWKb RQVHuBB0r5K009sLlE/7GuVkX8lqY/NWLZKu9WwpBL0WTWSYLqokrupSOpy2itAf/I8r xzKYdyff9RMsNShrlrPEytol4MLV4QYtcmIHF9d17/OvZ34GN+wYxIRoVJy4rVvkegJ6 1DN2OBlmCZw2Q4pRc2GZ8uYn0/uzok7N19XV7hNiy5EMdYYwoHXDn/jPqInbKKV2oEaA Pm5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q6Vn8EuRt3zWEIGcR+Vsso1EpzS5NZb4Sjnv0xY+IUE=; b=B29J401nB+olxr6k0C3vSmGywLNnBym/bhMngJcivASPRcLhVs5rAGNrUElUZpr2t2 5cvcQ9bjKtqcKVoCg18A1Az33EWafYzPc/UUcvap5Dx03x3KdLuiCd5oVCG5DqwxCdDf TYbkOM9XmoQWJqSSXnednO+ac3LDuhJo0/X27vqNl4gmJuz6h1ydNR//7A4EUqcLWTTq DnDe5ADFlnrALoXNCrcckJhycqRtRChM3Ouobtw5b64cAQ4uy7VtAZXW7mZCN0MmY5st kES9/lA/BAT7f8ADq3T8wXl6Mg30fDyCFTRstNp0Ea0atdabxQdp8C1h1RTweNfpwl4I UGcQ== X-Gm-Message-State: AOAM532/QCTjL2ufUxyG2oNjue/H0/av+K+linp3g8C0DZ7s9KnoN36Y bA0+AAszLHVOnmZ8MfRDK7tQTg== X-Google-Smtp-Source: ABdhPJz/yEGErCk7Zt/Jr61dhPZ59UrTF4umCcm5gp1WUGuNvi9T7g+4Ef3q+Jc0PjMiCJzrq2y4Zw== X-Received: by 2002:a17:902:8341:b029:dc:27b:be2d with SMTP id z1-20020a1709028341b02900dc027bbe2dmr15083974pln.30.1610750813805; Fri, 15 Jan 2021 14:46:53 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 03/21] exec: Use uintptr_t for guest_base Date: Fri, 15 Jan 2021 12:46:27 -1000 Message-Id: <20210115224645.1196742-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:00 -0000 This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c23c77589b..c52180e8e6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -158,7 +158,7 @@ static inline void tswap64s(uint64_t *s) /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient location. */ -extern unsigned long guest_base; +extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; diff --git a/bsd-user/main.c b/bsd-user/main.c index 65163e1396..5c8e6a4acd 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -41,7 +41,7 @@ int singlestep; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; unsigned long reserved_va; diff --git a/linux-user/main.c b/linux-user/main.c index bb4e55e8fc..2600245300 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -58,7 +58,7 @@ static const char *cpu_model; static const char *cpu_type; static const char *seed_optarg; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; /* -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsE-0003bL-S7 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xs3-0003Xc-PN for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:11 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:45616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xrt-0005D1-WF for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:04 -0500 Received: by mail-pl1-x631.google.com with SMTP id b8so5438227plh.12 for ; Fri, 15 Jan 2021 14:46:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uDiO56BD9yBVu0nwAI/hhOcXCMAfaRu426dsljY4dMQ=; b=Ii11emU21XXA52/szniJPxFW7eatwD+xZDT7o7o6j3R9fHAsGDCsRXujER8F9l0bV9 qSFsWQUaSvCuosTkzdQHBEYqgy5E3uO+y66zlvQH6bmaVbyhmNMi4HMgmSERSNCNFF0a qr90BL4XHqOmZHQg9TGVCWCWX1r35lnVAxKZvyvb8z7PQ9oMAyss/4ZJ8IaWQ/9FqEgI WAI2nGwYzR+b6d7HYudUVrgXaHzrN2+OBADyBuqKXO8KBKOIgtyg6jYyDjZVtWZ7lqoq GEbdMwzoNSWo8WWZRHAiUmTNb6f9OmXGL162uoeHdIXzB8rWLeyxj6FBArY1DKBRWNMq Hmlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uDiO56BD9yBVu0nwAI/hhOcXCMAfaRu426dsljY4dMQ=; b=rZQS65RGN6gmF/nPkqwPBs67eimsSyBzg7WhPHov/xaD1Lc2YStjFJBHTYoM4xqfSu k++rRZmTm2e+Ckx3KaG6w5T1MfKtL5QOtIE/KC3MXA/lZ5e2HfbDDtLKEwmul67R6Ee9 u2noeEKggiGvYzeUwPAxf0eYwUk6+B9MvZIJ/NGmTyRfmbdI3Kra0CxEDi26Z6nvRGn3 iRVfxWNHjZf2UttZdJgvS5Ff6ElKL85GuMXIpcdOT+xKWV3jUoSylrHZUpIXd/comrAs 2ft18xso01IqH3XiZIcvqWCwwiT7WrH8ISCyuUE3NZj4of8jDbVfH7GiJof9sSaFz9nZ MLyQ== X-Gm-Message-State: AOAM531KbuqVo7KTehp42VRkAZB92FdwyT626w3eK75ZPVjJngho//El azBk+7ELaUzmCnWftgqBSIkZLQ== X-Google-Smtp-Source: ABdhPJxgO9LF9GZs8nh8w+N3IXQ9fG/yQg85ZY7eyDFiP1Kb+fx5SEuhsTdB2Lgh+euIMmdOUWZlCg== X-Received: by 2002:a17:90a:5991:: with SMTP id l17mr1845333pji.187.1610750815323; Fri, 15 Jan 2021 14:46:55 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 04/21] exec: Use uintptr_t in cpu_ldst.h Date: Fri, 15 Jan 2021 12:46:28 -1000 Message-Id: <20210115224645.1196742-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:15 -0000 This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f..3f9063aade 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -70,14 +70,14 @@ typedef uint64_t abi_ptr; #endif /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS #define guest_addr_valid(x) (1) #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) +#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline int guest_range_valid(unsigned long start, unsigned long len) { @@ -85,7 +85,7 @@ static inline int guest_range_valid(unsigned long start, unsigned long len) } #define h2g_nocheck(x) ({ \ - unsigned long __ret = (unsigned long)(x) - guest_base; \ + uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsF-0003dP-KA for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xs6-0003Xv-TA for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:13 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:33330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xru-0005Dv-8V for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:07 -0500 Received: by mail-pl1-x62d.google.com with SMTP id b8so5462586plx.0 for ; Fri, 15 Jan 2021 14:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BPFkHBCfiYE2/tooUwU3w49LVJJCP7NOmKVnwS50G54=; b=cVKi/EO5fMAfl0J+r2MBksBLyMqvCDyxcwuWFw/B7d/QyOp3jq6CjIqXBdd5qtgeYx BK6B3yOo23/ugG7c2INs0jNR0Vpgxfmg7X/dgJONJOwZG2EU6r/OyikYnND6l+kcHJwU Qg3VKh7366OMoeOzo9TXybPAhNh83PeG4OODSM/JKNzefTkMGK+gE6WKwTEc9FahaYhD tVR0sK2xp7+e9GKKOoT+cVQZRXJUDBgWQRPocHFn//aVL8gxsF7dokk5sAs1wSDKJ46v fKjaJZjyLVJ3LNZQTzeMbdA2H8kL1k+I0hGZsjiJYj+Yh3kjp701dDTMqDzebEQoKXRM 4H1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BPFkHBCfiYE2/tooUwU3w49LVJJCP7NOmKVnwS50G54=; b=YwGHZ+Aj1DlFJOkUT60gfCg/ttyc/wGiwA6tN4qrEOk1mJoDqoIM9y/hk7HnZpJuur HlQ6sUbC0Aoeiywt4DJfIH44cIJpTB3tbAO2wtZtlGMCg6++GlmnjzWkgEzPPOcSuHDC mCC/X/n8XkP7wVfRvwvsnkjZ3o9eF+QbhwIca1es4v0oOx90qlSWJMtD8ZuJP+DR+Q8q mjB/d8k8wxtpMJy9kiQ4sDIXBDedbr0u0EdSfDgkLZ2sPi5t9PaHZCMgx70De0+TYfQY Voa4nzKQjhoT1fwSmK6QMUihTiunVC0LvHWZ+FKgDkilwXKeiK9Q1t3rJAfm1blbTDyj dQRQ== X-Gm-Message-State: AOAM531mSQVXXASL3i5beX654cbGZXhKVR6nYzla3h2Cythxfd8bSYoa +TmOKxv7yrfZ8wxrrR2flRTLDbjZ1gdwyU26 X-Google-Smtp-Source: ABdhPJyBOpOsu6OBJWbBU/auhm1HBzyzQEWFRl2H0VnP6d/hHQRD/m3916MQp2cwnQkSEk+D/k/9fw== X-Received: by 2002:a17:902:8d82:b029:dc:20b8:3c19 with SMTP id v2-20020a1709028d82b02900dc20b83c19mr14798262plo.29.1610750817019; Fri, 15 Jan 2021 14:46:57 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 05/21] exec: Improve types for guest_addr_valid Date: Fri, 15 Jan 2021 12:46:29 -1000 Message-Id: <20210115224645.1196742-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:15 -0000 Return bool not int; pass abi_ulong not 'unsigned long'. All callers use abi_ulong already, so the change in type has no effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3f9063aade..5e8878ee9b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; #endif #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsG-0003fS-DJ for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsE-0003aS-5S for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:41656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs3-0005Fp-Hy for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:17 -0500 Received: by mail-pg1-x52e.google.com with SMTP id i7so6937924pgc.8 for ; Fri, 15 Jan 2021 14:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XRNC7TN62/mhJ44h4TxsBn3p8qzX1+L1EKv8lKpxGuM=; b=O2doYa6yIz8jL6bI9AmMpYnadrmnXydclmOZtN9DK6QEVkOIFkl3snvVLj+rahu4LK 2dBT+zZvU5YuREnews9thuQFqdaM7u1Omeg1HpX92QUlm+RcQIehy4h/wsz0GPcglfva WPCqgy/7zuM7Oro7b0+kC0e0QaMx65b6jb4zXGuEjLBnfmR5sgQDoCw0EIYqGiWgO+wo vv51QNabKkqYElsendHDnly9fr7PsHs55rfPRFv4Doij21xLjcZ4cI8MEtE7Txux+R7A 0wpJa25sxhmCCTiWs/dofzZmktmertxL6nCucrfApOjxvhbJJRQQgKzlvMaXcDXrY18Z DE+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XRNC7TN62/mhJ44h4TxsBn3p8qzX1+L1EKv8lKpxGuM=; b=hrAxWNaIrs0LD64x6tHc74kcLkdvW9nJCx8X9BsQuXwbHXHLK3nQAdt100sKMfQq/Y /kwZv0JV4v3A50rNLUotJYz2IMramPQKEA34Gu45XK2zCVqjQ0Hz6aKOUezJ4H8M2fp/ ja3q03xPzXLlQNq5StxHTNlPQWHHDDqSQei5wmCzLl2KuMZEEaut5DnSSk5hhZEJwK8I z7NxLegtxDisKXZ2daRdoxwUGwUNyOd3/bX2JmcglddvXRTpme88WqArIXlG7MuSFrrN C5CUBhtrTktT1KCUnoHf4wJIACIFTIipK+G0yF1Iuv39csG/9ds37E5uZWcpyi+/ImnU SvdA== X-Gm-Message-State: AOAM532Uudwuv/7l5IDi2ob5G23tuUSgxAQamXe1+HznITJ/wNHPXKHW nwNattAbl/bDkkiLqAEe+FPgLdiGmMUBff+J X-Google-Smtp-Source: ABdhPJxrhROru5/oDYFEUmXYHLDX2YylAEj61YMUt1A/l8K7e84OD6oh5jy2yaKo0YamASNyhQbLPA== X-Received: by 2002:a63:130b:: with SMTP id i11mr14736622pgl.300.1610750824862; Fri, 15 Jan 2021 14:47:04 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 10/21] linux-user: Fix guest_addr_valid vs reserved_va Date: Fri, 15 Jan 2021 12:46:34 -1000 Message-Id: <20210115224645.1196742-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:18 -0000 We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 4e6ef3d542..e62f4fba00 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ulong x) +{ + return x <= GUEST_ADDR_MAX; +} static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsG-0003gC-Lo for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsE-0003ak-Fr for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:43084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs0-0005FN-2f for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: by mail-pg1-x535.google.com with SMTP id n10so6917583pgl.10 for ; Fri, 15 Jan 2021 14:47:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cekQQRp0i5HZWYUW7TcRhFHir1r8zA6FY8NgWmITL0g=; b=jWLwcRYiTngZ/Nzz67lB7NXK3iTuCNdax0+JWEbw4ZbC3U3xoWG/MaR5AOW2OwF0BB wbAETgmrWBV8aZ6tqMm8j8Qjl0gIutGuAvU2+sBOBKrlcakQLADxK+jSwxefH69a4c/t vB7HG3edLYHC4TEXrRmyyME2Kkt/IfiVl1hIXRS/A+up3JLGmngS9I+mSFqrfqn3fYV7 4e7IPFPTegFAa6LcAiFwrONaKLXfNy5JjXM4CxrwYLyzaeFLhuLMv8Fc80XLtLju9U+V uNTczzPWKSv6Tc6jEDOE8LfeuqfZB6DF1xQWt4ZWCw9HNZdI/16zg20pL486EHWK4A0j JoTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cekQQRp0i5HZWYUW7TcRhFHir1r8zA6FY8NgWmITL0g=; b=tNFVkQr3b4UlKwWCORqvVPCTZ5gxSPkMqnSW76qlevqxHMn3lHW/40fSDe5K55p4L5 CxJGiA0NilZsPnoGdILc73MvSKY7x9A9j67vWxcXhicz2GMv87gaYclLf028gOpr+DvW 8Ckkb4X3qfG570RqGDwypxMsRmnSp0CUeO5HDfrolA36c0b6cuFK5Wa9dkE4zmXMd9UH acfVEjahUslMCnN+iNP5RVWQ7l/h9MATi9Rnt9y6K4uc1h0Pvt+jc0h0WlFcCsGi22KW cQgLzcZPZTFpmzYv6DChhjmLfkymk/bqxTrZ+vhO7F+mt2bRAqeiYMxHaW0+66mDRS5p 0wzQ== X-Gm-Message-State: AOAM531+aygItOI97o/qC92A7W4QMxaA9tlbt2BXF5QWMv+3C0cEIMVd 3pp1ns4Dcx357Tza43SdeHNmHA== X-Google-Smtp-Source: ABdhPJwybbMjXU099WikbW4ojpTd6f9K0ktxyEX6YnamUwcN+OFzbjsCekDghIjlNqKpLAraB9p9CA== X-Received: by 2002:a63:6305:: with SMTP id x5mr14466820pgb.216.1610750821621; Fri, 15 Jan 2021 14:47:01 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 08/21] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Fri, 15 Jan 2021 12:46:32 -1000 Message-Id: <20210115224645.1196742-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:18 -0000 These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459..4076adabd0 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. */ -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsH-0003h7-30 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0Xs7-0003Y4-Q8 for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:14 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:51027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs0-0005EM-2P for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:11 -0500 Received: by mail-pj1-x1034.google.com with SMTP id md11so5895681pjb.0 for ; Fri, 15 Jan 2021 14:47:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qD60vJJte7K6bQArBY0DduIczHDfCgP2vdEmcn/7+GI=; b=YwlZV9wYAP5Rt/Z+Xt+EGN2PHf3ePFuoh8BcVKwFszB6IR8/OymngxewUfx0X8pjZ8 QQvfRKPY3qi3o3MQH6vejNAIvBoa+ZaC8E7cCs/k77dMnDp7eR6Ww6V2vtMrtxDEowlo o+dw87Dx3tAv1XLvTtH/HBSCoDy2z64DrCPajZ7tf2ZPX3OGUE3/lukbVPDX+uQ8uGrq f22EJjUFiSRXNyh+O9PraGYGWI5ffY76jdBR1rm8eF5//l+vlAla7h9LLzpXRmKILq1q x1KXup0FOSq++Kl0tlOogZNFskRAZ2a0imbe2c+/mRIhAUb4J6wUH2fWsXh3DLZI+G+q LTiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qD60vJJte7K6bQArBY0DduIczHDfCgP2vdEmcn/7+GI=; b=cLz6Dvnf9tk2voosk5q5ns9tFenoPbEXrAQzWLk2oGlpoTHy8gcSy6323zKrX5D+PM dE6/WOrVsxZAeBxijV/yNPf4SwQVHIuagQAGQEEdYn3t1zR0mxzhBsEnU1LWv3zidTUy zbi9Sd7Wa01huqg2h+Vk6Z9APj5E32LKKrJwgH3so35mOgfJURCt1CFY91p28tY8yaPE 5MuijeS67zM1kI5rmo5wIHjgYTQ8zas1gzCoZ41ogwvLm8h5f3McKpdASINDMlfS1+f9 vxItyDO8wRwQaBTeNdVLsN9YvpopWkPZ6WODQxfDLsTobw7/QbNwKWbIpKUWMSqipJ65 CEyw== X-Gm-Message-State: AOAM532vIEDU03YxKFiv7pVQZHHx1jLIM3Z8TovelP/wrxpBE8ZiEviV M3etRlrwFhjo/av7uDeCuA6bxQ== X-Google-Smtp-Source: ABdhPJwgdAho/OdF+WELsY1fJDi903omlO+a51vggx3VfMy+YE8DCF3cIlTDCJ8rz1hbfLIvN1Fzeg== X-Received: by 2002:a17:902:7086:b029:dc:8d:feab with SMTP id z6-20020a1709027086b02900dc008dfeabmr14921287plk.22.1610750820068; Fri, 15 Jan 2021 14:47:00 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 07/21] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Fri, 15 Jan 2021 12:46:31 -1000 Message-Id: <20210115224645.1196742-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:15 -0000 These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index a0f670832e..329a6de669 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -486,8 +486,8 @@ extern unsigned long guest_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -499,9 +499,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsH-0003hr-C2 for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53822) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsF-0003cN-7A for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:19 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:38591) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs3-0005FY-Ij for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:18 -0500 Received: by mail-pg1-x530.google.com with SMTP id q7so6940315pgm.5 for ; Fri, 15 Jan 2021 14:47:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4REF6cfdA8MQv8viPXefMUo/38x0z3uSDZzFVOD3Xwc=; b=yKJEbBv+SrFsgEnltc/TzCtw86pnuM6k14IqbwjELUAeVDqJ3li5/xF7UFZl6/sxkA yoABsgYO0PryhgXiatN2djfCWQaSm36thjzmLwcp0RGiZHjJmI1sawyRwW4QR0lwDFmk Fn+CgVCVbDdYNv6JTPClFC0Au3kM+t3LJvLoymZvDp4Hu2sdPMm8Xt7jp9tgAchii05j jsX9gyhDfZ9EMkzI6PRxvaKtjkanv8f77aw2EXXE12WascTVrohbA95VfyKejvuB4SkD 4t4Fx1bbDFqq8WBSFc0VBBhccVYOxdqeBd+5nyJtENFj6/mnWXp+BQGPWb4ivGkBZr6b hHuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4REF6cfdA8MQv8viPXefMUo/38x0z3uSDZzFVOD3Xwc=; b=VKRpGKMy1+kqaTTOSbz1TYilkQadH2M2vjKepxMtjkjjLXILykF3/VJBH9SwYU8p9p R3hIeKyG4nxWKcsR6xbaTjXlHcguLBtFrrSowWBXvNhRReR8r4U6WtoEi8cC8pDz6+RS tfY5+RLvimldHNi7YJWElBQcME2jX2L5iry8OiyenMVA6EGbf58Ge6Apw99XqGfnP+ab 8QvcYaqgDcoEJDR2Hk5SwnqSoMT+HUoJwrz/JNs3OnTrVLIvc2W2WSHIOrFGv2422G5k NoumK9L6yr5DSuNIU6hzCFAkIvPQOi1nY8Mmf/ZI7Qv0M9Bpx0K6WBSM609osJWLzmH2 8TXQ== X-Gm-Message-State: AOAM533jJmYVie1KMhmoNFl/Wl5O5s64J7fTTSxcps7gqGZNVigMhIZu vgrDzXpVS8OKX+WIlraMhTuzKWPzSvT5890R X-Google-Smtp-Source: ABdhPJzwSYG1HID140ykj4hN5FW2T7+OXAR2XVNf+MOzV+xS6hSZJ+WQ0mOEIJu8DddEkVMG0Ca0Sg== X-Received: by 2002:a63:65c5:: with SMTP id z188mr14580822pgb.332.1610750823237; Fri, 15 Jan 2021 14:47:03 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 09/21] linux-user: Do not use guest_addr_valid for h2g_valid Date: Fri, 15 Jan 2021 12:46:33 -1000 Message-Id: <20210115224645.1196742-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:19 -0000 This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Signed-off-by: Richard Henderson --- v3: Ditch type changes; retain true for HLB <= GAM (pmm). --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5e8878ee9b..4e6ef3d542 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,13 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } +#define h2g_valid(x) \ + (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsJ-0003lq-2W for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsB-0003Z0-SW for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:17 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:35531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xrw-0005EA-Cr for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:14 -0500 Received: by mail-pg1-x531.google.com with SMTP id n7so6956881pgg.2 for ; Fri, 15 Jan 2021 14:46:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rr4uhte3iLsKjX8Cbli6gBSl01cB/KM2FqNYctfYPe4=; b=ZwiPCxB+pgxqBSVhiKyzXLXxQL2ZxeJzOVekdmh0Png2yTdh5LHtbGJfe4xgh5KT5j MONKrUNjyAZIo/Q1APKbecM5C3a2XWQ9n1SkdQYEIAjD3by8a1EfLqIC78kqEvzPy2Iw X/eFDlBpD3YCYzZa19NwkpOOx/Y3yf+HWoCgmgKo2BTMP+Trc3cJb3vfouNGqfVOHF2Y J5j3S2NZgFFGIVUnvR5Mzy56uZgnFXNcA5fWhPpPP37Eb9xSnyHYOAKi9+o1+1smjgD0 z6HBA6xwvzedCCq9CzuCJnhO++Kf0zAKKG6opn1QJNchgzU6sBesjQK/wu7znGiPrZRK 7YOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rr4uhte3iLsKjX8Cbli6gBSl01cB/KM2FqNYctfYPe4=; b=SAptpIcknWaAQ344RQ+N8InmKbsQgar/cl2irEqpCSj/UCaHQE+awA3zi8qku36ODW bRr5+zVkJGTn1P6Ja+C60HzOW4AQCVEsyR1ytVduCDTIfuXp6/FYCOBUDo4je8Gx3iU9 wz4wuhp7drLWI2xU7pl7ZNgRcTva9eJjgVFncAoQtUd4mh4uYsjMOfVCi7sUyxucqWq0 J9aWp6fRpQ1iS0CvHf8/xqzsUx/yOzpiM8fd9lUoafag2ZscgxRowalsxL2qtgRCBy9S EjNi6G7JJ7UZkM6Go4QFqPJN6kfy4eb2PH8plBe62YJO0c2nL+g1TtZzkyyNgUgwdWnu 1duQ== X-Gm-Message-State: AOAM5306e4o2KiR1MsQBkvrSQ14FG+6vmUAggu7Ge48T8TwTLeHgXHNB 7Ww15VqvuyufelQ6fqridzsIRg== X-Google-Smtp-Source: ABdhPJxcsT7aNJHrEI9kefNnsvCzOZVgUW1giA0hGvYOCmrvP2zkMcewy7L+kS2jcSFk2KJJ6Kc8Cg== X-Received: by 2002:aa7:9706:0:b029:19d:a2c6:aeb with SMTP id a6-20020aa797060000b029019da2c60aebmr14865467pfg.36.1610750818505; Fri, 15 Jan 2021 14:46:58 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:46:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 06/21] linux-user: Check for overflow in access_ok Date: Fri, 15 Jan 2021 12:46:30 -1000 Message-Id: <20210115224645.1196742-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:17 -0000 Verify that addr + size - 1 does not wrap around. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..a0f670832e 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -489,12 +489,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size == 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size != 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type == VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsJ-0003mE-8p for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsF-0003dM-KZ for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:19 -0500 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:34070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs3-0005G2-J0 for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:19 -0500 Received: by mail-pg1-x530.google.com with SMTP id i5so6959454pgo.1 for ; Fri, 15 Jan 2021 14:47:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X+LaZKuwwsvEvbJ+r5ztAOZO016eLRKSU8aYWIJf1AQ=; b=LcG7qzDJHtDNdykP4TizHyjuonvDePY1rRb+OzUOPSISfOdv6f99MecPmI4SQFsF/+ nl8ZcxYvz6Y0w6HeI1ml2PWZrOym7gftokPucD4W7IZ2EdcVB0OT5JIGYAnNBj0q7FmV Amejm4HesUHbbbSrgcxzQEvrP6mzc80yj8xrXqmSpUhp9AeT21VjsXB6tXyXgmqhRh6H U/J33hGJT1lE+amylRe5H/zivAw+xyw340BVXyvl9Kg1hN0jR5c41MvjaqhN7KVIMGrG XxcXUGr2pISM4z2cDkUFctVz8btNmF698Iy+p6kyzd5W0uPduXLNK7q/fEuYGxmI8O0k 5C9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X+LaZKuwwsvEvbJ+r5ztAOZO016eLRKSU8aYWIJf1AQ=; b=q4f4ITuMUxTsG/9GT9TxZ/W0q28gEaSxP2SQxd0Vyc2/8z8aCHlqurokN2LVp0rdtf tvCwUXd6RqfK4M8yI0nr48RLu71ys7p2U1he8DLNfagsgb87Ak4eyQQdjiLSMnIznyJ4 V6/MM2E36cO3N8kFxRRMfKzn4IcdBenBvE//S+tO5ISUqVa2OU3Ic7AWBS8jGkZ33GFk qmsJF4GeIe1TIThxy1+2JgAGWWbxXQ4z+FjEoTMjmUbK32RtX4f6tW/gATEN52hWzKS6 0Ut1ocWGnkC3oCtiKP6h15MMql08S6zQOPM69kEdRX09yJPRaIW9hklihpFtFgImxsv+ /ZBA== X-Gm-Message-State: AOAM530/ZLCu4TmbwQzjSt3+CYCwtXRGZvXwnD/jx6X9Uk4CvEpsfwEy qB2QZ9BnD9Nq0FsmxzcQNW1nOEb2Ub7gm386 X-Google-Smtp-Source: ABdhPJzwOvTLazBZPSJKsjMWwkS/+c08OWJK8hkFYuOuyJ3RQTjE+5fr+AWDq+gvDLSF+3w2wI1A/A== X-Received: by 2002:a63:574b:: with SMTP id h11mr14885891pgm.25.1610750826381; Fri, 15 Jan 2021 14:47:06 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 11/21] exec: Add support for TARGET_TAGGED_ADDRESSES Date: Fri, 15 Jan 2021 12:46:35 -1000 Message-Id: <20210115224645.1196742-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:20 -0000 The AArch64 Linux ABI has always enabled TBI, but has historically required that pointer tags be removed before a syscall. This has changed in the lead-up to ARMv8.5-MTE, in a way that affects the ABI generically and not specifically to MTE. This patch allows the target to indicate that (1) there are tags and (2) whether or not they should be taken into account at the syscall level. Adjust g2h, guest_addr_valid, and guest_range_valid to ignore pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok in the arm64 kernel source. The prctl syscall is not not yet updated, so this change by itself has no visible effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e62f4fba00..1df9b93e59 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif +static inline abi_ptr untagged_addr(abi_ptr x) +{ +#ifdef TARGET_TAGGED_ADDRESSES + if (current_cpu) { + return cpu_untagged_addr(current_cpu, x); + } +#endif + return x; +} + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) +static inline void *g2h(abi_ulong x) +{ + return (void *)((uintptr_t)untagged_addr(x) + guest_base); +} static inline bool guest_addr_valid(abi_ulong x) { - return x <= GUEST_ADDR_MAX; + return untagged_addr(x) <= GUEST_ADDR_MAX; } static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { - return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; + return len - 1 <= GUEST_ADDR_MAX && + untagged_addr(start) <= GUEST_ADDR_MAX - len + 1; } #define h2g_valid(x) \ -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsK-0003pz-RQ for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsG-0003fx-If for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:20 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:34061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs6-0005GI-Mh for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:20 -0500 Received: by mail-pf1-x42c.google.com with SMTP id m6so6415572pfk.1 for ; Fri, 15 Jan 2021 14:47:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kevGJM1Q+4BI+TG/qeyrIdbD80I/diyx5FwIEqL89Lg=; b=yjl20JCzeSyY0d+TkDuN3wwMZiKpjLRYjZZFtN5FAQY0IP+krpQQkm7x9J+ZgBtnBK RxpY5TF6YB2r1Se761rLFzK0PUICPe21i+qUv9AywzvwvirYPO8ExUFEPfxAw2a2w4HX mO/gjZUUlb8YtnY/Q38ocaXymemjMP+7AjZqixWpccHwCTIowIWQtuWy1uje5RiDUknM hbariWoPORK3SyQIa7arfgicB8ao+WktrsL+r8bd8auzMwOoZVNKX9ojUP1zHkXoiRFM /cxDqFlj4W/eO72nLzxjNFhd02m1tPbI6X+C8nJnxnlQguPPZ6C+Q8xNuSw7iiwrP/VI LlSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kevGJM1Q+4BI+TG/qeyrIdbD80I/diyx5FwIEqL89Lg=; b=iMwZjOGHBBwchd2B894rY9crFEU71trtkt0RobSE2EV9MHXAOpz7BmYNA8+fmI5A2R bW5zIGgsThtu/l1RSOk/wH6OMxsT7QyHlqIg1vjbWVjK2M27ZNwyWYTj6Juj239N5Y25 u3T5MBQWIAr+Lo60lw54akM10AxWH0gzQ0m6FKpW5zUn/xvJcp48lK+bvt51N+QhnFrj 3KYe6cT2jT7fjiVKeEj2Dae+bouf4fEcYtBGiib72XNIVfzWpkepCC7CBwx7BX8HtV8d qbJ3t+CBVdnS5LNhytmGljZgARM55kAp1SJ2gkd/Ja8XdTvv7AoNbH1oWwowqLGMVWdq rcWQ== X-Gm-Message-State: AOAM530orWLRQ/gKwej7f/tQGtIgD2DnfY/Eksr7yXdvvh1Dr/48JhBK JQKrsnZBS/8oOTUraQtniYHppQ== X-Google-Smtp-Source: ABdhPJyV4SgVfvjZsXZSxCadhQf89wBQz68zzBFY4Y27oBJ+wKCss2UjY+1HDCkPRs7oVPN61VZeTQ== X-Received: by 2002:a63:ea01:: with SMTP id c1mr14823034pgi.138.1610750827934; Fri, 15 Jan 2021 14:47:07 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 12/21] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Fri, 15 Jan 2021 12:46:36 -1000 Message-Id: <20210115224645.1196742-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:21 -0000 This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 4 ++++ target/arm/cpu-param.h | 3 +++ target/arm/cpu.h | 23 +++++++++++++++++++++++ linux-user/syscall.c | 25 +++++++++++++++++++++++++ target/arm/cpu.c | 3 +++ 5 files changed, 58 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 3194e6b009..820601dfcc 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -30,4 +30,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6321385b46..f922aa0650 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f3bca73d98..6ddfd9ebe6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -712,6 +712,10 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + +#ifdef TARGET_TAGGED_ADDRESSES + target_ulong untagged_addr_mask; +#endif } CPUARMState; static inline void set_feature(CPUARMState *env, int feature) @@ -3556,6 +3560,25 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) */ #define PAGE_BTI PAGE_TARGET_1 +#ifdef TARGET_TAGGED_ADDRESSES +/** + * cpu_untagged_addr: + * @cs: CPU context + * @x: tagged address + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + */ +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) +{ + ARMCPU *cpu = ARM_CPU(cs); + return x & cpu->env.untagged_addr_mask; +} +#endif + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/syscall.c b/linux-user/syscall.c index bec2ab7769..ebb4e2898c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10948,6 +10948,31 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env = cpu_env; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + env->untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE + ? MAKE_64BIT_MASK(0, 56) : -1); + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret = 0; + CPUARMState *env = cpu_env; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (env->untagged_addr_mask != -1) { + ret |= TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8387e94b94..abc0affd00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,6 +208,9 @@ static void arm_cpu_reset(DeviceState *dev) * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); +# ifdef TARGET_TAGGED_ADDRESSES + env->untagged_addr_mask = -1; +# endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsL-0003sv-WA for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsK-0003oh-9U for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:24 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:42669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsB-0005H3-Hm for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:23 -0500 Received: by mail-pf1-x42d.google.com with SMTP id h10so6402964pfo.9 for ; Fri, 15 Jan 2021 14:47:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0M+ib82Q9NUsY8Zir/mvOr8pifWIKMIlNlMsQviVw94=; b=bvYoZzrUkQF3jvfLh8Vq77cIFtMUsoVGfyRpQtnQ42H/oMcy7izIfTvfHYhUXnmbJ5 l/mUBjeAfRXpEmC/BZ14Xqk9FUfEGY/N1g7DqZfaQorz5EcGkUuhdmX1Dfw0H2HVfTo5 Cn66q2nzdpIWujmYUc8BaTW9sJip9HZt2juvh2K7K54OPpDJYBuozVX7opcd2Y8PDkRC YTfsklVWJimCl3oFPU0XpnI4M4r5uY1VXuU5Sp8FC4+3k/hr4ejxmpzdEebk3S0edNSH 6sN0zuxqjKs9AR+Q6UkmG3ZzD57qvopzs+arXjNCmkv7UueoG9BkchYeQJC2LvGWf4UB aCXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0M+ib82Q9NUsY8Zir/mvOr8pifWIKMIlNlMsQviVw94=; b=pJOdZQ3W7pmlXxPGkBrXA+JT+WiOK1LVjm4NR+xm/uJHGLb54r8KSfD8kTXXxgc5iQ NJdjqXX+EsJJTObyJrW71cIDNGXAqrJ/iTd44gjESyRWSvdIE7pPUxLsCt4rGH0JjpG+ NH7SCFFrNJOh1dnnnXhJ5QFYGG4t0IgpSToGi2kn/a7GznukmuZfjfI0Y5NTqrG9DMUH Rz+VnZbFwKdsK1kHqsvZkS76chLJIlTxPTw3LiIzDPwzDBBivpFPD18wUVgwwnbXR2D3 73KG1L6GfJmaWIsTs9F/iU/UoawJxtYR4KX89ztw7oB+5AEhUp/2XKWniP73OwxeYkyB nbtg== X-Gm-Message-State: AOAM533i2ogMoRbj7OoVtbfO9tciKeJtXJpRPpGSVy/F/Tz+uVCAdjgt k93eOVFcMT4rCd2J8kfKOICZiA== X-Google-Smtp-Source: ABdhPJwvwxSmRRDNQZC74+OU5v9v/FpSewVFy9+aTH7hlGklYVpNXLikdI/1Kk7JKzZ0aq9uXqLsXA== X-Received: by 2002:a65:6116:: with SMTP id z22mr15091532pgu.264.1610750832944; Fri, 15 Jan 2021 14:47:12 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 15/21] target/arm: Split out syndrome.h from internals.h Date: Fri, 15 Jan 2021 12:46:39 -1000 Message-Id: <20210115224645.1196742-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:24 -0000 Move everything related to syndromes to a new file, which can be shared with linux-user. Signed-off-by: Richard Henderson --- target/arm/internals.h | 245 +----------------------------------- target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 244 deletions(-) create mode 100644 target/arm/syndrome.h diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..1e60c0e0e8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H #include "hw/registerfields.h" +#include "syndrome.h" /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -256,250 +257,6 @@ static inline bool extended_addresses_enabled(CPUARMState *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); } -/* Valid Syndrome Register EC field values */ -enum arm_exception_class { - EC_UNCATEGORIZED = 0x00, - EC_WFX_TRAP = 0x01, - EC_CP15RTTRAP = 0x03, - EC_CP15RRTTRAP = 0x04, - EC_CP14RTTRAP = 0x05, - EC_CP14DTTRAP = 0x06, - EC_ADVSIMDFPACCESSTRAP = 0x07, - EC_FPIDTRAP = 0x08, - EC_PACTRAP = 0x09, - EC_CP14RRTTRAP = 0x0c, - EC_BTITRAP = 0x0d, - EC_ILLEGALSTATE = 0x0e, - EC_AA32_SVC = 0x11, - EC_AA32_HVC = 0x12, - EC_AA32_SMC = 0x13, - EC_AA64_SVC = 0x15, - EC_AA64_HVC = 0x16, - EC_AA64_SMC = 0x17, - EC_SYSTEMREGISTERTRAP = 0x18, - EC_SVEACCESSTRAP = 0x19, - EC_INSNABORT = 0x20, - EC_INSNABORT_SAME_EL = 0x21, - EC_PCALIGNMENT = 0x22, - EC_DATAABORT = 0x24, - EC_DATAABORT_SAME_EL = 0x25, - EC_SPALIGNMENT = 0x26, - EC_AA32_FPTRAP = 0x28, - EC_AA64_FPTRAP = 0x2c, - EC_SERROR = 0x2f, - EC_BREAKPOINT = 0x30, - EC_BREAKPOINT_SAME_EL = 0x31, - EC_SOFTWARESTEP = 0x32, - EC_SOFTWARESTEP_SAME_EL = 0x33, - EC_WATCHPOINT = 0x34, - EC_WATCHPOINT_SAME_EL = 0x35, - EC_AA32_BKPT = 0x38, - EC_VECTORCATCH = 0x3a, - EC_AA64_BKPT = 0x3c, -}; - -#define ARM_EL_EC_SHIFT 26 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -static inline uint32_t syn_get_ec(uint32_t syn) -{ - return syn >> ARM_EL_EC_SHIFT; -} - -/* Utility functions for constructing various kinds of syndrome value. - * Note that in general we follow the AArch64 syndrome values; in a - * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, and we fix this up when populating HSR in - * arm_cpu_do_interrupt_aarch32_hyp(). - * The exception is FP/SIMD access traps -- these report extra information - * when taking an exception to AArch32. For those we include the extra coproc - * and TA fields, and mask them out when taking the exception to AArch64. - */ -static inline uint32_t syn_uncategorized(void) -{ - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_svc(uint32_t imm16) -{ - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_hvc(uint32_t imm16) -{ - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_smc(uint32_t imm16) -{ - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa32_hvc(uint32_t imm16) -{ - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_smc(void) -{ - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) -{ - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, - int crn, int crm, int rt, - int isread) -{ - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; -} - -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 SIMD trap: TA == 1 coproc == 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); -} - -static inline uint32_t syn_sve_access_trap(void) -{ - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_pactrap(void) -{ - return EC_PACTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_btitrap(int btype) -{ - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; -} - -static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) -{ - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; -} - -static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, - int ea, int cm, int s1ptw, - int wnr, int fsc) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; -} - -static inline uint32_t syn_data_abort_with_iss(int same_el, - int sas, int sse, int srt, - int sf, int ar, - int ea, int cm, int s1ptw, - int wnr, int fsc, - bool is_16bit) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; -} - -static inline uint32_t syn_swstep(int same_el, int isv, int ex) -{ - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; -} - -static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) -{ - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; -} - -static inline uint32_t syn_breakpoint(int same_el) -{ - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | 0x22; -} - -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) -{ - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; -} - /* Update a QEMU watchpoint based on the information the guest has set in the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h new file mode 100644 index 0000000000..39a31260f2 --- /dev/null +++ b/target/arm/syndrome.h @@ -0,0 +1,273 @@ +/* + * QEMU ARM CPU -- syndrome functions and types + * + * Copyright (c) 2014 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + * + * This header defines functions, types, etc which need to be shared + * between different source files within target/arm/ but which are + * private to it and not required by the rest of QEMU. + */ + +#ifndef TARGET_ARM_SYNDROME_H +#define TARGET_ARM_SYNDROME_H + +/* Valid Syndrome Register EC field values */ +enum arm_exception_class { + EC_UNCATEGORIZED = 0x00, + EC_WFX_TRAP = 0x01, + EC_CP15RTTRAP = 0x03, + EC_CP15RRTTRAP = 0x04, + EC_CP14RTTRAP = 0x05, + EC_CP14DTTRAP = 0x06, + EC_ADVSIMDFPACCESSTRAP = 0x07, + EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, + EC_CP14RRTTRAP = 0x0c, + EC_BTITRAP = 0x0d, + EC_ILLEGALSTATE = 0x0e, + EC_AA32_SVC = 0x11, + EC_AA32_HVC = 0x12, + EC_AA32_SMC = 0x13, + EC_AA64_SVC = 0x15, + EC_AA64_HVC = 0x16, + EC_AA64_SMC = 0x17, + EC_SYSTEMREGISTERTRAP = 0x18, + EC_SVEACCESSTRAP = 0x19, + EC_INSNABORT = 0x20, + EC_INSNABORT_SAME_EL = 0x21, + EC_PCALIGNMENT = 0x22, + EC_DATAABORT = 0x24, + EC_DATAABORT_SAME_EL = 0x25, + EC_SPALIGNMENT = 0x26, + EC_AA32_FPTRAP = 0x28, + EC_AA64_FPTRAP = 0x2c, + EC_SERROR = 0x2f, + EC_BREAKPOINT = 0x30, + EC_BREAKPOINT_SAME_EL = 0x31, + EC_SOFTWARESTEP = 0x32, + EC_SOFTWARESTEP_SAME_EL = 0x33, + EC_WATCHPOINT = 0x34, + EC_WATCHPOINT_SAME_EL = 0x35, + EC_AA32_BKPT = 0x38, + EC_VECTORCATCH = 0x3a, + EC_AA64_BKPT = 0x3c, +}; + +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + +/* + * Utility functions for constructing various kinds of syndrome value. + * Note that in general we follow the AArch64 syndrome values; in a + * few cases the value in HSR for exceptions taken to AArch32 Hyp + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra coproc + * and TA fields, and mask them out when taking the exception to AArch64. + */ +static inline uint32_t syn_uncategorized(void) +{ + return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_svc(uint32_t imm16) +{ + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa32_hvc(uint32_t imm16) +{ + return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_smc(void) +{ + return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +{ + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, + int crn, int crm, int rt, + int isread) +{ + return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL + | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) + | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 SIMD trap: TA == 1 coproc == 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); +} + +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + +static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, + int ea, int cm, int s1ptw, + int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + +static inline uint32_t syn_data_abort_with_iss(int same_el, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, + int wnr, int fsc, + bool is_16bit) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14) + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + +static inline uint32_t syn_swstep(int same_el, int isv, int ex) +{ + return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; +} + +static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) +{ + return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; +} + +static inline uint32_t syn_breakpoint(int same_el) +{ + return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | 0x22; +} + +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +{ + return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | + (cv << 24) | (cond << 20) | ti; +} + +#endif /* TARGET_ARM_SYNDROME_H */ -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsM-0003tb-7K for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsK-0003q3-RQ for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:24 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:34577) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsD-0005If-Ky for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:24 -0500 Received: by mail-pj1-x102b.google.com with SMTP id my11so6129215pjb.1 for ; Fri, 15 Jan 2021 14:47:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6xhR+Wss/1TBEEfYwI3TvMrUfFA269smX1ho0M9IxOI=; b=JnQ8QGg4P0SWQVCDznCnfTfLo5HbgayFH1jkcgJ7cs43998FeIl9D0N8Wt7zS+RJZU d9YeASIk+w2OuLNvplylox7MKfrpxkPhmAGh9YOfWfLe3QjD7GxsVBexQSCjP50XFcIy BdYw3KVr1qb7IXePM4vP+aaxbicDjYyBXw0FPfGC1b+TGZRcXkHLZ/8omVtyBIEn2LrK eriD7Xwm/ffD9/M6nS8blO1+qQJS5IjEzQD3yaGs6zGtNca1GjOaCNATIp6qM22tSL5u 2w1iZae0p2+c4CL36BVFiy1hBoAex7Z/SdD+oVXXg4fUv91i+NKizxWC1nE9IRKP9OYT A6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6xhR+Wss/1TBEEfYwI3TvMrUfFA269smX1ho0M9IxOI=; b=FniKClQ/ZjV+lHiW26xA6WZJszktjSXEXnDISL81n8j1knyCAI5tdu1flX6ThISqeN VIqKdU1KJ7KnplPCkaLrtu/WfumUqfpFAkOnsdfUlyIMmM85SGLnJRhVJken8ROkSiu8 hh2Tu6mpYA5DReQrXj7PbEsoJUpuMgAbBBpdG9d8KONNJinnnkvU0fQzkLIdguE2JvOp FxbGjfMzobw+3Ovt+sTtB6AmTFxUckPhOlpuA6AIrsAOL7x0IcwtkCdSsop4oAoAunwf IoCPBhm711dbWmOjo9352CutUmkZHhkHMIEIsdwPuTgqdUj+jmcfCyHOgp6TsoNBF41u x7yw== X-Gm-Message-State: AOAM531jl3wpoJIG2aDHg9aS0Vy9aOXdQ9qAxrOrdcty2AjxxauedS9k +pHTJxjqt8sIsIs0rA1FMaKD78mIk2X6X+yL X-Google-Smtp-Source: ABdhPJyHxlLsDHrcXSEHs+xK1UucLeagqRoo3BmkzQWOZmqsMiQgst1c16HGVb+EAYBkfanAg0Tg7Q== X-Received: by 2002:a17:90a:ae13:: with SMTP id t19mr13247354pjq.52.1610750836340; Fri, 15 Jan 2021 14:47:16 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 17/21] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault Date: Fri, 15 Jan 2021 12:46:41 -1000 Message-Id: <20210115224645.1196742-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:25 -0000 Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index ddd73169f0..777fb667fe 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 7811440c68..6867f0db2b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -133,6 +133,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code = TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code = TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsR-00040A-KS for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsI-0003jx-5I for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:22 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:32828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0Xs8-0005Gi-Pz for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:21 -0500 Received: by mail-pg1-x52c.google.com with SMTP id n25so6958975pgb.0 for ; Fri, 15 Jan 2021 14:47:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Aw5WXq5wBceHp2TEFV1G5r+xP2Xi/95Oor9t7natYrU=; b=TRNBEliC4lszDOEMK8EhLcK6PoSmSf2epLNZnh2HMN0KHLfnhTYqIrg5n19LcnHcYO X5LWGeai2dFNEa0VW48kdSGco8lprPDs5g05WUS21cj7bkcbTQX5OoWGeT9YmP0sxTbR dqsZG/dpbjyGqD5/feVFHNc1x1m0h7q9SxvgcTaFuDh0BGkoJB4Y+n3uhjJgqXP5k6AI YkysG9Ymu7WKJDd6g+xNLrabt5lN0jKZurlA0IcO/aJiUGOidwv0cfC+7dVAsZLKvJu6 z2xqcebGgWceNyEVlk7sgy5OSpozg7kH0XODl8pMqniBCKUwu0pKKyAV4JNtSGRhR+Ta OUcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aw5WXq5wBceHp2TEFV1G5r+xP2Xi/95Oor9t7natYrU=; b=FIfFWOviUE7oTmPStvYJw11B/q033PR6bwRbCTjgzOUuKAjqefJlifDZAw1a0fDQKl UAoVUTyrVhGTNvbRhVuXSx/lu17hB9MHdhASp1bT0gCLLQ2r8YS60Y/mAdcqCcUcK83n D59zOQTFGaAkqN8RhsIh4vnfC1kMC9D+Vz8lxOZVWYnXNDx+HsvU7KpzWFyb2ComuCbt rjuYeJ02sKFqfzDrvP9MJ123jgdldepNg0VjMJ/K/94vNWcOF0hKWAxWh+MxODSGieGS gvlglaw/M/vY/1cLA3ZemJXqqIazByB3afK+3Pvg9iGO1q+5rRf6K8WCA3Ld7MG5Yq3g I4sw== X-Gm-Message-State: AOAM532IWeDgWkHmoqPc8lnhMA5UgnoYM8O8j11nt1lu1PJmhxaTyec3 V8AkveQifB5KMNHqn+JE6zIVqg== X-Google-Smtp-Source: ABdhPJydAp/MPXTE4YA67A2AKhGy0uZJVWIbn5b0gsMOddc1djEHISEqIPH4zASAdVty4FpJPVHDNg== X-Received: by 2002:a65:6152:: with SMTP id o18mr15053560pgv.392.1610750831231; Fri, 15 Jan 2021 14:47:11 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 14/21] linux-user/aarch64: Implement PROT_MTE Date: Fri, 15 Jan 2021 12:46:38 -1000 Message-Id: <20210115224645.1196742-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:22 -0000 Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2. Otherwise this does not yet have effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Do not overlap PAGE_TARGET_2 with PAGE_RESERVED. --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + target/arm/cpu.h | 1 + linux-user/mmap.c | 22 ++++++++++++++-------- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c52180e8e6..b2a72f70ec 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -284,6 +284,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0200 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index a00bfc2647..0d6bb1ff8b 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1311,6 +1311,7 @@ struct target_winsize { #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif /* Common */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6ddfd9ebe6..e14c9a6277 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3559,6 +3559,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ #define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 7fb4c628e1..34bd114f97 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,24 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) | (prot & PROT_EXEC ? PROT_READ : 0); #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu = ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |= TARGET_PROT_BTI; page_flags |= PAGE_BTI; } + /* Similarly for the PROT_MTE bit. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |= TARGET_PROT_MTE; + page_flags |= PAGE_MTE; + } } #endif -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsR-00040q-Tn for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsK-0003qJ-VB for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:25 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:36603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsD-0005HE-IY for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:24 -0500 Received: by mail-pf1-x434.google.com with SMTP id b3so6421318pft.3 for ; Fri, 15 Jan 2021 14:47:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ag2kKkF2C6qi/FIsLVctK/0CDxQoX8dZZ8rQ2H49Ggg=; b=RMZ8WirJTLlQAkxfN7eeHO/oagdgYHAAbW6NEu+iTKJ76HXJ89l0L+Oruiil3w0L6o 6uFT0xML2KItKLRleptMbWNVd2Q6fFlbPiiz7/bcTtV64YD2gQUqW26ucALoa37oAlAg CD2JAZxA3od2hCxjVkaWKEGt/Rb5JBXwbms6zfDMpNYNYPaJIF5MZkdGHDzWTDvfETpw 0MJ/FIm3AZdjjoZWHn3DlAgi89IEOSN/H3kdS925nP0HiDWcz5GI0BHKl+dc47cUhtA+ nzZ/+IlH81aF8aBoAOOksmo5k0lEyfVLhNPxU9BuwbVTpmidYWUEGv/zRnOumIW2tXX+ rojA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ag2kKkF2C6qi/FIsLVctK/0CDxQoX8dZZ8rQ2H49Ggg=; b=LUO3qII1YKU7T9oSdbzvFIF2NKdzpOCclwtXTSg1trhyFUzrOYZMXZi3zrzRuAWJl7 9OlphA7SVaRqSRAojsssNhJdhodbK6NEsFLCbVQoKauZ8C8G+NiSzfGXvEsdNKy6pKat 9bV7Gq4ENx7+KvyfBQw40BBXsa3GiC4dseKCV3tUCOSgg7eoyYMrdx7zDS5O9HirmaoX opr6iaCQcBdny6r8OId9i2RXiAsX/nDQrFObmyk+DCMI9lrdgFL8lqn2SMTmYEDotkJm L446Gs46ym9Lj/SpGCpPBZgpV3IlzGJ3QZm1sABlP0QETPHFGGy4KigkXx5qxdoTXU1t 7oOQ== X-Gm-Message-State: AOAM531UMrKxMTsQ0vMU3VasBEX0JqFlFoITwxZ0+RTwg1Exq/H82OKi ERQH9AeHd/vccJ8dzqaOET1Ka6H5PeayFLYq X-Google-Smtp-Source: ABdhPJywB2cx8PPDH52lHqX7oPN8cbRCZQm2hK5rCFT5isUvNFb+bVbfShVughr0HhtEar2UuMNm7Q== X-Received: by 2002:a62:3386:0:b029:1ae:8580:99da with SMTP id z128-20020a6233860000b02901ae858099damr14821902pfz.61.1610750834718; Fri, 15 Jan 2021 14:47:14 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 16/21] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Fri, 15 Jan 2021 12:46:40 -1000 Message-Id: <20210115224645.1196742-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:25 -0000 A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Signed-off-by: Richard Henderson --- v3: Use syndrome.h, arm_deliver_fault. --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..7811440c68 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -75,7 +76,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; @@ -116,9 +117,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ + ec = syn_get_ec(env->exception.syndrome); + assert(ec == EC_DATAABORT || ec == EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code = TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b35dc8a011..31015749fd 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -151,21 +151,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress = address; - if (access_type == MMU_INST_FETCH) { - cs->exception_index = EXCP_PREFETCH_ABORT; + int flags = page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type = ARMFault_Permission; } else { - cs->exception_index = EXCP_DATA_ABORT; + fi.type = ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs = {}; - ARMMMUFaultInfo fi = {}; ARMCacheAttrs cacheattrs = {}; /* -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsV-00041x-KN for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsJ-0003nv-UT for qemu-arm@nongnu.org; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 13/21] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Fri, 15 Jan 2021 12:46:37 -1000 Message-Id: <20210115224645.1196742-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:24 -0000 These prctl fields are required for the function of MTE. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 44 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 820601dfcc..76f6c3391d 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -33,5 +33,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ebb4e2898c..0316497636 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10952,10 +10952,46 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= TARGET_PR_MTE_TCF_MASK; + valid_mask |= TARGET_PR_MTE_TAG_MASK; + } if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } + env->untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE ? MAKE_64BIT_MASK(0, 56) : -1); return 0; @@ -10964,6 +11000,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { abi_long ret = 0; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -10971,6 +11008,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, if (env->untagged_addr_mask != -1) { ret |= TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xsa-00045M-3F for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsQ-0003xr-GK for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:30 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:44764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsK-0005MW-EB for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:28 -0500 Received: by mail-pl1-x629.google.com with SMTP id r4so5433714pls.11 for ; Fri, 15 Jan 2021 14:47:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ed3dMxH1EDG+4PBQ/N+mQ4V0QrBrfta+sRgZmd+re9s=; b=NWG1XoMCLlY2/0IX+2jKgi7AjabxEF8DFhqzqZND57S+BDrcPB7oeix2aoQoUbJEQI pKT1aAJxESU7hsQIsEh34PBX2At59iRltsJPV2/T0WiTIKmoXlVBDOD2kfdQ2M4I6Xre iBzBeA+Ob2msjt5HgQFbCBEN/2VsthO2lE440LJ9St1EwYB1PEjapjtNhZBe/D3/xOA4 pbNbTOtFbkfD95P7DYgC57iwMjSJYrp5kKym2ttjG8kEFkT3OWSGj7nu83FyNodEQMA2 q1ob6MYEvLwalQhchBjeW5smngKI+UppF/Pi7fhubp+GIsNZw2Uf7YJmQ2NaxhuUslBB KqqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ed3dMxH1EDG+4PBQ/N+mQ4V0QrBrfta+sRgZmd+re9s=; b=huBo7mrPo8wdvPcoisthou8VhLU3J9iGmvwnLKEpnQX4GylBWqBcVS5iFnAnMW1eB5 lroVkRhUqLy0QgjqMJsFN9iUBN680p44afRPqtyC5STF9TOs/dWQv/fZXgWd06wtTRaA JvwxFoKHY/PH9ko9gv42eYV1Y6gYbKCk+QibgFiw7uyci1oaBlT4Y9sbQBPBBTtesVCT vDFSkbmbheWr5v/47f2RFw1uSwXtyfsswFC6sti+Uy42J5WTO7H+POQSNIyB5GkQxt4F 5UNtyh7R7yNfAGtjbyaJHWeHyVkaoCgwXtM9611RdVfQb3W8faCgGh+ukrS8ED5jaIaO mC3Q== X-Gm-Message-State: AOAM531VxMTz0kbOvEiuhJW3ce7H1eH6X/48Kj9hiQEo9SiOWf4uyRAH SD/RDl9GH7feobiMohniHHwnyA== X-Google-Smtp-Source: ABdhPJxMIqs0tgmhhfpSIs7D0vFJZyAoLAlNn4JvhdTBfQZaf6KRkEQeM6JJVaJB/9rxlSJh743zvA== X-Received: by 2002:a17:902:f54e:b029:de:19f9:c45f with SMTP id h14-20020a170902f54eb02900de19f9c45fmr14657803plf.48.1610750843012; Fri, 15 Jan 2021 14:47:23 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 21/21] tests/tcg/aarch64: Add mte smoke tests Date: Fri, 15 Jan 2021 12:46:45 -1000 Message-Id: <20210115224645.1196742-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:30 -0000 Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 53 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 25 +++++++++++++++ tests/tcg/aarch64/mte-2.c | 42 ++++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 47 +++++++++++++++++++++++++++ tests/tcg/aarch64/mte-4.c | 42 ++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++++ tests/tcg/configure.sh | 4 +++ 7 files changed, 219 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 0000000000..038d33ab6c --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,53 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r = prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_mem(size_t size) +{ + void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p == MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..02bc978482 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,25 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 = alloc_mte_mem(sizeof(*p0)); + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..a05f5183cb --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,42 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 = 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 0000000000..0d08b477cc --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,47 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + */ + *p2 = 0; + while (1); +} diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c new file mode 100644 index 0000000000..52aa6fae65 --- /dev/null +++ b/tests/tcg/aarch64/mte-4.c @@ -0,0 +1,42 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include "mte.h" + +void __attribute__((noinline)) tagset(void *p, size_t size) +{ + size_t i; + for (i = 0; i < size; i += 16) { + asm("stg %0, [%0]" : : "r"(p + i)); + } +} + +void __attribute__((noinline)) tagcheck(void *p, size_t size) +{ + size_t i; + void *c; + + for (i = 0; i < size; i += 16) { + asm("ldg %0, [%1]" : "=r"(c) : "r"(p + i), "0"(p)); + assert(c == p); + } +} + +int main(int ac, char **av) +{ + size_t size = getpagesize() * 4; + long excl = 1; + int *p0, *p1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(size); + + /* Tag the pointer. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + + tagset(p1, size); + tagcheck(p1, size); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index d7d33e293c..bf53ad0087 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -35,6 +35,12 @@ endif # bti-2 tests PROT_BTI, so no special compiler support required. AARCH64_TESTS += bti-2 +# MTE Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 +mte-%: CFLAGS += -march=armv8.5-a+memtag +endif + # Semihosting smoke test for linux-user AARCH64_TESTS += semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f2..ba8ac9a93e 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -244,6 +244,10 @@ for target in $target_list; do -mbranch-protection=standard -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=armv8.5-a+memtag -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak + fi ;; esac -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xsb-00046B-DF for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsO-0003xc-Ug for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:30 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:46260) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsI-0005L9-S7 for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:28 -0500 Received: by mail-pl1-x632.google.com with SMTP id u11so1155700plg.13 for ; Fri, 15 Jan 2021 14:47:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NVTYVf4zlgciMSRy3E1kBUuwxIM3r8rkk5rLkXytMCY=; b=OLeFUxgqe2FDpmYwh92ezhGorgX6wh3bNBwRjXWeEmTrHXU0zjxMmP+wYf3OHzu/Rl AAwAJ7LksE7lsf/cOKZWZx3O8rNO9n8gWsFiFx0Y7A/tsh7JBH1i0UlaFInjQTaXQakV L2EB7jpeyrs41u1J0t8ft+IutoXl3q0so9VzpKXrFiARRhCdsny4rDLCiBLrOFFaclN1 VDWAVRvop6xxFXHDgJFIdK4OSAHwY23DEkliXTI54cEpGNAaQAxg0ECQzbvkkG28jqvo WH0ZDzWLzxfqv7kX8hTeohF7V9XmZQ/xLUUKo+c99exdddajS4FNUaK2wu5FTaDLlCHr N9IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NVTYVf4zlgciMSRy3E1kBUuwxIM3r8rkk5rLkXytMCY=; b=EgWJFsdiGxNA/JceaerTDphMPXllkZzQVeuguG8kywuBwm7058MNAiA0HwHARPp372 d+3JtBrTjqGv+2SLZwzZaN/pO66RlUG8bT+3CCIaTux1iYSZJK4odyJvyNKivFpMvvy0 c/QfcoD4XoKJg+PckZ2gUseJkUMQoZ0I1O4ANr9lQHxXkoHivMML3QWUO+P5OSWAq3d0 Tb4fF/nYfGbAQdT2hxLnea6Y/6uFYcbbp5/unuVcDLeFlO0WMJPTe25nUAunqGsypzne sdWcWE98u47FLYicig1A+RsrCOlGt35gxxJYDP4uqoK9e45nTD48kZMbJ4lyEbGv2ufP 5b3w== X-Gm-Message-State: AOAM532aL3wyLMdF7QmOMaQ2cAsmhzgfCG9C5oBsqIKuMGlmJexayiW+ H0N66stNwKtq4wpsahQUYkTfUw== X-Google-Smtp-Source: ABdhPJwbkoKSF44+p4nnsIgjWU4uiwueypBZfIyF3VKb7UaQhH6DD8fjmaSF6GP1TOWPLYY74dRBBg== X-Received: by 2002:a17:90b:8d7:: with SMTP id ds23mr5581444pjb.116.1610750841311; Fri, 15 Jan 2021 14:47:21 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 20/21] target/arm: Enable MTE for user-only Date: Fri, 15 Jan 2021 12:46:44 -1000 Message-Id: <20210115224645.1196742-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:30 -0000 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index abc0affd00..5e613a747a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,6 +208,22 @@ static void arm_cpu_reset(DeviceState *dev) * Do not modify this without other changes. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl = 0. + * + * Set RRND, so that helper_irg() will generate a seed later. + * Here in cpu_reset(), the crypto subsystem has not yet been + * initialized. + */ + env->cp15.gcr_el1 = 0x1ffff; + } + # ifdef TARGET_TAGGED_ADDRESSES env->untagged_addr_mask = -1; # endif -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0Xsd-00047P-VU for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsO-0003xd-Uh for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:30 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:51233) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsF-0005JG-E7 for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:28 -0500 Received: by mail-pj1-x102f.google.com with SMTP id y12so5897187pji.1 for ; Fri, 15 Jan 2021 14:47:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d+pOvzjLdVYp+MmYo9tDbbGKAe+YDrG7n/EDarHxK9g=; b=x0XQUAUsc7bB+vP4BeTYRil5LWXgaCzg/miumn33qYnIpbwR0B06YQ3tHmXqOHdGKv EUecuDPif9BQWgX6TNmlmLfRrfR+GDSEjdKJNgUgLKM6mrAg6zhutkLlzqJ206o+8G29 Q7b4Tq0QPTNei1l1FyuVR/IP9cZdfZanRyfaX9LpCb829mKAtH/H5RmxFbEX+I+Kd8RD trTx/5L1rY9vvjRQ36HN5LRVkaLclWbm/3qJt1Afg06vzZoLgMFTqKqsDs3dGtHiq9r6 PF12XeazIhUAiLlkzVXDTwRFDZX4bg+oFylqc3gi//25pDh0Z7TvqFjErhPyRyk9BvML eWcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d+pOvzjLdVYp+MmYo9tDbbGKAe+YDrG7n/EDarHxK9g=; b=AQw1Xb0xmd8Z7URo66+nZUu/sPr5o3DktSJgeMuFXEfd1BMBXFxFhPnV24XOOdWEDl UDyoCG/FH9Gg+ObmvU1raM+6R4PWcAxfszSdPXw8o6EnHPJK5Prwm6lSuWeWcQs5W+u5 CcueYPvP4x5OsnTQbqxzzQyu1wd9krRGXcDroaPdrH7GRLcCwhS1FdBLQLmEyxV3YicR BfuSQ8OXnqu2FZ7iiKFdkFphLkkhM6WJiRFsV5lgIEqMc/9sWfdhYORqK/E352hFvAnb TzSvzFDUXnJlGjj+vCXULcBTWTwi8KAXhGGzDW7uuuKx720AGdZVQvcApnpxGjZ27yz8 C2uQ== X-Gm-Message-State: AOAM5310LPsTxdm+ReUfYPyHLPpaqYmLnHk66MVRqHPnTJo2gK543Vsc KZyxJ2ViEvUqQhr5WzbgAGyxMQ== X-Google-Smtp-Source: ABdhPJyIegFssN9gj9aZVacE2wYVAV0rck4ogiGU7LY3JSdPqG7CpQyrZpV48j2v9B5p5RRIBGx5RA== X-Received: by 2002:a17:90a:5318:: with SMTP id x24mr13186645pjh.226.1610750838077; Fri, 15 Jan 2021 14:47:18 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Fri, 15 Jan 2021 12:46:42 -1000 Message-Id: <20210115224645.1196742-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:30 -0000 Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 34 +++++++++++++++++++++--------- target/arm/mte_helper.c | 10 +++++++++ 3 files changed, 35 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index 777fb667fe..18013e1b23 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 6867f0db2b..6160a401bd 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -72,6 +72,21 @@ put_user_u16(__x, (gaddr)); \ }) +static bool check_mte_async_fault(CPUARMState *env, target_siginfo_t *info) +{ + if (likely(env->cp15.tfsr_el[0] == 0)) { + return false; + } + + env->cp15.tfsr_el[0] = 0; + info->si_signo = TARGET_SIGSEGV; + info->si_errno = 0; + info->_sifields._sigfault._addr = 0; + info->si_code = TARGET_SEGV_MTEAERR; + queue_signal(env, info->si_signo, QEMU_SI_FAULT, info); + return true; +} + /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { @@ -88,15 +103,13 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: - ret = do_syscall(env, - env->xregs[8], - env->xregs[0], - env->xregs[1], - env->xregs[2], - env->xregs[3], - env->xregs[4], - env->xregs[5], - 0, 0); + if (check_mte_async_fault(env, &info)) { + ret = -TARGET_ERESTARTSYS; + } else { + ret = do_syscall(env, env->xregs[8], env->xregs[0], + env->xregs[1], env->xregs[2], env->xregs[3], + env->xregs[4], env->xregs[5], 0, 0); + } if (ret == -TARGET_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { @@ -104,7 +117,8 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ + /* Just indicate that signals should be handled asap. */ + check_mte_async_fault(env, &info); break; case EXCP_UDEF: info.si_signo = TARGET_SIGILL; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df..d55f8d1e1e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, select = 0; } env->cp15.tfsr_el[el] |= 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; default: -- 2.25.1 From MAILER-DAEMON Fri Jan 15 17:47:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0XsX-00042v-EX for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 17:47:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0XsM-0003uB-EH for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:26 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:37921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0XsH-0005Kb-2R for qemu-arm@nongnu.org; Fri, 15 Jan 2021 17:47:26 -0500 Received: by mail-pj1-x102f.google.com with SMTP id x20so672156pjh.3 for ; Fri, 15 Jan 2021 14:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e1dRDYwqVg1e/BMj2WtrxEnKh4CuzKOtBUsWpusVo1U=; b=rIS9TFyK5NpMdRM+0ahyHi12GiHnDA7/L7VG4hDa8+RhC+6W/mOZ3zcgdrGjszWdXh h9j0UQn7wvuIl18f4TSY6gAfYxDwGftlZD1nluTKZMWOW7zJ5KfyZvNUMOPZhWV7Jsee g2XqRUaV9x/Ef/C9Nv+NqzpRF+F6Xn7mMQ4tDNCf1YDV3i9gD14/wFV4K7jSrFQgj8cw s790MCDblWSLhTXn1R82YFi9FsCF3rqvNv4F/blJcaYl8MBhPn9PDXewmxWS+2M6ybIq PkmUL0eThI3ZlUjZY8XBFJNpzwkxU4lhoRPd5J0ZPlRH8C/JgtuLX54tY9XVkOoznRrD IEyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e1dRDYwqVg1e/BMj2WtrxEnKh4CuzKOtBUsWpusVo1U=; b=tCaHG+v3mNAb38Ivnc5HUuT6neYSEOrHDg2N2hXZs5NTJSJLysS742HRf4dpPkKyU8 xEPV0B18+aPvf6+4HuoN0S9tHt0Uoe4dw4jEhmLiIsBoZVn97Purn0904qRbfoYBNEyH flCu8V3ORLVAAkQIATkZCNm72tdPdW1qFfHZu+s/IV3026appU/fFGr2ixwaAg5JJB/K 8tAu51S9ps9ObCIdnghn4xHnJAeSNwUXORLz98u0YCanRPhnO61IccNM5u150ZCh6dNo 9oonahsK7cpo2vB6jV2+NKHjQbybzI/noYDN/r6YkXyOWOuITbKfCaVL8HFhsowy4rlG TLkA== X-Gm-Message-State: AOAM530QdCsz5vElX3vwyPocBoDvsqZFaiguR+Wlq//J/aUNfBzft01K OhSUxopc+SHvggOLsrbwKE/JK75IXq1B1jBE X-Google-Smtp-Source: ABdhPJwuj7hIwSs9bgKHluMX/wctZ0NkzG3nqZ7sKkhaDIdqqjsdVoHLqzZK97zkOh2NqRLmpWL5HA== X-Received: by 2002:a17:90a:5b18:: with SMTP id o24mr13093339pji.120.1610750839784; Fri, 15 Jan 2021 14:47:19 -0800 (PST) Received: from localhost.localdomain (rrcs-173-197-107-21.west.biz.rr.com. [173.197.107.21]) by smtp.gmail.com with ESMTPSA id s13sm9521700pfd.99.2021.01.15.14.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 14:47:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 19/21] target/arm: Add allocation tag storage for user mode Date: Fri, 15 Jan 2021 12:46:43 -1000 Message-Id: <20210115224645.1196742-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115224645.1196742-1-richard.henderson@linaro.org> References: <20210115224645.1196742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jan 2021 22:47:26 -0000 Use the now-saved PAGE_ANON and PAGE_MTE bits, and the per-page saved data. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d55f8d1e1e..1c569336ea 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr = useronly_clean_ptr(ptr); + int flags = page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; -- 2.25.1 From MAILER-DAEMON Fri Jan 15 18:16:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0YK3-0005J1-Nv for mharc-qemu-arm@gnu.org; Fri, 15 Jan 2021 18:16:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) 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1l0lk7-0000Sg-Vb for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 08:35:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0lk4-0000RL-Ak; Sat, 16 Jan 2021 08:35:49 -0500 Received: from mail-yb1-xb34.google.com ([2607:f8b0:4864:20::b34]:39916) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0lk0-0003BQ-R8; Sat, 16 Jan 2021 08:35:48 -0500 Received: by mail-yb1-xb34.google.com with SMTP id k4so7897871ybp.6; Sat, 16 Jan 2021 05:35:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=8on2QyB1HDr8H7GCBL1pm3AsHHKa0V4OLPtywW5HFVo=; b=bwdhOMK2WEGXWe3uR6W+ZatKA48oN2rRWgd15YkOLcS1ujQViVCWeyziUCkRn/HmWs 3AJ3q+s4Qw2RyqxUPDJEjoGQymHoh/CB3woG+xPSnPYAzmdgYPyuNYhPNtXDJazt1MDa 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ABdhPJyLgCVSYIReOxQC65fflqgo9k6uZK9xD/asuw++BB5YfK24cc/QEKnA6qjqZfWSwd/2Muzr6zQ10GTXIeM5F1w= X-Received: by 2002:a25:b8ca:: with SMTP id g10mr23495282ybm.517.1610804142354; Sat, 16 Jan 2021 05:35:42 -0800 (PST) MIME-Version: 1.0 References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-5-f4bug@amsat.org> In-Reply-To: <20210115153049.3353008-5-f4bug@amsat.org> From: Bin Meng Date: Sat, 16 Jan 2021 21:35:30 +0800 Message-ID: Subject: Re: [PATCH v7 4/9] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Juan Quintela , Alistair Francis , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 13:35:49 -0000 On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > > When the block is disabled, it stay it is 'internal reset logic' > (internal clocks are gated off). Reading any register returns > its reset value. Only update this value if the device is enabled. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Reviewed-by: Juan Quintela > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- > 1 file changed, 29 insertions(+), 31 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 78b19c2eb91..ba7d3438d87 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -269,42 +269,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr o= ffset, unsigned size) > return 0; > } > > - switch (index) { > - case ECSPI_RXDATA: > - if (!imx_spi_is_enabled(s)) { > - value =3D 0; > - } else if (fifo32_is_empty(&s->rx_fifo)) { > - /* value is undefined */ > - value =3D 0xdeadbeef; > - } else { > - /* read from the RX FIFO */ > - value =3D fifo32_pop(&s->rx_fifo); > + value =3D s->regs[index]; > + > + if (imx_spi_is_enabled(s)) { > + switch (index) { > + case ECSPI_RXDATA: > + if (fifo32_is_empty(&s->rx_fifo)) { > + /* value is undefined */ > + value =3D 0xdeadbeef; > + } else { > + /* read from the RX FIFO */ > + value =3D fifo32_pop(&s->rx_fifo); > + } > + break; > + case ECSPI_TXDATA: > + qemu_log_mask(LOG_GUEST_ERROR, > + "[%s]%s: Trying to read from TX FIFO\n", > + TYPE_IMX_SPI, __func__); > + > + /* Reading from TXDATA gives 0 */ The new logic is a little bit non straight forward as the value 0 comes from s->regs[index] which was never written hence 0. While the previous logic is returning explicitly zero. Perhaps a comment update is needed. > + break; > + case ECSPI_MSGDATA: > + qemu_log_mask(LOG_GUEST_ERROR, > + "[%s]%s: Trying to read from MSG FIFO\n", > + TYPE_IMX_SPI, __func__); > + /* Reading from MSGDATA gives 0 */ ditto > + break; > + default: > + break; > } > > - break; > - case ECSPI_TXDATA: > - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX F= IFO\n", > - TYPE_IMX_SPI, __func__); > - > - /* Reading from TXDATA gives 0 */ > - > - break; > - case ECSPI_MSGDATA: > - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG = FIFO\n", > - TYPE_IMX_SPI, __func__); > - > - /* Reading from MSGDATA gives 0 */ > - > - break; > - default: > - value =3D s->regs[index]; > - break; > + imx_spi_update_irq(s); > } > - > DPRINTF("reg[%s] =3D> 0x%" PRIx32 "\n", imx_spi_reg_name(index), val= ue); > > - imx_spi_update_irq(s); > - > return (uint64_t)value; > } Regards, Bin From MAILER-DAEMON Sat Jan 16 08:57:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0m59-0006Sw-5U for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 08:57:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0m57-0006Qz-HV; Sat, 16 Jan 2021 08:57:33 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:44137) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0m55-0004K9-JJ; Sat, 16 Jan 2021 08:57:33 -0500 Received: by mail-yb1-xb30.google.com with SMTP id x78so3455439ybe.11; Sat, 16 Jan 2021 05:57:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=nu3Bbd5pelM1fs79IiPKF/oYSY6ihGViecK8gbgsqF4=; b=Sdbbdles0ebpcggKdpbjt7/oZsqNtFq3m7Lkqrk+KxM6jAXH/ZXNl92zWWfOmSF20s /8z8xllvcObSLOfM95CHgmxez9Jgbb0uEfFYMfjcEJfcyEboI5VMFkkrwE5erGL0oTS1 IVGQ8qbZBkxjn4i8W5VKNZmskgaB1kCOeoctTKfN2xdEVZm+gE5Z+jAhuY4dI/0z2zme mTPmgwPbZgnCmpHnhy71RCEyj0NCG3VPj/TThotRod3sBRDh17NArebSzPqVoMtGWaY5 fGh+Yr/0y+RwS4gUeJKKAnegeLJXlvuko6N4QJfhONdnSWk0MybRnvZrG0GF54H5HY92 sbRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=nu3Bbd5pelM1fs79IiPKF/oYSY6ihGViecK8gbgsqF4=; b=tO5lCxSqv2Ulz67aj2FLBYG96g8tuMksXcBTNVwSI//VtrvYyz8V/9WRKIKm7WJ5eZ L7MXKV+PxhkWseK1oCYmVqb6Lm1SJDdvdIktDzm2GlcoztE02AF0RGr5QI7mBJv5YCI6 BlpvLGYjAT0eZNbplTUqtUZg9E4QyMUhdjTZEHQEz6PjGL4NixSac239Cst1w9n9J1N1 YELA8nJtcb9X0tBQt3F3RIXd/wULtfeSBAFNhPa1fzj9lTKT5tB3qj2zQjFRa6QJfiT8 fhSHedQCpV8v+8Y2prI7pQY1XFCBelGd9IRUfDWIInQRsYa09eeQJnLO2e8D047Ljcg0 PiLw== X-Gm-Message-State: AOAM531heGn//Ysxtsadwl0SgslBhR/KSLYCJWpUPv48yjehd/f5QOG6 7X6BRmu4yyolbJ1hjsBfVTM9wBkXjnnRs9Tg714= X-Google-Smtp-Source: ABdhPJzNfcvG3zTLkwI+Bg2jvj332qvO/TQi8r1shvPpXnOXmvY8VyuostzoudxHG/hFcBpyUeIGCHFPN93Rx3k3OtE= X-Received: by 2002:a5b:5ce:: with SMTP id w14mr11892488ybp.314.1610805450189; Sat, 16 Jan 2021 05:57:30 -0800 (PST) MIME-Version: 1.0 References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-6-f4bug@amsat.org> In-Reply-To: <20210115153049.3353008-6-f4bug@amsat.org> From: Bin Meng Date: Sat, 16 Jan 2021 21:57:19 +0800 Message-ID: Subject: Re: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Alistair Francis , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 13:57:33 -0000 On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > > When the block is disabled, only the ECSPI_CONREG register can > be modified. Setting the EN bit enabled the device, clearing it I don't know how this conclusion came out. The manual only says the following 2 registers ignore the write when the block is disabled. ECSPI_TXDATA, ECSPI_INTREG > "disables the block and resets the internal logic with the > exception of the ECSPI_CONREG" register. > > Move the imx_spi_is_enabled() check earlier. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- > 1 file changed, 16 insertions(+), 10 deletions(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index ba7d3438d87..f06bbf317e2 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, > DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", imx_spi_reg_name(index), > (uint32_t)value); > > + if (!imx_spi_is_enabled(s)) { > + /* Block is disabled */ > + if (index !=3D ECSPI_CONREG) { > + /* Ignore access */ > + return; > + } > + s->regs[ECSPI_CONREG] =3D value; > + if (!(value & ECSPI_CONREG_EN)) { > + /* Keep disabled */ So other bits except ECSPI_CONREG_EN are discarded? The manual does not explicitly mention this but this looks suspicious. > + return; > + } > + /* Enable the block */ > + imx_spi_reset(DEVICE(s)); > + } > + > change_mask =3D s->regs[index] ^ value; > > switch (index) { > @@ -330,10 +345,7 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, > TYPE_IMX_SPI, __func__); > break; > case ECSPI_TXDATA: > - if (!imx_spi_is_enabled(s)) { > - /* Ignore writes if device is disabled */ > - break; > - } else if (fifo32_is_full(&s->tx_fifo)) { > + if (fifo32_is_full(&s->tx_fifo)) { > /* Ignore writes if queue is full */ > break; > } > @@ -359,12 +371,6 @@ static void imx_spi_write(void *opaque, hwaddr offse= t, uint64_t value, > case ECSPI_CONREG: > s->regs[ECSPI_CONREG] =3D value; > > - if (!imx_spi_is_enabled(s)) { > - /* device is disabled, so this is a reset */ > - imx_spi_reset(DEVICE(s)); > - return; > - } > - > if (imx_spi_channel_is_master(s)) { > int i; > Regards, Bin From MAILER-DAEMON Sat Jan 16 09:04:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0mBi-0002Qy-MB for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 09:04:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0mBg-0002OX-Um; Sat, 16 Jan 2021 09:04:20 -0500 Received: from mail-yb1-xb34.google.com ([2607:f8b0:4864:20::b34]:44171) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0mBc-00077G-1H; Sat, 16 Jan 2021 09:04:20 -0500 Received: by mail-yb1-xb34.google.com with SMTP id x78so3468051ybe.11; Sat, 16 Jan 2021 06:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=+9nb/K8vwwd5x39k2McpOKj8Lo9D+53Dc4FSxYQOg4A=; b=pMUS/1dgVdfzcIPIGC20v0SBAHICPI5PRaPb1QjLk1nN6Kn8WvWc9zyrysXATj1M76 Mi2G5ZoID26pG8vbQgaIWckyCQ9T1jLVr21FDl6Z1K/Gtx4pepBB7YY5elouTWPN9s1Y f5SfDndipbljMArCmuRnbUon9CLXayNMXaxtlIgFagpixhjWC2f0rqpJ0CW/h3rtIxFu TMSqBCNCoAfM5Xz8rwuiQBuByJkwRNWTqcGfql0AO/FZ6EfO0zC6n2jzO4GPosQ2tbCR 5vD54z8gqkOrAKHOeBEAkokt3A9rZ1F4q53lXWjAkniXpS7cBPuZPTVs56TysYuYYD5o fM0A== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 14:04:21 -0000 Hi Philippe, On Fri, Jan 15, 2021 at 11:31 PM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi, > > This is how I understand the ecSPI reset works, after > looking at the IMX6DQRM.pdf datasheet. > > This is a respin of Ben's v5 series [*]. > > Since v6: > - Dropped "Reduce 'change_mask' variable scope" patch > - Fixed inverted reset logic > - Added Juan R-b tags > - Removed 'RFC' tag as tests pass > > Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com> > (queued on riscv-next). > This series dropped my imx_spi_soft_reset() change that has the imx_spi_update_irq() moved from imx_spi_reset(). May I know why? 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id y63sm16804172wmd.21.2021.01.16.07.07.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 16 Jan 2021 07:07:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Bin Meng Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210115153049.3353008-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <5993ce13-85fc-35b8-57e3-8a694a930f44@amsat.org> Date: Sat, 16 Jan 2021 16:07:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.039, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 15:07:56 -0000 On 1/16/21 3:03 PM, Bin Meng wrote: > Hi Philippe, > > On Fri, Jan 15, 2021 at 11:31 PM Philippe Mathieu-Daudé wrote: >> >> Hi, >> >> This is how I understand the ecSPI reset works, after >> looking at the IMX6DQRM.pdf datasheet. >> >> This is a respin of Ben's v5 series [*]. >> >> Since v6: >> - Dropped "Reduce 'change_mask' variable scope" patch >> - Fixed inverted reset logic >> - Added Juan R-b tags >> - Removed 'RFC' tag as tests pass >> >> Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com> >> (queued on riscv-next). >> > > This series dropped my imx_spi_soft_reset() change that has the > imx_spi_update_irq() moved from imx_spi_reset(). May I know why? Because we don't need it. My comment without looking at the datasheet was incorrect: there is only one single reset on the block. > > Regards, > Bin > From MAILER-DAEMON Sat Jan 16 10:13:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0nGE-0006Mt-Ps for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 10:13:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0nGC-0006Me-Na; Sat, 16 Jan 2021 10:13:04 -0500 Received: from mail-yb1-xb2a.google.com ([2607:f8b0:4864:20::b2a]:45602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0nGB-0004zv-6j; Sat, 16 Jan 2021 10:13:04 -0500 Received: by mail-yb1-xb2a.google.com with SMTP id u18so5813804ybu.12; Sat, 16 Jan 2021 07:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=/SsEGjU/qMpLc11w6beFPoK1a3LRynOrJE9SBnON9Mc=; b=FBsByHof6Ng6KH5TZny/lcCMI24PmLDFCyrLENh6XBJLAu6EC2N6Fla9u+WtQheP1I 9wmjLDAbzBeiF4S44fwBpLliBKN3KyI4eYsL9dwdoZczJpmjFVgZKWX45Hp7xYsE+Fbw V7Yripe03WTPbj2xQsXGzy3b8clgkCkJchqvb83opMxwD/v2iHPhx+NefgtIJwm57iv0 Ecvm6ve1wr01bIiYXf4jSbv+mnYDaCNTiyM9buYHZanYBy/+9C1Dnye8/hcJ1sE1RF10 qijnlu+7a9LrpSNEdIgmJQT3hggCFoS28QQikQMC7bi85tBJp1lYRM8BpC89twszLrVC AoDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=/SsEGjU/qMpLc11w6beFPoK1a3LRynOrJE9SBnON9Mc=; b=MVnxSdyzoA59VuI0oVC8EIPTiGqbx0axqUJO/hq950MwrIkPQnJNb54JVW7uWB+lo4 CQSJvJa03H/39ga3wvGJgeSgMUYIEsntzu/Wl8QUDGERpXa5g5YNrnUQNxdcVt9P0gdJ QNKfS9HEKUpXrq/WA7GR6H+56zo9/Oiar5zBGvUzFNisoyGMGOomqjxGs9E+xNxMvGtV ysZCuMe99/gZCBooKgqrWnpaW5W6BTm7n0jCpNFrvjIMJjNOP1fwnduItuibniDPqWx3 aq5gdsE7WBZDjNMQQNWvikmx2GHrQHeL5cgy451wLnsk9kvTRvOjdjr9XH8RRC1qUuKR qoSg== X-Gm-Message-State: AOAM532z/3wmNJCKT+vuNHIULXx53FTQ7oh1dRHLRrplT2MWmeAC/lE0 p4+2gLAdPrWM4SOKcFi876+53UAPusmLubgJt44= X-Google-Smtp-Source: ABdhPJxYoK/QSrH+o7Rar4RJEnDk6wMRgQKLfVNCpD6+UqyCYj4nx6gjpXDdSrpyqhgFzsGn/jChHiRsl/wS1UFmP2s= X-Received: by 2002:a25:4d7:: with SMTP id 206mr26239728ybe.306.1610809981846; Sat, 16 Jan 2021 07:13:01 -0800 (PST) MIME-Version: 1.0 References: <20210115153049.3353008-1-f4bug@amsat.org> <5993ce13-85fc-35b8-57e3-8a694a930f44@amsat.org> In-Reply-To: <5993ce13-85fc-35b8-57e3-8a694a930f44@amsat.org> From: Bin Meng Date: Sat, 16 Jan 2021 23:12:50 +0800 Message-ID: Subject: Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2a; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 15:13:05 -0000 On Sat, Jan 16, 2021 at 11:07 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/16/21 3:03 PM, Bin Meng wrote: > > Hi Philippe, > > > > On Fri, Jan 15, 2021 at 11:31 PM Philippe Mathieu-Daud=C3=A9 wrote: > >> > >> Hi, > >> > >> This is how I understand the ecSPI reset works, after > >> looking at the IMX6DQRM.pdf datasheet. > >> > >> This is a respin of Ben's v5 series [*]. > >> > >> Since v6: > >> - Dropped "Reduce 'change_mask' variable scope" patch > >> - Fixed inverted reset logic > >> - Added Juan R-b tags > >> - Removed 'RFC' tag as tests pass > >> > >> Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com> > >> (queued on riscv-next). > >> > > > > This series dropped my imx_spi_soft_reset() change that has the > > imx_spi_update_irq() moved from imx_spi_reset(). May I know why? > > Because we don't need it. My comment without looking at the datasheet > was incorrect: there is only one single reset on the block. Oh, you must have missed Peter's comments. See his comments here: http://patchwork.ozlabs.org/project/qemu-devel/patch/20201202144523.24526-2= -bmeng.cn@gmail.com/ Regards, Bin From MAILER-DAEMON Sat Jan 16 10:21:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0nOQ-0008Cj-Kn for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 10:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0nOP-0008By-Cm; Sat, 16 Jan 2021 10:21:33 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0nON-0000XO-Rg; Sat, 16 Jan 2021 10:21:33 -0500 Received: by mail-wr1-x42a.google.com with SMTP id q18so12221350wrn.1; Sat, 16 Jan 2021 07:21:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=AjEQHqFZK0FcaMs+bXU5E0skq7VdWBykRyB/SIX8kA4=; b=tS5Wr+qnGFa9xT42RZxT21UgdmcIiVlVWWXwID8pDqIBA+LUNIhN6KP9T6f6UNMmmB o+TInL0jDaxxt9gbJQJoIaXRreyzhanJj3x0CfbDiargtYDkd7YCCeQUP5aBHPPoF4sz YfZNTIqHLT1WKiwVCRBE+kU9glRetAcBLfLOLkjiOEza0w/fiVdNglTMfbh/GbDyn3Dd XXt/BLh+clM3RAWG1PECY7WXWMwaGM5KeKinQmKCdLGKABkqUHHZrB8kkXqAPmvD+2S1 0Iiahaa/V2DSsiIP/byd9Txrs7u0RUXeOc6nnN2o4qJWC5pyph2B4woP+E5hb7E3EjE7 O5Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=AjEQHqFZK0FcaMs+bXU5E0skq7VdWBykRyB/SIX8kA4=; b=VKP4uqfOoL5eoLVwNgp5dojmpVCdAyH5fqGXo09k1itMAvvW2qdLxhj49i0qi7U6/y aDjoOOLctgpeU1kWf3ywlkpZZeZIYqm50BNdN4X5Oj7QGulQm2nOCEE23QFIZjJEm4a0 144ZIVhT57b4xAoidcMGP1Bb0DSr8tKqIuIaULeC8yT8dF4rfwCvjAYOCVl4CzVg917i qezWXz8xE3x0zV6FAHpnAsuAwd6RdQe38D7pbFTA5IJkyI7ZnN6QbIOSaurma6ruFB5L o5OJ8s0r5hlwbkoZkfSA7wBu21PRjiZEhKk5kvPESLHWJme3/PsS9PZX78Hrxlj74+7w yveA== X-Gm-Message-State: AOAM530e4PB6lIFhEB/sZWqAJCrgxsl97LYp0gU/N+6sDHi57Gwck1WK akSnHKv27Jx8cf6dgqVOQAw= X-Google-Smtp-Source: ABdhPJxDQDwPYx3+ODWT/yUgaIBKZg0qqHFpgqRtQtVfbxvUrSh+6EoKWy5XEq6rCG30RZMFaAU3+w== X-Received: by 2002:adf:8184:: with SMTP id 4mr18984362wra.63.1610810490111; Sat, 16 Jan 2021 07:21:30 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s13sm19965798wra.53.2021.01.16.07.21.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 16 Jan 2021 07:21:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: Bin Meng Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-6-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7fcb40af-12a4-8926-b612-34d21988baf5@amsat.org> Date: Sat, 16 Jan 2021 16:21:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.039, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 15:21:33 -0000 Hi Bin, On 1/16/21 2:57 PM, Bin Meng wrote: > On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daudé wrote: >> >> When the block is disabled, only the ECSPI_CONREG register can >> be modified. Setting the EN bit enabled the device, clearing it > > I don't know how this conclusion came out. The manual only says the > following 2 registers ignore the write when the block is disabled. > > ECSPI_TXDATA, ECSPI_INTREG 21.4.5 Reset Whenever a device reset occurs, a reset is performed on the ECSPI, resetting all registers to their default values. My understanding is it is pointless to update them when the device is in reset, as they will get their default value when going out of reset. > >> "disables the block and resets the internal logic with the >> exception of the ECSPI_CONREG" register. >> >> Move the imx_spi_is_enabled() check earlier. >> >> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), >> chapter 21.7.3: Control Register (ECSPIx_CONREG) >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- >> 1 file changed, 16 insertions(+), 10 deletions(-) >> >> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >> index ba7d3438d87..f06bbf317e2 100644 >> --- a/hw/ssi/imx_spi.c >> +++ b/hw/ssi/imx_spi.c >> @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, >> DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), >> (uint32_t)value); >> >> + if (!imx_spi_is_enabled(s)) { >> + /* Block is disabled */ >> + if (index != ECSPI_CONREG) { >> + /* Ignore access */ >> + return; >> + } >> + s->regs[ECSPI_CONREG] = value; [*] >> + if (!(value & ECSPI_CONREG_EN)) { >> + /* Keep disabled */ > > So other bits except ECSPI_CONREG_EN are discarded? The manual does > not explicitly mention this but this looks suspicious. See in [*], all bits from the register are updated. We simply check ECSPI_CONREG_EN to see if we need to go out of reset. See: 21.5 Initialization This section provides initialization information for ECSPI. To initialize the block: 1. Clear the EN bit in ECSPI_CONREG to reset the block. 2. Enable the clocks for ECSPI. 3. Set the EN bit in ECSPI_CONREG to put ECSPI out of reset. 4. Configure corresponding IOMUX for ECSPI external signals. 5 Configure registers of ECSPI properly according to the specifications of the external SPI device. And ECSPI_CONREG_EN bit description: SPI Block Enable Control. This bit enables the ECSPI. This bit must be set before writing to other registers or initiating an exchange. Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. The block's internal clocks are gated off whenever the block is disabled. I simply wanted to help you. I don't want to delay your work, so if you think my approach is incorrect, suggest Peter to queue your v5 or resend it (once riscv-next is merged) as v8. Regards, Phil. From MAILER-DAEMON Sat Jan 16 10:59:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0nzK-00072B-FS for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 10:59:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0nzJ-00071w-3T; Sat, 16 Jan 2021 10:59:41 -0500 Received: from mail-yb1-xb2b.google.com ([2607:f8b0:4864:20::b2b]:40045) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0nzH-0001m6-4x; Sat, 16 Jan 2021 10:59:40 -0500 Received: by mail-yb1-xb2b.google.com with SMTP id w24so5895087ybi.7; Sat, 16 Jan 2021 07:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=sA/3+kIxTZr3zKTbelwDwtDZEbFLBcIjG+sMsDsoh9w=; b=W3gQ2bkVtxCKjoLL9WPUsWeGCi4iWFWmQ/BDnLWWTeE28PToy0mdl+u3Xycpd3HwVU Wu70Z92S78jmakAMETz4LHBzzwICXaihCsacUb0UmSCW6LOo1yJDbwlsGjVk1aRhSIbs IVQGKlXHKcjkEyd0OPaGMyOKU+AYGGFeaVH3xMVvmHr0C3h+TVD8LB/rq9XtJA0RBLfJ +ibGc9+xe3mfSiFhO8wsbujBWBfHvbCYrxkGyk7QWs85RQSQJm75wnv05WM+JnzZX1Ia WR1SH6c/dJP2YwTZnkNHCRg15ur3qfV6adNsUSF6n61D8DaesSNx0gaZMletrVT85gqr Vibw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=sA/3+kIxTZr3zKTbelwDwtDZEbFLBcIjG+sMsDsoh9w=; b=f+1Y5fSAYm/AR7C2/Nhj0th9vXzNqFyrd9NQojiMOCxnQTmGgrienEMYtR7t1I9NlY meYT57ofmHKYKWRVshlMUHLlTjeNBBQkGB5ddOpXtF15EBmegFm8a6yweCHXBK+P3zhl FeQnsp3zjVTrCfQ1zgi1w6odjVfueMKFK5xx/tYoYLeh7/QZqiMoseTaclN6gQbatPVk t3JgK4xcUdEy7J1hh2SiSBXYVaMB0PKC4I7UzXUZs/uzqOMkPOEhDGcGwUgjNa0fT4hr KT8+QLtGgnAbjaG3+hB0gDnRkd0P6D5/d48JnWPBhe9SaLoNVLkgjHrwJxIymnDpsSXu ayFQ== X-Gm-Message-State: AOAM531SIEZoGhJd+4GAtCv24VLrsdIxdBHrfbXbeta4mZGHsN2R88VV ZXjSon5QNBFylraPtnV/ulqQw9auU9AeATmYVgU= X-Google-Smtp-Source: ABdhPJza4HC7zsmxnVq+LjeNHjghZdRMPvRTFQZku2SW2UEYLw3Oj3os0uW2qqE2hcJR/ICEHljOcCofxdWrhrmwvmc= X-Received: by 2002:a25:b8ca:: with SMTP id g10mr24135013ybm.517.1610812777809; Sat, 16 Jan 2021 07:59:37 -0800 (PST) MIME-Version: 1.0 References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-6-f4bug@amsat.org> <7fcb40af-12a4-8926-b612-34d21988baf5@amsat.org> In-Reply-To: <7fcb40af-12a4-8926-b612-34d21988baf5@amsat.org> From: Bin Meng Date: Sat, 16 Jan 2021 23:59:26 +0800 Message-ID: Subject: Re: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2b; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 15:59:41 -0000 Hi Philippe, On Sat, Jan 16, 2021 at 11:21 PM Philippe Mathieu-Daud=C3=A9 wrote: > > Hi Bin, > > On 1/16/21 2:57 PM, Bin Meng wrote: > > On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > >> > >> When the block is disabled, only the ECSPI_CONREG register can > >> be modified. Setting the EN bit enabled the device, clearing it > > > > I don't know how this conclusion came out. The manual only says the > > following 2 registers ignore the write when the block is disabled. > > > > ECSPI_TXDATA, ECSPI_INTREG > > 21.4.5 Reset > > Whenever a device reset occurs, a reset is performed on the > ECSPI, resetting all registers to their default values. > > My understanding is it is pointless to update them when the > device is in reset, as they will get their default value when > going out of reset. I have a different understanding. When ECSPI_CONREG[EN] is cleared, it's like a hardware reset, and the ECSPI takes the following action: "Whenever a device reset occurs, a reset is performed on the ECSPI, resetting all registers to their default values." Chapter 21.4.5 Reset does not mention what's the hardware behavior afterwar= ds. So my understanding is: afterwards, the software can still write to various registers, unless the register description tells us it's ignored. > > > > >> "disables the block and resets the internal logic with the > >> exception of the ECSPI_CONREG" register. > >> > >> Move the imx_spi_is_enabled() check earlier. > >> > >> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > >> chapter 21.7.3: Control Register (ECSPIx_CONREG) > >> > >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 > >> --- > >> hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- > >> 1 file changed, 16 insertions(+), 10 deletions(-) > >> > >> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > >> index ba7d3438d87..f06bbf317e2 100644 > >> --- a/hw/ssi/imx_spi.c > >> +++ b/hw/ssi/imx_spi.c > >> @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr of= fset, uint64_t value, > >> DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", imx_spi_reg_name(index), > >> (uint32_t)value); > >> > >> + if (!imx_spi_is_enabled(s)) { > >> + /* Block is disabled */ > >> + if (index !=3D ECSPI_CONREG) { > >> + /* Ignore access */ > >> + return; > >> + } > >> + s->regs[ECSPI_CONREG] =3D value; > > [*] > > >> + if (!(value & ECSPI_CONREG_EN)) { > >> + /* Keep disabled */ > > > > So other bits except ECSPI_CONREG_EN are discarded? The manual does > > not explicitly mention this but this looks suspicious. > > See in [*], all bits from the register are updated. We simply check > ECSPI_CONREG_EN to see if we need to go out of reset. Oops, I missed the [*] line. Now I have read this carefully, and found there is one problem: Now with the new logic the device reset activity has been postponed until next time a device register is written. This is wrong. > > See: > > 21.5 Initialization > > This section provides initialization information for ECSPI. > > To initialize the block: > > 1. Clear the EN bit in ECSPI_CONREG to reset the block. > 2. Enable the clocks for ECSPI. > 3. Set the EN bit in ECSPI_CONREG to put ECSPI out of reset. > 4. Configure corresponding IOMUX for ECSPI external signals. > 5 Configure registers of ECSPI properly according to the > specifications of the external SPI device. > > And ECSPI_CONREG_EN bit description: > > SPI Block Enable Control. This bit enables the ECSPI. This bit > must be set before writing to other registers or initiating an > exchange. Writing zero to this bit disables the block and resets > the internal logic with the exception of the ECSPI_CONREG. The > block's internal clocks are gated off whenever the block is > disabled. > > > I simply wanted to help you. I don't want to delay your work, so > if you think my approach is incorrect, suggest Peter to queue your > v5 or resend it (once riscv-next is merged) as v8. Thank you for the help. I mentioned in an earlier thread before, that my view was not to fix it until it's broken as the v5 series can satisfy my work. But since you pointed out various spec violation stuff related to device reset, I do think your findings make sense. So let's improve this model together. :) Regards, Bin From MAILER-DAEMON Sat Jan 16 11:04:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0o4E-0000Ju-1m for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 11:04:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0o4B-0000J0-Pm; Sat, 16 Jan 2021 11:04:43 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0o4A-00048C-1u; Sat, 16 Jan 2021 11:04:43 -0500 Received: by mail-wr1-x432.google.com with SMTP id d13so12241544wrc.13; Sat, 16 Jan 2021 08:04:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ZjPbJg3XfI2Oq3s/+61+tvtAFHWI6eDfktdagW1X7IU=; b=lZqZIqvCjRs/NnPFt8fkgzZoqXgOe/ojnIJ9fmc0N04y/X+mt5T1CZJZJFIsyP/K59 Tr0oqQXEjGSqc9TLPwu5YABop6aayu1EC4ngTddmNWDfNOLOcJ7X5gRhyVXPwst7DbTX qoY37NZOr+QmcE/7xFANHaRLnf0pO/MuJ4fafpKnrkcROO+0JJ9KZKqZ7LChAz2cfoKo V/HCAGKu8oTiJzh5CSY25diSeHpBhwAyKJaT0kzyMJxXPKlEuB0FYRYJ/ngFYNiuKZRJ +GURIkd27B3KHo3sbb3OwCDYxyJOdurdUATMV/IjcLHUja6PqXOz1Ao8Svz2PuvMKn5b zI1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ZjPbJg3XfI2Oq3s/+61+tvtAFHWI6eDfktdagW1X7IU=; b=joaKh10H0f0YR5pUXY+wGt+CJDT1l9Z+5qXwgJiLKCGNiZnYf0drpXdjhl4iJPTrbA bzsUdurbGqUp26UGyPiEFWR/Bt/o+khGt5xq8Rfyyn2LnpkwGuW4ISrD8O5/JZfmRooE 5MKsSD/4wQHo2skE93UFQRxxJMi17zf83YlNAT50KXKNWA2PMH14193c5a2wQVCY7PSL pUOirUojHs1JFTP5Pou4CJPjUelY64ip0WHZLdTyXCs1GziUbexbavdPWxBUiI4DIZ0v K76QJ1TDvvrbnRrMi7dHs87dzsDkBsmMSy/ba3KSD2K9tYvDoN0um4eHf4cbzuXOj94q oz6Q== X-Gm-Message-State: AOAM531t1TmEaozlXEjuHTttNEOpHa49gAZo51ZT+wQSnmTSEPsmIxPE nzOq3WFS0sIfCrtoYi4aAq4= X-Google-Smtp-Source: ABdhPJwrRCiToeq6lqQovp6BiNOIWSa8YeslPy79SRnm30HgfuJCT2KgbpQHWs3Zqi/qyd/zmbiuow== X-Received: by 2002:adf:f70c:: with SMTP id r12mr18529589wrp.234.1610813079438; Sat, 16 Jan 2021 08:04:39 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id r20sm21884665wrg.66.2021.01.16.08.04.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 16 Jan 2021 08:04:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v7 4/9] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled To: Bin Meng Cc: Peter Maydell , Juan Quintela , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-5-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <56ae54c7-5608-9670-af2f-8357e3acd214@amsat.org> Date: Sat, 16 Jan 2021 17:04:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.039, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 16:04:44 -0000 On 1/16/21 2:35 PM, Bin Meng wrote: > On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daudé wrote: >> >> When the block is disabled, it stay it is 'internal reset logic' >> (internal clocks are gated off). Reading any register returns >> its reset value. Only update this value if the device is enabled. >> >> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), >> chapter 21.7.3: Control Register (ECSPIx_CONREG) >> >> Reviewed-by: Juan Quintela >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- >> 1 file changed, 29 insertions(+), 31 deletions(-) >> >> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >> index 78b19c2eb91..ba7d3438d87 100644 >> --- a/hw/ssi/imx_spi.c >> +++ b/hw/ssi/imx_spi.c >> @@ -269,42 +269,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) >> return 0; >> } >> >> - switch (index) { >> - case ECSPI_RXDATA: >> - if (!imx_spi_is_enabled(s)) { >> - value = 0; >> - } else if (fifo32_is_empty(&s->rx_fifo)) { >> - /* value is undefined */ >> - value = 0xdeadbeef; >> - } else { >> - /* read from the RX FIFO */ >> - value = fifo32_pop(&s->rx_fifo); >> + value = s->regs[index]; >> + >> + if (imx_spi_is_enabled(s)) { >> + switch (index) { >> + case ECSPI_RXDATA: >> + if (fifo32_is_empty(&s->rx_fifo)) { >> + /* value is undefined */ >> + value = 0xdeadbeef; >> + } else { >> + /* read from the RX FIFO */ >> + value = fifo32_pop(&s->rx_fifo); >> + } >> + break; >> + case ECSPI_TXDATA: >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "[%s]%s: Trying to read from TX FIFO\n", >> + TYPE_IMX_SPI, __func__); >> + >> + /* Reading from TXDATA gives 0 */ > > The new logic is a little bit non straight forward as the value 0 > comes from s->regs[index] which was never written hence 0. While the > previous logic is returning explicitly zero. Perhaps a comment update > is needed. You are right, if the device is in reset, it will return the reset values (eventually 0, I haven't checked). Simple fix could be to better place the imx_spi_reset() call in imx_spi_write(). Since we are discussing the reset bit of this device, I wonder if it wouldn't be clearer to use the the 3-phase-reset API then... > >> + break; >> + case ECSPI_MSGDATA: >> + qemu_log_mask(LOG_GUEST_ERROR, >> + "[%s]%s: Trying to read from MSG FIFO\n", >> + TYPE_IMX_SPI, __func__); >> + /* Reading from MSGDATA gives 0 */ > > ditto > >> + break; >> + default: >> + break; >> } From MAILER-DAEMON Sat Jan 16 11:12:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0oBR-0003T5-Gz for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 11:12:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0oBQ-0003Sk-An; Sat, 16 Jan 2021 11:12:12 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:36996) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0oBO-00080G-Ij; Sat, 16 Jan 2021 11:12:12 -0500 Received: by mail-wr1-x435.google.com with SMTP id v15so8628199wrx.4; Sat, 16 Jan 2021 08:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=oxOL1MDGpic7M31Lg7mDraKuOjB4l0Ysgno9cxrjJLM=; b=Bq5Wt7B0692GwkYRGkktDE/N9CoGYffFSdriAxO6WbQeuWrGl7380XwD+iA045SMlV Uq/6IHgonHSHxPVHESdBBAgOlcA13LetkqzJGrhFHuptW1oR8XTpH2FT5xZQK2LVyn25 7mwzBfQk0zZaOa0CRtLqJEsD/GYhp5Beq2MjKeELjnQvR8mm54IUvXNe5wrXHaRKK17+ YEcyNrzdx2foJ1xF/D3NTTQWzhzWwxS1mjmnJ+PUFxM222Mt9CYOh7/jzQwiULRHmZQC b+LyfkYCMTtxvFFAGNHHFg10hRt9r5m9Yp2T6oXvqJuVF1gTSjSxDnrbyjbR+mqk8Oo3 oDxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=oxOL1MDGpic7M31Lg7mDraKuOjB4l0Ysgno9cxrjJLM=; b=ZeZotPo2vF6LP1syAW+mflnMdAh67WpovqbcylwobQKGwwnjMT1KwJTHm1g61YNp1Q sJ5rNCHCRAYbX9U4/SRuBL5BYm8YLOsRErmkJPeGQCRFu+WP08azOiaLxT7dAyj/t9CB X520aJh3Aesppa4kRB4+eKX/eGiBKDovqwGqlSr9x3FQfFwDfU4Z/HCu5GemOdnU8oo8 UE6xlwU2i5eWjhk8Zmq2GDAoJCfFp3RP+1pCRyOxI+89Hd4T6D8juM6WlPI7dT2NEpS+ 0knzVz3t+Lj8GpStzwyt0orVV5z6cftRo5otV21stYi2jwM5mO6U4cpihPBWDo26bC3F dRwg== X-Gm-Message-State: AOAM531VTlERIA2J9Cktli2x0zyUwFy4I2SlRKUj2Yl411wPUWnMgxZF JnFlKo8P0kqE9OOKuuxSd1E= X-Google-Smtp-Source: ABdhPJxB1WrvNr5gF4p33SJDmeT+Ln4Pm9TQJ0T3YhSXOvWttoD0oRz7EsvIS37CWWjoOlRAfYgdYQ== X-Received: by 2002:adf:b343:: with SMTP id k3mr18163677wrd.202.1610813528418; Sat, 16 Jan 2021 08:12:08 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id a62sm15652944wmf.7.2021.01.16.08.12.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 16 Jan 2021 08:12:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: Bin Meng Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-6-f4bug@amsat.org> <7fcb40af-12a4-8926-b612-34d21988baf5@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sat, 16 Jan 2021 17:12:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.039, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 16:12:12 -0000 On 1/16/21 4:59 PM, Bin Meng wrote: > Hi Philippe, > > On Sat, Jan 16, 2021 at 11:21 PM Philippe Mathieu-Daudé wrote: >> >> Hi Bin, >> >> On 1/16/21 2:57 PM, Bin Meng wrote: >>> On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daudé wrote: >>>> >>>> When the block is disabled, only the ECSPI_CONREG register can >>>> be modified. Setting the EN bit enabled the device, clearing it >>> >>> I don't know how this conclusion came out. The manual only says the >>> following 2 registers ignore the write when the block is disabled. >>> >>> ECSPI_TXDATA, ECSPI_INTREG >> >> 21.4.5 Reset >> >> Whenever a device reset occurs, a reset is performed on the >> ECSPI, resetting all registers to their default values. >> >> My understanding is it is pointless to update them when the >> device is in reset, as they will get their default value when >> going out of reset. > > I have a different understanding. When ECSPI_CONREG[EN] is cleared, > it's like a hardware reset, and the ECSPI takes the following action: > > "Whenever a device reset occurs, a reset is performed on the > ECSPI, resetting all registers to their default values." > > Chapter 21.4.5 Reset does not mention what's the hardware behavior afterwards. > > So my understanding is: afterwards, the software can still write to > various registers, unless the register description tells us it's > ignored. > >> >>> >>>> "disables the block and resets the internal logic with the >>>> exception of the ECSPI_CONREG" register. >>>> >>>> Move the imx_spi_is_enabled() check earlier. >>>> >>>> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), >>>> chapter 21.7.3: Control Register (ECSPIx_CONREG) >>>> >>>> Signed-off-by: Philippe Mathieu-Daudé >>>> --- >>>> hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- >>>> 1 file changed, 16 insertions(+), 10 deletions(-) >>>> >>>> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >>>> index ba7d3438d87..f06bbf317e2 100644 >>>> --- a/hw/ssi/imx_spi.c >>>> +++ b/hw/ssi/imx_spi.c >>>> @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, >>>> DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), >>>> (uint32_t)value); >>>> >>>> + if (!imx_spi_is_enabled(s)) { >>>> + /* Block is disabled */ >>>> + if (index != ECSPI_CONREG) { >>>> + /* Ignore access */ >>>> + return; >>>> + } >>>> + s->regs[ECSPI_CONREG] = value; >> >> [*] >> >>>> + if (!(value & ECSPI_CONREG_EN)) { >>>> + /* Keep disabled */ >>> >>> So other bits except ECSPI_CONREG_EN are discarded? The manual does >>> not explicitly mention this but this looks suspicious. >> >> See in [*], all bits from the register are updated. We simply check >> ECSPI_CONREG_EN to see if we need to go out of reset. > > Oops, I missed the [*] line. Now I have read this carefully, and found > there is one problem: > > Now with the new logic the device reset activity has been postponed > until next time a device register is written. This is wrong. Yes, I just realized that in the imx_spi_read() function. > >> >> See: >> >> 21.5 Initialization >> >> This section provides initialization information for ECSPI. >> >> To initialize the block: >> >> 1. Clear the EN bit in ECSPI_CONREG to reset the block. >> 2. Enable the clocks for ECSPI. >> 3. Set the EN bit in ECSPI_CONREG to put ECSPI out of reset. >> 4. Configure corresponding IOMUX for ECSPI external signals. >> 5 Configure registers of ECSPI properly according to the >> specifications of the external SPI device. >> >> And ECSPI_CONREG_EN bit description: >> >> SPI Block Enable Control. This bit enables the ECSPI. This bit >> must be set before writing to other registers or initiating an >> exchange. Writing zero to this bit disables the block and resets >> the internal logic with the exception of the ECSPI_CONREG. The >> block's internal clocks are gated off whenever the block is >> disabled. >> >> >> I simply wanted to help you. I don't want to delay your work, so >> if you think my approach is incorrect, suggest Peter to queue your >> v5 or resend it (once riscv-next is merged) as v8. > > Thank you for the help. I mentioned in an earlier thread before, that > my view was not to fix it until it's broken as the v5 series can > satisfy my work. But since you pointed out various spec violation > stuff related to device reset, I do think your findings make sense. So > let's improve this model together. :) I'm not mad, just I'm doing too many things and I should rather review your ssi-sd series. I don't have the physical hardware (neither know the firmware using it) so it is a bit dumb of me to code blindly with no possibility of testing. If you think this series is going the good way, it would be great if you can give it another try, and I will be happy to review. Regards, Phil. From MAILER-DAEMON Sat Jan 16 11:16:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0oFn-0005Yu-NI for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 11:16:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0oFl-0005WD-N2; Sat, 16 Jan 2021 11:16:41 -0500 Received: from mail-yb1-xb2d.google.com ([2607:f8b0:4864:20::b2d]:33677) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0oFj-0001sU-OV; Sat, 16 Jan 2021 11:16:41 -0500 Received: by mail-yb1-xb2d.google.com with SMTP id i141so686789yba.0; Sat, 16 Jan 2021 08:16:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Ymgw9EJaoycqtcZPMuEs2zZSi51jWFMW40h/C1BZ008=; b=nA+RhKak1E0xTA8sBDQpzyZUzlMDoyenrFQebakRNQfyn26MLp68SRT2MI9jSdaFgN W5ruX5/jSfQHh6SMZnfAjYfjTFQVjrcT0Yy/nqWsYjT61Vqkpe8NJRq8yKKb6BhDpc/2 +W/hT+GA8KG01IycF3VMSV+qeKk5FEFLMM5d0T1GBEL27SNBESKjQ0M464QBJOy0gHLJ YrPR3kqHU7+RuqqorHD/vsCZyYN/Ff3TrMYlc/MTysRRyce/31WzSFcyUNoOPt/Qt6NH F6T9KUHLOX9z5VbJ0yH93psdksiz+LDSp0xSt6eKFROTbLYup7V89OjdpuNxO3BTNcM6 oAzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Ymgw9EJaoycqtcZPMuEs2zZSi51jWFMW40h/C1BZ008=; b=c64SKcQWStEkdOXkz5Xy/QuHkA8vyUXXlyRzKCQfpGNJD1W1HAKfqisuigVAUYwuJM TQzDmnQcRZf1zVjn//RMH5vzsenb6L0ss+rYr3NkuFj6pFf1zkTrOLI3/3Hq/XlXY+20 LAX4y0taztkUm+MGG2Wu9B+yQsDl+vSWMmEyPcr/CJ3it9Dc7MpMGausCVFUKI56xsN6 p1YOj11upgH2d6W9V0dO1lqdzUwXvaXenrbT+LcLDRXTsyKGsAME9vXFWziGbkoNohUM YlgYLq4tLw5JwFHEmQ11/TZubBS+qoBuoMXikkB4m2kzIR+VcStxeMNO7cxRbL+qGPp7 f+9A== X-Gm-Message-State: AOAM532fWVTNialsLXXMERxdStxo/luvCPKEX2nON1hnga4/ROvm8RGa rS+EFu/b5yl6EpeXA+pC6fIBK82QO/cJm1V1TcI= X-Google-Smtp-Source: ABdhPJy2DYJxMvjUDXZ6jJ+B/6hdW7FjC1DhvCIlIXX7FiPrzkb5OT/hVQe7Y0+V+LeM2mtkrzPYywAoBnrDrXNIDcE= X-Received: by 2002:a05:6902:210:: with SMTP id j16mr26454420ybs.122.1610813798341; Sat, 16 Jan 2021 08:16:38 -0800 (PST) MIME-Version: 1.0 References: <20210115153049.3353008-1-f4bug@amsat.org> <20210115153049.3353008-6-f4bug@amsat.org> <7fcb40af-12a4-8926-b612-34d21988baf5@amsat.org> In-Reply-To: From: Bin Meng Date: Sun, 17 Jan 2021 00:16:26 +0800 Message-ID: Subject: Re: [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Alistair Francis , "qemu-devel@nongnu.org Developers" , Jean-Christophe Dubois , qemu-arm , Peter Chubb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2d; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 16:16:42 -0000 Hi Philippe, On Sun, Jan 17, 2021 at 12:12 AM Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/16/21 4:59 PM, Bin Meng wrote: > > Hi Philippe, > > > > On Sat, Jan 16, 2021 at 11:21 PM Philippe Mathieu-Daud=C3=A9 wrote: > >> > >> Hi Bin, > >> > >> On 1/16/21 2:57 PM, Bin Meng wrote: > >>> On Fri, Jan 15, 2021 at 11:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > >>>> > >>>> When the block is disabled, only the ECSPI_CONREG register can > >>>> be modified. Setting the EN bit enabled the device, clearing it > >>> > >>> I don't know how this conclusion came out. The manual only says the > >>> following 2 registers ignore the write when the block is disabled. > >>> > >>> ECSPI_TXDATA, ECSPI_INTREG > >> > >> 21.4.5 Reset > >> > >> Whenever a device reset occurs, a reset is performed on the > >> ECSPI, resetting all registers to their default values. > >> > >> My understanding is it is pointless to update them when the > >> device is in reset, as they will get their default value when > >> going out of reset. > > > > I have a different understanding. When ECSPI_CONREG[EN] is cleared, > > it's like a hardware reset, and the ECSPI takes the following action: > > > > "Whenever a device reset occurs, a reset is performed on the > > ECSPI, resetting all registers to their default values." > > > > Chapter 21.4.5 Reset does not mention what's the hardware behavior afte= rwards. > > > > So my understanding is: afterwards, the software can still write to > > various registers, unless the register description tells us it's > > ignored. > > > >> > >>> > >>>> "disables the block and resets the internal logic with the > >>>> exception of the ECSPI_CONREG" register. > >>>> > >>>> Move the imx_spi_is_enabled() check earlier. > >>>> > >>>> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > >>>> chapter 21.7.3: Control Register (ECSPIx_CONREG) > >>>> > >>>> Signed-off-by: Philippe Mathieu-Daud=C3=A9 > >>>> --- > >>>> hw/ssi/imx_spi.c | 26 ++++++++++++++++---------- > >>>> 1 file changed, 16 insertions(+), 10 deletions(-) > >>>> > >>>> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > >>>> index ba7d3438d87..f06bbf317e2 100644 > >>>> --- a/hw/ssi/imx_spi.c > >>>> +++ b/hw/ssi/imx_spi.c > >>>> @@ -322,6 +322,21 @@ static void imx_spi_write(void *opaque, hwaddr = offset, uint64_t value, > >>>> DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", imx_spi_reg_name(index)= , > >>>> (uint32_t)value); > >>>> > >>>> + if (!imx_spi_is_enabled(s)) { > >>>> + /* Block is disabled */ > >>>> + if (index !=3D ECSPI_CONREG) { > >>>> + /* Ignore access */ > >>>> + return; > >>>> + } > >>>> + s->regs[ECSPI_CONREG] =3D value; > >> > >> [*] > >> > >>>> + if (!(value & ECSPI_CONREG_EN)) { > >>>> + /* Keep disabled */ > >>> > >>> So other bits except ECSPI_CONREG_EN are discarded? The manual does > >>> not explicitly mention this but this looks suspicious. > >> > >> See in [*], all bits from the register are updated. We simply check > >> ECSPI_CONREG_EN to see if we need to go out of reset. > > > > Oops, I missed the [*] line. Now I have read this carefully, and found > > there is one problem: > > > > Now with the new logic the device reset activity has been postponed > > until next time a device register is written. This is wrong. > > Yes, I just realized that in the imx_spi_read() function. > > > > >> > >> See: > >> > >> 21.5 Initialization > >> > >> This section provides initialization information for ECSPI. > >> > >> To initialize the block: > >> > >> 1. Clear the EN bit in ECSPI_CONREG to reset the block. > >> 2. Enable the clocks for ECSPI. > >> 3. Set the EN bit in ECSPI_CONREG to put ECSPI out of reset. > >> 4. Configure corresponding IOMUX for ECSPI external signals. > >> 5 Configure registers of ECSPI properly according to the > >> specifications of the external SPI device. > >> > >> And ECSPI_CONREG_EN bit description: > >> > >> SPI Block Enable Control. This bit enables the ECSPI. This bit > >> must be set before writing to other registers or initiating an > >> exchange. Writing zero to this bit disables the block and resets > >> the internal logic with the exception of the ECSPI_CONREG. The > >> block's internal clocks are gated off whenever the block is > >> disabled. > >> > >> > >> I simply wanted to help you. I don't want to delay your work, so > >> if you think my approach is incorrect, suggest Peter to queue your > >> v5 or resend it (once riscv-next is merged) as v8. > > > > Thank you for the help. I mentioned in an earlier thread before, that > > my view was not to fix it until it's broken as the v5 series can > > satisfy my work. But since you pointed out various spec violation > > stuff related to device reset, I do think your findings make sense. So > > let's improve this model together. :) > > I'm not mad, just I'm doing too many things and I should rather review > your ssi-sd series. I don't have the physical hardware (neither know the > firmware using it) so it is a bit dumb of me to code blindly with no > possibility of testing. If you think this series is going the good way, > it would be great if you can give it another try, and I will be happy > to review. Sure I will see if I can find a hardware to verify the register write behavior when ECSPI is disabled. Regards, Bin From MAILER-DAEMON Sat Jan 16 17:10:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l0tlx-0002fK-ME for mharc-qemu-arm@gnu.org; Sat, 16 Jan 2021 17:10:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l0oRj-0007v9-UG for qemu-arm@nongnu.org; Sat, 16 Jan 2021 11:29:05 -0500 Received: from mail-qt1-x82f.google.com ([2607:f8b0:4864:20::82f]:42588) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l0oRi-0007tv-00 for qemu-arm@nongnu.org; Sat, 16 Jan 2021 11:29:03 -0500 Received: by mail-qt1-x82f.google.com with SMTP id e15so8337391qte.9 for ; Sat, 16 Jan 2021 08:28:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9vkaKqpFog4RJaXK06vFucVy6NaXyIRoCFanRKsv9UY=; b=nTvJX/hJ0W2GnVAQEyF85c1V7l20NwfxJzTENzyvasAOCrwnjoCAKJTVNbfsTUJXtz 4lnf3X7qjksnfQ13KSCmg4whpJDsjnYMYtQNpXWaV5xbnnPetDw/FG+KP+kVfi1WUk4C CgWRlQzlSdbSnKfMpTkUBVbIZEUFbHp5P9EluSkRN8f8nM6ShN3GOC49+GIlU3AAS/ks 2qAf8WYMhutBNCT9iEi332b1/VZpJs8QyB+4FSV7w0uoMnFGKmz6gE+3YziGZ/Jzwebc A4Zgpf3CO8Ma9lqnCWN7ODcxCmvO6/LUuxwUQEZnLGto+Lz+EpmYK6VFrv76+2vuttwc y60Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9vkaKqpFog4RJaXK06vFucVy6NaXyIRoCFanRKsv9UY=; b=ZeK/T1B9PtdxFUUVgHlEGug9DLUWqGD4HNFpoK/vzIA0x6U6GYoP664PzOR6FBpA9S G9jfi0ekOPsZNiqnWvzyJBm1vt6wgtYfX6JKKkTv+iTIVXGmuqtZC9yAXhedI/1O3tKH XOsI+Lw8YWc6uST2yQr2xxgZiTgzMptiz9socrgalPQXnc2NSDhtInwJFtC5bd1Yi1+U uA65K4GNdHKioaHp7rS3rhtCdmPYh8D7RnnlNLxS044jDEi2VwggT8VYtxvxQGry5bxI q65rSwmxsmf5dg84puXtJOcKiHtwjY+Mdq6eF7nGltbYAXFV/WvazAFglZCS0coHMnTD nBTA== X-Gm-Message-State: AOAM530DxT0j5Ya8iHEj1XBWEkXLgS0qBm+aN6gJbvwAH1KzimFc+GjV e3/HTw4QvoDFBt/KUvx03H3WVcBLjXfzX6zBgDFoKA== X-Google-Smtp-Source: ABdhPJwyJoR9EfBTynvvmFmahAEGAe5jhGlODcjl/g7iH6r7e9niX51UpkpxperKWXSRk2ZflalwVdYgI8k+RTb0sNM= X-Received: by 2002:a05:622a:303:: with SMTP id q3mr16114033qtw.235.1610814538072; Sat, 16 Jan 2021 08:28:58 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-9-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-9-richard.henderson@linaro.org> From: Warner Losh Date: Sat, 16 Jan 2021 09:28:47 -0700 Message-ID: Subject: Re: [PATCH v3 08/21] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE To: Richard Henderson Cc: QEMU Developers , Peter Maydell , qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="00000000000057592a05b906fcc0" Received-SPF: none client-ip=2607:f8b0:4864:20::82f; envelope-from=wlosh@bsdimp.com; helo=mail-qt1-x82f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 16 Jan 2021 17:10:16 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jan 2021 16:29:05 -0000 --00000000000057592a05b906fcc0 Content-Type: text/plain; charset="UTF-8" On Fri, Jan 15, 2021 at 3:56 PM Richard Henderson < richard.henderson@linaro.org> wrote: > These constants are only ever used with access_ok, and friends. > Rather than translating them to PAGE_* bits, let them equal > the PAGE_* bits to begin. > > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson > This looks OK to me. Reviewed-by: Warner Losh > --- > bsd-user/qemu.h | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h > index f8bb1e5459..4076adabd0 100644 > --- a/bsd-user/qemu.h > +++ b/bsd-user/qemu.h > @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; > > /* user access */ > > -#define VERIFY_READ 0 > -#define VERIFY_WRITE 1 /* implies read access */ > +#define VERIFY_READ PAGE_READ > +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) > > -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) > +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) > { > - return page_check_range((target_ulong)addr, size, > - (type == VERIFY_READ) ? PAGE_READ : > (PAGE_READ | PAGE_WRITE)) == 0; > + return page_check_range((target_ulong)addr, size, type) == 0; > } > > /* NOTE __get_user and __put_user use host pointers and don't check > access. */ > -- > --00000000000057592a05b906fcc0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id x17sm24097616wro.40.2021.01.17.09.28.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 17 Jan 2021 09:28:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH 18/18] hw/core/qdev: Display warning for devices missing migration state To: Peter Maydell , "Dr . David Alan Gilbert" Cc: QEMU Developers , Eduardo Habkost , Artyom Tarasenko , qemu-arm , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Marcel Apfelbaum , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Andrew Baumann , Joel Stanley , Subbaraya Sundeep , Mark Cave-Ayland , Laurent Vivier , Gerd Hoffmann , Andrew Jeffery , Juan Quintela References: <20200703201911.26573-1-f4bug@amsat.org> <20200703201911.26573-19-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sun, 17 Jan 2021 18:28:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.252, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 17:29:01 -0000 On 7/9/20 9:14 PM, Peter Maydell wrote: > On Fri, 3 Jul 2020 at 21:19, Philippe Mathieu-Daudé wrote: >> >> When built with --enable-qdev-debug, QEMU displays warnings >> listing devices missing migration state: >> >> $ qemu-system-arm -S -M spitz >> qemu-system-arm: warning: missing migration state for type: 'pxa270-c0-arm-cpu' >> qemu-system-arm: warning: missing migration state for type: 'serial' >> qemu-system-arm: warning: missing migration state for type: 'pxa2xx-pcmcia' >> qemu-system-arm: warning: missing migration state for type: 'pxa2xx-pcmcia' >> qemu-system-arm: warning: missing migration state for type: 'pxa2xx-i2c-slave' >> qemu-system-arm: warning: missing migration state for type: 'pxa2xx-i2c-slave' >> qemu-system-arm: warning: missing migration state for type: 'ads7846' >> qemu-system-arm: warning: missing migration state for type: 'max1111' >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> RFC because there might be something simpler than --enable-qdev-debug. > > I think where we'd like to get to is installing a migration > blocker if the machine has any devices which don't have a vmsd. > But for that we'd need to be pretty sure we'd got all the devices > on machines where we care about migration, and we're clearly a > fair way from that (eg we need to do something about the > devices like the CPU which don't have a vmsd but handle their > migration some other way so they don't trigger the condition > for warning/migration-blocker). Dave made a comment about it, I'd rather let him have a look. > I don't have a strong objection to this --enable-qdev-debug, I guess. > Another option halfway between this and a full migration-blocker > would be do a warn_report() for the relevant devices when savevm > tries to migrate them. OK. The problem is vmstate_save_state() is not qdev specific, it migrates a blob, which we can not report much about. I'll repost using 2 warnings. Thanks for your review, Phil. From MAILER-DAEMON Sun Jan 17 14:24:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DfT-0007aX-Ur for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:24:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DfS-0007aH-4Q; Sun, 17 Jan 2021 14:24:54 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46915) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DfQ-0004xA-GL; Sun, 17 Jan 2021 14:24:53 -0500 Received: by mail-wr1-x42d.google.com with SMTP id d13so14416630wrc.13; Sun, 17 Jan 2021 11:24:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F8qCNXZtPekis67hGa+ueKXZTEHHyBdE0u5HnMX1Wj0=; b=aY9yoYBvccEwHQQuFjtH4qM2Egwvr5pC619dstatdykra3nnpHBvtBooP/AjZdXmim scMFbQZkn1G01Tq4+gTmlUzenvdMStM4pbrfvcIDnOCS/cns1RvsVEC+gav/hJO8Lxy/ STA3bh88X1sxN19ePfyrgqmoidJIEg4kwiCCYNra1GKeyeiExGQg4VP9GjogUBYxMsGN vVGexD3c+sZJ3k2nJSooHeCVe4xdNr7OheX5XYZCMRXIRzAgxmUTBpB8btKFGVaqRqlH Vnkou7CD34IRq3wP/9fijtv+Zvl/3+1huIPieC/Sko869W8S3LBZgxitWCQqt/pBVk7p Seew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=F8qCNXZtPekis67hGa+ueKXZTEHHyBdE0u5HnMX1Wj0=; b=nDWpsSc4PVnQ0tATlvewKxSmxqFnBwbE2f1gBoHHiA8drhhOm1nN4MdjPmkZaWPEwe OAl0MYWLK5MeP76xjkcONwAO9O7IsXA0Km/55gxK+9I3DSDuUfTOYXdG0j8cYzeomj69 1DriQwVPZQCcaOkh96mO1pN1yADkVIz6eY9YextGYen13RwT9ekmIHQVO5OpWgZO9c2I Ln4B20mwOwBYRK780HfSuk3sqaSXtsGkiRvZDrga5LIYvxnDYOw48jZ8fJGSEpur3Y47 Q+RWEcj8bwpMFla4DZgV/y+4RWvbNTI2eP7PdKp48j9FUz2EzWoJQcMi2wrPq67yM43V URWg== X-Gm-Message-State: AOAM533U+qZwB2Qx5bS4Yq5iar1EEXmWja909Xu707Uz/9bmcrW7VIhc 9i2j27FWMVUlmB+irZy3WD8= X-Google-Smtp-Source: ABdhPJwqdje/upgYSv+MB4kKgkx6Xo3O4sJdAzqnxt+SxFbe/F3MKmD2DPpUVh82CVSHiiYN8mukNA== X-Received: by 2002:adf:f18a:: with SMTP id h10mr23998266wro.244.1610911490374; Sun, 17 Jan 2021 11:24:50 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u16sm13058661wrn.68.2021.01.17.11.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:24:49 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 00/20] hw: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:26 +0100 Message-Id: <20210117192446.23753-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:24:54 -0000 Since v1:=0D - Tried to address Dave and Daniel comments=0D - Added Peter R-b=0D - Handle GPEX device=0D =0D This is a proof-of-concept after chatting with Peter Maydell=0D on IRC last year.=0D =0D Introduce the vmstate_no_state_to_migrate structure, and=0D a reference to it: vmstate_qdev_no_state_to_migrate.=0D Use this reference in devices with no fields to migrate.=0D =0D This is useful to catch devices missing vmstate, such:=0D - ads7846=0D - mcf-uart=0D - mcf-fec=0D - versatile_i2c=0D - ...=0D =0D v1: https://www.mail-archive.com/qemu-devel@nongnu.org/msg719788.html=0D =0D Philippe Mathieu-Daud=C3=A9 (20):=0D migration/vmstate: Restrict vmstate_dummy to user-mode=0D hw/core/qdev: Add vmstate_qdev_no_state_to_migrate=0D hw/arm/armv7m: Mark the device with no migratable fields=0D hw/arm/aspeed_soc: Mark the device with no migratable fields=0D hw/arm/bcm283x: Mark devices with no migratable fields=0D hw/arm/msf2-soc: Mark the device with no migratable fields=0D hw/core/split-irq: Mark the device with no migratable fields=0D hw/cpu/a9mpcore: Mark the device with no migratable fields=0D hw/cpu/cluster: Mark the device with no migratable fields=0D hw/usb/hcd-ohci: Mark the device with no migratable fields=0D hw/intc/arm_gicv2m: Mark the device with no migratable fields=0D hw/misc/armsse-cpuid: Mark the device with no migratable fields=0D hw/misc/iotkit-sysinfo: Mark the device with no migratable fields=0D hw/misc/unimp: Mark the device with no migratable fields=0D hw/nubus/mac-nubus-bridge: Mark the device with no migratable fields=0D hw/sparc64/sun4u: Mark devices with no migratable fields=0D hw/pci-host/gpex: Mark device with no migratable fields=0D hw/core/qdev: Display warning for devices missing migration state=0D stubs/vmstate: Add VMSTATE_END_OF_LIST to vmstate_user_mode_cpu_dummy=0D migration/vmstate: Simplify vmstate for user-mode CPU=0D =0D configure | 10 ++++++++++=0D meson.build | 1 +=0D hw/usb/hcd-ohci.h | 2 ++=0D include/hw/arm/bcm2836.h | 5 +++--=0D include/hw/arm/msf2-soc.h | 11 ++++++-----=0D include/hw/core/cpu.h | 2 +-=0D include/hw/cpu/a9mpcore.h | 3 ++-=0D include/hw/qdev-core.h | 2 ++=0D include/migration/vmstate.h | 2 +-=0D hw/arm/armv7m.c | 1 +=0D hw/arm/aspeed_soc.c | 1 +=0D hw/arm/bcm2835_peripherals.c | 1 +=0D hw/arm/bcm2836.c | 1 +=0D hw/arm/msf2-soc.c | 1 +=0D hw/core/qdev.c | 8 ++++++++=0D hw/core/split-irq.c | 1 +=0D hw/cpu/a9mpcore.c | 1 +=0D hw/cpu/cluster.c | 1 +=0D hw/intc/arm_gicv2m.c | 2 ++=0D hw/misc/armsse-cpuid.c | 1 +=0D hw/misc/iotkit-sysinfo.c | 1 +=0D hw/misc/unimp.c | 1 +=0D hw/nubus/mac-nubus-bridge.c | 1 +=0D hw/pci-host/gpex.c | 1 +=0D hw/sparc64/sun4u.c | 6 +++++-=0D hw/usb/hcd-ohci.c | 1 +=0D migration/vmstate.c | 7 +++++++=0D stubs/vmstate.c | 7 ++++++-=0D 28 files changed, 70 insertions(+), 12 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 17 14:25:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dfl-0007dW-0n for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id g10sm15146735wmq.3.2021.01.17.11.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:24:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 01/20] migration/vmstate: Restrict vmstate_dummy to user-mode Date: Sun, 17 Jan 2021 20:24:27 +0100 Message-Id: <20210117192446.23753-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:07 -0000 'vmstate_dummy' is special and only used for user-mode. Rename it to something more specific. It was introduced restricted to user-mode in commit c71c3e99b8 ("Add a vmstate_dummy struct for CONFIG_USER_ONLY") but this restriction was later removed in commit 6afc14e92ac ("migration: Fix warning caused by missing declaration of vmstate_dummy"). Avoid the missing declaration warning by adding a stub for the symbol, and restore the #ifdef'ry. Suggested-by: Daniel Berrangé Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- include/migration/vmstate.h | 4 +++- stubs/vmstate.c | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 140fa32a5e3..c79a58db9b9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1132,7 +1132,7 @@ bool target_words_bigendian(void); #ifdef CONFIG_SOFTMMU extern const VMStateDescription vmstate_cpu_common; #else -#define vmstate_cpu_common vmstate_dummy +#define vmstate_cpu_common vmstate_user_mode_cpu_dummy #endif #define VMSTATE_CPU() { \ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..dda65c9987d 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,7 +194,9 @@ struct VMStateDescription { const VMStateDescription **subsections; }; -extern const VMStateDescription vmstate_dummy; +#if defined(CONFIG_USER_ONLY) +extern const VMStateDescription vmstate_user_mode_cpu_dummy; +#endif extern const VMStateInfo vmstate_info_bool; diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8da777a1fb4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,7 +1,9 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" -const VMStateDescription vmstate_dummy = {}; +#if defined(CONFIG_USER_ONLY) +const VMStateDescription vmstate_user_mode_cpu_dummy = {}; +#endif int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dfs-0007fA-5y for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dfc-0007cl-Tu; Sun, 17 Jan 2021 14:25:05 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dfb-00050E-4t; Sun, 17 Jan 2021 14:25:04 -0500 Received: by mail-wm1-x32e.google.com with SMTP id e15so5645117wme.0; Sun, 17 Jan 2021 11:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rOquWOYfnZ1HWefCZ4bvuH3r0gldDGI6o719tcrABHg=; b=EYnYeiQhZt4kdpurJRBjpjb/bcj/11MzVB6hWoOub2Sp7mN8xZudoHD1j7ZrWLtX8b RoZq9fdOkXGhavJbK4w2KZ1U4vmkeqpQcgbobilX16Ho2RzHV78cR5aDm4KihvLCNsGB 40Aq534HHEQK0hjW321NaI4/R0zR4TpTnpi7EZHcuTkRJvpZedDO0yHfqOYe5Kgpzis1 /8fU/glBDGWlwlF7gpsh+z2eman6W7+dn4l9ycIV1mNS78snMvDt7T61OWT7NTKyd+1I nwYp5hA29Iti93NhAi6Hd8T6fDmYU0KpiX0fI3r9UK909pE+LSLosLz/E7e380/rSPxd 1NQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rOquWOYfnZ1HWefCZ4bvuH3r0gldDGI6o719tcrABHg=; b=KC5qs/UbJ7mIjkEhn3JrQCNaEmkv15qqT0SLfVbtbpJ8JjK/SpLXlKFlLqo5tEo+Rn TP5xb4elHHz1dQYeyhO1vJffzy1ob73Y3Cbi9vldOfhgad7nwrpCTgAN7UCMj1AzBNlp aFjJpDzMDgggT0xjFbynrsQpFhX16ncJoF4QQZYLVkdVIRoMXdMoEQHvzqkHv1I2ir3k b7734xV+8clmAVtxege5SxikdYrZWIFBBbxS7HtOWuK1XCxWccb5k2TtyDKlRViOJZ7O SBDvhhJRtMJfSdjglM/h7vEUZDhsj2aOIvoOq/Fwr/foi2dgLexPyVoG8okf63v69CMr 4OFg== X-Gm-Message-State: AOAM531eI84xDbpTc8R0rTY1p4kWapkjWeYrgznHErE3YynfnzlLXUoh 1+JKyDuo8FcdEQ1BMUfwiKM= X-Google-Smtp-Source: ABdhPJxBDmPKuKJLqL7gFLmi+ElRcs/UoRPsNdLu+sTc3B0ONi5NIEEYj38j6gv73oHIYgSH7GkpSg== X-Received: by 2002:a1c:99d1:: with SMTP id b200mr17629965wme.37.1610911501420; Sun, 17 Jan 2021 11:25:01 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c7sm26812421wro.16.2021.01.17.11.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 02/20] hw/core/qdev: Add vmstate_qdev_no_state_to_migrate Date: Sun, 17 Jan 2021 20:24:28 +0100 Message-Id: <20210117192446.23753-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:11 -0000 Add vmstate_qdev_no_state_to_migrate, which is simply a pointer to vmstate_no_state_to_migrate. This way all qdev devices (including "hw/qdev-core.h") don't have to include "migration/vmstate.h". Signed-off-by: Philippe Mathieu-Daudé --- Unresolved issues: https://www.mail-archive.com/qemu-devel@nongnu.org/msg721695.html Peter: > Does this definitely not put any data into the migration stream? > We don't want to change what's on the wire for machines that > use devices that start using this. (If it does by default, it > would be easy to make the migration code special case the > magic symbol to act like "no vmsd specified"). https://www.mail-archive.com/qemu-devel@nongnu.org/msg727634.html Dave: > I'd need to test it to be sure, but I think if we added a .needed > to vmstate_no_state_to_migrate with a function that always returned > false, then I think the stream would stay unchanged. --- include/hw/qdev-core.h | 2 ++ include/migration/vmstate.h | 1 + hw/core/qdev.c | 3 +++ migration/vmstate.c | 7 +++++++ stubs/vmstate.c | 7 +++++++ 5 files changed, 20 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index bafc311bfa1..d2c7a46e6a2 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -140,6 +140,8 @@ struct DeviceClass { const char *bus_type; }; +extern const VMStateDescription *vmstate_qdev_no_state_to_migrate; + typedef struct NamedGPIOList NamedGPIOList; struct NamedGPIOList { diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index dda65c9987d..50559598eac 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -197,6 +197,7 @@ struct VMStateDescription { #if defined(CONFIG_USER_ONLY) extern const VMStateDescription vmstate_user_mode_cpu_dummy; #endif +extern const VMStateDescription vmstate_no_state_to_migrate; extern const VMStateInfo vmstate_info_bool; diff --git a/hw/core/qdev.c b/hw/core/qdev.c index cefc5eaa0a9..f0d0afd438d 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -44,6 +44,9 @@ static bool qdev_hot_added = false; bool qdev_hot_removed = false; +const VMStateDescription *vmstate_qdev_no_state_to_migrate = + &vmstate_no_state_to_migrate; + const VMStateDescription *qdev_get_vmsd(DeviceState *dev) { DeviceClass *dc = DEVICE_GET_CLASS(dev); diff --git a/migration/vmstate.c b/migration/vmstate.c index 05f87cdddc5..2c373774dfa 100644 --- a/migration/vmstate.c +++ b/migration/vmstate.c @@ -20,6 +20,13 @@ #include "qemu/error-report.h" #include "trace.h" +const VMStateDescription vmstate_no_state_to_migrate = { + .name = "empty-state", + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + static int vmstate_subsection_save(QEMUFile *f, const VMStateDescription *vmsd, void *opaque, JSONWriter *vmdesc); static int vmstate_subsection_load(QEMUFile *f, const VMStateDescription *vmsd, diff --git a/stubs/vmstate.c b/stubs/vmstate.c index 8da777a1fb4..f561f9f39bd 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -5,6 +5,13 @@ const VMStateDescription vmstate_user_mode_cpu_dummy = {}; #endif +const VMStateDescription vmstate_no_state_to_migrate = { + .name = "empty-state", + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dft-0007g0-B2 for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dfq-0007eZ-2C; Sun, 17 Jan 2021 14:25:18 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dfo-00052P-NO; Sun, 17 Jan 2021 14:25:17 -0500 Received: by mail-wr1-x430.google.com with SMTP id v15so10793792wrx.4; Sun, 17 Jan 2021 11:25:13 -0800 (PST) DKIM-Signature: v=1; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id r2sm25630352wrn.83.2021.01.17.11.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 04/20] hw/arm/aspeed_soc: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:30 +0100 Message-Id: <20210117192446.23753-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:19 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7eefd54ac07..b503d32fef6 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -407,6 +407,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) dc->realize = aspeed_soc_realize; /* Reason: Uses serial_hds and nd_table in realize() directly */ dc->user_creatable = false; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, aspeed_soc_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dft-0007ha-Vb for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dfk-0007dV-O3; Sun, 17 Jan 2021 14:25:14 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:38783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dfg-00051O-At; Sun, 17 Jan 2021 14:25:10 -0500 Received: by mail-wm1-x32a.google.com with SMTP id y187so12067502wmd.3; Sun, 17 Jan 2021 11:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wgGk6yPxUB2DXYQxZxUZbUfoW7pWWFaws3b1nVoeQJI=; b=bqRm9TOuPkd2JJzuiyB3+fC/IaQmbzS4vjNWsXGFo8+5Mflus030NR2kBkBcyAY/TY dX3c8vZ7mTigiWmGz1TjoZtig2/ssKmjq325+fujlQL59FlqKNOSopcsHzOYrOaSepVf 4cAzYJILLGjz+GqgDA49atJK3MjD4tSF2eM5Ob1d0QiXVE0XTaHHwDfRTva9SAAddjDR 8on2onc7unLskg1eeRVvy6qMjk+UCmlJZRW1lMCmco3StadumZWmL6EidgQVa2Cci5Ng Yxlzv7LoOeScwOMTeFppoXhfkx+A8a+7/anoWV68P/Nc1kWtENblYlvDQGnX8OgnS2Rg qtgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wgGk6yPxUB2DXYQxZxUZbUfoW7pWWFaws3b1nVoeQJI=; b=bvJisTFXWKpJ2Sb1f+rIHH9YfUR6OxvqnyyUW+3TcAWUPijTwIvLU6TbngK9nHELHr jnH/dF203lKWDqwQXo7no1VMZJDUnapiAOGROwkyjdYZFw3C2PEDIOn7VdbaZiJzYApC +dsuN22q8fbyV0oFjXpMZpoDg06+mfUS7BpSiiyvE1M6/P61Sq1FcZZoseS7KpPnEQUy DNTzZl3twq9z07eJew2mdWwvvEoFcExyaFEzj2re76o4yoiTiSpLORzbVineKDOQdgxu XVliurjkkpc8nZX2CN+P9m9FkeJ3KwC/YoAtLA1qjYh33rTPcLfDc0i12vgHFJLdg/qf 1Mnw== X-Gm-Message-State: AOAM531LwC8KxVgqfUzZKnPYPk0yY6pg027Q1qx2RKJheQzUG9BgIEjG bSLxugjMBRNgmgrZ9jmH7Ik= X-Google-Smtp-Source: ABdhPJwpd7o10gr0UWFsvUMmVK3jnwDM/gu8QrHjDx+1/Q3pAUJsv7+0OC7//09bWuFgQ+VEzCWJFQ== X-Received: by 2002:a1c:e255:: with SMTP id z82mr9888944wmg.60.1610911506845; Sun, 17 Jan 2021 11:25:06 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id g132sm7677099wmg.2.2021.01.17.11.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 03/20] hw/arm/armv7m: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:29 +0100 Message-Id: <20210117192446.23753-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:17 -0000 The TYPE_BITBAND device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- v2: Reworded (Peter) --- hw/arm/armv7m.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8224d4ade9f..41ac1b88ab4 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -347,6 +347,7 @@ static void bitband_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = bitband_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, bitband_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dfu-0007jO-Hf for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dft-0007fD-1w; Sun, 17 Jan 2021 14:25:21 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:46918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dfr-00054R-I4; Sun, 17 Jan 2021 14:25:20 -0500 Received: by mail-wr1-x42e.google.com with SMTP id d13so14417271wrc.13; Sun, 17 Jan 2021 11:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qdebcebcEgAUy36pbkwOtCiC8gYa7FMBNTjw+ZgzJr8=; b=okh6rYyT8WPB0Ldi5fnznckOXxu8R9A29W7mOana5evBSJUO9M+PZ+mXlLmf12WOoE 5jGrSGADlg8sUsn4uA0vkc74lAAqe/Qo4RqoQzjoh989ikJDMP2WHAYOBZgx6olSyBW0 rEIpmWGBSK/ojnfD51oSIXJeIMvHoJYWhSE7823T+P+txI7hi33ylobdsh10L1kGJDRj 7t/rEYZ2CHvxACFy9OUpIsfexlmg/zHHRh2ReiVK/aoODvSgQL+HVhKoAmcg2BfW66RZ yFkJCS2BTSzCngRyJ+m0NoAa4xWon5eo71UfslsmaPo81qwsbR6rGMRskT2guhxyRpbB c+tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qdebcebcEgAUy36pbkwOtCiC8gYa7FMBNTjw+ZgzJr8=; b=rcqtMv1BgceMZq0tjKQy5KecbA325kZzSFcGXduq1FHzGt115FlXRdHMPxWRnh8dIe f2g/FDeEXqSnyQ9iQQ5FC2j4F/HVcw94ej8hHGJG5tZLinm/Tt/DPYVOqQVREXj+++R0 S06dpwL6Qe0Rbr7igfL8wI2hkM+gYsjfz0RnzYMB5lWf0w0/JKH1B0xuJ6rsMIGh+Dun tptFVjbHC8F6wKySY1zBgty3SXAlKQkxmAmnpcjIDK1mtFNWiW/IdgXFFLTMuz1UGH/v vZKq+fFGtLA+vlTdU2UxSZ8DuPu7ieShCCpIr9GI1NTKrocAptnuoa3CcAKwP+RtmF17 A4lg== X-Gm-Message-State: AOAM531Szrj9BSnMggIrmKNLelMsSO8j60aZbU9sh7PYl1OYMsE3qPan MGGi4Z6Ug+jCjzQ1r+JRF6k= X-Google-Smtp-Source: ABdhPJxbcsgYoEjcTophK/SL5VZkGui8pHNjy61kf97Brgh1NWMVJ2NHSLes7iCFjvWlfgu/zrgpfA== X-Received: by 2002:a05:6000:368:: with SMTP id f8mr22623971wrf.150.1610911518019; Sun, 17 Jan 2021 11:25:18 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id b13sm23004714wrt.31.2021.01.17.11.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 05/20] hw/arm/bcm283x: Mark devices with no migratable fields Date: Sun, 17 Jan 2021 20:24:31 +0100 Message-Id: <20210117192446.23753-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:21 -0000 These devices don't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/bcm2836.h | 5 +++-- hw/arm/bcm2835_peripherals.c | 1 + hw/arm/bcm2836.c | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3a..becb6cfd0a7 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -35,13 +35,14 @@ struct BCM283XState { DeviceState parent_obj; /*< public >*/ - uint32_t enabled_cpus; - struct { ARMCPU core; } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; + + /* Properties */ + uint32_t enabled_cpus; }; #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index dcff13433e5..8cf85f028fd 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -386,6 +386,7 @@ static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = bcm2835_peripherals_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; } static const TypeInfo bcm2835_peripherals_type_info = { diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index de7ade2878e..d2de99147cc 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -176,6 +176,7 @@ static void bcm283x_class_init(ObjectClass *oc, void *data) /* Reason: Must be wired up in code (see raspi_init() function) */ dc->user_creatable = false; + dc->vmsd = vmstate_qdev_no_state_to_migrate; } static void bcm2835_class_init(ObjectClass *oc, void *data) -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgD-0007s1-Ef for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dfy-0007qJ-4G; Sun, 17 Jan 2021 14:25:28 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dfw-00058Q-Ph; Sun, 17 Jan 2021 14:25:25 -0500 Received: by mail-wr1-x42f.google.com with SMTP id w5so14425576wrm.11; Sun, 17 Jan 2021 11:25:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B4YUxFFcqfLKGc47lrHSN4rEV4rWS7YudCY+3T61Wdo=; b=Hw+879i6FA5pURTaL7CQP+GLpMvdsoTGDwnuQ+9kmBYGhIiHk1hqFo/fNuYG49S7Wl 2VviseMlvQfKy4hIX/zQDtdlIVAsWtfX+WMiImMd5c+/kdHvARiAQxuSb8t+GEJOV7QL Y5ZZzst3Q4Y1CXWklRHxqOOlpl3jwMDJ1hqORJP9N1QFTFnFc1Haq4r/FPLUOttFlGO1 0v0F7W3WXOL5BWGK5dKbCN3NbtqsMULQMiAhSmBAuJ1bA4Dr3UWI4Pdy+4c2o4/MZrhK QC5cbq9CHb1EvOgXzYwwizz0TGeOI11Uvv0kfmwo9V9odEnabftjxLlu6nRGtwTlUPVl NGmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=B4YUxFFcqfLKGc47lrHSN4rEV4rWS7YudCY+3T61Wdo=; b=L3NPhxW5pTRqxaudwRgHXW/IpNe1SZkozztDOzrYOME16qlaFB0QWWiYPH+tH8Pedk GXDbufQPSAr1K1F1axtFLqPDsmMiq2agNYjpYX1n0a5zRyQ9UdT9bt4yObjh/StWtSHO URwB5n0PjiUx3ro6FE+cXqYZan/fgAQEsdqvOft/oeNf84YyxQKyFc7aikOWGagU3P5v WiEjcpFTuFAUjotX8qsiH70w18OdsiO6vocd0ixj5zo6tjWbdDiY/sw9ANqSnlYZP053 S0U8mRSkGVo4mIsVOwRQLNf+eEHfnVdBPRdukDFnvyjh540T/QbupJY9s+SIBHlwDL59 zf/Q== X-Gm-Message-State: AOAM530U5doEn7uubbctF9R4ph3HbY7kjCzOBTYvsXJVBCJk3ysv0AQH XEHRwxKTxgrrd27p79ze78w= X-Google-Smtp-Source: ABdhPJzt3Ub4O6C1NHK9bPfWUH2XZrh4/Rf1HIK/DEOyPDqUSdDuIUBDsNoaJDyOIgQVxwVn3BdzXw== X-Received: by 2002:a5d:47c3:: with SMTP id o3mr17313895wrc.175.1610911523243; Sun, 17 Jan 2021 11:25:23 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c11sm22974584wmd.36.2021.01.17.11.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 06/20] hw/arm/msf2-soc: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:32 +0100 Message-Id: <20210117192446.23753-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:35 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/msf2-soc.h | 11 ++++++----- hw/arm/msf2-soc.c | 1 + 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index d4061846855..41a328c77f9 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -52,6 +52,12 @@ struct MSF2State { ARMv7MState armv7m; + MSF2SysregState sysreg; + MSSTimerState timer; + MSSSpiState spi[MSF2_NUM_SPIS]; + MSF2EmacState emac; + + /* Properties */ char *cpu_type; char *part_name; uint64_t envm_size; @@ -60,11 +66,6 @@ struct MSF2State { uint32_t m3clk; uint8_t apb0div; uint8_t apb1div; - - MSF2SysregState sysreg; - MSSTimerState timer; - MSSSpiState spi[MSF2_NUM_SPIS]; - MSF2EmacState emac; }; #endif diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index d2c29e82d13..2d163710f54 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -224,6 +224,7 @@ static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = m2sxxx_soc_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, m2sxxx_soc_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgI-0007sy-1Y for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58040) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dg3-0007qh-Fk; Sun, 17 Jan 2021 14:25:34 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:37376) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dg2-0005D6-3m; Sun, 17 Jan 2021 14:25:31 -0500 Received: by mail-wm1-x336.google.com with SMTP id g10so12049085wmh.2; Sun, 17 Jan 2021 11:25:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wX5YisuWL/1kxfpeKOV4oTMHdWldWIq42qYJ2gfj7dc=; b=o70zgkLCjTk2UunB4bDarF1cLu3Jbi3yIP7VJDK7c11SrDRhmIV1yLNUdenmCjok8u 4ADSSGJ6qzqcc5l7sZO87WbUkT1bQekPohWaF331aijg6hXgpjmGh9WGnH6VEgLMQOkO mWyu/4neq/W1ekNPxcPHi3H1kTToXfUH9cwmTF23l0OoV5i9Kix8CDi9hXz9MaZxtpeV g2Z82AJbxVOrPQUSWdq2cRU6FTqfCJYXIv0kiazkBEZhqiNsOanbpt0RxMRUpDL7zns9 9oDaTS1eQ5PuTUwHQ4gJLaIVJFurBATIV05O0YiAc1FnEPPcNkONEk2KQC7IDaNn26Mn KYSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wX5YisuWL/1kxfpeKOV4oTMHdWldWIq42qYJ2gfj7dc=; b=Fpk9SIzCyYHNVllfYWtW4JJBig+ZKIdr0G3upcivLqSwera/Qv8eL1P9koP7pJy5Ug 6NzjHDvE+7nubVxKk2HS3yWiqEb1dqeV/sq6BSaIsKpX4M2e4AW5u0Kr0ZyB8iJR/tPJ o8mGZXHXpjJ2oZ4/b/1MC+wQh2v1rCCCgFwJ8i1fWnpUNZVhTVweQjrqLbzXjTXPAu3z 7U6VO0FtJN0HTsZxcBmTEidqKK14NFxDYH5/x/s9HbIoO5+3YEAnIuEI96ko2pqPLhNP YEnG2zezXQxx5nRsXl94bgUCQgSsFzBe2Ym6LiFHqpWr7+r67DdHRlTq9dBeMuwXqMgd dywg== X-Gm-Message-State: AOAM530iPcl5ceZsfzR8+Hq0WpkQG3hP67ghPZFlbcx9jmHTJGrMpWGA 0GoPlcetrSBglHMNP/Feu9Q= X-Google-Smtp-Source: ABdhPJw5tInLIHrxS25OFyOXfZ0TxV2j0sp/xO2VJT+x5kdUNjd34M8oQ5/ZX1VSSeyeFHBh8CdBVA== X-Received: by 2002:a7b:c5d6:: with SMTP id n22mr17103434wmk.70.1610911528446; Sun, 17 Jan 2021 11:25:28 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id y13sm25915641wrl.63.2021.01.17.11.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 07/20] hw/core/split-irq: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:33 +0100 Message-Id: <20210117192446.23753-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:36 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/core/split-irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c index 3b90af2e8f9..a7072f922cd 100644 --- a/hw/core/split-irq.c +++ b/hw/core/split-irq.c @@ -71,6 +71,7 @@ static void split_irq_class_init(ObjectClass *klass, void *data) /* No state to reset or migrate */ device_class_set_props(dc, split_irq_properties); dc->realize = split_irq_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; /* Reason: Needs to be wired up to work */ dc->user_creatable = false; -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgM-0007un-LH for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DgH-0007st-Dc; Sun, 17 Jan 2021 14:25:46 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:40411) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DgF-0005GX-LP; Sun, 17 Jan 2021 14:25:44 -0500 Received: by mail-wr1-x42b.google.com with SMTP id 91so14457927wrj.7; Sun, 17 Jan 2021 11:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pKKkrFO8F1VopBGRhEeTOsmc/pmqYXz+y2wSUuToQKs=; b=abdd41j0opUWZIuUA79sZKaCfzJERrHUNPpBxp+ZHP9t5WKnzb5qJ/cv5+00yp9P3/ yc4hBydIt/XHqiy2exOUhN60eGoeP36HdCZo/tb1kZCJvZfbjNBQ5WDlyVZcRvcyI8Mn WVrMYcYcgCBQCKUobw2r6oXPrKWtBDGPEfQAqzjQ+J4rXQ+ikAhLLjR+5d85ecbEmp1M d+KW1onX1CQ5tVeq++cvABJvIN6othWtak6A8KyB6IWpySztCN5T3Cl8yMagC6QUGdBa xscbS5h6OHkcwHunFjNt5cUpDuwlGjhavY5pRCoo3POvPzUEBogQ0WUqiBdeYUav7tCN Q64A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pKKkrFO8F1VopBGRhEeTOsmc/pmqYXz+y2wSUuToQKs=; b=r87EdGk6ZaVpDBJ9/Vvco7UeYO30KR6822+Gz2qf491lbAAMkYgUZQLXTpq6UFyaP5 3fRpb+0/U5E0YwNLaxi1EHejhBPku4tksy325bxurt2oVnsQPoRCoPT0Zwi3ak0VDbQ5 e8xz7PW1+bReooXmNww7vOMe9gMIWYEC1aEl08ZgUvUkGDulhL7xfMb0ghxcwcIwgbl1 gM62uuF1rZSMXpqpLFBNE+P5nrAXiU4wiw5cHUavFI9MqWgmRhRjEU599DXqvzL57We/ Be0bkPfJBbrmiTA034vIMDNGuq1cue4mPanr7Da+qxvVjE/FcgD7yJWqEgI70atGi8t1 eHzg== X-Gm-Message-State: AOAM532MxHmrn0Ly043bhgqwLOUepe5sEUKwxTbFDGAIC7CxDd4SIh4e k4tRqE+uX5NapBytUP1lx2Q= X-Google-Smtp-Source: ABdhPJxGbiZ+QMxA8NFrJPa/qsSqN3k1USt0wHaekZ09igWMoTfvqW83Tbzp8QuMl1lP5mFX7q6a0Q== X-Received: by 2002:adf:e9d2:: with SMTP id l18mr22023842wrn.179.1610911539529; Sun, 17 Jan 2021 11:25:39 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id d7sm13672923wmb.47.2021.01.17.11.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 09/20] hw/cpu/cluster: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:35 +0100 Message-Id: <20210117192446.23753-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:49 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/cluster.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index e444b7c29d1..95653a643ad 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -80,6 +80,7 @@ static void cpu_cluster_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, cpu_cluster_properties); dc->realize = cpu_cluster_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; /* This is not directly for users, CPU children must be attached by code */ dc->user_creatable = false; -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgN-0007v2-PT for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dg9-0007ra-8q; Sun, 17 Jan 2021 14:25:39 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:53206) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dg7-0005F3-Iz; Sun, 17 Jan 2021 14:25:36 -0500 Received: by mail-wm1-x334.google.com with SMTP id m187so5480459wme.2; Sun, 17 Jan 2021 11:25:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gddpL1/dTBK1hhWCBYVWNUJWRgr6oC/oPS+FjqFdg/8=; b=MEj8ltNQAsGz6HhkTJgapNBfe0IqX1RUk87fpo+4ZlDjM4zgtCwgkEp9nUF+pxxhY5 sbyps4aVG5XlxrBzXquYrG2TR2iiSM/PNhQkbTXhFF5W3NawOAc/6X5Be2TNMXrnKtNk QX5ZXm/JIPt+jd5VS/tC8RnG0RWuxJ9lh64ISrq5awvS34PUSg/uElvpNEVBJmjlhEdg sX2E+eYmia7cJDGxZSYaeKK/cFW+qVUgVfEpK9X9ZlVXG1WEwTd457arKjZpJNcyEoxf kYHOJmt554sLczGB2utJUktB12+lAFG5uYhb/oksuibma+K8nJyjTR4Jw+oWWbgiq5Ts u/ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gddpL1/dTBK1hhWCBYVWNUJWRgr6oC/oPS+FjqFdg/8=; b=EfJl9tznZJeNSaWXRQGePu5mTSLX+nSspYiUi2/i1z6iuT9T/SoOK3ccHl7XVXCLEN UuQWLwc4XhqKK18QumRG49s7Q0Iii0Qckm+tRfJBRv+MZEDGPGxFbGeJ+TZDmumEAoyD G3FxWcQrHO5hhRVqmdTEcOoz630rKoLxlX3D4twVfd0gcqqLJqzwOmAump4TEadWu0YB AhpXtY7btcLN7IQpu2+LhJRC5XR1z2hhrJW3Ty6SE5n6dCPBdDrCabcRWrS08/9BlV5n sMTjXKfPpjO9dEKA4KYY8+zQOWjFXncav0J7fa0KUbW8jUhgevSQ+OptLQZw0WtDicTm Sp9Q== X-Gm-Message-State: AOAM5328r8Gjs/8BHjrQ241aaWDidtebeJVSjPyHexv81aM8rc5vLJ4X dsGg3onsgYV8+hCniM9UIAI= X-Google-Smtp-Source: ABdhPJxPlULh+KbAeGjEMtbR6PISEiUMYiKcem1wR8wu4GDx4AmpPY28PzPGjyFikBnjS0d0AvzZzQ== X-Received: by 2002:a05:600c:2a47:: with SMTP id x7mr15892217wme.145.1610911533975; Sun, 17 Jan 2021 11:25:33 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z63sm22476855wme.8.2021.01.17.11.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 08/20] hw/cpu/a9mpcore: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:34 +0100 Message-Id: <20210117192446.23753-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:41 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/cpu/a9mpcore.h | 3 ++- hw/cpu/a9mpcore.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index e0396ab6af7..234ac13be2c 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -25,10 +25,11 @@ struct A9MPPrivState { SysBusDevice parent_obj; /*< public >*/ + /* Properties */ uint32_t num_cpu; - MemoryRegion container; uint32_t num_irq; + MemoryRegion container; A9SCUState scu; GICState gic; A9GTimerState gtimer; diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d03f57e579b..2e1d2d46b5b 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -175,6 +175,7 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = a9mp_priv_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, a9mp_priv_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgP-00080W-Oc for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DgL-0007ue-Ub; Sun, 17 Jan 2021 14:25:50 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36146) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DgJ-0005Hp-5C; Sun, 17 Jan 2021 14:25:49 -0500 Received: by mail-wr1-x436.google.com with SMTP id 6so7158530wri.3; Sun, 17 Jan 2021 11:25:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jZzarPuuax9WApxhmE01fr+TB+KCuz6yb6zkBqC3alw=; b=BjEEoijBKCngZNJ4PJZ9MgD12GyN9KvoyfaGeEFEvlCRaOIoYLXGxTatCJpEj4A7y3 QeYv14aOuInHEnyD2NXsa1mdVFUhA4VsRr4jEeV0C6EH32G6pFo0XnD9buanUxPH/Udv Pj9vdTuj8vCc5hEOHzcdAAW81FX1G1O/iPSCtd9ArbzAtBvlkn5kfY3oGmREszpgJyjq PLGcmzXandd80hwLqc8pxwMEt709t7gPmIaEl+Jhk8jwEClgjH6k0D6RnY81wPR4fZeg pooL7huiagIHMJwBXtLpoAOMO2p8C1JidxSVlDjan/PgzTuikmo3UojoSN7dzQPT86Hl t3nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jZzarPuuax9WApxhmE01fr+TB+KCuz6yb6zkBqC3alw=; b=f6eis7R7bqSTLQxNpN3f47s+q9ZbvOpREUasBwZxRQOnUF+A8ZsXdAEJSBP3hAj2Cx 5pvbXA+bjBT58ZS+qBXBR6dXghpkqGZHOkdMO9L7sEONfCDKIIoXBS1+t+eEmldGMh5s eiQXyisapaLgDS+2PcdDLHuV/5NIGq+ud01e+9YJTyQmjkFwJejK+/HDry+Cv/+Nml46 CNgRwt7SUE/H5vQf4WuDeEBLYEGPJKf0aQtvO9oWL6cBlecnZKlo08WiZR78v9bF/zRw HkfarQC/SOih0Mv/NKIOTVwvr6tzF7UQ5cc7f1pWIooqQJaEif76Q34vHOafM/tcjRmZ z3XQ== X-Gm-Message-State: AOAM530qzSufZja1wj4LOcG4zWcEIFcH9QsoLaaX/gIrs1fTDdczp/cj 7CYMIbwqBIQ3+eirqESu3IM= X-Google-Smtp-Source: ABdhPJzhHN5NH3XdmnMDGLeheKdmt+bcamNy9x8l13em+2QyDbAM7LcWd7IqgOeUT8KztyA/3dOdlg== X-Received: by 2002:a05:6000:1547:: with SMTP id 7mr16295455wry.301.1610911545081; Sun, 17 Jan 2021 11:25:45 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id a62sm23805600wmh.40.2021.01.17.11.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 10/20] hw/usb/hcd-ohci: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:36 +0100 Message-Id: <20210117192446.23753-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:52 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/hcd-ohci.h | 2 ++ hw/usb/hcd-ohci.c | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h index 11ac57058d1..fd4842a352f 100644 --- a/hw/usb/hcd-ohci.h +++ b/hw/usb/hcd-ohci.h @@ -101,6 +101,8 @@ struct OHCISysBusState { /*< public >*/ OHCIState ohci; + + /* Properties */ char *masterbus; uint32_t num_ports; uint32_t firstport; diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index f8c64c8b95b..302aab30992 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -2007,6 +2007,7 @@ static void ohci_sysbus_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ohci_realize_pxa; + dc->vmsd = vmstate_qdev_no_state_to_migrate; set_bit(DEVICE_CATEGORY_USB, dc->categories); dc->desc = "OHCI USB Controller"; device_class_set_props(dc, ohci_sysbus_properties); -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:25:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DgR-00085g-Hk for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:25:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DgP-00080G-L6; Sun, 17 Jan 2021 14:25:53 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38732) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DgO-0005Iv-5u; Sun, 17 Jan 2021 14:25:53 -0500 Received: by mail-wr1-x435.google.com with SMTP id a9so11001436wrt.5; Sun, 17 Jan 2021 11:25:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z6fdnKTIA2Uc0MDNjyGFMUBSbkvaU7MEUTklOzizagw=; b=i831de7ev0B0ka/oKIaU7WcweUF8wA6VKEUx3FYesxBXhAhi8O2BP9AKIfHV6h2Zdb /KdQ2Qhs5o3gouffIc31QonCGidlp9UD+KBva0GCd9KslDqfyEwLCfCg6OHWsgCVeaip qYZncpxH3yJ3U0zQiedGxfG3Jt6bg4lry0ZcjuRWV1xUydMHr6Nlzh5mx+R4sZX6/Jn0 1mOgQNwgDuhqBH/shdu1RCmylc4/KJyLr1/uFhom5rx6HzokXlYUnodFYfe2etd6a7V/ ONu3ivBrmll+MpFjeawgRm4QOAuLvq5Ez8e3vITnBoCI3T4vLZ/BZa8PEz0fYwD/AW/c pHZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Z6fdnKTIA2Uc0MDNjyGFMUBSbkvaU7MEUTklOzizagw=; b=TUR/82hrUKAX9jP+BDoLLh6yI3wtJgZDRkR7b7RKPoPXAC2IGt3r8sqDWF9BSEdPMz +yr3UUuSx68qNsF4jDlVB34T2E4/y/dYGI6fVD3GSvVYauBlTJZJHna6bCyBINY9Sqcf xRn6isqDI/tWVbtIijnURyMMkKhJrHytMN8AKZimgaA7M62RydGYGLWWyVS/QzOmYfcX N5Drs9jVb2WRW8bG31xa5GX/2rtaOmMNtq5iQeIlLi1ypp3G5mh54WYNbe0HfpyVnnCL 7hTKAAML9rL7x/pWFF7ZrNMb6alMz9qEo7qAtNt+Ut7pQMIhHbXM5zNcsYxzd9mc20Ij ng0A== X-Gm-Message-State: AOAM531LutsHxrxHhJsxHU1g9mAk1wfNyUOfg9KpKiaUbTgJtXpzuAJ4 yMujdEYX2dqtwRcGb9X1fnc= X-Google-Smtp-Source: ABdhPJxWmbI7JojtrE4OgQhnrClZGqIaWR+FS2o3uA3TmpANaN2WRmhoOGuP+gy12dgSvAnRLi6ROQ== X-Received: by 2002:adf:cc81:: with SMTP id p1mr22516009wrj.339.1610911550627; Sun, 17 Jan 2021 11:25:50 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id p17sm1553314wmg.46.2021.01.17.11.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:49 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 11/20] hw/intc/arm_gicv2m: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:37 +0100 Message-Id: <20210117192446.23753-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:25:54 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/arm_gicv2m.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/intc/arm_gicv2m.c b/hw/intc/arm_gicv2m.c index d564b857eba..664cc9fb032 100644 --- a/hw/intc/arm_gicv2m.c +++ b/hw/intc/arm_gicv2m.c @@ -55,6 +55,7 @@ struct ARMGICv2mState { MemoryRegion iomem; qemu_irq spi[GICV2M_NUM_SPI_MAX]; + /* Properties */ uint32_t base_spi; uint32_t num_spi; }; @@ -182,6 +183,7 @@ static void gicv2m_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, gicv2m_properties); dc->realize = gicv2m_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; } static const TypeInfo gicv2m_info = { -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dgc-0008Gp-FH for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DgV-0008Ck-38; Sun, 17 Jan 2021 14:26:00 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:40352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DgT-0005Kg-ME; Sun, 17 Jan 2021 14:25:58 -0500 Received: by mail-wm1-x32b.google.com with SMTP id r4so12028468wmh.5; Sun, 17 Jan 2021 11:25:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ywUmqbvL1fXxkTM+pHTvth+aqc+cAGL+9PBE1kwGlvU=; b=k7DODHe+DDG3vQtF/snRglJd6BfW3ctKhMz9N5ZFRJPXSf0dzDpFVpp9dGeQyIgka2 mdTqYVgIVGe5jiF7pLc665Uf/KYCTz00064LRcNBOnBSZwp4xOO/C2FsgmaTxp+Kiri3 3Mf9O0Cx7AipZaS1Zz8GU8BYzJTllHxdSsIAZYe4jQYB666OfBzttpHt1QlcVEFKMp2/ DUtIxBfJ+7eq4+Tuhq2c7ApuCa19fDN6L1A5gmBj05wZQPRf7cxIsFi8TZ+4YZM1sl73 AzwsJyf9tONeU4ZjEQivy5FmqH5hXP/mttczYyRpcyFWIc7Di+uYnV/oAf6jLi0l8iIp oobg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ywUmqbvL1fXxkTM+pHTvth+aqc+cAGL+9PBE1kwGlvU=; b=JO3E7PMNOhR12fnOh8SGjSW0hJSAzkiJQPitnwtNEXaAKf6NRInpSqAuBZx4xGQfr9 0wwosy4h5Pql16JH70dqXL/Eppq7fx26rj+TSuNv1QAEr2g4oonRvdDblhOBQLG8j7Ez S5qoljalsEjKczlVJlV6RH+uC5+WOA5oVGRKTcH2b7o6Y66p4CqCcHXziN5qP6Izwe9o FoixtFRj9aPKo4HmZeVTWRJbYyefq+afAfVByUg1ZsL2LvmImUsfd/yHXfgVav5utuhm WVUfHU+brS0lJltQ5FetA9P4z0x5upEHbOzdwyRZbwxITiSSkccQJBYAtAAovXq5IO+4 cGCw== X-Gm-Message-State: AOAM533g0oP2YfIJEVAsfIY+7sHQTEvgJEUwXrygP+Mvud3CvGUVeR8W 9qTeNe0XHH5FnrPmRvZapNg= X-Google-Smtp-Source: ABdhPJza6zbRor9M5WyThlg8NoJDp6Fltcq7KawV8Ng1oH1jGEM16OJHPmdV21ZTChQidt5vQpLFbQ== X-Received: by 2002:a1c:9c91:: with SMTP id f139mr18028374wme.118.1610911556017; Sun, 17 Jan 2021 11:25:56 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c18sm42879172wmk.0.2021.01.17.11.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:25:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 12/20] hw/misc/armsse-cpuid: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:38 +0100 Message-Id: <20210117192446.23753-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:02 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/armsse-cpuid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index d58138dc28c..61251d538b9 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -115,6 +115,7 @@ static void armsse_cpuid_class_init(ObjectClass *klass, void *data) * This device has no guest-modifiable state and so it * does not need a reset function or VMState. */ + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, armsse_cpuid_props); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dgi-0008Ju-DY for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dga-0008Ey-J3; Sun, 17 Jan 2021 14:26:06 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:55547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DgY-0005Lz-Sy; Sun, 17 Jan 2021 14:26:04 -0500 Received: by mail-wm1-x330.google.com with SMTP id c124so11718468wma.5; Sun, 17 Jan 2021 11:26:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DRYX7wbIVKKy2xsQ0SOHg/10f2SElgXUvILpXN/GlbY=; b=lpPEyFuXuoafu/yi/Nqa55IIFSScEH1LM1s99Q2JEy5YXrYuZYLY1/LVTSuU369szr GG91IPMKGJStj2z43+4segzsyxdD31ASCqPzMDsVM1obfyhx4L/d94P+/+M89uwZbauA n3UWb4wcvZsd+7/zRF0MDjCHwjR2jzzZIeaMHe3sUqEfGIYnrlF/NBjAnh64oLilH4M5 ffEGLK2HAq/Ax9odiPh5vQtVKvwylVFWC9pH+5G6doaOAxUzKycwsNvJm+SsXr5vl5pa hga79J2/seUXvJNkyrSiJmto2tiMe7Y6HfoYywf3sp5SlAcCRei9UHD8DoswqWR0AN8z nDmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DRYX7wbIVKKy2xsQ0SOHg/10f2SElgXUvILpXN/GlbY=; b=jDeCf3lja3Hb5QncILWfM41RN6wD3tn/Y3b0rQIj3MJFRmSLpo2q909jKZNepu9LO6 /oa9iXny4Z77aouduXYYXO3JSIPErXmiawVB2TB3M5qO+LtRVxs6Mfp+cQiHT0jt8yRk 5tcYZGNZkj1jpipknwKFuxO2OZKciCtH4pSUxzckXcW/nRX1AkFx2i3DA92MW1u7cST5 WEHJ39A2Yd2sY+X0msaUbEMkEmFZ0cYzar9ovF1HgD8BB76GEjFLj4Zt5W0t6Af47gUJ C51hYkXgLrnCGGtb8spx2NRHmHp8tu6WGp1+Ofy1HGsJNNLrKdm6I1oZgnJissXkWqvs tSbQ== X-Gm-Message-State: AOAM531947AiNRa/FyF3mHjkfJ+WK867nSvOEmT57AlfzwuII5iwO1Ls M/Bpuaxn/xPt8Bl3uOkCexA= X-Google-Smtp-Source: ABdhPJy4cdiAJh+fC43tbu5pjvny/oXmQebYPEcKMKLunspdGaFCEQAwtWyCGO89YQa/dK69ZtsPYQ== X-Received: by 2002:a7b:cf3a:: with SMTP id m26mr14828497wmg.66.1610911561170; Sun, 17 Jan 2021 11:26:01 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id 14sm21096877wmk.37.2021.01.17.11.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 13/20] hw/misc/iotkit-sysinfo: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:39 +0100 Message-Id: <20210117192446.23753-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:08 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/iotkit-sysinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index b2dcfc4376c..8bb9a2ef8b2 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -120,6 +120,7 @@ static void iotkit_sysinfo_class_init(ObjectClass *klass, void *data) * This device has no guest-modifiable state and so it * does not need a reset function or VMState. */ + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, iotkit_sysinfo_props); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dgp-0008OC-Qr for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dgh-0008Ji-Qv; Sun, 17 Jan 2021 14:26:12 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:35555) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dge-0005NG-Fc; Sun, 17 Jan 2021 14:26:10 -0500 Received: by mail-wm1-x332.google.com with SMTP id e15so5646429wme.0; Sun, 17 Jan 2021 11:26:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+o+ioZvx1jeZgR8bC7wg2B3Sh0sACSJW4nTdU8f7aTU=; b=RILotdEvzW7p4sBqW4M3EnDurWmb3N1pLM5Sn80jZz3dhPqGzfe1LGXAZuKZFhPNfL 7Lx7XpFlVVSrcJsJXSE27NstSKS9FbF5TaaXEm6257Aes2wSs4ogex1kzLzabXoQYSIF hfcH2YVJ8DYFrNipRSor0w3i9gryP7mn5BQn1VHaXAUgUGYOtQapyTSkZAvZrkjM678L qguqYfFKE/GYaTw1mVfUQZOP8YDUeZCdbJ7H4CMKC/E16A66D64xL85cRrhR/kTt2TM8 V+zkE0A0GlZ5Ix/60gPfowSN+Wx9X3Drp1WCJDNWNG6RR9Y7pJY0Hka6u6o6g0cyQ7yP LLVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+o+ioZvx1jeZgR8bC7wg2B3Sh0sACSJW4nTdU8f7aTU=; b=gjqkyig8L5D0Dr1nWSeV5VtGCv7/T0WCssdiZZv7XDD4HNa7SSLjxjFD0zqE5WNvjI TFblGpMYsFtJuOfKqB3J/FbjBCVFNSJ3kZc8ubuTOuUbTKF304uzDmLN0tZCst1VTYpb SZcTeZTmpc9gemQHHXEPR6Be6O64u3HP8gpKOEqYXCU7M+AyuC2v5jchDWFGrNq0qUcK 5j9jd4ABbc9/iyzVFgMLY7adV3DtYG/x2XcXWF0C/ejELZCvww6VQKiKFowZGQZPyjIk lt4hm6oBHlY1Kspkf4oKSBAjQcvTKMWzo7ap7KSD80GNyffl/qgqZ6Ss/sQhEuzgLpBY tQIA== X-Gm-Message-State: AOAM533KdeSWs/Pcm5hEVnzW6fWtIFkQziLT7yEwZtGqax6I25TYDen0 b8zYrkyhxT36PVz+VoG095I= X-Google-Smtp-Source: ABdhPJwuJyD5eoJZdzZeLrTpidVMX4ieENOmYUA+91AatCaoyylhNKb7AwKmVzAyg91mXVCdFTHbWQ== X-Received: by 2002:a1c:6744:: with SMTP id b65mr6011059wmc.60.1610911566671; Sun, 17 Jan 2021 11:26:06 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id m18sm25364721wrw.43.2021.01.17.11.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 14/20] hw/misc/unimp: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:40 +0100 Message-Id: <20210117192446.23753-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:16 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/unimp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c index 6cfc5727f0b..e5ede95c124 100644 --- a/hw/misc/unimp.c +++ b/hw/misc/unimp.c @@ -81,6 +81,7 @@ static void unimp_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = unimp_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, unimp_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dgs-0008QI-PW for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dgn-0008N5-Tc; Sun, 17 Jan 2021 14:26:17 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:40352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dgk-0005PB-6z; Sun, 17 Jan 2021 14:26:16 -0500 Received: by mail-wm1-x32a.google.com with SMTP id r4so12028771wmh.5; Sun, 17 Jan 2021 11:26:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OG4UEEhgrdnthw/7SfhW0jpVgnxGKL48F7b84mxBL0Y=; b=d1hCPPD2xD1wJ+ELj4EXKXvHf5LWkdVFuJ6DUWt6j6JneNcQ5YKxKbitQlO+YmW+vO EnGhR+vcKbFIoe5cCUn/VYx+ycAQesN4/1eQKKGJ8aRaJ3O/iFxgq7XOsEEJGgOLFfVu 1Pv9HxD9KNv3eutgax74SADs46HixAvEknnx8jGCMz/i8NO+1YLgYT1z4s4Xuh5XHYTo E+XV3hrJ7nzNIE75qSqNrcxBlqp8dxtgsodEkFx93MEaPGLCxMpRyrRxLVglDI05Xl2D iU9v6VRnloJr1dHA5Xn1doJe9TcNhoTdsJY7MJOMcT3W8wGR67ygmXeqUHe5UQx4xmNN 04ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OG4UEEhgrdnthw/7SfhW0jpVgnxGKL48F7b84mxBL0Y=; b=kgXJcf0UfVvKcTYTvGqOYbgvl9S67JbiIJTe68UISCFcD+dLZdseMgNQwMDtT0oGJ7 IFk37QPj7fnuCqCvp5heTCvwnB3ZpMYchX6vKIgG5An/PpnmytjiJeSi5QzxYZMmo+IU 74ayC+eume0HFvrVqP/2SMn6ymPiPRWCoVyRNeHsoFGDfFkulXpuO1QoWy3FPKcSljIB W7TJvMJwUF+oN14zGUGnKntBYmrzg0f1GfIiIMqWriwyZfuwGZN5nGBsB4XpcFyKTwv5 syAFqrT1lpHDKoSwyPJ89L1IvqIQWRg8KAYW8Ok+i57X1bE8F76Kw+ANAdKa6uqlMeZs DZDw== X-Gm-Message-State: AOAM532yEctNGjBclFblL+ld1TAzseKBAz02h93WD7jO0dR7gNDIjhiT +TjBycO6EtwN6+0ffxJsrQs= X-Google-Smtp-Source: ABdhPJzutk6ePzHawSll3xN2iOVVCJtHT1zjoYf0c0Fn7F8ecRYwBXidzFLAGHXx/CMlgKv6LoEgdA== X-Received: by 2002:a7b:ce11:: with SMTP id m17mr721232wmc.158.1610911572131; Sun, 17 Jan 2021 11:26:12 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id v20sm27021723wra.19.2021.01.17.11.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 15/20] hw/nubus/mac-nubus-bridge: Mark the device with no migratable fields Date: Sun, 17 Jan 2021 20:24:41 +0100 Message-Id: <20210117192446.23753-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:19 -0000 This device doesn't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/nubus/mac-nubus-bridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c index 7c329300b82..ede36ccc5dd 100644 --- a/hw/nubus/mac-nubus-bridge.c +++ b/hw/nubus/mac-nubus-bridge.c @@ -27,6 +27,7 @@ static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->desc = "Nubus bridge"; + dc->vmsd = vmstate_qdev_no_state_to_migrate; } static const TypeInfo mac_nubus_bridge_info = { -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dgu-0008Ra-NG for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dgr-0008PJ-Pn; Sun, 17 Jan 2021 14:26:21 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:33197) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dgo-0005Tv-Vv; Sun, 17 Jan 2021 14:26:20 -0500 Received: by mail-wm1-x32c.google.com with SMTP id s24so3914301wmj.0; Sun, 17 Jan 2021 11:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bx350E5m3VyPci30nthMcxfcvDfYIGiblZKZEeXM5tA=; b=HDL1cOYRAppqKDmt0+6iCG+tyRa20Vszx0WdmS5WO4jtkTwdghRo7ux+0D8e69Uuiw 5Q/xpoa4zO6PZxWg34I8XAcOCHbo09E8+8AymMWcJ+19VUo/dFWq072XbTkgYlap/Iv4 34tjuUMRZkwuhTEq75obgsagYTcucmWPEESKu4unh5QY05yV8W4ImCOJaL2TdlgfmTn7 Paoui5pA9tXlupK38Io8YVI1ozZL8qLn/V6PAUOonYkcOiE8KWeocwhDD009rHjUedXq edFMLdbiI4AM33Wp2tryl8IrOQ8fOhStobBacJ+f63I31IVazo4JE8UW7WPcbt7zFtCZ wpxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Bx350E5m3VyPci30nthMcxfcvDfYIGiblZKZEeXM5tA=; b=ioFa+DBgLbQPN3klRzQqZlVpaAmyIWkrmSly+cy63Mk9OQYITiZd5Q/H49s91FbkOY fzvmoAm5fR5G9r0vrlqTUQZRFySTVWzM0vEhV1ddHb+5QDFh6HZrcgK7TwI496fnf7GX XH3LiWyEzoZL7zaaxrNHTaknWqUQsRKUdWlhO1Zr4p7iVSIZomezOLcz12R1rZI4M6VO LWGb27D/pWEKPic/miu4vMVW9DKDO6Efp5YC3xCYW7hrJBVtuZYI12w1KMQnucpdB0C6 U3Z+i9pb1s1jm02DpZwpeSOswhhhOI6BNSj3gLIq2jJp1AI93mUkdgvuvUVthXvxc+lr 9odA== X-Gm-Message-State: AOAM533q66OjPd9Zvpiknj9JPX2wgnbYETKT5Dcb7RDKXXtJO7kA3dVi N7wcT3a3x8gTf9/mZRnee9I= X-Google-Smtp-Source: ABdhPJwOdTStGNdd9lQ6Q15iSvEbhn8d+kx24B0aMkfbK/kzK64HdGME4mUFDC/bS4yOg2dAnQX5dA== X-Received: by 2002:a1c:984a:: with SMTP id a71mr11036888wme.175.1610911577485; Sun, 17 Jan 2021 11:26:17 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id a24sm15013983wmj.17.2021.01.17.11.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 16/20] hw/sparc64/sun4u: Mark devices with no migratable fields Date: Sun, 17 Jan 2021 20:24:42 +0100 Message-Id: <20210117192446.23753-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:23 -0000 These devices don't have fields to migrate. Be explicit by using vmstate_qdev_no_state_to_migrate. Add a more descriptive comment to keep a clear separation between static property vs runtime changeable. Signed-off-by: Philippe Mathieu-Daudé --- hw/sparc64/sun4u.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 0fa13a73302..fdf0aa875be 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -84,12 +84,15 @@ struct hwdef { struct EbusState { /*< private >*/ PCIDevice parent_obj; + /*< public >*/ ISABus *isa_bus; qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; - uint64_t console_serial_base; MemoryRegion bar0; MemoryRegion bar1; + + /* Properties */ + uint64_t console_serial_base; }; #define TYPE_EBUS "ebus" @@ -386,6 +389,7 @@ static void ebus_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_SUN_EBUS; k->revision = 0x01; k->class_id = PCI_CLASS_BRIDGE_OTHER; + dc->vmsd = vmstate_qdev_no_state_to_migrate; device_class_set_props(dc, ebus_properties); } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dh0-0008VT-Jw for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dgw-0008TM-LG; Sun, 17 Jan 2021 14:26:27 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39008) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dgu-0005Wy-Uy; Sun, 17 Jan 2021 14:26:26 -0500 Received: by mail-wr1-x42d.google.com with SMTP id c5so14444877wrp.6; Sun, 17 Jan 2021 11:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XogiRe5yl1pNdqgPP5V4b7SXP6ekjym12cW6DYLGVp0=; b=dHzl2LACEwVQNJhxnDfIp+k/e2+8X0LFiprYl04+U7/AQgBLE93j09+DEwxBHCx72r CpPITxjy0TJLx+gj5fT+DRnsn6nE411uOqW8Q0Qz+7e3Hzv2ATu6bA3hbpfk0+wVyWx0 urrTcZ+Q3haAu562yWx3+KF3Z1YQpnASASkSMdgJJ1h72rLOJOfRwKX3BllpWATYdY7H SV3Cv0fvvH2RbAGCDNA7wxT2nNU8eHb1aDIpyyFwoOM4+7aue5h+I1mRqG+ItGfAI2Tu LSeFn1EDviFdR6c5vpEaSX5nwDmIKmMKo8XujmtGig2c/WpZHoWmX90dUJgA4O/RwgFP Jy5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XogiRe5yl1pNdqgPP5V4b7SXP6ekjym12cW6DYLGVp0=; b=NZT33XADN0226G9ffxKXHsqLQsj4VkGjmwvJsljHiJFhUbPi1Zn0UJJ6YL8mBRSs5P BVOFIjBb65qon+vWaNGZIsQubF4Av6jZ/tcBMo3IsBgfs2r0sFeJzfT4nyhUJYSaMMdS nn0kUGFI1W9SSxr2IQReKkESaJf7Nx1Yq7dOLBuspdHL3XBDo/3TP2v/d3j43KiPNmq2 MYChHxFPJ03larWVfVBjahy/y/RBUczT8EDjogz0PxR4lG+S63QI8lsNYP3TqtyKdRQk QS78016dkKVaU9xup8Cv+ltRIV/igRZBcr/ZKqwDq2VEp6QwAF/b1fqgqEXM7jyYd346 nixA== X-Gm-Message-State: AOAM532UtLF02mEycn5UT/qa4P/GRMCitWUGKWufGlVbvEZFTWqPQAiA yXhosQ5HppcTKWP4CIorbII= X-Google-Smtp-Source: ABdhPJz3j/0k13Y+1hAKw3keqLsar5KE6t3HteVdbPBktHQmHravmlslxwvSJKSccWLBysDa73hcFw== X-Received: by 2002:adf:eecc:: with SMTP id a12mr22631110wrp.312.1610911582822; Sun, 17 Jan 2021 11:26:22 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id v4sm25387282wrw.42.2021.01.17.11.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 17/20] hw/pci-host/gpex: Mark device with no migratable fields Date: Sun, 17 Jan 2021 20:24:43 +0100 Message-Id: <20210117192446.23753-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:28 -0000 TYPE_GPEX_HOST does not have internal state to migrate. Its only interesting state is in the GPEXRootState, which is a TYPE_GPEX_ROOT_DEVICE which migrates itself. Explicit there is nothing to migrate by using the special vmstate_qdev_no_state_to_migrate. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gpex.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 2bdbe7b4561..2565dc27ae4 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -115,6 +115,7 @@ static void gpex_host_class_init(ObjectClass *klass, void *data) hc->root_bus_path = gpex_host_root_bus_path; dc->realize = gpex_host_realize; + dc->vmsd = vmstate_qdev_no_state_to_migrate; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name = "pci"; } -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Dh4-0000Cu-1q for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dh1-00007H-LL; Sun, 17 Jan 2021 14:26:31 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40427) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dgz-0005Z8-R1; Sun, 17 Jan 2021 14:26:31 -0500 Received: by mail-wr1-x435.google.com with SMTP id 91so14459064wrj.7; Sun, 17 Jan 2021 11:26:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sLzS9Bs5+OgQ/PoK/Es1Ix8oJMDYYC+sg+uBbYc2jF4=; b=CkwMsV8INxC6IbZrpQSLWtqkYM7Lrst93pFDrrc3JrCNpyl8DEtgIQRIklY4zeLfhI yXFPy4lMl4WV92ZnEdFZvwSS/hHcJ8PznnYo9IrN4tZz9iVrWbilg4pN3Mo7HFefVzT4 z/aybAzi/R5NF6BQ5rPc7h1KyRFdiRHhCHZvo65slVvfl3OW+0ilZcnHTg6a2G+sHcok n17dBnJhF6oRK3A3+h28snY7ClgEiKLuoa7FsnKBDQ4tDr9njcijK8/E/wxwy84l+LZB eXRJu8NLo6kjCugqwFJICAkikVgZn2rwDx3ndHgvbski6Ayk5W4o70rkLtpwTNf3k2Pv PlkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sLzS9Bs5+OgQ/PoK/Es1Ix8oJMDYYC+sg+uBbYc2jF4=; b=iHJQwQBbiMqjLlt82Bb0DLY+Sz2xrxFbuciWx0gfcIUYIMUc4A4KT3uYuoi8Z/YZ6+ U/OkgGU0//9bx57BOQCNXRfgEy75XJNwbY/+6NEXR5vyEJOuO5wnpbGWnWN4c8J0o2pT 31PnNIet/AEMc0DcHibHWC1MOmuPaxHcebS4MBTY156GutQYp/QObLj1khgn0sjlvnhy szojsNthWVdgSJC55ZalK9kHYahSMBAm6Z9fOK1SDZQS4ZQ738JYCLtXbG8iiD1c5yCy UhodwBOsTh7GNsbYysbrhRNdbia7ANsCQXRLr5YASCPUw/CrYSCd8iGiNzp6IWSMAykj z7kA== X-Gm-Message-State: AOAM533DE9AATkUHM73MjGAAFHyJNcJUuF+1/TexPJwMJgmlUUNQAGgT af3KS70TwienHkdG8XZfVsQ= X-Google-Smtp-Source: ABdhPJxWrf+AFOLydS3QL/cdCmgoG08Uh/rSVPpDcMqUO7MHLHlm/zfTafxeQ0CNyCiIKJf+lJj5Eg== X-Received: by 2002:a05:6000:1565:: with SMTP id 5mr23155649wrz.109.1610911588342; Sun, 17 Jan 2021 11:26:28 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z3sm25943380wrn.59.2021.01.17.11.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 18/20] hw/core/qdev: Display warning for devices missing migration state Date: Sun, 17 Jan 2021 20:24:44 +0100 Message-Id: <20210117192446.23753-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:32 -0000 When built with --enable-qdev-debug, QEMU displays warnings listing devices missing migration state: $ qemu-system-arm -S -M spitz qemu-system-arm: warning: missing migration state for type: 'pxa270-c0-arm-cpu' qemu-system-arm: warning: missing migration state for type: 'serial' qemu-system-arm: warning: missing migration state for type: 'pxa2xx-pcmcia' qemu-system-arm: warning: missing migration state for type: 'pxa2xx-pcmcia' qemu-system-arm: warning: missing migration state for type: 'pxa2xx-i2c-slave' qemu-system-arm: warning: missing migration state for type: 'pxa2xx-i2c-slave' qemu-system-arm: warning: missing migration state for type: 'ads7846' qemu-system-arm: warning: missing migration state for type: 'max1111' Signed-off-by: Philippe Mathieu-Daudé --- Unresolved issue: https://www.mail-archive.com/qemu-devel@nongnu.org/msg721700.html Peter: > I think where we'd like to get to is installing a migration > blocker if the machine has any devices which don't have a vmsd. > But for that we'd need to be pretty sure we'd got all the devices > on machines where we care about migration, and we're clearly a > fair way from that (eg we need to do something about the > devices like the CPU which don't have a vmsd but handle their > migration some other way so they don't trigger the condition > for warning/migration-blocker). --- configure | 10 ++++++++++ meson.build | 1 + hw/core/qdev.c | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/configure b/configure index 155dda124c2..984befbb99d 100755 --- a/configure +++ b/configure @@ -383,6 +383,7 @@ blobs="true" pkgversion="" pie="" qom_cast_debug="yes" +qdev_debug="no" trace_backends="log" trace_file="trace" spice="$default_feature" @@ -1005,6 +1006,10 @@ for opt do ;; --enable-qom-cast-debug) qom_cast_debug="yes" ;; + --disable-qdev-debug) qdev_debug="no" + ;; + --enable-qdev-debug) qdev_debug="yes" + ;; --disable-virtfs) virtfs="disabled" ;; --enable-virtfs) virtfs="enabled" @@ -1048,6 +1053,7 @@ for opt do debug="yes" strip_opt="no" fortify_source="no" + qdev_debug="yes" ;; --enable-sanitizers) sanitizers="yes" ;; @@ -5912,6 +5918,10 @@ if test "$qom_cast_debug" = "yes" ; then echo "CONFIG_QOM_CAST_DEBUG=y" >> $config_host_mak fi +if test "$qdev_debug" = "yes" ; then + echo "CONFIG_QDEV_DEBUG=y" >> $config_host_mak +fi + echo "CONFIG_COROUTINE_BACKEND=$coroutine" >> $config_host_mak if test "$coroutine_pool" = "yes" ; then echo "CONFIG_COROUTINE_POOL=1" >> $config_host_mak diff --git a/meson.build b/meson.build index 3d889857a09..545c8f9f88b 100644 --- a/meson.build +++ b/meson.build @@ -2472,6 +2472,7 @@ summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')} summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')} summary_info += {'QOM debugging': config_host.has_key('CONFIG_QOM_CAST_DEBUG')} +summary_info += {'QDEV debugging': config_host.has_key('CONFIG_QDEV_DEBUG')} summary_info += {'Live block migration': config_host.has_key('CONFIG_LIVE_BLOCK_MIGRATION')} summary_info += {'lzo support': lzo.found()} summary_info += {'snappy support': snappy.found()} diff --git a/hw/core/qdev.c b/hw/core/qdev.c index f0d0afd438d..9a73a242fa4 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -792,6 +792,11 @@ static void device_set_realized(Object *obj, bool value, Error **errp) &local_err) < 0) { goto post_realize_fail; } + } else { +#ifdef CONFIG_QDEV_DEBUG + warn_report("missing migration state for type: '%s'", + object_get_typename(OBJECT(dev))); +#endif } /* -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DhD-0000Mn-Fd for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Dh6-0000Gr-OT; Sun, 17 Jan 2021 14:26:37 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:40419) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Dh5-0005bA-AT; Sun, 17 Jan 2021 14:26:36 -0500 Received: by mail-wr1-x42c.google.com with SMTP id 91so14459156wrj.7; Sun, 17 Jan 2021 11:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id v11sm24403198wrt.25.2021.01.17.11.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 19/20] stubs/vmstate: Add VMSTATE_END_OF_LIST to vmstate_user_mode_cpu_dummy Date: Sun, 17 Jan 2021 20:24:45 +0100 Message-Id: <20210117192446.23753-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:39 -0000 Add a name and end marker to the vmstate_user_mode_cpu_dummy variable. Reported-by: Dr. David Alan Gilbert Signed-off-by: Philippe Mathieu-Daudé --- stubs/vmstate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/stubs/vmstate.c b/stubs/vmstate.c index f561f9f39bd..1d0e03e233b 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -2,7 +2,12 @@ #include "migration/vmstate.h" #if defined(CONFIG_USER_ONLY) -const VMStateDescription vmstate_user_mode_cpu_dummy = {}; +const VMStateDescription vmstate_user_mode_cpu_dummy = { + .name = "cpu_common_user", + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + }, +}; #endif const VMStateDescription vmstate_no_state_to_migrate = { -- 2.26.2 From MAILER-DAEMON Sun Jan 17 14:26:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1DhE-0000NY-Vj for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 14:26:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1DhB-0000KT-RQ; Sun, 17 Jan 2021 14:26:42 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:55547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1DhA-0005cM-Fc; Sun, 17 Jan 2021 14:26:41 -0500 Received: by mail-wm1-x32b.google.com with SMTP id c124so11719241wma.5; Sun, 17 Jan 2021 11:26:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D/vhGf9tYrzI/+Qv47CWtkJxcBt3ZEhYVSaLznm82dE=; b=dDIS/7Ww+gYmBQD8IMElHJNn7JWSXIxRghqGgbo8cMyxwhw8p/6ubLO11lw+vm1ZQ2 UqqHLYgUegb0abI5GEcwCObm3ghvemj1qkIY9BWUUpsuc3nBY1fIR/5egA46QCzJpq35 YJQclTTYuUqdvZXRJdbSN3tn56EW9NfesLJaMLMXDaPPkk39A5cak7kHtnv/DJmGiEIe BCYLb69WO7aLof7gZKSu2Dgs5ZiWtWGYEGSU7MrLm1rf16ioj+u7Ckxh8gVoPGHA3trD tVed2SiZPpXpVTRpAdMFFkMSRsdt48VTaXD9guI/2L+4SqYbTEd8DbKlwJwfL6cijqzk wmgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=D/vhGf9tYrzI/+Qv47CWtkJxcBt3ZEhYVSaLznm82dE=; b=LhSVJ5HiIoV5l9Srbs5EPezIrD9Z31JYO+BaXj/NMMD+sErx2eCq4ARbuR5jykyG18 aHHKSyV4AULcULswq4COUcU8B6RXWzpyJbEeUyD+u+dcMzYcoauDM7TQgLO1MSddtNOm 4Y6YAY0837/a5iEl/agriIHXDzqe7PeZTCDgY9P3Zk/NFrcDdEoX1yVS85otYsY8FNop G3AFgSZiihD6jQ2Ia44NXkZLIdzW/+lz/VHeNpGkiuCv7pS1GFItSFSuY4/ROiCxjMPd D8+3wBgOwnRP9Fv8QW2Rr4fAziRPa1qS2f6Gg+IpFG5NDBI3lrNOSUKOekrPdFapOsbB eQew== X-Gm-Message-State: AOAM532Ven8f5L4zXl2b7k0x8S+cpOSBIGlFaGsq8CJhROb2BIqeeiG3 8VFDFHlehOgPi9kcru0V5Kc= X-Google-Smtp-Source: ABdhPJzIcaeD79hTA/Hun2LIAf5jPVodgZiUbtt9nKaY6Exb5IX56l+RDcFbxAto+c8yERamWN+R+w== X-Received: by 2002:a05:600c:255:: with SMTP id 21mr17520686wmj.69.1610911599053; Sun, 17 Jan 2021 11:26:39 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id j7sm21720217wmb.40.2021.01.17.11.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 11:26:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 20/20] migration/vmstate: Simplify vmstate for user-mode CPU Date: Sun, 17 Jan 2021 20:24:46 +0100 Message-Id: <20210117192446.23753-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210117192446.23753-1-f4bug@amsat.org> References: <20210117192446.23753-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 19:26:42 -0000 User-mode wants an empty vmstate for the CPUs. We can use the generic vmstate_no_state_to_migrate object which is the same. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- include/migration/vmstate.h | 3 --- stubs/vmstate.c | 9 --------- 3 files changed, 1 insertion(+), 13 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c79a58db9b9..01e75cc7403 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1132,7 +1132,7 @@ bool target_words_bigendian(void); #ifdef CONFIG_SOFTMMU extern const VMStateDescription vmstate_cpu_common; #else -#define vmstate_cpu_common vmstate_user_mode_cpu_dummy +#define vmstate_cpu_common vmstate_no_state_to_migrate #endif #define VMSTATE_CPU() { \ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 50559598eac..dfe20b5caa1 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,9 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; -#if defined(CONFIG_USER_ONLY) -extern const VMStateDescription vmstate_user_mode_cpu_dummy; -#endif extern const VMStateDescription vmstate_no_state_to_migrate; extern const VMStateInfo vmstate_info_bool; diff --git a/stubs/vmstate.c b/stubs/vmstate.c index 1d0e03e233b..c360a929f60 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,15 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" -#if defined(CONFIG_USER_ONLY) -const VMStateDescription vmstate_user_mode_cpu_dummy = { - .name = "cpu_common_user", - .fields = (VMStateField[]) { - VMSTATE_END_OF_LIST() - }, -}; -#endif - const VMStateDescription vmstate_no_state_to_migrate = { .name = "empty-state", .fields = (VMStateField[]) { -- 2.26.2 From MAILER-DAEMON Sun Jan 17 15:37:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1EnY-0006xW-A0 for mharc-qemu-arm@gnu.org; Sun, 17 Jan 2021 15:37:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1EnW-0006wh-E0; Sun, 17 Jan 2021 15:37:18 -0500 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]:41056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1EnU-0003qC-Lj; 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Sun, 17 Jan 2021 12:37:14 -0800 (PST) MIME-Version: 1.0 References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-17-f4bug@amsat.org> In-Reply-To: <20210117192446.23753-17-f4bug@amsat.org> From: Artyom Tarasenko Date: Sun, 17 Jan 2021 21:37:02 +0100 Message-ID: Subject: Re: [RFC PATCH v2 16/20] hw/sparc64/sun4u: Mark devices with no migratable fields To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org, Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Content-Type: multipart/alternative; boundary="00000000000019047505b91e92d1" Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=a.tarasenko@gmail.com; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Jan 2021 20:37:18 -0000 --00000000000019047505b91e92d1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =D0=B2=D1=81, 17 =D1=8F=D0=BD=D0=B2. 2021 =D0=B3., 20:26 Philippe Mathieu-D= aud=C3=A9 : > These devices don't have fields to migrate. Be explicit > by using vmstate_qdev_no_state_to_migrate. > > Add a more descriptive comment to keep a clear separation > between static property vs runtime changeable. > Nice, thanks for this! > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Artyom Tarasenko --- > hw/sparc64/sun4u.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c > index 0fa13a73302..fdf0aa875be 100644 > --- a/hw/sparc64/sun4u.c > +++ b/hw/sparc64/sun4u.c > @@ -84,12 +84,15 @@ struct hwdef { > struct EbusState { > /*< private >*/ > PCIDevice parent_obj; > + /*< public >*/ > > ISABus *isa_bus; > qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; > - uint64_t console_serial_base; > MemoryRegion bar0; > MemoryRegion bar1; > + > + /* Properties */ > + uint64_t console_serial_base; > }; > > #define TYPE_EBUS "ebus" > @@ -386,6 +389,7 @@ static void ebus_class_init(ObjectClass *klass, void > *data) > k->device_id =3D PCI_DEVICE_ID_SUN_EBUS; > k->revision =3D 0x01; > k->class_id =3D PCI_CLASS_BRIDGE_OTHER; > + dc->vmsd =3D vmstate_qdev_no_state_to_migrate; > device_class_set_props(dc, ebus_properties); > } > > -- > 2.26.2 > > --00000000000019047505b91e92d1 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


These devices d= on't have fields to migrate. Be explicit
by using vmstate_qdev_no_state_to_migrate.

Add a more descriptive comment to keep a clear separation
between static property vs runtime changeable.
=

Nice, thanks for this!
<= div dir=3D"auto">

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>

=
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>

---
=C2=A0hw/sparc64/sun4u.c | 6 +++++-
=C2=A01 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 0fa13a73302..fdf0aa875be 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -84,12 +84,15 @@ struct hwdef {
=C2=A0struct EbusState {
=C2=A0 =C2=A0 =C2=A0/*< private >*/
=C2=A0 =C2=A0 =C2=A0PCIDevice parent_obj;
+=C2=A0 =C2=A0 /*< public >*/

=C2=A0 =C2=A0 =C2=A0ISABus *isa_bus;
=C2=A0 =C2=A0 =C2=A0qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
-=C2=A0 =C2=A0 uint64_t console_serial_base;
=C2=A0 =C2=A0 =C2=A0MemoryRegion bar0;
=C2=A0 =C2=A0 =C2=A0MemoryRegion bar1;
+
+=C2=A0 =C2=A0 /* Properties */
+=C2=A0 =C2=A0 uint64_t console_serial_base;
=C2=A0};

=C2=A0#define TYPE_EBUS "ebus"
@@ -386,6 +389,7 @@ static void ebus_class_init(ObjectClass *klass, void *d= ata)
=C2=A0 =C2=A0 =C2=A0k->device_id =3D PCI_DEVICE_ID_SUN_EBUS;
=C2=A0 =C2=A0 =C2=A0k->revision =3D 0x01;
=C2=A0 =C2=A0 =C2=A0k->class_id =3D PCI_CLASS_BRIDGE_OTHER;
+=C2=A0 =C2=A0 dc->vmsd =3D vmstate_qdev_no_state_to_migrate;
=C2=A0 =C2=A0 =C2=A0device_class_set_props(dc, ebus_properties);
=C2=A0}

--
2.26.2

--00000000000019047505b91e92d1-- From MAILER-DAEMON Mon Jan 18 02:33:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1P2n-0000JS-GU for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 02:33:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1P2l-0000Ie-RI; Mon, 18 Jan 2021 02:33:43 -0500 Received: from mout.kundenserver.de ([212.227.17.24]:37749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1P2j-0005Zy-VM; Mon, 18 Jan 2021 02:33:43 -0500 Received: from [192.168.100.1] ([82.252.149.54]) by mrelayeu.kundenserver.de (mreue108 [213.165.67.119]) with ESMTPSA (Nemesis) id 1M26n9-1l3Jmc1BBx-002TXw; Mon, 18 Jan 2021 08:33:23 +0100 Subject: Re: [PATCH 00/18] hw: Mark the device with no migratable fields To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell , Eduardo Habkost , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Paolo Bonzini , Gerd Hoffmann Cc: QEMU Developers , Artyom Tarasenko , "Dr . David Alan Gilbert" , qemu-arm , Marcel Apfelbaum , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Andrew Baumann , Joel Stanley , Subbaraya Sundeep , Mark Cave-Ayland , Andrew Jeffery , Juan Quintela References: <20200703201911.26573-1-f4bug@amsat.org> <17a5ddc4-c7d9-08f3-5260-f17e1bd48dac@amsat.org> From: Laurent Vivier Message-ID: Date: Mon, 18 Jan 2021 08:33:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <17a5ddc4-c7d9-08f3-5260-f17e1bd48dac@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: fr Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:+rZug63ri5WgwqYSq/LsOnwykK/CVUE7Hioh0xluSxDPE1rIqRx uu3Z7GUCCt6aPsWSp2BVbJS/N9HQRs+dx7ZY4npajdCBlSZ/QT/GuxUCsjduMMkjcYahCx6 6Td8XyOsn4Ifn6xHyLT3DRZtkzLFwV2H1vuvcrQ1m7gKKVbTAKrMA8/W3Bah6r+1DpVPKrs 6GccAfHttiZzQzt83KU1A== X-UI-Out-Filterresults: notjunk:1;V03:K0:efXCHmsUCME=:u0Lt6ROW8eFB5ESjXxD83V Wri+LsZ5MA5+lL5YNDxoQFF/dARCfF9k7VL0t+9JX4KTcWUEoAJ7xzIBzH4liKxUS7Q/gsVl1 MhkNQ2wcO8f3yIZ2GbWX0728sOHZiplRhT+f5HLWwaUmmEPdkqmRhrdvIpvsthGk6WTpbw2Y8 E+dBAnxwFAdysdlKicP7zaWljytDgb+dOD1lxxXqDLr+SDt3O/9GrFOAilGTbfBphFN0+thfw XMbYyU1m4aOabVSS01bLTFv+0DkkFTm/oeuXoBLsZb057kXHN78fHZBuhjiUFbKN0rYHZdqSq W5DPTgto+3Jiw0lawn/keed+JVzSwJvM98xAWaNISKsjm86lMtH5lOcDps2Jz4aTKj0fA/iha lpEjNd0S+Mw0Y2u7Q9h/EBiXsbL5UYhg1e3CuidZ4ZOUB+Ey71cFajuDeoW+p Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.252, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 07:33:44 -0000 Le 14/01/2021 à 16:49, Philippe Mathieu-Daudé a écrit : > On 7/9/20 9:19 PM, Peter Maydell wrote: >> On Fri, 3 Jul 2020 at 21:19, Philippe Mathieu-Daudé wrote: >>> >>> This is a proof-of-concept after chatting with Peter Maydell >>> on IRC earlier. >>> >>> Introduce the vmstate_no_state_to_migrate structure, and >>> a reference to it: vmstate_qdev_no_state_to_migrate. >>> Use this reference in devices with no fields to migrate. >>> >>> This is useful to catch devices missing vmstate, such: >>> - ads7846 >>> - mcf-uart >>> - mcf-fec >>> - versatile_i2c >>> - ... >>> >>> I am not sure about: >>> - gpex-pcihost >> >> I think it's correct that this has no internal state: >> the only interesting state is in the GPEXRootState, which >> is a TYPE_GPEX_ROOT_DEVICE which migrates itself. >> >> I made some comments on the "meaty" bits of the patchset, >> and reviewed one or two of the "mark this device as >> having no migration state" patches, but it doesn't seem >> worth reviewing all of them until the migration submaintainers >> have a chance to weigh in on whether they like the concept >> (I expect they're busy right now with freeze-related stuff :-)) > > Now that we are far from freeze-date is a good time to ping > again on this concept :) > > Most of the devices are ARM except: > - cpu-cluster (Eduardo/Marcel) > - hcd-ohci (Gerd) > - mac-nubus-bridge (Laurent) > - generic QOM (Daniel, Paolo) > > Is someone against this proposal? I'm not against the proposal, but I don't understand why we need this. Thanks, Laurent From MAILER-DAEMON Mon Jan 18 04:23:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1QkX-0002dn-MJ for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 04:23:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1QkV-0002bz-SG; Mon, 18 Jan 2021 04:22:59 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:32825) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1QkU-0005zv-7r; Mon, 18 Jan 2021 04:22:59 -0500 Received: by mail-wr1-x429.google.com with SMTP id 7so8459936wrz.0; Mon, 18 Jan 2021 01:22:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=gMJPUZg6CqWtEOOlMaBHvgfyN7dW5WThmSaIMy+HsZA=; b=A6IfZ+kpdcIxD2rRj6/a/OmQN16YYQ27QrJ3Gn1Lj1HHbDA8bEsFhL3uQ7Ylj+BTf6 CsHRMOPf1mJpv96wLlmlsSED5W/2zAcCQAHbcN3YrIWykf7D7vQ8oRnrSICNxJHcC92S ARIOz8zpVSv/7RFO/AIaA+fr4qQVwcQxJvSLGfNPWUVBDyOt/pMYLexyAjKkKpYknw4t 7tUmUllteSmpwTnZ45ioDjKQv2N3cktMD1OWswkzric+LIeu0wh4RKPgLt90LikzZqj3 ZM7250Eh7HYOfeehJQ8bg8zB1TPT7txPY52DKpPAPv6hG8vnqameVbmn2sn6Ds3IaB8f +NDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=gMJPUZg6CqWtEOOlMaBHvgfyN7dW5WThmSaIMy+HsZA=; b=jvGOiSYjehkuxSdvpEpfTzd61AvePDC1uoOjLFx+ExmBbD/tQkGOzW5LGfXBQkjoOE gab7FlOzVKeqhP4lUFPC0+YC0KyNmdR/krlwOOUAjGtSgb5xjA/dlYK8cQGglagAm6Yp FUXpGwFE2qQmLoq2p+vgSDlt5o/j2ELtbPbUuhivMQBV6xe12UWBoq3PTuZKA78sd5zc Dri/AgCcgv9Rj9WyCQLkBNPKsqMY7B/RUyNMAwulLiBfMIfF6YnG7HdZQWO89xAqU33X crsP2S9J50LSeQd9B2Tlpmm8nQmGzmLNwuljJr1Eh2+JrcipwAIjdG0l82HnW9ZJJeNc DhHg== X-Gm-Message-State: AOAM532nikmBI9gqSHWlnlw/C9At1BVGlAXnbIsIGqDQqf+c/KGP96KX XwzYC/7RJ07/FjyUxfN9cFA= X-Google-Smtp-Source: ABdhPJwkivlgOE8pgMcQ+N9IQbSUQvB8rAv629RAFZOMpOgMsNeJhBmaThIb8P6Xi5JPvSrShInkWQ== X-Received: by 2002:a5d:6686:: with SMTP id l6mr24791751wru.236.1610961776441; Mon, 18 Jan 2021 01:22:56 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id a184sm13089948wme.35.2021.01.18.01.22.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Jan 2021 01:22:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 00/18] hw: Mark the device with no migratable fields To: Laurent Vivier , Peter Maydell , Eduardo Habkost , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Paolo Bonzini , Gerd Hoffmann Cc: QEMU Developers , Artyom Tarasenko , "Dr . David Alan Gilbert" , qemu-arm , Marcel Apfelbaum , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Andrew Baumann , Joel Stanley , Subbaraya Sundeep , Mark Cave-Ayland , Andrew Jeffery , Juan Quintela References: <20200703201911.26573-1-f4bug@amsat.org> <17a5ddc4-c7d9-08f3-5260-f17e1bd48dac@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Mon, 18 Jan 2021 10:22:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.252, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 09:23:00 -0000 Hi Laurent, On 1/18/21 8:33 AM, Laurent Vivier wrote: > Le 14/01/2021 à 16:49, Philippe Mathieu-Daudé a écrit : >> On 7/9/20 9:19 PM, Peter Maydell wrote: >>> On Fri, 3 Jul 2020 at 21:19, Philippe Mathieu-Daudé wrote: >>>> >>>> This is a proof-of-concept after chatting with Peter Maydell >>>> on IRC earlier. >>>> >>>> Introduce the vmstate_no_state_to_migrate structure, and >>>> a reference to it: vmstate_qdev_no_state_to_migrate. >>>> Use this reference in devices with no fields to migrate. >>>> >>>> This is useful to catch devices missing vmstate, such: >>>> - ads7846 >>>> - mcf-uart >>>> - mcf-fec >>>> - versatile_i2c >>>> - ... >>>> >>>> I am not sure about: >>>> - gpex-pcihost >>> >>> I think it's correct that this has no internal state: >>> the only interesting state is in the GPEXRootState, which >>> is a TYPE_GPEX_ROOT_DEVICE which migrates itself. >>> >>> I made some comments on the "meaty" bits of the patchset, >>> and reviewed one or two of the "mark this device as >>> having no migration state" patches, but it doesn't seem >>> worth reviewing all of them until the migration submaintainers >>> have a chance to weigh in on whether they like the concept >>> (I expect they're busy right now with freeze-related stuff :-)) >> >> Now that we are far from freeze-date is a good time to ping >> again on this concept :) >> >> Most of the devices are ARM except: >> - cpu-cluster (Eduardo/Marcel) >> - hcd-ohci (Gerd) >> - mac-nubus-bridge (Laurent) >> - generic QOM (Daniel, Paolo) >> >> Is someone against this proposal? > > I'm not against the proposal, but I don't understand why we need this. IIRC the IRC discussion followed this thread: https://www.mail-archive.com/qemu-devel@nongnu.org/msg554453.html Quoting Peter: > I think we should care about migration on all architectures > and devices, in the sense that we want savevm/loadvm to work. > This is a really useful debugging and user tool, and when > I'm reviewing devices it's the minimum bar I think new > devices should clear. You then get migration "for free" but > I don't particularly expect it to be used compared to > snapshot save/restore. (Of course some of our existing code > doesn't support this, and we don't have a good way of testing > so bugs creep in easily, but as a principle I think it's > good.) Currently there is no automatic way to catch missing vmstate, we rely on code review (mostly from Peter...). To be able to add a code check to catch the future device added, we need to first clean the (old) devices missing VMState, justifying why each doesn't have any field to migrate. Also IMO it is simpler to have an unified API, rather than explaining each experienced and new contributor why "old style qdev" are allowed to do things than "new introduced qdev" can't do anymore. Regards, Phil. From MAILER-DAEMON Mon Jan 18 05:06:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1RQL-0004Jf-UY for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 05:06:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1RQJ-0004Hk-QV; Mon, 18 Jan 2021 05:06:11 -0500 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]:38941) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1RQC-0001Ey-PR; Mon, 18 Jan 2021 05:06:11 -0500 Received: by mail-lf1-x135.google.com with SMTP id a12so23239717lfl.6; Mon, 18 Jan 2021 02:06:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=XocRYHiVxslDJWv3JJvv1X/oaSWvgR0HrgzNqvEZJC8=; b=BralT5FJ2BQlwvu4soL4NiypPACjF+HwK7xEDwmE0V8CjSiMoxrrMgsdcz9W7/iHH8 enzHkqHdkrie2C9jvh3IKYd3M3clADlu+z5RCRQIe5CPjYzRk+wwJ9Q1JRT/GljubDeb UHlXpxfucogw4SJzWgmObYZRtNm/H6dv+ozj6TBntisVTfQpquy/MNW0nFgKftAt7h/7 9JO9+QLvgZZhjguBb0xIFg7yMTV3kMiZAOCa7rDPmNKiwKfB7QfgcV7F2i54f0W4BgL2 rnISxntgse4T+u+1vGYhL8B38dCSyqn8wYPOWltfR8Tbx6kT+pMLfgIOffONR5wS0nGg ysyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=XocRYHiVxslDJWv3JJvv1X/oaSWvgR0HrgzNqvEZJC8=; b=nstlmi4WjVC/pTqUZF8hegwp/cmPP6uexylRg8SY1if3WRhKaPMu1//sZ/CTgs85DE ClKeoVJrmi25YlBi76L2llzhJn7YUU5KEsNfeW/Sk/M4gZ7godRngG8wSCCi8QJ6J+AX 1GPP/CUHDZw7jmRUjxTjzUIFumjcWvCcD7gwcl75F9S6Kzf6ELxdp3cxIYIJ6H6FrC/R Ybb5WbbKrUZqL2sp9fibaK2pISlvPo2AiqcXxTFXmk4SIZFVoN9INji6aCAUtuNJfD8d nbkgh2NWnEuq1h0004LFyda/tA2afN3PvczIPMhqWktUDsyyu2tKomMCyOVn93273iqQ PGaQ== X-Gm-Message-State: AOAM533tauMk9KjqgMaJdpuCEdYSULU9ioWW/UGSbGYr2rmXQK8doR9r fJOI8i/Q/wNqMYtCRoIHJtU= X-Google-Smtp-Source: ABdhPJyKWCnVP97w1CXM6rlcP9mDSIcsRhIb4l/Q3pbuBHMapbIgZ6h/nUZsD1GWojdvHR+5nbixOA== X-Received: by 2002:a05:6512:286:: with SMTP id j6mr10609987lfp.92.1610964361243; Mon, 18 Jan 2021 02:06:01 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id p1sm1852774lfe.217.2021.01.18.02.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 02:06:00 -0800 (PST) Date: Mon, 18 Jan 2021 11:05:58 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210118100557.GA11373@fralle-msi> References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x135.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 10:06:12 -0000 Hi Bin, On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > Hi Francisco, > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > wrote: > > > > Hi Bin, > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > Hi Francisco, > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > wrote: > > > > > > > > Hi Bin, > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > From: Bin Meng > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > > bytes are expected to be received after it receives a command. For > > > > > example, depending on the address mode, either 3-byte address or > > > > > 4-byte address is needed. > > > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > > sending the address bytes, and the dummy cycles need to be counted > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > > It is not in bit, or cycle. However for some reason the model has > > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > > approach is to convert the number of dummy cycles to bytes based on > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > > > While not being the original implementor I must assume that above solution was > > > > considered but not chosen by the developers due to it is inaccuracy (it > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > > also because the detail is already in use for catching exactly above error. > > > > > > > > > > I found no clue from the commit message that my proposed solution here > > > was ever considered, otherwise all SPI controller models supporting > > > software generation should have been found out seriously broken long > > > time ago! > > > > > > The controllers you are referring to might lack support for commands requiring > > dummy clock cycles but I really hope they work with the other commands? If so I > > I am not sure why you view dummy clock cycles as something special > that needs some special support from the SPI controller. For the case > 1 controller, it's nothing special from the controller perspective, > just like sending out a command, or address bytes, or data. The > controller just shifts data bit by bit from its tx fifo and that's it. > In the Xilinx GQSPI controller case, the dummy cycles can either be > sent via a regular data (the case 1 controller) in the tx fifo, or > automatically generated (case 2 controller) by the hardware. Ok, I'll try to explain my view point a little differently. For that we also need to keep in mind that QEMU models HW, and any binary that runs on a HW board supported in QEMU should ideally run on that board inside QEMU aswell (this can be a bare metal application equaly well as a modified u-boot/Linux using SPI commands with a non multiple of 8 number of dummy clock cycles). Once functionality has been introduced into QEMU it is not easy to know which intentional or untentional features provided by the functionality are being used by users. One of the (perhaps not well known) features I'm aware of that is in use and is provided by the accurate dummy clock cycle modeling inside m25p80 is the be ability to test drivers accurately regarding the dummy clock cycles (even when using commands with a non-multiple of 8 number of dummy clock cycles), but there might be others aswell. So by removing this functionality above use case will brake, this since those test will not be reliable. Furthermore, since users tend to be creative it is not possible to know if there are other use cases that will be affected. This means that in case [1] needs to be followed the safe path is to add functionality instead of removing. Luckily it also easier in this case, see below. > > > don't think it is fair to call them 'seriously broken' (and else we should > > probably let the maintainers know about it). Most likely the lack of support > > I called it "seriously broken" because current implementation only > considered one type of SPI controllers while completely ignoring the > other type. If we change view and see this from the perspective of m25p80, it models the commands a certain way and provides an API that the SPI controllers need to implement for interacting with it. It is true that there are SPI controllers referred to above that do not support the portion of that API that corresponds to commands with dummy clock cycles, but I don't think it is true that this is broken since there is also one SPI controller that has a working implementation of m25p80's full API also when transfering through a tx fifo (use case 1). But as mentioned above, by doing a minor extension and improvement to m25p80's API and allow for toggling the accuracy from dummy clock cycles to dummy bytes [1] will still be honored as in the same time making it possible to have full support for the API in the SPI controllers that currently do not (please reread the proposal in my previous reply that attempts to do this). I myself see this as win/win situation, also because no controller should need modifications. > > > for the commands is because no request has been made for them. Also there is > > one controller that has support. > > Definitely it's not "no request". Nearly all SPI flashes support the > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > "seriously broken" for those case 1 type controllers because they > cannot read anything from the m25p80 model at all. Unless the guest > software being tested only uses Read (03h) command which is not > affected. But I can't find a software that uses Read instead of Fast > Read. > > > > The issue you pointed out that we require the total number of dummy > > > bits should be multiple of 8 is true, that's why I added the > > > unimplemented log message in this series (patch 2/3/4) to warn users > > > if this expectation is not met. However this will not cause any issue > > > when running U-Boot or Linux, because both spi-nor drivers expect the > > > same assumption as we do here. > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > > there is a logic to calculate the dummy bytes needed for fast read > > > command: > > > > > > /* convert the dummy cycles to the number of bytes */ > > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > Note the default dummy cycles configuration for all flashes I have > > > looked into as of today, meets the multiple of 8 assumption. On some > > > flashes the dummy cycle number is configurable, and if it's been > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > the first place. > > > > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > > flash controllers. There are major two cases: > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > > For such case, driver will calculate the correct number of dummy > > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > > fix flashes working with such controllers. > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > > > Please send patches to explain this in detail how this is going to > > > work. I am open to all possible solutions. > > > > In that case I suggest that you instead try with a device property > > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > > count to dummy bytes inside m25p80. Below is an example on how to modify the > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > > can follow a similar pattern). This way the fifo mode will be able to work the > > way you desire while also keeping the current functionality intact. Suddenly > > removing functionality (features) will take users by surprise. > > I don't think we are removing any features. This is a fix to make the > model to be used by any SPI controllers. > > As I pointed out, both U-Boot and Linux have the multiple of 8 > assumption for the dummy bit, which is the default configuration for > all flashes I have looked into so far. Can you please comment what use > case you want to support? I requested a U-Boot/Linux kernel testing in > the previous SST thread [1] against Xilinx GQSPI but there was no > response. In [2] instructions on how to boot u-boot/Linux is found. For building the various software components I followed the official doc in [3]. Best regards, Francisco [1] qemu/docs/system/deprecated.rst [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md [3] https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/460653138/Xilinx+Open+Source+Linux > > [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1606704602-59435-1-git-send-email-bmeng.cn@gmail.com/ > > > > > static void decode_fast_read_cmd(Flash *s) > > { > > uint8_t dummy_clk_cycles = 0; > > uint8_t extra_bytes; > > > > s->needed_bytes = get_addr_length(s); > > > > /* Obtain the number of dummy clock cycles needed */ > > switch (get_man(s)) { > > case MAN_WINBOND: > > dummy_clk_cycles += 8; > > break; > > case MAN_NUMONYX: > > dummy_clk_cycles += numonyx_extract_cfg_num_dummies(s); > > break; > > case MAN_MACRONIX: > > if (extract32(s->volatile_cfg, 6, 2) == 1) { > > dummy_clk_cycles += 6; > > } else { > > dummy_clk_cycles += 8; > > } > > break; > > case MAN_SPANSION: > > dummy_clk_cycles += extract32(s->spansion_cr2v, > > SPANSION_DUMMY_CLK_POS, > > SPANSION_DUMMY_CLK_LEN > > ); > > break; > > default: > > break; > > } > > > > if (s->model_dummy_bytes) { > > int lines = 1; > > > > /* > > * Expect dummy bytes from the controller so convert the dummy > > * clock cycles to dummy_bytes. > > */ > > extra_bytes = convert_to_dummy_bytes(dummy_clk_count, lines); > > } else { > > /* Model individual dummy clock cycles as byte writes */ > > extra_bytes = dummy_clk_cycles; > > } > > > > s->needed_bytes += extra_bytes; > > s->pos = 0; > > s->len = 0; > > s->state = STATE_COLLECTING_DATA; > > } > > > > Best regards, > > Francisco Iglesias > > > > > > > > > > > > > > - Dummy bytes not prepared by drivers. Drivers just tell the hardware > > > > > the dummy cycle configuration via some registers, and hardware will > > > > > automatically generate dummy cycles for us. Fixing the m25p80 model > > > > > is not enough, and we will need to fix the SPI/QSPI models for such > > > > > controllers. > > > > > > > > > > This series fixes the mess in the m25p80 from the flash side first, > > > > > > > > Considering the problems solved by the solution in tree I find m25p80 pretty > > > > clean, at least I don't see any clearly better way for accurately modeling the > > > > dummy clock cycles. Counting bits instead of bytes would for example still > > > > force the controllers to mark which bits to count (when transmitting one dummy > > > > byte from a txfifo on four lines (Quad command) it generates 2 dummy clock > > > > cycles since it takes two cycles to transfer 8 bits). > > > > > > > > > > SPI is a bit based protocol, not bytes. If you insist on bit modeling > > > with the dummy cycles then you should also suggest we change all > > > cycles (including command/addr/dummy/data phases) to be modeled with > > > bits. That way we can accurately emulate everything, for example one > > > potential problem like transferring 9 bit in the data phase. > > > > > > However modeling everything with bit is super inefficient. My view is > > > that we should avoid trying to support uncommon use cases (like not > > > multiple of 8 for dummy bits) in QEMU. > > Regards, > Bin From MAILER-DAEMON Mon Jan 18 06:48:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1T1c-0003KN-EJ for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 06:48:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1T1b-0003JG-FG for qemu-arm@nongnu.org; Mon, 18 Jan 2021 06:48:47 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:21021) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l1T1Z-0007p3-TX for qemu-arm@nongnu.org; Mon, 18 Jan 2021 06:48:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610970524; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VFMUsPlYLVMAWHd89rOzuMhGW52wriQcxIJYel05Sh8=; b=L7Qu6RNK7Bgot6aiS+GTkO49kC0DJ9YP6aWRy2Bb1ofQL9koDgwkPgJV7GBUzfkyfN3+3P D3iEJss7G1qDO6TPCgSvup+OPjIAjYcrKaEVpNDbFNc5pAk2O0i8ksOxgBASQ/DQUBKO1p hEGQCUKgSUlSc2NuaoTv61luSb4HaPs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-509-xeNc-rJKMce10F1jbaM7CQ-1; Mon, 18 Jan 2021 06:48:41 -0500 X-MC-Unique: xeNc-rJKMce10F1jbaM7CQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E3EE918C8C0C; Mon, 18 Jan 2021 11:48:38 +0000 (UTC) Received: from work-vm (ovpn-115-197.ams2.redhat.com [10.36.115.197]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A702260BFA; Mon, 18 Jan 2021 11:48:28 +0000 (UTC) Date: Mon, 18 Jan 2021 11:48:25 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric?= Le Goater , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Subject: Re: [RFC PATCH v2 01/20] migration/vmstate: Restrict vmstate_dummy to user-mode Message-ID: <20210118114825.GJ2998@work-vm> References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-2-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-2-f4bug@amsat.org> User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.189, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 11:48:47 -0000 * Philippe Mathieu-Daudé (f4bug@amsat.org) wrote: > 'vmstate_dummy' is special and only used for user-mode. Rename > it to something more specific. > It was introduced restricted to user-mode in commit c71c3e99b8 > ("Add a vmstate_dummy struct for CONFIG_USER_ONLY") but this > restriction was later removed in commit 6afc14e92ac ("migration: > Fix warning caused by missing declaration of vmstate_dummy"). > Avoid the missing declaration warning by adding a stub for the > symbol, and restore the #ifdef'ry. > > Suggested-by: Daniel Berrangé > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Dr. David Alan Gilbert > --- > include/hw/core/cpu.h | 2 +- > include/migration/vmstate.h | 4 +++- > stubs/vmstate.c | 4 +++- > 3 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 140fa32a5e3..c79a58db9b9 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -1132,7 +1132,7 @@ bool target_words_bigendian(void); > #ifdef CONFIG_SOFTMMU > extern const VMStateDescription vmstate_cpu_common; > #else > -#define vmstate_cpu_common vmstate_dummy > +#define vmstate_cpu_common vmstate_user_mode_cpu_dummy > #endif > > #define VMSTATE_CPU() { \ > diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h > index 075ee800960..dda65c9987d 100644 > --- a/include/migration/vmstate.h > +++ b/include/migration/vmstate.h > @@ -194,7 +194,9 @@ struct VMStateDescription { > const VMStateDescription **subsections; > }; > > -extern const VMStateDescription vmstate_dummy; > +#if defined(CONFIG_USER_ONLY) > +extern const VMStateDescription vmstate_user_mode_cpu_dummy; > +#endif > > extern const VMStateInfo vmstate_info_bool; > > diff --git a/stubs/vmstate.c b/stubs/vmstate.c > index cc4fe41dfc2..8da777a1fb4 100644 > --- a/stubs/vmstate.c > +++ b/stubs/vmstate.c > @@ -1,7 +1,9 @@ > #include "qemu/osdep.h" > #include "migration/vmstate.h" > > -const VMStateDescription vmstate_dummy = {}; > +#if defined(CONFIG_USER_ONLY) > +const VMStateDescription vmstate_user_mode_cpu_dummy = {}; > +#endif > > int vmstate_register_with_alias_id(VMStateIf *obj, > uint32_t instance_id, > -- > 2.26.2 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Mon Jan 18 07:04:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1TH6-0000na-Qp for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 07:04:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1TH4-0000kS-OK; Mon, 18 Jan 2021 07:04:46 -0500 Received: from mout.kundenserver.de ([217.72.192.75]:44413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1TGz-0006UD-Qb; Mon, 18 Jan 2021 07:04:46 -0500 Received: from [192.168.100.1] ([82.252.149.54]) by mrelayeu.kundenserver.de (mreue107 [213.165.67.119]) with ESMTPSA (Nemesis) id 1N5W4y-1m8EBn2EWI-016vNa; Mon, 18 Jan 2021 13:04:25 +0100 Subject: Re: [RFC PATCH v2 15/20] hw/nubus/mac-nubus-bridge: Mark the device with no migratable fields To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , "Dr. David Alan Gilbert" , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-16-f4bug@amsat.org> From: Laurent Vivier Message-ID: <641232f7-5e65-f066-b1a3-24a89e074eab@vivier.eu> Date: Mon, 18 Jan 2021 13:04:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-16-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: fr Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:uhQ20pO53uAaHGI95lgej+N+JCXx1J/pYMIgsjU6VGFH0+kSx4k 1V63uBA45aafqYAWORdipxcR/yWWxhqHFI01AmpeOxdKKs98STtG2dW3DtLaDHE/K++Mjdc ggoWO0xNDuo3RR45Zd0gqB8dSmQalxcxCcd1jQtc7W4WlwsvK33o0hqRWUSUXbhuZcVWPBW OOb0A4g9Xp50L6cuUgcpQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:oTBFu+24Gd8=:nnASlFm8m4tUi5ehpptpS9 L8bIe4mhb61Y8+LdlUwxk4AbbWvo9pDpfW7EUhXKp5XGZC84W+qCaAAVTJcWADRINcMIo4txb Mths7T9M7o4yl4+VUia9VNdZ99mEBp8JDrwXSrqob8ICJ8wERfZsSFnmm/uyTYsGlTXEzS5Md Kh3jfeiRj/IC+R2xySuftnN+FoMgTdkBdZPufIWZKsb322F+znMcOuW4ptiZabr8BJcLtLC5I GI4yTCn3g7NbsUDFegEun1Qk6bUlNz7faNq2C3nM0iJuvvzjAVJKJWpRzXTdTSq3zXtRmo0TK IPQYBGczR99Xx2PZMWZpmm2KTB0D2EwdeauURx4JHsiou8r5hjhIbY53SqLVxH9rbwUDfHGk+ oGkvxDQDPVCl/3LEIleQC4FoEu+Yql1LyuJdRQXJkYQVUibuBu2LxlEyUtLAC Received-SPF: none client-ip=217.72.192.75; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.194, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 12:04:47 -0000 Le 17/01/2021 à 20:24, Philippe Mathieu-Daudé a écrit : > This device doesn't have fields to migrate. Be explicit > by using vmstate_qdev_no_state_to_migrate. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/nubus/mac-nubus-bridge.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c > index 7c329300b82..ede36ccc5dd 100644 > --- a/hw/nubus/mac-nubus-bridge.c > +++ b/hw/nubus/mac-nubus-bridge.c > @@ -27,6 +27,7 @@ static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data) > DeviceClass *dc = DEVICE_CLASS(klass); > > dc->desc = "Nubus bridge"; > + dc->vmsd = vmstate_qdev_no_state_to_migrate; > } > > static const TypeInfo mac_nubus_bridge_info = { > Reviewed-by: Laurent Vivier From MAILER-DAEMON Mon Jan 18 07:32:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1Ti1-0000qS-Pc for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 07:32:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1Thz-0000oT-N2; Mon, 18 Jan 2021 07:32:35 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:38123) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1Thv-0002dz-CD; Mon, 18 Jan 2021 07:32:35 -0500 Received: by mail-yb1-xb30.google.com with SMTP id r32so2774590ybd.5; Mon, 18 Jan 2021 04:32:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=6EyI9x6cFHpTQV8J3KQ2NVQOkpXY5m6GxTR3FGz9GkM=; b=JrdAN/wPiSMTPU6vCdpF4sPNqxIwIfz9K86OGs8JFI5OVO25DNqczX8RIlTd4dYwHS 4BHk/hgxTEWlMucMF+2vnmM/WjETUamSTQoto16n0sdlMUCWG8ofO6FQ7mK2HSqA7/kF tF79/Wxt/WatKyVR6RJWeUX+Y2qwDzpDDJ2JOdSjJ8zmPgziYQrd25lE+ZWc/EvkpRpM USrE5Qg0AL0WRNKKM8okyjkANUoFM7s4TFgqHpZGVaGTKA0qwXJ76Z6oFPGHhh4fu1vb yzEONgnDAlLQmYin9Bxq7WrCsrhxzWnvAY7ho639q4bgIOGO79SbnilrCRFzreRl3wzr pGOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=6EyI9x6cFHpTQV8J3KQ2NVQOkpXY5m6GxTR3FGz9GkM=; b=KoLeV61Z5XOfTgKGKMwVBwuULPUr0geTHXRll434N7kEg4IPogbMU3lQOdX1WPx7AQ BSNRSkvA4bftgf9V4fzt1gzbh5gSTG4jNC/ko8xoWJ7w4J0emSBCjroq1imnV/DJho+s TgBFm4K7Gj2fhobiSpoj9hhveIH1OyCah88sYR7iIfapQa/SLe0Alh+tIrKH7Fs+xfYK fcwf2s5ri4oL6EXmZQp1kkxEsQaR/oAN73L8Kuo4FVMBitJ9bmmS/SdBBb06BqtVazZn +pKK2XBSgnHwBrrhSOwFgxqTP5snWUwciLI5ET70y6D6VVg6GyrWh+2zTuoz+Muji995 dlVw== X-Gm-Message-State: AOAM530PLsQKHq8Y85AQ0i5phMJ6gpF3G6oof+QCbYJWAExi9s3XBZnT pKIQuc1xgYlo8hLLzUmtPRZe2d8UNpCvKbnEc5k= X-Google-Smtp-Source: ABdhPJxj4C1ed7MYLXzVeNfspjAt/2hl/SO7Pox69646JFq6xOP2EMV19O4GAKxtzhvKNMYcvMnGOj+eF9DSyjRMxGE= X-Received: by 2002:a25:b8ca:: with SMTP id g10mr34044033ybm.517.1610973149166; Mon, 18 Jan 2021 04:32:29 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> In-Reply-To: <20210118100557.GA11373@fralle-msi> From: Bin Meng Date: Mon, 18 Jan 2021 20:32:19 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Francisco Iglesias Cc: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 12:32:35 -0000 Hi Francisco, On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias wrote: > > Hi Bin, > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > Hi Francisco, > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > wrote: > > > > > > Hi Bin, > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > Hi Francisco, > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > wrote: > > > > > > > > > > Hi Bin, > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many foll= ow-up > > > > > > bytes are expected to be received after it receives a command. = For > > > > > > example, depending on the address mode, either 3-byte address o= r > > > > > > 4-byte address is needed. > > > > > > > > > > > > For fast read family commands, some dummy cycles are required a= fter > > > > > > sending the address bytes, and the dummy cycles need to be coun= ted > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in b= yte. > > > > > > It is not in bit, or cycle. However for some reason the model h= as > > > > > > been using the number of dummy cycles for s->needed_bytes. The = right > > > > > > approach is to convert the number of dummy cycles to bytes base= d on > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read= Quad > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4= / 8). > > > > > > > > > > While not being the original implementor I must assume that above= solution was > > > > > considered but not chosen by the developers due to it is inaccura= cy (it > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multi= ple of 8, > > > > > meaning that if the controller is wrongly programmed to generate = 7 the error > > > > > wouldn't be caught and the controller will still be considered "c= orrect"). Now > > > > > that we have this detail in the implementation I'm in favor of ke= eping it, this > > > > > also because the detail is already in use for catching exactly ab= ove error. > > > > > > > > > > > > > I found no clue from the commit message that my proposed solution h= ere > > > > was ever considered, otherwise all SPI controller models supporting > > > > software generation should have been found out seriously broken lon= g > > > > time ago! > > > > > > > > > The controllers you are referring to might lack support for commands = requiring > > > dummy clock cycles but I really hope they work with the other command= s? If so I > > > > I am not sure why you view dummy clock cycles as something special > > that needs some special support from the SPI controller. For the case > > 1 controller, it's nothing special from the controller perspective, > > just like sending out a command, or address bytes, or data. The > > controller just shifts data bit by bit from its tx fifo and that's it. > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > sent via a regular data (the case 1 controller) in the tx fifo, or > > automatically generated (case 2 controller) by the hardware. > > Ok, I'll try to explain my view point a little differently. For that we a= lso > need to keep in mind that QEMU models HW, and any binary that runs on a H= W > board supported in QEMU should ideally run on that board inside QEMU aswe= ll > (this can be a bare metal application equaly well as a modified u-boot/Li= nux > using SPI commands with a non multiple of 8 number of dummy clock cycles)= . > > Once functionality has been introduced into QEMU it is not easy to know w= hich > intentional or untentional features provided by the functionality are bei= ng > used by users. One of the (perhaps not well known) features I'm aware of = that > is in use and is provided by the accurate dummy clock cycle modeling insi= de > m25p80 is the be ability to test drivers accurately regarding the dummy c= lock > cycles (even when using commands with a non-multiple of 8 number of dummy= clock > cycles), but there might be others aswell. So by removing this functional= ity > above use case will brake, this since those test will not be reliable. > Furthermore, since users tend to be creative it is not possible to know i= f > there are other use cases that will be affected. This means that in case = [1] > needs to be followed the safe path is to add functionality instead of rem= oving. > Luckily it also easier in this case, see below. I understand there might be users other than U-Boot/Linux that use an odd number of dummy bits (not multiple of 8). If your concern was about model behavior changes, sure I can update qemu/docs/system/deprecated.rst to mention that some flashes in the m25p80 model now implement dummy cycles as bytes. > > > > > don't think it is fair to call them 'seriously broken' (and else we s= hould > > > probably let the maintainers know about it). Most likely the lack of = support > > > > I called it "seriously broken" because current implementation only > > considered one type of SPI controllers while completely ignoring the > > other type. > > If we change view and see this from the perspective of m25p80, it models = the > commands a certain way and provides an API that the SPI controllers need = to > implement for interacting with it. It is true that there are SPI controll= ers > referred to above that do not support the portion of that API that corres= ponds > to commands with dummy clock cycles, but I don't think it is true that th= is is > broken since there is also one SPI controller that has a working implemen= tation > of m25p80's full API also when transfering through a tx fifo (use case 1)= . But > as mentioned above, by doing a minor extension and improvement to m25p80'= s API > and allow for toggling the accuracy from dummy clock cycles to dummy byte= s [1] > will still be honored as in the same time making it possible to have full > support for the API in the SPI controllers that currently do not (please = reread > the proposal in my previous reply that attempts to do this). I myself see= this > as win/win situation, also because no controller should need modification= s. > I am afraid your proposal does not work. Your proposed new device property 'model_dummy_bytes' to select to convert the accurate dummy clock cycle count to dummy bytes inside m25p80, is hard to justify as a property to the flash itself, as the behavior is tightly coupled to how the SPI controller works. Please take a look at the Xilinx GQSPI controller, which supports both use cases, that the dummy cycles can be transferred via tx fifo, or generated by the controller automatically. Please read the example given in: table 24=E2=80=9022, an example of Generic FIFO Contents for Quad I/O R= ead Command (EBh) in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ult= rascale-trm.pdf If you choose to set the m25p80 device property 'model_dummy_bytes' to true when working with the Xilinx GQSPI controller, you are bound to only allow guest software to use tx fifo to transfer the dummy cycles, and this is wrong. > > > > > > for the commands is because no request has been made for them. Also t= here is > > > one controller that has support. > > > > Definitely it's not "no request". Nearly all SPI flashes support the > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > > "seriously broken" for those case 1 type controllers because they > > cannot read anything from the m25p80 model at all. Unless the guest > > software being tested only uses Read (03h) command which is not > > affected. But I can't find a software that uses Read instead of Fast > > Read. > > > > > > The issue you pointed out that we require the total number of dummy > > > > bits should be multiple of 8 is true, that's why I added the > > > > unimplemented log message in this series (patch 2/3/4) to warn user= s > > > > if this expectation is not met. However this will not cause any iss= ue > > > > when running U-Boot or Linux, because both spi-nor drivers expect t= he > > > > same assumption as we do here. > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data()= , > > > > there is a logic to calculate the dummy bytes needed for fast read > > > > command: > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > op.dummy.nbytes =3D (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > > > Note the default dummy cycles configuration for all flashes I have > > > > looked into as of today, meets the multiple of 8 assumption. On som= e > > > > flashes the dummy cycle number is configurable, and if it's been > > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > > the first place. > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI or Q= SPI > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller = fifo. > > > > > > For such case, driver will calculate the correct number of du= mmy > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 mode= l will > > > > > > fix flashes working with such controllers. > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle i= mplementation > > > > > inside m25p80. Perhaps one of the following could be looked into:= configurating > > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or = by inheriting > > > > > some functionality handling this in the SPI controller. Or a mixt= ure of above. > > > > > > > > Please send patches to explain this in detail how this is going to > > > > work. I am open to all possible solutions. > > > > > > In that case I suggest that you instead try with a device property > > > 'model_dummy_bytes' used to select to convert the accurate dummy cloc= k cycle > > > count to dummy bytes inside m25p80. Below is an example on how to mod= ify the > > > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > > > decode_fast_read_cmd function (the other commands requiring dummy clo= ck cycles > > > can follow a similar pattern). This way the fifo mode will be able to= work the > > > way you desire while also keeping the current functionality intact. S= uddenly > > > removing functionality (features) will take users by surprise. > > > > I don't think we are removing any features. This is a fix to make the > > model to be used by any SPI controllers. > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > assumption for the dummy bit, which is the default configuration for > > all flashes I have looked into so far. Can you please comment what use > > case you want to support? I requested a U-Boot/Linux kernel testing in > > the previous SST thread [1] against Xilinx GQSPI but there was no > > response. > > In [2] instructions on how to boot u-boot/Linux is found. For building th= e > various software components I followed the official doc in [3]. I see the following QEMU commands are used to test booting U-Boot/Linux: $ qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don -m 4G -serial stdio -display none -device loader,file=3Du-boot.elf -kernel bl31.elf -device loader,addr=3D0x40000000,file=3DImage -device loader,addr=3D0x2000000,file=3Dsystem.dtb I am not sure where the system.dtb gets built from? In [3], it mentions the Xilinx QEMU is used. And a different QEMU command is used as the example to launch U-Boot which is different from your command above. See https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841606/QEMU+-+Z= ynq+UltraScale+MPSoC#QEMU-ZynqUltraScale+MPSoC-RunningaZynqUltraScale+U-boo= tImageOnXilinx'sARMQEMU $ ./aarch64-softmmu/qemu-system-aarch64 -M arm-generic-fdt -serial mon:stdio -serial /dev/null -display none \ -device loader,addr=3D0xfd1a0104,data=3D0x8000000e,data-len=3D4 \ # Un-re= set the A53 -device loader,file=3D./pre-built/linux/images/bl31.elf,cpu-num=3D0 \ # ARM Trusted Firmware -device loader,file=3D./pre-built/linux/images/u-boot.elf\ # The u-boot exectuable -hw-dtb ./pre-built/linux/images/zynqmp-qemu-arm.dtb # HW Device Tree that QEMU uses to generate the model It is using a machine called "arm-generic-fdt", but in the mainline QEMU there is no such machine called "arm-generic-fdt". > > Best regards, > Francisco > > [1] qemu/docs/system/deprecated.rst > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zc= u102-atf-u-boot-linux.md > [3] https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/460653138/Xilin= x+Open+Source+Linux > Regards, Bin From MAILER-DAEMON Mon Jan 18 15:11:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ars-0002g8-05 for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 15:11:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1arl-0002fP-6y for qemu-arm@nongnu.org; Mon, 18 Jan 2021 15:11:09 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:57228) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l1arg-000132-5m for qemu-arm@nongnu.org; Mon, 18 Jan 2021 15:11:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611000661; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WUVVBo6Ajtsp1p1cl9vt8il5Uqeysu/ud/O2QfPozL8=; b=CpkRA0UoG2T42432G5Zk3Yc3vDG90e8ku6CiE8eLb/j2C1kmuvR75XnsWRiF/ukugm/jHW 4RqkxITZ+y7s51n9Jl8qwhIXOlh5RfhT/unmOcq8BR6HgPeEYxzDaXPNHTtIZdJXxqX9dX 6fXQFkztwib7drjMgwcssO9X0s2ZbvI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-492-_5-D_X5wMBS0cETqTD7Ozg-1; Mon, 18 Jan 2021 15:10:58 -0500 X-MC-Unique: _5-D_X5wMBS0cETqTD7Ozg-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 8A459192FDA3; Mon, 18 Jan 2021 20:10:56 +0000 (UTC) Received: from work-vm (ovpn-115-197.ams2.redhat.com [10.36.115.197]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BB2DE1002388; Mon, 18 Jan 2021 20:10:47 +0000 (UTC) Date: Mon, 18 Jan 2021 20:10:45 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric?= Le Goater , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Subject: Re: [RFC PATCH v2 10/20] hw/usb/hcd-ohci: Mark the device with no migratable fields Message-ID: <20210118201045.GI9899@work-vm> References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-11-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-11-f4bug@amsat.org> User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.175, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 20:11:09 -0000 * Philippe Mathieu-Daudé (f4bug@amsat.org) wrote: > This device doesn't have fields to migrate. Be explicit > by using vmstate_qdev_no_state_to_migrate. > > Add a more descriptive comment to keep a clear separation > between static property vs runtime changeable. > > Signed-off-by: Philippe Mathieu-Daudé OK, Reviewed-by: Dr. David Alan Gilbert although I think it's quite interesting; I think we have a base class which has data to migrate which expects any child classes to migrate it's data; so marking it as not actually having any state is not quite right. > --- > hw/usb/hcd-ohci.h | 2 ++ > hw/usb/hcd-ohci.c | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h > index 11ac57058d1..fd4842a352f 100644 > --- a/hw/usb/hcd-ohci.h > +++ b/hw/usb/hcd-ohci.h > @@ -101,6 +101,8 @@ struct OHCISysBusState { > /*< public >*/ > > OHCIState ohci; > + > + /* Properties */ > char *masterbus; > uint32_t num_ports; > uint32_t firstport; > diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c > index f8c64c8b95b..302aab30992 100644 > --- a/hw/usb/hcd-ohci.c > +++ b/hw/usb/hcd-ohci.c > @@ -2007,6 +2007,7 @@ static void ohci_sysbus_class_init(ObjectClass *klass, void *data) > DeviceClass *dc = DEVICE_CLASS(klass); > > dc->realize = ohci_realize_pxa; > + dc->vmsd = vmstate_qdev_no_state_to_migrate; > set_bit(DEVICE_CATEGORY_USB, dc->categories); > dc->desc = "OHCI USB Controller"; > device_class_set_props(dc, ohci_sysbus_properties); > -- > 2.26.2 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Mon Jan 18 19:32:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewe-0002yN-Hn for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewd-0002yB-QL; Mon, 18 Jan 2021 19:32:27 -0500 Received: from mail.mutex.one ([62.77.152.124]:49448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewb-0004A6-PW; Mon, 18 Jan 2021 19:32:27 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id 825A0BF42513; Tue, 19 Jan 2021 02:32:21 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ppqm5IpkYmRZ; Tue, 19 Jan 2021 02:32:21 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id D8B59BF423B3; Tue, 19 Jan 2021 02:32:20 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1611016341; bh=4wTVWjOzwu2FvqZ0TYOspRLJGdOCcZOJq1nz6R9tIKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YL14kqXsPmo/DcuhNmDV5G1PGymnO0W5OIUlQQB8vPBZiLpCSjqUgFtUtYU4pf1/J HRh8OGtI1cmDydY61++8LBcDzuH7816PFGiWp6A0kO94PdqmbiwBfe4eSqP805c1w6 QX8NKMIhSwi08PRSn9IT08EkwDwE/lhCVMB76oO8= From: Marian Postevca To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Marcel Apfelbaum , Dongjiu Geng , Peter Maydell , Ben Warren , qemu-arm@nongnu.org, Paolo Bonzini , Xiang Zheng , Xiao Guangrong , Igor Mammedov , Sergio Lopez , "Michael S. Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 1/5] tests/acpi: allow updates for expected data files Date: Tue, 19 Jan 2021 02:32:12 +0200 Message-Id: <20210119003216.17637-2-posteuca@mutex.one> In-Reply-To: <20210119003216.17637-1-posteuca@mutex.one> References: <20210119003216.17637-1-posteuca@mutex.one> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:28 -0000 Signed-off-by: Marian Postevca --- tests/qtest/bios-tables-test-allowed-diff.h | 94 +++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..b20ae72949 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,95 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/APIC", +"tests/data/acpi/virt/FACP", +"tests/data/acpi/virt/GTDT", +"tests/data/acpi/virt/MCFG", +"tests/data/acpi/virt/SPCR", +"tests/data/acpi/virt/DSDT", +"tests/data/acpi/virt/APIC.numamem", +"tests/data/acpi/virt/FACP.numamem", +"tests/data/acpi/virt/GTDT.numamem", +"tests/data/acpi/virt/MCFG.numamem", +"tests/data/acpi/virt/SPCR.numamem", +"tests/data/acpi/virt/DSDT.numamem", +"tests/data/acpi/virt/SRAT.numamem", +"tests/data/acpi/virt/DSDT.memhp", +"tests/data/acpi/virt/NFIT.memhp", +"tests/data/acpi/virt/SSDT.memhp", +"tests/data/acpi/virt/SLIT.memhp", +"tests/data/acpi/virt/SRAT.memhp", +"tests/data/acpi/virt/SPCR.memhp", +"tests/data/acpi/virt/MCFG.memhp", +"tests/data/acpi/virt/GTDT.memhp", +"tests/data/acpi/virt/APIC.memhp", +"tests/data/acpi/virt/FACP.memhp", +"tests/data/acpi/virt/DSDT.pxb", + +"tests/data/acpi/pc/SRAT.acpihmat", +"tests/data/acpi/pc/HPET", +"tests/data/acpi/pc/DSDT.hpbrroot", +"tests/data/acpi/pc/SRAT.numamem", +"tests/data/acpi/pc/DSDT.dimmpxm", +"tests/data/acpi/pc/DSDT.acpihmat", +"tests/data/acpi/pc/FACP", +"tests/data/acpi/pc/SRAT.cphp", +"tests/data/acpi/pc/DSDT.numamem", +"tests/data/acpi/pc/DSDT.bridge", +"tests/data/acpi/pc/HMAT.acpihmat", +"tests/data/acpi/pc/DSDT.cphp", +"tests/data/acpi/pc/APIC.dimmpxm", +"tests/data/acpi/pc/SRAT.memhp", +"tests/data/acpi/pc/SLIT.cphp", +"tests/data/acpi/pc/DSDT.hpbridge", +"tests/data/acpi/pc/NFIT.dimmpxm", +"tests/data/acpi/pc/APIC.cphp", +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/pc/SRAT.dimmpxm", +"tests/data/acpi/pc/APIC.acpihmat", +"tests/data/acpi/pc/DSDT.memhp", +"tests/data/acpi/pc/DSDT.ipmikcs", +"tests/data/acpi/pc/SLIT.memhp", +"tests/data/acpi/pc/WAET", +"tests/data/acpi/pc/DSDT", +"tests/data/acpi/pc/APIC", +"tests/data/acpi/pc/DSDT.roothp", + +"tests/data/acpi/q35/SRAT.acpihmat", +"tests/data/acpi/q35/HPET", +"tests/data/acpi/q35/SRAT.numamem", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/FACP", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/SRAT.cphp", +"tests/data/acpi/q35/DSDT.numamem", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/HMAT.acpihmat", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/APIC.dimmpxm", +"tests/data/acpi/q35/SRAT.memhp", +"tests/data/acpi/q35/SLIT.cphp", +"tests/data/acpi/q35/NFIT.dimmpxm", +"tests/data/acpi/q35/APIC.cphp", +"tests/data/acpi/q35/SSDT.dimmpxm", +"tests/data/acpi/q35/SRAT.dimmpxm", +"tests/data/acpi/q35/APIC.acpihmat", +"tests/data/acpi/q35/MCFG", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/SLIT.memhp", +"tests/data/acpi/q35/WAET", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.tis", +"tests/data/acpi/q35/SRAT.mmio64", +"tests/data/acpi/q35/TPM2.tis", +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/APIC", + +"tests/data/acpi/microvm/APIC.pcie", +"tests/data/acpi/microvm/DSDT.pcie", +"tests/data/acpi/microvm/DSDT.usb", +"tests/data/acpi/microvm/DSDT.rtc", +"tests/data/acpi/microvm/FACP", +"tests/data/acpi/microvm/APIC.ioapic2", +"tests/data/acpi/microvm/DSDT.ioapic2", +"tests/data/acpi/microvm/DSDT", +"tests/data/acpi/microvm/APIC", -- 2.26.2 From MAILER-DAEMON Mon Jan 18 19:32:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewg-00030w-Ak for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewe-0002yP-H3; Mon, 18 Jan 2021 19:32:28 -0500 Received: from mail.mutex.one ([62.77.152.124]:49442) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewc-0004A4-4N; Mon, 18 Jan 2021 19:32:28 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id 07241BF4250E; Tue, 19 Jan 2021 02:32:21 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wRlDmgeo-Wb7; Tue, 19 Jan 2021 02:32:19 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id B7438BF4227A; Tue, 19 Jan 2021 02:32:19 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1611016339; bh=WsbrKiWSijFZOi0txX9TwEsaVHqaQQOrmRtQjMMAhhE=; h=From:To:Cc:Subject:Date:From; b=DU2o1pnrvX1qL0jL9Z8KFZPESPLQUvn2RioiZuVVxd/q16gQNemnJWpEOzxv6c/Lh mAoPmetc8YSyWGkLOAy46I3TJBHFiTZc7BiR3Pa1NbUMp/C/YSCtxiyoFfbI9NxP82 1hBAQESbdz/h2227C23d0slXdaxs7ewugCo21RiQ= From: Marian Postevca To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Marcel Apfelbaum , Dongjiu Geng , Peter Maydell , Ben Warren , qemu-arm@nongnu.org, Paolo Bonzini , Xiang Zheng , Xiao Guangrong , Igor Mammedov , Sergio Lopez , "Michael S. Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 0/5] acpi: Permit OEM ID and OEM table ID fields to be changed Date: Tue, 19 Jan 2021 02:32:11 +0200 Message-Id: <20210119003216.17637-1-posteuca@mutex.one> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:28 -0000 Qemu's ACPI table generation sets the fields OEM ID and OEM table ID=0D to "BOCHS " and "BXPCxxxx" where "xxxx" is replaced by the ACPI=0D table name.=0D =0D Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID=0D and OEM table ID for the strings "BOCHS" and "BXPC" and if they are=0D found, the game crashes(this may be an intentional detection=0D mechanism to prevent playing the game in a virtualized environment).=0D =0D This patch allows you to override these default values.=0D =0D The feature can be used in this manner:=0D qemu -machine oem-id=3DABCDEF,oem-table-id=3DGHIJKLMN=0D =0D The oem-id string can be up to 6 bytes in size, and the=0D oem-table-id string can be up to 8 bytes in size. If the string are=0D smaller than their respective sizes they will be padded with space.=0D If either of these parameters is not set, the current default values=0D will be used for the one missing.=0D =0D Note that the the OEM Table ID field will not be extended with the=0D name of the table, but will use either the default name or the user=0D provided one.=0D =0D This does not affect the -acpitable option (for user-defined ACPI=0D tables), which has precedence over -machine option.=0D =0D v4:=0D - Added testcases for pc,q35,microvm,aarch64=0D - Switched to strpadcpy() instead of own function=0D - Don't touch unrelated fields in tables=0D - Instead of VIRT_MACHINE(obj)->bar use Foo *vm =3D VIRT_MACHINE(obj);=0D vm->bar=0D =0D v3:=0D - Do not append the sig part to OEM table id=0D - build_header() always sets the passed in values for oem_id=0D and oem_table_id=0D - Fixed a call to g_strdup() with a non-terminated string=0D - Use MachineState structures to hold the OEM fields=0D - Proper error handling in object setters=0D - Added description for object setters/getters=0D - Added support for pc,q35,microvm,aarch64=0D =0D v2:=0D - Use machine properties to set the OEM fields values=0D - Pass the desired values from acpi_build()=0D =0D Marian Postevca (5):=0D tests/acpi: allow updates for expected data files=0D acpi: Permit OEM ID and OEM table ID fields to be changed=0D tests/acpi: add OEM ID and OEM TABLE ID test=0D tests/acpi: update expected data files=0D tests/acpi: disallow updates for expected data files=0D =0D hw/acpi/hmat.h | 3 +-=0D hw/i386/acpi-common.h | 3 +-=0D include/hw/acpi/acpi-defs.h | 2 +-=0D include/hw/acpi/aml-build.h | 8 +-=0D include/hw/acpi/ghes.h | 3 +-=0D include/hw/acpi/pci.h | 3 +-=0D include/hw/acpi/vmgenid.h | 2 +-=0D include/hw/arm/virt.h | 2 +=0D include/hw/i386/microvm.h | 4 +=0D include/hw/i386/pc.h | 5 +-=0D include/hw/mem/nvdimm.h | 3 +-=0D hw/acpi/aml-build.c | 29 ++---=0D hw/acpi/ghes.c | 5 +-=0D hw/acpi/hmat.c | 5 +-=0D hw/acpi/nvdimm.c | 18 +--=0D hw/acpi/pci.c | 5 +-=0D hw/acpi/vmgenid.c | 4 +-=0D hw/arm/virt-acpi-build.c | 40 ++++---=0D hw/arm/virt.c | 63 ++++++++++=0D hw/i386/acpi-build.c | 86 +++++++++-----=0D hw/i386/acpi-common.c | 5 +-=0D hw/i386/acpi-microvm.c | 13 +-=0D hw/i386/microvm.c | 66 +++++++++++=0D hw/i386/pc.c | 64 ++++++++++=0D tests/qtest/bios-tables-test.c | 170 +++++++++++++++++++++++----=0D tests/data/acpi/microvm/APIC | Bin 70 -> 70 bytes=0D tests/data/acpi/microvm/APIC.ioapic2 | Bin 82 -> 82 bytes=0D tests/data/acpi/microvm/APIC.pcie | Bin 110 -> 110 bytes=0D tests/data/acpi/microvm/DSDT | Bin 365 -> 365 bytes=0D tests/data/acpi/microvm/DSDT.ioapic2 | Bin 365 -> 365 bytes=0D tests/data/acpi/microvm/DSDT.pcie | Bin 3031 -> 3031 bytes=0D tests/data/acpi/microvm/DSDT.rtc | Bin 404 -> 404 bytes=0D tests/data/acpi/microvm/DSDT.usb | Bin 414 -> 414 bytes=0D tests/data/acpi/microvm/FACP | Bin 268 -> 268 bytes=0D tests/data/acpi/pc/APIC | Bin 120 -> 120 bytes=0D tests/data/acpi/pc/APIC.acpihmat | Bin 128 -> 128 bytes=0D tests/data/acpi/pc/APIC.cphp | Bin 160 -> 160 bytes=0D tests/data/acpi/pc/APIC.dimmpxm | Bin 144 -> 144 bytes=0D tests/data/acpi/pc/DSDT | Bin 5065 -> 5065 bytes=0D tests/data/acpi/pc/DSDT.acpihmat | Bin 6390 -> 6390 bytes=0D tests/data/acpi/pc/DSDT.bridge | Bin 6924 -> 6924 bytes=0D tests/data/acpi/pc/DSDT.cphp | Bin 5529 -> 5529 bytes=0D tests/data/acpi/pc/DSDT.dimmpxm | Bin 6719 -> 6719 bytes=0D tests/data/acpi/pc/DSDT.hpbridge | Bin 5026 -> 5026 bytes=0D tests/data/acpi/pc/DSDT.hpbrroot | Bin 3084 -> 3084 bytes=0D tests/data/acpi/pc/DSDT.ipmikcs | Bin 5137 -> 5137 bytes=0D tests/data/acpi/pc/DSDT.memhp | Bin 6424 -> 6424 bytes=0D tests/data/acpi/pc/DSDT.numamem | Bin 5071 -> 5071 bytes=0D tests/data/acpi/pc/DSDT.roothp | Bin 5261 -> 5261 bytes=0D tests/data/acpi/pc/FACP | Bin 116 -> 116 bytes=0D tests/data/acpi/pc/HMAT.acpihmat | Bin 280 -> 280 bytes=0D tests/data/acpi/pc/HPET | Bin 56 -> 56 bytes=0D tests/data/acpi/pc/NFIT.dimmpxm | Bin 240 -> 240 bytes=0D tests/data/acpi/pc/SLIT.cphp | Bin 48 -> 48 bytes=0D tests/data/acpi/pc/SLIT.memhp | Bin 48 -> 48 bytes=0D tests/data/acpi/pc/SRAT.acpihmat | Bin 280 -> 280 bytes=0D tests/data/acpi/pc/SRAT.cphp | Bin 304 -> 304 bytes=0D tests/data/acpi/pc/SRAT.dimmpxm | Bin 392 -> 392 bytes=0D tests/data/acpi/pc/SRAT.memhp | Bin 264 -> 264 bytes=0D tests/data/acpi/pc/SRAT.numamem | Bin 224 -> 224 bytes=0D tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 734 bytes=0D tests/data/acpi/pc/WAET | Bin 40 -> 40 bytes=0D tests/data/acpi/q35/APIC | Bin 120 -> 120 bytes=0D tests/data/acpi/q35/APIC.acpihmat | Bin 128 -> 128 bytes=0D tests/data/acpi/q35/APIC.cphp | Bin 160 -> 160 bytes=0D tests/data/acpi/q35/APIC.dimmpxm | Bin 144 -> 144 bytes=0D tests/data/acpi/q35/DSDT | Bin 7801 -> 7801 bytes=0D tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9126 bytes=0D tests/data/acpi/q35/DSDT.bridge | Bin 7819 -> 7819 bytes=0D tests/data/acpi/q35/DSDT.cphp | Bin 8265 -> 8265 bytes=0D tests/data/acpi/q35/DSDT.dimmpxm | Bin 9455 -> 9455 bytes=0D tests/data/acpi/q35/DSDT.ipmibt | Bin 7876 -> 7876 bytes=0D tests/data/acpi/q35/DSDT.memhp | Bin 9160 -> 9160 bytes=0D tests/data/acpi/q35/DSDT.mmio64 | Bin 8932 -> 8932 bytes=0D tests/data/acpi/q35/DSDT.numamem | Bin 7807 -> 7807 bytes=0D tests/data/acpi/q35/DSDT.tis | Bin 8407 -> 8407 bytes=0D tests/data/acpi/q35/FACP | Bin 244 -> 244 bytes=0D tests/data/acpi/q35/HMAT.acpihmat | Bin 280 -> 280 bytes=0D tests/data/acpi/q35/HPET | Bin 56 -> 56 bytes=0D tests/data/acpi/q35/MCFG | Bin 60 -> 60 bytes=0D tests/data/acpi/q35/NFIT.dimmpxm | Bin 240 -> 240 bytes=0D tests/data/acpi/q35/SLIT.cphp | Bin 48 -> 48 bytes=0D tests/data/acpi/q35/SLIT.memhp | Bin 48 -> 48 bytes=0D tests/data/acpi/q35/SRAT.acpihmat | Bin 280 -> 280 bytes=0D tests/data/acpi/q35/SRAT.cphp | Bin 304 -> 304 bytes=0D tests/data/acpi/q35/SRAT.dimmpxm | Bin 392 -> 392 bytes=0D tests/data/acpi/q35/SRAT.memhp | Bin 264 -> 264 bytes=0D tests/data/acpi/q35/SRAT.mmio64 | Bin 224 -> 224 bytes=0D tests/data/acpi/q35/SRAT.numamem | Bin 224 -> 224 bytes=0D tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 734 bytes=0D tests/data/acpi/q35/TPM2.tis | Bin 76 -> 76 bytes=0D tests/data/acpi/q35/WAET | Bin 40 -> 40 bytes=0D tests/data/acpi/virt/APIC | Bin 168 -> 168 bytes=0D tests/data/acpi/virt/APIC.memhp | Bin 168 -> 168 bytes=0D tests/data/acpi/virt/APIC.numamem | Bin 168 -> 168 bytes=0D tests/data/acpi/virt/DSDT | Bin 5204 -> 5204 bytes=0D tests/data/acpi/virt/DSDT.memhp | Bin 6565 -> 6565 bytes=0D tests/data/acpi/virt/DSDT.numamem | Bin 5204 -> 5204 bytes=0D tests/data/acpi/virt/DSDT.pxb | Bin 7689 -> 7689 bytes=0D tests/data/acpi/virt/FACP | Bin 268 -> 268 bytes=0D tests/data/acpi/virt/FACP.memhp | Bin 268 -> 268 bytes=0D tests/data/acpi/virt/FACP.numamem | Bin 268 -> 268 bytes=0D tests/data/acpi/virt/GTDT | Bin 96 -> 96 bytes=0D tests/data/acpi/virt/GTDT.memhp | Bin 96 -> 96 bytes=0D tests/data/acpi/virt/GTDT.numamem | Bin 96 -> 96 bytes=0D tests/data/acpi/virt/MCFG | Bin 60 -> 60 bytes=0D tests/data/acpi/virt/MCFG.memhp | Bin 60 -> 60 bytes=0D tests/data/acpi/virt/MCFG.numamem | Bin 60 -> 60 bytes=0D tests/data/acpi/virt/NFIT.memhp | Bin 224 -> 224 bytes=0D tests/data/acpi/virt/SLIT.memhp | Bin 48 -> 48 bytes=0D tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes=0D tests/data/acpi/virt/SPCR.memhp | Bin 80 -> 80 bytes=0D tests/data/acpi/virt/SPCR.numamem | Bin 80 -> 80 bytes=0D tests/data/acpi/virt/SRAT.memhp | Bin 226 -> 226 bytes=0D tests/data/acpi/virt/SRAT.numamem | Bin 106 -> 106 bytes=0D tests/data/acpi/virt/SSDT.memhp | Bin 736 -> 736 bytes=0D 116 files changed, 495 insertions(+), 116 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Mon Jan 18 19:32:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewh-00033D-PX for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewg-00030a-3j; Mon, 18 Jan 2021 19:32:30 -0500 Received: from mail.mutex.one ([62.77.152.124]:49554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewd-0004Bn-OI; Mon, 18 Jan 2021 19:32:29 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id ED0E0BF4265B; Tue, 19 Jan 2021 02:32:25 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V8qHXvWHbvXq; Tue, 19 Jan 2021 02:32:25 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id D1476BF423B3; Tue, 19 Jan 2021 02:32:24 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1611016345; bh=y7JLysCHpkns1hYxYdlzzv9H47TyaL9EnTVW5Ece6RA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F48KP/GpE70+jhaT5F8fWBe7kBEe48c268fgVRdwqFnjR2AxwBJhpWegQHSyDKlxf bsSpqTbsYUpkbhl07q+I/11QCKMYUWJrv3vEZStehr3ALLp0AK2T3k4n2KlVVXFQpm DLjxRiLi0EWrRFAIxaOWlNdkAqAbe2/deZCukBkk= From: Marian Postevca To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Marcel Apfelbaum , Dongjiu Geng , Peter Maydell , Ben Warren , qemu-arm@nongnu.org, Paolo Bonzini , Xiang Zheng , Xiao Guangrong , Igor Mammedov , Sergio Lopez , "Michael S. Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 5/5] tests/acpi: disallow updates for expected data files Date: Tue, 19 Jan 2021 02:32:16 +0200 Message-Id: <20210119003216.17637-6-posteuca@mutex.one> In-Reply-To: <20210119003216.17637-1-posteuca@mutex.one> References: <20210119003216.17637-1-posteuca@mutex.one> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:30 -0000 Signed-off-by: Marian Postevca --- tests/qtest/bios-tables-test-allowed-diff.h | 94 --------------------- 1 file changed, 94 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index b20ae72949..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,95 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/APIC", -"tests/data/acpi/virt/FACP", -"tests/data/acpi/virt/GTDT", -"tests/data/acpi/virt/MCFG", -"tests/data/acpi/virt/SPCR", -"tests/data/acpi/virt/DSDT", -"tests/data/acpi/virt/APIC.numamem", -"tests/data/acpi/virt/FACP.numamem", -"tests/data/acpi/virt/GTDT.numamem", -"tests/data/acpi/virt/MCFG.numamem", -"tests/data/acpi/virt/SPCR.numamem", -"tests/data/acpi/virt/DSDT.numamem", -"tests/data/acpi/virt/SRAT.numamem", -"tests/data/acpi/virt/DSDT.memhp", -"tests/data/acpi/virt/NFIT.memhp", -"tests/data/acpi/virt/SSDT.memhp", -"tests/data/acpi/virt/SLIT.memhp", -"tests/data/acpi/virt/SRAT.memhp", -"tests/data/acpi/virt/SPCR.memhp", -"tests/data/acpi/virt/MCFG.memhp", -"tests/data/acpi/virt/GTDT.memhp", -"tests/data/acpi/virt/APIC.memhp", -"tests/data/acpi/virt/FACP.memhp", -"tests/data/acpi/virt/DSDT.pxb", - -"tests/data/acpi/pc/SRAT.acpihmat", -"tests/data/acpi/pc/HPET", -"tests/data/acpi/pc/DSDT.hpbrroot", -"tests/data/acpi/pc/SRAT.numamem", -"tests/data/acpi/pc/DSDT.dimmpxm", -"tests/data/acpi/pc/DSDT.acpihmat", -"tests/data/acpi/pc/FACP", -"tests/data/acpi/pc/SRAT.cphp", -"tests/data/acpi/pc/DSDT.numamem", -"tests/data/acpi/pc/DSDT.bridge", -"tests/data/acpi/pc/HMAT.acpihmat", -"tests/data/acpi/pc/DSDT.cphp", -"tests/data/acpi/pc/APIC.dimmpxm", -"tests/data/acpi/pc/SRAT.memhp", -"tests/data/acpi/pc/SLIT.cphp", -"tests/data/acpi/pc/DSDT.hpbridge", -"tests/data/acpi/pc/NFIT.dimmpxm", -"tests/data/acpi/pc/APIC.cphp", -"tests/data/acpi/pc/SSDT.dimmpxm", -"tests/data/acpi/pc/SRAT.dimmpxm", -"tests/data/acpi/pc/APIC.acpihmat", -"tests/data/acpi/pc/DSDT.memhp", -"tests/data/acpi/pc/DSDT.ipmikcs", -"tests/data/acpi/pc/SLIT.memhp", -"tests/data/acpi/pc/WAET", -"tests/data/acpi/pc/DSDT", -"tests/data/acpi/pc/APIC", -"tests/data/acpi/pc/DSDT.roothp", - -"tests/data/acpi/q35/SRAT.acpihmat", -"tests/data/acpi/q35/HPET", -"tests/data/acpi/q35/SRAT.numamem", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/FACP", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/SRAT.cphp", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/HMAT.acpihmat", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/APIC.dimmpxm", -"tests/data/acpi/q35/SRAT.memhp", -"tests/data/acpi/q35/SLIT.cphp", -"tests/data/acpi/q35/NFIT.dimmpxm", -"tests/data/acpi/q35/APIC.cphp", -"tests/data/acpi/q35/SSDT.dimmpxm", -"tests/data/acpi/q35/SRAT.dimmpxm", -"tests/data/acpi/q35/APIC.acpihmat", -"tests/data/acpi/q35/MCFG", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/SLIT.memhp", -"tests/data/acpi/q35/WAET", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.tis", -"tests/data/acpi/q35/SRAT.mmio64", -"tests/data/acpi/q35/TPM2.tis", -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/APIC", - -"tests/data/acpi/microvm/APIC.pcie", -"tests/data/acpi/microvm/DSDT.pcie", -"tests/data/acpi/microvm/DSDT.usb", -"tests/data/acpi/microvm/DSDT.rtc", -"tests/data/acpi/microvm/FACP", -"tests/data/acpi/microvm/APIC.ioapic2", -"tests/data/acpi/microvm/DSDT.ioapic2", -"tests/data/acpi/microvm/DSDT", -"tests/data/acpi/microvm/APIC", -- 2.26.2 From MAILER-DAEMON Mon Jan 18 19:32:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewj-00036S-9N for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewh-00032j-Gr; Mon, 18 Jan 2021 19:32:31 -0500 Received: from mail.mutex.one ([62.77.152.124]:49540) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewd-0004Bi-90; Mon, 18 Jan 2021 19:32:31 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id 904F5BF42662; Tue, 19 Jan 2021 02:32:25 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7WwwuLeKCCoL; Tue, 19 Jan 2021 02:32:24 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id E54DFBF4265B; Tue, 19 Jan 2021 02:32:23 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1611016344; bh=L1QsFEDGO6yRS90RZvrQGbtPPfuzcJubfv32vkyGbOg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YNR4jCtJF1TSHnlZBNZnIFz+V9eJbzs9a/UhYv1bA1he65ydK0AxhRyNf6D7+DoDi OSb9/wooG3KzdLZ4XTuB7TKhFGp9rmphU+bOQjD6mIzNB3hSBhYhpqCK7R31VSl08j 0M8qXO30N+WMWGtCyQM/aZVC2wcHYQj9awWsZizs= From: Marian Postevca To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Marcel Apfelbaum , Dongjiu Geng , Peter Maydell , Ben Warren , qemu-arm@nongnu.org, Paolo Bonzini , Xiang Zheng , Xiao Guangrong , Igor Mammedov , Sergio Lopez , "Michael S. Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 4/5] tests/acpi: update expected data files Date: Tue, 19 Jan 2021 02:32:15 +0200 Message-Id: <20210119003216.17637-5-posteuca@mutex.one> In-Reply-To: <20210119003216.17637-1-posteuca@mutex.one> References: <20210119003216.17637-1-posteuca@mutex.one> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:31 -0000 Signed-off-by: Marian Postevca --- tests/data/acpi/microvm/APIC | Bin 70 -> 70 bytes tests/data/acpi/microvm/APIC.ioapic2 | Bin 82 -> 82 bytes tests/data/acpi/microvm/APIC.pcie | Bin 110 -> 110 bytes tests/data/acpi/microvm/DSDT | Bin 365 -> 365 bytes tests/data/acpi/microvm/DSDT.ioapic2 | Bin 365 -> 365 bytes tests/data/acpi/microvm/DSDT.pcie | Bin 3031 -> 3031 bytes tests/data/acpi/microvm/DSDT.rtc | Bin 404 -> 404 bytes tests/data/acpi/microvm/DSDT.usb | Bin 414 -> 414 bytes tests/data/acpi/microvm/FACP | Bin 268 -> 268 bytes tests/data/acpi/pc/APIC | Bin 120 -> 120 bytes tests/data/acpi/pc/APIC.acpihmat | Bin 128 -> 128 bytes tests/data/acpi/pc/APIC.cphp | Bin 160 -> 160 bytes tests/data/acpi/pc/APIC.dimmpxm | Bin 144 -> 144 bytes tests/data/acpi/pc/DSDT | Bin 5065 -> 5065 bytes tests/data/acpi/pc/DSDT.acpihmat | Bin 6390 -> 6390 bytes tests/data/acpi/pc/DSDT.bridge | Bin 6924 -> 6924 bytes tests/data/acpi/pc/DSDT.cphp | Bin 5529 -> 5529 bytes tests/data/acpi/pc/DSDT.dimmpxm | Bin 6719 -> 6719 bytes tests/data/acpi/pc/DSDT.hpbridge | Bin 5026 -> 5026 bytes tests/data/acpi/pc/DSDT.hpbrroot | Bin 3084 -> 3084 bytes tests/data/acpi/pc/DSDT.ipmikcs | Bin 5137 -> 5137 bytes tests/data/acpi/pc/DSDT.memhp | Bin 6424 -> 6424 bytes tests/data/acpi/pc/DSDT.numamem | Bin 5071 -> 5071 bytes tests/data/acpi/pc/DSDT.roothp | Bin 5261 -> 5261 bytes tests/data/acpi/pc/FACP | Bin 116 -> 116 bytes tests/data/acpi/pc/HMAT.acpihmat | Bin 280 -> 280 bytes tests/data/acpi/pc/HPET | Bin 56 -> 56 bytes tests/data/acpi/pc/NFIT.dimmpxm | Bin 240 -> 240 bytes tests/data/acpi/pc/SLIT.cphp | Bin 48 -> 48 bytes tests/data/acpi/pc/SLIT.memhp | Bin 48 -> 48 bytes tests/data/acpi/pc/SRAT.acpihmat | Bin 280 -> 280 bytes tests/data/acpi/pc/SRAT.cphp | Bin 304 -> 304 bytes tests/data/acpi/pc/SRAT.dimmpxm | Bin 392 -> 392 bytes tests/data/acpi/pc/SRAT.memhp | Bin 264 -> 264 bytes tests/data/acpi/pc/SRAT.numamem | Bin 224 -> 224 bytes tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 734 bytes tests/data/acpi/pc/WAET | Bin 40 -> 40 bytes tests/data/acpi/q35/APIC | Bin 120 -> 120 bytes tests/data/acpi/q35/APIC.acpihmat | Bin 128 -> 128 bytes tests/data/acpi/q35/APIC.cphp | Bin 160 -> 160 bytes tests/data/acpi/q35/APIC.dimmpxm | Bin 144 -> 144 bytes tests/data/acpi/q35/DSDT | Bin 7801 -> 7801 bytes tests/data/acpi/q35/DSDT.acpihmat | Bin 9126 -> 9126 bytes tests/data/acpi/q35/DSDT.bridge | Bin 7819 -> 7819 bytes tests/data/acpi/q35/DSDT.cphp | Bin 8265 -> 8265 bytes tests/data/acpi/q35/DSDT.dimmpxm | Bin 9455 -> 9455 bytes tests/data/acpi/q35/DSDT.ipmibt | Bin 7876 -> 7876 bytes tests/data/acpi/q35/DSDT.memhp | Bin 9160 -> 9160 bytes tests/data/acpi/q35/DSDT.mmio64 | Bin 8932 -> 8932 bytes tests/data/acpi/q35/DSDT.numamem | Bin 7807 -> 7807 bytes tests/data/acpi/q35/DSDT.tis | Bin 8407 -> 8407 bytes tests/data/acpi/q35/FACP | Bin 244 -> 244 bytes tests/data/acpi/q35/HMAT.acpihmat | Bin 280 -> 280 bytes tests/data/acpi/q35/HPET | Bin 56 -> 56 bytes tests/data/acpi/q35/MCFG | Bin 60 -> 60 bytes tests/data/acpi/q35/NFIT.dimmpxm | Bin 240 -> 240 bytes tests/data/acpi/q35/SLIT.cphp | Bin 48 -> 48 bytes tests/data/acpi/q35/SLIT.memhp | Bin 48 -> 48 bytes tests/data/acpi/q35/SRAT.acpihmat | Bin 280 -> 280 bytes tests/data/acpi/q35/SRAT.cphp | Bin 304 -> 304 bytes tests/data/acpi/q35/SRAT.dimmpxm | Bin 392 -> 392 bytes tests/data/acpi/q35/SRAT.memhp | Bin 264 -> 264 bytes tests/data/acpi/q35/SRAT.mmio64 | Bin 224 -> 224 bytes tests/data/acpi/q35/SRAT.numamem | Bin 224 -> 224 bytes tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 734 bytes tests/data/acpi/q35/TPM2.tis | Bin 76 -> 76 bytes tests/data/acpi/q35/WAET | Bin 40 -> 40 bytes tests/data/acpi/virt/APIC | Bin 168 -> 168 bytes tests/data/acpi/virt/APIC.memhp | Bin 168 -> 168 bytes tests/data/acpi/virt/APIC.numamem | Bin 168 -> 168 bytes tests/data/acpi/virt/DSDT | Bin 5204 -> 5204 bytes tests/data/acpi/virt/DSDT.memhp | Bin 6565 -> 6565 bytes tests/data/acpi/virt/DSDT.numamem | Bin 5204 -> 5204 bytes tests/data/acpi/virt/DSDT.pxb | Bin 7689 -> 7689 bytes tests/data/acpi/virt/FACP | Bin 268 -> 268 bytes tests/data/acpi/virt/FACP.memhp | Bin 268 -> 268 bytes tests/data/acpi/virt/FACP.numamem | Bin 268 -> 268 bytes tests/data/acpi/virt/GTDT | Bin 96 -> 96 bytes tests/data/acpi/virt/GTDT.memhp | Bin 96 -> 96 bytes tests/data/acpi/virt/GTDT.numamem | Bin 96 -> 96 bytes tests/data/acpi/virt/MCFG | Bin 60 -> 60 bytes tests/data/acpi/virt/MCFG.memhp | Bin 60 -> 60 bytes tests/data/acpi/virt/MCFG.numamem | Bin 60 -> 60 bytes tests/data/acpi/virt/NFIT.memhp | Bin 224 -> 224 bytes tests/data/acpi/virt/SLIT.memhp | Bin 48 -> 48 bytes tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes tests/data/acpi/virt/SPCR.memhp | Bin 80 -> 80 bytes tests/data/acpi/virt/SPCR.numamem | Bin 80 -> 80 bytes tests/data/acpi/virt/SRAT.memhp | Bin 226 -> 226 bytes tests/data/acpi/virt/SRAT.numamem | Bin 106 -> 106 bytes tests/data/acpi/virt/SSDT.memhp | Bin 736 -> 736 bytes 91 files changed, 0 insertions(+), 0 deletions(-) diff --git a/tests/data/acpi/microvm/APIC b/tests/data/acpi/microvm/APIC index 7472c7e830b6c7139720e93dd544d4441556661d..68dbd44a7e35a356083f086df60f70e424c4249f 100644 GIT binary patch delta 30 jcmZ>BlW+|1barE4U|=k9@^|(KR&a_4a8>|BlW+|1barE4U|_uN||9mu-vq!LkQ$&EX0uXGJ2xSBSqcI4) delta 33 mcmaFM^p;7&CDNNl4-4I==G1qf~c diff --git a/tests/data/acpi/microvm/DSDT.usb b/tests/data/acpi/microvm/DSDT.usb index 14423381ea235ed42f6f0f7d98e793c271a4e7c1..d63fd84620a2689120b32262f964e6a098d71632 100644 GIT binary patch delta 33 ncmbQoJdatzCDNNl4-8zTUcZwS}` diff --git a/tests/data/acpi/microvm/FACP b/tests/data/acpi/microvm/FACP index 0ba5795d622349e1521138e4123544637b4ab9af..f12cef5cb6461118d4f6c847bad5c173613443c6 100644 GIT binary patch delta 32 lcmeBS>S2;_b94^iVPs%nm2mQR_6SyRiU@F40D_4UUjS?i2T}k4 delta 32 lcmeBS>S2;_b94^iVPs%nt#k5s_6SyRiU@E9iA|LF0swY)2vPt5 diff --git a/tests/data/acpi/pc/APIC b/tests/data/acpi/pc/APIC index 84509e0ae4cabeb5ead3e42a4edfa50abddbc17d..208331db53b7dd5c6205cce0e95427636b86dd64 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mcmZ3%xPno_F~HM#1p@;EbAXe-vq!LkQ$&EX0uW4;m;eBTNC)@; delta 32 lcmZ3%xPno_F~HM#1p@;E^JXW1XOCb7r-%S&kk~|t2>_0s2>1X1 diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index ea8a0869af1637ab75fe335e100256a2acf85e16..134d8ae5b602e0aaade6756b99c9abca45279284 100644 GIT binary patch delta 33 ncmcbjaYaMICDNjnwtos delta 33 mcmZ2#ywq62CD9mn>33dtLlw)9Ey6@!g>=CTs6cOO800bK)KFR_Blt>8e delta 33 mcmeCQ>9mn>33dtLlw)9EGH~*D_6SyRiU@E9iEWhlC<_3KtO)G@ diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP index 27de99f51bfe846b1f8796ace49d83f5b33a1aed..1f764220f8533c427168e80ccf298604826a00b4 100644 GIT binary patch literal 268 ycmZ>BbPnKQWME(ob@F%i2v%^42yj*a0-z8Bhz+8t3j|P&V`iYf6{t24%>w}Cy9NOO literal 268 ycmZ>BbPnKQWME+3?d0$55v<@85#a0w6axw|fY>0KxBbPnKQWME(ob@F%i2v%^42yj*a0-z8Bhz+8t3j|P&V`iYf6{t24%>w}Cy9NOO literal 268 ycmZ>BbPnKQWME+3?d0$55v<@85#a0w6axw|fY>0KxBbPnKQWME(ob@F%i2v%^42yj*a0-z8Bhz+8t3j|P&V`iYf6{t24%>w}Cy9NOO literal 268 ycmZ>BbPnKQWME+3?d0$55v<@85#a0w6axw|fY>0Kx|||U3LF3c diff --git a/tests/data/acpi/virt/SLIT.memhp b/tests/data/acpi/virt/SLIT.memhp index 74ec3b4b461ffecca36d8537975c202a5f011185..67f00813af7b2356fe74eed943ab8dcf2291578b 100644 GIT binary patch literal 48 scmWIc@eDCwU|?W;;pFe^5v<@85#X!<1dKp25F11@0Wk=0iHdRo0OYg>0RR91 literal 48 scmWIc@eDCwU|?X>aq@Te2v%^42yhMtiZKGkKx`1r1jHb~B`V4V0NaKK0RR91 diff --git a/tests/data/acpi/virt/SPCR b/tests/data/acpi/virt/SPCR index 377271a0e7817cc21a28c02123a89facad63604f..24e0a579e7d73f432a614380e29aa95113344186 100644 GIT binary patch delta 30 jcmWFtkO&TN4hmpkU|>4!4!4!NNl3SDFC003Bv#Y diff --git a/tests/data/acpi/virt/SRAT.numamem b/tests/data/acpi/virt/SRAT.numamem index 9526e5a28eb2a315d3bc9d9b11852319d5a8898e..d45f40338ce4c06ba68163214f149b2414c5f18b 100644 GIT binary patch delta 30 jcmd1Gk_ZlR49Q|(U|>#l@^|(KR&a_4a8>|Avq!LkUzm%huP+0`Mu`(l0HqiSFaQ7m -- 2.26.2 From MAILER-DAEMON Mon Jan 18 19:32:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewl-0003Am-7U for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewi-00035F-P3; Mon, 18 Jan 2021 19:32:32 -0500 Received: from mail.mutex.one ([62.77.152.124]:49498) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewc-0004B7-PG; Mon, 18 Jan 2021 19:32:32 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id E27A3BF42635; Tue, 19 Jan 2021 02:32:23 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WsHNfswm9DRi; Tue, 19 Jan 2021 02:32:22 +0200 (EET) Received: [127.0.0.1] (localhost [127.0.0.1])nknown [109.103.89.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mutex.one (Postfix) with ESMTPSA id D31DDBF423B3; Tue, 19 Jan 2021 02:32:21 +0200 (EET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1611016342; bh=d17LbBQPN3H6u/W6FzuKFGUsg1FItpF8RPdcRQCYX6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G6EcurBnUjd+mZS0L8LsqpfJ6wgm4CSzXKHwTc7gsyeyvN1rQz8zJNLye3gH5ntN8 jFeZH8i/sxfMGV6hFDHV5CQ6OaGXCJ+B5WJdFurz7+xribK8NGEXEoYTuas/y/KJE6 Db2lzPKRlVrCrbW4r3QI2SJsTJaHhpy9NfU2mkrk= From: Marian Postevca To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Richard Henderson , Marcel Apfelbaum , Dongjiu Geng , Peter Maydell , Ben Warren , qemu-arm@nongnu.org, Paolo Bonzini , Xiang Zheng , Xiao Guangrong , Igor Mammedov , Sergio Lopez , "Michael S. Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 2/5] acpi: Permit OEM ID and OEM table ID fields to be changed Date: Tue, 19 Jan 2021 02:32:13 +0200 Message-Id: <20210119003216.17637-3-posteuca@mutex.one> In-Reply-To: <20210119003216.17637-1-posteuca@mutex.one> References: <20210119003216.17637-1-posteuca@mutex.one> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:33 -0000 Qemu's ACPI table generation sets the fields OEM ID and OEM table ID to "BOCHS " and "BXPCxxxx" where "xxxx" is replaced by the ACPI table name. Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID and OEM table ID for the strings "BOCHS" and "BXPC" and if they are found, the game crashes(this may be an intentional detection mechanism to prevent playing the game in a virtualized environment). This patch allows you to override these default values. The feature can be used in this manner: qemu -machine oem-id=ABCDEF,oem-table-id=GHIJKLMN The oem-id string can be up to 6 bytes in size, and the oem-table-id string can be up to 8 bytes in size. If the string are smaller than their respective sizes they will be padded with space. If either of these parameters is not set, the current default values will be used for the one missing. Note that the the OEM Table ID field will not be extended with the name of the table, but will use either the default name or the user provided one. This does not affect the -acpitable option (for user-defined ACPI tables), which has precedence over -machine option. Signed-off-by: Marian Postevca --- hw/acpi/hmat.h | 3 +- hw/i386/acpi-common.h | 3 +- include/hw/acpi/acpi-defs.h | 2 +- include/hw/acpi/aml-build.h | 8 ++-- include/hw/acpi/ghes.h | 3 +- include/hw/acpi/pci.h | 3 +- include/hw/acpi/vmgenid.h | 2 +- include/hw/arm/virt.h | 2 + include/hw/i386/microvm.h | 4 ++ include/hw/i386/pc.h | 5 ++- include/hw/mem/nvdimm.h | 3 +- hw/acpi/aml-build.c | 29 ++++++------- hw/acpi/ghes.c | 5 ++- hw/acpi/hmat.c | 5 ++- hw/acpi/nvdimm.c | 18 +++++--- hw/acpi/pci.c | 5 ++- hw/acpi/vmgenid.c | 4 +- hw/arm/virt-acpi-build.c | 40 +++++++++++------ hw/arm/virt.c | 63 +++++++++++++++++++++++++++ hw/i386/acpi-build.c | 86 +++++++++++++++++++++++++------------ hw/i386/acpi-common.c | 5 ++- hw/i386/acpi-microvm.c | 13 +++--- hw/i386/microvm.c | 66 ++++++++++++++++++++++++++++ hw/i386/pc.c | 64 +++++++++++++++++++++++++++ 24 files changed, 349 insertions(+), 92 deletions(-) diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h index e9031cac01..b57f0e7e80 100644 --- a/hw/acpi/hmat.h +++ b/hw/acpi/hmat.h @@ -37,6 +37,7 @@ */ #define HMAT_PROXIMITY_INITIATOR_VALID 0x1 -void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state); +void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state, + const char *oem_id, const char *oem_table_id); #endif diff --git a/hw/i386/acpi-common.h b/hw/i386/acpi-common.h index c30e461f18..b12cd73ea5 100644 --- a/hw/i386/acpi-common.h +++ b/hw/i386/acpi-common.h @@ -9,6 +9,7 @@ #define ACPI_BUILD_IOAPIC_ID 0x0 void acpi_build_madt(GArray *table_data, BIOSLinker *linker, - X86MachineState *x86ms, AcpiDeviceIf *adev); + X86MachineState *x86ms, AcpiDeviceIf *adev, + const char *oem_id, const char *oem_table_id); #endif diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 38a42f409a..cf9f44299c 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -41,7 +41,7 @@ enum { }; typedef struct AcpiRsdpData { - uint8_t oem_id[6] QEMU_NONSTRING; /* OEM identification */ + char *oem_id; /* OEM identification */ uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ unsigned *rsdt_tbl_offset; diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 54a5aec4d7..380d3e3924 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -8,7 +8,7 @@ #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 #define ACPI_BUILD_APPNAME6 "BOCHS " -#define ACPI_BUILD_APPNAME4 "BXPC" +#define ACPI_BUILD_APPNAME8 "BXPC " #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables" #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp" @@ -459,10 +459,12 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); -void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms); +void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id); void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); -void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog); +void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, + const char *oem_id, const char *oem_table_id); #endif diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 4ad025e09a..2ae8bc1ded 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -67,7 +67,8 @@ typedef struct AcpiGhesState { } AcpiGhesState; void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker); -void acpi_build_hest(GArray *table_data, BIOSLinker *linker); +void acpi_build_hest(GArray *table_data, BIOSLinker *linker, + const char *oem_id, const char *oem_table_id); void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr); diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h index bf2a3ed0ba..e514f179d8 100644 --- a/include/hw/acpi/pci.h +++ b/include/hw/acpi/pci.h @@ -33,5 +33,6 @@ typedef struct AcpiMcfgInfo { uint32_t size; } AcpiMcfgInfo; -void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info); +void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info, + const char *oem_id, const char *oem_table_id); #endif diff --git a/include/hw/acpi/vmgenid.h b/include/hw/acpi/vmgenid.h index cb4ad37fc5..dc8bb3433e 100644 --- a/include/hw/acpi/vmgenid.h +++ b/include/hw/acpi/vmgenid.h @@ -31,7 +31,7 @@ static inline Object *find_vmgenid_dev(void) } void vmgenid_build_acpi(VmGenIdState *vms, GArray *table_data, GArray *guid, - BIOSLinker *linker); + BIOSLinker *linker, const char *oem_id); void vmgenid_add_fw_cfg(VmGenIdState *vms, FWCfgState *s, GArray *guid); #endif diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e4a2d21642..ac34edad53 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -163,6 +163,8 @@ struct VirtMachineState { DeviceState *acpi_dev; Notifier powerdown_notifier; PCIBus *bus; + char *oem_id; + char *oem_table_id; }; #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index f25f837441..372b05774e 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -76,6 +76,8 @@ #define MICROVM_MACHINE_ISA_SERIAL "isa-serial" #define MICROVM_MACHINE_OPTION_ROMS "x-option-roms" #define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline" +#define MICROVM_MACHINE_OEM_ID "oem-id" +#define MICROVM_MACHINE_OEM_TABLE_ID "oem-table-id" struct MicrovmMachineClass { X86MachineClass parent; @@ -104,6 +106,8 @@ struct MicrovmMachineState { Notifier machine_done; Notifier powerdown_req; struct GPEXConfig gpex; + char *oem_id; + char *oem_table_id; }; #define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2aa8797c6e..5f93540a43 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -45,6 +45,8 @@ typedef struct PCMachineState { bool pit_enabled; bool hpet_enabled; uint64_t max_fw_size; + char *oem_id; + char *oem_table_id; /* NUMA information: */ uint64_t numa_nodes; @@ -62,7 +64,8 @@ typedef struct PCMachineState { #define PC_MACHINE_SATA "sata" #define PC_MACHINE_PIT "pit" #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" - +#define PC_MACHINE_OEM_ID "oem-id" +#define PC_MACHINE_OEM_TABLE_ID "oem-table-id" /** * PCMachineClass: * diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index c699842dd0..bcf62f825c 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -154,7 +154,8 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, void nvdimm_build_srat(GArray *table_data); void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, NVDIMMState *state, - uint32_t ram_slots); + uint32_t ram_slots, const char *oem_id, + const char *oem_table_id); void nvdimm_plug(NVDIMMState *state); void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev); #endif diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 7b6ebb0cc8..a2cd7a5830 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -30,6 +30,7 @@ #include "hw/pci/pci_host.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" +#include "qemu/cutils.h" static GArray *build_alloc_array(void) { @@ -1674,21 +1675,12 @@ build_header(BIOSLinker *linker, GArray *table_data, h->length = cpu_to_le32(len); h->revision = rev; - if (oem_id) { - strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id); - } else { - memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6); - } - - if (oem_table_id) { - strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id)); - } else { - memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4); - memcpy(h->oem_table_id + 4, sig, 4); - } + strpadcpy((char *)h->oem_id, sizeof h->oem_id, oem_id, ' '); + strpadcpy((char *)h->oem_table_id, sizeof h->oem_table_id, + oem_table_id, ' '); h->oem_revision = cpu_to_le32(1); - memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4); + memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME8, 4); h->asl_compiler_revision = cpu_to_le32(1); /* Checksum to be filled in by Guest linker */ bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE, @@ -1871,7 +1863,8 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, * ACPI spec 5.2.17 System Locality Distance Information Table * (Revision 2.0 or later) */ -void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms) +void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id) { int slit_start, i, j; slit_start = table_data->len; @@ -1892,7 +1885,7 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms) build_header(linker, table_data, (void *)(table_data->data + slit_start), "SLIT", - table_data->len - slit_start, 1, NULL, NULL); + table_data->len - slit_start, 1, oem_id, oem_table_id); } /* build rev1/rev3/rev5.1 FADT */ @@ -2024,7 +2017,8 @@ build_hdr: * table 7: TCG Hardware Interface Description Table Format for TPM 2.0 * of TCG ACPI Specification, Family “1.2” and “2.0”, Version 1.2, Rev 8 */ -void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) +void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, + const char *oem_id, const char *oem_table_id) { uint8_t start_method_params[12] = {}; unsigned log_addr_offset, tpm2_start; @@ -2073,7 +2067,8 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0); build_header(linker, table_data, - tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL); + tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, oem_id, + oem_table_id); } Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index f0ee9f51ca..a4dac6bf15 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -359,7 +359,8 @@ static void build_ghes_v2(GArray *table_data, int source_id, BIOSLinker *linker) } /* Build Hardware Error Source Table */ -void acpi_build_hest(GArray *table_data, BIOSLinker *linker) +void acpi_build_hest(GArray *table_data, BIOSLinker *linker, + const char *oem_id, const char *oem_table_id) { uint64_t hest_start = table_data->len; @@ -372,7 +373,7 @@ void acpi_build_hest(GArray *table_data, BIOSLinker *linker) build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker); build_header(linker, table_data, (void *)(table_data->data + hest_start), - "HEST", table_data->len - hest_start, 1, NULL, NULL); + "HEST", table_data->len - hest_start, 1, oem_id, oem_table_id); } void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s, diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c index 37806f7a06..edb3fd91b2 100644 --- a/hw/acpi/hmat.c +++ b/hw/acpi/hmat.c @@ -253,7 +253,8 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state) } } -void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state) +void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state, + const char *oem_id, const char *oem_table_id) { int hmat_start = table_data->len; @@ -264,5 +265,5 @@ void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state) build_header(linker, table_data, (void *)(table_data->data + hmat_start), - "HMAT", table_data->len - hmat_start, 2, NULL, NULL); + "HMAT", table_data->len - hmat_start, 2, oem_id, oem_table_id); } diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index aa95b0cbaf..e3d5fe1939 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -402,7 +402,8 @@ void nvdimm_plug(NVDIMMState *state) } static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets, - GArray *table_data, BIOSLinker *linker) + GArray *table_data, BIOSLinker *linker, + const char *oem_id, const char *oem_table_id) { NvdimmFitBuffer *fit_buf = &state->fit_buf; unsigned int header; @@ -417,7 +418,8 @@ static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets, build_header(linker, table_data, (void *)(table_data->data + header), "NFIT", - sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, NULL, NULL); + sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, oem_id, + oem_table_id); } #define NVDIMM_DSM_MEMORY_SIZE 4096 @@ -1278,7 +1280,7 @@ static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, NVDIMMState *nvdimm_state, - uint32_t ram_slots) + uint32_t ram_slots, const char *oem_id) { Aml *ssdt, *sb_scope, *dev; int mem_addr_offset, nvdimm_ssdt; @@ -1331,7 +1333,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, NVDIMM_DSM_MEM_FILE, 0); build_header(linker, table_data, (void *)(table_data->data + nvdimm_ssdt), - "SSDT", table_data->len - nvdimm_ssdt, 1, NULL, "NVDIMM"); + "SSDT", table_data->len - nvdimm_ssdt, 1, oem_id, "NVDIMM"); free_aml_allocator(); } @@ -1359,7 +1361,8 @@ void nvdimm_build_srat(GArray *table_data) void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, NVDIMMState *state, - uint32_t ram_slots) + uint32_t ram_slots, const char *oem_id, + const char *oem_table_id) { GSList *device_list; @@ -1369,7 +1372,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, } nvdimm_build_ssdt(table_offsets, table_data, linker, state, - ram_slots); + ram_slots, oem_id); device_list = nvdimm_get_device_list(); /* no NVDIMM device is plugged. */ @@ -1377,6 +1380,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, return; } - nvdimm_build_nfit(state, table_offsets, table_data, linker); + nvdimm_build_nfit(state, table_offsets, table_data, linker, + oem_id, oem_table_id); g_slist_free(device_list); } diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c index 9510597a19..ec455c3b25 100644 --- a/hw/acpi/pci.c +++ b/hw/acpi/pci.c @@ -28,7 +28,8 @@ #include "hw/acpi/pci.h" #include "hw/pci/pcie_host.h" -void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) +void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info, + const char *oem_id, const char *oem_table_id) { int mcfg_start = table_data->len; @@ -56,6 +57,6 @@ void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info) build_append_int_noprefix(table_data, 0, 4); build_header(linker, table_data, (void *)(table_data->data + mcfg_start), - "MCFG", table_data->len - mcfg_start, 1, NULL, NULL); + "MCFG", table_data->len - mcfg_start, 1, oem_id, oem_table_id); } diff --git a/hw/acpi/vmgenid.c b/hw/acpi/vmgenid.c index 6c92fdae49..4f41a13ea0 100644 --- a/hw/acpi/vmgenid.c +++ b/hw/acpi/vmgenid.c @@ -24,7 +24,7 @@ #include "sysemu/reset.h" void vmgenid_build_acpi(VmGenIdState *vms, GArray *table_data, GArray *guid, - BIOSLinker *linker) + BIOSLinker *linker, const char *oem_id) { Aml *ssdt, *dev, *scope, *method, *addr, *if_ctx; uint32_t vgia_offset; @@ -118,7 +118,7 @@ void vmgenid_build_acpi(VmGenIdState *vms, GArray *table_data, GArray *guid, build_header(linker, table_data, (void *)(table_data->data + table_data->len - ssdt->buf->len), - "SSDT", ssdt->buf->len, 1, NULL, "VMGENID"); + "SSDT", ssdt->buf->len, 1, oem_id, "VMGENID"); free_aml_allocator(); } diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9d9ee24053..f9c9df916c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -341,7 +341,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) iort->length = cpu_to_le32(iort_length); build_header(linker, table_data, (void *)(table_data->data + iort_start), - "IORT", table_data->len - iort_start, 0, NULL, NULL); + "IORT", table_data->len - iort_start, 0, vms->oem_id, + vms->oem_table_id); } static void @@ -375,7 +376,8 @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ build_header(linker, table_data, (void *)(table_data->data + spcr_start), - "SPCR", table_data->len - spcr_start, 2, NULL, NULL); + "SPCR", table_data->len - spcr_start, 2, vms->oem_id, + vms->oem_table_id); } static void @@ -427,7 +429,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) } build_header(linker, table_data, (void *)(table_data->data + srat_start), - "SRAT", table_data->len - srat_start, 3, NULL, NULL); + "SRAT", table_data->len - srat_start, 3, vms->oem_id, + vms->oem_table_id); } /* GTDT */ @@ -462,7 +465,8 @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_header(linker, table_data, (void *)(table_data->data + gtdt_start), "GTDT", - table_data->len - gtdt_start, 2, NULL, NULL); + table_data->len - gtdt_start, 2, vms->oem_id, + vms->oem_table_id); } /* MADT */ @@ -551,7 +555,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_header(linker, table_data, (void *)(table_data->data + madt_start), "APIC", - table_data->len - madt_start, 3, NULL, NULL); + table_data->len - madt_start, 3, vms->oem_id, + vms->oem_table_id); } /* FADT */ @@ -581,7 +586,7 @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, g_assert_not_reached(); } - build_fadt(table_data, linker, &fadt, NULL, NULL); + build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } /* DSDT */ @@ -645,7 +650,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - dsdt->buf->len), - "DSDT", dsdt->buf->len, 2, NULL, NULL); + "DSDT", dsdt->buf->len, 2, vms->oem_id, + vms->oem_table_id); free_aml_allocator(); } @@ -704,7 +710,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, }; - build_mcfg(tables_blob, tables->linker, &mcfg); + build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, + vms->oem_table_id); } acpi_add_table(table_offsets, tables_blob); @@ -713,7 +720,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (vms->ras) { build_ghes_error_table(tables->hardware_errors, tables->linker); acpi_add_table(table_offsets, tables_blob); - acpi_build_hest(tables_blob, tables->linker); + acpi_build_hest(tables_blob, tables->linker, vms->oem_id, + vms->oem_table_id); } if (ms->numa_state->num_nodes > 0) { @@ -721,13 +729,15 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) build_srat(tables_blob, tables->linker, vms); if (ms->numa_state->have_numa_distance) { acpi_add_table(table_offsets, tables_blob); - build_slit(tables_blob, tables->linker, ms); + build_slit(tables_blob, tables->linker, ms, vms->oem_id, + vms->oem_table_id); } } if (ms->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, - ms->nvdimms_state, ms->ram_slots); + ms->nvdimms_state, ms->ram_slots, vms->oem_id, + vms->oem_table_id); } if (its_class_name() && !vmc->no_its) { @@ -737,18 +747,20 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { acpi_add_table(table_offsets, tables_blob); - build_tpm2(tables_blob, tables->linker, tables->tcpalog); + build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, + vms->oem_table_id); } /* XSDT is pointed to by RSDP */ xsdt = tables_blob->len; - build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); + build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, + vms->oem_table_id); /* RSDP is in FSEG memory, so allocate it separately */ { AcpiRsdpData rsdp_data = { .revision = 2, - .oem_id = ACPI_BUILD_APPNAME6, + .oem_id = vms->oem_id, .xsdt_tbl_offset = &xsdt, .rsdt_tbl_offset = NULL, }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 86070dfd98..ecb0e14816 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2089,6 +2089,49 @@ static void virt_set_its(Object *obj, bool value, Error **errp) vms->its = value; } +static char *virt_get_oem_id(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return g_strdup(vms->oem_id); +} + +static void virt_set_oem_id(Object *obj, const char *value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + size_t len = strlen(value); + + if (len > 6) { + error_setg(errp, + "User specified oem-id value is bigger than 6 bytes in size"); + return; + } + + strncpy(vms->oem_id, value, len + 1); +} + +static char *virt_get_oem_table_id(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return g_strdup(vms->oem_table_id); +} + +static void virt_set_oem_table_id(Object *obj, const char *value, + Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + size_t len = strlen(value); + + if (len > 8) { + error_setg(errp, + "User specified oem-table-id value is bigger than 8 bytes in size"); + return; + } + strncpy(vms->oem_table_id, value, len + 1); +} + + bool virt_is_acpi_enabled(VirtMachineState *vms) { if (vms->acpi == ON_OFF_AUTO_OFF) { @@ -2538,6 +2581,23 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) "Set on/off to enable/disable " "ITS instantiation"); + object_class_property_add_str(oc, "oem-id", + virt_get_oem_id, + virt_set_oem_id); + object_class_property_set_description(oc, "oem-id", + "Override the default value of field OEMID " + "in ACPI table header." + "The string may be up to 6 bytes in size"); + + + object_class_property_add_str(oc, "oem-table-id", + virt_get_oem_table_id, + virt_set_oem_table_id); + object_class_property_set_description(oc, "oem-table-id", + "Override the default value of field OEM Table ID " + "in ACPI table header." + "The string may be up to 8 bytes in size"); + } static void virt_instance_init(Object *obj) @@ -2579,6 +2639,9 @@ static void virt_instance_init(Object *obj) vms->irqmap = a15irqmap; virt_flash_create(vms); + + vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); + vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); } static const TypeInfo virt_machine_info = { diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f56d699c7f..b9190b924a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1637,12 +1637,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - dsdt->buf->len), - "DSDT", dsdt->buf->len, 1, NULL, NULL); + "DSDT", dsdt->buf->len, 1, pcms->oem_id, pcms->oem_table_id); free_aml_allocator(); } static void -build_hpet(GArray *table_data, BIOSLinker *linker) +build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id, + const char *oem_table_id) { Acpi20Hpet *hpet; @@ -1653,11 +1654,12 @@ build_hpet(GArray *table_data, BIOSLinker *linker) hpet->timer_block_id = cpu_to_le32(0x8086a201); hpet->addr.address = cpu_to_le64(HPET_BASE); build_header(linker, table_data, - (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); + (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_table_id); } static void -build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) +build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, + const char *oem_id, const char *oem_table_id) { Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); unsigned log_addr_size = sizeof(tcpa->log_area_start_address); @@ -1677,7 +1679,7 @@ build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) ACPI_BUILD_TPMLOG_FILE, 0); build_header(linker, table_data, - (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); + (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id); } #define HOLE_640K_START (640 * KiB) @@ -1812,7 +1814,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_header(linker, table_data, (void *)(table_data->data + srat_start), "SRAT", - table_data->len - srat_start, 1, NULL, NULL); + table_data->len - srat_start, 1, pcms->oem_id, + pcms->oem_table_id); } /* @@ -1820,7 +1823,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) * (version Oct. 2014 or later) */ static void -build_dmar_q35(GArray *table_data, BIOSLinker *linker) +build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id, + const char *oem_table_id) { int dmar_start = table_data->len; @@ -1870,7 +1874,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) } build_header(linker, table_data, (void *)(table_data->data + dmar_start), - "DMAR", table_data->len - dmar_start, 1, NULL, NULL); + "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id); } /* @@ -1881,7 +1885,8 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) * Helpful to speedup Windows guests and ignored by others. */ static void -build_waet(GArray *table_data, BIOSLinker *linker) +build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id, + const char *oem_table_id) { int waet_start = table_data->len; @@ -1897,7 +1902,7 @@ build_waet(GArray *table_data, BIOSLinker *linker) build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); build_header(linker, table_data, (void *)(table_data->data + waet_start), - "WAET", table_data->len - waet_start, 1, NULL, NULL); + "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id); } /* @@ -1999,7 +2004,8 @@ ivrs_host_bridges(Object *obj, void *opaque) } static void -build_amd_iommu(GArray *table_data, BIOSLinker *linker) +build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, + const char *oem_table_id) { int ivhd_table_len = 24; int iommu_start = table_data->len; @@ -2094,7 +2100,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker) } build_header(linker, table_data, (void *)(table_data->data + iommu_start), - "IVRS", table_data->len - iommu_start, 1, NULL, NULL); + "IVRS", table_data->len - iommu_start, 1, oem_id, + oem_table_id); } typedef @@ -2150,12 +2157,26 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) GArray *tables_blob = tables->table_data; AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; Object *vmgenid_dev; + char *oem_id; + char *oem_table_id; acpi_get_pm_info(machine, &pm); acpi_get_misc_info(&misc); acpi_get_pci_holes(&pci_hole, &pci_hole64); acpi_get_slic_oem(&slic_oem); + if (slic_oem.id) { + oem_id = slic_oem.id; + } else { + oem_id = pcms->oem_id; + } + + if (slic_oem.table_id) { + oem_table_id = slic_oem.table_id; + } else { + oem_table_id = pcms->oem_table_id; + } + table_offsets = g_array_new(false, true /* clear */, sizeof(uint32_t)); ACPI_BUILD_DPRINTF("init ACPI tables\n"); @@ -2189,32 +2210,35 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) pm.fadt.facs_tbl_offset = &facs; pm.fadt.dsdt_tbl_offset = &dsdt; pm.fadt.xdsdt_tbl_offset = &dsdt; - build_fadt(tables_blob, tables->linker, &pm.fadt, - slic_oem.id, slic_oem.table_id); + build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); aml_len += tables_blob->len - fadt; acpi_add_table(table_offsets, tables_blob); acpi_build_madt(tables_blob, tables->linker, x86ms, - ACPI_DEVICE_IF(x86ms->acpi_dev)); + ACPI_DEVICE_IF(x86ms->acpi_dev), pcms->oem_id, + pcms->oem_table_id); vmgenid_dev = find_vmgenid_dev(); if (vmgenid_dev) { acpi_add_table(table_offsets, tables_blob); vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, - tables->vmgenid, tables->linker); + tables->vmgenid, tables->linker, pcms->oem_id); } if (misc.has_hpet) { acpi_add_table(table_offsets, tables_blob); - build_hpet(tables_blob, tables->linker); + build_hpet(tables_blob, tables->linker, pcms->oem_id, + pcms->oem_table_id); } if (misc.tpm_version != TPM_VERSION_UNSPEC) { if (misc.tpm_version == TPM_VERSION_1_2) { acpi_add_table(table_offsets, tables_blob); - build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); + build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, + pcms->oem_id, pcms->oem_table_id); } else { /* TPM_VERSION_2_0 */ acpi_add_table(table_offsets, tables_blob); - build_tpm2(tables_blob, tables->linker, tables->tcpalog); + build_tpm2(tables_blob, tables->linker, tables->tcpalog, + pcms->oem_id, pcms->oem_table_id); } } if (pcms->numa_nodes) { @@ -2222,34 +2246,40 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) build_srat(tables_blob, tables->linker, machine); if (machine->numa_state->have_numa_distance) { acpi_add_table(table_offsets, tables_blob); - build_slit(tables_blob, tables->linker, machine); + build_slit(tables_blob, tables->linker, machine, pcms->oem_id, + pcms->oem_table_id); } if (machine->numa_state->hmat_enabled) { acpi_add_table(table_offsets, tables_blob); - build_hmat(tables_blob, tables->linker, machine->numa_state); + build_hmat(tables_blob, tables->linker, machine->numa_state, + pcms->oem_id, pcms->oem_table_id); } } if (acpi_get_mcfg(&mcfg)) { acpi_add_table(table_offsets, tables_blob); - build_mcfg(tables_blob, tables->linker, &mcfg); + build_mcfg(tables_blob, tables->linker, &mcfg, pcms->oem_id, + pcms->oem_table_id); } if (x86_iommu_get_default()) { IommuType IOMMUType = x86_iommu_get_type(); if (IOMMUType == TYPE_AMD) { acpi_add_table(table_offsets, tables_blob); - build_amd_iommu(tables_blob, tables->linker); + build_amd_iommu(tables_blob, tables->linker, pcms->oem_id, + pcms->oem_table_id); } else if (IOMMUType == TYPE_INTEL) { acpi_add_table(table_offsets, tables_blob); - build_dmar_q35(tables_blob, tables->linker); + build_dmar_q35(tables_blob, tables->linker, pcms->oem_id, + pcms->oem_table_id); } } if (machine->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, - machine->nvdimms_state, machine->ram_slots); + machine->nvdimms_state, machine->ram_slots, + pcms->oem_id, pcms->oem_table_id); } acpi_add_table(table_offsets, tables_blob); - build_waet(tables_blob, tables->linker); + build_waet(tables_blob, tables->linker, pcms->oem_id, pcms->oem_table_id); /* Add tables supplied by user (if any) */ for (u = acpi_table_first(); u; u = acpi_table_next(u)) { @@ -2262,13 +2292,13 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) /* RSDT is pointed to by RSDP */ rsdt = tables_blob->len; build_rsdt(tables_blob, tables->linker, table_offsets, - slic_oem.id, slic_oem.table_id); + oem_id, oem_table_id); /* RSDP is in FSEG memory, so allocate it separately */ { AcpiRsdpData rsdp_data = { .revision = 0, - .oem_id = ACPI_BUILD_APPNAME6, + .oem_id = pcms->oem_id, .xsdt_tbl_offset = NULL, .rsdt_tbl_offset = &rsdt, }; diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index a6a30e8363..1f5947fcf9 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -72,7 +72,8 @@ void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, } void acpi_build_madt(GArray *table_data, BIOSLinker *linker, - X86MachineState *x86ms, AcpiDeviceIf *adev) + X86MachineState *x86ms, AcpiDeviceIf *adev, + const char *oem_id, const char *oem_table_id) { MachineClass *mc = MACHINE_GET_CLASS(x86ms); const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms)); @@ -157,6 +158,6 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker, build_header(linker, table_data, (void *)(table_data->data + madt_start), "APIC", - table_data->len - madt_start, 1, NULL, NULL); + table_data->len - madt_start, 1, oem_id, oem_table_id); } diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index d34a301b84..54b3af478a 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -149,7 +149,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *linker, g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - dsdt->buf->len), - "DSDT", dsdt->buf->len, 2, NULL, NULL); + "DSDT", dsdt->buf->len, 2, mms->oem_id, mms->oem_table_id); free_aml_allocator(); } @@ -201,21 +201,24 @@ static void acpi_build_microvm(AcpiBuildTables *tables, pmfadt.dsdt_tbl_offset = &dsdt; pmfadt.xdsdt_tbl_offset = &dsdt; acpi_add_table(table_offsets, tables_blob); - build_fadt(tables_blob, tables->linker, &pmfadt, NULL, NULL); + build_fadt(tables_blob, tables->linker, &pmfadt, mms->oem_id, + mms->oem_table_id); acpi_add_table(table_offsets, tables_blob); acpi_build_madt(tables_blob, tables->linker, X86_MACHINE(machine), - ACPI_DEVICE_IF(x86ms->acpi_dev)); + ACPI_DEVICE_IF(x86ms->acpi_dev), mms->oem_id, + mms->oem_table_id); xsdt = tables_blob->len; - build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL); + build_xsdt(tables_blob, tables->linker, table_offsets, mms->oem_id, + mms->oem_table_id); /* RSDP is in FSEG memory, so allocate it separately */ { AcpiRsdpData rsdp_data = { /* ACPI 2.0: 5.2.4.3 RSDP Structure */ .revision = 2, /* xsdt needs v2 */ - .oem_id = ACPI_BUILD_APPNAME6, + .oem_id = mms->oem_id, .xsdt_tbl_offset = &xsdt, .rsdt_tbl_offset = NULL, }; diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index edf2b0f061..1dc2956e72 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -648,6 +648,51 @@ static void microvm_powerdown_req(Notifier *notifier, void *data) } } +static char *microvm_machine_get_oem_id(Object *obj, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + + return g_strdup(mms->oem_id); +} + +static void microvm_machine_set_oem_id(Object *obj, const char *value, + Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + size_t len = strlen(value); + + if (len > 6) { + error_setg(errp, + "User specified "MICROVM_MACHINE_OEM_ID" value is bigger than " + "6 bytes in size"); + return; + } + + strncpy(mms->oem_id, value, len + 1); +} + +static char *microvm_machine_get_oem_table_id(Object *obj, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + + return g_strdup(mms->oem_table_id); +} + +static void microvm_machine_set_oem_table_id(Object *obj, const char *value, + Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + size_t len = strlen(value); + + if (len > 8) { + error_setg(errp, + "User specified "MICROVM_MACHINE_OEM_TABLE_ID" value is bigger than " + "8 bytes in size"); + return; + } + strncpy(mms->oem_table_id, value, len + 1); +} + static void microvm_machine_initfn(Object *obj) { MicrovmMachineState *mms = MICROVM_MACHINE(obj); @@ -669,6 +714,9 @@ static void microvm_machine_initfn(Object *obj) qemu_add_machine_init_done_notifier(&mms->machine_done); mms->powerdown_req.notify = microvm_powerdown_req; qemu_register_powerdown_notifier(&mms->powerdown_req); + + mms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); + mms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); } static void microvm_class_init(ObjectClass *oc, void *data) @@ -757,6 +805,24 @@ static void microvm_class_init(ObjectClass *oc, void *data) MICROVM_MACHINE_AUTO_KERNEL_CMDLINE, "Set off to disable adding virtio-mmio devices to the kernel cmdline"); + object_class_property_add_str(oc, MICROVM_MACHINE_OEM_ID, + microvm_machine_get_oem_id, + microvm_machine_set_oem_id); + object_class_property_set_description(oc, MICROVM_MACHINE_OEM_ID, + "Override the default value of field OEMID " + "in ACPI table header." + "The string may be up to 6 bytes in size"); + + + object_class_property_add_str(oc, MICROVM_MACHINE_OEM_TABLE_ID, + microvm_machine_get_oem_table_id, + microvm_machine_set_oem_table_id); + object_class_property_set_description(oc, MICROVM_MACHINE_OEM_TABLE_ID, + "Override the default value of field OEM Table ID " + "in ACPI table header." + "The string may be up to 8 bytes in size"); + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5458f61d10..437977c49e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1611,6 +1611,50 @@ static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, pcms->max_fw_size = value; } +static char *pc_machine_get_oem_id(Object *obj, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + + return g_strdup(pcms->oem_id); +} + +static void pc_machine_set_oem_id(Object *obj, const char *value, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + size_t len = strlen(value); + + if (len > 6) { + error_setg(errp, + "User specified "PC_MACHINE_OEM_ID" value is bigger than " + "6 bytes in size"); + return; + } + + strncpy(pcms->oem_id, value, len + 1); +} + +static char *pc_machine_get_oem_table_id(Object *obj, Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + + return g_strdup(pcms->oem_table_id); +} + +static void pc_machine_set_oem_table_id(Object *obj, const char *value, + Error **errp) +{ + PCMachineState *pcms = PC_MACHINE(obj); + size_t len = strlen(value); + + if (len > 8) { + error_setg(errp, + "User specified "PC_MACHINE_OEM_TABLE_ID" value is bigger than " + "8 bytes in size"); + return; + } + strncpy(pcms->oem_table_id, value, len + 1); +} + static void pc_machine_initfn(Object *obj) { PCMachineState *pcms = PC_MACHINE(obj); @@ -1623,6 +1667,8 @@ static void pc_machine_initfn(Object *obj) pcms->max_ram_below_4g = 0; /* use default */ /* acpi build is enabled by default if machine supports it */ pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; + pcms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); + pcms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); pcms->smbus_enabled = true; pcms->sata_enabled = true; pcms->pit_enabled = true; @@ -1759,6 +1805,24 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) NULL, NULL); object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, "Maximum combined firmware size"); + + object_class_property_add_str(oc, PC_MACHINE_OEM_ID, + pc_machine_get_oem_id, + pc_machine_set_oem_id); + object_class_property_set_description(oc, PC_MACHINE_OEM_ID, + "Override the default value of field OEMID " + "in ACPI table header." + "The string may be up to 6 bytes in size"); + + + object_class_property_add_str(oc, PC_MACHINE_OEM_TABLE_ID, + pc_machine_get_oem_table_id, + pc_machine_set_oem_table_id); + object_class_property_set_description(oc, PC_MACHINE_OEM_TABLE_ID, + "Override the default value of field OEM Table ID " + "in ACPI table header." + "The string may be up to 8 bytes in size"); + } static const TypeInfo pc_machine_info = { -- 2.26.2 From MAILER-DAEMON Mon Jan 18 19:32:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1ewn-0003Gu-N6 for mharc-qemu-arm@gnu.org; Mon, 18 Jan 2021 19:32:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewk-00039L-Ie; Mon, 18 Jan 2021 19:32:34 -0500 Received: from mail.mutex.one ([62.77.152.124]:49596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1ewf-0004Cv-9O; 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Tsirkin" , Shannon Zhao , Marian Postevca Subject: [PATCH v4 3/5] tests/acpi: add OEM ID and OEM TABLE ID test Date: Tue, 19 Jan 2021 02:32:14 +0200 Message-Id: <20210119003216.17637-4-posteuca@mutex.one> In-Reply-To: <20210119003216.17637-1-posteuca@mutex.one> References: <20210119003216.17637-1-posteuca@mutex.one> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=62.77.152.124; envelope-from=marian@mutex.one; helo=mail.mutex.one X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 00:32:34 -0000 Add support for testing the fields OEM ID and OEM TABLE ID in all ACPI tables for PC,Q35,MICROVM,AARCH64 Full diff of changed files disassembly: Table tests/data/acpi/virt/FACP diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-VQIIX0, Mon Jan 18 23:55:00 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : BB +[009h 0009 1] Checksum : 55 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/APIC diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/APIC, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-BQIIX0, Mon Jan 18 23:55:00 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 000000A8 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : B3 +[009h 0009 1] Checksum : 50 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/GTDT diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-QQIIX0, Mon Jan 18 23:55:00 2021 * * ACPI Data Table [GTDT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] [004h 0004 4] Table Length : 00000060 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : D9 +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCGTDT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/MCFG diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/MCFG, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-OQIIX0, Mon Jan 18 23:55:00 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 4F +[009h 0009 1] Checksum : EC [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SPCR diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-EMIIX0, Mon Jan 18 23:55:00 2021 * * ACPI Data Table [SPCR] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 13 +[009h 0009 1] Checksum : CB [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSPCR" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/DSDT diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT, Mon Jan 18 23:55:00 2021 + * Disassembly of /tmp/aml-RMIIX0, Mon Jan 18 23:55:00 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0x60 + * Checksum 0x0F * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Table tests/data/acpi/virt/FACP.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-JROMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : BB +[009h 0009 1] Checksum : 55 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/APIC.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/APIC.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-2ROMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 000000A8 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : B3 +[009h 0009 1] Checksum : 50 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/GTDT.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-WROMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [GTDT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] [004h 0004 4] Table Length : 00000060 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : D9 +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCGTDT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/MCFG.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/MCFG.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-YOOMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 4F +[009h 0009 1] Checksum : EC [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SPCR.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-TOOMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [SPCR] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 13 +[009h 0009 1] Checksum : CB [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSPCR" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SRAT.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SRAT.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-LPOMX0, Mon Jan 18 23:55:27 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 0000006A [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : AB +[009h 0009 1] Checksum : 65 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/DSDT.numamem diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.numamem, Mon Jan 18 23:55:27 2021 + * Disassembly of /tmp/aml-HPOMX0, Mon Jan 18 23:55:27 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0x60 + * Checksum 0x0F * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Table tests/data/acpi/virt/FACP.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-OERTX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : BB +[009h 0009 1] Checksum : 55 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/APIC.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/APIC.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-FERTX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 000000A8 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : B3 +[009h 0009 1] Checksum : 50 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/GTDT.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-BERTX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [GTDT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] [004h 0004 4] Table Length : 00000060 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : D9 +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCGTDT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/MCFG.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/MCFG.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-8DRTX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 4F +[009h 0009 1] Checksum : EC [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SPCR.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-IN6NX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [SPCR] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 13 +[009h 0009 1] Checksum : CB [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSPCR" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SRAT.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SRAT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-FN6NX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 000000E2 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 5C +[009h 0009 1] Checksum : 16 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SLIT.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SLIT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-CN6NX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [SLIT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SLIT" [System Locality Information Table] [004h 0004 4] Table Length : 00000030 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 2C +[009h 0009 1] Checksum : E8 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSLIT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SSDT.memhp diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/SSDT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-9M6NX0, Mon Jan 18 23:55:41 2021 * * Original Table Header: * Signature "SSDT" * Length 0x000002E0 (736) * Revision 0x01 - * Checksum 0x3F + * Checksum 0xFF * OEM ID "BOCHS " - * OEM Table ID "NVDIMM" + * OEM Table ID "NVDIMM " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM ", 0x00000001) { Scope (\_SB) { Table tests/data/acpi/virt/NFIT.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/NFIT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-6M6NX0, Mon Jan 18 23:55:41 2021 * * ACPI Data Table [NFIT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] [004h 0004 4] Table Length : 000000E0 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : D1 +[009h 0009 1] Checksum : 82 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCNFIT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/DSDT.memhp diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.memhp, Mon Jan 18 23:55:41 2021 + * Disassembly of /tmp/aml-3M6NX0, Mon Jan 18 23:55:41 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000019A5 (6565) * Revision 0x02 - * Checksum 0x90 + * Checksum 0x3F * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj) Table tests/data/acpi/virt/FACP.pxb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-206LX0, Mon Jan 18 23:55:52 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : BB +[009h 0009 1] Checksum : 55 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/APIC.pxb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/APIC, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-E16LX0, Mon Jan 18 23:55:52 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 000000A8 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : B3 +[009h 0009 1] Checksum : 50 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/GTDT.pxb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-J16LX0, Mon Jan 18 23:55:52 2021 * * ACPI Data Table [GTDT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] [004h 0004 4] Table Length : 00000060 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : D9 +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCGTDT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/MCFG.pxb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/MCFG, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-N16LX0, Mon Jan 18 23:55:52 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 4F +[009h 0009 1] Checksum : EC [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/SPCR.pxb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-B16LX0, Mon Jan 18 23:55:52 2021 * * ACPI Data Table [SPCR] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 13 +[009h 0009 1] Checksum : CB [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSPCR" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/virt/DSDT.pxb diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.pxb, Mon Jan 18 23:55:52 2021 + * Disassembly of /tmp/aml-G16LX0, Mon Jan 18 23:55:52 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001E09 (7689) * Revision 0x02 - * Checksum 0x30 + * Checksum 0xDF * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Table tests/data/acpi/pc/HPET diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/HPET, Mon Jan 18 23:58:53 2021 + * Disassembly of /tmp/aml-QNVAX0, Mon Jan 18 23:58:53 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/WAET diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/WAET, Mon Jan 18 23:58:53 2021 + * Disassembly of /tmp/aml-NNVAX0, Mon Jan 18 23:58:53 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/FACP.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-MB7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-3C7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-0C7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/TPM2.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/TPM2.tis, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-ZC7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [TPM2] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table] [004h 0004 4] Table Length : 0000004C [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : 72 +[009h 0009 1] Checksum : 15 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCTPM2" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-XC7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.tis diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-VC7EX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.tis diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.tis, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-RC7EX0, Mon Jan 18 23:58:55 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000020D7 (8407) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xC8 + * Checksum 0x77 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/q35/FACP.bridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-3N7NX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.bridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-WN7NX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.bridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-DI7NX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.bridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-BI7NX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.bridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-9H7NX0, Mon Jan 18 23:58:55 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.bridge diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.bridge, Mon Jan 18 23:58:55 2021 + * Disassembly of /tmp/aml-6H7NX0, Mon Jan 18 23:58:55 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001E8B (7819) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x8F + * Checksum 0x3E * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/q35/FACP.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-KW0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-HR0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-LR0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SRAT.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/SRAT.mmio64, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-OR0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 000000E0 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 3B +[009h 0009 1] Checksum : F5 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-TR0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.mmio64 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-ZR0GX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.mmio64 diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.mmio64, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-7R0GX0, Mon Jan 18 23:58:56 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000022E4 (8932) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x9D + * Checksum 0x4C * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/q35/FACP.ipmibt diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-VVX8W0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.ipmibt diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-GUX8W0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.ipmibt diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-LUX8W0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.ipmibt diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-QUX8W0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.ipmibt diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-VUX8W0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.ipmibt diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.ipmibt, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-3UX8W0, Mon Jan 18 23:58:56 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001EC4 (7876) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x2A + * Checksum 0xD9 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/q35/FACP.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-2HJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.cphp, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-ARJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 000000A0 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 7B +[009h 0009 1] Checksum : 18 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-ERJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SRAT.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/SRAT.cphp, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-IRJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 00000130 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 36 +[009h 0009 1] Checksum : F0 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SLIT.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/SLIT.cphp, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-MRJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [SLIT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SLIT" [System Locality Information Table] [004h 0004 4] Table Length : 00000030 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 2C +[009h 0009 1] Checksum : E8 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSLIT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:56 2021 + * Disassembly of /tmp/aml-PRJNX0, Mon Jan 18 23:58:56 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.cphp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-TRJNX0, Mon Jan 18 23:58:57 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.cphp diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.cphp, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-2RJNX0, Mon Jan 18 23:58:57 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00002049 (8265) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x5A + * Checksum 0x09 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/q35/HPET.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-V1NBX0, Mon Jan 18 23:58:57 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.memhp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-B2NBX0, Mon Jan 18 23:58:57 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-BJ6PX0, Mon Jan 18 23:58:57 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.numamem diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:57 2021 + * Disassembly of /tmp/aml-UH6PX0, Mon Jan 18 23:58:57 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/FACP.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-ITDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.dimmpxm, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-STDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000090 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : AE +[009h 0009 1] Checksum : 4B [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-WTDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SRAT.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/SRAT.dimmpxm, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-XTJEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 00000188 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 68 +[009h 0009 1] Checksum : 22 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-0TDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SSDT.dimmpxm diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-8TDEX0, Mon Jan 18 23:58:58 2021 * * Original Table Header: * Signature "SSDT" * Length 0x000002DE (734) * Revision 0x01 - * Checksum 0x46 + * Checksum 0x06 * OEM ID "BOCHS " - * OEM Table ID "NVDIMM" + * OEM Table ID "NVDIMM " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM ", 0x00000001) { Scope (\_SB) { Table tests/data/acpi/q35/NFIT.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-9VDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [NFIT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] [004h 0004 4] Table Length : 000000F0 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 24 +[009h 0009 1] Checksum : D5 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCNFIT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.dimmpxm diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-DWDEX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.dimmpxm diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.dimmpxm, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-IWDEX0, Mon Jan 18 23:58:58 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000024EF (9455) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x26 + * Checksum 0xD5 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { External (_SB_.NVDR, UnknownObj) Table tests/data/acpi/q35/FACP.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/FACP, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-OKSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 1F +[009h 0009 1] Checksum : B9 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/APIC.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.acpihmat, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-0KSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000080 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : DA +[009h 0009 1] Checksum : 77 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HPET.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HPET, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-5KSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/SRAT.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/SRAT.acpihmat, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-9KSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [SRAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] [004h 0004 4] Table Length : 00000118 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : C0 +[009h 0009 1] Checksum : 7A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCSRAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/HMAT.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-ALYOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [HMAT] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] [004h 0004 4] Table Length : 00000118 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 98 +[009h 0009 1] Checksum : 42 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHMAT" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/MCFG.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/MCFG, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-ELSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [MCFG] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : EF +[009h 0009 1] Checksum : 8C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCMCFG" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/WAET.acpihmat diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/WAET, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-ILSOX0, Mon Jan 18 23:58:58 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/q35/DSDT.acpihmat diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.acpihmat, Mon Jan 18 23:58:58 2021 + * Disassembly of /tmp/aml-2JSOX0, Mon Jan 18 23:58:58 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000023A6 (9126) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xB3 + * Checksum 0x62 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/pc/FACP.ipmikcs diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/FACP, Mon Jan 18 23:58:59 2021 + * Disassembly of /tmp/aml-1HH9W0, Mon Jan 18 23:58:59 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000074 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : A1 +[009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/APIC.ipmikcs diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/APIC, Mon Jan 18 23:58:59 2021 + * Disassembly of /tmp/aml-GIH9W0, Mon Jan 18 23:58:59 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/HPET.ipmikcs diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/HPET, Mon Jan 18 23:58:59 2021 + * Disassembly of /tmp/aml-PIH9W0, Mon Jan 18 23:58:59 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/WAET.ipmikcs diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/WAET, Mon Jan 18 23:58:59 2021 + * Disassembly of /tmp/aml-OIH9W0, Mon Jan 18 23:58:59 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/DSDT.ipmikcs diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT.ipmikcs, Mon Jan 18 23:58:59 2021 + * Disassembly of /tmp/aml-9GH9W0, Mon Jan 18 23:58:59 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00001411 (5137) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x33 + * Checksum 0xE2 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/pc/FACP.roothp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/FACP, Mon Jan 18 23:59:01 2021 + * Disassembly of /tmp/aml-84PIX0, Mon Jan 18 23:59:01 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000074 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : A1 +[009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/APIC.roothp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/APIC, Mon Jan 18 23:59:01 2021 + * Disassembly of /tmp/aml-D5PIX0, Mon Jan 18 23:59:01 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/HPET.roothp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/HPET, Mon Jan 18 23:59:01 2021 + * Disassembly of /tmp/aml-P5PIX0, Mon Jan 18 23:59:01 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/WAET.roothp diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/WAET, Mon Jan 18 23:59:01 2021 + * Disassembly of /tmp/aml-N5PIX0, Mon Jan 18 23:59:01 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/DSDT.roothp diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT.roothp, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-83PIX0, Mon Jan 18 23:59:02 2021 * * Original Table Header: * Signature "DSDT" * Length 0x0000148D (5261) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xC6 + * Checksum 0x75 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/pc/FACP.hpbridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/FACP, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-2ZSAX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000074 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : A1 +[009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/APIC.hpbridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/APIC, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-B0SAX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/HPET.hpbridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/HPET, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-G2SAX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/WAET.hpbridge diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/WAET, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-F2SAX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/DSDT.hpbridge diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT.hpbridge, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-R2SAX0, Mon Jan 18 23:59:02 2021 * * Original Table Header: * Signature "DSDT" * Length 0x000013A2 (5026) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xD9 + * Checksum 0x88 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/pc/FACP.hpbrroot diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/FACP, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-D9COX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000074 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : A1 +[009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/APIC.hpbrroot diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/APIC, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-K9COX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : ED +[009h 0009 1] Checksum : 8A [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/HPET.hpbrroot diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/HPET, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-L4COX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [HPET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 03 +[009h 0009 1] Checksum : B4 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCHPET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/WAET.hpbrroot diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/pc/WAET, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-W4COX0, Mon Jan 18 23:59:02 2021 * * ACPI Data Table [WAET] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] [004h 0004 4] Table Length : 00000028 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 88 +[009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCWAET" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/pc/DSDT.hpbrroot diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT.hpbrroot, Mon Jan 18 23:59:02 2021 + * Disassembly of /tmp/aml-S4COX0, Mon Jan 18 23:59:02 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00000C0C (3084) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x81 + * Checksum 0x30 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { Table tests/data/acpi/microvm/FACP.usb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/FACP, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-PZ3FX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : 7E +[009h 0009 1] Checksum : 18 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/APIC.usb diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/APIC, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-ZZ3FX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000046 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : D7 +[009h 0009 1] Checksum : 74 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/DSDT.usb diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/microvm/DSDT.usb, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-XZ3FX0, Mon Jan 18 23:59:03 2021 * * Original Table Header: * Signature "DSDT" * Length 0x0000019E (414) * Revision 0x02 - * Checksum 0x72 + * Checksum 0x21 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (_SB) { Table tests/data/acpi/microvm/FACP.rtc diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/FACP, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-TX8BX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : 7E +[009h 0009 1] Checksum : 18 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/APIC.rtc diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/APIC, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-QS8BX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000046 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : D7 +[009h 0009 1] Checksum : 74 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/DSDT.rtc diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/microvm/DSDT.rtc, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-4S8BX0, Mon Jan 18 23:59:03 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00000194 (404) * Revision 0x02 - * Checksum 0x30 + * Checksum 0xDF * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (_SB) { Table tests/data/acpi/microvm/FACP.ioapic2 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/FACP, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-ZRMOX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : 7E +[009h 0009 1] Checksum : 18 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/APIC.ioapic2 diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/APIC.ioapic2, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-VMMOX0, Mon Jan 18 23:59:03 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000052 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : E6 +[009h 0009 1] Checksum : 83 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/DSDT.ioapic2 diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/microvm/DSDT.ioapic2, Mon Jan 18 23:59:03 2021 + * Disassembly of /tmp/aml-TMMOX0, Mon Jan 18 23:59:03 2021 * * Original Table Header: * Signature "DSDT" * Length 0x0000016D (365) * Revision 0x02 - * Checksum 0x1C + * Checksum 0xCB * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (_SB) { Table tests/data/acpi/microvm/FACP.pcie diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/FACP, Tue Jan 19 00:03:13 2021 + * Disassembly of /tmp/aml-M6CGX0, Tue Jan 19 00:03:13 2021 * * ACPI Data Table [FACP] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 0000010C [008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : 7E +[009h 0009 1] Checksum : 18 [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCFACP" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/APIC.pcie diff: @@ -3,7 +3,7 @@ * AML/ASL+ Disassembler version 20200326 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/microvm/APIC.pcie, Tue Jan 19 00:03:13 2021 + * Disassembly of /tmp/aml-V6CGX0, Tue Jan 19 00:03:13 2021 * * ACPI Data Table [APIC] * @@ -13,9 +13,9 @@ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 0000006E [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : DF +[009h 0009 1] Checksum : 7C [00Ah 0010 6] Oem ID : "BOCHS " -[010h 0016 8] Oem Table ID : "BXPCAPIC" +[010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 Table tests/data/acpi/microvm/DSDT.pcie diff: @@ -5,20 +5,20 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Tue Jan 19 00:03:13 2021 + * Disassembly of /tmp/aml-16CGX0, Tue Jan 19 00:03:13 2021 * * Original Table Header: * Signature "DSDT" * Length 0x00000BD7 (3031) * Revision 0x02 - * Checksum 0x99 + * Checksum 0x48 * OEM ID "BOCHS " - * OEM Table ID "BXPCDSDT" + * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ -DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (_SB) { Signed-off-by: Marian Postevca --- tests/qtest/bios-tables-test.c | 170 ++++++++++++++++++++++++++++----- 1 file changed, 146 insertions(+), 24 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 669202fc95..77053975aa 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -64,13 +64,17 @@ #include "boot-sector.h" #include "tpm-emu.h" #include "hw/acpi/tpm.h" - +#include "qemu/cutils.h" #define MACHINE_PC "pc" #define MACHINE_Q35 "q35" #define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" +#define OEM_ID "TEST" +#define OEM_TABLE_ID "OEM" +#define OEM_TEST_ARGS "-machine oem-id="OEM_ID",oem-table-id="OEM_TABLE_ID + typedef struct { bool tcg_only; const char *machine; @@ -654,17 +658,28 @@ static void test_smbios_structs(test_data *data) } } -static void test_acpi_one(const char *params, test_data *data) +static void test_acpi_load_tables(test_data *data, bool use_uefi) { - char *args; - bool use_uefi = data->uefi_fl1 && data->uefi_fl2; - -#ifndef CONFIG_TCG - if (data->tcg_only) { - g_test_skip("TCG disabled, skipping ACPI tcg_only test"); - return; + if (use_uefi) { + g_assert(data->scan_len); + data->rsdp_addr = acpi_find_rsdp_address_uefi(data->qts, + data->ram_start, data->scan_len); + } else { + boot_sector_test(data->qts); + data->rsdp_addr = acpi_find_rsdp_address(data->qts); + g_assert_cmphex(data->rsdp_addr, <, 0x100000); } -#endif /* CONFIG_TCG */ + + data->tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + test_acpi_rsdp_table(data); + test_acpi_rxsdt_table(data); + test_acpi_fadt_table(data); +} + +static char *test_acpi_create_args(test_data *data, const char *params, + bool use_uefi) +{ + char *args; if (use_uefi) { /* @@ -695,23 +710,24 @@ static void test_acpi_one(const char *params, test_data *data) params ? params : "", disk, data->blkdev ?: "ide-hd"); } + return args; +} - data->qts = qtest_init(args); +static void test_acpi_one(const char *params, test_data *data) +{ + char *args; + bool use_uefi = data->uefi_fl1 && data->uefi_fl2; - if (use_uefi) { - g_assert(data->scan_len); - data->rsdp_addr = acpi_find_rsdp_address_uefi(data->qts, - data->ram_start, data->scan_len); - } else { - boot_sector_test(data->qts); - data->rsdp_addr = acpi_find_rsdp_address(data->qts); - g_assert_cmphex(data->rsdp_addr, <, 0x100000); +#ifndef CONFIG_TCG + if (data->tcg_only) { + g_test_skip("TCG disabled, skipping ACPI tcg_only test"); + return; } +#endif /* CONFIG_TCG */ - data->tables = g_array_new(false, true, sizeof(AcpiSdtTable)); - test_acpi_rsdp_table(data); - test_acpi_rxsdt_table(data); - test_acpi_fadt_table(data); + args = test_acpi_create_args(data, params, use_uefi); + data->qts = qtest_init(args); + test_acpi_load_tables(data, use_uefi); if (getenv(ACPI_REBUILD_EXPECTED_AML)) { dump_aml_files(data, true); @@ -1292,6 +1308,109 @@ static void test_acpi_virt_tcg(void) free_test_data(&data); } +static void test_oem_fields(test_data *data) +{ + int i; + char oem_id[6]; + char oem_table_id[8]; + + strpadcpy(oem_id, sizeof oem_id, OEM_ID, ' '); + strpadcpy(oem_table_id, sizeof oem_table_id, OEM_TABLE_ID, ' '); + for (i = 0; i < data->tables->len; ++i) { + AcpiSdtTable *sdt; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + /* FACS doesn't have OEMID and OEMTABLEID fields */ + if (compare_signature(sdt, "FACS")) { + continue; + } + + g_assert(memcmp(sdt->aml + 10, oem_id, 6) == 0); + g_assert(memcmp(sdt->aml + 16, oem_table_id, 8) == 0); + } +} + +static void test_acpi_oem_fields_pc(void) +{ + test_data data; + char *args; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + + args = test_acpi_create_args(&data, + OEM_TEST_ARGS, false); + data.qts = qtest_init(args); + test_acpi_load_tables(&data, false); + test_oem_fields(&data); + qtest_quit(data.qts); + free_test_data(&data); + g_free(args); +} + +static void test_acpi_oem_fields_q35(void) +{ + test_data data; + char *args; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + + args = test_acpi_create_args(&data, + OEM_TEST_ARGS, false); + data.qts = qtest_init(args); + test_acpi_load_tables(&data, false); + test_oem_fields(&data); + qtest_quit(data.qts); + free_test_data(&data); + g_free(args); +} + +static void test_acpi_oem_fields_microvm(void) +{ + test_data data; + char *args; + + test_acpi_microvm_prepare(&data); + + args = test_acpi_create_args(&data, + OEM_TEST_ARGS",acpi=on", false); + data.qts = qtest_init(args); + test_acpi_load_tables(&data, false); + test_oem_fields(&data); + qtest_quit(data.qts); + free_test_data(&data); + g_free(args); +} + +static void test_acpi_oem_fields_virt(void) +{ + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + char *args; + + args = test_acpi_create_args(&data, + "-cpu cortex-a57 "OEM_TEST_ARGS, true); + data.qts = qtest_init(args); + test_acpi_load_tables(&data, true); + test_oem_fields(&data); + qtest_quit(data.qts); + free_test_data(&data); + g_free(args); +} + + int main(int argc, char *argv[]) { const char *arch = qtest_get_arch(); @@ -1304,9 +1423,10 @@ int main(int argc, char *argv[]) if (ret) { return ret; } - + qtest_add_func("acpi/q35/oem-fields", test_acpi_oem_fields_q35); qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis); qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); + qtest_add_func("acpi/oem-fields", test_acpi_oem_fields_pc); qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); qtest_add_func("acpi/piix4/pci-hotplug/no_root_hotplug", test_acpi_piix4_no_root_hotplug); @@ -1333,6 +1453,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg); qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg); qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2_tcg); + qtest_add_func("acpi/microvm/oem-fields", test_acpi_oem_fields_microvm); if (strcmp(arch, "x86_64") == 0) { qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg); } @@ -1341,6 +1462,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); + qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); } ret = g_test_run(); boot_sector_cleanup(disk); -- 2.26.2 From MAILER-DAEMON Tue Jan 19 01:27:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1kUW-0005lF-7x for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 01:27:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1kUT-0005dx-SS; Tue, 19 Jan 2021 01:27:45 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:46264) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1kUR-00025k-Vz; Tue, 19 Jan 2021 01:27:45 -0500 Received: by mail-ej1-x630.google.com with SMTP id rv9so8105600ejb.13; Mon, 18 Jan 2021 22:27:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QGEW/zhOCWpBx/ValuvqrDoUReEloE3J1VaEmWJOUPE=; b=dUtqZiCpuugJXP+lVz8o5S3DnNQCHOvVd0OE+I6H0e7Qu24JDuw+Qr5EO362RzBBUR ULiNIR7wOPxb3dfceqqL97YDlxaI+V2oFW2qtJvd99TOyAJ+90V20GGt8MD8IPzOt8+t DlLLd54NxP4/kxpYKNWHc5KPZxIgQnWZf3JojQ4Lle9ov05MBucOIYZ6Ou7pzQWEAc1y i+p/JyIa9kCd63QW+CrVDhtkEQkU76Y20isPhcvLN2CwQO8USvP8q7KV7hNHjNcngpEa SNxPz23BAY6z8XBn7HoITGjIgurVa2txPWKxF8BJHASf0VRHwrjwQgpGd/TrUr4qQZic CbnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=QGEW/zhOCWpBx/ValuvqrDoUReEloE3J1VaEmWJOUPE=; b=G8dhIHMKo8jiNaWMXrfmWZ2cb6svijn4MEzJ33J+YNX0fy5SoQGpFBbjTcHw2zakGO vWpnE65CW5VmESWRe9p4ih9eHgY1dvezKHauq1UdgbI+i6gt9HxBKL4qK5WCDB7cD2Q0 VH0rq75btung/qBIFpD02yTyNjSi+DB5ghRCjsf4qzz/IsmyqoQN3PSmhuXqzAroHGWK j9rCwa77FqG8T5yd1IpF9ig6kB0vOlqBRFa25oCGA9QNstr9UjtF/eYA7BYcXESaK/yF bK2+2q5TF8dK2cYfLZJ8u8ik3uCYgbz2c6vrC09Exms8Hx53NocQ0qgw01d1SRv/eiVF FbCQ== X-Gm-Message-State: AOAM533ox3mfE/aDYB5L79HHichCZs9THLdnQsyTJMT9CtFjoTkdN6hz tL5q6NEW40R6gzxebsmuNyFWGl+6+ic= X-Google-Smtp-Source: ABdhPJxd1EJzrrB+1loKd/kLbqMd14iHb6TEvtBpcmFb7PTCkkPughfkBUxZaCUTc96lMMhOegNOxw== X-Received: by 2002:a17:906:3111:: with SMTP id 17mr1900065ejx.152.1611037661580; Mon, 18 Jan 2021 22:27:41 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z1sm12374201edm.89.2021.01.18.22.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 22:27:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error Date: Tue, 19 Jan 2021 07:27:39 +0100 Message-Id: <20210119062739.589049-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 06:27:46 -0000 When building with GCC 10.2 configured with --extra-cflags=-Os, we get: target/arm/m_helper.c: In function ‘arm_v7m_cpu_do_interrupt’: target/arm/m_helper.c:1811:16: error: ‘restore_s16_s31’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 1811 | if (restore_s16_s31) { | ^ target/arm/m_helper.c:1350:10: note: ‘restore_s16_s31’ was declared here 1350 | bool restore_s16_s31; | ^~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Initialize the 'restore_s16_s31' variable to silence the warning. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/m_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 61760030292..731c435c00b 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1347,7 +1347,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) bool exc_secure = false; bool return_to_secure; bool ftype; - bool restore_s16_s31; + bool restore_s16_s31 = false; /* * If we're not in Handler mode then jumps to magic exception-exit -- 2.26.2 From MAILER-DAEMON Tue Jan 19 04:31:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1nMe-0002NY-F5 for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 04:31:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1nMa-0002Mq-B2 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 04:31:48 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:40458) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l1nMU-0004Lu-1v for qemu-arm@nongnu.org; Tue, 19 Jan 2021 04:31:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611048698; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xulv5qrwxLW33dgl698lNJ3S8VNsLvKeCSoAliN+00Q=; b=QeC52+s8y7nS2SC91421+okPPrnvg5DFVtaatND+TM4JHBmtQowA5Ho/eVSU1cNrUKLz7R 8H2lMLAoO1fTO5jBrANYtaE6wmR0ZAIKCF+K8405AGcSOsYYGootaguEKXstAV/rSQek9z OVXHCdLAntpNgpQQ0+xzCpP6hEhfiqk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-40-CssNfIJaMfuScwP84PLyXA-1; Tue, 19 Jan 2021 04:31:35 -0500 X-MC-Unique: CssNfIJaMfuScwP84PLyXA-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3735859; Tue, 19 Jan 2021 09:31:33 +0000 (UTC) Received: from work-vm (ovpn-115-97.ams2.redhat.com [10.36.115.97]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7FFAC27C2E; Tue, 19 Jan 2021 09:31:26 +0000 (UTC) Date: Tue, 19 Jan 2021 09:31:23 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric?= Le Goater , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Subject: Re: [RFC PATCH v2 02/20] hw/core/qdev: Add vmstate_qdev_no_state_to_migrate Message-ID: <20210119093123.GB3008@work-vm> References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-3-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-3-f4bug@amsat.org> User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.175, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 09:31:48 -0000 * Philippe Mathieu-Daud (f4bug@amsat.org) wrote: > Add vmstate_qdev_no_state_to_migrate, which is simply a > pointer to vmstate_no_state_to_migrate. This way all > qdev devices (including "hw/qdev-core.h") don't have to > include "migration/vmstate.h". > > Signed-off-by: Philippe Mathieu-Daud > --- > Unresolved issues: > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg721695.html > Peter: > > Does this definitely not put any data into the migration stream? > > We don't want to change what's on the wire for machines that > > use devices that start using this. (If it does by default, it > > would be easy to make the migration code special case the > > magic symbol to act like "no vmsd specified"). > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg727634.html > Dave: > > I'd need to test it to be sure, but I think if we added a .needed > > to vmstate_no_state_to_migrate with a function that always returned > > false, then I think the stream would stay unchanged. Yes I still think you need that; if you only use this for base classes rather than devices themselves you're probably OK; but if you use it on a device I think you'll end up with an empty-state entry in the migration stream. Dave > --- > include/hw/qdev-core.h | 2 ++ > include/migration/vmstate.h | 1 + > hw/core/qdev.c | 3 +++ > migration/vmstate.c | 7 +++++++ > stubs/vmstate.c | 7 +++++++ > 5 files changed, 20 insertions(+) > > diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h > index bafc311bfa1..d2c7a46e6a2 100644 > --- a/include/hw/qdev-core.h > +++ b/include/hw/qdev-core.h > @@ -140,6 +140,8 @@ struct DeviceClass { > const char *bus_type; > }; > > +extern const VMStateDescription *vmstate_qdev_no_state_to_migrate; > + > typedef struct NamedGPIOList NamedGPIOList; > > struct NamedGPIOList { > diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h > index dda65c9987d..50559598eac 100644 > --- a/include/migration/vmstate.h > +++ b/include/migration/vmstate.h > @@ -197,6 +197,7 @@ struct VMStateDescription { > #if defined(CONFIG_USER_ONLY) > extern const VMStateDescription vmstate_user_mode_cpu_dummy; > #endif > +extern const VMStateDescription vmstate_no_state_to_migrate; > > extern const VMStateInfo vmstate_info_bool; > > diff --git a/hw/core/qdev.c b/hw/core/qdev.c > index cefc5eaa0a9..f0d0afd438d 100644 > --- a/hw/core/qdev.c > +++ b/hw/core/qdev.c > @@ -44,6 +44,9 @@ > static bool qdev_hot_added = false; > bool qdev_hot_removed = false; > > +const VMStateDescription *vmstate_qdev_no_state_to_migrate = > + &vmstate_no_state_to_migrate; > + > const VMStateDescription *qdev_get_vmsd(DeviceState *dev) > { > DeviceClass *dc = DEVICE_GET_CLASS(dev); > diff --git a/migration/vmstate.c b/migration/vmstate.c > index 05f87cdddc5..2c373774dfa 100644 > --- a/migration/vmstate.c > +++ b/migration/vmstate.c > @@ -20,6 +20,13 @@ > #include "qemu/error-report.h" > #include "trace.h" > > +const VMStateDescription vmstate_no_state_to_migrate = { > + .name = "empty-state", > + .fields = (VMStateField[]) { > + VMSTATE_END_OF_LIST() > + } > +}; > + > static int vmstate_subsection_save(QEMUFile *f, const VMStateDescription *vmsd, > void *opaque, JSONWriter *vmdesc); > static int vmstate_subsection_load(QEMUFile *f, const VMStateDescription *vmsd, > diff --git a/stubs/vmstate.c b/stubs/vmstate.c > index 8da777a1fb4..f561f9f39bd 100644 > --- a/stubs/vmstate.c > +++ b/stubs/vmstate.c > @@ -5,6 +5,13 @@ > const VMStateDescription vmstate_user_mode_cpu_dummy = {}; > #endif > > +const VMStateDescription vmstate_no_state_to_migrate = { > + .name = "empty-state", > + .fields = (VMStateField[]) { > + VMSTATE_END_OF_LIST() > + } > +}; > + > int vmstate_register_with_alias_id(VMStateIf *obj, > uint32_t instance_id, > const VMStateDescription *vmsd, > -- > 2.26.2 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Tue Jan 19 05:37:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1oOU-0007KA-QW for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 05:37:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1oOR-0007IJ-Hn for qemu-arm@nongnu.org; Tue, 19 Jan 2021 05:37:47 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:36262) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1oOO-00088D-T8 for qemu-arm@nongnu.org; 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Tue, 19 Jan 2021 02:37:43 -0800 (PST) MIME-Version: 1.0 References: <20210111235740.462469-1-richard.henderson@linaro.org> In-Reply-To: <20210111235740.462469-1-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 10:37:32 +0000 Message-ID: Subject: Re: [PATCH v7 0/3] target/arm: Implement an IMPDEF pauth algorithm To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 10:37:47 -0000 On Mon, 11 Jan 2021 at 23:57, Richard Henderson wrote: > > The architected pauth algorithm is quite slow without > hardware support, and boot times for kernels that enable > use of the feature have been significantly impacted. > > Version 7 changes: > * Fix rebase error (drjones). > > Version 6 changes: > * Rearrange xxhash64 (pmm). > * Add documentation (pmm). Applied to target-arm.next, thanks. I fixed a typo in the docs text in patch 2 and adjusted the text to say "impdef algorithm used by QEMU" to clarify that this is something of our own devising. -- PMM From MAILER-DAEMON Tue Jan 19 06:13:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1owy-0005Jg-Sd for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 06:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1owx-0005JY-RE for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:13:27 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:40037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1oww-0005LJ-4G for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:13:27 -0500 Received: by mail-ej1-x62e.google.com with SMTP id gx5so8684097ejb.7 for ; Tue, 19 Jan 2021 03:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Va2ToqzuZXjLYTsrbZlOjg9ZDsVIJQMzTwvNuZq3HZY=; b=x40L2mUUILLpCyFJxOTslHgDR5TQOztFfbS9hrrx1LLz3sDUCFQQKGHxSLmgs26Q/1 h37m5PxmJ90zHXZa8cWEykSmn2bOGPhUmM9TQs8mE0vPVxN4dvg1c+geIlD3J65fxWKq lcutKiv8akQkiu67TZ2c2LTgRoF2aYwM8zVucN/3/QIPwEqEQ8F41hSPSP3M2n5pCQV+ bLLcr8M+3jenP8+70Z1yS1UUCFWiflu7M2mJM4nL9PMwayR1qkChpQFQ7IFd+dxPEOSr fdQnHESyzmQEnbnlQp7BVsi3dg15h2hB+h1/DWBiINHw2heXsm/iFLC9ZUaN9WbpJ0fy y18w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Va2ToqzuZXjLYTsrbZlOjg9ZDsVIJQMzTwvNuZq3HZY=; b=OIJ0gEzKR2zQpqjJkgDMpKGuploATELeKySceI+YZiIAFGrmt9OUd3RWs8Eq7PMctO Nq7NgG+3VPzEY5Lq/fh/6dffOdBpxATnUAg8WT0Vvj+rLz6z4uE+UwzO75IT2Q0wqC1E Ej0o2J0MtXHT7kA/Wjijo9NeyA9bbMFE2jlheeCtOiKktTFEGx8rRsUVA6uLs76w4arU IbKZMHojhEhttY2DJeJxtdQN5ytdegvyqOgkNT0dofSRpyIpAOMee5SD+68amzu+kaaU Y31fT9y5n4bOz7G0WwFXaVolbAKr88tc+pTHp4XLPSCB5e+K2g5QvUf0qX7J/f/AiJIR vTig== X-Gm-Message-State: AOAM533jg0kgRCg407xttLrCgrpXL6yCKXs0NR47/HzEkxzcRLBqRPYB YcOi0uc69HWqcalDT9OZoOY0SBqs0ir63KyDGCuQqQ== X-Google-Smtp-Source: ABdhPJwyX2kKTa7Q9KQ0cgG99w7SHSB70vUN6mUhZB/w39G4U5fwq0ddottFpWIZByx8DNUrtSrckdzuLbUMRBvGK48= X-Received: by 2002:a17:906:b215:: with SMTP id p21mr2578993ejz.407.1611054804458; Tue, 19 Jan 2021 03:13:24 -0800 (PST) MIME-Version: 1.0 References: <12681824.uLZWGnKmhe@basile.remlab.net> In-Reply-To: <12681824.uLZWGnKmhe@basile.remlab.net> From: Peter Maydell Date: Tue, 19 Jan 2021 11:13:13 +0000 Message-ID: Subject: Re: [PATCHv5 00/19] ARMv8.4-A Secure EL2 To: =?UTF-8?Q?R=C3=A9mi_Denis=2DCourmont?= Cc: qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 11:13:28 -0000 On Tue, 12 Jan 2021 at 10:59, R=C3=A9mi Denis-Courmont wrote: > > Hi, > > This adds Secure EL2. > > Changes since version 4: > - Fix NS unitialised in secure state stage 2 translation. > - Remove EEL2 translation block flag in 32-bit mode. > - Clarify comments on arm_is_el2_enabled(). Looking through this patchset, it's practically ready and only needs a couple of very tiny tweaks, so rather than asking you to roll a v6, I'm just going to apply it to target-arm.next and make the tweaks in the process: * patch 6 needed adjustment on rebase as commit 00a92832f4532 has already added definitions of the ID_AA64PFR0 fields; I dropped the now-duplicate part of the patch and adjusted the commit message to match * patch 17: added the change requested by RTH: --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2837,7 +2837,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, */ TCGv_i32 tcg_el; - if (dc_isar_feature(aa64_sel2, s)) { + if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && + dc_isar_feature(aa64_sel2, s)) { /* Target EL is EL<3 minus SCR_EL3.EEL2> */ tcg_el =3D load_cpu_field(cp15.scr_el3); tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); and corrected the patch subject line to "target/arm: Implement SCR_EL2.EEL2" thanks -- PMM From MAILER-DAEMON Tue Jan 19 06:28:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1pBS-00034S-Hs for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 06:28:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1pBN-000338-8C for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:28:24 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]:45784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1pBL-0007WX-3S for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:28:21 -0500 Received: by mail-ej1-x632.google.com with SMTP id ke15so20303275ejc.12 for ; Tue, 19 Jan 2021 03:28:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=K+TcLFw/uO2ce2majfh9q8JMObqRCpJz3IWRacF/D5U=; b=yO0jdxizQ2aa++R1xr+g1v+MuyQ9l2ojTkZsgOJ/ja/AgOltglH9qI83IcpUocqa+C MAnuWzNqbbKjqjROcmhkVM6tqeMh/AKm/I3sDDEhxYz1OEwjO3mBDuxBGRf7GlZkG9Nb fIym6HsRbiYTcFWhluAUSC35c+2kOvZV5eYsvcbpcpPWG7a5Aq6RkxMV2L3sV/SmW8zY qDIoblZjnTIZtb+NDCx41+Pw3/Ty4XAxxY90IBn2jGDNNZChhb0XP3cW1OHGnIjM7a29 bKwXNVNJTCZ3XHhIz02KP/d6Vp4IzfaFCPmGJmLdu08lhaEcr2mKxcwdkE2GX7Lj8ACr SGkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=K+TcLFw/uO2ce2majfh9q8JMObqRCpJz3IWRacF/D5U=; b=Prp9rReifNBrOx8soccJOaltJjipNjxdPF+hxL5jD3FOqisP7zvh18/nogIrKM8yrZ 9OSXPlHRYve2FMwZDqdnGEzEQ6rblR5q6MApDhlO86nloYxX0gKC0TAX1yqxza27I9/7 VZjPZqVElbqo084R6QGOrAzZuEjKVaLoh5Axj6pGi3HRtlAoImXJkphXgvOVr3OQnHbK OcrtP02i1p8i8VqlyEAnPws2j2/987bgWslSYF2aFvpC2viAtStE7xXAA6yP+T2im0FU OoXI7YF5270LaIMgqLfG1LJNax6Dqme39aR2OddJQL74aaFkjnHF1sYp8BRl6JTZR2zQ yLXQ== X-Gm-Message-State: AOAM530Bd6DW2EWIrLaXmPh1bVUy6jWlr57N4KypDipnlTQAa5CtDsP+ 1IQ7AkmrBDJ2pwo3ABBFTrblE1bLKjAsBi1bMWxtgA== X-Google-Smtp-Source: ABdhPJx6t7IX9Ox7VQfxrQj8QJBXKvUUR+oGNJQZFeTv0Rf69wgYo9rc9PqhXOF5LN+D0s55R6+ywVP1vU1KtSZMWCg= X-Received: by 2002:a17:906:4bc2:: with SMTP id x2mr2641017ejv.4.1611055697533; Tue, 19 Jan 2021 03:28:17 -0800 (PST) MIME-Version: 1.0 References: <20210113062650.593824-1-richard.henderson@linaro.org> In-Reply-To: <20210113062650.593824-1-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 11:28:06 +0000 Message-ID: Subject: Re: [PATCH v2 0/4] target/arm: Fix sve pred_desc decoding To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 11:28:25 -0000 On Wed, 13 Jan 2021 at 06:26, Richard Henderson wrote: > > There was an inconsistency between encoding, which uses > SIMD_DATA_SHIFT, and decoding which used SIMD_OPRSZ_BITS. > This happened to be ok, until e2e7168a214, which reduced > the size of SIMD_OPRSZ_BITS, which lead to truncating all > predicate vector lengths. > > Changes in v2: > * Introduce and use PREDDESC field definitions, rather > than abusing a different SIMD_* macro. > > > r~ > > > Richard Henderson (4): > target/arm: Introduce PREDDESC field definitions > target/arm: Update PFIRST, PNEXT for pred_desc > target/arm: Update ZIP, UZP, TRN for pred_desc > target/arm: Update REV, PUNPK for pred_desc Reviewed-by: Peter Maydell and applied to target-arm.next. thanks -- PMM From MAILER-DAEMON Tue Jan 19 06:37:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1pJs-0007d8-4P for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 06:37:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1pJr-0007am-09 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:37:07 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:39598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1pJo-0000MO-9J for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:37:06 -0500 Received: by mail-ej1-x62d.google.com with SMTP id g3so8635530ejb.6 for ; Tue, 19 Jan 2021 03:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=R89qZj5UKCLtQgoFay4PetKhi2tpRwPy4aJiyPuN8UI=; b=rODQBQfyU92g4nEXx3/FeQe5C6h3SivE6wpovOZW3pfYjDdXVXNYCVXZUnLC1MgXho sNyMWC+RGmw34xp4RvYLQx2VYXdK8M6GTPzah2FbJlQbrllduP0VGxoFGkwXcLpKR2/s GVqnMQZ1wZV8aMlF5KCKMleNS7e4rl13hpb9xDTzlKjPLlPgkJ7cODIfDh7O/hBzkuQM R8RTxcBmYQiXEDvkBIi5o2gpFWZfo3TeW8dw/4WUqkeNreg5aUOBqjDV1gWLu2cddmee nsrcYtqWAJAjLIz9FZOUtg7WrLYLwe5Ac6xRzqybJ5WO6r/jjmGzx60oPvvkTmCY5Irf VO2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=R89qZj5UKCLtQgoFay4PetKhi2tpRwPy4aJiyPuN8UI=; b=g/oncfizRefzsiukbNx5NVXONdDUpWZ7mJLLtX44wUGiYwC790EFJe9IFy2bCDDGUn 3EcvGUJe0zo74B9e+tsgM+v8O1cCt5F31+Kq3UrUc7qxz6LDRoGF0mmxSEC0FIWjAoni HFCd7Vln6sCd25N7Ue40JVSfR6uZ5zUVUagCSY5n/jnqn3QWgRA19d9h1r+tVRWHOLQH +5Kug9L8WGCnjD0kD3EWmoyCzB/jgPaWX4tfe5w0AOZ5GxCTSzk6tQnqNNp3xdD4DbId MPzkf6N2mU5lZFEwE7jY2XUEJqYQA7znAQGuoLUYIDjwG81YQbbFCWyiSiLB9qss5RLn +kHA== X-Gm-Message-State: AOAM530Uu2ru3Eqn511O6fVQzWcqwBSw40faZa4L3vdi4E694G1AdE1q t+DghKcdN1yuzoZXB9+FGqSAPixQwuzbDtBM/4qToQ== X-Google-Smtp-Source: ABdhPJxXzkwNOKDCq1D8fzByB97q6/yqPjVxN7SdOqnc6ep6iGE8N28jNPD8HOZZWem4nnj8AfwosdX61vRlYnFswJM= X-Received: by 2002:a17:906:3603:: with SMTP id q3mr2611168ejb.382.1611056222378; Tue, 19 Jan 2021 03:37:02 -0800 (PST) MIME-Version: 1.0 References: <20210115101126.4259-1-maxim.uvarov@linaro.org> <20210115101126.4259-2-maxim.uvarov@linaro.org> In-Reply-To: <20210115101126.4259-2-maxim.uvarov@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 11:36:51 +0000 Message-ID: Subject: Re: [PATCHv7 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 11:37:07 -0000 On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote: > > Implement gpio-pwr driver to allow reboot and poweroff machine. > This is simple driver with just 2 gpios lines. Current use case > is to reboot and poweroff virt machine in secure mode. Secure > pl066 gpio chip is needed for that. > > Signed-off-by: Maxim Uvarov > Reviewed-by: Hao Wu > --- > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > 3 files changed, 74 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c > +/* > + * QEMU interface: > + * two named input GPIO lines: > + * 'reset' : when asserted, trigger system reset > + * 'shutdown' : when asserted, trigger system shutdown > + */ The comment says we perform the actions when the lines are asserted... > +static void gpio_pwr_reset(void *opaque, int n, int level) > +{ > + if (!level) { > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); > + } > +} > + > +static void gpio_pwr_shutdown(void *opaque, int n, int level) > +{ > + if (!level) { > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); > + } > +} ...but the code performs the actions when the lines are de-asserted, ie when they go to 0. I think the code should be "if (level)". thanks -- PMM From MAILER-DAEMON Tue Jan 19 06:39:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1pMG-0000Wo-Gg for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 06:39:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1pMF-0000V2-Ac for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:39:35 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:35981) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1pMD-0000hB-6L for qemu-arm@nongnu.org; Tue, 19 Jan 2021 06:39:35 -0500 Received: by mail-ed1-x52a.google.com with SMTP id b2so21097141edm.3 for ; Tue, 19 Jan 2021 03:39:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0rU4pgfuM1Krq+DVaJerzEogm45of/z5p4kmvRCy4cs=; b=v0VprRlf5rL21iDun2z2aptcr9xMlw8xlediz7aSoCwC7XknO02fZ/erqrHuTw8i6Y 9zKQKhzbSXDBtzt8TBM/wN/Exrdh75DIb+UawOt8Z31eBU5kgh9MLadA4+kzd0exsz2I dJw3BjBkikuvaMRDZK2PLpB/qb64STc8IlTIimc48nBwEd2Z7upU5NUXLEaYxVCnFubB ckk7wcdSPXcvOn/GmLznawMW10vW0KmwkPZlZ0oG2DfdURz8Fh31q8jeZNBgCnwWFOtJ 8rjg//UIcsmRmBmmDXYptYqqYzULgMecVVomSXh+jTFNgRBDTrmuAKKq8W98S99Id3uR 56hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0rU4pgfuM1Krq+DVaJerzEogm45of/z5p4kmvRCy4cs=; b=Eld6W+60Q8pzgsY8QFdN5SiRb4wAU+HUEjqblriGmq79gsbO6kj4K6FtgRqakqlBq1 xaqVwVm5H2+DB6dzaB+p7MIpiK2PDkm1y5KLjutKF7LgfT+U58fBD3RW9xXyedg03oFz a7cC0hqIX85DyktQ1nz9PqFBSqKSh4rDqA9IR4PPfO0If3RhJK8A3RLIqLOiK7p5hCyK e5Wz7vj8mMFJqT3be4rVQAPeLKjFnel5PXlhwocIVizuKRS6P9l7CwxADO00ohZ7017E dB9kJ/LuV9A1ZKagmRanaQ33ZVSJrvvmjbNg7Hk8qTtfgmLrwE2jPGqndbRJA8ij4fHG TWJg== X-Gm-Message-State: AOAM533HMRxaFykfzC27HtT2P93I7uYfm5I+rKMxXpAmJQ5+zIDfT/9e jnVtUDM7NDsACywSFGr+R6ly3rlinBRY3fieihmgjg== X-Google-Smtp-Source: ABdhPJxbbffUj92dQjMWQVzcplRIy5uNNHaYtMZ4vNpR5b8tKFMqS5VQOvbo7ZEe97z4gBbNc0s9Ggw5dbPyCPdmNjE= X-Received: by 2002:aa7:c88a:: with SMTP id p10mr3020986eds.204.1611056371462; Tue, 19 Jan 2021 03:39:31 -0800 (PST) MIME-Version: 1.0 References: <20210115101126.4259-1-maxim.uvarov@linaro.org> <20210115101126.4259-3-maxim.uvarov@linaro.org> In-Reply-To: <20210115101126.4259-3-maxim.uvarov@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 11:39:19 +0000 Message-ID: Subject: Re: [PATCHv7 2/3] arm-virt: refactor gpios creation To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 11:39:35 -0000 On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote: > > No functional change. Just refactor code to better > support secure and normal world gpios. > > Signed-off-by: Maxim Uvarov > --- > @@ -847,21 +873,22 @@ static void create_gpio(const VirtMachineState *vms) > qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); > qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); > > - gpio_key_dev = sysbus_create_simple("gpio-key", -1, > - qdev_get_gpio_in(pl061_dev, 3)); > - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); > - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); > + if (gpio == VIRT_GPIO) { > + qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); You don't want to set /chosen/stdout-path (that is specific to the uart, it's telling the kernel where it should send its bootup output by default). > + } else { > + /* Mark as not usable by the normal world */ > + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); > + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); > > - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); > - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", > - "label", "GPIO Key Poweroff"); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", > - KEY_POWER); > - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", > - "gpios", phandle, 3, 0); > + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", > + nodename); > + } Similarly here you don't want to set /secure-chosen/stdout-path. Patch looks OK otherwise. thanks -- PMM From MAILER-DAEMON Tue Jan 19 08:01:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1qdh-0006IX-Rp for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:01:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1qdZ-0006EX-0m; Tue, 19 Jan 2021 08:01:33 -0500 Received: from mail-lj1-x22c.google.com ([2a00:1450:4864:20::22c]:32802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1qdT-0005lm-9e; Tue, 19 Jan 2021 08:01:32 -0500 Received: by mail-lj1-x22c.google.com with SMTP id u21so21840279lja.0; Tue, 19 Jan 2021 05:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=WSyQL/wNaBrrrtKF4nXVrAQUnu57GKNMYm1rLmJTZuQ=; b=hkq9LTIMyztqmtCiOHDTSrRHgi0MPJavcstJEgDoCxh5aGimzJi5jwNFOl1eyFT8cY Mn9CzWeYaAcDLpcGN1zuXO6Zeh+QMHIKlfYBmN/2PFN81cd3LU3fo6YjYqnESwgp49FV c/bN3W2+6cAA+VQtOvgL/SvJi1Un/uFV666JuaXnjEuBpILSlNc6+erexjWsQHFzg73d EvB12kyxzJ+DvcUYkZVVRaEdcsJE3t7h9LbJu3R0PpSxilSy7XFYKYHICfELVRJ9sDnn ici7U0NAVMnqoBqdZao71ZdRJOZMY6Pa8pW24mnJwXEtcXnDuKt4g+Ic5cpbOa7enRGL NYuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=WSyQL/wNaBrrrtKF4nXVrAQUnu57GKNMYm1rLmJTZuQ=; b=HKQ6G9TpqUZlouek/MMnd3iLeMYMFYNunFUgwGkFF9sqJ/Onc/tu+KWr2/Bf/iWaAf 8+4MvGdex9XabmFZvlRe1pUuLojqXKjkLNf3S1p73+thOT5Doo/La4DANZfTmmYeCoAR kNDj86q5c6ovkCjXBpu97v7XpJnDrhqkLe6zMqxTzEnWrLJQxWuHsWGGrmIb6cW5Q2Ft xeputjOQiOkfiTSLSadkMTyhFmcHmmdvmrz8Elol9Ahf4GLqNQ5E7WIN9f0E2Uxiqc3N jIkohc3mx2VXEuN7AEkhrdQlf1U/510lpgkVbkK1e5Esnph69xC9HlkQ2sDL6FLVkXIn Q4iQ== X-Gm-Message-State: AOAM532f3k3TIYab8ic4RI6iN7RFTjqtKdnxJBOJQSzNC3dRYvwL6UU1 iPoOO9CO/veXM0Z0ufJIK2Y= X-Google-Smtp-Source: ABdhPJwIOuGiF3oXzYrndAuPIBh7H58tGMJ/KXDMfNRDZXnomDOGhUJObOTspI7Ceugwdu2O6waV9Q== X-Received: by 2002:a05:651c:217:: with SMTP id y23mr1793725ljn.247.1611061277508; Tue, 19 Jan 2021 05:01:17 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id u16sm2282299lfr.288.2021.01.19.05.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 05:01:16 -0800 (PST) Date: Tue, 19 Jan 2021 14:01:14 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210119130113.GA28306@fralle-msi> References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=frasse.iglesias@gmail.com; helo=mail-lj1-x22c.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:01:33 -0000 Hi Bin, On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > Hi Francisco, > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > wrote: > > > > Hi Bin, > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > Hi Francisco, > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > wrote: > > > > > > > > Hi Bin, > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > Hi Francisco, > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > wrote: > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > From: Bin Meng > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > > > > bytes are expected to be received after it receives a command. For > > > > > > > example, depending on the address mode, either 3-byte address or > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > > > > sending the address bytes, and the dummy cycles need to be counted > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > > > > It is not in bit, or cycle. However for some reason the model has > > > > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > > > > approach is to convert the number of dummy cycles to bytes based on > > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > > > > > > > While not being the original implementor I must assume that above solution was > > > > > > considered but not chosen by the developers due to it is inaccuracy (it > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > > > > also because the detail is already in use for catching exactly above error. > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed solution here > > > > > was ever considered, otherwise all SPI controller models supporting > > > > > software generation should have been found out seriously broken long > > > > > time ago! > > > > > > > > > > > > The controllers you are referring to might lack support for commands requiring > > > > dummy clock cycles but I really hope they work with the other commands? If so I > > > > > > I am not sure why you view dummy clock cycles as something special > > > that needs some special support from the SPI controller. For the case > > > 1 controller, it's nothing special from the controller perspective, > > > just like sending out a command, or address bytes, or data. The > > > controller just shifts data bit by bit from its tx fifo and that's it. > > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > > sent via a regular data (the case 1 controller) in the tx fifo, or > > > automatically generated (case 2 controller) by the hardware. > > > > Ok, I'll try to explain my view point a little differently. For that we also > > need to keep in mind that QEMU models HW, and any binary that runs on a HW > > board supported in QEMU should ideally run on that board inside QEMU aswell > > (this can be a bare metal application equaly well as a modified u-boot/Linux > > using SPI commands with a non multiple of 8 number of dummy clock cycles). > > > > Once functionality has been introduced into QEMU it is not easy to know which > > intentional or untentional features provided by the functionality are being > > used by users. One of the (perhaps not well known) features I'm aware of that > > is in use and is provided by the accurate dummy clock cycle modeling inside > > m25p80 is the be ability to test drivers accurately regarding the dummy clock > > cycles (even when using commands with a non-multiple of 8 number of dummy clock > > cycles), but there might be others aswell. So by removing this functionality > > above use case will brake, this since those test will not be reliable. > > Furthermore, since users tend to be creative it is not possible to know if > > there are other use cases that will be affected. This means that in case [1] > > needs to be followed the safe path is to add functionality instead of removing. > > Luckily it also easier in this case, see below. > > I understand there might be users other than U-Boot/Linux that use an > odd number of dummy bits (not multiple of 8). If your concern was > about model behavior changes, sure I can update > qemu/docs/system/deprecated.rst to mention that some flashes in the > m25p80 model now implement dummy cycles as bytes. Yes, something like that. My concern is that since this functionality has been in tree for while, users have found known or unknown features that got introduced by it. By removing the functionality (and the known/uknown features) we are riscing to brake our user's use cases (currently I'm aware of one feature/use case but it is not unlikely that there are more). [1] states that "In general features are intended to be supported indefinitely once introduced into QEMU", to me that makes very much sense because the opposite would mean that we were not reliable. So in case [1] needs to be honored it looks to be safer to add functionality instead of removing (and riscing the removal of use cases/features). Luckily I still believe in this case that it will be easier to go forward (even if I also agree on what you are saying below about what I proposed). > > > > > > > > don't think it is fair to call them 'seriously broken' (and else we should > > > > probably let the maintainers know about it). Most likely the lack of support > > > > > > I called it "seriously broken" because current implementation only > > > considered one type of SPI controllers while completely ignoring the > > > other type. > > > > If we change view and see this from the perspective of m25p80, it models the > > commands a certain way and provides an API that the SPI controllers need to > > implement for interacting with it. It is true that there are SPI controllers > > referred to above that do not support the portion of that API that corresponds > > to commands with dummy clock cycles, but I don't think it is true that this is > > broken since there is also one SPI controller that has a working implementation > > of m25p80's full API also when transfering through a tx fifo (use case 1). But > > as mentioned above, by doing a minor extension and improvement to m25p80's API > > and allow for toggling the accuracy from dummy clock cycles to dummy bytes [1] > > will still be honored as in the same time making it possible to have full > > support for the API in the SPI controllers that currently do not (please reread > > the proposal in my previous reply that attempts to do this). I myself see this > > as win/win situation, also because no controller should need modifications. > > > > I am afraid your proposal does not work. Your proposed new device > property 'model_dummy_bytes' to select to convert the accurate dummy > clock cycle count to dummy bytes inside m25p80, is hard to justify as > a property to the flash itself, as the behavior is tightly coupled to > how the SPI controller works. I agree on above. I decided though that instead of posting sample code in here I'll post an RFC with hopefully an improved proposal. I'll cc you. About below, Xilinx ZynqMP GQSPI should not need any modication in a first step. > > Please take a look at the Xilinx GQSPI controller, which supports both > use cases, that the dummy cycles can be transferred via tx fifo, or > generated by the controller automatically. Please read the example > given in: > > table 24‐22, an example of Generic FIFO Contents for Quad I/O Read > Command (EBh) > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > If you choose to set the m25p80 device property 'model_dummy_bytes' to > true when working with the Xilinx GQSPI controller, you are bound to > only allow guest software to use tx fifo to transfer the dummy cycles, > and this is wrong. > > > > > > > > > > for the commands is because no request has been made for them. Also there is > > > > one controller that has support. > > > > > > Definitely it's not "no request". Nearly all SPI flashes support the > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > > > "seriously broken" for those case 1 type controllers because they > > > cannot read anything from the m25p80 model at all. Unless the guest > > > software being tested only uses Read (03h) command which is not > > > affected. But I can't find a software that uses Read instead of Fast > > > Read. > > > > > > > > The issue you pointed out that we require the total number of dummy > > > > > bits should be multiple of 8 is true, that's why I added the > > > > > unimplemented log message in this series (patch 2/3/4) to warn users > > > > > if this expectation is not met. However this will not cause any issue > > > > > when running U-Boot or Linux, because both spi-nor drivers expect the > > > > > same assumption as we do here. > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > > > > there is a logic to calculate the dummy bytes needed for fast read > > > > > command: > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > > > > > Note the default dummy cycles configuration for all flashes I have > > > > > looked into as of today, meets the multiple of 8 assumption. On some > > > > > flashes the dummy cycle number is configurable, and if it's been > > > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > > > the first place. > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > > > > For such case, driver will calculate the correct number of dummy > > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > > > > > > > Please send patches to explain this in detail how this is going to > > > > > work. I am open to all possible solutions. > > > > > > > > In that case I suggest that you instead try with a device property > > > > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > > > > count to dummy bytes inside m25p80. Below is an example on how to modify the > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > > > > > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > > > > can follow a similar pattern). This way the fifo mode will be able to work the > > > > way you desire while also keeping the current functionality intact. Suddenly > > > > removing functionality (features) will take users by surprise. > > > > > > I don't think we are removing any features. This is a fix to make the > > > model to be used by any SPI controllers. > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > assumption for the dummy bit, which is the default configuration for > > > all flashes I have looked into so far. Can you please comment what use > > > case you want to support? I requested a U-Boot/Linux kernel testing in > > > the previous SST thread [1] against Xilinx GQSPI but there was no > > > response. > > > > In [2] instructions on how to boot u-boot/Linux is found. For building the > > various software components I followed the official doc in [3]. > > I see the following QEMU commands are used to test booting U-Boot/Linux: > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m 4G > -serial stdio -display none -device loader,file=u-boot.elf -kernel > bl31.elf -device loader,addr=0x40000000,file=Image -device > loader,addr=0x2000000,file=system.dtb > > I am not sure where the system.dtb gets built from? It is the instructions in [2] to look into. 'system.dtb' is the kernel dtb for zcu102 ([2] has been fixed). I created [2] purely for you, so respectfully I will ask you to try a little first before asking for further guidance. Best regards, Francisco Iglesias [1] qemu/docs/system/deprecated.rst [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md > > In [3], it mentions the Xilinx QEMU is used. And a different QEMU > command is used as the example to launch U-Boot which is different > from your command above. > > See https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841606/QEMU+-+Zynq+UltraScale+MPSoC#QEMU-ZynqUltraScale+MPSoC-RunningaZynqUltraScale+U-bootImageOnXilinx'sARMQEMU > > $ ./aarch64-softmmu/qemu-system-aarch64 -M arm-generic-fdt -serial > mon:stdio -serial /dev/null -display none \ > -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 \ # Un-reset the A53 > -device loader,file=./pre-built/linux/images/bl31.elf,cpu-num=0 \ # > ARM Trusted Firmware > -device loader,file=./pre-built/linux/images/u-boot.elf\ # The > u-boot exectuable > -hw-dtb ./pre-built/linux/images/zynqmp-qemu-arm.dtb # HW Device > Tree that QEMU uses to generate the model > > It is using a machine called "arm-generic-fdt", but in the mainline > QEMU there is no such machine called "arm-generic-fdt". > > > > > Best regards, > > Francisco > > > > [1] qemu/docs/system/deprecated.rst > > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md > > [3] https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/460653138/Xilinx+Open+Source+Linux > > > > Regards, > Bin From MAILER-DAEMON Tue Jan 19 08:08:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1qju-0002KU-UA for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:08:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1qjm-0002JS-SC for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:07:59 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:32790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1qjk-0006ns-Po for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:07:58 -0500 Received: by mail-ed1-x531.google.com with SMTP id c6so14298195ede.0 for ; Tue, 19 Jan 2021 05:07:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5bXiHWkDHuGNqPxK6b0dfBoHjyPw7FWQ4FviaJl/KSw=; b=POmsJaS596r11EIb9KM3Bv7X38itEd52XRgTByy3L8I9G9io0QwT9L8azr356E8wOt lLIO+cWSWZOYnZGuX4jzpjb4ym3NcUa2UPTw7u/vHH7CE2QClzQpHtyHIK691JMA7VkW tNQZCX7mlKkXXz9dR5DQCf1xXZpP4pIN9z6sgfLS0VksV3GAZGKgXjYFWsrrmyjk8ibZ aQcsBt6yecwe8S8liWXcDPvVYMJLnLp4fkkbpcdmArWuGeBDkN9is7eMyvoMRcZR2572 KNiF7cfv0kNYVuAdZQHr79Ybaqs4thbdxxXbnm7x3Ky29YLarRGJeZ1uWMuDDrRyqNpQ r69g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5bXiHWkDHuGNqPxK6b0dfBoHjyPw7FWQ4FviaJl/KSw=; b=b92km94BScHFGXz3LXNW7BSIiEQ7H13u2fldeZLm+ktE/8qQaKXGpvuEalPLN/5ffy GvVARdQg7OQoeStRYrF3V6HNN5FxD26BBRGYdT9PJcShDfbPuRFVpKV/CWveg2PmTKqZ 97zXeX6FjPz1oGnX2lyBilsqgCy/X0gdkTYug+VwCax2wmDrtysXjrXgpWzs9CTwMmN/ r/mkxz4oVe32jQl/DdwUBMSy00h3VFjQG7tWi1IRWS1jXDLuObA42W/awwfHSe078iZk KO+o3VQ/pXcDsBajriQ2BXTuLLDs3zqw/gv3064EIWEGOcv1CCGQWG8fNNFI6KRgbt94 5gug== X-Gm-Message-State: AOAM532mZD+knJ8UIS2zTcOkuKO3TfNQykt3NwD7CXQsvGfjCEhqW0AV TPfv1dwODZm6c08qbTLMpk24DnToo/3FjmRiW/HmIQ== X-Google-Smtp-Source: ABdhPJxLuC02nEALG4gyQqDuIwYX5RyLQfDpoHs4Yx9QCZUn9PXitiMc5uvXSPri+o9YGErC4fq9jTsDhGxNC3tENEI= X-Received: by 2002:a50:9ee3:: with SMTP id a90mr3338287edf.44.1611061675047; Tue, 19 Jan 2021 05:07:55 -0800 (PST) MIME-Version: 1.0 References: <20210115101126.4259-1-maxim.uvarov@linaro.org> <20210115101126.4259-4-maxim.uvarov@linaro.org> In-Reply-To: <20210115101126.4259-4-maxim.uvarov@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 13:07:43 +0000 Message-ID: Subject: Re: [PATCHv7 3/3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:07:59 -0000 On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). Connect it > with gpio-pwr driver. > > Signed-off-by: Maxim Uvarov > --- > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++++++++++++ > include/hw/arm/virt.h | 2 ++ > 3 files changed, 53 insertions(+) > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 0a242e4c5d..13cc42dcc8 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -17,6 +17,7 @@ config ARM_VIRT > select PL011 # UART > select PL031 # RTC > select PL061 # GPIO > + select GPIO_PWR > select PLATFORM_BUS > select SMBIOS > select VIRTIO_MMIO > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 26bb66e8e1..436ae894c9 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { > [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, > [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, > [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, > + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ > [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, > @@ -841,6 +842,46 @@ static void create_gpio_keys(const VirtMachineState *vms, > "gpios", phandle, 3, 0); > } > > +#define ATF_GPIO_POWEROFF 3 > +#define ATF_GPIO_REBOOT 4 These aren't ATF specific, so you could name them SECURE_GPIO_POWEROFF and SECURE_GPIO_REBOOT. Remind me why we start with GPIO line number 3 and not 0 ? > + > +static void create_gpio_pwr(const VirtMachineState *vms, > + DeviceState *pl061_dev, > + uint32_t phandle) > +{ > + DeviceState *gpio_pwr_dev; > + > + /* gpio-pwr */ > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); > + > + /* connect secure pl061 to gpio-pwr */ > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); You've connected the POWEROFF gpio line to 'reset' and the REBOOT line to 'shutdown'. This looks like it's backwards. > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", > + "label", "GPIO PWR Poweroff"); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", > + ATF_GPIO_POWEROFF); > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", > + "gpios", phandle, 3, 0); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", > + "label", "GPIO PWR Reboot"); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", > + ATF_GPIO_REBOOT); > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", > + "gpios", phandle, 3, 0); There doesn't seem to be any documented 'gpio-pwr' devicetree binding. Where does this come from ? I think the bindings you want to be using are https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-restart.txt https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt thanks -- PMM From MAILER-DAEMON Tue Jan 19 08:32:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1r7C-00066l-Hm for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:32:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1r7B-00064a-0c for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:32:09 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:44918) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1r71-00024b-Eb for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:32:03 -0500 Received: by mail-ed1-x536.google.com with SMTP id p22so21492474edu.11 for ; Tue, 19 Jan 2021 05:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=McwflRvpuADbnXsQ9z7Mrv30L7ZFQBot8rTULjaKimo=; b=USf/mlx3CGcedBgyRKICTXQ6tvEOV6QXlrBqpyLngQRk1GNQfUjzJsQ8KFjN80d2AT kAQ1WrpDEMa0NvhKOzMsWD3QqzFoOQbS4XVHUfj8U0rntsExDrPo8dtjTI1nv9idUhFr oJg/aLp6AYr1SD/At9s4CjS/BH/o5OZ21S7pLG9GYdofP6CP8znKUr0uFbLhSpLI7RJ6 HTCCgo+LSL86tAcT4AH9NLVi35YO18mcf4A1h+006QSLi12mqv2leNz9xbhwwFJqsgOh phs0pZ5Ny8LObVgll02NGSshx5mD6oNvcap9CH9k80Xi/hrjW0CPhj2yWScJL12UXjUb BBGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=McwflRvpuADbnXsQ9z7Mrv30L7ZFQBot8rTULjaKimo=; b=MZzYOtYeSYrUMR+ZJDDG8iF5kIW6wIDnr05OcE5W/d1xSNkczVhp7eLQXkBPQodTWI KPm/ezlnHLD2h00EvXl/dpqyjeQvLfrilPz3r2pk1c4qTsNVnWReRa+uq/MfSlJAFnB1 TiM0jberdmNKA5VOejltBUhLTaBOWtIQ0hMOqdAF9Jlp4kKQ2bfrvlVkVl1AQxp5xDMe E09em9LTdQccgUZPEuAb5FqZPtfs1pbCiebbZUAVj3pgLGTnpmFrDFBehzKsQ1KCRZIt yWr5QvnVADFkWlumkmMH3TmPtLJOEiak9fW7Gw2Ee++puyIQuoSuCJYququAFxtIr3aE SypA== X-Gm-Message-State: AOAM532AEpTLenjXxGWXKM732U77qggOv6nOlAqZ5AUCJlCSw/Gdq49d Y23XLGKle57CTso/ZEE5XGYThUjBObilFNwd3JrcJw== X-Google-Smtp-Source: ABdhPJwriV63C4zMDCHY2VB2pxNB0i0ALoC1tPbJt9xhp3SS7pugo7GNhaTnqivXArYlKCfJoa5nkGAyNkpN2JcO3tQ= X-Received: by 2002:a05:6402:1a55:: with SMTP id bf21mr3530164edb.146.1611063116121; Tue, 19 Jan 2021 05:31:56 -0800 (PST) MIME-Version: 1.0 References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-3-f4bug@amsat.org> In-Reply-To: <20210117192446.23753-3-f4bug@amsat.org> From: Peter Maydell Date: Tue, 19 Jan 2021 13:31:44 +0000 Message-ID: Subject: Re: [RFC PATCH v2 02/20] hw/core/qdev: Add vmstate_qdev_no_state_to_migrate To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "Dr. David Alan Gilbert" , QEMU Developers , Mark Cave-Ayland , qemu-arm , Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:32:09 -0000 On Sun, 17 Jan 2021 at 19:25, Philippe Mathieu-Daud=C3=A9 = wrote: > > Add vmstate_qdev_no_state_to_migrate, which is simply a > pointer to vmstate_no_state_to_migrate. This way all > qdev devices (including "hw/qdev-core.h") don't have to > include "migration/vmstate.h". > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Unresolved issues: > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg721695.html > Peter: > > Does this definitely not put any data into the migration stream? > > We don't want to change what's on the wire for machines that > > use devices that start using this. (If it does by default, it > > would be easy to make the migration code special case the > > magic symbol to act like "no vmsd specified"). > > https://www.mail-archive.com/qemu-devel@nongnu.org/msg727634.html > Dave: > > I'd need to test it to be sure, but I think if we added a .needed > > to vmstate_no_state_to_migrate with a function that always returned > > false, then I think the stream would stay unchanged. > --- It should be easy to test -- just do a 'savevm' of a running system with a machine model that uses one of the devices that has been marked as "no state to migrate", then apply the patchseries, and see if 'loadvm' works or not. thanks -- PMM From MAILER-DAEMON Tue Jan 19 08:39:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rDr-0001v4-CG for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:39:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rDm-0001tu-7B; Tue, 19 Jan 2021 08:38:59 -0500 Received: from mx2.suse.de ([195.135.220.15]:35792) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rDa-0003Eq-TD; Tue, 19 Jan 2021 08:38:50 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 24F35AB7F; Tue, 19 Jan 2021 13:38:43 +0000 (UTC) Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , peter.maydell@linaro.org Cc: Luis Machado , "open list:ARM TCG CPUs" , qemu-devel@nongnu.org References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> From: Claudio Fontana Message-ID: <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> Date: Tue, 19 Jan 2021 14:38:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210115130828.23968-22-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:39:00 -0000 Hi Alex, after updating to latest master today, I am getting the following error with make check-tcg qemu-system-aarch64: -gdb unix:path=/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEMU waiting for connection on: disconnected:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" warning: Could not load XML target description; ignoring qemu-system-aarch64: QEMU: Terminated via GDBstub Seems to indicate it is "ieee_half" -related? Thanks, Claudio On 1/15/21 2:08 PM, Alex Bennée wrote: > While GDB can work with any XML description given to it there is > special handling for SVE registers on the GDB side which makes the > users life a little better. The changes aren't that major and all the > registers save the $vg reported the same. All that changes is: > > - report org.gnu.gdb.aarch64.sve > - use gdb nomenclature for names and types > - minor re-ordering of the types to match reference > - re-enable ieee_half (as we know gdb supports it now) > - $vg is now a 64 bit int > - check $vN and $zN aliasing in test > > Signed-off-by: Alex Bennée > Reviewed-by: Luis Machado > Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> > > diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > index 866595b4f1..a8fff2a3d0 100644 > --- a/target/arm/gdbstub.c > +++ b/target/arm/gdbstub.c > @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { > { "uint128", 128, 'q', 'u' }, > { "int128", 128, 'q', 's' }, > /* 64 bit */ > + { "ieee_double", 64, 'd', 'f' }, > { "uint64", 64, 'd', 'u' }, > { "int64", 64, 'd', 's' }, > - { "ieee_double", 64, 'd', 'f' }, > /* 32 bit */ > + { "ieee_single", 32, 's', 'f' }, > { "uint32", 32, 's', 'u' }, > { "int32", 32, 's', 's' }, > - { "ieee_single", 32, 's', 'f' }, > /* 16 bit */ > + { "ieee_half", 16, 'h', 'f' }, > { "uint16", 16, 'h', 'u' }, > { "int16", 16, 'h', 's' }, > - /* > - * TODO: currently there is no reliable way of telling > - * if the remote gdb actually understands ieee_half so > - * we don't expose it in the target description for now. > - * { "ieee_half", 16, 'h', 'f' }, > - */ > /* bytes */ > { "uint8", 8, 'b', 'u' }, > { "int8", 8, 'b', 's' }, > @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > GString *s = g_string_new(NULL); > DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; > g_autoptr(GString) ts = g_string_new(""); > - int i, bits, reg_width = (cpu->sve_max_vq * 128); > + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); > info->num = 0; > g_string_printf(s, ""); > g_string_append_printf(s, ""); > - g_string_append_printf(s, ""); > + g_string_append_printf(s, ""); > > /* First define types and totals in a whole VL */ > for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > int count = reg_width / vec_lanes[i].size; > - g_string_printf(ts, "vq%d%c%c", count, > - vec_lanes[i].sz, vec_lanes[i].suffix); > + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); > g_string_append_printf(s, > "", > ts->str, vec_lanes[i].gdb_type, count); > @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > * signed and potentially float versions of each size from 128 to > * 8 bits. > */ > - for (bits = 128; bits >= 8; bits /= 2) { > - int count = reg_width / bits; > - g_string_append_printf(s, "", count); > - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > - if (vec_lanes[i].size == bits) { > - g_string_append_printf(s, "", > - vec_lanes[i].suffix, > - count, > - vec_lanes[i].sz, vec_lanes[i].suffix); > + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { > + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; > + g_string_append_printf(s, "", suf[i]); > + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { > + if (vec_lanes[j].size == bits) { > + g_string_append_printf(s, "", > + vec_lanes[j].suffix, > + vec_lanes[j].sz, vec_lanes[j].suffix); > } > } > g_string_append(s, ""); > } > /* And now the final union of unions */ > - g_string_append(s, ""); > - for (bits = 128; bits >= 8; bits /= 2) { > - int count = reg_width / bits; > - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { > - if (vec_lanes[i].size == bits) { > - g_string_append_printf(s, "", > - vec_lanes[i].sz, count); > - break; > - } > - } > + g_string_append(s, ""); > + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { > + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; > + g_string_append_printf(s, "", > + suf[i], suf[i]); > } > g_string_append(s, ""); > > + /* Finally the sve prefix type */ > + g_string_append_printf(s, > + "", > + reg_width / 8); > + > /* Then define each register in parts for each vq */ > for (i = 0; i < 32; i++) { > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"vq\"/>", > + " regnum=\"%d\" type=\"svev\"/>", > i, reg_width, base_reg++); > info->num++; > } > @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) > " regnum=\"%d\" group=\"float\"" > " type=\"int\"/>", base_reg++); > info->num += 2; > - /* > - * Predicate registers aren't so big they are worth splitting up > - * but we do need to define a type to hold the array of quad > - * references. > - */ > - g_string_append_printf(s, > - "", > - cpu->sve_max_vq); > + > for (i = 0; i < 16; i++) { > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"vqp\"/>", > + " regnum=\"%d\" type=\"svep\"/>", > i, cpu->sve_max_vq * 16, base_reg++); > info->num++; > } > g_string_append_printf(s, > " " regnum=\"%d\" group=\"vector\"" > - " type=\"vqp\"/>", > + " type=\"svep\"/>", > cpu->sve_max_vq * 16, base_reg++); > g_string_append_printf(s, > " - " regnum=\"%d\" group=\"vector\"" > - " type=\"uint32\"/>", > + " regnum=\"%d\" type=\"int\"/>", > base_reg++); > info->num += 2; > g_string_append_printf(s, ""); > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 5ab3f5ace3..8a492465d6 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) > * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. > */ > int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; > - return gdb_get_reg32(buf, vq * 2); > + return gdb_get_reg64(buf, vq * 2); > } > default: > /* gdbstub asked for something out our range */ > diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > index 972cf73c31..b9ef169c1a 100644 > --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): > except gdb.error: > report(False, "checking zregs (out of range)") > > + # Check the aliased V registers are set and GDB has correctly > + # created them for us having recognised and handled SVE. > + try: > + for i in range(0, 16): > + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) > + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) > + report(int(val_z) == int(val_v), > + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) > + except gdb.error: > + report(False, "checking vregs (out of range)") > + > > def run_test(): > "Run through the tests one by one" > From MAILER-DAEMON Tue Jan 19 08:40:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rF6-0002hd-2j for mharc-qemu-arm@gnu.org; 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[147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:12 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Tue, 19 Jan 2021 21:38:56 +0800 Message-Id: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:17 -0000 From: Bin Meng This v8 series is based on the following 2 versions: - v5 series sent from Bin http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 - v7 series sent from Philippe http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - remove imx_spi_update_irq() in imx_spi_reset() - chip select signal was not lower down when spi controller is disabled - round up the tx burst length to be multiple of 8 - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect - remove pointless variable (s->burst_length) initialization (Philippe) - rework imx_spi_reset() to keep CONREG register value (Philippe) - rework imx_spi_read() to handle block disabled (Philippe) - rework imx_spi_write() to handle block disabled (Philippe) Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value - new patch: [RFC] rework imx_spi_read() to handle block disabled - new patch: [RFC] rework imx_spi_write() to handle block disabled Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() - round up the burst length to be multiple of 8 Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé (4): hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 +- hw/ssi/imx_spi.c | 138 +++++++++++++++++++++++++++++------------------ 2 files changed, 90 insertions(+), 53 deletions(-) -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rF7-0002lH-Qe for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rF5-0002gN-7J; Tue, 19 Jan 2021 08:40:19 -0500 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]:43474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rF3-0003Su-JL; Tue, 19 Jan 2021 08:40:18 -0500 Received: by mail-io1-xd2c.google.com with SMTP id x21so21350905iog.10; Tue, 19 Jan 2021 05:40:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G3I8+jePmJbFvmYMVYrWYUHgNMI7m5yuQVcYxqGZCyU=; b=HnS4XdwrzV4g53pMU850oQhmX3spg+kN7aJ2YbaZ0wwAgogbdZxDd86iGLFHSMWiq2 jIYzS0e9y048z7Of7Fp+yVezpQabm10ban2pBaKYg7umGaQv473x2m39fQioRlyCEIhe W5f75innhHlfRZbL7BWyZvEVsIaTsbOxp+h2d8k+JKixBtiZjxaoQk9Yh2WX+aHND8p0 eTYMlAmOlvqQciTQPIHWAiQgmH0Ja3hh19hS4wRqovhBVdLgR1QkT4QR7qtUkqvfirKw KcaNH3twFDJ3SJ/2jtfpV86xDV4WOBqB4U0/2MFdUjQvch2VrxKDUMulNQnEwJWaXsyQ SKvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G3I8+jePmJbFvmYMVYrWYUHgNMI7m5yuQVcYxqGZCyU=; b=VDI3U7X/xq/Z+Na5FaNtIXO6qcY1ksVOv1Hs6TjYnBSMpxHHMdbOgROa9+r6TmZwuZ 8AG4JJ2HKBcVUYztlvYuzKHPkGVESeVSoy8sS+ZIah4UVFMLMe6O0XkijcMEA23IXXo0 8QbIO5guzjRSeABoIeaJncMtlPbXKLgrIa9jOfe4afsBvuX90s0QdoCluyWldMmh3UgB Ymb+M+ZBe57GVGDl+717M2N4fSV3YSdKxZbTXuOwHQADT16QcV3yido6KQ1HNVy3Upax fhL0cKpRbzPtHuFPFU1dyxr0Stthatad/6Qf/ZkYjDv2dauKtG8ZqRdaSDfYMYFZoFAe 3S6g== X-Gm-Message-State: AOAM530rQKkAYrZrimRahlr8woOF1wg7+hdGi3S+lN00R/PveDFwSWwf 6Hlr5uE1vpfypZ4XnV8pAloKoS+Xl2E= X-Google-Smtp-Source: ABdhPJyoFEgoBH4UhLmH97vpcQIXS80OA+fsxfLeutpZp7z5NM916/cKdBXS77qtcTDKjfiv10bj0A== X-Received: by 2002:a05:6e02:cb:: with SMTP id r11mr3500211ilq.116.1611063616267; Tue, 19 Jan 2021 05:40:16 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.13 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:15 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Tue, 19 Jan 2021 21:38:57 +0800 Message-Id: <1611063546-20278-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:19 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f..eeaf49b 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae..e605049 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFM-0002ql-N4 for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rF8-0002m5-Ai; Tue, 19 Jan 2021 08:40:25 -0500 Received: from mail-io1-xd2a.google.com ([2607:f8b0:4864:20::d2a]:40574) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rF6-0003TX-Kc; Tue, 19 Jan 2021 08:40:22 -0500 Received: by mail-io1-xd2a.google.com with SMTP id n2so22376589iom.7; Tue, 19 Jan 2021 05:40:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CwVyKj0nLazpAlMHIq5E4YX2HLtnW6e2Pi2ImRJMI34=; b=ZArDqVFUHgXs7fESjXtQHhu/ckVThhSTT7nyAI/3j+djLcsETDnNhF6tBQb+ndSYYQ ZTWfa9RVP9kzLS+EM9s55P6Zfop+rvA5AXlrf8dTZahWZsKjXCQUzy0zp6klYqJ83jD+ sCiRopyjfB5Mn2tXf/6lla8T/8ZgbdHJ73lD3VusnUzgY8hd5JpOBxB+6jw+pG2zvJ0P nPELOth0epns+G95tsmn0Mt5/YMz4QpnTf9HyLVsv2zBpW1EmhQwrpq+bvruapguabMK fgwp5ljzUfBYJaSr/4qMFnT87rhR6R172ZTR8jcAyrHH+OoK5/Ls8Pr1O5QFYHoRSgfO K6fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CwVyKj0nLazpAlMHIq5E4YX2HLtnW6e2Pi2ImRJMI34=; b=HfWucHryNEu9wLJ7zPxyKH+oWIpM2+v0QJarkQU6NAsK+8JkDFS8UvvpeXgblhVvW5 +SWB8SDNF85jLu9xhDcifI5P+vGy/+6wgV84GCZ60B9zSKm3b+RlolADuGflvIPa6HTZ yuld5oG0q4Luww7JPFdcesvC0OeJ/icVukEQpQ3ocmNXbk5Aa8obQEQfytCZ2x8uQyia zyoFaeDHeV2cXuVDR0gsGCHJa415E9iERLle3GyYiyMAOpoZEX6etqoP7KJkoLJuzccs xYjagCEzvZ6zj2YV11bcTjyq7HvNQH6l6itYKSX8yrDsdT74YX+CtfTz/xRAMe+ybvHR EAnA== X-Gm-Message-State: AOAM532ZYYroF6WiWV2MUOSJIksfbp5Y0hCevsvk0SVsgZXGeJ2ZV4p5 6hlG+AAY1yDLUNFvBCD2OceEzAftBBA= X-Google-Smtp-Source: ABdhPJxgHn6q9c7lcmA4lyuWlxeyqCYE8qLfq6IxpXG9jWZvKtHyAS/czLgsE2qWKVkx2MSlMKe+8Q== X-Received: by 2002:a05:6e02:12cc:: with SMTP id i12mr3341876ilm.113.1611063619499; Tue, 19 Jan 2021 05:40:19 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:19 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Tue, 19 Jan 2021 21:38:58 +0800 Message-Id: <1611063546-20278-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::d2a; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:34 -0000 From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng --- (no changes since v5) Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049..4d488b1 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); - imx_spi_update_irq(s); - s->burst_length = 0; } +static void imx_spi_soft_reset(IMXSPIState *s) +{ + imx_spi_reset(DEVICE(s)); + + imx_spi_update_irq(s); +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); + return; } -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFO-0002uZ-1l for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFL-0002oZ-Ne; Tue, 19 Jan 2021 08:40:35 -0500 Received: from mail-io1-xd35.google.com ([2607:f8b0:4864:20::d35]:34361) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFA-0003Tx-FX; Tue, 19 Jan 2021 08:40:34 -0500 Received: by mail-io1-xd35.google.com with SMTP id u17so39613917iow.1; Tue, 19 Jan 2021 05:40:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SqWEsFEvcxyZ/X/Aq4mkUc4tlPZsiwZEYgKXZtCqeJg=; b=b13vNqwbiITGojMPjalYj7p5TXbJzDXWRobt3chF4FAMobgWd+7hysyKE5bmTt2SsR p0d7ubP947Fj4h6i7P1nfkr6kV4SpuXvOv6FRlcAWIHwcwlWpidYSfJ4okpMxrWunYbI gRM9pZx5kc/gB0pbSeT6k0SHr8LwxMy8Iid982G4nsuKWPq4Sg34IUmOb0pFhGMNsxwo 0btLkMi64HOcttk87QfiDGvIpx1Gj7OuBP2yKhTR6fCeJQ/gHYvSW4zIXctdtthFE1om AUGMMw7j6vecfpKc57cTplNTO20QebZWL/9CpUVvmoMix48OyBSy14C6yQYAULokpysD y/ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SqWEsFEvcxyZ/X/Aq4mkUc4tlPZsiwZEYgKXZtCqeJg=; b=uWSpV1MP8SYMsBxfNMZ3Wmxi698q5TXfDrYU9gyV8K1CIC7a/EV1Dub0yRohuxwqIy vou97H4tHm9bUNUR2bbWcpe7VThWQF6mq5Dg9An2gcVGFhSMVGyL4FlLpeJjvevRKXC0 lqnOX0teyMa3ZmrHBqFDTIkqrjbu68ePvDaqZyqMgkaEaLClBG0B08EQf7N/H5THdLlM pllY7gNsGo+kpFL1I54X0C8TA7nYsSWThaP4k8Czruniw0cYI6boy6uF2oHaua+w7B6z 5mmLbrc/4ugeA6qeifQAD1aVLNVRvxvB8lbCIKHhpiUE/37b55zvD0To9RVnObpZW/bI 6YSA== X-Gm-Message-State: AOAM531RjcCNFwd5rOXgBDQ0AkSxIIocf3XEPsDXfksQ9xONbEWwuZNA XX01YILm0NWNqGuEdrhGVvlt8+rYwTM= X-Google-Smtp-Source: ABdhPJyW0inTJWFNQU99JrrU7FRDlpqmBhYSyKlcclHPYQ6h532bgxehqxh2M6sdMH1rrLX2C2LULQ== X-Received: by 2002:a05:6602:122b:: with SMTP id z11mr2914194iot.210.1611063622638; Tue, 19 Jan 2021 05:40:22 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:22 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Date: Tue, 19 Jan 2021 21:38:59 +0800 Message-Id: <1611063546-20278-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d35; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:36 -0000 From: Philippe Mathieu-Daudé 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-3-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4d488b1..8fb3c9b 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -434,8 +434,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFP-0002zq-IX for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFM-0002pL-2w; Tue, 19 Jan 2021 08:40:36 -0500 Received: from mail-io1-xd2b.google.com ([2607:f8b0:4864:20::d2b]:39139) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFF-0003U4-Tt; Tue, 19 Jan 2021 08:40:35 -0500 Received: by mail-io1-xd2b.google.com with SMTP id e22so15849710iog.6; Tue, 19 Jan 2021 05:40:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7gJngOH1B/sa/seE8Ljjvfh+JI+wjQtzMvApotHkWzA=; b=gh0yZC5b31mmFR6ZbDoxeaQWRnsnVHl/5YhCEw0XxFurBwazGUC7Ad/1DxWdGfC+K4 +uJVIXLFnYKEZfvieqIUuxVPmcT00wuic1axAy3K+tkn8+OWIiZVddzl2YeWBPdeAp1o dJn06QYV1SDk4Ji2pMNIDaJ0B0vQoBaBDVWHzV5uiuxFYsNywLd9s/X869gsNpYIaWBe XpSdQJR1ZEk/Lt95zNp2J/otmxT3ZqCBaMVYfm0kQ19Zmy48IEWI0sFRJ7TVHrY7hqMX O/Cz3WvqF1pEVHd7uE8f/p045AvlBbni5auxMlpygUhaVMek7r82n3bxRdhhp/8POoOs mkHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7gJngOH1B/sa/seE8Ljjvfh+JI+wjQtzMvApotHkWzA=; b=n6hq4of13iAdaDprwmrqblLpr134gg7iwkRP06dontpHxDzgIKhh5NvvwX9Kkj65R0 sg2M/NyTrxmE6rjF/45mepYBww6eYKbwsNV+qF9QxJJuqHbQEWQQJo64rG+40PWDNFas fvq2Q5pefvxcU37zXYCQUc2u0ZA0+dvdiEEABF3MEZmPKTf0smfI62QOm1zu8djQoDsU vFrJ2ffgjZV38RqqxORJXGPd1CRJImS7bDPEovYsMooFzK2Fr+g633Q1N/imgSz+cNOe bTPUEcHAwQZIue4YD8VpW9x7jrGPEm3N9T6rolwvKFz+yJjLXcV7wsKfXS1BdPV5EMdQ FttA== X-Gm-Message-State: AOAM532QuE4HkXIf0/4jfpY2VaAh/882s7ZiXlt2zmIbuzANwHPhJGcn FBFyO9028+9cO2NK3Pc0Zuc= X-Google-Smtp-Source: ABdhPJwCobkDcMIiOGUvGdNg0s9mDHusTq5KQDx2BF2M2l8P9u1Qq2alcQjinWT6E6NLDEgOm5YHmg== X-Received: by 2002:a05:6e02:1a6d:: with SMTP id w13mr3567279ilv.181.1611063625865; Tue, 19 Jan 2021 05:40:25 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:25 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Tue, 19 Jan 2021 21:39:00 +0800 Message-Id: <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:36 -0000 From: Philippe Mathieu-Daudé When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-4-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value hw/ssi/imx_spi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8fb3c9b..c952a3d 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); + int i; DPRINTF("\n"); - memset(s->regs, 0, sizeof(s->regs)); - - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFT-00030z-PB for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFN-0002sm-GG; Tue, 19 Jan 2021 08:40:37 -0500 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]:34354) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFJ-0003UA-Su; Tue, 19 Jan 2021 08:40:37 -0500 Received: by mail-io1-xd2c.google.com with SMTP id u17so39614773iow.1; Tue, 19 Jan 2021 05:40:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZGjLBdXEirecxcEY2UAZYu8cwlhOHSgOGxMxIwxYN+o=; b=I+nBbn2pBdNV20+c7iLT5QKyk9DcstTflI66BrJW0TQzTPjFNOgz3T2xj/SxRjgtiS ERGtvNBXByMSK9hm4QvnerPTJhHabFLb9c0Y02iMJn2UUbJug1n3XbBkfHg6uvtrIo56 GyISSr6WuHzuLmHPnN7RhePEhP2gAx5iBfydKslI/5uWFyPC2xSz29TaJghNJk/vDKxH MUTKTkKKZAmR0JOMeiGPwAsjHbf7i+VPoXpVWW/dgg3KqpotlCP8u/01g0SyfOB113la bihCwfZDrAU2uTgNFDDKQmRUc4rRYwd7pCiJVj/05QC9cHOxddG/NaSXm+7NaPIX7sZ7 g9Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZGjLBdXEirecxcEY2UAZYu8cwlhOHSgOGxMxIwxYN+o=; b=WOu3dHyGMk4EfVw9Bn9TRYa8PDwc5kkOrORF37u/J1I0y5Tx96QqsKTmZdu56XV8/n O2xaK6Prqnsjsq6O4lqjRfDakdVJdAdTtHUb80xmdXJq6MXFpgrM2piIg+JGZo6JyEWB 4XLdTQs87Y1iD9Xe17OwPxbA8SmHbOu8rTFmDUGfeV8ngV5H4FR5V1J6YcmyMjiikmhm UbCADj3uixaOZLLzR6ULDMbNO9m+rKW8CxcCV/FTkmTzY7DQGSo/LGzTE36zSenLwJyr TFndJzejo2f+J8utz2waGEivAdqtax9Ki9YoiGPEb7TUNR78KgSDp3iCmvrK/lUdNNsS 05bA== X-Gm-Message-State: AOAM530V394VC2S3j63gfGOSrm5lJ26E1sMvW74NznG0g9Xfsmjoxrrg FALAYE0iu6Wo1ID4GIiIDUY= X-Google-Smtp-Source: ABdhPJyd8lOM0UDQNwS3gbS3zs8S3gSmmW/8arGBf7ubWzwiaSqizg2ZmV4s7toBOKA2L0oJaIyCfA== X-Received: by 2002:a02:b78e:: with SMTP id f14mr3376535jam.97.1611063629205; Tue, 19 Jan 2021 05:40:29 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.26 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:28 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Tue, 19 Jan 2021 21:39:01 +0800 Message-Id: <1611063546-20278-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:38 -0000 From: Philippe Mathieu-Daudé When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_read() to handle block disabled hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++++++----------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index c952a3d..277b936 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -274,42 +274,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); - } - - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); - /* Reading from MSGDATA gives 0 */ + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; + } - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFV-00034i-CW for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFO-0002xo-Sk; Tue, 19 Jan 2021 08:40:38 -0500 Received: from mail-io1-xd2f.google.com ([2607:f8b0:4864:20::d2f]:36958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFN-0003VG-7S; Tue, 19 Jan 2021 08:40:38 -0500 Received: by mail-io1-xd2f.google.com with SMTP id d13so36317291ioy.4; Tue, 19 Jan 2021 05:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8RGy8xtddkf/Hto4xoWIa8XeOj/4qpPYA/syTc95gqg=; b=K2GDJ+5tCgk1p4oz1whw/ZDacMlkuUBqH8Z6zP6UmQhk0QRpiOb21oFGchagmNZYwv 9l5YE/Qp9GuBATYWzCnuW9JaUvXo49DE+EDR6exklbxiwSddP67HNTsUExTOxtwkhwSb juX25InKpQxPqdSF5jalMcnzBFy08RbfOAib+XIUMIk5rsnMprp/9JylUCkPsQGHtzZS QRtRQypdwAE6ktTZ6LRxxEC19KoDj2FR6DLMWzcwDwySP6ZES/Mr3gb84CBeJEaPfXan 5yJdTG28WM9mTxCDq4TjrfMDjxJWXoQgomDodvk8Kucsh0KpHNGjOYuf2nUBS6lTVe/T GP1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8RGy8xtddkf/Hto4xoWIa8XeOj/4qpPYA/syTc95gqg=; b=KCYX/0uSfwGtxn4K/pKfE4Ez28Dp9ekCY7qUXf4KvtYEsZH2pBesdHvUT2ZU9y7F5l S6mKGfvu+/eoAS2hdqEsHa0+Q8xfEw005vVbk2PkuQrPu0PcEnMFFLVF9qzvZ6Z9Jjo4 gjvteGQi0nMTjrekdVdBBvtwK3mgPprOFYbyOOZ8SYBc/NU7GNM0oRSrNh37MAQVek+C 3WEzoqcB8yvBk24p0X1bf5wuylj0iS68eEQlKWupS7ExKWarEWygCWmAFNQ11ZlzYTEk CdeXIadOCIKll8Bo0Harc3L28exME2nu8CWFLbNMpB+P5ad0PGiGHNe698ZAlwDuw9TL GPDA== X-Gm-Message-State: AOAM532NXrOCQC+xfWQaNWKON05OpvS7ZdsldHHCiiGHTGjQjmCTKPma GftAlyhV/6Rw8OcPbgM08NA= X-Google-Smtp-Source: ABdhPJy3Ux6p2NP5QBZNpMdeFFm+tETzDN9JrFtzjUcowAi94is/DiKgqU+fITJ+mZvop/Ce3xlFjQ== X-Received: by 2002:a05:6638:214a:: with SMTP id z10mr3500247jaj.41.1611063635884; Tue, 19 Jan 2021 05:40:35 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:35 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Xuzhou Cheng , Bin Meng Subject: [PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 19 Jan 2021 21:39:03 +0800 Message-Id: <1611063546-20278-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:43 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 23f9f9d..5838bb0 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -257,9 +257,15 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFV-00035Q-Il for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFP-0002yd-4L; Tue, 19 Jan 2021 08:40:39 -0500 Received: from mail-io1-xd2f.google.com ([2607:f8b0:4864:20::d2f]:45978) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFL-0003UU-4o; Tue, 19 Jan 2021 08:40:38 -0500 Received: by mail-io1-xd2f.google.com with SMTP id p72so14791855iod.12; Tue, 19 Jan 2021 05:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G3+vtrL9NOpi9RzrlahaCTFTA/TF6kWi2FPH4n3xjHo=; b=YR8Ba06jIEfT2ztj4T58FvZUHEG3IbbiYcejg35UZ55YLapWjTEY3GhB7icO6n+w5R Kl66kf4FgfikCa4UkBjusazWcAa0oEgcv2preIwLh2UjxyWQoH7IL6snpRmOt2iU9Wgp pTIh5NF6bnqF39epbatGW/wxx8wRpo9Jj61N3AE8Xla+Z5BdZM4gfb4mezbiQnytCGJb JAHROZmeP0ru6KOwLIbss20NLsJ2y4SJDQoZe0eDoxHR+vOmBTdSB9D4SG8iJPloq9Rw lJpDncwvb9OLxT+D9LpQmySehtPImy46/Ogm6aV0GfhamEJk501CT19oIIo7Oj7j8zUi ZeVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G3+vtrL9NOpi9RzrlahaCTFTA/TF6kWi2FPH4n3xjHo=; b=L5ZudOwPFyXGN4XBoyfUJSC8vxxLdoLO8Q92ZAwwzis1zlYT2WF6ZwhKjJhpezup/k wJN/lZ7m0ZIQZnbpp6i1bHr+Jtky4sqqe8025zsLgkrzwUzADcatB+585Hzl0OblNdBx Kml4uQSRCRd/4GJiVVyErbz+XFJf8blsoh0FHy5phUyE6YtO4P6rrw3Hd8gVJ2SAmt89 FhQCkEXH4wFDYn7wdfVHIcgFQTXgY8aD8TKGMz4AnAGmjloRSZSskuTiMypuVNRudWRf qWLt+saBfr9NVID2NAPlZ4THQ++kHL6Qnl3D/tRV81KDHiowFEf2P3mPk3iccs73D6TL CGJg== X-Gm-Message-State: AOAM5319XDDJHb6HFWQNGT3PxWmBZGh108E+DLsccOIaotpZdmlP7iwL 26BG/2JmYuJvg9sJXbtRqww= X-Google-Smtp-Source: ABdhPJxjWGMfpLngMa8A5d1m87ZoKgOMQfh/WiBa8VmDhXfhOGRFfSugxNcF7+petRlGY9by/lCFSg== X-Received: by 2002:a02:a183:: with SMTP id n3mr3418109jah.31.1611063632614; Tue, 19 Jan 2021 05:40:32 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:32 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Tue, 19 Jan 2021 21:39:02 +0800 Message-Id: <1611063546-20278-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:43 -0000 From: Philippe Mathieu-Daudé When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng --- Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_write() to handle block disabled hw/ssi/imx_spi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 277b936..23f9f9d 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -327,6 +327,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + } + change_mask = s->regs[index] ^ value; switch (index) { @@ -335,10 +343,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFW-00038x-PE for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFV-00034Y-98; Tue, 19 Jan 2021 08:40:45 -0500 Received: from mail-io1-xd29.google.com ([2607:f8b0:4864:20::d29]:43478) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFT-0003Wh-Ko; Tue, 19 Jan 2021 08:40:45 -0500 Received: by mail-io1-xd29.google.com with SMTP id x21so21354187iog.10; Tue, 19 Jan 2021 05:40:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ih8DXH2AR1+PTjLqD5HM8bi1+XcqteQvWXEW3+VB5p8=; b=pEKXCxJdHwxJVr9HfKLp+E/Ae/Nb+PYYmQUzI3ekzXXX9w2sqs7TgNtkIeZeKepwiq 7CYqR4aESAJtz5Z9a4Z3FcAtHdG0MFHp89BdIOM7mES8yWMrJZuuAcOPRUjLvGQ6taHp kD+gVqGpZcpaRtE56Y9RMPuaOzKKXAXZqI4zS1u6zYqpGLg519HsvHwP5T1D6jgxIQzs 5aVAdg/JXzzSchMem8zbUBEDnWt+CkTn875ZWDiNLLF/Xi2/kAQ0qRr80nQwuwGBziD1 n2Z7/mumIEMQFmzQHTF0cHB0tE7Y8Ss7y6Aip9r61i47ueh4ph3jR4vab00dL3o+gzBG tJ0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ih8DXH2AR1+PTjLqD5HM8bi1+XcqteQvWXEW3+VB5p8=; b=rnQ2j0FnJyMIjNQCfuBtp8fxPu1fpspexM6EDLA/h/Hy/Qagz8lPbSJPMu65bPqlTq qWWO1Fm3TKNI2TNTOTHzjKfz3eJPls4l45tSSLPCtIHdO+ldfiwMZEKM1Dizco7KdVqH cYd0PpsB2WB+MN0W+g9P22zPsmbGjTvF088csPRGZCWWVx+ov3hYIwaW1vuIjM6jFkdu CDyrozI1u4sQvcVXYK8l8moJn9s+P++Ip7Wa/zOBQ/BXJgR5f642VM6spQFi6iHAC5J1 cX5sMCdcFXTgyyL+vlTqN5QXLyGxKK65PI7dyfldF/uOj5MfFxU98pD1x7qFMCT97jl6 6kaA== X-Gm-Message-State: AOAM531zldYgSLj0tK3r88M/C0wXpIY6XDMtNS3y3/Et0MHElNI4WMXK 7d2/sdE0aBac4lgCQFEXzCLF/YA7d2U= X-Google-Smtp-Source: ABdhPJzZeIAOGWIzTZB+TQT3GzyNtS1d/Ko8/u496PYEYKeYvvk3U1pra8Z6qCL0GZHNswwOlLLO/g== X-Received: by 2002:a05:6602:20c9:: with SMTP id 9mr2904371ioz.51.1611063642160; Tue, 19 Jan 2021 05:40:42 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:41 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Tue, 19 Jan 2021 21:39:05 +0800 Message-Id: <1611063546-20278-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d29; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:46 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 3c80725..de0c481 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -191,7 +191,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFX-0003D9-WF for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFW-000374-32; Tue, 19 Jan 2021 08:40:46 -0500 Received: from mail-io1-xd34.google.com ([2607:f8b0:4864:20::d34]:35775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFT-0003WT-KS; Tue, 19 Jan 2021 08:40:45 -0500 Received: by mail-io1-xd34.google.com with SMTP id y19so39553782iov.2; Tue, 19 Jan 2021 05:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HWzb9NPxWe6zyUwwKtlVZgXltJoC0KnXjNfztjX3fMQ=; b=dl6T87y1YNVYT4kq6iRLKx9UWiHGFGBkyR/JyAFmqAOQucTzLJFTXAE6ZNbikxpxf7 Iw9I2NckKPcz3JbyvDtgQpH+XvED1nYsQ/8DQ5StyTTbX2EiSnfpzU5U7lFQlNjHXQGy h2fgqFDt4jJHAfGcO5/wcYOHSoF6k/TP09pNbEJLMaB7rzXg0FjOFwUpHB7JfGT3fypI 2wcQOI5RYxAhrdUv1Gh9m/40iOzxwCXZbJcTu1VqNW4CLunYveaZdrRjz1kSjz4TTrF7 P1ML0XNh0kW1AEXXPkgsw90AizYj+GVA6Lp3IVW2Y7K3OEg6x7AIKOAok5w5DLGba1G/ P4TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HWzb9NPxWe6zyUwwKtlVZgXltJoC0KnXjNfztjX3fMQ=; b=AIhZvHC6939cZE6OtmfVLQ5Ovj3ZpKHFpJRRfcFsKjovtUW+eM3vQWTVWGBvp4Se0y nICviTPX67xpHRou8DxFngPL4n4t/8pUYmQS7obZjkaoF4MtE2sZaz1/hyJw+lfDx2bl 7cWYalSb0NcnbOV9zNdflcY8biC5o60/MvEg+vu+o+DXOl+uYxLC03znuk/1ysoRsyyP zi3dzFMvUZUWmTqcn+AQ0BO4sCdvGQZUlDaJya/No9UxWEHIJs/PgdCc5xpA6yITEaI+ kF8SmPK1HVPWM0ogQSmrRRiqfSFx6nRpIUDFiuqxtRUi0CEc8Jl4RKKjYmrVs1MMQV20 Mv0Q== X-Gm-Message-State: AOAM532N56A2Al0sf6uI9oFJSujt0bk0uqFBkygnAvvylM/vGhFiPDLH iZPdcvQnI7CZNX3ZQRIXNQhwN9BTen8= X-Google-Smtp-Source: ABdhPJxxyiVLQ2ZOCRvmJQGLhy8HEh35gM3sqMoIPjPyXOaF33k0i2YfFSlE82pQL/owIG1CNUG4Dg== X-Received: by 2002:a92:cd47:: with SMTP id v7mr3407233ilq.288.1611063639095; Tue, 19 Jan 2021 05:40:39 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:38 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Tue, 19 Jan 2021 21:39:04 +0800 Message-Id: <1611063546-20278-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:46 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng --- (no changes since v5) Changes in v5: - round up the burst length to be multiple of 8 Changes in v4: - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 5838bb0..3c80725 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length (%d) not multiple of 8!\n", + TYPE_IMX_SPI, __func__, burst); + burst = ROUND_UP(burst, 8); + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length rounded up to %d; this may not work.\n", + TYPE_IMX_SPI, __func__, burst); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:40:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rFe-0003KD-8U for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:40:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rFY-0003EH-AG; Tue, 19 Jan 2021 08:40:52 -0500 Received: from mail-io1-xd2a.google.com ([2607:f8b0:4864:20::d2a]:40581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rFW-0003XG-MG; Tue, 19 Jan 2021 08:40:48 -0500 Received: by mail-io1-xd2a.google.com with SMTP id n2so22380028iom.7; Tue, 19 Jan 2021 05:40:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=81q2vH6wgdVZqHaFuZsg0z4KTvL3AEbyHNnby4vouL8=; b=OB1lhn+ERAtxV/VC4+8o8f0IKyRI6GVxoqscBkkTCQKqzo66KHVZre/TUsb4FfdHzP 3Hpc8WBy1KN3iGi9vkFf0eWZ2mo+o+bPSxTdKwnqyfbqh9dOG53T2mD/68TFIK3epnpd Mpaq6f2jDlFTwjmQou509507Aofvs9Be2H15X8c+RNdAHNDZdcarcbKiS/7a3oZ3IPvL a+/aypUcbfjJTQRk1vjn3Rhng5IUeAotNSaJ7FJ5IaJJVLUSWj9ICaSnafRRCVNfXkCg EV68wXbSb1lhNpgyR9Q3FHuDCTmOVorqLPaUX/3C3CWVefllg1unesQ4QbGvLqp3o3SG O5Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=81q2vH6wgdVZqHaFuZsg0z4KTvL3AEbyHNnby4vouL8=; b=JL+jZV/PeWr9WCbAa6+VUq5p1pv2jN4nsN8/ufepRntcKbJJtqdwMFKKf2TRtbfKK0 GEd8DXxdRI6xrR4J0MqRC6LShyZcLkIcd8GukXmtWvfniGYuiWXIrWZExOwd6LxsVJ7x mD78jlM5uciU3aLBhqCqB7Er7CKtUgJo7P68+J2KdzguGUpGoGIbawXM59EUiPF2eQ5x FI2Be4b6W9cBRfxwvv1XNtVjvy+kpLK5fUG1Hjy3QJO+gV8T6M1ygtnQPCSHK67RQlTE kimfNLlUpzeUILiz10G5PKzQj+x7YDGmJrilTLSWsCvymRMKtJ9yZEKKxRwztNj9jZrY 4/uA== X-Gm-Message-State: AOAM531OE5FvpNUBocAunkCJlcL0gxToxUXUA6ww2qSkFwbkPDr5NHwQ Ql9NPlkH0TVUQTBNNdGsBCDLusYVPAE= X-Google-Smtp-Source: ABdhPJxrAaBLJJc65IJBEfjDc2RdNTTm9lTDHjllijzOHkD6BWbTvUyL51NT96Zlb6Q3tPr16/di7w== X-Received: by 2002:a02:3213:: with SMTP id j19mr3460480jaa.79.1611063645447; Tue, 19 Jan 2021 05:40:45 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (unknown-124-94.windriver.com. [147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:44 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Bin Meng Subject: [PATCH v8 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Tue, 19 Jan 2021 21:39:06 +0800 Message-Id: <1611063546-20278-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::d2a; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:40:52 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng --- (no changes since v3) Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index de0c481..dee7368 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -175,7 +175,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -196,7 +195,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -205,13 +204,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.7.4 From MAILER-DAEMON Tue Jan 19 08:47:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rMI-0001ne-Ii for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:47:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rMG-0001kb-Ae for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:47:44 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:53048) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rM8-0004k2-1X for qemu-arm@nongnu.org; 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Tue, 19 Jan 2021 05:47:32 -0800 (PST) MIME-Version: 1.0 References: <20210115101126.4259-1-maxim.uvarov@linaro.org> <20210115101126.4259-4-maxim.uvarov@linaro.org> In-Reply-To: From: Maxim Uvarov Date: Tue, 19 Jan 2021 16:47:21 +0300 Message-ID: Subject: Re: [PATCHv7 3/3] arm-virt: add secure pl061 for reset/power down To: Peter Maydell Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=maxim.uvarov@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:47:44 -0000 On Tue, 19 Jan 2021 at 16:07, Peter Maydell wrote: > > On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote: > > > > Add secure pl061 for reset/power down machine from > > the secure world (Arm Trusted Firmware). Connect it > > with gpio-pwr driver. > > > > Signed-off-by: Maxim Uvarov > > --- > > hw/arm/Kconfig | 1 + > > hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++++++++++++ > > include/hw/arm/virt.h | 2 ++ > > 3 files changed, 53 insertions(+) > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index 0a242e4c5d..13cc42dcc8 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -17,6 +17,7 @@ config ARM_VIRT > > select PL011 # UART > > select PL031 # RTC > > select PL061 # GPIO > > + select GPIO_PWR > > select PLATFORM_BUS > > select SMBIOS > > select VIRTIO_MMIO > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > > index 26bb66e8e1..436ae894c9 100644 > > --- a/hw/arm/virt.c > > +++ b/hw/arm/virt.c > > @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { > > [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, > > [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, > > [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, > > + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ > > [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, > > @@ -841,6 +842,46 @@ static void create_gpio_keys(const VirtMachineState *vms, > > "gpios", phandle, 3, 0); > > } > > > > +#define ATF_GPIO_POWEROFF 3 > > +#define ATF_GPIO_REBOOT 4 > > These aren't ATF specific, so you could name them SECURE_GPIO_POWEROFF > and SECURE_GPIO_REBOOT. > OK. > Remind me why we start with GPIO line number 3 and not 0 ? > Original gpio power key use 3 and 4 (non-secure). I just selected the same to be consistent. > > + > > +static void create_gpio_pwr(const VirtMachineState *vms, > > + DeviceState *pl061_dev, > > + uint32_t phandle) > > +{ > > + DeviceState *gpio_pwr_dev; > > + > > + /* gpio-pwr */ > > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); > > + > > + /* connect secure pl061 to gpio-pwr */ > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_POWEROFF, > > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > > + qdev_connect_gpio_out(pl061_dev, ATF_GPIO_REBOOT, > > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > > You've connected the POWEROFF gpio line to 'reset' and the > REBOOT line to 'shutdown'. This looks like it's backwards. > Oh, yes. Thanks for finding that. > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); > > + > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", > > + "label", "GPIO PWR Poweroff"); > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", > > + ATF_GPIO_POWEROFF); > > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", > > + "gpios", phandle, 3, 0); > > + > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", > > + "label", "GPIO PWR Reboot"); > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", > > + ATF_GPIO_REBOOT); > > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", > > + "gpios", phandle, 3, 0); > > There doesn't seem to be any documented 'gpio-pwr' devicetree > binding. Where does this come from ? > gpio-pwr created from the first patch. There are no bindings yet. > I think the bindings you want to be using are > https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-restart.txt > https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt > These handles are from 'secure memory' where linux does not have access. But I think we can use that binding with other compatible. Like compatible = "gpio-poweroff,secure". Maxim. > thanks > -- PMM From MAILER-DAEMON Tue Jan 19 08:49:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rOP-0004ht-CB for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:49:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rOO-0004eo-1m; Tue, 19 Jan 2021 08:49:56 -0500 Received: from mx2.suse.de ([195.135.220.15]:45332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rOL-00056A-OU; Tue, 19 Jan 2021 08:49:55 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id F3696B185; Tue, 19 Jan 2021 13:49:51 +0000 (UTC) Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers From: Claudio Fontana To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , peter.maydell@linaro.org Cc: "open list:ARM TCG CPUs" , Luis Machado , qemu-devel@nongnu.org References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> Message-ID: <0a39b15c-4b34-1600-c8b6-cc73c7c89e00@suse.de> Date: Tue, 19 Jan 2021 14:49:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:49:56 -0000 On 1/19/21 2:38 PM, Claudio Fontana wrote: > Hi Alex, > > after updating to latest master today, I am getting the following error with > > make check-tcg > > qemu-system-aarch64: -gdb unix:path=/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEMU waiting for connection on: disconnected:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server > warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" > warning: Could not load XML target description; ignoring > qemu-system-aarch64: QEMU: Terminated via GDBstub > > Seems to indicate it is "ieee_half" -related? > > Thanks, > > Claudio also later on I get: TEST basic gdbstub support warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" warning: Could not load XML target description; ignoring TEST basic gdbstub qXfer:auxv:read support warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" warning: Could not load XML target description; ignoring TEST basic gdbstub SVE support warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" warning: Could not load XML target description; ignoring *** stack smashing detected ***: terminated TEST basic gdbstub SVE ZLEN support warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" warning: Could not load XML target description; ignoring Python 3.6.10 (default, Jan 16 2020, 09:12:04) [GCC] on linux Type "help", "copyright", "credits" or "license" for more information. (InteractiveConsole) ... and here it buzzes. Thanks, Claudio > > On 1/15/21 2:08 PM, Alex Bennée wrote: >> While GDB can work with any XML description given to it there is >> special handling for SVE registers on the GDB side which makes the >> users life a little better. The changes aren't that major and all the >> registers save the $vg reported the same. All that changes is: >> >> - report org.gnu.gdb.aarch64.sve >> - use gdb nomenclature for names and types >> - minor re-ordering of the types to match reference >> - re-enable ieee_half (as we know gdb supports it now) >> - $vg is now a 64 bit int >> - check $vN and $zN aliasing in test >> >> Signed-off-by: Alex Bennée >> Reviewed-by: Luis Machado >> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> >> >> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >> index 866595b4f1..a8fff2a3d0 100644 >> --- a/target/arm/gdbstub.c >> +++ b/target/arm/gdbstub.c >> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { >> { "uint128", 128, 'q', 'u' }, >> { "int128", 128, 'q', 's' }, >> /* 64 bit */ >> + { "ieee_double", 64, 'd', 'f' }, >> { "uint64", 64, 'd', 'u' }, >> { "int64", 64, 'd', 's' }, >> - { "ieee_double", 64, 'd', 'f' }, >> /* 32 bit */ >> + { "ieee_single", 32, 's', 'f' }, >> { "uint32", 32, 's', 'u' }, >> { "int32", 32, 's', 's' }, >> - { "ieee_single", 32, 's', 'f' }, >> /* 16 bit */ >> + { "ieee_half", 16, 'h', 'f' }, >> { "uint16", 16, 'h', 'u' }, >> { "int16", 16, 'h', 's' }, >> - /* >> - * TODO: currently there is no reliable way of telling >> - * if the remote gdb actually understands ieee_half so >> - * we don't expose it in the target description for now. >> - * { "ieee_half", 16, 'h', 'f' }, >> - */ >> /* bytes */ >> { "uint8", 8, 'b', 'u' }, >> { "int8", 8, 'b', 's' }, >> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >> GString *s = g_string_new(NULL); >> DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; >> g_autoptr(GString) ts = g_string_new(""); >> - int i, bits, reg_width = (cpu->sve_max_vq * 128); >> + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); >> info->num = 0; >> g_string_printf(s, ""); >> g_string_append_printf(s, ""); >> - g_string_append_printf(s, ""); >> + g_string_append_printf(s, ""); >> >> /* First define types and totals in a whole VL */ >> for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >> int count = reg_width / vec_lanes[i].size; >> - g_string_printf(ts, "vq%d%c%c", count, >> - vec_lanes[i].sz, vec_lanes[i].suffix); >> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); >> g_string_append_printf(s, >> "", >> ts->str, vec_lanes[i].gdb_type, count); >> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >> * signed and potentially float versions of each size from 128 to >> * 8 bits. >> */ >> - for (bits = 128; bits >= 8; bits /= 2) { >> - int count = reg_width / bits; >> - g_string_append_printf(s, "", count); >> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size == bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].suffix, >> - count, >> - vec_lanes[i].sz, vec_lanes[i].suffix); >> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", suf[i]); >> + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { >> + if (vec_lanes[j].size == bits) { >> + g_string_append_printf(s, "", >> + vec_lanes[j].suffix, >> + vec_lanes[j].sz, vec_lanes[j].suffix); >> } >> } >> g_string_append(s, ""); >> } >> /* And now the final union of unions */ >> - g_string_append(s, ""); >> - for (bits = 128; bits >= 8; bits /= 2) { >> - int count = reg_width / bits; >> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size == bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].sz, count); >> - break; >> - } >> - } >> + g_string_append(s, ""); >> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", >> + suf[i], suf[i]); >> } >> g_string_append(s, ""); >> >> + /* Finally the sve prefix type */ >> + g_string_append_printf(s, >> + "", >> + reg_width / 8); >> + >> /* Then define each register in parts for each vq */ >> for (i = 0; i < 32; i++) { >> g_string_append_printf(s, >> "> - " regnum=\"%d\" group=\"vector\"" >> - " type=\"vq\"/>", >> + " regnum=\"%d\" type=\"svev\"/>", >> i, reg_width, base_reg++); >> info->num++; >> } >> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >> " regnum=\"%d\" group=\"float\"" >> " type=\"int\"/>", base_reg++); >> info->num += 2; >> - /* >> - * Predicate registers aren't so big they are worth splitting up >> - * but we do need to define a type to hold the array of quad >> - * references. >> - */ >> - g_string_append_printf(s, >> - "", >> - cpu->sve_max_vq); >> + >> for (i = 0; i < 16; i++) { >> g_string_append_printf(s, >> "> - " regnum=\"%d\" group=\"vector\"" >> - " type=\"vqp\"/>", >> + " regnum=\"%d\" type=\"svep\"/>", >> i, cpu->sve_max_vq * 16, base_reg++); >> info->num++; >> } >> g_string_append_printf(s, >> "> " regnum=\"%d\" group=\"vector\"" >> - " type=\"vqp\"/>", >> + " type=\"svep\"/>", >> cpu->sve_max_vq * 16, base_reg++); >> g_string_append_printf(s, >> "> - " regnum=\"%d\" group=\"vector\"" >> - " type=\"uint32\"/>", >> + " regnum=\"%d\" type=\"int\"/>", >> base_reg++); >> info->num += 2; >> g_string_append_printf(s, ""); >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 5ab3f5ace3..8a492465d6 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) >> * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. >> */ >> int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >> - return gdb_get_reg32(buf, vq * 2); >> + return gdb_get_reg64(buf, vq * 2); >> } >> default: >> /* gdbstub asked for something out our range */ >> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> index 972cf73c31..b9ef169c1a 100644 >> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >> except gdb.error: >> report(False, "checking zregs (out of range)") >> >> + # Check the aliased V registers are set and GDB has correctly >> + # created them for us having recognised and handled SVE. >> + try: >> + for i in range(0, 16): >> + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) >> + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) >> + report(int(val_z) == int(val_v), >> + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) >> + except gdb.error: >> + report(False, "checking vregs (out of range)") >> + >> >> def run_test(): >> "Run through the tests one by one" >> > > From MAILER-DAEMON Tue Jan 19 08:51:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rPZ-0005k3-LR for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:51:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58646) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rPY-0005gB-7a for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:51:08 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:35177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rPR-0005Jv-7h for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:51:08 -0500 Received: by mail-ed1-x529.google.com with SMTP id u19so21606095edx.2 for ; Tue, 19 Jan 2021 05:51:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=d+vjECBYFoR6D1gAq6LxYtYPG1ClriFhGmGlhv7QJag=; b=VNOEhDZYFKYnZVyUKcLpLVuYPtgVIJf5JIohfKT4j/JCdn5ReKeNCpZDQki82g1Evr GqrkFxhXPBgiGgcyYAUWoTMtNs1eQ1DfBPg721+2onicGY7UUVRMl+YwfqZqJ6vYVEiJ kpNqiACNaNZzOc83bM2jQMZueI9Px1iTZFbideSdIPiWXdqA0J6bkIOJER8LafxY/GrU EJIXxosuvN/9k0uQ8OV81MrsDhppCvYW9S9GbeezS/3ZZYSrqVPtCDTH2EjVnuNft9O5 0cr6n0k3y0yWJb9khbbkii7nLs6lVqkJeQefjlvz93CaZGqkwEDaMZ/VrKzM6AwySzul a6aA== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:51:08 -0000 On Sun, 17 Jan 2021 at 19:24, Philippe Mathieu-Daud=C3=A9 = wrote: > > 'vmstate_dummy' is special and only used for user-mode. Rename > it to something more specific. > It was introduced restricted to user-mode in commit c71c3e99b8 > ("Add a vmstate_dummy struct for CONFIG_USER_ONLY") but this > restriction was later removed in commit 6afc14e92ac ("migration: > Fix warning caused by missing declaration of vmstate_dummy"). > Avoid the missing declaration warning by adding a stub for the > symbol, and restore the #ifdef'ry. So what is the actual use of vmstate_dummy ? I had a grep through and as far as I can see the points where vmstate_cpu_common is used are all in softmmu-only code. I tried this patch and QEMU seems to compile OK: diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 140fa32a5e3..a827417a4d8 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1131,8 +1131,6 @@ bool target_words_bigendian(void); #ifdef CONFIG_SOFTMMU extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy #endif #define VMSTATE_CPU() { = \ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..8df7b69f389 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,8 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; -extern const VMStateDescription vmstate_dummy; - extern const VMStateInfo vmstate_info_bool; extern const VMStateInfo vmstate_info_int8; diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8513d9204e4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,8 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" -const VMStateDescription vmstate_dummy =3D {}; - int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, thanks -- PMM From MAILER-DAEMON Tue Jan 19 08:53:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rS1-0000c1-Li for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 08:53:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rRz-0000Vd-FN for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:53:39 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:44572) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rRx-0005hG-SQ for qemu-arm@nongnu.org; Tue, 19 Jan 2021 08:53:39 -0500 Received: by mail-ej1-x62f.google.com with SMTP id w1so28552220ejf.11 for ; Tue, 19 Jan 2021 05:53:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; 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Tue, 19 Jan 2021 05:53:36 -0800 (PST) MIME-Version: 1.0 References: <20210119062739.589049-1-f4bug@amsat.org> In-Reply-To: <20210119062739.589049-1-f4bug@amsat.org> From: Peter Maydell Date: Tue, 19 Jan 2021 13:53:25 +0000 Message-ID: Subject: Re: [PATCH] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , qemu-arm , QEMU Trivial Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 13:53:39 -0000 On Tue, 19 Jan 2021 at 06:27, Philippe Mathieu-Daud=C3=A9 = wrote: > > When building with GCC 10.2 configured with --extra-cflags=3D-Os, we get: > > target/arm/m_helper.c: In function =E2=80=98arm_v7m_cpu_do_interrupt=E2= =80=99: > target/arm/m_helper.c:1811:16: error: =E2=80=98restore_s16_s31=E2=80=99= may be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] > 1811 | if (restore_s16_s31) { > | ^ > target/arm/m_helper.c:1350:10: note: =E2=80=98restore_s16_s31=E2=80=99 = was declared here > 1350 | bool restore_s16_s31; > | ^~~~~~~~~~~~~~~ > cc1: all warnings being treated as errors > > Initialize the 'restore_s16_s31' variable to silence the warning. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/m_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Tue Jan 19 09:12:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1rkb-0007td-19 for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 09:12:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1rkZ-0007sR-FN for qemu-arm@nongnu.org; Tue, 19 Jan 2021 09:12:51 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:34218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1rkW-0000Oa-Sh for qemu-arm@nongnu.org; Tue, 19 Jan 2021 09:12:51 -0500 Received: by mail-ej1-x631.google.com with SMTP id hs11so26361891ejc.1 for ; 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Tue, 19 Jan 2021 06:12:46 -0800 (PST) MIME-Version: 1.0 References: <20210115101126.4259-1-maxim.uvarov@linaro.org> <20210115101126.4259-4-maxim.uvarov@linaro.org> In-Reply-To: From: Peter Maydell Date: Tue, 19 Jan 2021 14:12:35 +0000 Message-ID: Subject: Re: [PATCHv7 3/3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 14:12:51 -0000 On Tue, 19 Jan 2021 at 13:47, Maxim Uvarov wrote: > > On Tue, 19 Jan 2021 at 16:07, Peter Maydell wrote: > > > > On Fri, 15 Jan 2021 at 10:11, Maxim Uvarov wrote: > > Remind me why we start with GPIO line number 3 and not 0 ? > > > > Original gpio power key use 3 and 4 (non-secure). I just selected the > same to be consistent. Those are different GPIO lines on a different PL061 doing a different job. I don't think they need to be the same number. The power keys are on 3 and 4 because pins 0, 1 and 2 were reserved for PCI hotplug, CPU hotplug and memory hotplug. Unless you have some similar reason why you need to reserve pins on the secure PL061, I would just start from 0. > > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr"); > > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr", "compatible", "gpio-pwr"); > > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#size-cells", 0); > > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr", "#address-cells", 1); > > > + > > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/poweroff"); > > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/poweroff", > > > + "label", "GPIO PWR Poweroff"); > > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/poweroff", "code", > > > + ATF_GPIO_POWEROFF); > > > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/poweroff", > > > + "gpios", phandle, 3, 0); > > > + > > > + qemu_fdt_add_subnode(vms->fdt, "/gpio-pwr/reboot"); > > > + qemu_fdt_setprop_string(vms->fdt, "/gpio-pwr/reboot", > > > + "label", "GPIO PWR Reboot"); > > > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-pwr/reboot", "code", > > > + ATF_GPIO_REBOOT); > > > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-pwr/reboot", > > > + "gpios", phandle, 3, 0); > > > > There doesn't seem to be any documented 'gpio-pwr' devicetree > > binding. Where does this come from ? > > > gpio-pwr created from the first patch. There are no bindings yet. You can't use bindings you've just made up -- you have to get them accepted into the kernel's official devicetree documentation if the ones already there aren't sufficient, before you can add code to QEMU that generates them. > > I think the bindings you want to be using are > > https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-restart.txt > > https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt > > > These handles are from 'secure memory' where linux does not have > access. But I think we can use that > binding with other compatible. Like compatible = "gpio-poweroff,secure". That's not how you specify that a node is only relevant to the secure world: you set the 'status' property to 'disabled' and the 'secure-status' property to 'okay': https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/secure.txt thanks -- PMM From MAILER-DAEMON Tue Jan 19 09:51:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1sLl-0007yW-Q4 for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 09:51:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1sLk-0007vz-BF for qemu-arm@nongnu.org; Tue, 19 Jan 2021 09:51:16 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:35510) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1sLi-0006Xa-5B for qemu-arm@nongnu.org; Tue, 19 Jan 2021 09:51:16 -0500 Received: by mail-wm1-x333.google.com with SMTP id e15so22085wme.0 for ; Tue, 19 Jan 2021 06:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=1q28dFMb5vwgVc6oasyKknW+jNglDaiNk9hIqJ0mcT8=; b=jzSuyAj49ltXbb997GnrJwTtxzUal1fJTL0jFtYtN1O34FGjm1vXLBvdImdMs1XJMo I5FCP8FazM7uaTTHvZPCFaDd4dFPBx1BR5jpeNbEwrbmKV+iNn0QDLl5GrldRVrIvir2 1Ycf9GgVMrsPGAJla/Pt21g1AvxeyiKGFIggTpCbC3dbC2VWs7ft/hbgN3ZhNoWGASfI M3ldM85j5D+u0m5RNnm+z2+jeL/7RE+/0rr6HIURUmXuxbCEC17jOvLgG9CVnq6LFIeP QmUVbPdjzXmTCDU0SwAesBjCgIp6Reul3TSu2G4FX6p8W6jDoV15VWdVO/4+BR1wJTGu 5gyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=1q28dFMb5vwgVc6oasyKknW+jNglDaiNk9hIqJ0mcT8=; b=qr+l7YsyX8h3NMb+rweTv6il++SP/0O5wpyunFLJEBQcYZN2w7abI4ZPrwZ/g+X4wb Flvi+Peuo6rKRXycDDls2N51lEpqEs3Zaq8Zs1jsyPoQSU5BsF3OvF6QXqsicbKeh+Y1 oGNn4vlwSdSyKDrnFG56OO7bF2X19k4GjotUO+k1IzgqeXMrq4NH5VJTbwo7HIPUcX01 Libv7i2jgvsc6VYDr0itRqVj6X5iJvmt0vaKtuOiyNbCjq+3E3lKVx4zu8tSApL9xjl1 Nje/Z721FE1H1+lBpsF5mr16iwm1ZYlLTnCf9izBg+n6bgZ1+I05/GMCHKvGwHPNkko2 5FPw== X-Gm-Message-State: AOAM530QTwcdpYde+rdt2mDgv4FEz9WT2kWZC3O2yWmn0Gs5lJsDJ7Z8 qqC0+ZXhdR5cPP3mwnvktfUx2A== X-Google-Smtp-Source: ABdhPJx6RWX4i+Cm6Z1vBIrgGo/sCPfc+wYdQsr2DAe9P60eUkCMI04vE9jnjzyt7YlG4pBqWu936g== X-Received: by 2002:a05:600c:1549:: with SMTP id f9mr4512976wmg.61.1611067872729; Tue, 19 Jan 2021 06:51:12 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h15sm4573652wmq.3.2021.01.19.06.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jan 2021 06:51:11 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0BAA81FF7E; Tue, 19 Jan 2021 14:51:11 +0000 (GMT) References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Cc: peter.maydell@linaro.org, Luis Machado , "open list:ARM TCG CPUs" , qemu-devel@nongnu.org Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Date: Tue, 19 Jan 2021 14:50:01 +0000 In-reply-to: <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> Message-ID: <874kjdugip.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 14:51:16 -0000 Claudio Fontana writes: > Hi Alex, > > after updating to latest master today, I am getting the following error w= ith > > make check-tcg > > qemu-system-aarch64: -gdb unix:path=3D/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstu= b.socket,server: info: QEMU waiting for connection on: disconnected:unix:/t= mp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server > warning: while parsing target description (at line 47): Vector "svevhf" r= eferences undefined type "ieee_half" > warning: Could not load XML target description; ignoring > qemu-system-aarch64: QEMU: Terminated via GDBstub > > Seems to indicate it is "ieee_half" -related? *sigh* yes - it is. I thought this was solved by the GDB version check in 14/30. What does your gdb report? > > Thanks, > > Claudio > > On 1/15/21 2:08 PM, Alex Benn=C3=A9e wrote: >> While GDB can work with any XML description given to it there is >> special handling for SVE registers on the GDB side which makes the >> users life a little better. The changes aren't that major and all the >> registers save the $vg reported the same. All that changes is: >>=20 >> - report org.gnu.gdb.aarch64.sve >> - use gdb nomenclature for names and types >> - minor re-ordering of the types to match reference >> - re-enable ieee_half (as we know gdb supports it now) >> - $vg is now a 64 bit int >> - check $vN and $zN aliasing in test >>=20 >> Signed-off-by: Alex Benn=C3=A9e >> Reviewed-by: Luis Machado >> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> >>=20 >> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >> index 866595b4f1..a8fff2a3d0 100644 >> --- a/target/arm/gdbstub.c >> +++ b/target/arm/gdbstub.c >> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] =3D { >> { "uint128", 128, 'q', 'u' }, >> { "int128", 128, 'q', 's' }, >> /* 64 bit */ >> + { "ieee_double", 64, 'd', 'f' }, >> { "uint64", 64, 'd', 'u' }, >> { "int64", 64, 'd', 's' }, >> - { "ieee_double", 64, 'd', 'f' }, >> /* 32 bit */ >> + { "ieee_single", 32, 's', 'f' }, >> { "uint32", 32, 's', 'u' }, >> { "int32", 32, 's', 's' }, >> - { "ieee_single", 32, 's', 'f' }, >> /* 16 bit */ >> + { "ieee_half", 16, 'h', 'f' }, >> { "uint16", 16, 'h', 'u' }, >> { "int16", 16, 'h', 's' }, >> - /* >> - * TODO: currently there is no reliable way of telling >> - * if the remote gdb actually understands ieee_half so >> - * we don't expose it in the target description for now. >> - * { "ieee_half", 16, 'h', 'f' }, >> - */ >> /* bytes */ >> { "uint8", 8, 'b', 'u' }, >> { "int8", 8, 'b', 's' }, >> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> GString *s =3D g_string_new(NULL); >> DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; >> g_autoptr(GString) ts =3D g_string_new(""); >> - int i, bits, reg_width =3D (cpu->sve_max_vq * 128); >> + int i, j, bits, reg_width =3D (cpu->sve_max_vq * 128); >> info->num =3D 0; >> g_string_printf(s, ""); >> g_string_append_printf(s, ""); >> - g_string_append_printf(s, ""); >> + g_string_append_printf(s, ""); >>=20=20 >> /* First define types and totals in a whole VL */ >> for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> int count =3D reg_width / vec_lanes[i].size; >> - g_string_printf(ts, "vq%d%c%c", count, >> - vec_lanes[i].sz, vec_lanes[i].suffix); >> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].s= uffix); >> g_string_append_printf(s, >> "", >> ts->str, vec_lanes[i].gdb_type, count); >> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> * signed and potentially float versions of each size from 128 to >> * 8 bits. >> */ >> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >> - int count =3D reg_width / bits; >> - g_string_append_printf(s, "", count); >> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size =3D=3D bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].suffix, >> - count, >> - vec_lanes[i].sz, vec_lanes[i].su= ffix); >> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", suf[i]); >> + for (j =3D 0; j < ARRAY_SIZE(vec_lanes); j++) { >> + if (vec_lanes[j].size =3D=3D bits) { >> + g_string_append_printf(s, "", >> + vec_lanes[j].suffix, >> + vec_lanes[j].sz, vec_lanes[j].su= ffix); >> } >> } >> g_string_append(s, ""); >> } >> /* And now the final union of unions */ >> - g_string_append(s, ""); >> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >> - int count =3D reg_width / bits; >> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >> - if (vec_lanes[i].size =3D=3D bits) { >> - g_string_append_printf(s, "", >> - vec_lanes[i].sz, count); >> - break; >> - } >> - } >> + g_string_append(s, ""); >> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >> + g_string_append_printf(s, "", >> + suf[i], suf[i]); >> } >> g_string_append(s, ""); >>=20=20 >> + /* Finally the sve prefix type */ >> + g_string_append_printf(s, >> + "", >> + reg_width / 8); >> + >> /* Then define each register in parts for each vq */ >> for (i =3D 0; i < 32; i++) { >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vq\"/>", >> + " regnum=3D\"%d\" type=3D\"svev\"/>", >> i, reg_width, base_reg++); >> info->num++; >> } >> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int b= ase_reg) >> " regnum=3D\"%d\" group=3D\"float\"" >> " type=3D\"int\"/>", base_reg++); >> info->num +=3D 2; >> - /* >> - * Predicate registers aren't so big they are worth splitting up >> - * but we do need to define a type to hold the array of quad >> - * references. >> - */ >> - g_string_append_printf(s, >> - "", >> - cpu->sve_max_vq); >> + >> for (i =3D 0; i < 16; i++) { >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vqp\"/>", >> + " regnum=3D\"%d\" type=3D\"svep\"/>", >> i, cpu->sve_max_vq * 16, base_reg++); >> info->num++; >> } >> g_string_append_printf(s, >> "> " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"vqp\"/>", >> + " type=3D\"svep\"/>", >> cpu->sve_max_vq * 16, base_reg++); >> g_string_append_printf(s, >> "> - " regnum=3D\"%d\" group=3D\"vector\"" >> - " type=3D\"uint32\"/>", >> + " regnum=3D\"%d\" type=3D\"int\"/>", >> base_reg++); >> info->num +=3D 2; >> g_string_append_printf(s, ""); >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 5ab3f5ace3..8a492465d6 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByt= eArray *buf, int reg) >> * while the ZCR works in Vector Quads (VQ) which is 128bit chu= nks. >> */ >> int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >> - return gdb_get_reg32(buf, vq * 2); >> + return gdb_get_reg64(buf, vq * 2); >> } >> default: >> /* gdbstub asked for something out our range */ >> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aar= ch64/gdbstub/test-sve-ioctl.py >> index 972cf73c31..b9ef169c1a 100644 >> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >> except gdb.error: >> report(False, "checking zregs (out of range)") >>=20=20 >> + # Check the aliased V registers are set and GDB has correctly >> + # created them for us having recognised and handled SVE. >> + try: >> + for i in range(0, 16): >> + val_z =3D gdb.parse_and_eval("$z0.b.u[%d]" % i) >> + val_v =3D gdb.parse_and_eval("$v0.b.u[%d]" % i) >> + report(int(val_z) =3D=3D int(val_v), >> + "v0.b.u[%d] =3D=3D z0.b.u[%d]" % (i, i)) >> + except gdb.error: >> + report(False, "checking vregs (out of range)") >> + >>=20=20 >> def run_test(): >> "Run through the tests one by one" >>=20 --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 19 10:11:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1sfg-0008DY-HH for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 10:11:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1sfe-00089A-SP; Tue, 19 Jan 2021 10:11:50 -0500 Received: from mx2.suse.de ([195.135.220.15]:54948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1sfc-0001Oi-6P; Tue, 19 Jan 2021 10:11:50 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D212EB28A; Tue, 19 Jan 2021 15:11:41 +0000 (UTC) Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: peter.maydell@linaro.org, Luis Machado , "open list:ARM TCG CPUs" , qemu-devel@nongnu.org References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> <874kjdugip.fsf@linaro.org> From: Claudio Fontana Message-ID: <8cb88b76-caa3-ba26-b288-4d87b06f56ec@suse.de> Date: Tue, 19 Jan 2021 16:11:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <874kjdugip.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 15:11:51 -0000 On 1/19/21 3:50 PM, Alex Bennée wrote: > > Claudio Fontana writes: > >> Hi Alex, >> >> after updating to latest master today, I am getting the following error with >> >> make check-tcg >> >> qemu-system-aarch64: -gdb unix:path=/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEMU waiting for connection on: disconnected:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server >> warning: while parsing target description (at line 47): Vector "svevhf" references undefined type "ieee_half" >> warning: Could not load XML target description; ignoring >> qemu-system-aarch64: QEMU: Terminated via GDBstub >> >> Seems to indicate it is "ieee_half" -related? > > *sigh* > > yes - it is. I thought this was solved by the GDB version check in > 14/30. What does your gdb report? $ gdb --version GNU gdb (GDB; openSUSE Leap 15.2) 8.3.1 Copyright (C) 2019 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. gdb --configuration This GDB was configured as follows: configure --host=x86_64-suse-linux --target=x86_64-suse-linux --with-auto-load-dir=$debugdir:$datadir/auto-load --with-auto-load-safe-path=$debugdir:$datadir/auto-load --with-expat --with-gdb-datadir=/usr/share/gdb --with-jit-reader-dir=/usr/lib64/gdb --without-libunwind-ia64 --with-lzma --without-babeltrace --with-intel-pt --disable-libmcheck --with-mpfr --with-python=/usr --without-guile --disable-source-highlight --with-separate-debug-dir=/usr/lib/debug --with-system-gdbinit=/etc/gdbinit does this help? Let me know if more info is needed. Thanks! Claudio > >> >> Thanks, >> >> Claudio >> >> On 1/15/21 2:08 PM, Alex Bennée wrote: >>> While GDB can work with any XML description given to it there is >>> special handling for SVE registers on the GDB side which makes the >>> users life a little better. The changes aren't that major and all the >>> registers save the $vg reported the same. All that changes is: >>> >>> - report org.gnu.gdb.aarch64.sve >>> - use gdb nomenclature for names and types >>> - minor re-ordering of the types to match reference >>> - re-enable ieee_half (as we know gdb supports it now) >>> - $vg is now a 64 bit int >>> - check $vN and $zN aliasing in test >>> >>> Signed-off-by: Alex Bennée >>> Reviewed-by: Luis Machado >>> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> >>> >>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >>> index 866595b4f1..a8fff2a3d0 100644 >>> --- a/target/arm/gdbstub.c >>> +++ b/target/arm/gdbstub.c >>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] = { >>> { "uint128", 128, 'q', 'u' }, >>> { "int128", 128, 'q', 's' }, >>> /* 64 bit */ >>> + { "ieee_double", 64, 'd', 'f' }, >>> { "uint64", 64, 'd', 'u' }, >>> { "int64", 64, 'd', 's' }, >>> - { "ieee_double", 64, 'd', 'f' }, >>> /* 32 bit */ >>> + { "ieee_single", 32, 's', 'f' }, >>> { "uint32", 32, 's', 'u' }, >>> { "int32", 32, 's', 's' }, >>> - { "ieee_single", 32, 's', 'f' }, >>> /* 16 bit */ >>> + { "ieee_half", 16, 'h', 'f' }, >>> { "uint16", 16, 'h', 'u' }, >>> { "int16", 16, 'h', 's' }, >>> - /* >>> - * TODO: currently there is no reliable way of telling >>> - * if the remote gdb actually understands ieee_half so >>> - * we don't expose it in the target description for now. >>> - * { "ieee_half", 16, 'h', 'f' }, >>> - */ >>> /* bytes */ >>> { "uint8", 8, 'b', 'u' }, >>> { "int8", 8, 'b', 's' }, >>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> GString *s = g_string_new(NULL); >>> DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; >>> g_autoptr(GString) ts = g_string_new(""); >>> - int i, bits, reg_width = (cpu->sve_max_vq * 128); >>> + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); >>> info->num = 0; >>> g_string_printf(s, ""); >>> g_string_append_printf(s, ""); >>> - g_string_append_printf(s, ""); >>> + g_string_append_printf(s, ""); >>> >>> /* First define types and totals in a whole VL */ >>> for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> int count = reg_width / vec_lanes[i].size; >>> - g_string_printf(ts, "vq%d%c%c", count, >>> - vec_lanes[i].sz, vec_lanes[i].suffix); >>> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); >>> g_string_append_printf(s, >>> "", >>> ts->str, vec_lanes[i].gdb_type, count); >>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> * signed and potentially float versions of each size from 128 to >>> * 8 bits. >>> */ >>> - for (bits = 128; bits >= 8; bits /= 2) { >>> - int count = reg_width / bits; >>> - g_string_append_printf(s, "", count); >>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> - if (vec_lanes[i].size == bits) { >>> - g_string_append_printf(s, "", >>> - vec_lanes[i].suffix, >>> - count, >>> - vec_lanes[i].sz, vec_lanes[i].suffix); >>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >>> + g_string_append_printf(s, "", suf[i]); >>> + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { >>> + if (vec_lanes[j].size == bits) { >>> + g_string_append_printf(s, "", >>> + vec_lanes[j].suffix, >>> + vec_lanes[j].sz, vec_lanes[j].suffix); >>> } >>> } >>> g_string_append(s, ""); >>> } >>> /* And now the final union of unions */ >>> - g_string_append(s, ""); >>> - for (bits = 128; bits >= 8; bits /= 2) { >>> - int count = reg_width / bits; >>> - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { >>> - if (vec_lanes[i].size == bits) { >>> - g_string_append_printf(s, "", >>> - vec_lanes[i].sz, count); >>> - break; >>> - } >>> - } >>> + g_string_append(s, ""); >>> + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { >>> + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; >>> + g_string_append_printf(s, "", >>> + suf[i], suf[i]); >>> } >>> g_string_append(s, ""); >>> >>> + /* Finally the sve prefix type */ >>> + g_string_append_printf(s, >>> + "", >>> + reg_width / 8); >>> + >>> /* Then define each register in parts for each vq */ >>> for (i = 0; i < 32; i++) { >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vq\"/>", >>> + " regnum=\"%d\" type=\"svev\"/>", >>> i, reg_width, base_reg++); >>> info->num++; >>> } >>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) >>> " regnum=\"%d\" group=\"float\"" >>> " type=\"int\"/>", base_reg++); >>> info->num += 2; >>> - /* >>> - * Predicate registers aren't so big they are worth splitting up >>> - * but we do need to define a type to hold the array of quad >>> - * references. >>> - */ >>> - g_string_append_printf(s, >>> - "", >>> - cpu->sve_max_vq); >>> + >>> for (i = 0; i < 16; i++) { >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vqp\"/>", >>> + " regnum=\"%d\" type=\"svep\"/>", >>> i, cpu->sve_max_vq * 16, base_reg++); >>> info->num++; >>> } >>> g_string_append_printf(s, >>> ">> " regnum=\"%d\" group=\"vector\"" >>> - " type=\"vqp\"/>", >>> + " type=\"svep\"/>", >>> cpu->sve_max_vq * 16, base_reg++); >>> g_string_append_printf(s, >>> ">> - " regnum=\"%d\" group=\"vector\"" >>> - " type=\"uint32\"/>", >>> + " regnum=\"%d\" type=\"int\"/>", >>> base_reg++); >>> info->num += 2; >>> g_string_append_printf(s, ""); >>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>> index 5ab3f5ace3..8a492465d6 100644 >>> --- a/target/arm/helper.c >>> +++ b/target/arm/helper.c >>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) >>> * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. >>> */ >>> int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >>> - return gdb_get_reg32(buf, vq * 2); >>> + return gdb_get_reg64(buf, vq * 2); >>> } >>> default: >>> /* gdbstub asked for something out our range */ >>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> index 972cf73c31..b9ef169c1a 100644 >>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >>> except gdb.error: >>> report(False, "checking zregs (out of range)") >>> >>> + # Check the aliased V registers are set and GDB has correctly >>> + # created them for us having recognised and handled SVE. >>> + try: >>> + for i in range(0, 16): >>> + val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i) >>> + val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i) >>> + report(int(val_z) == int(val_v), >>> + "v0.b.u[%d] == z0.b.u[%d]" % (i, i)) >>> + except gdb.error: >>> + report(False, "checking vregs (out of range)") >>> + >>> >>> def run_test(): >>> "Run through the tests one by one" >>> > > From MAILER-DAEMON Tue Jan 19 10:57:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1tNo-0002Ib-6W for mharc-qemu-arm@gnu.org; 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Tue, 19 Jan 2021 07:57:20 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8ABD91FF7E; Tue, 19 Jan 2021 15:57:19 +0000 (GMT) References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> <874kjdugip.fsf@linaro.org> <8cb88b76-caa3-ba26-b288-4d87b06f56ec@suse.de> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Cc: peter.maydell@linaro.org, Luis Machado , "open list:ARM TCG CPUs" , qemu-devel@nongnu.org Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers Date: Tue, 19 Jan 2021 15:54:27 +0000 In-reply-to: <8cb88b76-caa3-ba26-b288-4d87b06f56ec@suse.de> Message-ID: <871regvs0w.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 15:57:26 -0000 Claudio Fontana writes: > On 1/19/21 3:50 PM, Alex Benn=C3=A9e wrote: >>=20 >> Claudio Fontana writes: >>=20 >>> Hi Alex, >>> >>> after updating to latest master today, I am getting the following error= with >>> >>> make check-tcg >>> >>> qemu-system-aarch64: -gdb unix:path=3D/tmp/tmp9ru5tgk8qemu-gdbstub/gdbs= tub.socket,server: info: QEMU waiting for connection on: disconnected:unix:= /tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server >>> warning: while parsing target description (at line 47): Vector "svevhf"= references undefined type "ieee_half" >>> warning: Could not load XML target description; ignoring >>> qemu-system-aarch64: QEMU: Terminated via GDBstub >>> >>> Seems to indicate it is "ieee_half" -related? >>=20 >> *sigh* >>=20 >> yes - it is. I thought this was solved by the GDB version check in >> 14/30. What does your gdb report? > > > $ gdb --version > GNU gdb (GDB; openSUSE Leap 15.2) 8.3.1 > Copyright (C) 2019 Free Software Foundation, Inc. > License GPLv3+: GNU GPL version 3 or later > This is free software: you are free to change and redistribute it. > There is NO WARRANTY, to the extent permitted by law. > > gdb --configuration > This GDB was configured as follows: > configure --host=3Dx86_64-suse-linux --target=3Dx86_64-suse-linux > --with-auto-load-dir=3D$debugdir:$datadir/auto-load > --with-auto-load-safe-path=3D$debugdir:$datadir/auto-load > --with-expat > --with-gdb-datadir=3D/usr/share/gdb > --with-jit-reader-dir=3D/usr/lib64/gdb > --without-libunwind-ia64 > --with-lzma > --without-babeltrace > --with-intel-pt > --disable-libmcheck > --with-mpfr > --with-python=3D/usr > --without-guile > --disable-source-highlight > --with-separate-debug-dir=3D/usr/lib/debug > --with-system-gdbinit=3D/etc/gdbinit > > > does this help? So it looks like TDESC_TYPE_IEEE_HALF was only implemented in GDB 9.1 and there is no probing possible during the gdbstub connection. I guess I can either go back to stubbing it out (which would break gdb's SVE understanding) or up our minimum GDB version check for running tests. That would mean less people test GDB (or at least until the distros catch up) but considering it was zero people not too long ago maybe that's acceptable? > > Let me know if more info is needed. Thanks! > > Claudio > > >>=20 >>> >>> Thanks, >>> >>> Claudio >>> >>> On 1/15/21 2:08 PM, Alex Benn=C3=A9e wrote: >>>> While GDB can work with any XML description given to it there is >>>> special handling for SVE registers on the GDB side which makes the >>>> users life a little better. The changes aren't that major and all the >>>> registers save the $vg reported the same. All that changes is: >>>> >>>> - report org.gnu.gdb.aarch64.sve >>>> - use gdb nomenclature for names and types >>>> - minor re-ordering of the types to match reference >>>> - re-enable ieee_half (as we know gdb supports it now) >>>> - $vg is now a 64 bit int >>>> - check $vN and $zN aliasing in test >>>> >>>> Signed-off-by: Alex Benn=C3=A9e >>>> Reviewed-by: Luis Machado >>>> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> >>>> >>>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >>>> index 866595b4f1..a8fff2a3d0 100644 >>>> --- a/target/arm/gdbstub.c >>>> +++ b/target/arm/gdbstub.c >>>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] =3D { >>>> { "uint128", 128, 'q', 'u' }, >>>> { "int128", 128, 'q', 's' }, >>>> /* 64 bit */ >>>> + { "ieee_double", 64, 'd', 'f' }, >>>> { "uint64", 64, 'd', 'u' }, >>>> { "int64", 64, 'd', 's' }, >>>> - { "ieee_double", 64, 'd', 'f' }, >>>> /* 32 bit */ >>>> + { "ieee_single", 32, 's', 'f' }, >>>> { "uint32", 32, 's', 'u' }, >>>> { "int32", 32, 's', 's' }, >>>> - { "ieee_single", 32, 's', 'f' }, >>>> /* 16 bit */ >>>> + { "ieee_half", 16, 'h', 'f' }, >>>> { "uint16", 16, 'h', 'u' }, >>>> { "int16", 16, 'h', 's' }, >>>> - /* >>>> - * TODO: currently there is no reliable way of telling >>>> - * if the remote gdb actually understands ieee_half so >>>> - * we don't expose it in the target description for now. >>>> - * { "ieee_half", 16, 'h', 'f' }, >>>> - */ >>>> /* bytes */ >>>> { "uint8", 8, 'b', 'u' }, >>>> { "int8", 8, 'b', 's' }, >>>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int= base_reg) >>>> GString *s =3D g_string_new(NULL); >>>> DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; >>>> g_autoptr(GString) ts =3D g_string_new(""); >>>> - int i, bits, reg_width =3D (cpu->sve_max_vq * 128); >>>> + int i, j, bits, reg_width =3D (cpu->sve_max_vq * 128); >>>> info->num =3D 0; >>>> g_string_printf(s, ""); >>>> g_string_append_printf(s, ""); >>>> - g_string_append_printf(s, ""); >>>> + g_string_append_printf(s, ""); >>>>=20=20 >>>> /* First define types and totals in a whole VL */ >>>> for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >>>> int count =3D reg_width / vec_lanes[i].size; >>>> - g_string_printf(ts, "vq%d%c%c", count, >>>> - vec_lanes[i].sz, vec_lanes[i].suffix); >>>> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i]= .suffix); >>>> g_string_append_printf(s, >>>> "", >>>> ts->str, vec_lanes[i].gdb_type, count); >>>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int= base_reg) >>>> * signed and potentially float versions of each size from 128 to >>>> * 8 bits. >>>> */ >>>> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >>>> - int count =3D reg_width / bits; >>>> - g_string_append_printf(s, "", count); >>>> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >>>> - if (vec_lanes[i].size =3D=3D bits) { >>>> - g_string_append_printf(s, "", >>>> - vec_lanes[i].suffix, >>>> - count, >>>> - vec_lanes[i].sz, vec_lanes[i].= suffix); >>>> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >>>> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >>>> + g_string_append_printf(s, "", suf[i]); >>>> + for (j =3D 0; j < ARRAY_SIZE(vec_lanes); j++) { >>>> + if (vec_lanes[j].size =3D=3D bits) { >>>> + g_string_append_printf(s, "", >>>> + vec_lanes[j].suffix, >>>> + vec_lanes[j].sz, vec_lanes[j].= suffix); >>>> } >>>> } >>>> g_string_append(s, ""); >>>> } >>>> /* And now the final union of unions */ >>>> - g_string_append(s, ""); >>>> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { >>>> - int count =3D reg_width / bits; >>>> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { >>>> - if (vec_lanes[i].size =3D=3D bits) { >>>> - g_string_append_printf(s, "", >>>> - vec_lanes[i].sz, count); >>>> - break; >>>> - } >>>> - } >>>> + g_string_append(s, ""); >>>> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { >>>> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; >>>> + g_string_append_printf(s, "", >>>> + suf[i], suf[i]); >>>> } >>>> g_string_append(s, ""); >>>>=20=20 >>>> + /* Finally the sve prefix type */ >>>> + g_string_append_printf(s, >>>> + "", >>>> + reg_width / 8); >>>> + >>>> /* Then define each register in parts for each vq */ >>>> for (i =3D 0; i < 32; i++) { >>>> g_string_append_printf(s, >>>> ">>> - " regnum=3D\"%d\" group=3D\"vector\"" >>>> - " type=3D\"vq\"/>", >>>> + " regnum=3D\"%d\" type=3D\"svev\"/>", >>>> i, reg_width, base_reg++); >>>> info->num++; >>>> } >>>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int= base_reg) >>>> " regnum=3D\"%d\" group=3D\"float\"" >>>> " type=3D\"int\"/>", base_reg++); >>>> info->num +=3D 2; >>>> - /* >>>> - * Predicate registers aren't so big they are worth splitting up >>>> - * but we do need to define a type to hold the array of quad >>>> - * references. >>>> - */ >>>> - g_string_append_printf(s, >>>> - "", >>>> - cpu->sve_max_vq); >>>> + >>>> for (i =3D 0; i < 16; i++) { >>>> g_string_append_printf(s, >>>> ">>> - " regnum=3D\"%d\" group=3D\"vector\"" >>>> - " type=3D\"vqp\"/>", >>>> + " regnum=3D\"%d\" type=3D\"svep\"/>", >>>> i, cpu->sve_max_vq * 16, base_reg++); >>>> info->num++; >>>> } >>>> g_string_append_printf(s, >>>> ">>> " regnum=3D\"%d\" group=3D\"vector\"" >>>> - " type=3D\"vqp\"/>", >>>> + " type=3D\"svep\"/>", >>>> cpu->sve_max_vq * 16, base_reg++); >>>> g_string_append_printf(s, >>>> ">>> - " regnum=3D\"%d\" group=3D\"vector\"" >>>> - " type=3D\"uint32\"/>", >>>> + " regnum=3D\"%d\" type=3D\"int\"/>", >>>> base_reg++); >>>> info->num +=3D 2; >>>> g_string_append_printf(s, ""); >>>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>>> index 5ab3f5ace3..8a492465d6 100644 >>>> --- a/target/arm/helper.c >>>> +++ b/target/arm/helper.c >>>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GB= yteArray *buf, int reg) >>>> * while the ZCR works in Vector Quads (VQ) which is 128bit c= hunks. >>>> */ >>>> int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; >>>> - return gdb_get_reg32(buf, vq * 2); >>>> + return gdb_get_reg64(buf, vq * 2); >>>> } >>>> default: >>>> /* gdbstub asked for something out our range */ >>>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/a= arch64/gdbstub/test-sve-ioctl.py >>>> index 972cf73c31..b9ef169c1a 100644 >>>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py >>>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >>>> except gdb.error: >>>> report(False, "checking zregs (out of range)") >>>>=20=20 >>>> + # Check the aliased V registers are set and GDB has correctly >>>> + # created them for us having recognised and handled SVE. >>>> + try: >>>> + for i in range(0, 16): >>>> + val_z =3D gdb.parse_and_eval("$z0.b.u[%d]" % i) >>>> + val_v =3D gdb.parse_and_eval("$v0.b.u[%d]" % i) >>>> + report(int(val_z) =3D=3D int(val_v), >>>> + "v0.b.u[%d] =3D=3D z0.b.u[%d]" % (i, i)) >>>> + except gdb.error: >>>> + report(False, "checking vregs (out of range)") >>>> + >>>>=20=20 >>>> def run_test(): >>>> "Run through the tests one by one" >>>> >>=20 >>=20 --=20 Alex Benn=C3=A9e From MAILER-DAEMON Tue Jan 19 11:20:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1tjc-0003Ts-IU for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 11:20:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1tjZ-0003Rg-V7 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:19:57 -0500 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]:46519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1tjW-0004hy-MK for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:19:57 -0500 Received: by mail-qk1-x72e.google.com with SMTP id d14so22306572qkc.13 for ; Tue, 19 Jan 2021 08:19:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NW0N4uLv1eQiKdM0oK4rx7h2Nsg5RamUU5ILDthX5Zo=; b=MMrBTVV5BcaoUnLTrzS7XjIFpATKXURlZn5y3HaNf8HpvRrJazFw+reSl9+M84HCYU WXkGxV2/pNQLzZIWAq0XnST9tJB9Ii91H9/yVyGLnvrmFewmyASfvbFFbXa0WlVR7mHf KNLj9Z6vx0GmCBz2aTQz340h+e61sl66qUlLtbfZbdykBM3YDpES3cvKtei0vOw0RlkL 5ms4LsPtuF3OP7XdwajAa4Bq2o+sWbpKC2YnxCzVt4J2pmxnSzvPmvenaEcrZr2bYmEV mNMy2EZ8lApspYh4zYgKa7TJcYE3iQtHjm4eS970ZeSyzNM8EHodejwx2FGDHeyPGdy7 pkUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NW0N4uLv1eQiKdM0oK4rx7h2Nsg5RamUU5ILDthX5Zo=; b=s/7xo787iTF+h6DrwCDsmixsbe4Mobdc/NwW03rwkwpW2WNtmO/P0g+zDn5GY8miMj U3zv6YbzWSqQH9VW4/6FpAANibJ8ZAm1gsmxlfCsz0e8UbkDTRYGYUcYGeqJBM2NAP+k Dql7e3HK7gwvF5yE2mtVhymGKTGW0yRJ+sUnw/l1/8Yz0K9mXT3R3xdJ/S+aaqicbt6W fFAbwejaCaMwwxbRVydN/prlUxL3YytmkMX54Cd2oZMwF1upy7ltOtdBgm/9yVr6rPwZ pbT1ovhtQ1E0wEV80CwCPtc8mC18IbEv7T582fCbTJKtGbWyhpNtG36snpMj6Z/bhYyg xv0A== X-Gm-Message-State: AOAM532VkDTt8C8wjpCWYGp9h0egVU24mzObWSLg1tZ60doxQUL70Bly cDrlVi/+BWx+ndRls/uP4fKekzURKD8NDAbNgPfy5w== X-Google-Smtp-Source: ABdhPJxmvzDclGAyP2WLpwX70utku/6cR35D01gPLW6NDLFCE3YQV0HPwFNMZIn71P/3iQvs3vmyeZIyJc3JwHdXlaE= X-Received: by 2002:a37:6810:: with SMTP id d16mr4896178qkc.194.1611073192927; Tue, 19 Jan 2021 08:19:52 -0800 (PST) MIME-Version: 1.0 References: <20210115130828.23968-1-alex.bennee@linaro.org> <20210115130828.23968-22-alex.bennee@linaro.org> <540354a8-bcba-aa82-814d-7f11dc75f5bf@suse.de> <874kjdugip.fsf@linaro.org> <8cb88b76-caa3-ba26-b288-4d87b06f56ec@suse.de> <871regvs0w.fsf@linaro.org> In-Reply-To: <871regvs0w.fsf@linaro.org> From: Luis Machado Date: Tue, 19 Jan 2021 13:19:36 -0300 Message-ID: Subject: Re: [PULL 21/30] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers To: =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: Claudio Fontana , Peter Maydell , "open list:ARM TCG CPUs" , qemu-devel@nongnu.org Content-Type: multipart/alternative; boundary="0000000000005f3cb005b943359b" Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=luis.machado@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:19:58 -0000 --0000000000005f3cb005b943359b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable This is not ideal. GDB should probably have a way to negotiate available types. On Tue, 19 Jan 2021 at 12:57, Alex Benn=C3=A9e wro= te: > > Claudio Fontana writes: > > > On 1/19/21 3:50 PM, Alex Benn=C3=A9e wrote: > >> > >> Claudio Fontana writes: > >> > >>> Hi Alex, > >>> > >>> after updating to latest master today, I am getting the following > error with > >>> > >>> make check-tcg > >>> > >>> qemu-system-aarch64: -gdb > unix:path=3D/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server: info: QEM= U > waiting for connection on: > disconnected:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server > >>> warning: while parsing target description (at line 47): Vector > "svevhf" references undefined type "ieee_half" > >>> warning: Could not load XML target description; ignoring > >>> qemu-system-aarch64: QEMU: Terminated via GDBstub > >>> > >>> Seems to indicate it is "ieee_half" -related? > >> > >> *sigh* > >> > >> yes - it is. I thought this was solved by the GDB version check in > >> 14/30. What does your gdb report? > > > > > > $ gdb --version > > GNU gdb (GDB; openSUSE Leap 15.2) 8.3.1 > > Copyright (C) 2019 Free Software Foundation, Inc. > > License GPLv3+: GNU GPL version 3 or later < > http://gnu.org/licenses/gpl.html> > > This is free software: you are free to change and redistribute it. > > There is NO WARRANTY, to the extent permitted by law. > > > > gdb --configuration > > This GDB was configured as follows: > > configure --host=3Dx86_64-suse-linux --target=3Dx86_64-suse-linux > > --with-auto-load-dir=3D$debugdir:$datadir/auto-load > > --with-auto-load-safe-path=3D$debugdir:$datadir/auto-load > > --with-expat > > --with-gdb-datadir=3D/usr/share/gdb > > --with-jit-reader-dir=3D/usr/lib64/gdb > > --without-libunwind-ia64 > > --with-lzma > > --without-babeltrace > > --with-intel-pt > > --disable-libmcheck > > --with-mpfr > > --with-python=3D/usr > > --without-guile > > --disable-source-highlight > > --with-separate-debug-dir=3D/usr/lib/debug > > --with-system-gdbinit=3D/etc/gdbinit > > > > > > does this help? > > So it looks like TDESC_TYPE_IEEE_HALF was only implemented in GDB 9.1 > and there is no probing possible during the gdbstub connection. I guess > I can either go back to stubbing it out (which would break gdb's SVE > understanding) or up our minimum GDB version check for running tests. > That would mean less people test GDB (or at least until the distros > catch up) but considering it was zero people not too long ago maybe > that's acceptable? > > > > > Let me know if more info is needed. Thanks! > > > > Claudio > > > > > >> > >>> > >>> Thanks, > >>> > >>> Claudio > >>> > >>> On 1/15/21 2:08 PM, Alex Benn=C3=A9e wrote: > >>>> While GDB can work with any XML description given to it there is > >>>> special handling for SVE registers on the GDB side which makes the > >>>> users life a little better. The changes aren't that major and all th= e > >>>> registers save the $vg reported the same. All that changes is: > >>>> > >>>> - report org.gnu.gdb.aarch64.sve > >>>> - use gdb nomenclature for names and types > >>>> - minor re-ordering of the types to match reference > >>>> - re-enable ieee_half (as we know gdb supports it now) > >>>> - $vg is now a 64 bit int > >>>> - check $vN and $zN aliasing in test > >>>> > >>>> Signed-off-by: Alex Benn=C3=A9e > >>>> Reviewed-by: Luis Machado > >>>> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org> > >>>> > >>>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > >>>> index 866595b4f1..a8fff2a3d0 100644 > >>>> --- a/target/arm/gdbstub.c > >>>> +++ b/target/arm/gdbstub.c > >>>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lanes[] =3D { > >>>> { "uint128", 128, 'q', 'u' }, > >>>> { "int128", 128, 'q', 's' }, > >>>> /* 64 bit */ > >>>> + { "ieee_double", 64, 'd', 'f' }, > >>>> { "uint64", 64, 'd', 'u' }, > >>>> { "int64", 64, 'd', 's' }, > >>>> - { "ieee_double", 64, 'd', 'f' }, > >>>> /* 32 bit */ > >>>> + { "ieee_single", 32, 's', 'f' }, > >>>> { "uint32", 32, 's', 'u' }, > >>>> { "int32", 32, 's', 's' }, > >>>> - { "ieee_single", 32, 's', 'f' }, > >>>> /* 16 bit */ > >>>> + { "ieee_half", 16, 'h', 'f' }, > >>>> { "uint16", 16, 'h', 'u' }, > >>>> { "int16", 16, 'h', 's' }, > >>>> - /* > >>>> - * TODO: currently there is no reliable way of telling > >>>> - * if the remote gdb actually understands ieee_half so > >>>> - * we don't expose it in the target description for now. > >>>> - * { "ieee_half", 16, 'h', 'f' }, > >>>> - */ > >>>> /* bytes */ > >>>> { "uint8", 8, 'b', 'u' }, > >>>> { "int8", 8, 'b', 's' }, > >>>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, > int base_reg) > >>>> GString *s =3D g_string_new(NULL); > >>>> DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; > >>>> g_autoptr(GString) ts =3D g_string_new(""); > >>>> - int i, bits, reg_width =3D (cpu->sve_max_vq * 128); > >>>> + int i, j, bits, reg_width =3D (cpu->sve_max_vq * 128); > >>>> info->num =3D 0; > >>>> g_string_printf(s, ""); > >>>> g_string_append_printf(s, " \"gdb-target.dtd\">"); > >>>> - g_string_append_printf(s, " name=3D\"org.qemu.gdb.aarch64.sve\">"); > >>>> + g_string_append_printf(s, " name=3D\"org.gnu.gdb.aarch64.sve\">"); > >>>> > >>>> /* First define types and totals in a whole VL */ > >>>> for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { > >>>> int count =3D reg_width / vec_lanes[i].size; > >>>> - g_string_printf(ts, "vq%d%c%c", count, > >>>> - vec_lanes[i].sz, vec_lanes[i].suffix); > >>>> + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, > vec_lanes[i].suffix); > >>>> g_string_append_printf(s, > >>>> " count=3D\"%d\"/>", > >>>> ts->str, vec_lanes[i].gdb_type, > count); > >>>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, > int base_reg) > >>>> * signed and potentially float versions of each size from 128 = to > >>>> * 8 bits. > >>>> */ > >>>> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { > >>>> - int count =3D reg_width / bits; > >>>> - g_string_append_printf(s, "", count); > >>>> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { > >>>> - if (vec_lanes[i].size =3D=3D bits) { > >>>> - g_string_append_printf(s, " type=3D\"vq%d%c%c\"/>", > >>>> - vec_lanes[i].suffix, > >>>> - count, > >>>> - vec_lanes[i].sz, > vec_lanes[i].suffix); > >>>> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { > >>>> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; > >>>> + g_string_append_printf(s, "", suf[i= ]); > >>>> + for (j =3D 0; j < ARRAY_SIZE(vec_lanes); j++) { > >>>> + if (vec_lanes[j].size =3D=3D bits) { > >>>> + g_string_append_printf(s, " type=3D\"svev%c%c\"/>", > >>>> + vec_lanes[j].suffix, > >>>> + vec_lanes[j].sz, > vec_lanes[j].suffix); > >>>> } > >>>> } > >>>> g_string_append(s, ""); > >>>> } > >>>> /* And now the final union of unions */ > >>>> - g_string_append(s, ""); > >>>> - for (bits =3D 128; bits >=3D 8; bits /=3D 2) { > >>>> - int count =3D reg_width / bits; > >>>> - for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { > >>>> - if (vec_lanes[i].size =3D=3D bits) { > >>>> - g_string_append_printf(s, " type=3D\"vq%dn\"/>", > >>>> - vec_lanes[i].sz, count); > >>>> - break; > >>>> - } > >>>> - } > >>>> + g_string_append(s, ""); > >>>> + for (bits =3D 128, i =3D 0; bits >=3D 8; bits /=3D 2, i++) { > >>>> + const char suf[] =3D { 'q', 'd', 's', 'h', 'b' }; > >>>> + g_string_append_printf(s, " type=3D\"svevn%c\"/>", > >>>> + suf[i], suf[i]); > >>>> } > >>>> g_string_append(s, ""); > >>>> > >>>> + /* Finally the sve prefix type */ > >>>> + g_string_append_printf(s, > >>>> + " count=3D\"%d\"/>", > >>>> + reg_width / 8); > >>>> + > >>>> /* Then define each register in parts for each vq */ > >>>> for (i =3D 0; i < 32; i++) { > >>>> g_string_append_printf(s, > >>>> " >>>> - " regnum=3D\"%d\" group=3D\"vector\"= " > >>>> - " type=3D\"vq\"/>", > >>>> + " regnum=3D\"%d\" type=3D\"svev\"/>"= , > >>>> i, reg_width, base_reg++); > >>>> info->num++; > >>>> } > >>>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, > int base_reg) > >>>> " regnum=3D\"%d\" group=3D\"float\"" > >>>> " type=3D\"int\"/>", base_reg++); > >>>> info->num +=3D 2; > >>>> - /* > >>>> - * Predicate registers aren't so big they are worth splitting u= p > >>>> - * but we do need to define a type to hold the array of quad > >>>> - * references. > >>>> - */ > >>>> - g_string_append_printf(s, > >>>> - " count=3D\"%d\"/>", > >>>> - cpu->sve_max_vq); > >>>> + > >>>> for (i =3D 0; i < 16; i++) { > >>>> g_string_append_printf(s, > >>>> " >>>> - " regnum=3D\"%d\" group=3D\"vector\"= " > >>>> - " type=3D\"vqp\"/>", > >>>> + " regnum=3D\"%d\" type=3D\"svep\"/>"= , > >>>> i, cpu->sve_max_vq * 16, base_reg++)= ; > >>>> info->num++; > >>>> } > >>>> g_string_append_printf(s, > >>>> " >>>> " regnum=3D\"%d\" group=3D\"vector\"" > >>>> - " type=3D\"vqp\"/>", > >>>> + " type=3D\"svep\"/>", > >>>> cpu->sve_max_vq * 16, base_reg++); > >>>> g_string_append_printf(s, > >>>> " >>>> - " regnum=3D\"%d\" group=3D\"vector\"" > >>>> - " type=3D\"uint32\"/>", > >>>> + " regnum=3D\"%d\" type=3D\"int\"/>", > >>>> base_reg++); > >>>> info->num +=3D 2; > >>>> g_string_append_printf(s, ""); > >>>> diff --git a/target/arm/helper.c b/target/arm/helper.c > >>>> index 5ab3f5ace3..8a492465d6 100644 > >>>> --- a/target/arm/helper.c > >>>> +++ b/target/arm/helper.c > >>>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, > GByteArray *buf, int reg) > >>>> * while the ZCR works in Vector Quads (VQ) which is 128bit > chunks. > >>>> */ > >>>> int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1= ; > >>>> - return gdb_get_reg32(buf, vq * 2); > >>>> + return gdb_get_reg64(buf, vq * 2); > >>>> } > >>>> default: > >>>> /* gdbstub asked for something out our range */ > >>>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > >>>> index 972cf73c31..b9ef169c1a 100644 > >>>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > >>>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py > >>>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): > >>>> except gdb.error: > >>>> report(False, "checking zregs (out of range)") > >>>> > >>>> + # Check the aliased V registers are set and GDB has correct= ly > >>>> + # created them for us having recognised and handled SVE. > >>>> + try: > >>>> + for i in range(0, 16): > >>>> + val_z =3D gdb.parse_and_eval("$z0.b.u[%d]" % i) > >>>> + val_v =3D gdb.parse_and_eval("$v0.b.u[%d]" % i) > >>>> + report(int(val_z) =3D=3D int(val_v), > >>>> + "v0.b.u[%d] =3D=3D z0.b.u[%d]" % (i, i)) > >>>> + except gdb.error: > >>>> + report(False, "checking vregs (out of range)") > >>>> + > >>>> > >>>> def run_test(): > >>>> "Run through the tests one by one" > >>>> > >> > >> > > > -- > Alex Benn=C3=A9e > --0000000000005f3cb005b943359b Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
This is not ideal. GDB should probably have a way to negot= iate available types.

On Tue, 19 Jan 2021 at 12:57, Alex Benn=C3=A9e <alex.bennee@linaro.org> wrote= :

Claudio Fontana <c= fontana@suse.de> writes:

> On 1/19/21 3:50 PM, Alex Benn=C3=A9e wrote:
>>
>> Claudio Fontana <cfontana@suse.de> writes:
>>
>>> Hi Alex,
>>>
>>> after updating to latest master today, I am getting the follow= ing error with
>>>
>>> make check-tcg
>>>
>>> qemu-system-aarch64: -gdb unix:path=3D/tmp/tmp9ru5tgk8qemu-gdb= stub/gdbstub.socket,server: info: QEMU waiting for connection on: disconnec= ted:unix:/tmp/tmp9ru5tgk8qemu-gdbstub/gdbstub.socket,server
>>> warning: while parsing target description (at line 47): Vector= "svevhf" references undefined type "ieee_half"
>>> warning: Could not load XML target description; ignoring
>>> qemu-system-aarch64: QEMU: Terminated via GDBstub
>>>
>>> Seems to indicate it is "ieee_half" -related?
>>
>> *sigh*
>>
>> yes - it is. I thought this was solved by the GDB version check in=
>> 14/30. What does your gdb report?
>
>
> $ gdb --version
> GNU gdb (GDB; openSUSE Leap 15.2) 8.3.1
> Copyright (C) 2019 Free Software Foundation, Inc.
> License GPLv3+: GNU GPL version 3 or later <http://gnu.org/l= icenses/gpl.html>
> This is free software: you are free to change and redistribute it.
> There is NO WARRANTY, to the extent permitted by law.
>
> gdb --configuration
> This GDB was configured as follows:
>=C2=A0 =C2=A0 configure --host=3Dx86_64-suse-linux --target=3Dx86_64-su= se-linux
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-auto-load-dir= =3D$debugdir:$datadir/auto-load
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-auto-load-safe-= path=3D$debugdir:$datadir/auto-load
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-expat
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-gdb-datadir=3D/= usr/share/gdb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-jit-reader-dir= =3D/usr/lib64/gdb
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --without-libunwind-ia= 64
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-lzma
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --without-babeltrace >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-intel-pt
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --disable-libmcheck >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-mpfr
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-python=3D/usr >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --without-guile
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --disable-source-highl= ight
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-separate-debug-= dir=3D/usr/lib/debug
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 --with-system-gdbinit= =3D/etc/gdbinit
>
>
> does this help?

So it looks like TDESC_TYPE_IEEE_HALF was only implemented in GDB 9.1
and there is no probing possible during the gdbstub connection. I guess
I can either go back to stubbing it out (which would break gdb's SVE understanding) or up our minimum GDB version check for running tests.
That would mean less people test GDB (or at least until the distros
catch up) but considering it was zero people not too long ago maybe
that's acceptable?

>
> Let me know if more info is needed. Thanks!
>
> Claudio
>
>
>>
>>>
>>> Thanks,
>>>
>>> Claudio
>>>
>>> On 1/15/21 2:08 PM, Alex Benn=C3=A9e wrote:
>>>> While GDB can work with any XML description given to it th= ere is
>>>> special handling for SVE registers on the GDB side which m= akes the
>>>> users life a little better. The changes aren't that ma= jor and all the
>>>> registers save the $vg reported the same. All that changes= is:
>>>>
>>>>=C2=A0 =C2=A0- report org.gnu.gdb.aarch64.sve
>>>>=C2=A0 =C2=A0- use gdb nomenclature for names and types
>>>>=C2=A0 =C2=A0- minor re-ordering of the types to match refe= rence
>>>>=C2=A0 =C2=A0- re-enable ieee_half (as we know gdb supports= it now)
>>>>=C2=A0 =C2=A0- $vg is now a 64 bit int
>>>>=C2=A0 =C2=A0- check $vN and $zN aliasing in test
>>>>
>>>> Signed-off-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
>>>> Reviewed-by: Luis Machado <luis.machado@linaro.org>
>>>> Message-Id: <20210108224256.2321-11-alex.bennee= @linaro.org>
>>>>
>>>> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c >>>> index 866595b4f1..a8fff2a3d0 100644
>>>> --- a/target/arm/gdbstub.c
>>>> +++ b/target/arm/gdbstub.c
>>>> @@ -195,22 +195,17 @@ static const struct TypeSize vec_lan= es[] =3D {
>>>>=C2=A0 =C2=A0 =C2=A0 { "uint128", 128, 'q'= ;, 'u' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "int128", 128, 'q'= , 's' },
>>>>=C2=A0 =C2=A0 =C2=A0 /* 64 bit */
>>>> +=C2=A0 =C2=A0 { "ieee_double", 64, 'd',= 'f' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "uint64", 64, 'd',= 'u' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "int64", 64, 'd', = 's' },
>>>> -=C2=A0 =C2=A0 { "ieee_double", 64, 'd',= 'f' },
>>>>=C2=A0 =C2=A0 =C2=A0 /* 32 bit */
>>>> +=C2=A0 =C2=A0 { "ieee_single", 32, 's',= 'f' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "uint32", 32, 's',= 'u' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "int32", 32, 's', = 's' },
>>>> -=C2=A0 =C2=A0 { "ieee_single", 32, 's',= 'f' },
>>>>=C2=A0 =C2=A0 =C2=A0 /* 16 bit */
>>>> +=C2=A0 =C2=A0 { "ieee_half", 16, 'h', &= #39;f' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "uint16", 16, 'h',= 'u' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "int16", 16, 'h', = 's' },
>>>> -=C2=A0 =C2=A0 /*
>>>> -=C2=A0 =C2=A0 =C2=A0* TODO: currently there is no reliabl= e way of telling
>>>> -=C2=A0 =C2=A0 =C2=A0* if the remote gdb actually understa= nds ieee_half so
>>>> -=C2=A0 =C2=A0 =C2=A0* we don't expose it in the targe= t description for now.
>>>> -=C2=A0 =C2=A0 =C2=A0* { "ieee_half", 16, 'h= ', 'f' },
>>>> -=C2=A0 =C2=A0 =C2=A0*/
>>>>=C2=A0 =C2=A0 =C2=A0 /* bytes */
>>>>=C2=A0 =C2=A0 =C2=A0 { "uint8", 8, 'b', &= #39;u' },
>>>>=C2=A0 =C2=A0 =C2=A0 { "int8", 8, 'b', &#= 39;s' },
>>>> @@ -223,17 +218,16 @@ int arm_gen_dynamic_svereg_xml(CPUSt= ate *cs, int base_reg)
>>>>=C2=A0 =C2=A0 =C2=A0 GString *s =3D g_string_new(NULL);
>>>>=C2=A0 =C2=A0 =C2=A0 DynamicGDBXMLInfo *info =3D &cpu-&= gt;dyn_svereg_xml;
>>>>=C2=A0 =C2=A0 =C2=A0 g_autoptr(GString) ts =3D g_string_new= ("");
>>>> -=C2=A0 =C2=A0 int i, bits, reg_width =3D (cpu->sve_max= _vq * 128);
>>>> +=C2=A0 =C2=A0 int i, j, bits, reg_width =3D (cpu->sve_= max_vq * 128);
>>>>=C2=A0 =C2=A0 =C2=A0 info->num =3D 0;
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_printf(s, "<?xml vers= ion=3D\"1.0\"?>");
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s, "<!D= OCTYPE target SYSTEM \"gdb-target.dtd\">");
>>>> -=C2=A0 =C2=A0 g_string_append_printf(s, "<feature= name=3D\"org.qemu.gdb.aarch64.sve\">");
>>>> +=C2=A0 =C2=A0 g_string_append_printf(s, "<feature= name=3D\"org.gnu.gdb.aarch64.sve\">");
>>>>=C2=A0
>>>>=C2=A0 =C2=A0 =C2=A0 /* First define types and totals in a = whole VL */
>>>>=C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(vec_la= nes); i++) {
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int count =3D reg_width = / vec_lanes[i].size;
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_printf(ts, "vq%= d%c%c", count,
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 vec_lanes[i].sz, vec_lanes[i].suffix);
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_printf(ts, "sve= v%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s= ,
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<vector= id=3D\"%s\" type=3D\"%s\" count=3D\"%d\"/>= ;",
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ts->str, vec_= lanes[i].gdb_type, count);
>>>> @@ -243,39 +237,37 @@ int arm_gen_dynamic_svereg_xml(CPUSt= ate *cs, int base_reg)
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0* signed and potentially float v= ersions of each size from 128 to
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0* 8 bits.
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>>>> -=C2=A0 =C2=A0 for (bits =3D 128; bits >=3D 8; bits /= =3D 2) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int count =3D reg_width / bit= s;
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s, &qu= ot;<union id=3D\"vq%dn\">", count);
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SI= ZE(vec_lanes); i++) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (vec_lanes[i= ].size =3D=3D bits) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g= _string_append_printf(s, "<field name=3D\"%c\" type=3D\&q= uot;vq%d%c%c\"/>",
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0vec_lanes[i].suffix,
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0count,
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0vec_lanes[i].sz, vec_lanes[i].suffix);
>>>> +=C2=A0 =C2=A0 for (bits =3D 128, i =3D 0; bits >=3D 8;= bits /=3D 2, i++) {
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 const char suf[] =3D { 'q= ', 'd', 's', 'h', 'b' };
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s, &qu= ot;<union id=3D\"svevn%c\">", suf[i]);
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (j =3D 0; j < ARRAY_SI= ZE(vec_lanes); j++) {
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (vec_lanes[j= ].size =3D=3D bits) {
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g= _string_append_printf(s, "<field name=3D\"%c\" type=3D\&q= uot;svev%c%c\"/>",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0vec_lanes[j].suffix,
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0vec_lanes[j].sz, vec_lanes[j].suffix);
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append(s, "= ;</union>");
>>>>=C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 /* And now the final union of unions *= /
>>>> -=C2=A0 =C2=A0 g_string_append(s, "<union id=3D\&q= uot;vq\">");
>>>> -=C2=A0 =C2=A0 for (bits =3D 128; bits >=3D 8; bits /= =3D 2) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 int count =3D reg_width / bit= s;
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SI= ZE(vec_lanes); i++) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (vec_lanes[i= ].size =3D=3D bits) {
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g= _string_append_printf(s, "<field name=3D\"%c\" type=3D\&q= uot;vq%dn\"/>",
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0vec_lanes[i].sz, count);
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 b= reak;
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>>>> +=C2=A0 =C2=A0 g_string_append(s, "<union id=3D\&q= uot;svev\">");
>>>> +=C2=A0 =C2=A0 for (bits =3D 128, i =3D 0; bits >=3D 8;= bits /=3D 2, i++) {
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 const char suf[] =3D { 'q= ', 'd', 's', 'h', 'b' };
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s, &qu= ot;<field name=3D\"%c\" type=3D\"svevn%c\"/>"= ;,
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0suf[i], suf[i]);
>>>>=C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_append(s, "</union>= ;");
>>>>=C2=A0
>>>> +=C2=A0 =C2=A0 /* Finally the sve prefix type */
>>>> +=C2=A0 =C2=A0 g_string_append_printf(s,
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<vector id=3D\"svep\= " type=3D\"uint8\" count=3D\"%d\"/>",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reg_width / 8);
>>>> +
>>>>=C2=A0 =C2=A0 =C2=A0 /* Then define each register in parts = for each vq */
>>>>=C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < 32; i++) {
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s= ,
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<reg na= me=3D\"z%d\" bitsize=3D\"%d\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\&qu= ot;%d\" group=3D\"vector\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"= ;vq\"/>",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\&qu= ot;%d\" type=3D\"svev\"/>",
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0i, reg_width, ba= se_reg++);
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 info->num++;
>>>>=C2=A0 =C2=A0 =C2=A0 }
>>>> @@ -287,31 +279,22 @@ int arm_gen_dynamic_svereg_xml(CPUSt= ate *cs, int base_reg)
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\"%d\&quo= t; group=3D\"float\""
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"int\"= ;/>", base_reg++);
>>>>=C2=A0 =C2=A0 =C2=A0 info->num +=3D 2;
>>>> -=C2=A0 =C2=A0 /*
>>>> -=C2=A0 =C2=A0 =C2=A0* Predicate registers aren't so b= ig they are worth splitting up
>>>> -=C2=A0 =C2=A0 =C2=A0* but we do need to define a type to = hold the array of quad
>>>> -=C2=A0 =C2=A0 =C2=A0* references.
>>>> -=C2=A0 =C2=A0 =C2=A0*/
>>>> -=C2=A0 =C2=A0 g_string_append_printf(s,
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<vector id=3D\"vqp\&= quot; type=3D\"uint16\" count=3D\"%d\"/>",
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu->sve_max_vq);
>>>> +
>>>>=C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < 16; i++) {
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s= ,
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<reg na= me=3D\"p%d\" bitsize=3D\"%d\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\&qu= ot;%d\" group=3D\"vector\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"= ;vqp\"/>",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\&qu= ot;%d\" type=3D\"svep\"/>",
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0i, cpu->sve_m= ax_vq * 16, base_reg++);
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 info->num++;
>>>>=C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s,
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<reg name=3D\"ff= r\" bitsize=3D\"%d\""
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\"%d\&quo= t; group=3D\"vector\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"vqp\"/&g= t;",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"svep\"/&= gt;",
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu->sve_max_vq * 16, base_= reg++);
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s,
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"<reg name=3D\"vg= \" bitsize=3D\"64\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\"%d\" g= roup=3D\"vector\""
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" type=3D\"uint32\"= />",
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" regnum=3D\"%d\" t= ype=3D\"int\"/>",
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0base_reg++);
>>>>=C2=A0 =C2=A0 =C2=A0 info->num +=3D 2;
>>>>=C2=A0 =C2=A0 =C2=A0 g_string_append_printf(s, "</f= eature>");
>>>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>>>> index 5ab3f5ace3..8a492465d6 100644
>>>> --- a/target/arm/helper.c
>>>> +++ b/target/arm/helper.c
>>>> @@ -276,7 +276,7 @@ static int arm_gdb_get_svereg(CPUARMSt= ate *env, GByteArray *buf, int reg)
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* while the ZCR wo= rks in Vector Quads (VQ) which is 128bit chunks.
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int vq =3D sve_zcr_len_f= or_el(env, arm_current_el(env)) + 1;
>>>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg32(buf, vq = * 2);
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg64(buf, vq = * 2);
>>>>=C2=A0 =C2=A0 =C2=A0 }
>>>>=C2=A0 =C2=A0 =C2=A0 default:
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* gdbstub asked for som= ething out our range */
>>>> diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b= /tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>>>> index 972cf73c31..b9ef169c1a 100644
>>>> --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>>>> +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
>>>> @@ -40,6 +40,17 @@ class TestBreakpoint(gdb.Breakpoint): >>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 except gdb.error:
>>>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 report(Fal= se, "checking zregs (out of range)")
>>>>=C2=A0
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 # Check the aliased V registe= rs are set and GDB has correctly
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 # created them for us having = recognised and handled SVE.
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 try:
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for i in range(= 0, 16):
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 v= al_z =3D gdb.parse_and_eval("$z0.b.u[%d]" % i)
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 v= al_v =3D gdb.parse_and_eval("$v0.b.u[%d]" % i)
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r= eport(int(val_z) =3D=3D int(val_v),
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0"v0.b.u[%d] =3D=3D z0.b.u[%d]" % (i, i= ))
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 except gdb.error:
>>>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 report(False, &= quot;checking vregs (out of range)")
>>>> +
>>>>=C2=A0
>>>>=C2=A0 def run_test():
>>>>=C2=A0 =C2=A0 =C2=A0 "Run through the tests one by one= "
>>>>
>>
>>


--
Alex Benn=C3=A9e
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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id y59sm13043562ede.59.2021.01.19.08.37.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Jan 2021 08:37:04 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [RFC PATCH v2 01/20] migration/vmstate: Restrict vmstate_dummy to user-mode To: Peter Maydell , Juan Quintela , "Dr. David Alan Gilbert" Cc: Laurent Vivier , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Eduardo Habkost , Andrew Jeffery , Mark Cave-Ayland , Andrew Baumann , QEMU Developers , Joel Stanley , qemu-arm , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Paolo Bonzini , Subbaraya Sundeep , Artyom Tarasenko , Gerd Hoffmann References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-2-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <004525a7-e8bb-9316-6ad5-ba5765471639@amsat.org> Date: Tue, 19 Jan 2021 17:37:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:37:09 -0000 On 1/19/21 2:50 PM, Peter Maydell wrote: > On Sun, 17 Jan 2021 at 19:24, Philippe Mathieu-Daudé wrote: >> >> 'vmstate_dummy' is special and only used for user-mode. Rename >> it to something more specific. >> It was introduced restricted to user-mode in commit c71c3e99b8 >> ("Add a vmstate_dummy struct for CONFIG_USER_ONLY") but this >> restriction was later removed in commit 6afc14e92ac ("migration: >> Fix warning caused by missing declaration of vmstate_dummy"). >> Avoid the missing declaration warning by adding a stub for the >> symbol, and restore the #ifdef'ry. > > So what is the actual use of vmstate_dummy ? I had a grep > through and as far as I can see the points where vmstate_cpu_common > is used are all in softmmu-only code. No clue, maybe simply remnant from unfinished work? > I tried this patch > and QEMU seems to compile OK: > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 140fa32a5e3..a827417a4d8 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -1131,8 +1131,6 @@ bool target_words_bigendian(void); > > #ifdef CONFIG_SOFTMMU > extern const VMStateDescription vmstate_cpu_common; > -#else > -#define vmstate_cpu_common vmstate_dummy > #endif > > #define VMSTATE_CPU() { \ Great! Maybe even restricting VMSTATE_CPU() to softmmu-only: -- >8 -- @@ -1131,9 +1131,6 @@ bool target_words_bigendian(void); #ifdef CONFIG_SOFTMMU extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif #define VMSTATE_CPU() { \ .name = "parent_obj", \ @@ -1142,6 +1139,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags = VMS_STRUCT, \ .offset = 0, \ } +#endif #endif /* NEED_CPU_H */ --- I'll wait if David/Juan have any comment, else respin based on your patch. Thanks, Phil. From MAILER-DAEMON Tue Jan 19 11:53:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uGI-0007dt-I4 for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 11:53:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uGH-0007bH-0i for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:53:45 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:39031) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uGF-0002A1-CB for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:53:44 -0500 Received: by mail-ed1-x536.google.com with SMTP id b21so13527721edy.6 for ; Tue, 19 Jan 2021 08:53:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pdvFCGCnfU+8VT2E5bpBPH3G9762bVnLk37eqDLYaWc=; b=AIozRlL/yU8cn0QuT1TnRSSwIh1mNMl2d/NpI2Gi+98HnvftU4jXihra+D5itBdDMX SLFOQH95rWVgNpxncJb4m6g8sTGSd4mxysfHpyE6iCDuh6qDNUVpeE5SCWLBxcPg86qN omQhecD+vVNrdjeIVct2rBgEwVfxDdUG/JlsqXeEPMLvx4SZ6ghfVC4P9W/PXqQ4I3Wo ST+xPZQIDWvisylApw2vOLZ4soNCQ6BdKMt/S3elQXFmnd8est2yhAgr2QqUKf254/FT 5zAFkKt6Fn6ajlp/LneoZGBSdTVtKYRBr26X/75Nj6JtGwY8uBeu1TQi6+9RuNJEbiLl ECOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=pdvFCGCnfU+8VT2E5bpBPH3G9762bVnLk37eqDLYaWc=; b=R5oPdEO/3fx7PkFhSrUDoSo4tRSELa9KPKBQ2Y1xY4fnDM05iFfufcrZQUZKxmjFve pp0tlAJx2qw/T4uVhXoQ9kw4u3JCxhZP/Ro9P8qOjlo27qPJOV/6UjaG4d9+AkDkYXFv TF0Wvib+BNHvybIBUA1YkspMyIRbYhypLV1aITiD1X+AD6pB3NuXswzRFeCAR8EpqeAv ifpgreOy3L9FBWVzB++z+RL2ZKl+g7oHCzlFZv+dTZ6cryM6GK1/bfHPL5Y/+BTWZsPd +pLI5F3lid5ttsS6cbBYQetdMRNTFvGajV80o04ItyXOMkG94fMFEYmVS0eoyxjOFyKs vwMw== X-Gm-Message-State: AOAM533yH5hVFCmGAbMvQgaxawp225cbPoJ8GvWoIDte/J9PHSB/S/26 KCoV+5gsVDkbpRGLZ8PyoOUl0XY3x7baa4qVfjk3Sg== X-Google-Smtp-Source: ABdhPJyFn1TerrsRkYW2sdYXZqZE6XyqxHhXIQRRGczHyA+Ktt/aChrGTWso2shsJGJ0LmHtfYEd4AHx/tPZl8scvgA= X-Received: by 2002:a05:6402:1383:: with SMTP id b3mr4013015edv.100.1611075221597; Tue, 19 Jan 2021 08:53:41 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-2-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-2-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 16:53:30 +0000 Message-ID: Subject: Re: [PATCH v3 01/21] tcg: Introduce target-specific page data for user-only To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:53:45 -0000 On Fri, 15 Jan 2021 at 22:46, Richard Henderson wrote: > > This data can be allocated by page_alloc_target_data() and > released by page_set_flags(start, end, prot | PAGE_RESET). > > This data will be used to hold tag memory for AArch64 MTE. > > Signed-off-by: Richard Henderson > --- > v3: Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 11:56:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uJ5-0002QD-Ry for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 11:56:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uJ2-0002O8-7J for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:56:37 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:33240) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uIx-0002YF-Sa for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:56:36 -0500 Received: by mail-ej1-x62b.google.com with SMTP id by1so23088528ejc.0 for ; Tue, 19 Jan 2021 08:56:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Xd+BCL3iHWTvFRJb3pccf1sHG27Ef6cwmx5A6nCxzVY=; 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Tue, 19 Jan 2021 08:56:30 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-4-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-4-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 16:56:19 +0000 Message-ID: Subject: Re: [PATCH v3 03/21] exec: Use uintptr_t for guest_base To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:56:37 -0000 On Fri, 15 Jan 2021 at 22:46, Richard Henderson wrote: > > This is more descriptive than 'unsigned long'. > No functional change, since these match on all linux+bsd hosts. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 11:57:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uJZ-0002p4-OS for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:57:07 -0000 On Fri, 15 Jan 2021 at 22:46, Richard Henderson wrote: > > This is more descriptive than 'unsigned long'. > No functional change, since these match on all linux+bsd hosts. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 11:58:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uKm-0003Qy-OM for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 11:58:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uKa-0003O4-FN for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:58:13 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:37487) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uKS-0002gb-PO for qemu-arm@nongnu.org; Tue, 19 Jan 2021 11:58:12 -0500 Received: by mail-ej1-x62f.google.com with SMTP id b5so13066395ejv.4 for ; Tue, 19 Jan 2021 08:58:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=oRoULs7q7/xf60wCfWU9kPfmr16BDxgD+lP1vebTTHI=; b=VbX7UytP8Z1hLcF93G7kCejalNPuvRYfxO4A2p2fEZAZowdWzqnoLzSLW2FDkuaSdM GTkCw572TGn7h9nPEfge30zypcz3a5/j+qHtDDxo8CXelxlflGVvbONAu2NVyoKAuyxV HcOT5SX5GMKpePTXCDMO4NtqOnkP1B5ill0WylZUg20ixfxKn7BwsUOUcPT0kpomg0si GdsAysQ7MRpx3BvKz3nuwe9oCaReCNcfa33tnZ825uNIvLSh8AWCzjXYXpDKpWN/jUn4 rjpQSo6OuQetxAWCanrO9dpHAIh8YJMBACtkPFd7VOXUtBA8QZ1NeA/9skkldI5ATiGO 9loQ== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 16:58:13 -0000 On Fri, 15 Jan 2021 at 22:46, Richard Henderson wrote: > > Return bool not int; pass abi_ulong not 'unsigned long'. > All callers use abi_ulong already, so the change in type > has no effect. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu_ldst.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h > index 3f9063aade..5e8878ee9b 100644 > --- a/include/exec/cpu_ldst.h > +++ b/include/exec/cpu_ldst.h > @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; > #endif > #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) > > -static inline int guest_range_valid(unsigned long start, unsigned long len) > +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) > { > return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; > } > -- Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 12:00:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uMh-00076J-Oh for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 12:00:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uMN-00073M-Bk for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:00:13 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:41147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uMF-0002rh-NA for qemu-arm@nongnu.org; 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Tue, 19 Jan 2021 08:59:54 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-10-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-10-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 16:59:43 +0000 Message-ID: Subject: Re: [PATCH v3 09/21] linux-user: Do not use guest_addr_valid for h2g_valid To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 17:00:17 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > This is the only use of guest_addr_valid that does not begin > with a guest address, but a host address being transformed to > a guest address. > > We will shortly adjust guest_addr_valid to handle guest memory > tags, and the host address should not be subjected to that. > > Move h2g_valid adjacent to the other h2g macros. > > Signed-off-by: Richard Henderson > --- > v3: Ditch type changes; retain true for HLB <= GAM (pmm). Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 12:04:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uQY-0001yv-IX for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 12:04:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54124) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uQN-0001wK-F2 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:04:11 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:41201) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uQK-0003WU-TW for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:04:11 -0500 Received: by mail-ej1-x62c.google.com with SMTP id g12so29543025ejf.8 for ; Tue, 19 Jan 2021 09:04:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nYcrjI7Zodna8WKQcC7mBl2yfQhUtgvneKR3bEJRrCY=; b=tL158EHd5uPPZVDUf//PyoQwapEB3TME6Ea+mtUE6slXW735PNjSpuYd7AFeMtWpqx SB1BlSx8Tl1o6mSR5ZBN5J0O+RqvGUf2gHSDjgxznuH/20KhZHkZ5EOOvS8HtrEhgkd1 YRG71bw5E5aUejf8q0S846a8g4iqyEIZu22u92/phWX3i8ByAgwqocqD3WzXEntxPx4q 41beMzR+r4/uo0z/IaXrSNvhOm/8Mhex7i8qXRNz+cschU676CU3u0yCtaDAOXYeNJG1 TTDSivK2EBMqPBFXLAE55k90VWt9Lpa1+VulguzqRzda12wl42q1Nz5OFbIYttDsqPWh EYNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nYcrjI7Zodna8WKQcC7mBl2yfQhUtgvneKR3bEJRrCY=; b=krgLhLoltTJc6RxSKRyn/GlDDCACmY0EOkJFD7ebtX20Vz4NfNeKthkT3qF51tzC2a OMqrrW+5iIAAkr9pG8njT2tQO59getSvDCjWjysVJHu1cg7KYgf+lsTaW8qaGimvc+/B MzyQMeSQvT+RN7ZvkyX53C6ZPL9lrtEMeioaGb8lydjN3js86roDQrbrfT5blRL5XMpJ yi0SCl6NTuwvHa6DuSxSxL5KRu1xWfCbmlmVRQ9TLoUQQOBj0DHbapioIe6ROQbRFoHB Ndq3Rh/NvIFcsGgp8YzY34plffJwyBAdj+DQjE+M1mASZUPqV0HEnPhlidg1k7y6MR6k iqpw== X-Gm-Message-State: AOAM533ycMMHB7806YPRb/43RJ6GgmkSgVBo+ICrMCfZO56aIVoifI+k gB/nAAYL2IHtLZsjAl8qXCfB27OB4bF1vAH6N/MpZQ== X-Google-Smtp-Source: ABdhPJw7FDKs57GkcqV8Vq/S7hNre57Of9edLDCowAFXW+4p/7VVGuux9bi1ngDfMZbL2ndhwgKAQgOMJoN83kOJi+w= X-Received: by 2002:a17:906:2747:: with SMTP id a7mr3702048ejd.250.1611075844753; Tue, 19 Jan 2021 09:04:04 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-11-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-11-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 17:03:53 +0000 Message-ID: Subject: Re: [PATCH v3 10/21] linux-user: Fix guest_addr_valid vs reserved_va To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 17:04:15 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > We must always use GUEST_ADDR_MAX, because even 32-bit hosts can > use -R to restrict the memory address of the guest. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu_ldst.h | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h > index 4e6ef3d542..e62f4fba00 100644 > --- a/include/exec/cpu_ldst.h > +++ b/include/exec/cpu_ldst.h > @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; > /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ > #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) > > -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS > -#define guest_addr_valid(x) (1) > -#else > -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) > -#endif > +static inline bool guest_addr_valid(abi_ulong x) > +{ > + return x <= GUEST_ADDR_MAX; > +} Reviewed-by: Peter Maydell Looking back at patch 9 -- if we always check against GUEST_ADDR_MAX here, should we also do that for h2g_valid(), or are the two uses different ? (The v2->v3 changes list for patch 9 suggests we may have had this discussion previously, but I forget the details...) thanks -- PMM From MAILER-DAEMON Tue Jan 19 12:07:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uTu-0004uk-0X for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 12:07:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1uTs-0004q2-6s for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:07:48 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:42553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1uTq-0004Ml-I2 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:07:47 -0500 Received: by mail-ej1-x630.google.com with SMTP id r12so18187885ejb.9 for ; Tue, 19 Jan 2021 09:07:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; 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Tue, 19 Jan 2021 09:07:42 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-16-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-16-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 19 Jan 2021 17:07:31 +0000 Message-ID: Subject: Re: [PATCH v3 15/21] target/arm: Split out syndrome.h from internals.h To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 17:07:48 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Move everything related to syndromes to a new file, > which can be shared with linux-user. > > Signed-off-by: Richard Henderson > --- > target/arm/internals.h | 245 +----------------------------------- > target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 274 insertions(+), 244 deletions(-) > create mode 100644 target/arm/syndrome.h Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 12:12:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1uYT-0001Yl-0t for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 17:12:30 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > A proper syndrome is required to fill in the proper si_code. > Use page_get_flags to determine permission vs translation for user-only. > > Signed-off-by: Richard Henderson > --- > v3: Use syndrome.h, arm_deliver_fault. Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Tue Jan 19 12:41:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l1v0v-0001EO-KG for mharc-qemu-arm@gnu.org; Tue, 19 Jan 2021 12:41:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l1v0t-00018Z-89 for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:41:55 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:36344) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l1v0r-0001Vw-LM for qemu-arm@nongnu.org; Tue, 19 Jan 2021 12:41:54 -0500 Received: by mail-pg1-x533.google.com with SMTP id c132so13411773pga.3 for ; Tue, 19 Jan 2021 09:41:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=teoFIjHTxxemjEhw6yQFudejaRj5aytDCRbSfMh6bro=; b=YBNPM2mDKEPhp6+dBaXjGiIyS3nhsBSpE0cZlwoRu/WzmrOqcShFoNbN9iVKK7j9rY pWyyB9EoIWKOEQA2K2TOjgnnBB7r/zJ76q/RAdliL+zj5cSRnoZf8V1lH5EtmPNFmdJz yan2oprXGKPjNje7MEVo7OKYPn3PJjYj/Tqer2JWUDSPEn8+n0Bp0k4U/Jsskyue/+5S kMCTIMZAEBJzJRyrVGXxYylQEnqT/i16JkxMdwb3YTLxnVjpjxGY3tkpclGSbyis6WBk TtTxvm7U13MKalnkSClOl5UGOdl++jqJjc3d8dEAzVob4OfzPLoSQVXZpFABy569+T3M krvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=teoFIjHTxxemjEhw6yQFudejaRj5aytDCRbSfMh6bro=; b=uZfmcg1CZ0veEcatv32gWg1pFXcNwSoEnnFCN+MViOJR2cnwfmjpR07AsndECvo4db l4gWQOX0H3+Xl2ALWLL4/Nt7uNohRFO11cQW53oXW0rIvNULjnLgHoNGWO76L7Lrwmw2 YKIN/rMlU4YrFdpD2E2LtJAjZK23sz9TG7j+JBox55bULcGn11EaU2TfW1M6QPSFfmAK 0rkClGnZ6TnHgg0dwybXsgN1U4FVVzN8tSFnsq4rAdbUDI7AOv1JC18LA4SOmYdgQ3uM GyctVHPuFr/0aiXLd5noGhcBmf6H8o5UYS7GaWUa+GJy7FzSMJX25BYNVjCo+c1zJBLW kCaQ== X-Gm-Message-State: AOAM531CkH2PPGrEPA9uoTJHiP+ECKUVp17NcsBJVAtSjjBxNAoNuU3E 9BzFCFMv16E5Q4BFr399OXrTZ7glkwUqUA== X-Google-Smtp-Source: ABdhPJwPo7EnAX5RxZCBDh19WQY734oWk4H5pUYqxhJucFNoOzx4JmrmWqAZ4gdbRuIfc65eyZRy6g== X-Received: by 2002:a62:4e43:0:b029:1a4:684c:87ea with SMTP id c64-20020a624e430000b02901a4684c87eamr5374554pfb.75.1611078111306; Tue, 19 Jan 2021 09:41:51 -0800 (PST) Received: from [192.168.3.43] (cpe-66-75-72-126.hawaii.res.rr.com. [66.75.72.126]) by smtp.gmail.com with ESMTPSA id l3sm4036008pjz.27.2021.01.19.09.41.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Jan 2021 09:41:50 -0800 (PST) Subject: Re: [PATCH v3 10/21] linux-user: Fix guest_addr_valid vs reserved_va To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-11-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <390dffbb-84e6-ff01-2117-758d50871ecd@linaro.org> Date: Tue, 19 Jan 2021 07:41:47 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2021 17:41:55 -0000 On 1/19/21 7:03 AM, Peter Maydell wrote: > On Fri, 15 Jan 2021 at 22:47, Richard Henderson > wrote: >> >> We must always use GUEST_ADDR_MAX, because even 32-bit hosts can >> use -R to restrict the memory address of the guest. >> >> Signed-off-by: Richard Henderson >> --- >> include/exec/cpu_ldst.h | 9 ++++----- >> 1 file changed, 4 insertions(+), 5 deletions(-) >> >> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h >> index 4e6ef3d542..e62f4fba00 100644 >> --- a/include/exec/cpu_ldst.h >> +++ b/include/exec/cpu_ldst.h >> @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; >> /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ >> #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) >> >> -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS >> -#define guest_addr_valid(x) (1) >> -#else >> -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) >> -#endif >> +static inline bool guest_addr_valid(abi_ulong x) >> +{ >> + return x <= GUEST_ADDR_MAX; >> +} > > Reviewed-by: Peter Maydell > > Looking back at patch 9 -- if we always check against > GUEST_ADDR_MAX here, should we also do that for h2g_valid(), > or are the two uses different ? > (The v2->v3 changes list for patch 9 suggests we may have > had this discussion previously, but I forget the details...) I had thought we should always check GUEST_ADDR_MAX. If something is outside G_A_M, then it doesn't fit into the reserved_va that either (1) the user requested via the command-line or (2) for which the guest has constraints (e.g. TARGET_VIRT_ADDR_SPACE_BITS for sh4 or mips, requiring 31-bit addresses). r~ From MAILER-DAEMON Wed Jan 20 04:28:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l29mU-0000ve-6v for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 04:28:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l29mS-0000sV-Bg for qemu-arm@nongnu.org; Wed, 20 Jan 2021 04:28:00 -0500 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]:42642) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l29mO-000561-U9 for qemu-arm@nongnu.org; Wed, 20 Jan 2021 04:28:00 -0500 Received: by mail-lf1-x133.google.com with SMTP id b26so33226760lff.9 for ; Wed, 20 Jan 2021 01:27:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vEZQ1y1NFv0BYfclNl3dBsXayOat5WWlg5bfIXSoTYA=; b=An9qOYzcBaft+pwc8SwyMU1x8szv07tmYUaHXWtMx0rhfMbbtbd8lrVoS8KPaVCbYz 0zbfXBQmx80bffjo18xV6hHO+74gMNV/TFdPxJNzTLuPvJwXrAASpb1D/KE8/dGOR/oH E9kpTLJU9EfrVi0yu0lDPJJgaPRbIFcqGhbY/7tnFVwbaPXW/U3iL7SvhaNd8RatvVBz zWZJhGJi9uxly7M9JAMMJxDPJC3pT9FaJQJgnionDfOko6YcxKL1t6uirH9j6reWFjxZ JGZYj4Ueyv/zL2F/YMVJKHUZys/+smAVNnMaiNobiaHv3M0WU1oJeVTjusw9uHC8LpBu MiAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vEZQ1y1NFv0BYfclNl3dBsXayOat5WWlg5bfIXSoTYA=; b=kCAEP7+9noy4n55Gpfvg1GKArduXLPt/XC7G3mRAD1EW8/CrYJLUsAyX7M/efOBA/e R5WdJjpnSrfd0xrrgiVRSJNNVIV6qvebVnk1FgcwW7J6DonKntUddJTKbevf7Onw55DC GaU1GIq3NqwvlHoghzfwDs2aHFS002BpQ1Rn2UezB2suaaUZIsrF/UVUwysQQPZvTyy7 L5+v4wc4J+2wpSm7cjC6O4rzfPic+O8PsrAOvrZyfoiYXfvhpOZNmc4/biTDQtlnlfHh szEAMGQ6/D6xpXf36ItAGtnhFD1mD0lzFLOGVs039hUyuI6B4T0SsGCo1HYgxsnrg+4P xRKQ== X-Gm-Message-State: AOAM5327oOWfvxquyWT+/P9tjVw5AngVVdFWqOUGXtXix4qLwRakqwuI LUR1mhMFBvoBbABOILS/azZNaOxJ9lRKWQ== X-Google-Smtp-Source: ABdhPJwlJwzkojLGqx4IDCv++ee5OYpA8HbNiO1F3j13daBvOiA/znYvOu5U5j3FFzfjGeq2Dg0l9Q== X-Received: by 2002:a19:991:: with SMTP id 139mr3774083lfj.637.1611134874895; Wed, 20 Jan 2021 01:27:54 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id r81sm147479lff.215.2021.01.20.01.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 01:27:54 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv8 2/3] arm-virt: refactor gpios creation Date: Wed, 20 Jan 2021 12:27:47 +0300 Message-Id: <20210120092748.14789-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210120092748.14789-1-maxim.uvarov@linaro.org> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 09:28:00 -0000 No functional change. Just refactor code to better support secure and normal world gpios. Signed-off-by: Maxim Uvarov --- hw/arm/virt.c | 64 ++++++++++++++++++++++++++++++++++----------------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..c427ce5f81 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -820,17 +820,43 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms) +static void create_gpio_keys(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + gpio_key_dev = sysbus_create_simple("gpio-key", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", + "label", "GPIO Key Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", + KEY_POWER); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", + "gpios", phandle, 3, 0); +} + +static void create_gpio_devices(const VirtMachineState *vms, int gpio, + MemoryRegion *mem) { char *nodename; DeviceState *pl061_dev; - hwaddr base = vms->memmap[VIRT_GPIO].base; - hwaddr size = vms->memmap[VIRT_GPIO].size; - int irq = vms->irqmap[VIRT_GPIO]; + hwaddr base = vms->memmap[gpio].base; + hwaddr size = vms->memmap[gpio].size; + int irq = vms->irqmap[gpio]; const char compat[] = "arm,pl061\0arm,primecell"; + SysBusDevice *s; - pl061_dev = sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); nodename = g_strdup_printf("/pl061@%" PRIx64, base); @@ -847,21 +873,17 @@ static void create_gpio(const VirtMachineState *vms) qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); - gpio_key_dev = sysbus_create_simple("gpio-key", -1, - qdev_get_gpio_in(pl061_dev, 3)); - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); - - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", - "label", "GPIO Key Poweroff"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", - KEY_POWER); - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", - "gpios", phandle, 3, 0); + if (gpio != VIRT_GPIO) { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); + } g_free(nodename); + + /* Child gpio devices */ + if (gpio == VIRT_GPIO) { + create_gpio_keys(vms, pl061_dev, phandle); + } } static void create_virtio_devices(const VirtMachineState *vms) @@ -1990,7 +2012,7 @@ static void machvirt_init(MachineState *machine) if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms); + create_gpio_devices(vms, VIRT_GPIO, sysmem); } /* connect powerdown request */ -- 2.17.1 From MAILER-DAEMON Wed Jan 20 04:28:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l29mU-0000wS-DU for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 04:28:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l29mT-0000tZ-3o for qemu-arm@nongnu.org; Wed, 20 Jan 2021 04:28:01 -0500 Received: from mail-lj1-x22c.google.com ([2a00:1450:4864:20::22c]:37741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l29mP-00055p-0H for qemu-arm@nongnu.org; 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Wed, 20 Jan 2021 01:27:53 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id r81sm147479lff.215.2021.01.20.01.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 01:27:53 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv8 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Wed, 20 Jan 2021 12:27:46 +0300 Message-Id: <20210120092748.14789-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210120092748.14789-1-maxim.uvarov@linaro.org> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 09:28:01 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov Reviewed-by: Hao Wu --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..7714fa0dc4 --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Wed Jan 20 04:28:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l29mV-0000yl-6e for mharc-qemu-arm@gnu.org; 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Wed, 20 Jan 2021 01:27:51 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv8 0/3] arm-virt: add secure pl061 for reset/power down Date: Wed, 20 Jan 2021 12:27:45 +0300 Message-Id: <20210120092748.14789-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 09:28:01 -0000 v8: - use gpio 0 and 1, align dtb with kernel gpio-restart, gpio-poweroff, change define names, trigger on upper front. (Peter Maydell). v7: - same as v6, but resplit patches: patch 2 no function changes and refactor gpio setup for virt platfrom and patch 3 adds secure gpio. v6: - 64k align gpio memory region (Andrew Jones) - adjusted memory region to map this address in the corresponding atf patch v5: - removed vms flag, added fdt (Andrew Jones) - added patch3 to combine secure and non secure pl061. It has to be more easy to review if this changes are in the separate patch. v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/886965bddb0624bdf85103efb2b39fd4eb73d89b Maxim Uvarov (3): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: refactor gpios creation arm-virt: add secure pl061 for reset/power down hw/arm/Kconfig | 1 + hw/arm/virt.c | 111 ++++++++++++++++++++++++++++++++++-------- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 ++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 2 + 6 files changed, 167 insertions(+), 21 deletions(-) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Wed Jan 20 04:28:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l29mV-00010X-Rr for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 04:28:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l29mU-0000wD-AR for qemu-arm@nongnu.org; Wed, 20 Jan 2021 04:28:02 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:41664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l29mQ-00056F-HT for qemu-arm@nongnu.org; Wed, 20 Jan 2021 04:28:02 -0500 Received: by mail-lf1-x131.google.com with SMTP id s26so33160820lfc.8 for ; Wed, 20 Jan 2021 01:27:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nyATO8LViNbtJAlpgYG4nBlTtGVbfXPoadAOe5B+tpw=; b=FeHkgiFL+Fqz/wKvODdXMXYqEbs8/4CqVnO+3nx31pdBGfH2tCQTLcS1kXkmvZT5sa rypEJZ3HxEDcvwC8X3SfbXXPUT1GZfSq/mEScbw73g0f9DGHwToS1O9E6dp2QkJ3nJH0 p4XqvLsP9azFOrJnmur9JjmELvj//HmY1TW7SRo3v14fgEnRiH6D6o/9y+TRBboxaaRz aittoJmJnRcMsNyJesNrAKYBY+RA7EI88mmFKJaQFpvhpNIYYIGwIqhT7Cr95gcdy/e/ paX5zk8pp8/YXz5LHbdPE7UIrkilfOHiW4jCa3fWoOB+XOpzYB6qcHX1CQ1aRpwW/tzq RT9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nyATO8LViNbtJAlpgYG4nBlTtGVbfXPoadAOe5B+tpw=; b=cWmXWZfaTJy3v84jRqxFEq/aMr8oDKRNMRLdfi8TNtyynnKZd/xPNuBSE07EKMB/qw NzNZi55Tl0rlQJwcfcW+0uERGXCqPLceCgJxk43T+V3ItRzaukVshBdqUUf9TKeX77JF H3dI/WuWY4rypckDQGmjezTxR/D5BaYfUtHYYFJrzH0Wg8YuDHoQW7Q/PmsImzb47V0I DOZjjD8UP6BqzMKM79Cokpy9fnHWlwtF1g6zPMBXY2Okc6UY5bfUsgxMMyvc4T48hOxv CvOfbSgxlkyaZNibTx5o7637sFnZR5SZDmUiHOvFiPYfxILS1bC25TnggVjZIwqmvWD2 KUMg== X-Gm-Message-State: AOAM531cdMyIbZGAsMH8ztlTpW4l0K/fUgyEkm5pe1wfgPWFApILRYAg jwKSS1vIDcDPTinsgyQ4js6N5RRdvo8FbQ== X-Google-Smtp-Source: ABdhPJyjQ1UmZzu7C6VCpG7dm4oHh449cI+yMWMTk+16zMNgPygzTCicKcLbgA+xZGLKu8IQWmdy+w== X-Received: by 2002:a19:7ed2:: with SMTP id z201mr1918924lfc.310.1611134876232; Wed, 20 Jan 2021 01:27:56 -0800 (PST) Received: from localhost.localdomain ([2.92.195.184]) by smtp.gmail.com with ESMTPSA id r81sm147479lff.215.2021.01.20.01.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 01:27:55 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv8 3/3] arm-virt: add secure pl061 for reset/power down Date: Wed, 20 Jan 2021 12:27:48 +0300 Message-Id: <20210120092748.14789-4-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210120092748.14789-1-maxim.uvarov@linaro.org> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 09:28:02 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 50 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c427ce5f81..060a5f492e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -841,6 +842,43 @@ static void create_gpio_keys(const VirtMachineState *vms, "gpios", phandle, 3, 0); } +#define SECURE_GPIO_POWEROFF 0 +#define SECURE_GPIO_REBOOT 1 + +static void create_gpio_pwr(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + DeviceState *gpio_pwr_dev; + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_REBOOT, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "compatible", + "gpio-poweroff"); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-poweroff", + "gpios", phandle, SECURE_GPIO_POWEROFF, 0); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "secure-status", + "okay"); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-restart"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "compatible", + "gpio-restart"); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-restart", + "gpios", phandle, SECURE_GPIO_REBOOT, 0); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "secure-status", + "okay"); +} + static void create_gpio_devices(const VirtMachineState *vms, int gpio, MemoryRegion *mem) { @@ -883,6 +921,8 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio, /* Child gpio devices */ if (gpio == VIRT_GPIO) { create_gpio_keys(vms, pl061_dev, phandle); + } else { + create_gpio_pwr(vms, pl061_dev, phandle); } } @@ -2015,6 +2055,10 @@ static void machvirt_init(MachineState *machine) create_gpio_devices(vms, VIRT_GPIO, sysmem); } + if (vms->secure && !vmc->no_secure_gpio) { + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2630,8 +2674,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..6f6c85ffcf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { -- 2.17.1 From MAILER-DAEMON Wed Jan 20 05:57:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2BAf-0006vB-04 for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 05:57:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2BAc-0006sY-01 for qemu-arm@nongnu.org; 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Wed, 20 Jan 2021 05:56:56 -0500 X-MC-Unique: XV0LmhzPNpiBFFGW_iosUw-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0A24F107ACE3; Wed, 20 Jan 2021 10:56:54 +0000 (UTC) Received: from work-vm (ovpn-115-106.ams2.redhat.com [10.36.115.106]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 95C9160C6A; Wed, 20 Jan 2021 10:56:46 +0000 (UTC) Date: Wed, 20 Jan 2021 10:56:43 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Mark Cave-Ayland , qemu-arm@nongnu.org, Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric?= Le Goater , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier Subject: Re: [RFC PATCH v2 19/20] stubs/vmstate: Add VMSTATE_END_OF_LIST to vmstate_user_mode_cpu_dummy Message-ID: <20210120105643.GC2930@work-vm> References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-20-f4bug@amsat.org> MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-20-f4bug@amsat.org> User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.195, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 10:57:03 -0000 * Philippe Mathieu-Daudé (f4bug@amsat.org) wrote: > Add a name and end marker to the vmstate_user_mode_cpu_dummy variable. > > Reported-by: Dr. David Alan Gilbert > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Dr. David Alan Gilbert > --- > stubs/vmstate.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/stubs/vmstate.c b/stubs/vmstate.c > index f561f9f39bd..1d0e03e233b 100644 > --- a/stubs/vmstate.c > +++ b/stubs/vmstate.c > @@ -2,7 +2,12 @@ > #include "migration/vmstate.h" > > #if defined(CONFIG_USER_ONLY) > -const VMStateDescription vmstate_user_mode_cpu_dummy = {}; > +const VMStateDescription vmstate_user_mode_cpu_dummy = { > + .name = "cpu_common_user", > + .fields = (VMStateField[]) { > + VMSTATE_END_OF_LIST() > + }, > +}; > #endif > > const VMStateDescription vmstate_no_state_to_migrate = { > -- > 2.26.2 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Wed Jan 20 06:03:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2BGw-0003me-Bu for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 06:03:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2BGu-0003l0-N7 for qemu-arm@nongnu.org; Wed, 20 Jan 2021 06:03:32 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:33117) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l2BGs-0004XM-06 for qemu-arm@nongnu.org; Wed, 20 Jan 2021 06:03:32 -0500 DKIM-Signature: v=1; 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Wed, 20 Jan 2021 11:03:24 +0000 (UTC) Received: from work-vm (ovpn-115-106.ams2.redhat.com [10.36.115.106]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1276271CB0; Wed, 20 Jan 2021 11:03:16 +0000 (UTC) Date: Wed, 20 Jan 2021 11:03:14 +0000 From: "Dr. David Alan Gilbert" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: Peter Maydell , Juan Quintela , Laurent Vivier , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , Eduardo Habkost , Andrew Jeffery , Mark Cave-Ayland , Andrew Baumann , QEMU Developers , Joel Stanley , qemu-arm , =?iso-8859-1?Q?C=E9dric?= Le Goater , Paolo Bonzini , Subbaraya Sundeep , Artyom Tarasenko , Gerd Hoffmann Subject: Re: [RFC PATCH v2 01/20] migration/vmstate: Restrict vmstate_dummy to user-mode Message-ID: <20210120110314.GD2930@work-vm> References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-2-f4bug@amsat.org> <004525a7-e8bb-9316-6ad5-ba5765471639@amsat.org> MIME-Version: 1.0 In-Reply-To: <004525a7-e8bb-9316-6ad5-ba5765471639@amsat.org> User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.195, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 11:03:32 -0000 * Philippe Mathieu-Daud (f4bug@amsat.org) wrote: > On 1/19/21 2:50 PM, Peter Maydell wrote: > > On Sun, 17 Jan 2021 at 19:24, Philippe Mathieu-Daud wrote: > >> > >> 'vmstate_dummy' is special and only used for user-mode. Rename > >> it to something more specific. > >> It was introduced restricted to user-mode in commit c71c3e99b8 > >> ("Add a vmstate_dummy struct for CONFIG_USER_ONLY") but this > >> restriction was later removed in commit 6afc14e92ac ("migration: > >> Fix warning caused by missing declaration of vmstate_dummy"). > >> Avoid the missing declaration warning by adding a stub for the > >> symbol, and restore the #ifdef'ry. > > > > So what is the actual use of vmstate_dummy ? I had a grep > > through and as far as I can see the points where vmstate_cpu_common > > is used are all in softmmu-only code. > > No clue, maybe simply remnant from unfinished work? Not sure either; but it looks like Paolo fixed some of it up in d9f24bf5724 a few months ago; prior to that cpu_exec_unrealizefn used it even on a USER_ONLY build. Dave > > I tried this patch > > and QEMU seems to compile OK: > > > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > > index 140fa32a5e3..a827417a4d8 100644 > > --- a/include/hw/core/cpu.h > > +++ b/include/hw/core/cpu.h > > @@ -1131,8 +1131,6 @@ bool target_words_bigendian(void); > > > > #ifdef CONFIG_SOFTMMU > > extern const VMStateDescription vmstate_cpu_common; > > -#else > > -#define vmstate_cpu_common vmstate_dummy > > #endif > > > > #define VMSTATE_CPU() { \ > > Great! Maybe even restricting VMSTATE_CPU() to softmmu-only: > > -- >8 -- > @@ -1131,9 +1131,6 @@ bool target_words_bigendian(void); > > #ifdef CONFIG_SOFTMMU > extern const VMStateDescription vmstate_cpu_common; > -#else > -#define vmstate_cpu_common vmstate_dummy > -#endif > > #define VMSTATE_CPU() { > \ > .name = "parent_obj", > \ > @@ -1142,6 +1139,7 @@ extern const VMStateDescription vmstate_cpu_common; > .flags = VMS_STRUCT, > \ > .offset = 0, > \ > } > +#endif > > #endif /* NEED_CPU_H */ > --- > > I'll wait if David/Juan have any comment, else respin based > on your patch. > > Thanks, > > Phil. > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Wed Jan 20 09:20:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2ELo-0000Tc-Ue for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 09:20:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2ELn-0000Ss-4W; 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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=DspembmaJIJarXxk54NctOgIA9U7/BNi3Xxxnni+IrE=; b=QGAPv02eDgF+grpKdA831wNUio1hrs2UJAA0kwA8eWLe8tmQA7hdwvEYXPV3Kl7qd1 YRoPmrLUfo139PFpZyL668+Zgjl8imcgJaAI1Z0DGazDu3ioFITN/SjVsflkaXTriugn O5rhY5Jf4Ze3u67rAD+j2TU96wxK7N0JP0sn8k91oFV465NoTYECkI8XR+GMPpEsNQdP 4Oy+RmzDqemnMEuzXj9ShZ9X0YLobS5dQakC/eFYYzaSbj/AEA+x2XewBR9I3FhDQb2d o/V3xJl4i96+jpxaFhpQwwhoeZAaglh8z2sjjgrqF6x9iLs6kZKhAeT62XxW2fjB6cfR V+Mg== X-Gm-Message-State: AOAM532+Ikfu39ydM76wuq4xwW/+8q2WMc896ERYdQoJt5kLodreF82y A7m/SHPmjcxWZsjHjn49oYw6TsnJEoAF05PEGZk= X-Google-Smtp-Source: ABdhPJzXtqMz7rmBJSMUnKJ2EbDe6Zw31DGnpl1pn7Bppl3waF1ywD+hnxl0trAXU+Ya+8B70eRXKPrts0IMj+PtYig= X-Received: by 2002:a17:907:68c:: with SMTP id wn12mr6528914ejb.41.1611152439986; Wed, 20 Jan 2021 06:20:39 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> <20210119130113.GA28306@fralle-msi> In-Reply-To: <20210119130113.GA28306@fralle-msi> From: Bin Meng Date: Wed, 20 Jan 2021 22:20:25 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Francisco Iglesias Cc: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 14:20:47 -0000 Hi Francisco, On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias wrote: > > Hi Bin, > > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > > Hi Francisco, > > > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > > wrote: > > > > > > Hi Bin, > > > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > > Hi Francisco, > > > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > > wrote: > > > > > > > > > > Hi Bin, > > > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > > Hi Francisco, > > > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many = follow-up > > > > > > > > bytes are expected to be received after it receives a comma= nd. For > > > > > > > > example, depending on the address mode, either 3-byte addre= ss or > > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are requir= ed after > > > > > > > > sending the address bytes, and the dummy cycles need to be = counted > > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is = in byte. > > > > > > > > It is not in bit, or cycle. However for some reason the mod= el has > > > > > > > > been using the number of dummy cycles for s->needed_bytes. = The right > > > > > > > > approach is to convert the number of dummy cycles to bytes = based on > > > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast = Read Quad > > > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6= * 4 / 8). > > > > > > > > > > > > > > While not being the original implementor I must assume that a= bove solution was > > > > > > > considered but not chosen by the developers due to it is inac= curacy (it > > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a m= ultiple of 8, > > > > > > > meaning that if the controller is wrongly programmed to gener= ate 7 the error > > > > > > > wouldn't be caught and the controller will still be considere= d "correct"). Now > > > > > > > that we have this detail in the implementation I'm in favor o= f keeping it, this > > > > > > > also because the detail is already in use for catching exactl= y above error. > > > > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed soluti= on here > > > > > > was ever considered, otherwise all SPI controller models suppor= ting > > > > > > software generation should have been found out seriously broken= long > > > > > > time ago! > > > > > > > > > > > > > > > The controllers you are referring to might lack support for comma= nds requiring > > > > > dummy clock cycles but I really hope they work with the other com= mands? If so I > > > > > > > > I am not sure why you view dummy clock cycles as something special > > > > that needs some special support from the SPI controller. For the ca= se > > > > 1 controller, it's nothing special from the controller perspective, > > > > just like sending out a command, or address bytes, or data. The > > > > controller just shifts data bit by bit from its tx fifo and that's = it. > > > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > > > sent via a regular data (the case 1 controller) in the tx fifo, or > > > > automatically generated (case 2 controller) by the hardware. > > > > > > Ok, I'll try to explain my view point a little differently. For that = we also > > > need to keep in mind that QEMU models HW, and any binary that runs on= a HW > > > board supported in QEMU should ideally run on that board inside QEMU = aswell > > > (this can be a bare metal application equaly well as a modified u-boo= t/Linux > > > using SPI commands with a non multiple of 8 number of dummy clock cyc= les). > > > > > > Once functionality has been introduced into QEMU it is not easy to kn= ow which > > > intentional or untentional features provided by the functionality are= being > > > used by users. One of the (perhaps not well known) features I'm aware= of that > > > is in use and is provided by the accurate dummy clock cycle modeling = inside > > > m25p80 is the be ability to test drivers accurately regarding the dum= my clock > > > cycles (even when using commands with a non-multiple of 8 number of d= ummy clock > > > cycles), but there might be others aswell. So by removing this functi= onality > > > above use case will brake, this since those test will not be reliable= . > > > Furthermore, since users tend to be creative it is not possible to kn= ow if > > > there are other use cases that will be affected. This means that in c= ase [1] > > > needs to be followed the safe path is to add functionality instead of= removing. > > > Luckily it also easier in this case, see below. > > > > I understand there might be users other than U-Boot/Linux that use an > > odd number of dummy bits (not multiple of 8). If your concern was > > about model behavior changes, sure I can update > > qemu/docs/system/deprecated.rst to mention that some flashes in the > > m25p80 model now implement dummy cycles as bytes. > > Yes, something like that. My concern is that since this functionality has= been > in tree for while, users have found known or unknown features that got > introduced by it. By removing the functionality (and the known/uknown fea= tures) > we are riscing to brake our user's use cases (currently I'm aware of one > feature/use case but it is not unlikely that there are more). [1] states = that > "In general features are intended to be supported indefinitely once intro= duced > into QEMU", to me that makes very much sense because the opposite would m= ean > that we were not reliable. So in case [1] needs to be honored it looks to= be > safer to add functionality instead of removing (and riscing the removal o= f use > cases/features). Luckily I still believe in this case that it will be eas= ier to > go forward (even if I also agree on what you are saying below about what = I > proposed). > Even if the implementation is buggy and we need to keep the buggy implementation forever? I think that's why qemu/docs/system/deprecated.rst was created for deprecating such feature. > > > > > > > > > > > don't think it is fair to call them 'seriously broken' (and else = we should > > > > > probably let the maintainers know about it). Most likely the lack= of support > > > > > > > > I called it "seriously broken" because current implementation only > > > > considered one type of SPI controllers while completely ignoring th= e > > > > other type. > > > > > > If we change view and see this from the perspective of m25p80, it mod= els the > > > commands a certain way and provides an API that the SPI controllers n= eed to > > > implement for interacting with it. It is true that there are SPI cont= rollers > > > referred to above that do not support the portion of that API that co= rresponds > > > to commands with dummy clock cycles, but I don't think it is true tha= t this is > > > broken since there is also one SPI controller that has a working impl= ementation > > > of m25p80's full API also when transfering through a tx fifo (use cas= e 1). But > > > as mentioned above, by doing a minor extension and improvement to m25= p80's API > > > and allow for toggling the accuracy from dummy clock cycles to dummy = bytes [1] > > > will still be honored as in the same time making it possible to have = full > > > support for the API in the SPI controllers that currently do not (ple= ase reread > > > the proposal in my previous reply that attempts to do this). I myself= see this > > > as win/win situation, also because no controller should need modifica= tions. > > > > > > > I am afraid your proposal does not work. Your proposed new device > > property 'model_dummy_bytes' to select to convert the accurate dummy > > clock cycle count to dummy bytes inside m25p80, is hard to justify as > > a property to the flash itself, as the behavior is tightly coupled to > > how the SPI controller works. > > I agree on above. I decided though that instead of posting sample code in= here > I'll post an RFC with hopefully an improved proposal. I'll cc you. About = below, > Xilinx ZynqMP GQSPI should not need any modication in a first step. > Wait, (see below) > > > > Please take a look at the Xilinx GQSPI controller, which supports both > > use cases, that the dummy cycles can be transferred via tx fifo, or > > generated by the controller automatically. Please read the example > > given in: > > > > table 24=E2=80=9022, an example of Generic FIFO Contents for Quad I= /O Read > > Command (EBh) > > > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq= -ultrascale-trm.pdf > > > > If you choose to set the m25p80 device property 'model_dummy_bytes' to > > true when working with the Xilinx GQSPI controller, you are bound to > > only allow guest software to use tx fifo to transfer the dummy cycles, > > and this is wrong. > > You missed this part. I looked at your RFC, and as I mentioned above your proposal cannot support the complicated controller like Xilinx GQSPI. Please read the example of table 24-22. With your RFC, you mandate guest software's GQSPI driver to only use hardware dummy cycle generation, which is wrong. > > > > > > > > > > > > for the commands is because no request has been made for them. Al= so there is > > > > > one controller that has support. > > > > > > > > Definitely it's not "no request". Nearly all SPI flashes support th= e > > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This= is > > > > "seriously broken" for those case 1 type controllers because they > > > > cannot read anything from the m25p80 model at all. Unless the guest > > > > software being tested only uses Read (03h) command which is not > > > > affected. But I can't find a software that uses Read instead of Fas= t > > > > Read. > > > > > > > > > > The issue you pointed out that we require the total number of d= ummy > > > > > > bits should be multiple of 8 is true, that's why I added the > > > > > > unimplemented log message in this series (patch 2/3/4) to warn = users > > > > > > if this expectation is not met. However this will not cause any= issue > > > > > > when running U-Boot or Linux, because both spi-nor drivers expe= ct the > > > > > > same assumption as we do here. > > > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_da= ta(), > > > > > > there is a logic to calculate the dummy bytes needed for fast r= ead > > > > > > command: > > > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > > op.dummy.nbytes =3D (nor->read_dummy * op.dummy.buswidth) /= 8; > > > > > > > > > > > > Note the default dummy cycles configuration for all flashes I h= ave > > > > > > looked into as of today, meets the multiple of 8 assumption. On= some > > > > > > flashes the dummy cycle number is configurable, and if it's bee= n > > > > > > configured to be an odd value, it would not work on U-Boot/Linu= x in > > > > > > the first place. > > > > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI = or QSPI > > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the control= ler fifo. > > > > > > > > For such case, driver will calculate the correct number o= f dummy > > > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 = model will > > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cyc= le implementation > > > > > > > inside m25p80. Perhaps one of the following could be looked i= nto: configurating > > > > > > > the amount, letting the spi ctrl fetch the amount from m25p80= or by inheriting > > > > > > > some functionality handling this in the SPI controller. Or a = mixture of above. > > > > > > > > > > > > Please send patches to explain this in detail how this is going= to > > > > > > work. I am open to all possible solutions. > > > > > > > > > > In that case I suggest that you instead try with a device propert= y > > > > > 'model_dummy_bytes' used to select to convert the accurate dummy = clock cycle > > > > > count to dummy bytes inside m25p80. Below is an example on how to= modify the > > > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO handlin= g. > > > > > > > > > decode_fast_read_cmd function (the other commands requiring dummy= clock cycles > > > > > can follow a similar pattern). This way the fifo mode will be abl= e to work the > > > > > way you desire while also keeping the current functionality intac= t. Suddenly > > > > > removing functionality (features) will take users by surprise. > > > > > > > > I don't think we are removing any features. This is a fix to make t= he > > > > model to be used by any SPI controllers. > > > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > > assumption for the dummy bit, which is the default configuration fo= r > > > > all flashes I have looked into so far. Can you please comment what = use > > > > case you want to support? I requested a U-Boot/Linux kernel testing= in > > > > the previous SST thread [1] against Xilinx GQSPI but there was no > > > > response. > > > > > > In [2] instructions on how to boot u-boot/Linux is found. For buildin= g the > > > various software components I followed the official doc in [3]. > > > > I see the following QEMU commands are used to test booting U-Boot/Linux= : > > > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don -m= 4G > > -serial stdio -display none -device loader,file=3Du-boot.elf -kernel > > bl31.elf -device loader,addr=3D0x40000000,file=3DImage -device > > loader,addr=3D0x2000000,file=3Dsystem.dtb > > > > I am not sure where the system.dtb gets built from? > > It is the instructions in [2] to look into. 'system.dtb' is the kernel dt= b for > zcu102 ([2] has been fixed). I created [2] purely for you, so respectfull= y I > will ask you to try a little first before asking for further guidance. > I tried, but no success. I removed the "-device loader" part for loading kernel image and the device tree, and only focused on booting U-Boot. The ATF bl31.elf was built from https://github.com/ARM-software/arm-trusted-firmware, by following build instructions at https://trustedfirmware-a.readthedocs.io/en/latest/plat/xilinx-zynqmp.html. U-Boot was built from the upstream U-Boot. $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don -m 4G -serial stdio -display none -device loader,file=3Du-boot.elf -kernel bl31.elf ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 NOTICE: BL31: v2.4(release):v2.4-228-g337e493 NOTICE: BL31: Built : 21:18:14, Jan 20 2021 ERROR: BL31: Platform Management API version error. Expected: v1.1 - Found: v0.0 ERROR: Error initializing runtime service sip_svc I also tried the Xilinx fork of ATF from https://github.com/Xilinx/arm-trusted-firmware, by following build instructions at https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842305/Build+ARM+Tr= usted+Firmware+ATF $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don -m 4G -serial stdio -display none -device loader,file=3Du-boot.elf -kernel bl31.elf ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 NOTICE: BL31: v2.2(release):xilinx-v2020.2 NOTICE: BL31: Built : 21:52:38, Jan 20 2021 ERROR: BL31: Platform Management API version error. Expected: v1.1 - Found: v0.0 ERROR: Error initializing runtime service sip_svc Then I tried to build a U-Boot from the Xilinx fork at https://github.com/Xilinx/u-boot-xlnx/, still no success. > Best regards, > Francisco Iglesias > > [1] qemu/docs/system/deprecated.rst > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zc= u102-atf-u-boot-linux.md > > Regards, Bin From MAILER-DAEMON Wed Jan 20 17:44:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDe-0003rf-Fv for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:44:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDd-0003rB-28; Wed, 20 Jan 2021 17:44:53 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45084 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDa-0001SZ-PA; Wed, 20 Jan 2021 17:44:52 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 23E0A39000FA; Wed, 20 Jan 2021 23:44:46 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 00/11] hvf: Implement Apple Silicon Support Date: Wed, 20 Jan 2021 23:44:33 +0100 Message-Id: <20210120224444.71840-1-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:53 -0000 Now that Apple Silicon is widely available, people are obviously excited to try and run virtualized workloads on them, such as Linux and Windows. This patch set implements a fully functional version to get the ball going on that. With this applied, I can successfully run both Linux and Windows as guests. I am not aware of any limitations specific to Hypervisor.framework apart from: - Live migration / savevm - gdbstub debugging (SP register) Enjoy! Alex v1 -> v2: - New patch: hvf: Actually set SIG_IPI mask - New patch: hvf: Introduce hvf vcpu struct - New patch: hvf: arm: Mark CPU as dirty on reset - Removed patch: hw/arm/virt: Disable highmem when on hypervisor.framework - Removed patch: arm: Synchronize CPU on PSCI on - Fix build on 32bit arm - Merge vcpu kick function patch into ARM enablement - Implement WFI handling (allows vCPUs to sleep) - Synchronize system registers (fixes OVMF crashes and reboot) - Don't always call cpu_synchronize_state() - Use more fine grained iothread locking - Populate aa64mmfr0 from hardware - Make safe to ctrl-C entitlement application v2 -> v3: - Removed patch: hvf: Actually set SIG_IPI mask - New patch: hvf: arm: Add support for GICv3 - New patch: hvf: arm: Implement -cpu host - Advance PC on SMC - Use cp list interface for sysreg syncs - Do not set current_cpu - Fix sysreg isread mask - Move sysreg handling to functions - Remove WFI logic again - Revert to global iothread locking v3 -> v4: - Removed patch: hvf: arm: Mark CPU as dirty on reset - New patch: hvf: Simplify post reset/init/loadvm hooks - Remove i386-softmmu target (meson.build for hvf target) - Combine both if statements (PSCI) - Use hv.h instead of Hypervisor.h for 10.15 compat - Remove manual inclusion of Hypervisor.h in common .c files - No longer include Hypervisor.h in arm hvf .c files - Remove unused exe_full variable - Reuse exe_name variable v4 -> v5: - Use g_free() on destroy v5 -> v6: - Switch SYSREG() macro order to the same as asm intrinsics Alexander Graf (10): hvf: Add hypervisor entitlement to output binaries hvf: x86: Remove unused definitions hvf: Move common code out hvf: Introduce hvf vcpu struct arm: Set PSCI to 0.2 for HVF hvf: Simplify post reset/init/loadvm hooks hvf: Add Apple Silicon support arm: Add Hypervisor.framework build target hvf: arm: Add support for GICv3 hvf: arm: Implement -cpu host Peter Collingbourne (1): arm/hvf: Add a WFI handler MAINTAINERS | 13 + accel/hvf/entitlements.plist | 8 + accel/hvf/hvf-all.c | 54 +++ accel/hvf/hvf-cpus.c | 466 +++++++++++++++++++ accel/hvf/meson.build | 7 + accel/meson.build | 1 + include/hw/core/cpu.h | 3 +- include/sysemu/hvf.h | 2 + include/sysemu/hvf_int.h | 66 +++ meson.build | 40 +- scripts/entitlement.sh | 13 + target/arm/cpu.c | 13 +- target/arm/cpu.h | 2 + target/arm/hvf/hvf.c | 856 +++++++++++++++++++++++++++++++++++ target/arm/hvf/meson.build | 3 + target/arm/kvm_arm.h | 2 - target/arm/meson.build | 2 + target/i386/hvf/hvf-cpus.c | 131 ------ target/i386/hvf/hvf-cpus.h | 25 - target/i386/hvf/hvf-i386.h | 49 +- target/i386/hvf/hvf.c | 462 +++---------------- target/i386/hvf/meson.build | 1 - target/i386/hvf/vmx.h | 24 +- target/i386/hvf/x86.c | 28 +- target/i386/hvf/x86_descr.c | 26 +- target/i386/hvf/x86_emu.c | 62 +-- target/i386/hvf/x86_mmu.c | 4 +- target/i386/hvf/x86_task.c | 12 +- target/i386/hvf/x86hvf.c | 224 ++++----- target/i386/hvf/x86hvf.h | 2 - 30 files changed, 1786 insertions(+), 815 deletions(-) create mode 100644 accel/hvf/entitlements.plist create mode 100644 accel/hvf/hvf-all.c create mode 100644 accel/hvf/hvf-cpus.c create mode 100644 accel/hvf/meson.build create mode 100644 include/sysemu/hvf_int.h create mode 100755 scripts/entitlement.sh create mode 100644 target/arm/hvf/hvf.c create mode 100644 target/arm/hvf/meson.build delete mode 100644 target/i386/hvf/hvf-cpus.c delete mode 100644 target/i386/hvf/hvf-cpus.h -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:44:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDh-0003tM-Ia for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:44:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDd-0003rK-KI; Wed, 20 Jan 2021 17:44:53 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45112 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDa-0001Sq-PA; Wed, 20 Jan 2021 17:44:53 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 4B0233900496; Wed, 20 Jan 2021 23:44:47 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 02/11] hvf: x86: Remove unused definitions Date: Wed, 20 Jan 2021 23:44:35 +0100 Message-Id: <20210120224444.71840-3-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:53 -0000 The hvf i386 has a few struct and cpp definitions that are never used. Remove them. Suggested-by: Roman Bolshakov Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- target/i386/hvf/hvf-i386.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e0edffd077..e31938e5ff 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -21,21 +21,6 @@ #include "cpu.h" #include "x86.h" -#define HVF_MAX_VCPU 0x10 - -extern struct hvf_state hvf_global; - -struct hvf_vm { - int id; - struct hvf_vcpu_state *vcpus[HVF_MAX_VCPU]; -}; - -struct hvf_state { - uint32_t version; - struct hvf_vm *vm; - uint64_t mem_quota; -}; - /* hvf_slot flags */ #define HVF_SLOT_LOG (1 << 0) @@ -75,7 +60,6 @@ hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); /* Host specific functions */ int hvf_inject_interrupt(CPUArchState *env, int vector); -int hvf_vcpu_run(struct hvf_vcpu_state *vcpu); #endif #endif -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:44:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDj-0003un-8l for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:44:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDf-0003sm-Nr; Wed, 20 Jan 2021 17:44:56 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45200 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDd-0001V5-MB; Wed, 20 Jan 2021 17:44:55 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id BCA273900565; Wed, 20 Jan 2021 23:44:49 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 06/11] hvf: Simplify post reset/init/loadvm hooks Date: Wed, 20 Jan 2021 23:44:39 +0100 Message-Id: <20210120224444.71840-7-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:57 -0000 The hooks we have that call us after reset, init and loadvm really all just want to say "The reference of all register state is in the QEMU vcpu struct, please push it". We already have a working pushing mechanism though called cpu->vcpu_dirty, so we can just reuse that for all of the above, syncing state properly the next time we actually execute a vCPU. This fixes PSCI resets on ARM, as they modify CPU state even after the post init call has completed, but before we execute the vCPU again. To also make the scheme work for x86, we have to make sure we don't move stale eflags into our env when the vcpu state is dirty. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- accel/hvf/hvf-cpus.c | 27 +++++++-------------------- target/i386/hvf/x86hvf.c | 5 ++++- 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c index 2c6796604a..a324da2757 100644 --- a/accel/hvf/hvf-cpus.c +++ b/accel/hvf/hvf-cpus.c @@ -275,39 +275,26 @@ static void hvf_cpu_synchronize_state(CPUState *cpu) } } -static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) +static void do_hvf_cpu_synchronize_set_dirty(CPUState *cpu, + run_on_cpu_data arg) { - hvf_put_registers(cpu); - cpu->vcpu_dirty = false; + /* QEMU state is the reference, push it to HVF now and on next entry */ + cpu->vcpu_dirty = true; } static void hvf_cpu_synchronize_post_reset(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty = false; + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } static void hvf_cpu_synchronize_post_init(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty = true; + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); + run_on_cpu(cpu, do_hvf_cpu_synchronize_set_dirty, RUN_ON_CPU_NULL); } static void hvf_vcpu_destroy(CPUState *cpu) diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 0f2aeb1cf8..3111c0be4c 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -435,7 +435,10 @@ int hvf_process_events(CPUState *cpu_state) X86CPU *cpu = X86_CPU(cpu_state); CPUX86State *env = &cpu->env; - env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + if (!cpu_state->vcpu_dirty) { + /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ + env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + } if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { cpu_synchronize_state(cpu_state); -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDo-0003yE-Pk for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDe-0003rm-W3; Wed, 20 Jan 2021 17:44:55 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45100 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDa-0001Sd-P9; Wed, 20 Jan 2021 17:44:54 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id B306239003C7; Wed, 20 Jan 2021 23:44:46 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 01/11] hvf: Add hypervisor entitlement to output binaries Date: Wed, 20 Jan 2021 23:44:34 +0100 Message-Id: <20210120224444.71840-2-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:55 -0000 In macOS 11, QEMU only gets access to Hypervisor.framework if it has the respective entitlement. Add an entitlement template and automatically self sign and apply the entitlement in the build. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- v1 -> v2: - Make safe to ctrl-C v3 -> v4: - Remove unused exe_full variable - Reuse exe_name variable --- accel/hvf/entitlements.plist | 8 ++++++++ meson.build | 29 +++++++++++++++++++++++++---- scripts/entitlement.sh | 13 +++++++++++++ 3 files changed, 46 insertions(+), 4 deletions(-) create mode 100644 accel/hvf/entitlements.plist create mode 100755 scripts/entitlement.sh diff --git a/accel/hvf/entitlements.plist b/accel/hvf/entitlements.plist new file mode 100644 index 0000000000..154f3308ef --- /dev/null +++ b/accel/hvf/entitlements.plist @@ -0,0 +1,8 @@ + + + + + com.apple.security.hypervisor + + + diff --git a/meson.build b/meson.build index 3d889857a0..c667d64498 100644 --- a/meson.build +++ b/meson.build @@ -2146,9 +2146,14 @@ foreach target : target_dirs }] endif foreach exe: execs - emulators += {exe['name']: - executable(exe['name'], exe['sources'], - install: true, + exe_name = exe['name'] + exe_sign = 'CONFIG_HVF' in config_target + if exe_sign + exe_name += '-unsigned' + endif + + emulator = executable(exe_name, exe['sources'], + install: not exe_sign, c_args: c_args, dependencies: arch_deps + deps + exe['dependencies'], objects: lib.extract_all_objects(recursive: true), @@ -2156,7 +2161,23 @@ foreach target : target_dirs link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []), link_args: link_args, gui_app: exe['gui']) - } + + if exe_sign + emulators += {exe['name'] : custom_target(exe['name'], + install: true, + install_dir: get_option('bindir'), + depends: emulator, + output: exe['name'], + command: [ + meson.current_source_dir() / 'scripts/entitlement.sh', + meson.current_build_dir() / exe_name, + meson.current_build_dir() / exe['name'], + meson.current_source_dir() / 'accel/hvf/entitlements.plist' + ]) + } + else + emulators += {exe['name']: emulator} + endif if 'CONFIG_TRACE_SYSTEMTAP' in config_host foreach stp: [ diff --git a/scripts/entitlement.sh b/scripts/entitlement.sh new file mode 100755 index 0000000000..c540fa6435 --- /dev/null +++ b/scripts/entitlement.sh @@ -0,0 +1,13 @@ +#!/bin/sh -e +# +# Helper script for the build process to apply entitlements + +SRC="$1" +DST="$2" +ENTITLEMENT="$3" + +trap 'rm "$DST.tmp"' exit +cp -af "$SRC" "$DST.tmp" +codesign --entitlements "$ENTITLEMENT" --force -s - "$DST.tmp" +mv "$DST.tmp" "$DST" +trap '' exit -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDr-0003zc-7W for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDh-0003tr-SC; Wed, 20 Jan 2021 17:44:58 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45132 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDb-0001Tj-7b; Wed, 20 Jan 2021 17:44:57 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 862FC3900545; Wed, 20 Jan 2021 23:44:48 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v6 04/11] hvf: Introduce hvf vcpu struct Date: Wed, 20 Jan 2021 23:44:37 +0100 Message-Id: <20210120224444.71840-5-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:59 -0000 We will need more than a single field for hvf going forward. To keep the global vcpu struct uncluttered, let's allocate a special hvf vcpu struct, similar to how hax does it. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Alex Bennée --- v4 -> v5: - Use g_free() on destroy --- accel/hvf/hvf-cpus.c | 8 +- include/hw/core/cpu.h | 3 +- include/sysemu/hvf_int.h | 4 + target/i386/hvf/hvf.c | 102 +++++++++--------- target/i386/hvf/vmx.h | 24 +++-- target/i386/hvf/x86.c | 28 ++--- target/i386/hvf/x86_descr.c | 26 ++--- target/i386/hvf/x86_emu.c | 62 +++++------ target/i386/hvf/x86_mmu.c | 4 +- target/i386/hvf/x86_task.c | 12 +-- target/i386/hvf/x86hvf.c | 210 ++++++++++++++++++------------------ 11 files changed, 247 insertions(+), 236 deletions(-) diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c index 60f6d76bf3..2c6796604a 100644 --- a/accel/hvf/hvf-cpus.c +++ b/accel/hvf/hvf-cpus.c @@ -312,10 +312,12 @@ static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) static void hvf_vcpu_destroy(CPUState *cpu) { - hv_return_t ret = hv_vcpu_destroy(cpu->hvf_fd); + hv_return_t ret = hv_vcpu_destroy(cpu->hvf->fd); assert_hvf_ok(ret); hvf_arch_vcpu_destroy(cpu); + g_free(cpu->hvf); + cpu->hvf = NULL; } static void dummy_signal(int sig) @@ -326,6 +328,8 @@ static int hvf_init_vcpu(CPUState *cpu) { int r; + cpu->hvf = g_malloc0(sizeof(*cpu->hvf)); + /* init cpu signals */ sigset_t set; struct sigaction sigact; @@ -337,7 +341,7 @@ static int hvf_init_vcpu(CPUState *cpu) pthread_sigmask(SIG_BLOCK, NULL, &set); sigdelset(&set, SIG_IPI); - r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); + r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); cpu->vcpu_dirty = 1; assert_hvf_ok(r); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 140fa32a5e..9e1b61f63d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -281,6 +281,7 @@ struct KVMState; struct kvm_run; struct hax_vcpu_state; +struct hvf_vcpu_state; #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) @@ -464,7 +465,7 @@ struct CPUState { struct hax_vcpu_state *hax_vcpu; - int hvf_fd; + struct hvf_vcpu_state *hvf; /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 69de46db7d..9d3cb53e47 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -43,6 +43,10 @@ struct HVFState { }; extern HVFState *hvf_state; +struct hvf_vcpu_state { + int fd; +}; + void assert_hvf_ok(hv_return_t ret); int hvf_get_registers(CPUState *cpu); int hvf_put_registers(CPUState *cpu); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 8b96ecd619..08b4adecd9 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -80,11 +80,11 @@ void vmx_update_tpr(CPUState *cpu) int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); - wreg(cpu->hvf_fd, HV_X86_TPR, tpr); + wreg(cpu->hvf->fd, HV_X86_TPR, tpr); if (irr == -1) { - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); } else { - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4); } } @@ -92,7 +92,7 @@ void vmx_update_tpr(CPUState *cpu) static void update_apic_tpr(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); - int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4; + int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } @@ -194,43 +194,43 @@ int hvf_arch_init_vcpu(CPUState *cpu) } /* set VMCS control fields */ - wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, VMCS_PIN_BASED_CTLS_EXTINT | VMCS_PIN_BASED_CTLS_NMI | VMCS_PIN_BASED_CTLS_VNMI)); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, VMCS_PRI_PROC_BASED_CTLS_HLT | VMCS_PRI_PROC_BASED_CTLS_MWAIT | VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); - wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS, + wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES)); - wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, + wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0)); - wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ + wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ - wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); x86cpu = X86_CPU(cpu); x86cpu->env.xsave_buf = qemu_memalign(4096, 4096); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1); - hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); + hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); return 0; } @@ -271,16 +271,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_in } if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { env->has_error_code = true; - env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR); + env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR); } } - if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { env->hflags2 |= HF2_NMI_MASK; } else { env->hflags2 &= ~HF2_NMI_MASK; } - if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags |= HF_INHIBIT_IRQ_MASK; @@ -317,20 +317,20 @@ int hvf_vcpu_exec(CPUState *cpu) return EXCP_HLT; } - hv_return_t r = hv_vcpu_run(cpu->hvf_fd); + hv_return_t r = hv_vcpu_run(cpu->hvf->fd); assert_hvf_ok(r); /* handle VMEXIT */ - uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON); - uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION); - uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, + uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); + uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION); + uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); - uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO); + uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); hvf_store_events(cpu, ins_len, idtvec_info); - rip = rreg(cpu->hvf_fd, HV_X86_RIP); - env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS); + rip = rreg(cpu->hvf->fd, HV_X86_RIP); + env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS); qemu_mutex_lock_iothread(); @@ -360,7 +360,7 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_EPT_FAULT: { hvf_slot *slot; - uint64_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS); + uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS); if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { @@ -405,7 +405,7 @@ int hvf_vcpu_exec(CPUState *cpu) store_regs(cpu); break; } else if (!string && !in) { - RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX); + RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX); hvf_handle_io(env, port, &RAX(env), 1, size, 1); macvm_set_rip(cpu, rip + ins_len); break; @@ -421,17 +421,17 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_CPUID: { - uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); - uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX); - uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); - uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); + uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); + uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); + uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); + uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); - wreg(cpu->hvf_fd, HV_X86_RAX, rax); - wreg(cpu->hvf_fd, HV_X86_RBX, rbx); - wreg(cpu->hvf_fd, HV_X86_RCX, rcx); - wreg(cpu->hvf_fd, HV_X86_RDX, rdx); + wreg(cpu->hvf->fd, HV_X86_RAX, rax); + wreg(cpu->hvf->fd, HV_X86_RBX, rbx); + wreg(cpu->hvf->fd, HV_X86_RCX, rcx); + wreg(cpu->hvf->fd, HV_X86_RDX, rdx); macvm_set_rip(cpu, rip + ins_len); break; @@ -439,16 +439,16 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_XSETBV: { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; - uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX); - uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX); - uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX); + uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); + uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); + uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); if (ecx) { macvm_set_rip(cpu, rip + ins_len); break; } env->xcr0 = ((uint64_t)edx << 32) | eax; - wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1); + wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); macvm_set_rip(cpu, rip + ins_len); break; } @@ -487,11 +487,11 @@ int hvf_vcpu_exec(CPUState *cpu) switch (cr) { case 0x0: { - macvm_set_cr0(cpu->hvf_fd, RRX(env, reg)); + macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); break; } case 4: { - macvm_set_cr4(cpu->hvf_fd, RRX(env, reg)); + macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); break; } case 8: { @@ -527,7 +527,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_TASK_SWITCH: { - uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO); + uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO); x68_segment_selector sel = {.sel = exit_qual & 0xffff}; vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo @@ -540,8 +540,8 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_RDPMC: - wreg(cpu->hvf_fd, HV_X86_RAX, 0); - wreg(cpu->hvf_fd, HV_X86_RDX, 0); + wreg(cpu->hvf->fd, HV_X86_RAX, 0); + wreg(cpu->hvf->fd, HV_X86_RDX, 0); macvm_set_rip(cpu, rip + ins_len); break; case VMX_REASON_VMCALL: diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 24c4cdf0be..6df87116f6 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -30,6 +30,8 @@ #include "vmcs.h" #include "cpu.h" #include "x86.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "exec/address-spaces.h" @@ -179,15 +181,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip) uint64_t val; /* BUG, should take considering overlap.. */ - wreg(cpu->hvf_fd, HV_X86_RIP, rip); + wreg(cpu->hvf->fd, HV_X86_RIP, rip); env->eip = rip; /* after moving forward in rip, we need to clean INTERRUPTABILITY */ - val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); + val = rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags &= ~HF_INHIBIT_IRQ_MASK; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); } @@ -199,9 +201,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu) CPUX86State *env = &x86_cpu->env; env->hflags2 &= ~HF2_NMI_MASK; - uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); + uint32_t gi = (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } static inline void vmx_set_nmi_blocking(CPUState *cpu) @@ -210,16 +212,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu) CPUX86State *env = &x86_cpu->env; env->hflags2 |= HF2_NMI_MASK; - uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY); + uint32_t gi = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } static inline void vmx_set_nmi_window_exiting(CPUState *cpu) { uint64_t val; - val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | + val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); } @@ -228,8 +230,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUState *cpu) { uint64_t val; - val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & + val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); } diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index cd045183a8..2898bb70a8 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -62,11 +62,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, } if (GDT_SEL == sel.ti) { - base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); - limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); + base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); + limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); - limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); + base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); + limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); } if (sel.index * 8 >= limit) { @@ -85,11 +85,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, uint32_t limit; if (GDT_SEL == sel.ti) { - base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE); - limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT); + base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); + limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE); - limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT); + base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); + limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); } if (sel.index * 8 >= limit) { @@ -103,8 +103,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate) { - target_ulong base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE); - uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT); + target_ulong base = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); + uint32_t limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); memset(idt_desc, 0, sizeof(*idt_desc)); if (gate * 8 >= limit) { @@ -118,7 +118,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, bool x86_is_protected(struct CPUState *cpu) { - uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE; } @@ -136,7 +136,7 @@ bool x86_is_v8086(struct CPUState *cpu) bool x86_is_long_mode(struct CPUState *cpu) { - return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; + return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } bool x86_is_long64_mode(struct CPUState *cpu) @@ -149,13 +149,13 @@ bool x86_is_long64_mode(struct CPUState *cpu) bool x86_is_paging_mode(struct CPUState *cpu) { - uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG; } bool x86_is_pae_enabled(struct CPUState *cpu) { - uint64_t cr4 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4); + uint64_t cr4 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE; } diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index 9f539e73f6..af15c06ac5 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -48,47 +48,47 @@ static const struct vmx_segment_field { uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); + return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); } uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); + return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); } uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) { - return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); + return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); } x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) { x68_segment_selector sel; - sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); + sel.sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); return sel; } void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg) { - wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel); + wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel); } void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { - desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector); - desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base); - desc->limit = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit); - desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes); + desc->sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); + desc->base = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); + desc->limit = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); + desc->ar = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); } void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { const struct vmx_segment_field *sf = &vmx_segment_fields[seg]; - wvmcs(cpu->hvf_fd, sf->base, desc->base); - wvmcs(cpu->hvf_fd, sf->limit, desc->limit); - wvmcs(cpu->hvf_fd, sf->selector, desc->sel); - wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar); + wvmcs(cpu->hvf->fd, sf->base, desc->base); + wvmcs(cpu->hvf->fd, sf->limit, desc->limit); + wvmcs(cpu->hvf->fd, sf->selector, desc->sel); + wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar); } void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index da570e352b..5a512f6768 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -673,7 +673,7 @@ void simulate_rdmsr(struct CPUState *cpu) switch (msr) { case MSR_IA32_TSC: - val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET); + val = rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); @@ -682,16 +682,16 @@ void simulate_rdmsr(struct CPUState *cpu) val = x86_cpu->ucode_rev; break; case MSR_EFER: - val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER); + val = rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE); + val = rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE); + val = rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE); + val = rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -775,13 +775,13 @@ void simulate_wrmsr(struct CPUState *cpu) cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data); + wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -794,9 +794,9 @@ void simulate_wrmsr(struct CPUState *cpu) break; case MSR_EFER: /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data); + wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->hvf_fd); + hv_vcpu_invalidate_tlb(cpu->hvf->fd); } break; case MSR_MTRRphysBase(0): @@ -1420,21 +1420,21 @@ void load_regs(struct CPUState *cpu) CPUX86State *env = &x86_cpu->env; int i = 0; - RRX(env, R_EAX) = rreg(cpu->hvf_fd, HV_X86_RAX); - RRX(env, R_EBX) = rreg(cpu->hvf_fd, HV_X86_RBX); - RRX(env, R_ECX) = rreg(cpu->hvf_fd, HV_X86_RCX); - RRX(env, R_EDX) = rreg(cpu->hvf_fd, HV_X86_RDX); - RRX(env, R_ESI) = rreg(cpu->hvf_fd, HV_X86_RSI); - RRX(env, R_EDI) = rreg(cpu->hvf_fd, HV_X86_RDI); - RRX(env, R_ESP) = rreg(cpu->hvf_fd, HV_X86_RSP); - RRX(env, R_EBP) = rreg(cpu->hvf_fd, HV_X86_RBP); + RRX(env, R_EAX) = rreg(cpu->hvf->fd, HV_X86_RAX); + RRX(env, R_EBX) = rreg(cpu->hvf->fd, HV_X86_RBX); + RRX(env, R_ECX) = rreg(cpu->hvf->fd, HV_X86_RCX); + RRX(env, R_EDX) = rreg(cpu->hvf->fd, HV_X86_RDX); + RRX(env, R_ESI) = rreg(cpu->hvf->fd, HV_X86_RSI); + RRX(env, R_EDI) = rreg(cpu->hvf->fd, HV_X86_RDI); + RRX(env, R_ESP) = rreg(cpu->hvf->fd, HV_X86_RSP); + RRX(env, R_EBP) = rreg(cpu->hvf->fd, HV_X86_RBP); for (i = 8; i < 16; i++) { - RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i); + RRX(env, i) = rreg(cpu->hvf->fd, HV_X86_RAX + i); } - env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS); + env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip = rreg(cpu->hvf_fd, HV_X86_RIP); + env->eip = rreg(cpu->hvf->fd, HV_X86_RIP); } void store_regs(struct CPUState *cpu) @@ -1443,20 +1443,20 @@ void store_regs(struct CPUState *cpu) CPUX86State *env = &x86_cpu->env; int i = 0; - wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env)); - wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env)); - wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env)); - wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env)); - wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env)); - wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env)); - wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env)); - wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env)); + wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env)); + wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env)); + wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env)); + wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env)); + wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env)); + wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env)); + wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env)); + wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env)); for (i = 8; i < 16; i++) { - wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i)); + wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i)); } lflags_to_rflags(env); - wreg(cpu->hvf_fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); macvm_set_rip(cpu, env->eip); } diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 882a6237ee..b7e3f8568f 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -128,7 +128,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, pt->err_code |= MMU_PAGE_PT; } - uint32_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0); + uint32_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); /* check protection */ if (cr0 & CR0_WP) { if (pt->write_access && !pte_write_access(pte)) { @@ -173,7 +173,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, { int top_level, level; bool is_large = false; - target_ulong cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3); + target_ulong cr3 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; memset(pt, 0, sizeof(*pt)); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6f04478b3a..c25c8ec88f 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -62,7 +62,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; - wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3); + wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3); env->eip = tss->eip; env->eflags = tss->eflags | 2; @@ -111,11 +111,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type) { - uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP); + uint64_t rip = rreg(cpu->hvf->fd, HV_X86_RIP); if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION && gate_type != VMCS_INTR_T_HWINTR && gate_type != VMCS_INTR_T_NMI)) { - int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH); + int ins_len = rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); macvm_set_rip(cpu, rip + ins_len); return; } @@ -174,12 +174,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc); VM_PANIC("task_switch_16"); - macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS); + macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | CR0_TS); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); store_regs(cpu); - hv_vcpu_invalidate_tlb(cpu->hvf_fd); - hv_vcpu_flush(cpu->hvf_fd); + hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_flush(cpu->hvf->fd); } diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 89b8e9d87a..0f2aeb1cf8 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -82,7 +82,7 @@ void hvf_put_xsave(CPUState *cpu_state) x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave); - if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { + if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) { abort(); } } @@ -92,19 +92,19 @@ void hvf_put_segments(CPUState *cpu_state) CPUX86State *env = &X86_CPU(cpu_state)->env; struct vmx_segment seg; - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); - /* wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]); + /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); vmx_update_tpr(cpu_state); - wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer); + wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); - macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]); - macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]); + macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]); + macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]); hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); vmx_write_segment_descriptor(cpu_state, &seg, R_CS); @@ -130,31 +130,31 @@ void hvf_put_segments(CPUState *cpu_state) hvf_set_segment(cpu_state, &seg, &env->ldt, false); vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); - hv_vcpu_flush(cpu_state->hvf_fd); + hv_vcpu_flush(cpu_state->hvf->fd); } void hvf_put_msrs(CPUState *cpu_state) { CPUX86State *env = &X86_CPU(cpu_state)->env; - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star); #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsbase); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar); #endif - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base); - hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); + hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); } @@ -164,7 +164,7 @@ void hvf_get_xsave(CPUState *cpu_state) xsave = X86_CPU(cpu_state)->env.xsave_buf; - if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) { + if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) { abort(); } @@ -203,17 +203,17 @@ void hvf_get_segments(CPUState *cpu_state) vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); - env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE); - env->cr[0] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0); + env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0); env->cr[2] = 0; - env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3); - env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4); + env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3); + env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4); - env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER); + env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER); } void hvf_get_msrs(CPUState *cpu_state) @@ -221,27 +221,27 @@ void hvf_get_msrs(CPUState *cpu_state) CPUX86State *env = &X86_CPU(cpu_state)->env; uint64_t tmp; - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs = tmp; - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp = tmp; - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip = tmp; - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star); #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsbase); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar); #endif - hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp); - env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET); + env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET); } int hvf_put_registers(CPUState *cpu_state) @@ -249,26 +249,26 @@ int hvf_put_registers(CPUState *cpu_state) X86CPU *x86cpu = X86_CPU(cpu_state); CPUX86State *env = &x86cpu->env; - wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]); - wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]); - wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]); - wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]); - wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]); - wreg(cpu_state->hvf_fd, HV_X86_R13, env->regs[13]); - wreg(cpu_state->hvf_fd, HV_X86_R14, env->regs[14]); - wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]); - wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags); - wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip); + wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]); + wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]); + wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]); + wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]); + wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]); + wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]); + wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]); + wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]); + wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip); - wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0); + wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0); hvf_put_xsave(cpu_state); @@ -276,14 +276,14 @@ int hvf_put_registers(CPUState *cpu_state) hvf_put_msrs(cpu_state); - wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]); - wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]); - wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]); - wreg(cpu_state->hvf_fd, HV_X86_DR3, env->dr[3]); - wreg(cpu_state->hvf_fd, HV_X86_DR4, env->dr[4]); - wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]); - wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]); - wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]); + wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]); + wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]); + wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]); + wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]); + wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]); + wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]); + wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]); + wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]); return 0; } @@ -293,40 +293,40 @@ int hvf_get_registers(CPUState *cpu_state) X86CPU *x86cpu = X86_CPU(cpu_state); CPUX86State *env = &x86cpu->env; - env->regs[R_EAX] = rreg(cpu_state->hvf_fd, HV_X86_RAX); - env->regs[R_EBX] = rreg(cpu_state->hvf_fd, HV_X86_RBX); - env->regs[R_ECX] = rreg(cpu_state->hvf_fd, HV_X86_RCX); - env->regs[R_EDX] = rreg(cpu_state->hvf_fd, HV_X86_RDX); - env->regs[R_EBP] = rreg(cpu_state->hvf_fd, HV_X86_RBP); - env->regs[R_ESP] = rreg(cpu_state->hvf_fd, HV_X86_RSP); - env->regs[R_ESI] = rreg(cpu_state->hvf_fd, HV_X86_RSI); - env->regs[R_EDI] = rreg(cpu_state->hvf_fd, HV_X86_RDI); - env->regs[8] = rreg(cpu_state->hvf_fd, HV_X86_R8); - env->regs[9] = rreg(cpu_state->hvf_fd, HV_X86_R9); - env->regs[10] = rreg(cpu_state->hvf_fd, HV_X86_R10); - env->regs[11] = rreg(cpu_state->hvf_fd, HV_X86_R11); - env->regs[12] = rreg(cpu_state->hvf_fd, HV_X86_R12); - env->regs[13] = rreg(cpu_state->hvf_fd, HV_X86_R13); - env->regs[14] = rreg(cpu_state->hvf_fd, HV_X86_R14); - env->regs[15] = rreg(cpu_state->hvf_fd, HV_X86_R15); + env->regs[R_EAX] = rreg(cpu_state->hvf->fd, HV_X86_RAX); + env->regs[R_EBX] = rreg(cpu_state->hvf->fd, HV_X86_RBX); + env->regs[R_ECX] = rreg(cpu_state->hvf->fd, HV_X86_RCX); + env->regs[R_EDX] = rreg(cpu_state->hvf->fd, HV_X86_RDX); + env->regs[R_EBP] = rreg(cpu_state->hvf->fd, HV_X86_RBP); + env->regs[R_ESP] = rreg(cpu_state->hvf->fd, HV_X86_RSP); + env->regs[R_ESI] = rreg(cpu_state->hvf->fd, HV_X86_RSI); + env->regs[R_EDI] = rreg(cpu_state->hvf->fd, HV_X86_RDI); + env->regs[8] = rreg(cpu_state->hvf->fd, HV_X86_R8); + env->regs[9] = rreg(cpu_state->hvf->fd, HV_X86_R9); + env->regs[10] = rreg(cpu_state->hvf->fd, HV_X86_R10); + env->regs[11] = rreg(cpu_state->hvf->fd, HV_X86_R11); + env->regs[12] = rreg(cpu_state->hvf->fd, HV_X86_R12); + env->regs[13] = rreg(cpu_state->hvf->fd, HV_X86_R13); + env->regs[14] = rreg(cpu_state->hvf->fd, HV_X86_R14); + env->regs[15] = rreg(cpu_state->hvf->fd, HV_X86_R15); - env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); - env->eip = rreg(cpu_state->hvf_fd, HV_X86_RIP); + env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + env->eip = rreg(cpu_state->hvf->fd, HV_X86_RIP); hvf_get_xsave(cpu_state); - env->xcr0 = rreg(cpu_state->hvf_fd, HV_X86_XCR0); + env->xcr0 = rreg(cpu_state->hvf->fd, HV_X86_XCR0); hvf_get_segments(cpu_state); hvf_get_msrs(cpu_state); - env->dr[0] = rreg(cpu_state->hvf_fd, HV_X86_DR0); - env->dr[1] = rreg(cpu_state->hvf_fd, HV_X86_DR1); - env->dr[2] = rreg(cpu_state->hvf_fd, HV_X86_DR2); - env->dr[3] = rreg(cpu_state->hvf_fd, HV_X86_DR3); - env->dr[4] = rreg(cpu_state->hvf_fd, HV_X86_DR4); - env->dr[5] = rreg(cpu_state->hvf_fd, HV_X86_DR5); - env->dr[6] = rreg(cpu_state->hvf_fd, HV_X86_DR6); - env->dr[7] = rreg(cpu_state->hvf_fd, HV_X86_DR7); + env->dr[0] = rreg(cpu_state->hvf->fd, HV_X86_DR0); + env->dr[1] = rreg(cpu_state->hvf->fd, HV_X86_DR1); + env->dr[2] = rreg(cpu_state->hvf->fd, HV_X86_DR2); + env->dr[3] = rreg(cpu_state->hvf->fd, HV_X86_DR3); + env->dr[4] = rreg(cpu_state->hvf->fd, HV_X86_DR4); + env->dr[5] = rreg(cpu_state->hvf->fd, HV_X86_DR5); + env->dr[6] = rreg(cpu_state->hvf->fd, HV_X86_DR6); + env->dr[7] = rreg(cpu_state->hvf->fd, HV_X86_DR7); x86_update_hflags(env); return 0; @@ -335,16 +335,16 @@ int hvf_get_registers(CPUState *cpu_state) static void vmx_set_int_window_exiting(CPUState *cpu) { uint64_t val; - val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | + val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } void vmx_clear_int_window_exiting(CPUState *cpu) { uint64_t val; - val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & + val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } @@ -380,7 +380,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) uint64_t info = 0; if (have_event) { info = vector | intr_type | VMCS_INTR_VALID; - uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON); + uint64_t reason = rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) { vmx_clear_nmi_blocking(cpu_state); } @@ -389,17 +389,17 @@ bool hvf_inject_interrupts(CPUState *cpu_state) info &= ~(1 << 12); /* clear undefined bit */ if (intr_type == VMCS_INTR_T_SWINTR || intr_type == VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); } if (env->has_error_code) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |= VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); }; } @@ -407,7 +407,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI; info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); } else { vmx_set_nmi_window_exiting(cpu_state); } @@ -419,7 +419,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) int line = cpu_get_pic_interrupt(&x86cpu->env); cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD; if (line >= 0) { - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } @@ -435,7 +435,7 @@ int hvf_process_events(CPUState *cpu_state) X86CPU *cpu = X86_CPU(cpu_state); CPUX86State *env = &cpu->env; - env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); + env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { cpu_synchronize_state(cpu_state); -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDs-0003zq-LT for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDj-0003up-8R; Wed, 20 Jan 2021 17:44:59 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45118 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDa-0001TW-P8; Wed, 20 Jan 2021 17:44:58 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id DC5E239004ED; Wed, 20 Jan 2021 23:44:47 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 03/11] hvf: Move common code out Date: Wed, 20 Jan 2021 23:44:36 +0100 Message-Id: <20210120224444.71840-4-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:59 -0000 Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's move common code out into its own accel directory. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- v3 -> v4: - Use hv.h instead of Hypervisor.h for 10.15 compat - Remove manual inclusion of Hypervisor.h in common .c files --- MAINTAINERS | 8 + accel/hvf/hvf-all.c | 54 +++++ accel/hvf/hvf-cpus.c | 462 ++++++++++++++++++++++++++++++++++++ accel/hvf/meson.build | 7 + accel/meson.build | 1 + include/sysemu/hvf_int.h | 54 +++++ target/i386/hvf/hvf-cpus.c | 131 ---------- target/i386/hvf/hvf-cpus.h | 25 -- target/i386/hvf/hvf-i386.h | 33 +-- target/i386/hvf/hvf.c | 360 +--------------------------- target/i386/hvf/meson.build | 1 - target/i386/hvf/x86hvf.c | 11 +- target/i386/hvf/x86hvf.h | 2 - 13 files changed, 596 insertions(+), 553 deletions(-) create mode 100644 accel/hvf/hvf-all.c create mode 100644 accel/hvf/hvf-cpus.c create mode 100644 accel/hvf/meson.build create mode 100644 include/sysemu/hvf_int.h delete mode 100644 target/i386/hvf/hvf-cpus.c delete mode 100644 target/i386/hvf/hvf-cpus.h diff --git a/MAINTAINERS b/MAINTAINERS index 3216387521..e589ec02e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -448,7 +448,15 @@ M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: target/i386/hvf/ + +HVF +M: Cameron Esfahani +M: Roman Bolshakov +W: https://wiki.qemu.org/Features/HVF +S: Maintained +F: accel/hvf/ F: include/sysemu/hvf.h +F: include/sysemu/hvf_int.h WHPX CPUs M: Sunil Muthuswamy diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c new file mode 100644 index 0000000000..5b415eb0ed --- /dev/null +++ b/accel/hvf/hvf-all.c @@ -0,0 +1,54 @@ +/* + * QEMU Hypervisor.framework support + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" +#include "sysemu/runstate.h" + +#include "qemu/main-loop.h" +#include "sysemu/accel.h" + +bool hvf_allowed; +HVFState *hvf_state; + +void assert_hvf_ok(hv_return_t ret) +{ + if (ret == HV_SUCCESS) { + return; + } + + switch (ret) { + case HV_ERROR: + error_report("Error: HV_ERROR"); + break; + case HV_BUSY: + error_report("Error: HV_BUSY"); + break; + case HV_BAD_ARGUMENT: + error_report("Error: HV_BAD_ARGUMENT"); + break; + case HV_NO_RESOURCES: + error_report("Error: HV_NO_RESOURCES"); + break; + case HV_NO_DEVICE: + error_report("Error: HV_NO_DEVICE"); + break; + case HV_UNSUPPORTED: + error_report("Error: HV_UNSUPPORTED"); + break; + default: + error_report("Unknown Error"); + } + + abort(); +} diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c new file mode 100644 index 0000000000..60f6d76bf3 --- /dev/null +++ b/accel/hvf/hvf-cpus.c @@ -0,0 +1,462 @@ +/* + * Copyright 2008 IBM Corporation + * 2008 Red Hat, Inc. + * Copyright 2011 Intel Corporation + * Copyright 2016 Veertu, Inc. + * Copyright 2017 The Android Open Source Project + * + * QEMU Hypervisor.framework support + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of version 2 of the GNU General Public + * License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * This file contain code under public domain from the hvdos project: + * https://github.com/mist64/hvdos + * + * Parts Copyright (c) 2011 NetApp, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "exec/address-spaces.h" +#include "exec/exec-all.h" +#include "sysemu/cpus.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" +#include "sysemu/runstate.h" +#include "qemu/guest-random.h" + +/* Memory slots */ + +struct mac_slot { + int present; + uint64_t size; + uint64_t gpa_start; + uint64_t gva; +}; + +hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) +{ + hvf_slot *slot; + int x; + for (x = 0; x < hvf_state->num_slots; ++x) { + slot = &hvf_state->slots[x]; + if (slot->size && start < (slot->start + slot->size) && + (start + size) > slot->start) { + return slot; + } + } + return NULL; +} + +struct mac_slot mac_slots[32]; + +static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) +{ + struct mac_slot *macslot; + hv_return_t ret; + + macslot = &mac_slots[slot->slot_id]; + + if (macslot->present) { + if (macslot->size != slot->size) { + macslot->present = 0; + ret = hv_vm_unmap(macslot->gpa_start, macslot->size); + assert_hvf_ok(ret); + } + } + + if (!slot->size) { + return 0; + } + + macslot->present = 1; + macslot->gpa_start = slot->start; + macslot->size = slot->size; + ret = hv_vm_map(slot->mem, slot->start, slot->size, flags); + assert_hvf_ok(ret); + return 0; +} + +static void hvf_set_phys_mem(MemoryRegionSection *section, bool add) +{ + hvf_slot *mem; + MemoryRegion *area = section->mr; + bool writeable = !area->readonly && !area->rom_device; + hv_memory_flags_t flags; + + if (!memory_region_is_ram(area)) { + if (writeable) { + return; + } else if (!memory_region_is_romd(area)) { + /* + * If the memory device is not in romd_mode, then we actually want + * to remove the hvf memory slot so all accesses will trap. + */ + add = false; + } + } + + mem = hvf_find_overlap_slot( + section->offset_within_address_space, + int128_get64(section->size)); + + if (mem && add) { + if (mem->size == int128_get64(section->size) && + mem->start == section->offset_within_address_space && + mem->mem == (memory_region_get_ram_ptr(area) + + section->offset_within_region)) { + return; /* Same region was attempted to register, go away. */ + } + } + + /* Region needs to be reset. set the size to 0 and remap it. */ + if (mem) { + mem->size = 0; + if (do_hvf_set_memory(mem, 0)) { + error_report("Failed to reset overlapping slot"); + abort(); + } + } + + if (!add) { + return; + } + + if (area->readonly || + (!memory_region_is_ram(area) && memory_region_is_romd(area))) { + flags = HV_MEMORY_READ | HV_MEMORY_EXEC; + } else { + flags = HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC; + } + + /* Now make a new slot. */ + int x; + + for (x = 0; x < hvf_state->num_slots; ++x) { + mem = &hvf_state->slots[x]; + if (!mem->size) { + break; + } + } + + if (x == hvf_state->num_slots) { + error_report("No free slots"); + abort(); + } + + mem->size = int128_get64(section->size); + mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region; + mem->start = section->offset_within_address_space; + mem->region = area; + + if (do_hvf_set_memory(mem, flags)) { + error_report("Error registering new memory slot"); + abort(); + } +} + +static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) +{ + hvf_slot *slot; + + slot = hvf_find_overlap_slot( + section->offset_within_address_space, + int128_get64(section->size)); + + /* protect region against writes; begin tracking it */ + if (on) { + slot->flags |= HVF_SLOT_LOG; + hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, + HV_MEMORY_READ); + /* stop tracking region*/ + } else { + slot->flags &= ~HVF_SLOT_LOG; + hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, + HV_MEMORY_READ | HV_MEMORY_WRITE); + } +} + +static void hvf_log_start(MemoryListener *listener, + MemoryRegionSection *section, int old, int new) +{ + if (old != 0) { + return; + } + + hvf_set_dirty_tracking(section, 1); +} + +static void hvf_log_stop(MemoryListener *listener, + MemoryRegionSection *section, int old, int new) +{ + if (new != 0) { + return; + } + + hvf_set_dirty_tracking(section, 0); +} + +static void hvf_log_sync(MemoryListener *listener, + MemoryRegionSection *section) +{ + /* + * sync of dirty pages is handled elsewhere; just make sure we keep + * tracking the region. + */ + hvf_set_dirty_tracking(section, 1); +} + +static void hvf_region_add(MemoryListener *listener, + MemoryRegionSection *section) +{ + hvf_set_phys_mem(section, true); +} + +static void hvf_region_del(MemoryListener *listener, + MemoryRegionSection *section) +{ + hvf_set_phys_mem(section, false); +} + +static MemoryListener hvf_memory_listener = { + .priority = 10, + .region_add = hvf_region_add, + .region_del = hvf_region_del, + .log_start = hvf_log_start, + .log_stop = hvf_log_stop, + .log_sync = hvf_log_sync, +}; + +static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) +{ + if (!cpu->vcpu_dirty) { + hvf_get_registers(cpu); + cpu->vcpu_dirty = true; + } +} + +static void hvf_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, + run_on_cpu_data arg) +{ + hvf_put_registers(cpu); + cpu->vcpu_dirty = false; +} + +static void hvf_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, + run_on_cpu_data arg) +{ + hvf_put_registers(cpu); + cpu->vcpu_dirty = false; +} + +static void hvf_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, + run_on_cpu_data arg) +{ + cpu->vcpu_dirty = true; +} + +static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +static void hvf_vcpu_destroy(CPUState *cpu) +{ + hv_return_t ret = hv_vcpu_destroy(cpu->hvf_fd); + assert_hvf_ok(ret); + + hvf_arch_vcpu_destroy(cpu); +} + +static void dummy_signal(int sig) +{ +} + +static int hvf_init_vcpu(CPUState *cpu) +{ + int r; + + /* init cpu signals */ + sigset_t set; + struct sigaction sigact; + + memset(&sigact, 0, sizeof(sigact)); + sigact.sa_handler = dummy_signal; + sigaction(SIG_IPI, &sigact, NULL); + + pthread_sigmask(SIG_BLOCK, NULL, &set); + sigdelset(&set, SIG_IPI); + + r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); + cpu->vcpu_dirty = 1; + assert_hvf_ok(r); + + return hvf_arch_init_vcpu(cpu); +} + +/* + * The HVF-specific vCPU thread function. This one should only run when the host + * CPU supports the VMX "unrestricted guest" feature. + */ +static void *hvf_cpu_thread_fn(void *arg) +{ + CPUState *cpu = arg; + + int r; + + assert(hvf_enabled()); + + rcu_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + + cpu->thread_id = qemu_get_thread_id(); + cpu->can_do_io = 1; + current_cpu = cpu; + + hvf_init_vcpu(cpu); + + /* signal CPU creation */ + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + do { + if (cpu_can_run(cpu)) { + r = hvf_vcpu_exec(cpu); + if (r == EXCP_DEBUG) { + cpu_handle_guest_debug(cpu); + } + } + qemu_wait_io_event(cpu); + } while (!cpu->unplug || cpu_can_run(cpu)); + + hvf_vcpu_destroy(cpu); + cpu_thread_signal_destroyed(cpu); + qemu_mutex_unlock_iothread(); + rcu_unregister_thread(); + return NULL; +} + +static void hvf_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + + /* + * HVF currently does not support TCG, and only runs in + * unrestricted-guest mode. + */ + assert(hvf_enabled()); + + cpu->thread = g_malloc0(sizeof(QemuThread)); + cpu->halt_cond = g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/HVF", + cpu->cpu_index); + qemu_thread_create(cpu->thread, thread_name, hvf_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); +} + +static const CpusAccel hvf_cpus = { + .create_vcpu_thread = hvf_start_vcpu_thread, + + .synchronize_post_reset = hvf_cpu_synchronize_post_reset, + .synchronize_post_init = hvf_cpu_synchronize_post_init, + .synchronize_state = hvf_cpu_synchronize_state, + .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm, +}; + +static int hvf_accel_init(MachineState *ms) +{ + int x; + hv_return_t ret; + HVFState *s; + + ret = hv_vm_create(HV_VM_DEFAULT); + assert_hvf_ok(ret); + + s = g_new0(HVFState, 1); + + s->num_slots = 32; + for (x = 0; x < s->num_slots; ++x) { + s->slots[x].size = 0; + s->slots[x].slot_id = x; + } + + hvf_state = s; + memory_listener_register(&hvf_memory_listener, &address_space_memory); + cpus_register_accel(&hvf_cpus); + return 0; +} + +static void hvf_accel_class_init(ObjectClass *oc, void *data) +{ + AccelClass *ac = ACCEL_CLASS(oc); + ac->name = "HVF"; + ac->init_machine = hvf_accel_init; + ac->allowed = &hvf_allowed; +} + +static const TypeInfo hvf_accel_type = { + .name = TYPE_HVF_ACCEL, + .parent = TYPE_ACCEL, + .class_init = hvf_accel_class_init, +}; + +static void hvf_type_init(void) +{ + type_register_static(&hvf_accel_type); +} + +type_init(hvf_type_init); diff --git a/accel/hvf/meson.build b/accel/hvf/meson.build new file mode 100644 index 0000000000..dfd6b68dc7 --- /dev/null +++ b/accel/hvf/meson.build @@ -0,0 +1,7 @@ +hvf_ss = ss.source_set() +hvf_ss.add(files( + 'hvf-all.c', + 'hvf-cpus.c', +)) + +specific_ss.add_all(when: 'CONFIG_HVF', if_true: hvf_ss) diff --git a/accel/meson.build b/accel/meson.build index b26cca227a..6de12ce5d5 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(files('accel.c')) +subdir('hvf') subdir('qtest') subdir('kvm') subdir('tcg') diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h new file mode 100644 index 0000000000..69de46db7d --- /dev/null +++ b/include/sysemu/hvf_int.h @@ -0,0 +1,54 @@ +/* + * QEMU Hypervisor.framework (HVF) support + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +/* header to be included in HVF-specific code */ + +#ifndef HVF_INT_H +#define HVF_INT_H + +#include + +/* hvf_slot flags */ +#define HVF_SLOT_LOG (1 << 0) + +typedef struct hvf_slot { + uint64_t start; + uint64_t size; + uint8_t *mem; + int slot_id; + uint32_t flags; + MemoryRegion *region; +} hvf_slot; + +typedef struct hvf_vcpu_caps { + uint64_t vmx_cap_pinbased; + uint64_t vmx_cap_procbased; + uint64_t vmx_cap_procbased2; + uint64_t vmx_cap_entry; + uint64_t vmx_cap_exit; + uint64_t vmx_cap_preemption_timer; +} hvf_vcpu_caps; + +struct HVFState { + AccelState parent; + hvf_slot slots[32]; + int num_slots; + + hvf_vcpu_caps *hvf_caps; +}; +extern HVFState *hvf_state; + +void assert_hvf_ok(hv_return_t ret); +int hvf_get_registers(CPUState *cpu); +int hvf_put_registers(CPUState *cpu); +int hvf_arch_init_vcpu(CPUState *cpu); +void hvf_arch_vcpu_destroy(CPUState *cpu); +int hvf_vcpu_exec(CPUState *cpu); +hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); + +#endif diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-cpus.c deleted file mode 100644 index 817b3d7452..0000000000 --- a/target/i386/hvf/hvf-cpus.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright 2008 IBM Corporation - * 2008 Red Hat, Inc. - * Copyright 2011 Intel Corporation - * Copyright 2016 Veertu, Inc. - * Copyright 2017 The Android Open Source Project - * - * QEMU Hypervisor.framework support - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of version 2 of the GNU General Public - * License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - * - * This file contain code under public domain from the hvdos project: - * https://github.com/mist64/hvdos - * - * Parts Copyright (c) 2011 NetApp, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include "qemu/osdep.h" -#include "qemu/error-report.h" -#include "qemu/main-loop.h" -#include "sysemu/hvf.h" -#include "sysemu/runstate.h" -#include "target/i386/cpu.h" -#include "qemu/guest-random.h" - -#include "hvf-cpus.h" - -/* - * The HVF-specific vCPU thread function. This one should only run when the host - * CPU supports the VMX "unrestricted guest" feature. - */ -static void *hvf_cpu_thread_fn(void *arg) -{ - CPUState *cpu = arg; - - int r; - - assert(hvf_enabled()); - - rcu_register_thread(); - - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id = qemu_get_thread_id(); - cpu->can_do_io = 1; - current_cpu = cpu; - - hvf_init_vcpu(cpu); - - /* signal CPU creation */ - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - do { - if (cpu_can_run(cpu)) { - r = hvf_vcpu_exec(cpu); - if (r == EXCP_DEBUG) { - cpu_handle_guest_debug(cpu); - } - } - qemu_wait_io_event(cpu); - } while (!cpu->unplug || cpu_can_run(cpu)); - - hvf_vcpu_destroy(cpu); - cpu_thread_signal_destroyed(cpu); - qemu_mutex_unlock_iothread(); - rcu_unregister_thread(); - return NULL; -} - -static void hvf_start_vcpu_thread(CPUState *cpu) -{ - char thread_name[VCPU_THREAD_NAME_SIZE]; - - /* - * HVF currently does not support TCG, and only runs in - * unrestricted-guest mode. - */ - assert(hvf_enabled()); - - cpu->thread = g_malloc0(sizeof(QemuThread)); - cpu->halt_cond = g_malloc0(sizeof(QemuCond)); - qemu_cond_init(cpu->halt_cond); - - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/HVF", - cpu->cpu_index); - qemu_thread_create(cpu->thread, thread_name, hvf_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); -} - -const CpusAccel hvf_cpus = { - .create_vcpu_thread = hvf_start_vcpu_thread, - - .synchronize_post_reset = hvf_cpu_synchronize_post_reset, - .synchronize_post_init = hvf_cpu_synchronize_post_init, - .synchronize_state = hvf_cpu_synchronize_state, - .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm, -}; diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-cpus.h deleted file mode 100644 index ced31b82c0..0000000000 --- a/target/i386/hvf/hvf-cpus.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Accelerator CPUS Interface - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef HVF_CPUS_H -#define HVF_CPUS_H - -#include "sysemu/cpus.h" - -extern const CpusAccel hvf_cpus; - -int hvf_init_vcpu(CPUState *); -int hvf_vcpu_exec(CPUState *); -void hvf_cpu_synchronize_state(CPUState *); -void hvf_cpu_synchronize_post_reset(CPUState *); -void hvf_cpu_synchronize_post_init(CPUState *); -void hvf_cpu_synchronize_pre_loadvm(CPUState *); -void hvf_vcpu_destroy(CPUState *); - -#endif /* HVF_CPUS_H */ diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e31938e5ff..f41f9444b4 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -18,42 +18,11 @@ #include "sysemu/accel.h" #include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "cpu.h" #include "x86.h" -/* hvf_slot flags */ -#define HVF_SLOT_LOG (1 << 0) - -typedef struct hvf_slot { - uint64_t start; - uint64_t size; - uint8_t *mem; - int slot_id; - uint32_t flags; - MemoryRegion *region; -} hvf_slot; - -typedef struct hvf_vcpu_caps { - uint64_t vmx_cap_pinbased; - uint64_t vmx_cap_procbased; - uint64_t vmx_cap_procbased2; - uint64_t vmx_cap_entry; - uint64_t vmx_cap_exit; - uint64_t vmx_cap_preemption_timer; -} hvf_vcpu_caps; - -struct HVFState { - AccelState parent; - hvf_slot slots[32]; - int num_slots; - - hvf_vcpu_caps *hvf_caps; -}; -extern HVFState *hvf_state; - -void hvf_set_phys_mem(MemoryRegionSection *, bool); void hvf_handle_io(CPUArchState *, uint16_t, void *, int, int, int); -hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); #ifdef NEED_CPU_H /* Functions exported to host specific mode */ diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ed9356565c..8b96ecd619 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -51,6 +51,7 @@ #include "qemu/error-report.h" #include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" #include "sysemu/runstate.h" #include "hvf-i386.h" #include "vmcs.h" @@ -72,171 +73,6 @@ #include "sysemu/accel.h" #include "target/i386/cpu.h" -#include "hvf-cpus.h" - -HVFState *hvf_state; - -static void assert_hvf_ok(hv_return_t ret) -{ - if (ret == HV_SUCCESS) { - return; - } - - switch (ret) { - case HV_ERROR: - error_report("Error: HV_ERROR"); - break; - case HV_BUSY: - error_report("Error: HV_BUSY"); - break; - case HV_BAD_ARGUMENT: - error_report("Error: HV_BAD_ARGUMENT"); - break; - case HV_NO_RESOURCES: - error_report("Error: HV_NO_RESOURCES"); - break; - case HV_NO_DEVICE: - error_report("Error: HV_NO_DEVICE"); - break; - case HV_UNSUPPORTED: - error_report("Error: HV_UNSUPPORTED"); - break; - default: - error_report("Unknown Error"); - } - - abort(); -} - -/* Memory slots */ -hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size) -{ - hvf_slot *slot; - int x; - for (x = 0; x < hvf_state->num_slots; ++x) { - slot = &hvf_state->slots[x]; - if (slot->size && start < (slot->start + slot->size) && - (start + size) > slot->start) { - return slot; - } - } - return NULL; -} - -struct mac_slot { - int present; - uint64_t size; - uint64_t gpa_start; - uint64_t gva; -}; - -struct mac_slot mac_slots[32]; - -static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) -{ - struct mac_slot *macslot; - hv_return_t ret; - - macslot = &mac_slots[slot->slot_id]; - - if (macslot->present) { - if (macslot->size != slot->size) { - macslot->present = 0; - ret = hv_vm_unmap(macslot->gpa_start, macslot->size); - assert_hvf_ok(ret); - } - } - - if (!slot->size) { - return 0; - } - - macslot->present = 1; - macslot->gpa_start = slot->start; - macslot->size = slot->size; - ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags); - assert_hvf_ok(ret); - return 0; -} - -void hvf_set_phys_mem(MemoryRegionSection *section, bool add) -{ - hvf_slot *mem; - MemoryRegion *area = section->mr; - bool writeable = !area->readonly && !area->rom_device; - hv_memory_flags_t flags; - - if (!memory_region_is_ram(area)) { - if (writeable) { - return; - } else if (!memory_region_is_romd(area)) { - /* - * If the memory device is not in romd_mode, then we actually want - * to remove the hvf memory slot so all accesses will trap. - */ - add = false; - } - } - - mem = hvf_find_overlap_slot( - section->offset_within_address_space, - int128_get64(section->size)); - - if (mem && add) { - if (mem->size == int128_get64(section->size) && - mem->start == section->offset_within_address_space && - mem->mem == (memory_region_get_ram_ptr(area) + - section->offset_within_region)) { - return; /* Same region was attempted to register, go away. */ - } - } - - /* Region needs to be reset. set the size to 0 and remap it. */ - if (mem) { - mem->size = 0; - if (do_hvf_set_memory(mem, 0)) { - error_report("Failed to reset overlapping slot"); - abort(); - } - } - - if (!add) { - return; - } - - if (area->readonly || - (!memory_region_is_ram(area) && memory_region_is_romd(area))) { - flags = HV_MEMORY_READ | HV_MEMORY_EXEC; - } else { - flags = HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC; - } - - /* Now make a new slot. */ - int x; - - for (x = 0; x < hvf_state->num_slots; ++x) { - mem = &hvf_state->slots[x]; - if (!mem->size) { - break; - } - } - - if (x == hvf_state->num_slots) { - error_report("No free slots"); - abort(); - } - - mem->size = int128_get64(section->size); - mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region; - mem->start = section->offset_within_address_space; - mem->region = area; - - if (do_hvf_set_memory(mem, flags)) { - error_report("Error registering new memory slot"); - abort(); - } -} - void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ @@ -276,56 +112,6 @@ void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer, } } -static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) -{ - if (!cpu->vcpu_dirty) { - hvf_get_registers(cpu); - cpu->vcpu_dirty = true; - } -} - -void hvf_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty = false; -} - -void hvf_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - hvf_put_registers(cpu); - cpu->vcpu_dirty = false; -} - -void hvf_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hvf_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty = true; -} - -void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_hvf_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) { int read, write; @@ -370,109 +156,19 @@ static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) return false; } -static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) -{ - hvf_slot *slot; - - slot = hvf_find_overlap_slot( - section->offset_within_address_space, - int128_get64(section->size)); - - /* protect region against writes; begin tracking it */ - if (on) { - slot->flags |= HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ); - /* stop tracking region*/ - } else { - slot->flags &= ~HVF_SLOT_LOG; - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ | HV_MEMORY_WRITE); - } -} - -static void hvf_log_start(MemoryListener *listener, - MemoryRegionSection *section, int old, int new) -{ - if (old != 0) { - return; - } - - hvf_set_dirty_tracking(section, 1); -} - -static void hvf_log_stop(MemoryListener *listener, - MemoryRegionSection *section, int old, int new) -{ - if (new != 0) { - return; - } - - hvf_set_dirty_tracking(section, 0); -} - -static void hvf_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - /* - * sync of dirty pages is handled elsewhere; just make sure we keep - * tracking the region. - */ - hvf_set_dirty_tracking(section, 1); -} - -static void hvf_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - hvf_set_phys_mem(section, true); -} - -static void hvf_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - hvf_set_phys_mem(section, false); -} - -static MemoryListener hvf_memory_listener = { - .priority = 10, - .region_add = hvf_region_add, - .region_del = hvf_region_del, - .log_start = hvf_log_start, - .log_stop = hvf_log_stop, - .log_sync = hvf_log_sync, -}; - -void hvf_vcpu_destroy(CPUState *cpu) +void hvf_arch_vcpu_destroy(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; - hv_return_t ret = hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd); g_free(env->hvf_mmio_buf); - assert_hvf_ok(ret); -} - -static void dummy_signal(int sig) -{ } -int hvf_init_vcpu(CPUState *cpu) +int hvf_arch_init_vcpu(CPUState *cpu) { X86CPU *x86cpu = X86_CPU(cpu); CPUX86State *env = &x86cpu->env; - int r; - - /* init cpu signals */ - sigset_t set; - struct sigaction sigact; - - memset(&sigact, 0, sizeof(sigact)); - sigact.sa_handler = dummy_signal; - sigaction(SIG_IPI, &sigact, NULL); - - pthread_sigmask(SIG_BLOCK, NULL, &set); - sigdelset(&set, SIG_IPI); init_emu(); init_decoder(); @@ -480,10 +176,6 @@ int hvf_init_vcpu(CPUState *cpu) hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); env->hvf_mmio_buf = g_new(char, 4096); - r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT); - cpu->vcpu_dirty = 1; - assert_hvf_ok(r); - if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &hvf_state->hvf_caps->vmx_cap_pinbased)) { abort(); @@ -865,49 +557,3 @@ int hvf_vcpu_exec(CPUState *cpu) return ret; } - -bool hvf_allowed; - -static int hvf_accel_init(MachineState *ms) -{ - int x; - hv_return_t ret; - HVFState *s; - - ret = hv_vm_create(HV_VM_DEFAULT); - assert_hvf_ok(ret); - - s = g_new0(HVFState, 1); - - s->num_slots = 32; - for (x = 0; x < s->num_slots; ++x) { - s->slots[x].size = 0; - s->slots[x].slot_id = x; - } - - hvf_state = s; - memory_listener_register(&hvf_memory_listener, &address_space_memory); - cpus_register_accel(&hvf_cpus); - return 0; -} - -static void hvf_accel_class_init(ObjectClass *oc, void *data) -{ - AccelClass *ac = ACCEL_CLASS(oc); - ac->name = "HVF"; - ac->init_machine = hvf_accel_init; - ac->allowed = &hvf_allowed; -} - -static const TypeInfo hvf_accel_type = { - .name = TYPE_HVF_ACCEL, - .parent = TYPE_ACCEL, - .class_init = hvf_accel_class_init, -}; - -static void hvf_type_init(void) -{ - type_register_static(&hvf_accel_type); -} - -type_init(hvf_type_init); diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index 409c9a3f14..c8a43717ee 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -1,6 +1,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( 'hvf.c', - 'hvf-cpus.c', 'x86.c', 'x86_cpuid.c', 'x86_decode.c', diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index bbec412b6c..89b8e9d87a 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -20,6 +20,9 @@ #include "qemu/osdep.h" #include "qemu-common.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" +#include "sysemu/hw_accel.h" #include "x86hvf.h" #include "vmx.h" #include "vmcs.h" @@ -32,8 +35,6 @@ #include #include -#include "hvf-cpus.h" - void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) { @@ -437,7 +438,7 @@ int hvf_process_events(CPUState *cpu_state) env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); do_cpu_init(cpu); } @@ -451,12 +452,12 @@ int hvf_process_events(CPUState *cpu_state) cpu_state->halted = 0; } if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); do_cpu_sipi(cpu); } if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR; - hvf_cpu_synchronize_state(cpu_state); + cpu_synchronize_state(cpu_state); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); } diff --git a/target/i386/hvf/x86hvf.h b/target/i386/hvf/x86hvf.h index 635ab0f34e..99ed8d608d 100644 --- a/target/i386/hvf/x86hvf.h +++ b/target/i386/hvf/x86hvf.h @@ -21,8 +21,6 @@ #include "x86_descr.h" int hvf_process_events(CPUState *); -int hvf_put_registers(CPUState *); -int hvf_get_registers(CPUState *); bool hvf_inject_interrupts(CPUState *); void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr); -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDt-00040N-Am for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDj-0003vW-LE; Wed, 20 Jan 2021 17:45:00 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45214 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDe-0001VM-FG; Wed, 20 Jan 2021 17:44:59 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id E9105390057B; Wed, 20 Jan 2021 23:44:50 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 08/11] arm: Add Hypervisor.framework build target Date: Wed, 20 Jan 2021 23:44:41 +0100 Message-Id: <20210120224444.71840-9-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:45:00 -0000 Now that we have all logic in place that we need to handle Hypervisor.framework on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we can build it. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov (x86 only) --- v1 -> v2: - Fix build on 32bit arm v3 -> v4: - Remove i386-softmmu target --- meson.build | 11 ++++++++++- target/arm/hvf/meson.build | 3 +++ target/arm/meson.build | 2 ++ 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 target/arm/hvf/meson.build diff --git a/meson.build b/meson.build index c667d64498..8302fcbd90 100644 --- a/meson.build +++ b/meson.build @@ -74,16 +74,25 @@ else endif accelerator_targets = { 'CONFIG_KVM': kvm_targets } + +if cpu in ['x86', 'x86_64'] + hvf_targets = ['x86_64-softmmu'] +elif cpu in ['aarch64'] + hvf_targets = ['aarch64-softmmu'] +else + hvf_targets = [] +endif + if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] # i368 emulator provides xenpv machine type for multiple architectures accelerator_targets += { 'CONFIG_XEN': ['i386-softmmu', 'x86_64-softmmu'], + 'CONFIG_HVF': hvf_targets, } endif if cpu in ['x86', 'x86_64'] accelerator_targets += { 'CONFIG_HAX': ['i386-softmmu', 'x86_64-softmmu'], - 'CONFIG_HVF': ['x86_64-softmmu'], 'CONFIG_WHPX': ['i386-softmmu', 'x86_64-softmmu'], } endif diff --git a/target/arm/hvf/meson.build b/target/arm/hvf/meson.build new file mode 100644 index 0000000000..855e6cce5a --- /dev/null +++ b/target/arm/hvf/meson.build @@ -0,0 +1,3 @@ +arm_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( + 'hvf.c', +)) diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c101..2efd6e672a 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -54,5 +54,7 @@ arm_softmmu_ss.add(files( 'psci.c', )) +subdir('hvf') + target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDu-000419-73 for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDk-0003vn-4z; Wed, 20 Jan 2021 17:45:00 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45230 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDg-0001WS-Ux; Wed, 20 Jan 2021 17:44:59 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 81B0B390057D; Wed, 20 Jan 2021 23:44:51 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 09/11] arm/hvf: Add a WFI handler Date: Wed, 20 Jan 2021 23:44:42 +0100 Message-Id: <20210120224444.71840-10-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:45:01 -0000 From: Peter Collingbourne Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. In this implementation IPI is blocked on the CPU thread at startup and pselect() is used to atomically unblock the signal and begin sleeping. The signal is sent unconditionally so there's no need to worry about races between actually sleeping and the "we think we're sleeping" state. It may lead to an extra wakeup but that's better than missing it entirely. Signed-off-by: Peter Collingbourne [agraf: Remove unused 'set' variable, always advance PC on WFX trap] Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov --- accel/hvf/hvf-cpus.c | 5 ++-- include/sysemu/hvf_int.h | 1 + target/arm/hvf/hvf.c | 56 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 3 deletions(-) diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c index 6d70ee742e..abef6a58f7 100644 --- a/accel/hvf/hvf-cpus.c +++ b/accel/hvf/hvf-cpus.c @@ -322,15 +322,14 @@ static int hvf_init_vcpu(CPUState *cpu) cpu->hvf = g_malloc0(sizeof(*cpu->hvf)); /* init cpu signals */ - sigset_t set; struct sigaction sigact; memset(&sigact, 0, sizeof(sigact)); sigact.sa_handler = dummy_signal; sigaction(SIG_IPI, &sigact, NULL); - pthread_sigmask(SIG_BLOCK, NULL, &set); - sigdelset(&set, SIG_IPI); + pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); + sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); #ifdef __aarch64__ r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index c2ac6c8f97..7a397fe85a 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -51,6 +51,7 @@ extern HVFState *hvf_state; struct hvf_vcpu_state { uint64_t fd; void *exit; + sigset_t unblock_ipi_mask; }; void assert_hvf_ok(hv_return_t ret); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8f18efe856..f0850ab14a 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2,6 +2,7 @@ * QEMU Hypervisor.framework support for Apple Silicon * Copyright 2020 Alexander Graf + * Copyright 2020 Google LLC * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -17,6 +18,8 @@ #include "sysemu/hvf_int.h" #include "sysemu/hw_accel.h" +#include + #include "exec/address-spaces.h" #include "hw/irq.h" #include "qemu/main-loop.h" @@ -411,6 +414,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_kick_vcpu_thread(CPUState *cpu) { + cpus_kick_thread(cpu); hv_vcpus_exit(&cpu->hvf->fd, 1); } @@ -466,6 +470,18 @@ static int hvf_inject_interrupts(CPUState *cpu) return 0; } +static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) +{ + /* + * Use pselect to sleep so that other threads can IPI us while we're + * sleeping. + */ + qatomic_mb_set(&cpu->thread_kicked, false); + qemu_mutex_unlock_iothread(); + pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); + qemu_mutex_lock_iothread(); +} + int hvf_vcpu_exec(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -577,6 +593,46 @@ int hvf_vcpu_exec(CPUState *cpu) } case EC_WFX_TRAP: advance_pc = true; + if (!(syndrome & WFX_IS_WFE) && !(cpu->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ))) { + + uint64_t ctl; + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, + &ctl); + assert_hvf_ok(r); + + if (!(ctl & 1) || (ctl & 2)) { + /* Timer disabled or masked, just wait for an IPI. */ + hvf_wait_for_ipi(cpu, NULL); + break; + } + + uint64_t cval; + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, + &cval); + assert_hvf_ok(r); + + int64_t ticks_to_sleep = cval - mach_absolute_time(); + if (ticks_to_sleep < 0) { + break; + } + + uint64_t seconds = ticks_to_sleep / arm_cpu->gt_cntfrq_hz; + uint64_t nanos = + (ticks_to_sleep - arm_cpu->gt_cntfrq_hz * seconds) * + 1000000000 / arm_cpu->gt_cntfrq_hz; + + /* + * Don't sleep for less than 2ms. This is believed to improve + * latency of message passing workloads. + */ + if (!seconds && nanos < 2000000) { + break; + } + + struct timespec ts = { seconds, nanos }; + hvf_wait_for_ipi(cpu, &ts); + } break; case EC_AA64_HVC: cpu_synchronize_state(cpu); -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDw-00042L-FP for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDh-0003tE-EI; Wed, 20 Jan 2021 17:44:57 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45198 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDd-0001V4-MZ; Wed, 20 Jan 2021 17:44:57 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 2F5863900559; Wed, 20 Jan 2021 23:44:49 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 05/11] arm: Set PSCI to 0.2 for HVF Date: Wed, 20 Jan 2021 23:44:38 +0100 Message-Id: <20210120224444.71840-6-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:44:57 -0000 In Hypervisor.framework, we just pass PSCI calls straight on to the QEMU emulation of it. That means, if TCG is compatible with PSCI 0.2, so are we. Let's transpose that fact in code too. Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov --- v3 -> v4: - Combine both if statements --- target/arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141..f1929b5eba 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1063,8 +1063,8 @@ static void arm_cpu_initfn(Object *obj) cpu->psci_version = 1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; - if (tcg_enabled()) { - cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ + if (tcg_enabled() || hvf_enabled()) { + cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ } } -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2MDz-00044l-FT for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2MDk-0003w8-WE; Wed, 20 Jan 2021 17:45:01 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45212 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2MDe-0001VL-Hb; Wed, 20 Jan 2021 17:45:00 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 57B1F390056B; Wed, 20 Jan 2021 23:44:50 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 07/11] hvf: Add Apple Silicon support Date: Wed, 20 Jan 2021 23:44:40 +0100 Message-Id: <20210120224444.71840-8-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:45:02 -0000 With Apple Silicon available to the masses, it's a good time to add support for driving its virtualization extensions from QEMU. This patch adds all necessary architecture specific code to get basic VMs working. It's still pretty raw, but definitely functional. Known limitations: - Vtimer acknowledgement is hacky - Should implement more sysregs and fault on invalid ones then - WFI handling is missing, need to marry it with vtimer Signed-off-by: Alexander Graf Reviewed-by: Roman Bolshakov --- v1 -> v2: - Merge vcpu kick function patch - Implement WFI handling (allows vCPUs to sleep) - Synchronize system registers (fixes OVMF crashes and reboot) - Don't always call cpu_synchronize_state() - Use more fine grained iothread locking - Populate aa64mmfr0 from hardware v2 -> v3: - Advance PC on SMC - Use cp list interface for sysreg syncs - Do not set current_cpu - Fix sysreg isread mask - Move sysreg handling to functions - Remove WFI logic again - Revert to global iothread locking - Use Hypervisor.h on arm, hv.h does not contain aarch64 definitions v3 -> v4: - No longer include Hypervisor.h v5 -> v6: - Swap sysreg definition order. This way we're in line with asm outputs. --- MAINTAINERS | 5 + accel/hvf/hvf-cpus.c | 14 + include/sysemu/hvf_int.h | 9 +- target/arm/hvf/hvf.c | 618 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 645 insertions(+), 1 deletion(-) create mode 100644 target/arm/hvf/hvf.c diff --git a/MAINTAINERS b/MAINTAINERS index e589ec02e0..8cbb3f37b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -442,6 +442,11 @@ F: accel/accel.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs +Apple Silicon HVF CPUs +M: Alexander Graf +S: Maintained +F: target/arm/hvf/ + X86 HVF CPUs M: Cameron Esfahani M: Roman Bolshakov diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c index a324da2757..6d70ee742e 100644 --- a/accel/hvf/hvf-cpus.c +++ b/accel/hvf/hvf-cpus.c @@ -58,6 +58,10 @@ #include "sysemu/runstate.h" #include "qemu/guest-random.h" +#ifdef __aarch64__ +#define HV_VM_DEFAULT NULL +#endif + /* Memory slots */ struct mac_slot { @@ -328,7 +332,11 @@ static int hvf_init_vcpu(CPUState *cpu) pthread_sigmask(SIG_BLOCK, NULL, &set); sigdelset(&set, SIG_IPI); +#ifdef __aarch64__ + r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); +#else r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); +#endif cpu->vcpu_dirty = 1; assert_hvf_ok(r); @@ -399,8 +407,14 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } +__attribute__((weak)) void hvf_kick_vcpu_thread(CPUState *cpu) +{ + cpus_kick_thread(cpu); +} + static const CpusAccel hvf_cpus = { .create_vcpu_thread = hvf_start_vcpu_thread, + .kick_vcpu_thread = hvf_kick_vcpu_thread, .synchronize_post_reset = hvf_cpu_synchronize_post_reset, .synchronize_post_init = hvf_cpu_synchronize_post_init, diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 9d3cb53e47..c2ac6c8f97 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -11,7 +11,12 @@ #ifndef HVF_INT_H #define HVF_INT_H +#include "qemu/osdep.h" +#ifdef __aarch64__ +#include +#else #include +#endif /* hvf_slot flags */ #define HVF_SLOT_LOG (1 << 0) @@ -44,7 +49,8 @@ struct HVFState { extern HVFState *hvf_state; struct hvf_vcpu_state { - int fd; + uint64_t fd; + void *exit; }; void assert_hvf_ok(hv_return_t ret); @@ -54,5 +60,6 @@ int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); int hvf_vcpu_exec(CPUState *cpu); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); +void hvf_kick_vcpu_thread(CPUState *cpu); #endif diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c new file mode 100644 index 0000000000..8f18efe856 --- /dev/null +++ b/target/arm/hvf/hvf.c @@ -0,0 +1,618 @@ +/* + * QEMU Hypervisor.framework support for Apple Silicon + + * Copyright 2020 Alexander Graf + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" + +#include "sysemu/runstate.h" +#include "sysemu/hvf.h" +#include "sysemu/hvf_int.h" +#include "sysemu/hw_accel.h" + +#include "exec/address-spaces.h" +#include "hw/irq.h" +#include "qemu/main-loop.h" +#include "sysemu/accel.h" +#include "sysemu/cpus.h" +#include "target/arm/cpu.h" +#include "target/arm/internals.h" + +#define HVF_DEBUG 0 +#define DPRINTF(...) \ + if (HVF_DEBUG) { \ + fprintf(stderr, "HVF %s:%d ", __func__, __LINE__); \ + fprintf(stderr, __VA_ARGS__); \ + fprintf(stderr, "\n"); \ + } + +#define HVF_SYSREG(crn, crm, op0, op1, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) +#define PL1_WRITE_MASK 0x4 + +#define SYSREG(op0, op1, crn, crm, op2) \ + ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1)) +#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7) +#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) +#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) + +#define WFX_IS_WFE (1 << 0) + +struct hvf_reg_match { + int reg; + uint64_t offset; +}; + +static const struct hvf_reg_match hvf_reg_match[] = { + { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, + { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, + { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, + { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, + { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, + { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, + { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, + { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, + { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, + { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, + { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, + { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, + { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, + { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, + { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, + { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, + { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, + { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, + { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, + { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, + { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, + { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, + { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, + { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, + { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, + { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, + { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, + { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, + { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, + { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, + { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, + { HV_REG_PC, offsetof(CPUARMState, pc) }, +}; + +struct hvf_sreg_match { + int reg; + uint32_t key; +}; + +static const struct hvf_sreg_match hvf_sreg_match[] = { + { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, + + { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, + { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, + { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, + { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, + +#ifdef SYNC_NO_RAW_REGS + /* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easier. + */ + { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, + { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, + { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, + { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, +#endif + { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, + { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, + { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, +#ifdef SYNC_NO_MMFR0 + /* We keep the hardware MMFR0 around. HW limits are there anyway */ + { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, +#endif + { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, + + { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, + { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, + { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, + { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, + { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, + { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, + + { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, + { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, + { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, + { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, + { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, + { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, + { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, + { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, + { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, + { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, + + { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 1, 0) }, + { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, + { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, + { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, + { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, + { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, + { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, + { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, + { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, + { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, + { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, + { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, + { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, + { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, + { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, + { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, + { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, + { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, + { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, + { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, +}; + +int hvf_get_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_return_t ret; + uint64_t val; + int i; + + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { + ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); + *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; + assert_hvf_ok(ret); + } + + val = 0; + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); + assert_hvf_ok(ret); + vfp_set_fpcr(env, val); + + val = 0; + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); + assert_hvf_ok(ret); + vfp_set_fpsr(env, val); + + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); + assert_hvf_ok(ret); + pstate_write(env, val); + + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); + assert_hvf_ok(ret); + + arm_cpu->cpreg_values[i] = val; + } + write_list_to_cpustate(arm_cpu); + + return 0; +} + +int hvf_put_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_return_t ret; + uint64_t val; + int i; + + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { + val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); + ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); + + assert_hvf_ok(ret); + } + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); + assert_hvf_ok(ret); + + write_cpustate_to_list(arm_cpu, false); + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { + val = arm_cpu->cpreg_values[i]; + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val); + assert_hvf_ok(ret); + } + + return 0; +} + +static void flush_cpu_state(CPUState *cpu) +{ + if (cpu->vcpu_dirty) { + hvf_put_registers(cpu); + cpu->vcpu_dirty = false; + } +} + +static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) +{ + hv_return_t r; + + flush_cpu_state(cpu); + + if (rt < 31) { + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); + assert_hvf_ok(r); + } +} + +static uint64_t hvf_get_reg(CPUState *cpu, int rt) +{ + uint64_t val = 0; + hv_return_t r; + + flush_cpu_state(cpu); + + if (rt < 31) { + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); + assert_hvf_ok(r); + } + + return val; +} + +void hvf_arch_vcpu_destroy(CPUState *cpu) +{ +} + +int hvf_arch_init_vcpu(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); + uint64_t pfr; + hv_return_t ret; + int i; + + env->aarch64 = 1; + asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); + + /* Allocate enough space for our sysreg sync */ + arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, + sregs_match_len); + arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, + sregs_match_len); + arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, + arm_cpu->cpreg_vmstate_indexes, + sregs_match_len); + arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, + arm_cpu->cpreg_vmstate_values, + sregs_match_len); + + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); + arm_cpu->cpreg_array_len = sregs_match_len; + arm_cpu->cpreg_vmstate_array_len = sregs_match_len; + + /* Populate cp list for all known sysregs */ + for (i = 0; i < sregs_match_len; i++) { + const ARMCPRegInfo *ri; + + arm_cpu->cpreg_indexes[i] = cpreg_to_kvm_id(hvf_sreg_match[i].key); + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + } + } + write_cpustate_to_list(arm_cpu, false); + + /* Set CP_NO_RAW system registers on init */ + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, + arm_cpu->midr); + assert_hvf_ok(ret); + + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, + arm_cpu->mp_affinity); + assert_hvf_ok(ret); + + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); + assert_hvf_ok(ret); + pfr |= env->gicv3state ? (1 << 24) : 0; + ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); + assert_hvf_ok(ret); + + /* We're limited to underlying hardware caps, override internal versions */ + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, + &arm_cpu->isar.id_aa64mmfr0); + assert_hvf_ok(ret); + + return 0; +} + +void hvf_kick_vcpu_thread(CPUState *cpu) +{ + hv_vcpus_exit(&cpu->hvf->fd, 1); +} + +static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + uint64_t val = 0; + + switch (reg) { + case SYSREG_CNTPCT_EL0: + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + gt_cntfrq_period_ns(arm_cpu); + break; + case SYSREG_PMCCNTR_EL0: + val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + break; + default: + DPRINTF("unhandled sysreg read %08x (op0=%d op1=%d op2=%d " + "crn=%d crm=%d)", reg, (reg >> 20) & 0x3, + (reg >> 14) & 0x7, (reg >> 17) & 0x7, + (reg >> 10) & 0xf, (reg >> 1) & 0xf); + break; + } + + return val; +} + +static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + + switch (reg) { + case SYSREG_CNTPCT_EL0: + break; + default: + DPRINTF("unhandled sysreg write %08x", reg); + break; + } +} + +static int hvf_inject_interrupts(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { + DPRINTF("injecting FIQ"); + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, true); + } + + if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + DPRINTF("injecting IRQ"); + hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, true); + } + + return 0; +} + +int hvf_vcpu_exec(CPUState *cpu) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit; + hv_return_t r; + + while (1) { + bool advance_pc = false; + + qemu_wait_io_event_common(cpu); + flush_cpu_state(cpu); + + if (hvf_inject_interrupts(cpu)) { + return EXCP_INTERRUPT; + } + + if (cpu->halted) { + return EXCP_HLT; + } + + qemu_mutex_unlock_iothread(); + assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); + + /* handle VMEXIT */ + uint64_t exit_reason = hvf_exit->reason; + uint64_t syndrome = hvf_exit->exception.syndrome; + uint32_t ec = syn_get_ec(syndrome); + + qemu_mutex_lock_iothread(); + switch (exit_reason) { + case HV_EXIT_REASON_EXCEPTION: + /* This is the main one, handle below. */ + break; + case HV_EXIT_REASON_VTIMER_ACTIVATED: + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); + continue; + case HV_EXIT_REASON_CANCELED: + /* we got kicked, no exit to process */ + continue; + default: + assert(0); + } + + switch (ec) { + case EC_DATAABORT: { + bool isv = syndrome & ARM_EL_ISV; + bool iswrite = (syndrome >> 6) & 1; + bool s1ptw = (syndrome >> 7) & 1; + uint32_t sas = (syndrome >> 22) & 3; + uint32_t len = 1 << sas; + uint32_t srt = (syndrome >> 16) & 0x1f; + uint64_t val = 0; + + DPRINTF("data abort: [pc=0x%llx va=0x%016llx pa=0x%016llx isv=%x " + "iswrite=%x s1ptw=%x len=%d srt=%d]\n", + env->pc, hvf_exit->exception.virtual_address, + hvf_exit->exception.physical_address, isv, iswrite, + s1ptw, len, srt); + + assert(isv); + + if (iswrite) { + val = hvf_get_reg(cpu, srt); + address_space_write(&address_space_memory, + hvf_exit->exception.physical_address, + MEMTXATTRS_UNSPECIFIED, &val, len); + + /* + * We do not have a callback to see if the timer is out of + * pending state. That means every MMIO write could + * potentially be an EOI ends the vtimer. Until we get an + * actual callback, let's just see if the timer is still + * pending on every possible toggle point. + */ + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0); + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); + } else { + address_space_read(&address_space_memory, + hvf_exit->exception.physical_address, + MEMTXATTRS_UNSPECIFIED, &val, len); + hvf_set_reg(cpu, srt, val); + } + + advance_pc = true; + break; + } + case EC_SYSTEMREGISTERTRAP: { + bool isread = (syndrome >> 0) & 1; + uint32_t rt = (syndrome >> 5) & 0x1f; + uint32_t reg = syndrome & SYSREG_MASK; + uint64_t val = 0; + + DPRINTF("sysreg %s operation reg=%08x (op0=%d op1=%d op2=%d " + "crn=%d crm=%d)", (isread) ? "read" : "write", + reg, (reg >> 20) & 0x3, + (reg >> 14) & 0x7, (reg >> 17) & 0x7, + (reg >> 10) & 0xf, (reg >> 1) & 0xf); + + if (isread) { + hvf_set_reg(cpu, rt, hvf_sysreg_read(cpu, reg)); + } else { + val = hvf_get_reg(cpu, rt); + hvf_sysreg_write(cpu, reg, val); + } + + advance_pc = true; + break; + } + case EC_WFX_TRAP: + advance_pc = true; + break; + case EC_AA64_HVC: + cpu_synchronize_state(cpu); + if (arm_is_psci_call(arm_cpu, EXCP_HVC)) { + arm_handle_psci_call(arm_cpu); + } else { + DPRINTF("unknown HVC! %016llx", env->xregs[0]); + env->xregs[0] = -1; + } + break; + case EC_AA64_SMC: + cpu_synchronize_state(cpu); + if (arm_is_psci_call(arm_cpu, EXCP_SMC)) { + arm_handle_psci_call(arm_cpu); + } else { + DPRINTF("unknown SMC! %016llx", env->xregs[0]); + env->xregs[0] = -1; + } + env->pc += 4; + break; + default: + cpu_synchronize_state(cpu); + DPRINTF("exit: %llx [ec=0x%x pc=0x%llx]", syndrome, ec, env->pc); + error_report("%llx: unhandled exit %llx", env->pc, exit_reason); + } + + if (advance_pc) { + uint64_t pc; + + flush_cpu_state(cpu); + + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); + assert_hvf_ok(r); + pc += 4; + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); + assert_hvf_ok(r); + } + } +} -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2ME5-0004AI-Fd for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2ME4-00048B-GM; Wed, 20 Jan 2021 17:45:20 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45200 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2ME1-0001V5-FC; Wed, 20 Jan 2021 17:45:20 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 3F74639000FA; Wed, 20 Jan 2021 23:44:53 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 11/11] hvf: arm: Implement -cpu host Date: Wed, 20 Jan 2021 23:44:44 +0100 Message-Id: <20210120224444.71840-12-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:45:20 -0000 Now that we have working system register sync, we push more target CPU properties into the virtual machine. That might be useful in some situations, but is not the typical case that users want. So let's add a -cpu host option that allows them to explicitly pass all CPU capabilities of their host CPU into the guest. Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov --- include/sysemu/hvf.h | 2 ++ target/arm/cpu.c | 9 ++++++--- target/arm/cpu.h | 2 ++ target/arm/hvf/hvf.c | 41 +++++++++++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 2 -- 5 files changed, 51 insertions(+), 5 deletions(-) diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index f893768df9..7eb61cf094 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -19,6 +19,8 @@ #ifdef CONFIG_HVF uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, int reg); +struct ARMCPU; +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) #else /* !CONFIG_HVF */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1929b5eba..abd129d23f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2288,12 +2288,16 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif } -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) static void arm_host_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); +#ifdef CONFIG_KVM kvm_arm_set_cpu_features_from_host(cpu); +#else + hvf_arm_set_cpu_features_from_host(cpu); +#endif if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } @@ -2305,7 +2309,6 @@ static const TypeInfo host_arm_cpu_type_info = { .parent = TYPE_AARCH64_CPU, .instance_init = arm_host_initfn, }; - #endif static void arm_cpu_instance_init(Object *obj) @@ -2364,7 +2367,7 @@ static void arm_cpu_register_types(void) type_register_static(&arm_cpu_type_info); -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) type_register_static(&host_arm_cpu_type_info); #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df0d677833..5cc59df451 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2961,6 +2961,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU + #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 98bd6712c0..42dcc23ba0 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -372,6 +372,47 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + ARMISARegisters host_isar; + const struct isar_regs { + int reg; + uint64_t *val; + } regs[] = { + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + }; + hv_vcpu_t fd; + hv_vcpu_exit_t *exit; + int i; + + cpu->dtb_compatible = "arm,arm-v8"; + cpu->env.features = (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + /* We set up a small vcpu to extract host registers */ + + assert_hvf_ok(hv_vcpu_create(&fd, &exit, NULL)); + for (i = 0; i < ARRAY_SIZE(regs); i++) { + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val)); + } + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &cpu->midr)); + assert_hvf_ok(hv_vcpu_destroy(fd)); + + cpu->isar = host_isar; + cpu->reset_sctlr = 0x00c50078; +} + void hvf_arch_vcpu_destroy(CPUState *cpu) { } diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index eb81b7059e..081727a37e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,8 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU - /** * ARMHostCPUFeatures: information about the host CPU (identified * by asking the host kernel) -- 2.24.3 (Apple Git-128) From MAILER-DAEMON Wed Jan 20 17:45:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2ME7-0004DZ-6v for mharc-qemu-arm@gnu.org; Wed, 20 Jan 2021 17:45:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2ME5-00049c-2k; Wed, 20 Jan 2021 17:45:21 -0500 Received: from mail.csgraf.de ([188.138.100.120]:45228 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2ME0-0001WT-0A; Wed, 20 Jan 2021 17:45:20 -0500 Received: from localhost.localdomain (dynamic-077-002-091-253.77.2.pool.telefonica.de [77.2.91.253]) by csgraf.de (Postfix) with ESMTPSA id 73BAD3900586; Wed, 20 Jan 2021 23:44:52 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Cameron Esfahani , Roman Bolshakov , Peter Maydell , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Subject: [PATCH v6 10/11] hvf: arm: Add support for GICv3 Date: Wed, 20 Jan 2021 23:44:43 +0100 Message-Id: <20210120224444.71840-11-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 22:45:21 -0000 We currently only support GICv2 emulation. To also support GICv3, we will need to pass a few system registers into their respective handler functions. This patch adds handling for all of the required system registers, so that we can run with more than 8 vCPUs. Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov --- v5 -> v6: - Adapt to new SYSREG() ordering --- target/arm/hvf/hvf.c | 141 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f0850ab14a..98bd6712c0 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -22,6 +22,7 @@ #include "exec/address-spaces.h" #include "hw/irq.h" +#include "hw/intc/gicv3_internal.h" #include "qemu/main-loop.h" #include "sysemu/accel.h" #include "sysemu/cpus.h" @@ -46,6 +47,33 @@ #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) +#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) +#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) +#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) +#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) +#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) +#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) +#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) +#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) +#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) +#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) +#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) +#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) +#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) +#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) +#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) +#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) +#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) +#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) +#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) +#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) +#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) +#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) +#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) +#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) +#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) +#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) + #define WFX_IS_WFE (1 << 0) struct hvf_reg_match { @@ -418,6 +446,38 @@ void hvf_kick_vcpu_thread(CPUState *cpu) hv_vcpus_exit(&cpu->hvf->fd, 1); } +static uint32_t hvf_reg2cp_reg(uint32_t reg) +{ + return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 17) & 0x7); +} + +static uint64_t hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + const ARMCPRegInfo *ri; + uint64_t val = 0; + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + if (ri) { + if (ri->type & ARM_CP_CONST) { + val = ri->resetvalue; + } else if (ri->readfn) { + val = ri->readfn(env, ri); + } else { + val = CPREG_FIELD64(env, ri); + } + DPRINTF("vgic read from %s [val=%016llx]", ri->name, val); + } + + return val; +} + static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -431,6 +491,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) case SYSREG_PMCCNTR_EL0: val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + val = hvf_sysreg_read_cp(cpu, reg); + break; + case SYSREG_ICC_CTLR_EL1: + val = hvf_sysreg_read_cp(cpu, reg); + + /* AP0R registers above 0 don't trap, expose less PRIs to fit */ + val &= ~ICC_CTLR_EL1_PRIBITS_MASK; + val |= 4 << ICC_CTLR_EL1_PRIBITS_SHIFT; + break; default: DPRINTF("unhandled sysreg read %08x (op0=%d op1=%d op2=%d " "crn=%d crm=%d)", reg, (reg >> 20) & 0x3, @@ -442,6 +535,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) return val; } +static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + + if (ri) { + if (ri->writefn) { + ri->writefn(env, ri, val); + } else { + CPREG_FIELD64(env, ri) = val; + } + DPRINTF("vgic write to %s [val=%016llx]", ri->name, val); + } +} + static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -449,6 +560,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) switch (reg) { case SYSREG_CNTPCT_EL0: break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_CTLR_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + break; + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0); + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); default: DPRINTF("unhandled sysreg write %08x", reg); break; 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Resent-From: From: no-reply@patchew.org To: agraf@csgraf.de Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, ehabkost@redhat.com, richard.henderson@linaro.org, dirty@apple.com, r.bolshakov@yadro.com, qemu-arm@nongnu.org, lfy@google.com, pbonzini@redhat.com, pcc@google.com Date: Wed, 20 Jan 2021 15:03:50 -0800 (PST) X-ZohoMailClient: External Received-SPF: pass client-ip=136.143.188.53; envelope-from=no-reply@patchew.org; helo=sender4-of-o53.zoho.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2021 23:04:26 -0000 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id m26sm1840826ejr.54.2021.01.20.23.26.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Jan 2021 23:26:37 -0800 (PST) Subject: Re: [PATCH v6 03/11] hvf: Move common code out To: Alexander Graf , qemu-devel@nongnu.org Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm@nongnu.org, Marcel Apfelbaum , Frank Yang , Paolo Bonzini , Peter Collingbourne , Claudio Fontana References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-4-agraf@csgraf.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 08:26:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210120224444.71840-4-agraf@csgraf.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 07:26:49 -0000 Hi Alexander, On 1/20/21 11:44 PM, Alexander Graf wrote: > Until now, Hypervisor.framework has only been available on x86_64 systems. > With Apple Silicon shipping now, it extends its reach to aarch64. To > prepare for support for multiple architectures, let's move common code out > into its own accel directory. > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Tested-by: Roman Bolshakov > > --- > > v3 -> v4: > > - Use hv.h instead of Hypervisor.h for 10.15 compat > - Remove manual inclusion of Hypervisor.h in common .c files > --- > MAINTAINERS | 8 + > accel/hvf/hvf-all.c | 54 +++++ > accel/hvf/hvf-cpus.c | 462 ++++++++++++++++++++++++++++++++++++ > accel/hvf/meson.build | 7 + > accel/meson.build | 1 + > include/sysemu/hvf_int.h | 54 +++++ > target/i386/hvf/hvf-cpus.c | 131 ---------- > target/i386/hvf/hvf-cpus.h | 25 -- > target/i386/hvf/hvf-i386.h | 33 +-- > target/i386/hvf/hvf.c | 360 +--------------------------- > target/i386/hvf/meson.build | 1 - > target/i386/hvf/x86hvf.c | 11 +- > target/i386/hvf/x86hvf.h | 2 - > 13 files changed, 596 insertions(+), 553 deletions(-) > create mode 100644 accel/hvf/hvf-all.c > create mode 100644 accel/hvf/hvf-cpus.c > create mode 100644 accel/hvf/meson.build > create mode 100644 include/sysemu/hvf_int.h > delete mode 100644 target/i386/hvf/hvf-cpus.c > delete mode 100644 target/i386/hvf/hvf-cpus.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 3216387521..e589ec02e0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -448,7 +448,15 @@ M: Roman Bolshakov > W: https://wiki.qemu.org/Features/HVF > S: Maintained > F: target/i386/hvf/ > + > +HVF > +M: Cameron Esfahani > +M: Roman Bolshakov > +W: https://wiki.qemu.org/Features/HVF > +S: Maintained > +F: accel/hvf/ > F: include/sysemu/hvf.h > +F: include/sysemu/hvf_int.h > > WHPX CPUs > M: Sunil Muthuswamy > diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c > new file mode 100644 > index 0000000000..5b415eb0ed > --- /dev/null > +++ b/accel/hvf/hvf-all.c > @@ -0,0 +1,54 @@ > +/* > + * QEMU Hypervisor.framework support > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See > + * the COPYING file in the top-level directory. > + * > + * Contributions after 2012-01-13 are licensed under the terms of the > + * GNU GPL, version 2 or (at your option) any later version. Maybe start with GPLv2+ directly? > diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h > new file mode 100644 > index 0000000000..69de46db7d > --- /dev/null > +++ b/include/sysemu/hvf_int.h > @@ -0,0 +1,54 @@ > +/* > + * QEMU Hypervisor.framework (HVF) support > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + * > + */ > + > +/* header to be included in HVF-specific code */ Can we have this header local to accel/hvf/ ? Otherwise: Reviewed-by: Philippe Mathieu-Daudé > + > +#ifndef HVF_INT_H > +#define HVF_INT_H > + > +#include > + > +/* hvf_slot flags */ > +#define HVF_SLOT_LOG (1 << 0) > + > +typedef struct hvf_slot { > + uint64_t start; > + uint64_t size; > + uint8_t *mem; > + int slot_id; > + uint32_t flags; > + MemoryRegion *region; > +} hvf_slot; > + > +typedef struct hvf_vcpu_caps { > + uint64_t vmx_cap_pinbased; > + uint64_t vmx_cap_procbased; > + uint64_t vmx_cap_procbased2; > + uint64_t vmx_cap_entry; > + uint64_t vmx_cap_exit; > + uint64_t vmx_cap_preemption_timer; > +} hvf_vcpu_caps; > + > +struct HVFState { > + AccelState parent; > + hvf_slot slots[32]; > + int num_slots; > + > + hvf_vcpu_caps *hvf_caps; > +}; > +extern HVFState *hvf_state; > + > +void assert_hvf_ok(hv_return_t ret); > +int hvf_get_registers(CPUState *cpu); > +int hvf_put_registers(CPUState *cpu); > +int hvf_arch_init_vcpu(CPUState *cpu); > +void hvf_arch_vcpu_destroy(CPUState *cpu); > +int hvf_vcpu_exec(CPUState *cpu); > +hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); > + > +#endif From MAILER-DAEMON Thu Jan 21 02:27:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2UNB-0007ya-S4 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 02:27:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2UN6-0007x8-5W for qemu-arm@nongnu.org; Thu, 21 Jan 2021 02:27:13 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:29147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l2UN4-0005yh-Hn for qemu-arm@nongnu.org; Thu, 21 Jan 2021 02:27:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611214029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kuRBfY316bu+rPk/o/xoEShIeY5OdTFwwTSZR0dof64=; b=Gt6T1kStMHSToBI8cBV6hDr2s6FKQE0TqPqeAzXHTF3q5GAvg3yKbs67INvMQrUX852HPd dH1p5KVd2a5YPIj0lDUxWfgNEeIj9VH5cJxt3nbjqcSEfV0fiXY9vJVpe0Nayr2WWpx4QW J+inVCPNXzN/riWZ/8i4ZvSWf2/yeMY= Received: from mail-ej1-f72.google.com (mail-ej1-f72.google.com [209.85.218.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-532-orsvxbYXMPWIloeR-9CFuw-1; Thu, 21 Jan 2021 02:27:08 -0500 X-MC-Unique: orsvxbYXMPWIloeR-9CFuw-1 Received: by mail-ej1-f72.google.com with SMTP id q11so423110ejd.0 for ; Wed, 20 Jan 2021 23:27:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=kuRBfY316bu+rPk/o/xoEShIeY5OdTFwwTSZR0dof64=; b=cecu7ZQf2V/QWpcUBERH62ZLtwB2cm5AFWHU5bKMJTmzoVHe9C8c41cS1+kl1lP318 AbdG1CJeNTQGSSrB+dxrvdOSOBLaYPUgGphmYlRr+D83Sw5paLb6w4DBNuZ0pUxVifQ1 iBI/fWVMglBer1CWGziTWZ66hiImlYsX7N4UET8FnR65QXNgTItE85XfUdA9Pd0bIY1V i89w1UqNTg+pSBFNTsB4OLYBpv/sfkoBZs+RXi5+uhhw/m+3GXBzR75ekqlWSWhPfkEU c0b8jf0+gTjpIcyU94UDQ98dDzDJY9JC/IwDMZLqsb7+mKsqYImil9vrnjvFUMcVzh/I L/Hg== X-Gm-Message-State: AOAM531IthtHFxy0Qs7brPQASaomM2sngT4ugNeUZJuCzPB7fELKQYyI e8LUuZDVipGClojn54X1z1M3pbWGNiYVBhmXpSZuHPFA7HCdnUkYfRKjsbptzEvVFun4e2j1fgn wzgVGe8aeIKcx X-Received: by 2002:a05:6402:1e5:: with SMTP id i5mr10462600edy.86.1611214027015; Wed, 20 Jan 2021 23:27:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJw1EpSA58jtIoinJ6s2wyA3wADQHlgRhtzjub0bHdV1NlzRzZCiMrXyXyIk2Jh1wzEqvI6RLA== X-Received: by 2002:a05:6402:1e5:: with SMTP id i5mr10462586edy.86.1611214026874; Wed, 20 Jan 2021 23:27:06 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u9sm1845230ejc.57.2021.01.20.23.27.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Jan 2021 23:27:06 -0800 (PST) Subject: Re: [PATCH v6 02/11] hvf: x86: Remove unused definitions To: Alexander Graf , qemu-devel@nongnu.org Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm@nongnu.org, Marcel Apfelbaum , Frank Yang , Paolo Bonzini , Peter Collingbourne References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-3-agraf@csgraf.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 08:27:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210120224444.71840-3-agraf@csgraf.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 07:27:14 -0000 On 1/20/21 11:44 PM, Alexander Graf wrote: > The hvf i386 has a few struct and cpp definitions that are never > used. Remove them. > > Suggested-by: Roman Bolshakov > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Tested-by: Roman Bolshakov > --- > target/i386/hvf/hvf-i386.h | 16 ---------------- > 1 file changed, 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 03:50:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2VfV-00082d-UO for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 03:50:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2VfU-00082O-KE; Thu, 21 Jan 2021 03:50:16 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]:38318) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2VfR-0002h8-FL; Thu, 21 Jan 2021 03:50:16 -0500 Received: by mail-lj1-x234.google.com with SMTP id n11so1579702lji.5; Thu, 21 Jan 2021 00:50:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=8ioPpS6eS/iiNq71iDETibfijepHL0ZyEK3TZsTpkBI=; b=CAWPtNfwhez9FaUoRy1RjTTtp8RLR0cmnst6kn4Kbxvd1QYj4f8eMpe4k62pmBhPca +47P2+tjpAvOm90b7ho8iNS5yVkkxn0OJvR+SRBVYKx2Hg8NEo/iMw8HZtfUxhPXghty Osggbz2mVloL7/DuNC16j1xeJHP+mshkimjBXJbrZerjcU0mX/h1WxX8ImdDAnDCjZMU GCpxF7d+zHw+Dpp5SpUxydgR1UzpCMPcnQxec8uc/4MbZ+Ag5wV/0BB+LWicwSusZCJV fRXfpQZykfFfZ2V3nU7XZu5V5sOmtpEs5QrEPODiBtBtAxDBsKmEP7hzwNXdcE6s2irk lmvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=8ioPpS6eS/iiNq71iDETibfijepHL0ZyEK3TZsTpkBI=; b=Ur69dF8rVt4djzpNhOfVdNlB9tBPmMzAcq/o3sJQ0g6jbEt1iUctPePRH8sA0MabnE 8zE/Ow+IEx5MXKPXal/67NdWga62FxLOby0AHHiqqGoZq0r7EO/VaFczVfQqtRsN558N JIuG6lgEpQQBRW9lkj2f4kl8cFOSz21sNGhmjRBFXdFAT1FAHt8vW+wlJQuSprk+IC61 fOcn4wSrkBGON1ljbdS+TxVa27wEUrH/LKAsRBetKY51aELPHaRLRgwjRE/jkUaunU41 cTk6he1FMV9d1zn6reNAyZ1KY1iPNZkyzxyUcduA4akesiySbvY+7HVbNfw1W4RNKvat 0vNw== X-Gm-Message-State: AOAM531ND/iYnqX+DSR7gu6h6xdU1It3t8gWEjpIzDngrg35ZBO4matx OmzshuCa6+s2ss2X+4746+w= X-Google-Smtp-Source: ABdhPJzN90nd0cVcqbPWPjRg2+RcyN4uWrdEPwNtsQv6S1QAyoaDZwRjBZpqBn92G+ihGY/C7OsGyw== X-Received: by 2002:a2e:9310:: with SMTP id e16mr1732248ljh.111.1611219010349; Thu, 21 Jan 2021 00:50:10 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id f9sm460521lft.114.2021.01.21.00.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 00:50:09 -0800 (PST) Date: Thu, 21 Jan 2021 09:50:07 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210121085006.GA10391@fralle-msi> References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> <20210119130113.GA28306@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=frasse.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 08:50:16 -0000 Dear Bin, On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote: > Hi Francisco, > > On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias > wrote: > > > > Hi Bin, > > > > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > > > Hi Francisco, > > > > > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > > > wrote: > > > > > > > > Hi Bin, > > > > > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > > > Hi Francisco, > > > > > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > > > wrote: > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > > > Hi Francisco, > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > > > > > > bytes are expected to be received after it receives a command. For > > > > > > > > > example, depending on the address mode, either 3-byte address or > > > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > > > > > > sending the address bytes, and the dummy cycles need to be counted > > > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > > > > > > It is not in bit, or cycle. However for some reason the model has > > > > > > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > > > > > > approach is to convert the number of dummy cycles to bytes based on > > > > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > > > > > > > > > > > While not being the original implementor I must assume that above solution was > > > > > > > > considered but not chosen by the developers due to it is inaccuracy (it > > > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > > > > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > > > > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > > > > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > > > > > > also because the detail is already in use for catching exactly above error. > > > > > > > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed solution here > > > > > > > was ever considered, otherwise all SPI controller models supporting > > > > > > > software generation should have been found out seriously broken long > > > > > > > time ago! > > > > > > > > > > > > > > > > > > The controllers you are referring to might lack support for commands requiring > > > > > > dummy clock cycles but I really hope they work with the other commands? If so I > > > > > > > > > > I am not sure why you view dummy clock cycles as something special > > > > > that needs some special support from the SPI controller. For the case > > > > > 1 controller, it's nothing special from the controller perspective, > > > > > just like sending out a command, or address bytes, or data. The > > > > > controller just shifts data bit by bit from its tx fifo and that's it. > > > > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > > > > sent via a regular data (the case 1 controller) in the tx fifo, or > > > > > automatically generated (case 2 controller) by the hardware. > > > > > > > > Ok, I'll try to explain my view point a little differently. For that we also > > > > need to keep in mind that QEMU models HW, and any binary that runs on a HW > > > > board supported in QEMU should ideally run on that board inside QEMU aswell > > > > (this can be a bare metal application equaly well as a modified u-boot/Linux > > > > using SPI commands with a non multiple of 8 number of dummy clock cycles). > > > > > > > > Once functionality has been introduced into QEMU it is not easy to know which > > > > intentional or untentional features provided by the functionality are being > > > > used by users. One of the (perhaps not well known) features I'm aware of that > > > > is in use and is provided by the accurate dummy clock cycle modeling inside > > > > m25p80 is the be ability to test drivers accurately regarding the dummy clock > > > > cycles (even when using commands with a non-multiple of 8 number of dummy clock > > > > cycles), but there might be others aswell. So by removing this functionality > > > > above use case will brake, this since those test will not be reliable. > > > > Furthermore, since users tend to be creative it is not possible to know if > > > > there are other use cases that will be affected. This means that in case [1] > > > > needs to be followed the safe path is to add functionality instead of removing. > > > > Luckily it also easier in this case, see below. > > > > > > I understand there might be users other than U-Boot/Linux that use an > > > odd number of dummy bits (not multiple of 8). If your concern was > > > about model behavior changes, sure I can update > > > qemu/docs/system/deprecated.rst to mention that some flashes in the > > > m25p80 model now implement dummy cycles as bytes. > > > > Yes, something like that. My concern is that since this functionality has been > > in tree for while, users have found known or unknown features that got > > introduced by it. By removing the functionality (and the known/uknown features) > > we are riscing to brake our user's use cases (currently I'm aware of one > > feature/use case but it is not unlikely that there are more). [1] states that > > "In general features are intended to be supported indefinitely once introduced > > into QEMU", to me that makes very much sense because the opposite would mean > > that we were not reliable. So in case [1] needs to be honored it looks to be > > safer to add functionality instead of removing (and riscing the removal of use > > cases/features). Luckily I still believe in this case that it will be easier to > > go forward (even if I also agree on what you are saying below about what I > > proposed). > > > > Even if the implementation is buggy and we need to keep the buggy > implementation forever? I think that's why > qemu/docs/system/deprecated.rst was created for deprecating such > feature. With the RFC I posted all commands in m25p80 are working for both the case 1 controller (using a txfifo) and the case 2 controller (no txfifo, as GQSPI). Because of this, I, with all respect, will have to disagree that this is buggy. > > > > > > > > > > > > > > > don't think it is fair to call them 'seriously broken' (and else we should > > > > > > probably let the maintainers know about it). Most likely the lack of support > > > > > > > > > > I called it "seriously broken" because current implementation only > > > > > considered one type of SPI controllers while completely ignoring the > > > > > other type. > > > > > > > > If we change view and see this from the perspective of m25p80, it models the > > > > commands a certain way and provides an API that the SPI controllers need to > > > > implement for interacting with it. It is true that there are SPI controllers > > > > referred to above that do not support the portion of that API that corresponds > > > > to commands with dummy clock cycles, but I don't think it is true that this is > > > > broken since there is also one SPI controller that has a working implementation > > > > of m25p80's full API also when transfering through a tx fifo (use case 1). But > > > > as mentioned above, by doing a minor extension and improvement to m25p80's API > > > > and allow for toggling the accuracy from dummy clock cycles to dummy bytes [1] > > > > will still be honored as in the same time making it possible to have full > > > > support for the API in the SPI controllers that currently do not (please reread > > > > the proposal in my previous reply that attempts to do this). I myself see this > > > > as win/win situation, also because no controller should need modifications. > > > > > > > > > > I am afraid your proposal does not work. Your proposed new device > > > property 'model_dummy_bytes' to select to convert the accurate dummy > > > clock cycle count to dummy bytes inside m25p80, is hard to justify as > > > a property to the flash itself, as the behavior is tightly coupled to > > > how the SPI controller works. > > > > I agree on above. I decided though that instead of posting sample code in here > > I'll post an RFC with hopefully an improved proposal. I'll cc you. About below, > > Xilinx ZynqMP GQSPI should not need any modication in a first step. > > > > Wait, (see below) > > > > > > > Please take a look at the Xilinx GQSPI controller, which supports both > > > use cases, that the dummy cycles can be transferred via tx fifo, or > > > generated by the controller automatically. Please read the example > > > given in: > > > > > > table 24‐22, an example of Generic FIFO Contents for Quad I/O Read > > > Command (EBh) > > > > > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > > > > > If you choose to set the m25p80 device property 'model_dummy_bytes' to > > > true when working with the Xilinx GQSPI controller, you are bound to > > > only allow guest software to use tx fifo to transfer the dummy cycles, > > > and this is wrong. > > > > > You missed this part. I looked at your RFC, and as I mentioned above > your proposal cannot support the complicated controller like Xilinx > GQSPI. Please read the example of table 24-22. With your RFC, you > mandate guest software's GQSPI driver to only use hardware dummy cycle > generation, which is wrong. > First, thank you very much for looking into the RFC series, very much appreciated. Secondly, about above, the GQSPI model in QEMU transfers from 2 locations in the file, in 1 location the transfer referred to above is done, in another location the transfer through the txfifo is done. The location where transfer referred to above is done will not need any modifications (and will thus work equally well as it does currently). Now that above has is cleared out, and since I know you are heavily loaded with other higher prio tasks, lets wait for the maintainers to also have a look into the RFC (understandibly this can take some time due to that they also are heavily loaded). Best regards, Francisco Iglesias > > > > > > > > > > > > > > > for the commands is because no request has been made for them. Also there is > > > > > > one controller that has support. > > > > > > > > > > Definitely it's not "no request". Nearly all SPI flashes support the > > > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > > > > > "seriously broken" for those case 1 type controllers because they > > > > > cannot read anything from the m25p80 model at all. Unless the guest > > > > > software being tested only uses Read (03h) command which is not > > > > > affected. But I can't find a software that uses Read instead of Fast > > > > > Read. > > > > > > > > > > > > The issue you pointed out that we require the total number of dummy > > > > > > > bits should be multiple of 8 is true, that's why I added the > > > > > > > unimplemented log message in this series (patch 2/3/4) to warn users > > > > > > > if this expectation is not met. However this will not cause any issue > > > > > > > when running U-Boot or Linux, because both spi-nor drivers expect the > > > > > > > same assumption as we do here. > > > > > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > > > > > > there is a logic to calculate the dummy bytes needed for fast read > > > > > > > command: > > > > > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > > > > > > > > > Note the default dummy cycles configuration for all flashes I have > > > > > > > looked into as of today, meets the multiple of 8 assumption. On some > > > > > > > flashes the dummy cycle number is configurable, and if it's been > > > > > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > > > > > the first place. > > > > > > > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > > > > > > For such case, driver will calculate the correct number of dummy > > > > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > > > > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > > > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > > > > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > > > > > > > > > > > Please send patches to explain this in detail how this is going to > > > > > > > work. I am open to all possible solutions. > > > > > > > > > > > > In that case I suggest that you instead try with a device property > > > > > > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > > > > > > count to dummy bytes inside m25p80. Below is an example on how to modify the > > > > > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > > > > > > > > > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > > > > > > can follow a similar pattern). This way the fifo mode will be able to work the > > > > > > way you desire while also keeping the current functionality intact. Suddenly > > > > > > removing functionality (features) will take users by surprise. > > > > > > > > > > I don't think we are removing any features. This is a fix to make the > > > > > model to be used by any SPI controllers. > > > > > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > > > assumption for the dummy bit, which is the default configuration for > > > > > all flashes I have looked into so far. Can you please comment what use > > > > > case you want to support? I requested a U-Boot/Linux kernel testing in > > > > > the previous SST thread [1] against Xilinx GQSPI but there was no > > > > > response. > > > > > > > > In [2] instructions on how to boot u-boot/Linux is found. For building the > > > > various software components I followed the official doc in [3]. > > > > > > I see the following QEMU commands are used to test booting U-Boot/Linux: > > > > > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m 4G > > > -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > bl31.elf -device loader,addr=0x40000000,file=Image -device > > > loader,addr=0x2000000,file=system.dtb > > > > > > I am not sure where the system.dtb gets built from? > > > > It is the instructions in [2] to look into. 'system.dtb' is the kernel dtb for > > zcu102 ([2] has been fixed). I created [2] purely for you, so respectfully I > > will ask you to try a little first before asking for further guidance. > > > > I tried, but no success. I removed the "-device loader" part for > loading kernel image and the device tree, and only focused on booting > U-Boot. > > The ATF bl31.elf was built from > https://github.com/ARM-software/arm-trusted-firmware, by following > build instructions at > https://trustedfirmware-a.readthedocs.io/en/latest/plat/xilinx-zynqmp.html. > U-Boot was built from the upstream U-Boot. > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > bl31.elf > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > NOTICE: BL31: v2.4(release):v2.4-228-g337e493 > NOTICE: BL31: Built : 21:18:14, Jan 20 2021 > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > Found: v0.0 > ERROR: Error initializing runtime service sip_svc > > I also tried the Xilinx fork of ATF from > https://github.com/Xilinx/arm-trusted-firmware, by following build > instructions at > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842305/Build+ARM+Trusted+Firmware+ATF > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > bl31.elf > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > NOTICE: BL31: v2.2(release):xilinx-v2020.2 > NOTICE: BL31: Built : 21:52:38, Jan 20 2021 > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > Found: v0.0 > ERROR: Error initializing runtime service sip_svc > > Then I tried to build a U-Boot from the Xilinx fork at > https://github.com/Xilinx/u-boot-xlnx/, still no success. > > > Best regards, > > Francisco Iglesias > > > > [1] qemu/docs/system/deprecated.rst > > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md > > > > > > Regards, > Bin From MAILER-DAEMON Thu Jan 21 04:00:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2VpC-00033A-Dv for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 04:00:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2VpA-00032x-8g; Thu, 21 Jan 2021 04:00:16 -0500 Received: from mail-yb1-xb29.google.com ([2607:f8b0:4864:20::b29]:45398) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2Vp6-0007RC-29; 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Thu, 21 Jan 2021 01:00:09 -0800 (PST) MIME-Version: 1.0 References: <20210114150902.11515-1-bmeng.cn@gmail.com> <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> <20210119130113.GA28306@fralle-msi> <20210121085006.GA10391@fralle-msi> In-Reply-To: <20210121085006.GA10391@fralle-msi> From: Bin Meng Date: Thu, 21 Jan 2021 16:59:51 +0800 Message-ID: Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands To: Francisco Iglesias Cc: Alistair Francis , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b29; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 09:00:16 -0000 Hi Francisco, On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias wrote: > > Dear Bin, > > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote: > > Hi Francisco, > > > > On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias > > wrote: > > > > > > Hi Bin, > > > > > > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > > > > Hi Francisco, > > > > > > > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > > > > wrote: > > > > > > > > > > Hi Bin, > > > > > > > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > > > > Hi Francisco, > > > > > > > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > > > > Hi Francisco, > > > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how m= any follow-up > > > > > > > > > > bytes are expected to be received after it receives a c= ommand. For > > > > > > > > > > example, depending on the address mode, either 3-byte a= ddress or > > > > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are re= quired after > > > > > > > > > > sending the address bytes, and the dummy cycles need to= be counted > > > > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit= is in byte. > > > > > > > > > > It is not in bit, or cycle. However for some reason the= model has > > > > > > > > > > been using the number of dummy cycles for s->needed_byt= es. The right > > > > > > > > > > approach is to convert the number of dummy cycles to by= tes based on > > > > > > > > > > the SPI protocol, for example, 6 dummy cycles for the F= ast Read Quad > > > > > > > > > > I/O (EBh) should be converted to 3 bytes per the formul= a (6 * 4 / 8). > > > > > > > > > > > > > > > > > > While not being the original implementor I must assume th= at above solution was > > > > > > > > > considered but not chosen by the developers due to it is = inaccuracy (it > > > > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only= a multiple of 8, > > > > > > > > > meaning that if the controller is wrongly programmed to g= enerate 7 the error > > > > > > > > > wouldn't be caught and the controller will still be consi= dered "correct"). Now > > > > > > > > > that we have this detail in the implementation I'm in fav= or of keeping it, this > > > > > > > > > also because the detail is already in use for catching ex= actly above error. > > > > > > > > > > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed so= lution here > > > > > > > > was ever considered, otherwise all SPI controller models su= pporting > > > > > > > > software generation should have been found out seriously br= oken long > > > > > > > > time ago! > > > > > > > > > > > > > > > > > > > > > The controllers you are referring to might lack support for c= ommands requiring > > > > > > > dummy clock cycles but I really hope they work with the other= commands? If so I > > > > > > > > > > > > I am not sure why you view dummy clock cycles as something spec= ial > > > > > > that needs some special support from the SPI controller. For th= e case > > > > > > 1 controller, it's nothing special from the controller perspect= ive, > > > > > > just like sending out a command, or address bytes, or data. The > > > > > > controller just shifts data bit by bit from its tx fifo and tha= t's it. > > > > > > In the Xilinx GQSPI controller case, the dummy cycles can eithe= r be > > > > > > sent via a regular data (the case 1 controller) in the tx fifo,= or > > > > > > automatically generated (case 2 controller) by the hardware. > > > > > > > > > > Ok, I'll try to explain my view point a little differently. For t= hat we also > > > > > need to keep in mind that QEMU models HW, and any binary that run= s on a HW > > > > > board supported in QEMU should ideally run on that board inside Q= EMU aswell > > > > > (this can be a bare metal application equaly well as a modified u= -boot/Linux > > > > > using SPI commands with a non multiple of 8 number of dummy clock= cycles). > > > > > > > > > > Once functionality has been introduced into QEMU it is not easy t= o know which > > > > > intentional or untentional features provided by the functionality= are being > > > > > used by users. One of the (perhaps not well known) features I'm a= ware of that > > > > > is in use and is provided by the accurate dummy clock cycle model= ing inside > > > > > m25p80 is the be ability to test drivers accurately regarding the= dummy clock > > > > > cycles (even when using commands with a non-multiple of 8 number = of dummy clock > > > > > cycles), but there might be others aswell. So by removing this fu= nctionality > > > > > above use case will brake, this since those test will not be reli= able. > > > > > Furthermore, since users tend to be creative it is not possible t= o know if > > > > > there are other use cases that will be affected. This means that = in case [1] > > > > > needs to be followed the safe path is to add functionality instea= d of removing. > > > > > Luckily it also easier in this case, see below. > > > > > > > > I understand there might be users other than U-Boot/Linux that use = an > > > > odd number of dummy bits (not multiple of 8). If your concern was > > > > about model behavior changes, sure I can update > > > > qemu/docs/system/deprecated.rst to mention that some flashes in the > > > > m25p80 model now implement dummy cycles as bytes. > > > > > > Yes, something like that. My concern is that since this functionality= has been > > > in tree for while, users have found known or unknown features that go= t > > > introduced by it. By removing the functionality (and the known/uknown= features) > > > we are riscing to brake our user's use cases (currently I'm aware of = one > > > feature/use case but it is not unlikely that there are more). [1] sta= tes that > > > "In general features are intended to be supported indefinitely once i= ntroduced > > > into QEMU", to me that makes very much sense because the opposite wou= ld mean > > > that we were not reliable. So in case [1] needs to be honored it look= s to be > > > safer to add functionality instead of removing (and riscing the remov= al of use > > > cases/features). Luckily I still believe in this case that it will be= easier to > > > go forward (even if I also agree on what you are saying below about w= hat I > > > proposed). > > > > > > > Even if the implementation is buggy and we need to keep the buggy > > implementation forever? I think that's why > > qemu/docs/system/deprecated.rst was created for deprecating such > > feature. > > With the RFC I posted all commands in m25p80 are working for both the cas= e 1 > controller (using a txfifo) and the case 2 controller (no txfifo, as GQSP= I). > Because of this, I, with all respect, will have to disagree that this is = buggy. Well, the existing m25p80 implementation that uses dummy cycle accuracy for those flashes prevents all SPI controllers that use tx fifo to work with those flashes. Hence it is buggy. > > > > > > > > > > > > > > > > > > > > don't think it is fair to call them 'seriously broken' (and e= lse we should > > > > > > > probably let the maintainers know about it). Most likely the = lack of support > > > > > > > > > > > > I called it "seriously broken" because current implementation o= nly > > > > > > considered one type of SPI controllers while completely ignorin= g the > > > > > > other type. > > > > > > > > > > If we change view and see this from the perspective of m25p80, it= models the > > > > > commands a certain way and provides an API that the SPI controlle= rs need to > > > > > implement for interacting with it. It is true that there are SPI = controllers > > > > > referred to above that do not support the portion of that API tha= t corresponds > > > > > to commands with dummy clock cycles, but I don't think it is true= that this is > > > > > broken since there is also one SPI controller that has a working = implementation > > > > > of m25p80's full API also when transfering through a tx fifo (use= case 1). But > > > > > as mentioned above, by doing a minor extension and improvement to= m25p80's API > > > > > and allow for toggling the accuracy from dummy clock cycles to du= mmy bytes [1] > > > > > will still be honored as in the same time making it possible to h= ave full > > > > > support for the API in the SPI controllers that currently do not = (please reread > > > > > the proposal in my previous reply that attempts to do this). I my= self see this > > > > > as win/win situation, also because no controller should need modi= fications. > > > > > > > > > > > > > I am afraid your proposal does not work. Your proposed new device > > > > property 'model_dummy_bytes' to select to convert the accurate dumm= y > > > > clock cycle count to dummy bytes inside m25p80, is hard to justify = as > > > > a property to the flash itself, as the behavior is tightly coupled = to > > > > how the SPI controller works. > > > > > > I agree on above. I decided though that instead of posting sample cod= e in here > > > I'll post an RFC with hopefully an improved proposal. I'll cc you. Ab= out below, > > > Xilinx ZynqMP GQSPI should not need any modication in a first step. > > > > > > > Wait, (see below) > > > > > > > > > > Please take a look at the Xilinx GQSPI controller, which supports b= oth > > > > use cases, that the dummy cycles can be transferred via tx fifo, or > > > > generated by the controller automatically. Please read the example > > > > given in: > > > > > > > > table 24=E2=80=9022, an example of Generic FIFO Contents for Qu= ad I/O Read > > > > Command (EBh) > > > > > > > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-= zynq-ultrascale-trm.pdf > > > > > > > > If you choose to set the m25p80 device property 'model_dummy_bytes'= to > > > > true when working with the Xilinx GQSPI controller, you are bound t= o > > > > only allow guest software to use tx fifo to transfer the dummy cycl= es, > > > > and this is wrong. > > > > > > > > You missed this part. I looked at your RFC, and as I mentioned above > > your proposal cannot support the complicated controller like Xilinx > > GQSPI. Please read the example of table 24-22. With your RFC, you > > mandate guest software's GQSPI driver to only use hardware dummy cycle > > generation, which is wrong. > > > > First, thank you very much for looking into the RFC series, very much > appreciated. Secondly, about above, the GQSPI model in QEMU transfers fro= m 2 > locations in the file, in 1 location the transfer referred to above is do= ne, in > another location the transfer through the txfifo is done. The location wh= ere > transfer referred to above is done will not need any modifications (and w= ill > thus work equally well as it does currently). Please explain this a little bit. How does your RFC series handle cases as described in table 24-22, where the 6 dummy cycles are split into 2 transfers, with one transfer using tx fifo, and the other one using hardware dummy cycle generation? > > Now that above has is cleared out, and since I know you are heavily loade= d with > other higher prio tasks, lets wait for the maintainers to also have a loo= k into > the RFC (understandibly this can take some time due to that they also are > heavily loaded). Yes, maintainers are pretty much silent on this topic. However may I ask you to provide more details on my questions below on booting U-Boot/Linux with the QEMU? You can post patches to add documentation for zynqmp in docs/system/arm, or once I get a working instructions, I could do that too. Much appreciated. > > Best regards, > Francisco Iglesias > > > > > > > > > > > > > > > > > > > > for the commands is because no request has been made for them= . Also there is > > > > > > > one controller that has support. > > > > > > > > > > > > Definitely it's not "no request". Nearly all SPI flashes suppor= t the > > > > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. = This is > > > > > > "seriously broken" for those case 1 type controllers because th= ey > > > > > > cannot read anything from the m25p80 model at all. Unless the g= uest > > > > > > software being tested only uses Read (03h) command which is not > > > > > > affected. But I can't find a software that uses Read instead of= Fast > > > > > > Read. > > > > > > > > > > > > > > The issue you pointed out that we require the total number = of dummy > > > > > > > > bits should be multiple of 8 is true, that's why I added th= e > > > > > > > > unimplemented log message in this series (patch 2/3/4) to w= arn users > > > > > > > > if this expectation is not met. However this will not cause= any issue > > > > > > > > when running U-Boot or Linux, because both spi-nor drivers = expect the > > > > > > > > same assumption as we do here. > > > > > > > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_rea= d_data(), > > > > > > > > there is a logic to calculate the dummy bytes needed for fa= st read > > > > > > > > command: > > > > > > > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > > > > op.dummy.nbytes =3D (nor->read_dummy * op.dummy.buswidt= h) / 8; > > > > > > > > > > > > > > > > Note the default dummy cycles configuration for all flashes= I have > > > > > > > > looked into as of today, meets the multiple of 8 assumption= . On some > > > > > > > > flashes the dummy cycle number is configurable, and if it's= been > > > > > > > > configured to be an odd value, it would not work on U-Boot/= Linux in > > > > > > > > the first place. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different = SPI or QSPI > > > > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the con= troller fifo. > > > > > > > > > > For such case, driver will calculate the correct numb= er of dummy > > > > > > > > > > bytes and write them into the tx fifo. Fixing the m25= p80 model will > > > > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy= cycle implementation > > > > > > > > > inside m25p80. Perhaps one of the following could be look= ed into: configurating > > > > > > > > > the amount, letting the spi ctrl fetch the amount from m2= 5p80 or by inheriting > > > > > > > > > some functionality handling this in the SPI controller. O= r a mixture of above. > > > > > > > > > > > > > > > > Please send patches to explain this in detail how this is g= oing to > > > > > > > > work. I am open to all possible solutions. > > > > > > > > > > > > > > In that case I suggest that you instead try with a device pro= perty > > > > > > > 'model_dummy_bytes' used to select to convert the accurate du= mmy clock cycle > > > > > > > count to dummy bytes inside m25p80. Below is an example on ho= w to modify the > > > > > > > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO han= dling. > > > > > > > > > > > > > decode_fast_read_cmd function (the other commands requiring d= ummy clock cycles > > > > > > > can follow a similar pattern). This way the fifo mode will be= able to work the > > > > > > > way you desire while also keeping the current functionality i= ntact. Suddenly > > > > > > > removing functionality (features) will take users by surprise= . > > > > > > > > > > > > I don't think we are removing any features. This is a fix to ma= ke the > > > > > > model to be used by any SPI controllers. > > > > > > > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > > > > assumption for the dummy bit, which is the default configuratio= n for > > > > > > all flashes I have looked into so far. Can you please comment w= hat use > > > > > > case you want to support? I requested a U-Boot/Linux kernel tes= ting in > > > > > > the previous SST thread [1] against Xilinx GQSPI but there was = no > > > > > > response. > > > > > > > > > > In [2] instructions on how to boot u-boot/Linux is found. For bui= lding the > > > > > various software components I followed the official doc in [3]. > > > > > > > > I see the following QEMU commands are used to test booting U-Boot/L= inux: > > > > > > > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Do= n -m 4G > > > > -serial stdio -display none -device loader,file=3Du-boot.elf -kerne= l > > > > bl31.elf -device loader,addr=3D0x40000000,file=3DImage -device > > > > loader,addr=3D0x2000000,file=3Dsystem.dtb > > > > > > > > I am not sure where the system.dtb gets built from? > > > > > > It is the instructions in [2] to look into. 'system.dtb' is the kerne= l dtb for > > > zcu102 ([2] has been fixed). I created [2] purely for you, so respect= fully I > > > will ask you to try a little first before asking for further guidance= . > > > > > > > I tried, but no success. I removed the "-device loader" part for > > loading kernel image and the device tree, and only focused on booting > > U-Boot. > > > > The ATF bl31.elf was built from > > https://github.com/ARM-software/arm-trusted-firmware, by following > > build instructions at > > https://trustedfirmware-a.readthedocs.io/en/latest/plat/xilinx-zynqmp.h= tml. > > U-Boot was built from the upstream U-Boot. > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don = -m > > 4G -serial stdio -display none -device loader,file=3Du-boot.elf -kernel > > bl31.elf > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > NOTICE: BL31: v2.4(release):v2.4-228-g337e493 > > NOTICE: BL31: Built : 21:18:14, Jan 20 2021 > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > Found: v0.0 > > ERROR: Error initializing runtime service sip_svc > > > > I also tried the Xilinx fork of ATF from > > https://github.com/Xilinx/arm-trusted-firmware, by following build > > instructions at > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842305/Build+AR= M+Trusted+Firmware+ATF > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=3Don,virtualization=3Don = -m > > 4G -serial stdio -display none -device loader,file=3Du-boot.elf -kernel > > bl31.elf > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > NOTICE: BL31: v2.2(release):xilinx-v2020.2 > > NOTICE: BL31: Built : 21:52:38, Jan 20 2021 > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > Found: v0.0 > > ERROR: Error initializing runtime service sip_svc > > > > Then I tried to build a U-Boot from the Xilinx fork at > > https://github.com/Xilinx/u-boot-xlnx/, still no success. > > > > > Best regards, > > > Francisco Iglesias > > > > > > [1] qemu/docs/system/deprecated.rst > > > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xln= x-zcu102-atf-u-boot-linux.md > > > Regards, Bin From MAILER-DAEMON Thu Jan 21 05:01:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2Wmd-0000ab-2K for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 05:01:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2WmX-0000Ye-2y; Thu, 21 Jan 2021 05:01:38 -0500 Received: from mail-lj1-x236.google.com ([2a00:1450:4864:20::236]:34352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2WmQ-0001I2-Nl; Thu, 21 Jan 2021 05:01:36 -0500 Received: by mail-lj1-x236.google.com with SMTP id i17so1821585ljn.1; Thu, 21 Jan 2021 02:01:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=SXwHnFyIoKrX28rtRsuF9EfUt1H9NkHp6Mh1clKX/5E=; b=oklYX0oKlEvjP6BT/GtTRtZgB1WEDDWSBN5gmP1j51h3q1Hwv3yzzvq4nDWXyv71Ut FWP5o0iBnXcgGxlSQs4WeA63MF/r29/f55K2/z9F8ktm1yzSV35OivZdNf+uKRkBqwry n2mfhgc3YWiJmXFYQsQ+l+ig+N/y7jZ8kpDty14aYiZhRk+oBDsX0XxydOgrrAreoddM dT1caQXB/4cQbujisCIO3tZHEUq1kgGM8c5ELocR7CRNNeNyaH9yQA6KAz1lBLh5aB/o g9fc4aw59EGFt3NJD/UQG7m/W20oodJlQdIVyypcigYVJKhMUHdQ7XHvwaEyCG4Pmvbi BCag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=SXwHnFyIoKrX28rtRsuF9EfUt1H9NkHp6Mh1clKX/5E=; b=ueAfPJDsVWt/aR9wmQbY+HdwObYggPx6YUCyTUu3VEKUALUQ80AKFwYmbOD0dxgdKy YS5/MjyYeQQxS4EQb0fOZFcNYoh/UCJp58IaJgEGX60ZQyfq3Q/ej5Zu+9I2PwtKpF4l fWvhbkKp21VTZz71KsJfyWnTRcaRkqzTa2PdI8/2WWvjEbBr+cZambc9z4T2tYoCH0ya HaZr0B2Us/FGg87MYkf5bjD3KodlQXCvBjo6IGobPoJU4a9M3vlPvcApRi2nzmoo6UDZ C27wcMQrmjoxkOQ+BbnLxPC38nITNI86QDSsqOLdjO4zhh8QVjW2kB4lqzrwzhecPmi9 P68A== X-Gm-Message-State: AOAM531E6/f7BG0c8Ihz2CMgwTIqGuxw/i44/rAw3aVEoBwcoLoWQu6G ynqle/p0gXyf2D4ZVr0kGOs= X-Google-Smtp-Source: ABdhPJyPJnJGn4uAJisfNdmJ4SI+Q4YJsHpihmCwG7nu+f1w0TJbfEwWfc/GiWzyqx6fBHsCcnkUqQ== X-Received: by 2002:a2e:988d:: with SMTP id b13mr4600258ljj.176.1611223288004; Thu, 21 Jan 2021 02:01:28 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id v63sm477552lfa.89.2021.01.21.02.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 02:01:27 -0800 (PST) Date: Thu, 21 Jan 2021 11:01:25 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210121100124.GB10391@fralle-msi> References: <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> <20210119130113.GA28306@fralle-msi> <20210121085006.GA10391@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=frasse.iglesias@gmail.com; helo=mail-lj1-x236.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 10:01:39 -0000 Dear Bin, On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote: > Hi Francisco, > > On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias > wrote: > > > > Dear Bin, > > > > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote: > > > Hi Francisco, > > > > > > On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias > > > wrote: > > > > > > > > Hi Bin, > > > > > > > > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > > > > > Hi Francisco, > > > > > > > > > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > > > > > wrote: > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > > > > > Hi Francisco, > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > > > > > Hi Francisco, > > > > > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > > > > > > > > bytes are expected to be received after it receives a command. For > > > > > > > > > > > example, depending on the address mode, either 3-byte address or > > > > > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > > > > > > > > sending the address bytes, and the dummy cycles need to be counted > > > > > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > > > > > > > > It is not in bit, or cycle. However for some reason the model has > > > > > > > > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > > > > > > > > approach is to convert the number of dummy cycles to bytes based on > > > > > > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > > > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > > > > > > > > > > > > > > > While not being the original implementor I must assume that above solution was > > > > > > > > > > considered but not chosen by the developers due to it is inaccuracy (it > > > > > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > > > > > > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > > > > > > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > > > > > > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > > > > > > > > also because the detail is already in use for catching exactly above error. > > > > > > > > > > > > > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed solution here > > > > > > > > > was ever considered, otherwise all SPI controller models supporting > > > > > > > > > software generation should have been found out seriously broken long > > > > > > > > > time ago! > > > > > > > > > > > > > > > > > > > > > > > > The controllers you are referring to might lack support for commands requiring > > > > > > > > dummy clock cycles but I really hope they work with the other commands? If so I > > > > > > > > > > > > > > I am not sure why you view dummy clock cycles as something special > > > > > > > that needs some special support from the SPI controller. For the case > > > > > > > 1 controller, it's nothing special from the controller perspective, > > > > > > > just like sending out a command, or address bytes, or data. The > > > > > > > controller just shifts data bit by bit from its tx fifo and that's it. > > > > > > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > > > > > > sent via a regular data (the case 1 controller) in the tx fifo, or > > > > > > > automatically generated (case 2 controller) by the hardware. > > > > > > > > > > > > Ok, I'll try to explain my view point a little differently. For that we also > > > > > > need to keep in mind that QEMU models HW, and any binary that runs on a HW > > > > > > board supported in QEMU should ideally run on that board inside QEMU aswell > > > > > > (this can be a bare metal application equaly well as a modified u-boot/Linux > > > > > > using SPI commands with a non multiple of 8 number of dummy clock cycles). > > > > > > > > > > > > Once functionality has been introduced into QEMU it is not easy to know which > > > > > > intentional or untentional features provided by the functionality are being > > > > > > used by users. One of the (perhaps not well known) features I'm aware of that > > > > > > is in use and is provided by the accurate dummy clock cycle modeling inside > > > > > > m25p80 is the be ability to test drivers accurately regarding the dummy clock > > > > > > cycles (even when using commands with a non-multiple of 8 number of dummy clock > > > > > > cycles), but there might be others aswell. So by removing this functionality > > > > > > above use case will brake, this since those test will not be reliable. > > > > > > Furthermore, since users tend to be creative it is not possible to know if > > > > > > there are other use cases that will be affected. This means that in case [1] > > > > > > needs to be followed the safe path is to add functionality instead of removing. > > > > > > Luckily it also easier in this case, see below. > > > > > > > > > > I understand there might be users other than U-Boot/Linux that use an > > > > > odd number of dummy bits (not multiple of 8). If your concern was > > > > > about model behavior changes, sure I can update > > > > > qemu/docs/system/deprecated.rst to mention that some flashes in the > > > > > m25p80 model now implement dummy cycles as bytes. > > > > > > > > Yes, something like that. My concern is that since this functionality has been > > > > in tree for while, users have found known or unknown features that got > > > > introduced by it. By removing the functionality (and the known/uknown features) > > > > we are riscing to brake our user's use cases (currently I'm aware of one > > > > feature/use case but it is not unlikely that there are more). [1] states that > > > > "In general features are intended to be supported indefinitely once introduced > > > > into QEMU", to me that makes very much sense because the opposite would mean > > > > that we were not reliable. So in case [1] needs to be honored it looks to be > > > > safer to add functionality instead of removing (and riscing the removal of use > > > > cases/features). Luckily I still believe in this case that it will be easier to > > > > go forward (even if I also agree on what you are saying below about what I > > > > proposed). > > > > > > > > > > Even if the implementation is buggy and we need to keep the buggy > > > implementation forever? I think that's why > > > qemu/docs/system/deprecated.rst was created for deprecating such > > > feature. > > > > With the RFC I posted all commands in m25p80 are working for both the case 1 > > controller (using a txfifo) and the case 2 controller (no txfifo, as GQSPI). > > Because of this, I, with all respect, will have to disagree that this is buggy. > > Well, the existing m25p80 implementation that uses dummy cycle > accuracy for those flashes prevents all SPI controllers that use tx > fifo to work with those flashes. Hence it is buggy. > > > > > > > > > > > > > > > > > > > > > > > > > > don't think it is fair to call them 'seriously broken' (and else we should > > > > > > > > probably let the maintainers know about it). Most likely the lack of support > > > > > > > > > > > > > > I called it "seriously broken" because current implementation only > > > > > > > considered one type of SPI controllers while completely ignoring the > > > > > > > other type. > > > > > > > > > > > > If we change view and see this from the perspective of m25p80, it models the > > > > > > commands a certain way and provides an API that the SPI controllers need to > > > > > > implement for interacting with it. It is true that there are SPI controllers > > > > > > referred to above that do not support the portion of that API that corresponds > > > > > > to commands with dummy clock cycles, but I don't think it is true that this is > > > > > > broken since there is also one SPI controller that has a working implementation > > > > > > of m25p80's full API also when transfering through a tx fifo (use case 1). But > > > > > > as mentioned above, by doing a minor extension and improvement to m25p80's API > > > > > > and allow for toggling the accuracy from dummy clock cycles to dummy bytes [1] > > > > > > will still be honored as in the same time making it possible to have full > > > > > > support for the API in the SPI controllers that currently do not (please reread > > > > > > the proposal in my previous reply that attempts to do this). I myself see this > > > > > > as win/win situation, also because no controller should need modifications. > > > > > > > > > > > > > > > > I am afraid your proposal does not work. Your proposed new device > > > > > property 'model_dummy_bytes' to select to convert the accurate dummy > > > > > clock cycle count to dummy bytes inside m25p80, is hard to justify as > > > > > a property to the flash itself, as the behavior is tightly coupled to > > > > > how the SPI controller works. > > > > > > > > I agree on above. I decided though that instead of posting sample code in here > > > > I'll post an RFC with hopefully an improved proposal. I'll cc you. About below, > > > > Xilinx ZynqMP GQSPI should not need any modication in a first step. > > > > > > > > > > Wait, (see below) > > > > > > > > > > > > > Please take a look at the Xilinx GQSPI controller, which supports both > > > > > use cases, that the dummy cycles can be transferred via tx fifo, or > > > > > generated by the controller automatically. Please read the example > > > > > given in: > > > > > > > > > > table 24‐22, an example of Generic FIFO Contents for Quad I/O Read > > > > > Command (EBh) > > > > > > > > > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > > > > > > > > > If you choose to set the m25p80 device property 'model_dummy_bytes' to > > > > > true when working with the Xilinx GQSPI controller, you are bound to > > > > > only allow guest software to use tx fifo to transfer the dummy cycles, > > > > > and this is wrong. > > > > > > > > > > > You missed this part. I looked at your RFC, and as I mentioned above > > > your proposal cannot support the complicated controller like Xilinx > > > GQSPI. Please read the example of table 24-22. With your RFC, you > > > mandate guest software's GQSPI driver to only use hardware dummy cycle > > > generation, which is wrong. > > > > > > > First, thank you very much for looking into the RFC series, very much > > appreciated. Secondly, about above, the GQSPI model in QEMU transfers from 2 > > locations in the file, in 1 location the transfer referred to above is done, in > > another location the transfer through the txfifo is done. The location where > > transfer referred to above is done will not need any modifications (and will > > thus work equally well as it does currently). > > Please explain this a little bit. How does your RFC series handle > cases as described in table 24-22, where the 6 dummy cycles are split > into 2 transfers, with one transfer using tx fifo, and the other one > using hardware dummy cycle generation? Above transfer is already handled in the model, and since it will not change it will still work afterwards. About below, sure I'll provide some doc once I get some time over. Best regards, Francisco Iglesias > > > > > Now that above has is cleared out, and since I know you are heavily loaded with > > other higher prio tasks, lets wait for the maintainers to also have a look into > > the RFC (understandibly this can take some time due to that they also are > > heavily loaded). > > Yes, maintainers are pretty much silent on this topic. > > However may I ask you to provide more details on my questions below on > booting U-Boot/Linux with the QEMU? > > You can post patches to add documentation for zynqmp in > docs/system/arm, or once I get a working instructions, I could do that > too. Much appreciated. > > > > > Best regards, > > Francisco Iglesias > > > > > > > > > > > > > > > > > > > > > > > > > for the commands is because no request has been made for them. Also there is > > > > > > > > one controller that has support. > > > > > > > > > > > > > > Definitely it's not "no request". Nearly all SPI flashes support the > > > > > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > > > > > > > "seriously broken" for those case 1 type controllers because they > > > > > > > cannot read anything from the m25p80 model at all. Unless the guest > > > > > > > software being tested only uses Read (03h) command which is not > > > > > > > affected. But I can't find a software that uses Read instead of Fast > > > > > > > Read. > > > > > > > > > > > > > > > > The issue you pointed out that we require the total number of dummy > > > > > > > > > bits should be multiple of 8 is true, that's why I added the > > > > > > > > > unimplemented log message in this series (patch 2/3/4) to warn users > > > > > > > > > if this expectation is not met. However this will not cause any issue > > > > > > > > > when running U-Boot or Linux, because both spi-nor drivers expect the > > > > > > > > > same assumption as we do here. > > > > > > > > > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > > > > > > > > there is a logic to calculate the dummy bytes needed for fast read > > > > > > > > > command: > > > > > > > > > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > > > > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > > > > > > > > > > > > > Note the default dummy cycles configuration for all flashes I have > > > > > > > > > looked into as of today, meets the multiple of 8 assumption. On some > > > > > > > > > flashes the dummy cycle number is configurable, and if it's been > > > > > > > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > > > > > > > the first place. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > > > > > > > > For such case, driver will calculate the correct number of dummy > > > > > > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > > > > > > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > > > > > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > > > > > > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > > > > > > > > > > > > > > > Please send patches to explain this in detail how this is going to > > > > > > > > > work. I am open to all possible solutions. > > > > > > > > > > > > > > > > In that case I suggest that you instead try with a device property > > > > > > > > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > > > > > > > > count to dummy bytes inside m25p80. Below is an example on how to modify the > > > > > > > > > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > > > > > > > > > > > > > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > > > > > > > > can follow a similar pattern). This way the fifo mode will be able to work the > > > > > > > > way you desire while also keeping the current functionality intact. Suddenly > > > > > > > > removing functionality (features) will take users by surprise. > > > > > > > > > > > > > > I don't think we are removing any features. This is a fix to make the > > > > > > > model to be used by any SPI controllers. > > > > > > > > > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > > > > > assumption for the dummy bit, which is the default configuration for > > > > > > > all flashes I have looked into so far. Can you please comment what use > > > > > > > case you want to support? I requested a U-Boot/Linux kernel testing in > > > > > > > the previous SST thread [1] against Xilinx GQSPI but there was no > > > > > > > response. > > > > > > > > > > > > In [2] instructions on how to boot u-boot/Linux is found. For building the > > > > > > various software components I followed the official doc in [3]. > > > > > > > > > > I see the following QEMU commands are used to test booting U-Boot/Linux: > > > > > > > > > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m 4G > > > > > -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > > > bl31.elf -device loader,addr=0x40000000,file=Image -device > > > > > loader,addr=0x2000000,file=system.dtb > > > > > > > > > > I am not sure where the system.dtb gets built from? > > > > > > > > It is the instructions in [2] to look into. 'system.dtb' is the kernel dtb for > > > > zcu102 ([2] has been fixed). I created [2] purely for you, so respectfully I > > > > will ask you to try a little first before asking for further guidance. > > > > > > > > > > I tried, but no success. I removed the "-device loader" part for > > > loading kernel image and the device tree, and only focused on booting > > > U-Boot. > > > > > > The ATF bl31.elf was built from > > > https://github.com/ARM-software/arm-trusted-firmware, by following > > > build instructions at > > > https://trustedfirmware-a.readthedocs.io/en/latest/plat/xilinx-zynqmp.html. > > > U-Boot was built from the upstream U-Boot. > > > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > > > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > bl31.elf > > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > > NOTICE: BL31: v2.4(release):v2.4-228-g337e493 > > > NOTICE: BL31: Built : 21:18:14, Jan 20 2021 > > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > > Found: v0.0 > > > ERROR: Error initializing runtime service sip_svc > > > > > > I also tried the Xilinx fork of ATF from > > > https://github.com/Xilinx/arm-trusted-firmware, by following build > > > instructions at > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842305/Build+ARM+Trusted+Firmware+ATF > > > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > > > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > bl31.elf > > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > > NOTICE: BL31: v2.2(release):xilinx-v2020.2 > > > NOTICE: BL31: Built : 21:52:38, Jan 20 2021 > > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > > Found: v0.0 > > > ERROR: Error initializing runtime service sip_svc > > > > > > Then I tried to build a U-Boot from the Xilinx fork at > > > https://github.com/Xilinx/u-boot-xlnx/, still no success. > > > > > > > Best regards, > > > > Francisco Iglesias > > > > > > > > [1] qemu/docs/system/deprecated.rst > > > > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md > > > > > > Regards, > Bin From MAILER-DAEMON Thu Jan 21 09:18:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2ana-0000dk-ES for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 09:18:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2anY-0000dJ-Kp; Thu, 21 Jan 2021 09:18:56 -0500 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]:43556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2anS-0008Kw-Mw; Thu, 21 Jan 2021 09:18:56 -0500 Received: by mail-lf1-x130.google.com with SMTP id q8so2699696lfm.10; Thu, 21 Jan 2021 06:18:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=9Ba2VZkAK1Ral+x3NWU0sxI9dcGvQgZH744lMcTH4XU=; b=Zew26YpiYl5Gx1Msnb9a0WurNX29rnbZBKghAB9nRSsndAUGWdAwL2DoBMSKM1rI4H WaH9RfQcHjLkTFcU6komvOARYb0eMx/g5IQUwEj46ZUZiHs+LVneB8xeqNqI4oowJKaE yHGmWw/f62cX0sppvkPUFY1tKc1KucqHsMgQaD3l/Ji/0JRPJEjYD6WOdRN53kapFxmT coapsRKAohkK5sL/Y0M6IpiNYAjRitvQiMsfVtMUcQ6KtmDm4T1QX8KY7gVjE7WUwi6J gBBlASOceS3esrYTsEObqQxzned8btRX64clcabVfG+kyghx74L38k+tVLaSkpFm5bgW opjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=9Ba2VZkAK1Ral+x3NWU0sxI9dcGvQgZH744lMcTH4XU=; b=sTqfffWc1UREfVN4EpROcYUE1U1IATKOS4UYRqmimZcO44ZIh63tEqDNySvYP4VK+8 +ao28t93E/tkWB4ZN08ZqJVC7mDMa1GwqJCOyPYvt30+X96/oJ3VLwNOHP+stjgOVcFn 0kW5U/G8hupsM286ANZHH7T/PplEAiMXEHujEWihnsD+m5OMZdqdROtevzlEKhLFVUpA xx/6fUfSDPi07hsruJP3FVeG7o9uOTAHvKagwef/eHYP2CiRQ4q3q2AYb1In/5kAoqly x7oCqxSbKL7WoE4RcaCVo5dSLN4bOrzLtXXE9IlMf/jPkNNyrzK/UfnxjG5CwfHhCxrV l6Xg== X-Gm-Message-State: AOAM5328p+kKjNtg7dMX7mPn27OzsONGHFtNT2FJRjWVLp+EDSDj8TuA 4fNGRU7adcF6KSlsDvOrlws= X-Google-Smtp-Source: ABdhPJzwVh2HT6b3faYAw7Zx4oWWk7DkpGOumN62hRrPtX/tzUrasi1p0U3kZKmRzR/o3TOPxx4yyg== X-Received: by 2002:a19:2c4:: with SMTP id 187mr6796882lfc.391.1611238727875; Thu, 21 Jan 2021 06:18:47 -0800 (PST) Received: from fralle-msi (31-208-27-151.cust.bredband2.com. [31.208.27.151]) by smtp.gmail.com with ESMTPSA id n25sm539900lfh.177.2021.01.21.06.18.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 06:18:47 -0800 (PST) Date: Thu, 21 Jan 2021 15:18:45 +0100 From: Francisco Iglesias To: Bin Meng Cc: Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Bin Meng , Joe Komlodi , Andrew Jeffery , =?iso-8859-1?Q?C=E9dric?= Le Goater , Havard Skinnemoen , Joel Stanley , Kevin Wolf , Max Reitz , Tyrone Ting , qemu-arm , Qemu-block , "qemu-devel@nongnu.org Developers" Subject: Re: [PATCH 0/9] hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands Message-ID: <20210121141844.GC10391@fralle-msi> References: <20210114181300.GA29923@fralle-msi> <20210115122627.GB29923@fralle-msi> <20210118100557.GA11373@fralle-msi> <20210119130113.GA28306@fralle-msi> <20210121085006.GA10391@fralle-msi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x130.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 14:18:56 -0000 Hi Bin, On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote: > Hi Francisco, > > On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias > wrote: > > > > Dear Bin, > > > > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote: > > > Hi Francisco, > > > > > > On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias > > > wrote: > > > > > > > > Hi Bin, > > > > > > > > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote: > > > > > Hi Francisco, > > > > > > > > > > On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias > > > > > wrote: > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote: > > > > > > > Hi Francisco, > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote: > > > > > > > > > Hi Francisco, > > > > > > > > > > > > > > > > > > On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote: > > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > > > The m25p80 model uses s->needed_bytes to indicate how many follow-up > > > > > > > > > > > bytes are expected to be received after it receives a command. For > > > > > > > > > > > example, depending on the address mode, either 3-byte address or > > > > > > > > > > > 4-byte address is needed. > > > > > > > > > > > > > > > > > > > > > > For fast read family commands, some dummy cycles are required after > > > > > > > > > > > sending the address bytes, and the dummy cycles need to be counted > > > > > > > > > > > in s->needed_bytes. This is where the mess began. > > > > > > > > > > > > > > > > > > > > > > As the variable name (needed_bytes) indicates, the unit is in byte. > > > > > > > > > > > It is not in bit, or cycle. However for some reason the model has > > > > > > > > > > > been using the number of dummy cycles for s->needed_bytes. The right > > > > > > > > > > > approach is to convert the number of dummy cycles to bytes based on > > > > > > > > > > > the SPI protocol, for example, 6 dummy cycles for the Fast Read Quad > > > > > > > > > > > I/O (EBh) should be converted to 3 bytes per the formula (6 * 4 / 8). > > > > > > > > > > > > > > > > > > > > While not being the original implementor I must assume that above solution was > > > > > > > > > > considered but not chosen by the developers due to it is inaccuracy (it > > > > > > > > > > wouldn't be possible to model exacly 6 dummy cycles, only a multiple of 8, > > > > > > > > > > meaning that if the controller is wrongly programmed to generate 7 the error > > > > > > > > > > wouldn't be caught and the controller will still be considered "correct"). Now > > > > > > > > > > that we have this detail in the implementation I'm in favor of keeping it, this > > > > > > > > > > also because the detail is already in use for catching exactly above error. > > > > > > > > > > > > > > > > > > > > > > > > > > > > I found no clue from the commit message that my proposed solution here > > > > > > > > > was ever considered, otherwise all SPI controller models supporting > > > > > > > > > software generation should have been found out seriously broken long > > > > > > > > > time ago! > > > > > > > > > > > > > > > > > > > > > > > > The controllers you are referring to might lack support for commands requiring > > > > > > > > dummy clock cycles but I really hope they work with the other commands? If so I > > > > > > > > > > > > > > I am not sure why you view dummy clock cycles as something special > > > > > > > that needs some special support from the SPI controller. For the case > > > > > > > 1 controller, it's nothing special from the controller perspective, > > > > > > > just like sending out a command, or address bytes, or data. The > > > > > > > controller just shifts data bit by bit from its tx fifo and that's it. > > > > > > > In the Xilinx GQSPI controller case, the dummy cycles can either be > > > > > > > sent via a regular data (the case 1 controller) in the tx fifo, or > > > > > > > automatically generated (case 2 controller) by the hardware. > > > > > > > > > > > > Ok, I'll try to explain my view point a little differently. For that we also > > > > > > need to keep in mind that QEMU models HW, and any binary that runs on a HW > > > > > > board supported in QEMU should ideally run on that board inside QEMU aswell > > > > > > (this can be a bare metal application equaly well as a modified u-boot/Linux > > > > > > using SPI commands with a non multiple of 8 number of dummy clock cycles). > > > > > > > > > > > > Once functionality has been introduced into QEMU it is not easy to know which > > > > > > intentional or untentional features provided by the functionality are being > > > > > > used by users. One of the (perhaps not well known) features I'm aware of that > > > > > > is in use and is provided by the accurate dummy clock cycle modeling inside > > > > > > m25p80 is the be ability to test drivers accurately regarding the dummy clock > > > > > > cycles (even when using commands with a non-multiple of 8 number of dummy clock > > > > > > cycles), but there might be others aswell. So by removing this functionality > > > > > > above use case will brake, this since those test will not be reliable. > > > > > > Furthermore, since users tend to be creative it is not possible to know if > > > > > > there are other use cases that will be affected. This means that in case [1] > > > > > > needs to be followed the safe path is to add functionality instead of removing. > > > > > > Luckily it also easier in this case, see below. > > > > > > > > > > I understand there might be users other than U-Boot/Linux that use an > > > > > odd number of dummy bits (not multiple of 8). If your concern was > > > > > about model behavior changes, sure I can update > > > > > qemu/docs/system/deprecated.rst to mention that some flashes in the > > > > > m25p80 model now implement dummy cycles as bytes. > > > > > > > > Yes, something like that. My concern is that since this functionality has been > > > > in tree for while, users have found known or unknown features that got > > > > introduced by it. By removing the functionality (and the known/uknown features) > > > > we are riscing to brake our user's use cases (currently I'm aware of one > > > > feature/use case but it is not unlikely that there are more). [1] states that > > > > "In general features are intended to be supported indefinitely once introduced > > > > into QEMU", to me that makes very much sense because the opposite would mean > > > > that we were not reliable. So in case [1] needs to be honored it looks to be > > > > safer to add functionality instead of removing (and riscing the removal of use > > > > cases/features). Luckily I still believe in this case that it will be easier to > > > > go forward (even if I also agree on what you are saying below about what I > > > > proposed). > > > > > > > > > > Even if the implementation is buggy and we need to keep the buggy > > > implementation forever? I think that's why > > > qemu/docs/system/deprecated.rst was created for deprecating such > > > feature. > > > > With the RFC I posted all commands in m25p80 are working for both the case 1 > > controller (using a txfifo) and the case 2 controller (no txfifo, as GQSPI). > > Because of this, I, with all respect, will have to disagree that this is buggy. > > Well, the existing m25p80 implementation that uses dummy cycle > accuracy for those flashes prevents all SPI controllers that use tx > fifo to work with those flashes. Hence it is buggy. > > > > > > > > > > > > > > > > > > > > > > > > > > don't think it is fair to call them 'seriously broken' (and else we should > > > > > > > > probably let the maintainers know about it). Most likely the lack of support > > > > > > > > > > > > > > I called it "seriously broken" because current implementation only > > > > > > > considered one type of SPI controllers while completely ignoring the > > > > > > > other type. > > > > > > > > > > > > If we change view and see this from the perspective of m25p80, it models the > > > > > > commands a certain way and provides an API that the SPI controllers need to > > > > > > implement for interacting with it. It is true that there are SPI controllers > > > > > > referred to above that do not support the portion of that API that corresponds > > > > > > to commands with dummy clock cycles, but I don't think it is true that this is > > > > > > broken since there is also one SPI controller that has a working implementation > > > > > > of m25p80's full API also when transfering through a tx fifo (use case 1). But > > > > > > as mentioned above, by doing a minor extension and improvement to m25p80's API > > > > > > and allow for toggling the accuracy from dummy clock cycles to dummy bytes [1] > > > > > > will still be honored as in the same time making it possible to have full > > > > > > support for the API in the SPI controllers that currently do not (please reread > > > > > > the proposal in my previous reply that attempts to do this). I myself see this > > > > > > as win/win situation, also because no controller should need modifications. > > > > > > > > > > > > > > > > I am afraid your proposal does not work. Your proposed new device > > > > > property 'model_dummy_bytes' to select to convert the accurate dummy > > > > > clock cycle count to dummy bytes inside m25p80, is hard to justify as > > > > > a property to the flash itself, as the behavior is tightly coupled to > > > > > how the SPI controller works. > > > > > > > > I agree on above. I decided though that instead of posting sample code in here > > > > I'll post an RFC with hopefully an improved proposal. I'll cc you. About below, > > > > Xilinx ZynqMP GQSPI should not need any modication in a first step. > > > > > > > > > > Wait, (see below) > > > > > > > > > > > > > Please take a look at the Xilinx GQSPI controller, which supports both > > > > > use cases, that the dummy cycles can be transferred via tx fifo, or > > > > > generated by the controller automatically. Please read the example > > > > > given in: > > > > > > > > > > table 24‐22, an example of Generic FIFO Contents for Quad I/O Read > > > > > Command (EBh) > > > > > > > > > > in https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > > > > > > > > > If you choose to set the m25p80 device property 'model_dummy_bytes' to > > > > > true when working with the Xilinx GQSPI controller, you are bound to > > > > > only allow guest software to use tx fifo to transfer the dummy cycles, > > > > > and this is wrong. > > > > > > > > > > > You missed this part. I looked at your RFC, and as I mentioned above > > > your proposal cannot support the complicated controller like Xilinx > > > GQSPI. Please read the example of table 24-22. With your RFC, you > > > mandate guest software's GQSPI driver to only use hardware dummy cycle > > > generation, which is wrong. > > > > > > > First, thank you very much for looking into the RFC series, very much > > appreciated. Secondly, about above, the GQSPI model in QEMU transfers from 2 > > locations in the file, in 1 location the transfer referred to above is done, in > > another location the transfer through the txfifo is done. The location where > > transfer referred to above is done will not need any modifications (and will > > thus work equally well as it does currently). > > Please explain this a little bit. How does your RFC series handle > cases as described in table 24-22, where the 6 dummy cycles are split > into 2 transfers, with one transfer using tx fifo, and the other one > using hardware dummy cycle generation? Sorry, I missunderstod. You are right, that won't work. Best regards, Francisco Iglesias > > > > > Now that above has is cleared out, and since I know you are heavily loaded with > > other higher prio tasks, lets wait for the maintainers to also have a look into > > the RFC (understandibly this can take some time due to that they also are > > heavily loaded). > > Yes, maintainers are pretty much silent on this topic. > > However may I ask you to provide more details on my questions below on > booting U-Boot/Linux with the QEMU? > > You can post patches to add documentation for zynqmp in > docs/system/arm, or once I get a working instructions, I could do that > too. Much appreciated. > > > > > Best regards, > > Francisco Iglesias > > > > > > > > > > > > > > > > > > > > > > > > > for the commands is because no request has been made for them. Also there is > > > > > > > > one controller that has support. > > > > > > > > > > > > > > Definitely it's not "no request". Nearly all SPI flashes support the > > > > > > > Fast Read (0Bh) command today, and 0Bh requires a dummy cycle. This is > > > > > > > "seriously broken" for those case 1 type controllers because they > > > > > > > cannot read anything from the m25p80 model at all. Unless the guest > > > > > > > software being tested only uses Read (03h) command which is not > > > > > > > affected. But I can't find a software that uses Read instead of Fast > > > > > > > Read. > > > > > > > > > > > > > > > > The issue you pointed out that we require the total number of dummy > > > > > > > > > bits should be multiple of 8 is true, that's why I added the > > > > > > > > > unimplemented log message in this series (patch 2/3/4) to warn users > > > > > > > > > if this expectation is not met. However this will not cause any issue > > > > > > > > > when running U-Boot or Linux, because both spi-nor drivers expect the > > > > > > > > > same assumption as we do here. > > > > > > > > > > > > > > > > > > See U-Boot spi_nor_read_data() and Linux spi_nor_spimem_read_data(), > > > > > > > > > there is a logic to calculate the dummy bytes needed for fast read > > > > > > > > > command: > > > > > > > > > > > > > > > > > > /* convert the dummy cycles to the number of bytes */ > > > > > > > > > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > > > > > > > > > > > > > > > > > Note the default dummy cycles configuration for all flashes I have > > > > > > > > > looked into as of today, meets the multiple of 8 assumption. On some > > > > > > > > > flashes the dummy cycle number is configurable, and if it's been > > > > > > > > > configured to be an odd value, it would not work on U-Boot/Linux in > > > > > > > > > the first place. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Things get complicated when interacting with different SPI or QSPI > > > > > > > > > > > flash controllers. There are major two cases: > > > > > > > > > > > > > > > > > > > > > > - Dummy bytes prepared by drivers, and wrote to the controller fifo. > > > > > > > > > > > For such case, driver will calculate the correct number of dummy > > > > > > > > > > > bytes and write them into the tx fifo. Fixing the m25p80 model will > > > > > > > > > > > fix flashes working with such controllers. > > > > > > > > > > > > > > > > > > > > Above can be fixed while still keeping the detailed dummy cycle implementation > > > > > > > > > > inside m25p80. Perhaps one of the following could be looked into: configurating > > > > > > > > > > the amount, letting the spi ctrl fetch the amount from m25p80 or by inheriting > > > > > > > > > > some functionality handling this in the SPI controller. Or a mixture of above. > > > > > > > > > > > > > > > > > > Please send patches to explain this in detail how this is going to > > > > > > > > > work. I am open to all possible solutions. > > > > > > > > > > > > > > > > In that case I suggest that you instead try with a device property > > > > > > > > 'model_dummy_bytes' used to select to convert the accurate dummy clock cycle > > > > > > > > count to dummy bytes inside m25p80. Below is an example on how to modify the > > > > > > > > > > > > > > No this is wrong in my view. This is not like a DMA vs. PIO handling. > > > > > > > > > > > > > > > decode_fast_read_cmd function (the other commands requiring dummy clock cycles > > > > > > > > can follow a similar pattern). This way the fifo mode will be able to work the > > > > > > > > way you desire while also keeping the current functionality intact. Suddenly > > > > > > > > removing functionality (features) will take users by surprise. > > > > > > > > > > > > > > I don't think we are removing any features. This is a fix to make the > > > > > > > model to be used by any SPI controllers. > > > > > > > > > > > > > > As I pointed out, both U-Boot and Linux have the multiple of 8 > > > > > > > assumption for the dummy bit, which is the default configuration for > > > > > > > all flashes I have looked into so far. Can you please comment what use > > > > > > > case you want to support? I requested a U-Boot/Linux kernel testing in > > > > > > > the previous SST thread [1] against Xilinx GQSPI but there was no > > > > > > > response. > > > > > > > > > > > > In [2] instructions on how to boot u-boot/Linux is found. For building the > > > > > > various software components I followed the official doc in [3]. > > > > > > > > > > I see the following QEMU commands are used to test booting U-Boot/Linux: > > > > > > > > > > $ qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m 4G > > > > > -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > > > bl31.elf -device loader,addr=0x40000000,file=Image -device > > > > > loader,addr=0x2000000,file=system.dtb > > > > > > > > > > I am not sure where the system.dtb gets built from? > > > > > > > > It is the instructions in [2] to look into. 'system.dtb' is the kernel dtb for > > > > zcu102 ([2] has been fixed). I created [2] purely for you, so respectfully I > > > > will ask you to try a little first before asking for further guidance. > > > > > > > > > > I tried, but no success. I removed the "-device loader" part for > > > loading kernel image and the device tree, and only focused on booting > > > U-Boot. > > > > > > The ATF bl31.elf was built from > > > https://github.com/ARM-software/arm-trusted-firmware, by following > > > build instructions at > > > https://trustedfirmware-a.readthedocs.io/en/latest/plat/xilinx-zynqmp.html. > > > U-Boot was built from the upstream U-Boot. > > > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > > > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > bl31.elf > > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > > NOTICE: BL31: v2.4(release):v2.4-228-g337e493 > > > NOTICE: BL31: Built : 21:18:14, Jan 20 2021 > > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > > Found: v0.0 > > > ERROR: Error initializing runtime service sip_svc > > > > > > I also tried the Xilinx fork of ATF from > > > https://github.com/Xilinx/arm-trusted-firmware, by following build > > > instructions at > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842305/Build+ARM+Trusted+Firmware+ATF > > > > > > $ ./qemu-system-aarch64 -M xlnx-zcu102,secure=on,virtualization=on -m > > > 4G -serial stdio -display none -device loader,file=u-boot.elf -kernel > > > bl31.elf > > > ERROR: Incorrect XILINX IDCODE 0x0, maskid 0x4600093 > > > NOTICE: ATF running on XCZUUNKN/silicon v1/RTL0.0 at 0xfffea000 > > > NOTICE: BL31: v2.2(release):xilinx-v2020.2 > > > NOTICE: BL31: Built : 21:52:38, Jan 20 2021 > > > ERROR: BL31: Platform Management API version error. Expected: v1.1 - > > > Found: v0.0 > > > ERROR: Error initializing runtime service sip_svc > > > > > > Then I tried to build a U-Boot from the Xilinx fork at > > > https://github.com/Xilinx/u-boot-xlnx/, still no success. > > > > > > > Best regards, > > > > Francisco Iglesias > > > > > > > > [1] qemu/docs/system/deprecated.rst > > > > [2] https://github.com/franciscoIglesias/qemu-cmdline/blob/master/xlnx-zcu102-atf-u-boot-linux.md > > > > > > Regards, > Bin From MAILER-DAEMON Thu Jan 21 14:06:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fI1-0002AL-CO for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:06:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0002A1-SC for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:40 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHr-0005mm-Rt for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:39 -0500 Received: by mail-wr1-x42f.google.com with SMTP id q7so2797154wre.13 for ; Thu, 21 Jan 2021 11:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TB7wjfajbIvKGvglJefMlToUTk7cmyyxw+srKxsN0iM=; b=tG46E8L4NhWAz79VmzTFQli25+44SF+SEEPyDCObVfykbsivI3dQzc+yyaK5dkpgpX 1QiPeanvfPTyI1K0E5v57PSSIbxhvEwb09Z1aSTjnwIyhfhOYSCSb2QZDorfq3YsCjGw zojMo4+fQF88bx72fZMLfCJ+9OgGPBVJwjCT1jU9GOFum0yj0TNsz42oY7ghRM83+vvB yPpISmsPO2DF9aXpB4aUbOuIhvf6pH8m+UdtG2rSI+8uXeQs613FTTa0Xb96Unxnlm2o vOfr4yR3MNchPQiBeO8+tHil4nYEq4fjnCBIOCEL8ZzRW5agHddZ4UJBapIM0Jx0H5Xe UAyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TB7wjfajbIvKGvglJefMlToUTk7cmyyxw+srKxsN0iM=; b=NQOolxsW+nUGTOxnX6wSqec17lVFvTGOsxn/nd99fs6kynvELmBakAFFfNfKqx39Sq VqJnF9WnjgIp1Nbi7idvrO/LhBkdIzT3bOhBCmKzzq6eq0+Gsxzjy4SycKwXyuAlZpfE YSYKpuQdNumekjn2YPxrSVSovvqqyS7NfhrhrlhshbACKBkWd8CQ2IoeflO6wWS6eJ/A NAdR7Kf/9Ccaiahx07s2Ot1ssZBs8lXMfOTSiUOcOLAOzvn0QL4PBYHBsmsP7Yc0vMMh GtUsNj4Eo6pW8lg1WrUN1sjfvu5cYBEhiKTIfCFKW7i1LLFydqPA2Bt4o4P6MaftWn4x MlgA== X-Gm-Message-State: AOAM532/QKaabLOOS5XMyny5VJ+u3sFovxIZTxbG6Fkw+s0ovU6F4tgD 8UuYfJB4HGC2hHIz9lojEG+FEwbjQk2QNQ== X-Google-Smtp-Source: ABdhPJw6OAW6z6R0PwKdv2TRpmORVWal62iEh4QvR5SvmUf9G/bzdjWpF7811EK/CKj595+XhtSX6w== X-Received: by 2002:adf:dc89:: with SMTP id r9mr932065wrj.52.1611255989324; Thu, 21 Jan 2021 11:06:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Date: Thu, 21 Jan 2021 19:06:01 +0000 Message-Id: <20210121190622.22000-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:40 -0000 Add a simple test of the CMSDK watchdog, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 82 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c new file mode 100644 index 00000000000..c6add1fee85 --- /dev/null +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -0,0 +1,80 @@ +/* + * QTest testcase for the CMSDK APB watchdog device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz, + * which is 80ns per tick. + */ +#define WDOG_BASE 0x40000000 + +#define WDOGLOAD 0 +#define WDOGVALUE 4 +#define WDOGCONTROL 8 +#define WDOGINTCLR 0xc +#define WDOGRIS 0x10 +#define WDOGMIS 0x14 +#define WDOGLOCK 0xc00 + +static void test_watchdog(void) +{ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(500 * 80 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine lm3s811evb"); + + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 010405b0884..58956497888 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c F: include/hw/watchdog/cmsdk-apb-watchdog.h +F: tests/qtest/cmsdk-apb-watchdog-test.c F: hw/misc/tz-ppc.c F: include/hw/misc/tz-ppc.h F: hw/misc/tz-mpc.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 74addd74868..9e2ebc47041 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx = \ 'npcm7xx_watchdog_timer-test'] qtests_arm = \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:06:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fI4-0002D9-9o for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0002Aj-VL for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:41 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHr-0005lc-TA for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:41 -0500 Received: by mail-wr1-x42f.google.com with SMTP id d16so2144579wro.11 for ; Thu, 21 Jan 2021 11:06:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lAXftL8tozQWWTPvWf+4JDafcrxm0XnUCLn5NpEaPkY=; b=pCE1bNozYjUvvwp5pd2YvLY+xKm67VBFoeN3W0PYb1xbEwS/n7ofQalSvv3g/RpH9j nUSk2+2FQLNxZhgc4ZKLSDABf0La9RaNZ8iKF3b05jEfzA4cEr4Cbl577AoNocaQ9wav MqNYDAOoIo3K7gni2kjWiaYbUFUdqT0XX98vhGHNvkrLvJTLBeF85QQyPuBY8jCFuZZg R7OovvRgxe3haCiRmFBCJg+n+x4yYgO8Qae67mXGKcYzqMjVDweWDTmyFt5LeuWIp1N0 V5vJZVUmGH/l98hfMa+l4IMcJsAOgshNzImGF7NG+ygo6vL9asgv75/XkfMElWoF04h5 H1Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lAXftL8tozQWWTPvWf+4JDafcrxm0XnUCLn5NpEaPkY=; b=Aw3Xv0Q7rFXZeDfgueFGwwgguW23NVTUKEZgzU2Q/SOoJPFbDDdzxtYqocAweUFfJ3 NgVKoT3cQfJoXzVpGnLdIhX6VBNdeJvYoS7wGG+NzCNumcoRBESuBbL7NSRtVnyPJjGs nzABAPrOnRGg3ZFsxFqaeucNfUA8VZs0wBwqpANHkqTkcBCnzZMO/OBFSagGlvstjooE fVFhwg5byHIuOjAvmF+Q0yryEmqFzLsTy7mf27EvswV0oobZFc+/ZyP+oDoXZoq1Evdb Sm1jxLv6QTHSV8e37oGBUDIuG8iZaEVGkCGQjWtpkedtpaHRDNs8r6MYaOyiMiTHV76O +tyQ== X-Gm-Message-State: AOAM5301K137lFd9xm98hYbneTTaAg6qzLMHM/pbjVbSA/Z6UbM9EKEX 9T3QNmLeEjSvMDtvQV5wjP3aC1BVcTcXCQ== X-Google-Smtp-Source: ABdhPJzZ5zqTvUptyD6EH+pY8cUauJ/gPXDqjfNByWsvt3W7i4FQ7nPSVk3si45gXwJRVC5Qtbv29g== X-Received: by 2002:adf:ec8c:: with SMTP id z12mr912237wrn.208.1611255988353; Thu, 21 Jan 2021 11:06:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Date: Thu, 21 Jan 2021 19:06:00 +0000 Message-Id: <20210121190622.22000-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:42 -0000 Add a simple test of the CMSDK APB timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 78 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-timer-test.c diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c new file mode 100644 index 00000000000..085005cce99 --- /dev/null +++ b/tests/qtest/cmsdk-apb-timer-test.c @@ -0,0 +1,76 @@ +/* + * QTest testcase for the CMSDK APB timer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40000000 + +#define CTRL 0 +#define VALUE 4 +#define RELOAD 8 +#define INTSTATUS 0xc + +static void test_timer(void) +{ + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + RELOAD, 1000); + writel(TIMER_BASE + CTRL, 9); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(20001); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(20000); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0); + + /* VALUE reloads at the following tick */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); + + /* Check write-1-to-clear behaviour of INTSTATUS */ + writel(TIMER_BASE + INTSTATUS, 0); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + writel(TIMER_BASE + INTSTATUS, 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + CTRL, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-timer/timer", test_timer); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 3216387521d..010405b0884 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h F: include/hw/arm/primecell.h F: hw/timer/cmsdk-apb-timer.c F: include/hw/timer/cmsdk-apb-timer.h +F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h F: hw/char/cmsdk-apb-uart.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8b..74addd74868 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:06:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fI4-0002Du-VJ for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:06:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0002C5-0Z for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:43 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHs-0005mv-MX for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:42 -0500 Received: by mail-wr1-x42d.google.com with SMTP id c12so2815854wrc.7 for ; Thu, 21 Jan 2021 11:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MgUOZVXgTuq+ewB882N1Uysmr2goe72Go52/tWAmfH4=; b=Y11OzRdJGKxQNZokVvT7EEd/YMEtfNqxfPCkKaDdsIWPQYvm5tVmRbf3V5AJd9NcLh VqMhDz8M3SvuMP5Ts6uBvhVyniaJ6hKiLJTxf8b1VY3ci0KfLmNubK25xS0gzSoCzXJJ rKbha/8+Ev6QUeesyjzxx4M+X1TK4kHq1v0f9DltHYeh9dBZtZDPuTP2Dg1y99HiVyjh hnwEZSBznbftF79j8GHSjFrUhos02/5nOY/8zm+SrE8gSue5Htc4AFxqJB18Qo3H85eD mmcKWppHT3DLWQgYs507NZKql06enx5VDJUzhvUwPXb5WilI78j+6giAxCUQcJjJgVG+ 3N4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MgUOZVXgTuq+ewB882N1Uysmr2goe72Go52/tWAmfH4=; b=BhfqbKGYbbPF7DbWr04iz85M/8w7nKcktVEufFG/iSRMrPWIy3OTySRr7CeokQAMaJ ykR6HECDk6aDbbqaZgKzOeMPpjrTVhji639morR+YVU4soLfVwvvJNW+b2gjAz1fcGSG 329H9jh2W0Y5yOmOM1c8rKC2C99Hk//1lzKq917AbQA9GVgzGBpQo7ZS9ogg3kZVPR40 RfOg86WsdfQNqhC5/3Q8leE2elEauiiA4dqvhS+Zt2mPm89fwNnzjc4eqypJSkbtMcCH R+LmGgSqGKVT4x91AWAq2w4hNN6gftMVMg1JK/Wqn5LOPa+2dsxH/VSg5i6xYoGYRNIa QZiQ== X-Gm-Message-State: AOAM5305iaZ+rtCiX3BNxOFXaNvxLsQxIEJFrYYpMr3iBOGX5suG8MCe BivU1epCK1WCDGwHHjix0xMr9nNm+siXCw== X-Google-Smtp-Source: ABdhPJyriSVaahPFM0phiZOSE7vZXJq2nUAapisczNOLJ/rLvuHgGK3g0woNMkJ8wI1evmR6JYpZNQ== X-Received: by 2002:a5d:6204:: with SMTP id y4mr940444wru.48.1611255990430; Thu, 21 Jan 2021 11:06:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Date: Thu, 21 Jan 2021 19:06:02 +0000 Message-Id: <20210121190622.22000-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:43 -0000 Add a simple test of the CMSDK dual timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 133 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c new file mode 100644 index 00000000000..5a29d65fd6d --- /dev/null +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c @@ -0,0 +1,131 @@ +/* + * QTest testcase for the CMSDK APB dualtimer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40002000 + +#define TIMER1LOAD 0 +#define TIMER1VALUE 4 +#define TIMER1CONTROL 8 +#define TIMER1INTCLR 0xc +#define TIMER1RIS 0x10 +#define TIMER1MIS 0x14 +#define TIMER1BGLOAD 0x18 + +#define TIMER2LOAD 0x20 +#define TIMER2VALUE 0x24 +#define TIMER2CONTROL 0x28 +#define TIMER2INTCLR 0x2c +#define TIMER2RIS 0x30 +#define TIMER2MIS 0x34 +#define TIMER2BGLOAD 0x38 + +#define CTRL_ENABLE (1 << 7) +#define CTRL_PERIODIC (1 << 6) +#define CTRL_INTEN (1 << 5) +#define CTRL_PRESCALE_1 (0 << 2) +#define CTRL_PRESCALE_16 (1 << 2) +#define CTRL_PRESCALE_256 (2 << 2) +#define CTRL_32BIT (1 << 1) +#define CTRL_ONESHOT (1 << 0) + +static void test_dualtimer(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + TIMER1LOAD, 1000); + /* enable in free-running, wrapping, interrupt mode */ + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(20001); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(20000); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); + + /* + * We are in free-running wrapping 16-bit mode, so on the following + * tick VALUE should have wrapped round to 0xffff. + */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER1INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER1CONTROL, 0); +} + +static void test_prescale(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); + + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ + writel(TIMER_BASE + TIMER2LOAD, 1000); + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ + writel(TIMER_BASE + TIMER2CONTROL, + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 256 * 501); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 256 * 500); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); + + /* In periodic mode the tick VALUE now reloads */ + clock_step(256); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER2INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER2CONTROL, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 58956497888..118f70e47fb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h +F: tests/qtest/cmsdk-apb-dualtimer-test.c F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 9e2ebc47041..69dd4a8547c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:06:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fI7-0002G8-Dd for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:06:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI2-0002B3-DH for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:42 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:32891) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHq-0005ka-Nz for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:42 -0500 Received: by mail-wr1-x42d.google.com with SMTP id 7so2830883wrz.0 for ; Thu, 21 Jan 2021 11:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CMkjp0id/Ultib0Bf01Fa0R4lEkPZ5/dYQA5kFPJtl0=; b=ZzR2c6LcIZG+nAvsY8WT9NBeBekCHgIaKMSHtduHxKdS8aEKGaivd62tbC7yz7/7HG iZPqSndP3TLv4W0696PeTouTpl9oEoJQ1wpUSeIfSDpsWXPs0myMNMY/xr/NTndZpStA E6vT78LnVR21gmhRu2i3X7t/av/rD2jm9l4zoriX1NO8rY/R9p2pxph0znXM1UI95uXk BOAm6BqjDjp2kG+RRxI6OPR+dFXgUP9GJRGCEzuzEmHxeIo4InUDkBVkGX9MeTp6wggM GEuvtthWVEIFNNsrxWaxH6Uek67sO19X0Fx/g5YH1aT9MtIxGx9Z6mJdpsGIMXbSOqVu GFyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CMkjp0id/Ultib0Bf01Fa0R4lEkPZ5/dYQA5kFPJtl0=; b=HP5jJHBKrW4gMPF4pS2537AZd+tAFOST7vY+1G7AmHqIKcWplI8bCaaZNvkuOn1Uy2 9hZs5kVvG3tHpTFrhktg0fBXiFipSuGcGi1nWaNyvNiZnDAn3BoSgM1eZJEwx3lSoioX l9pq29G1W6g5yofin+gJAN2eC/cWa3h3/nA0Cr+fcBwGhqSpJTaq1/kjL3eqamINIigk cZ+sBnrEP12G6HlMKoLhmSaTxzKvfZi8DZLF5DQm9me85p2Mg+FuSZp6pRRDKm7fhl5b 2t1fFaAy+96/GgBPHXA96kE8gS0FXXN8kTzwzIOhQ8v9etfxjHAKho0GWdT1P0NdVY52 bS9w== X-Gm-Message-State: AOAM531H1bW2y/bO9tBT9kECaJ9ano5+Q9dzqtFQqXX/pWtLIvWhoAHz ng1XGtNqK4QAh7BlQyiH3DUryzfyJp1nlA== X-Google-Smtp-Source: ABdhPJwSXHMqP14E55+6xcXB7ek2tOIi/siekqYIsekSYoBPmPi+9vWzau5chQtQ7FagYaePCmEaxQ== X-Received: by 2002:a5d:43d2:: with SMTP id v18mr912137wrr.326.1611255986528; Thu, 21 Jan 2021 11:06:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Date: Thu, 21 Jan 2021 19:05:58 +0000 Message-Id: <20210121190622.22000-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:42 -0000 The ptimer API currently provides two methods for setting the period: ptimer_set_period(), which takes a period in nanoseconds, and ptimer_set_freq(), which takes a frequency in Hz. Neither of these lines up nicely with the Clock API, because although both the Clock and the ptimer track the frequency using a representation of whole and fractional nanoseconds, conversion via either period-in-ns or frequency-in-Hz will introduce a rounding error. Add a new function ptimer_set_period_from_clock() which takes the Clock object directly to avoid the rounding issues. This includes a facility for the user to specify that there is a frequency divider between the Clock proper and the timer, as some timer devices like the CMSDK APB dualtimer need this. To avoid having to drag in clock.h from ptimer.h we add the Clock type to typedefs.h. Signed-off-by: Peter Maydell --- Side note, I forget why we didn't go for 64.32 fixedpoint for the Clock too. I kinda feel we might run into the "clocks can't handle periods greater than 4 seconds" limit some day. Hopefully we can backwards-compatibly expand it if that day ever comes... The 'divisor' functionality seemed like the simplest way to get to what I needed for the dualtimer; perhaps we should think about whether we can have generic lightweight support for clock frequency divider/multipliers... --- include/hw/ptimer.h | 22 ++++++++++++++++++++++ include/qemu/typedefs.h | 1 + hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 412763fffb2..c443218475b 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s); */ void ptimer_set_period(ptimer_state *s, int64_t period); +/** + * ptimer_set_period_from_clock - Set counter increment from a Clock + * @s: ptimer to configure + * @clk: pointer to Clock object to take period from + * @divisor: value to scale the clock frequency down by + * + * If the ptimer is being driven from a Clock, this is the preferred + * way to tell the ptimer about the period, because it avoids any + * possible rounding errors that might happen if the internal + * representation of the Clock period was converted to either a period + * in ns or a frequency in Hz. + * + * If the ptimer should run at the same frequency as the clock, + * pass 1 as the @divisor; if the ptimer should run at half the + * frequency, pass 2, and so on. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block. + */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock, + unsigned int divisor); + /** * ptimer_set_freq - Set counter frequency in Hz * @s: ptimer to configure diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 976b529dfb5..68deb74ef6f 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState; typedef struct BusClass BusClass; typedef struct BusState BusState; typedef struct Chardev Chardev; +typedef struct Clock Clock; typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct CPUAddressSpace CPUAddressSpace; diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 2aa97cb665c..6ba19fd9658 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -15,6 +15,7 @@ #include "sysemu/qtest.h" #include "block/aio.h" #include "sysemu/cpus.h" +#include "hw/clock.h" #define DELTA_ADJUST 1 #define DELTA_NO_ADJUST -1 @@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period) } } +/* Set counter increment interval from a Clock */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk, + unsigned int divisor) +{ + /* + * The raw clock period is a 64-bit value in units of 2^-32 ns; + * put another way it's a 32.32 fixed-point ns value. Our internal + * representation of the period is 64.32 fixed point ns, so + * the conversion is simple. + */ + uint64_t raw_period = clock_get(clk); + uint64_t period_frac; + + assert(s->in_transaction); + s->delta = ptimer_get_count(s); + s->period = extract64(raw_period, 32, 32); + period_frac = extract64(raw_period, 0, 32); + /* + * divisor specifies a possible frequency divisor between the + * clock and the timer, so it is a multiplier on the period. + * We do the multiply after splitting the raw period out into + * period and frac to avoid having to do a 32*64->96 multiply. + */ + s->period *= divisor; + period_frac *= divisor; + s->period += extract64(period_frac, 32, 32); + s->period_frac = (uint32_t)period_frac; + + if (s->enabled) { + s->need_reload = true; + } +} + /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:06:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIC-0002HQ-FX for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:06:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55576) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI5-0002F0-LT for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:47 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:50397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005pV-GV for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:45 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 190so2412857wmz.0 for ; Thu, 21 Jan 2021 11:06:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=71fXmSxG4SGO/lxGONnTuENMy4+MVUOt7YwIy8LfeBo=; b=gye4933kAc2ne7YO71GYHXD59s2FPYqiDoWpqU3dzr5tETDWrm5S+CVr75TOFVOsJC rLHf1+fV/40Fbh35e3dI2rQH51mk9grziKBKVaZmPQgnwvXbw2HDPek9KadtEEVpcZwL vfyJGzQCABdjOiX+gc96aM/7bNuYR4a2SyNaibKB/YDeThJiMrKvbeZQKls9vN/H5EiZ 4UyTxSHdiHL8sXnlQEO8zkEtiYQGkpBmg47muvvervCcaykQYfFpV737Bg06UXlHKeMC 1xP08o24dZKDu466+vQXsZylv+i1ktZrDsfomuiAj2SkYunsV29yIjo9OMVCvc0SqUaW tZIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=71fXmSxG4SGO/lxGONnTuENMy4+MVUOt7YwIy8LfeBo=; b=BUC/sDR2lyjAhCMpv6gdJaKL2hQIG7wL9iRUreEidNlRAVbzNluptM5UJov+nkVrB3 SkMP9ISloojdCpDyko7XsPLwJPEiGZSIAN2PIA+3tCW/f6/I9IcQ5LtaUAww6BfuyCQb e0k+3WdoQ9AZ9BHfG6bsmaeqwTioXWR3fh4f+RqZTvKKN+Vlhf8uvfREbGTP11sf3NHW m6x7G5tooMBvPDLciW5pijaU04q00GKlXSuokxLu0QLndvashXfzaMhMMWZ4Ywvo5QrL gW6QBpFoCDCtnrSCnESJRHjBYG4MCR/TJCKaDlUsXymFeLKNHyanlnDfhhVVzYQWhwTm ICiw== X-Gm-Message-State: AOAM5311eN9pIBhctm47bMkDSujrCB9Z6eO4xh0zrk4ecDpttGDDEION rFJssBHctTjpsWgx9sgYAB0/P+I/Fr+JgQ== X-Google-Smtp-Source: ABdhPJy+thCtVML5VkorJnHUJKfiDdXDawra/TmHMbijyF2wxAA2i/ZKzkNZVABKeaAT3meBtCEWUg== X-Received: by 2002:a1c:7f94:: with SMTP id a142mr690186wmd.145.1611255996983; Thu, 21 Jan 2021 11:06:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Date: Thu, 21 Jan 2021 19:06:09 +0000 Message-Id: <20210121190622.22000-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:47 -0000 The old-style convenience function cmsdk_apb_timer_create() for creating CMSDK_APB_TIMER objects is used in only two places in mps2.c. Most of the rest of the code in that file uses the new "initialize in place" coding style. We want to connect up a Clock object which should be done between the object creation and realization; rather than adding a Clock* argument to the convenience function, convert the timer creation code in mps2.c to the same style as is used already for the watchdog, dualtimer and other devices, and delete the now-unused convenience function. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-timer.h | 21 --------------------- hw/arm/mps2.c | 18 ++++++++++++++++-- 2 files changed, 16 insertions(+), 23 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index fc2aa97acac..54f7ec8c502 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -45,25 +45,4 @@ struct CMSDKAPBTimer { uint32_t intstatus; }; -/** - * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER - * @addr: location in system memory to map registers - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate) - */ -static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr, - qemu_irq timerint, - uint32_t pclk_frq) -{ - DeviceState *dev; - SysBusDevice *s; - - dev = qdev_new(TYPE_CMSDK_APB_TIMER); - s = SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, timerint); - return dev; -} - #endif diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 9a8b23c64ce..f762d1b46af 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -83,6 +83,7 @@ struct MPS2MachineState { /* CMSDK APB subsystem */ CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; + CMSDKAPBTimer timer[2]; }; #define TYPE_MPS2_MACHINE "mps2" @@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine) } /* CMSDK APB subsystem */ - cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); - cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); + for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { + g_autofree char *name = g_strdup_printf("timer%d", i); + hwaddr base = 0x40000000 + i * 0x1000; + int irqno = 8 + i; + SysBusDevice *sbd; + + object_initialize_child(OBJECT(mms), name, &mms->timer[i], + TYPE_CMSDK_APB_TIMER); + sbd = SYS_BUS_DEVICE(&mms->timer[i]); + qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); + } + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIJ-0002Lb-Ay for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI9-0002Gq-9F for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:50 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:32897) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005pL-Gg for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:49 -0500 Received: by mail-wr1-x432.google.com with SMTP id 7so2831269wrz.0 for ; Thu, 21 Jan 2021 11:06:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NEZ5U7Po5BeujzVL1PMxzLMD8dogU0kUTKX4d32S7Mw=; b=yae5CO8Pdpe1iCQd1WZYhi23ZllqMFL4g+A/13mTrfun9hlfzhyBy9VEID5WM+0bch z5dZrEquwThQ8AMai651EEcttcY8H5VpXgGklpP/Xm+Y8hEL2b6LYnhHruluNcGbjp0o 0Bzc5efxuTDU3gjZzlNDXBD5JMfwUl0ZkWKLhUqPxCdfDkyzp986+1B8EPupdOIW6HSd 85ack7jonZnobQ0reN+jFjzZubW7ZZbZ+oyKJIechoCaFfC5dO2pz0u9NszdGutg63dx uHSThFO+kPVbt6B9KbXE+x31/QFC1sCo1rhvFSTKK0bq7MhHtmuxgcTaHM+nS4uENQ5g riNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NEZ5U7Po5BeujzVL1PMxzLMD8dogU0kUTKX4d32S7Mw=; b=tqcBV3jtpsmxtJjFZEdlVA2bvnjGMnGH7tcJH0lZ893mS1T24gOAdz4+PaVqFB0YZI 6Fmg2hGtM/zq3qjO+0vI1b0GWFP8UZtAfpyeTmQbP5D7TnxZv45gUQI1tlAeYtBmD/rz xbCsWluC13ysVKXjaP3jNSuGDVvdV2tjmmwXtoZqIb7tLlId+x3xQv8GPQfpkZLWTBiG eAgLJO383LgHrk3hufHHyJ4gVwd3nxv/JBk3s+AhLgqHB6eyIgMm+haPJ25KPsP1JA+/ r+dsw+i6nV/uc+KPhRCoH+r0uWwxPr9uq9I1iMh0XgpChXbrcYmzK6j31mSniREuoVKg cbvA== X-Gm-Message-State: AOAM532cO+nJbUzksczxz4UN01osCH6/bjLA/aIRenxCxFhg93c0L+fI VihNqKf1aVHm/7/V5NjVozEChzE3jgi0mA== X-Google-Smtp-Source: ABdhPJzd8zq3H0OQk9JUwXldL1wksWUqcC9tOkplhwB7g4YdGPgUKZYh6Vtl4QkUMQRYQzmB62hAzQ== X-Received: by 2002:adf:8285:: with SMTP id 5mr847952wrc.289.1611255996081; Thu, 21 Jan 2021 11:06:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 11/25] hw/arm/armsse: Wire up clocks Date: Thu, 21 Jan 2021 19:06:08 +0000 Message-Id: <20210121190622.22000-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:52 -0000 Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 6 ++++++ hw/arm/armsse.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 4860a793f4b..bfa1e79c4fe 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -37,6 +37,8 @@ * per-CPU identity and control register blocks * * QEMU interface: + * + Clock input "MAINCLK": clock for CPUs and most peripherals + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock @@ -103,6 +105,7 @@ #include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" +#include "hw/clock.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" #include "qom/object.h" @@ -209,6 +212,9 @@ struct ARMSSE { uint32_t nsccfg; + Clock *mainclk; + Clock *s32kclk; + /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d2ba0459c44..4349ce9bfdb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,6 +21,7 @@ #include "hw/arm/armsse.h" #include "hw/arm/boot.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) assert(info->sram_banks <= MAX_SRAM_BANKS); assert(info->num_cpus <= SSE_MAX_CPUS); + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); for (i = 0; i < info->num_cpus; i++) { @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * map its upstream ends to the right place in the container. */ qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; } @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; } @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; } @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * 0x4002f000: S32K timer */ qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; } @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; } @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; } @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; } @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, static const VMStateDescription armsse_vmstate = { .name = "iotkit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(mainclk, ARMSSE), + VMSTATE_CLOCK(s32kclk, ARMSSE), VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() } -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIL-0002MP-5A for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0002Cs-UK for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:39202) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHx-0005kC-0p for qemu-arm@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Date: Thu, 21 Jan 2021 19:05:57 +0000 Message-Id: <20210121190622.22000-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:44 -0000 This patchset converts the CMSDK timer, watchdog and dualtimer devices to use the Clock framework instead of an integer property specifying a frequency in Hz. The series is quito a lot of patches but they should be mostly small and I hope easy to review. The motivation here is the upcoming Arm SSE-300 model: this has a new kind of timer device, which I wanted to write in the modern style with a Clock input. That meant the ARMSSE container object needed to know about Clocks, so converting the existing devices it used to Clocks seemed like a good first step. The series as a whole is a migration compat break for the machines involved: mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. Series structure: * patches adding new clock and ptimer API functions * add tests for the devices * add Clock inputs to devices, which do nothing for now * wire up the clocks in the code that uses the devices * make the devices use the clocks and ignore the frq properties * remove the setting of the frq properties in code using the devices * remove the frq properties from the devices The new ptimer and clock functions are probably the most interesting part: * ptimer_set_period_from_clock(ptimer, clk, divisor) is for setting the period of a ptimer directly from a Clock (possibly accounting for the frequency being divided by some integer first) -- this avoids possible rounding errors if we went via ptimer_set_period() or ptimer_set_freq() * clock_has_source() returns true if an input Clock has been connected to an output clock; this is for devices to be able to check in their realize method that a mandatory clock was wired up by the board (More detailed info and rationale in patches 1 and 2.) A couple of bits of food-for-thought as a result of working with the relatively-new Clock APIs: * it might be worth thinking about whether we can have a fairly lightweight implementation of a clock-divider or clock-multiplier, because I feel they are pretty common. (For this series I opted just to handle this via the ptimer_set_period_from_clock() divisor argumuent.) * it feels a little awkward that devices with an input Clock need to do ptimer_set_period_from_clock() or similar both in their realize method (to cope with fixed-frequency input clocks, because the clock callback functions are not called when board setup code creates and configures those) and in the clock callback function (to cope with variable-frequency clocks) * I found it odd that ptimer's period representation is 64.32 fixedpoint 2^-32 ns units, whereas Clock's is only 32.32 (so ptimer can handle much larger periods than Clock can.) I forget why we didn't go for the same representation in Clock as we have for ptimer... * there's no MAINTAINERS entry for the Clock framework I don't think these need to be blockers on this series, though. thanks -- PMM Peter Maydell (25): ptimer: Add new ptimer_set_period_from_clock() function clock: Add new clock_has_source() function tests: Add a simple test of the CMSDK APB timer tests: Add a simple test of the CMSDK APB watchdog tests: Add a simple test of the CMSDK APB dual timer hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer hw/timer/cmsdk-apb-timer: Add Clock input hw/timer/cmsdk-apb-dualtimer: Add Clock input hw/watchdog/cmsdk-apb-watchdog: Add Clock input hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" hw/arm/armsse: Wire up clocks hw/arm/mps2: Inline CMSDK_APB_TIMER creation hw/arm/mps2: Create and connect SYSCLK Clock hw/arm/mps2-tz: Create and connect ARMSSE Clocks hw/arm/musca: Create and connect ARMSSE Clocks hw/arm/stellaris: Convert SSYS to QOM device hw/arm/stellaris: Create Clock input for watchdog hw/timer/cmsdk-apb-timer: Convert to use Clock input hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input tests/qtest/cmsdk-apb-watchdog-test: Test clock changes hw/arm/armsse: Use Clock to set system_clock_scale arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS docs/devel/clocks.rst | 16 +++ include/hw/arm/armsse.h | 14 +- include/hw/clock.h | 15 ++ include/hw/ptimer.h | 22 +++ include/hw/timer/cmsdk-apb-dualtimer.h | 5 +- include/hw/timer/cmsdk-apb-timer.h | 34 ++--- include/hw/watchdog/cmsdk-apb-watchdog.h | 5 +- include/qemu/typedefs.h | 1 + hw/arm/armsse.c | 47 +++++-- hw/arm/mps2-tz.c | 14 +- hw/arm/mps2.c | 28 +++- hw/arm/musca.c | 13 +- hw/arm/stellaris.c | 170 +++++++++++++++++------ hw/core/ptimer.c | 34 +++++ hw/timer/cmsdk-apb-dualtimer.c | 53 +++++-- hw/timer/cmsdk-apb-timer.c | 55 ++++---- hw/watchdog/cmsdk-apb-watchdog.c | 29 ++-- tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++ tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++ tests/qtest/cmsdk-apb-watchdog-test.c | 132 ++++++++++++++++++ MAINTAINERS | 3 + tests/qtest/meson.build | 3 + 22 files changed, 758 insertions(+), 142 deletions(-) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c create mode 100644 tests/qtest/cmsdk-apb-timer-test.c create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIM-0002N4-SU for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI9-0002GQ-3i for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:50 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:32894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005oV-Gd for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:47 -0500 Received: by mail-wr1-x42f.google.com with SMTP id 7so2831167wrz.0 for ; Thu, 21 Jan 2021 11:06:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H+D/Gt7JsF9hn1kRelKr/4gM1Ewyi0uJ0hZ0lBf0vAM=; b=u/LvHBnQzZEe8w8M/W6QpoL4pX8rxzdR7/8jMb2FIn0Vhh+UuayocOGuvRt8zMK+O+ koDEMcOrMS0lZ4gnfbvvXJErp0/i/NtYB0eu1h5KHzglCJfoSW60VkUZMk4NlWTGRp16 +OsXoDhxSTRVX+ZLZjFxinzhZt+QNuViCTvh1kIcSpe6I5SwqGJja77g9GNYKCe5YBZS xTO8YuRZ/QdcUA6u1UHDbl6v1dU/LWAdUQmWEsuwcXBUi8frIlN5S7dfBin/Zn1+FsqE pUra+PE4l/5h8V2OhRfc2SDWQaYDI6DpnOiIn9cM0yz5SlEqEbDRJkQ2jHEVQNqKZp6d aZ8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H+D/Gt7JsF9hn1kRelKr/4gM1Ewyi0uJ0hZ0lBf0vAM=; b=f+xE5GVYZR1Eqb5BHeF0IyGWuRf0kPSIxSehTfPNOf5/sPf/ZjLjlNYGLIqLkSvFnu 54uoDTKNQHnPaCiDnpYr5Hpk97uDF53Vh2DHFecNS5weo+TN3MXpqMVMtjpiuszxw9Ky 1kbHqEqk3Shle/Ut9QuHYaoQVOxScSKHPwyuHXVVXc0cZol2mw+ALYbUrfzmYhAKml3Z /AcEo9t6/n7ulsYhdL1fJwhkbWekYIovTMbOEOyyeIzMsrCgi67NgfU8iRdC0YOpaJbv f7puaguL4r+6VX0CLERNDuC2dEehgtgwDqUONFh3pQIcU2iNV0j5TBRUbkx3opoi+zO+ uu5g== X-Gm-Message-State: AOAM530BIh3F0WGsGMyl91qWq37v1YqVqkYdy4g4gkyMM08QC0jgtmJZ z6TjXpDKSygle6QMb89iNOwfksJ3t4QtRg== X-Google-Smtp-Source: ABdhPJzJvrDMu+NAjev6D3ygcCTfhQ+CM2U/fSsab161YWgjA9tfI7e2m7CTTtO9snOu+GyHi5iy+w== X-Received: by 2002:a5d:68ce:: with SMTP id p14mr896028wrw.386.1611255994104; Thu, 21 Jan 2021 11:06:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input Date: Thu, 21 Jan 2021 19:06:06 +0000 Message-Id: <20210121190622.22000-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:52 -0000 As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the wdogclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. Signed-off-by: Peter Maydell --- include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++ hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 3da0d43e355..34069ca6969 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked + * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt * @@ -33,6 +34,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" @@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog { uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; + Clock *wdogclk; uint32_t control; uint32_t intstatus; diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 5bbadadfa68..b03bcb73628 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" @@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_watchdog_vmstate = { .name = "cmsdk-apb-watchdog", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog), VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), VMSTATE_UINT32(control, CMSDKAPBWatchdog), VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIQ-0002Ri-F4 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIL-0002MM-4y for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46138) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005kj-13 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:58 -0500 Received: by mail-wr1-x42a.google.com with SMTP id q7so2797091wre.13 for ; Thu, 21 Jan 2021 11:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=upN7NId7waDqdq/y54Hzrsu+F+aVKMHy5OMUTW9rDEw=; b=sn0dGRtex5P42T3hk2ht1eoYTF/07UWBYlpSpd3RZbe8zb9QSZ4BIdtMinLn+Uxt0o 2bNlUqkjAroSzWDqS/6rvaOr93syDheLNOfwXaqpDFjyqAUzZMAx5n2I6Z77uZLuscUk 79N2daVjLwtxNHbJDblLS2TpjR3w5P9KnUV5VPFKJrJQ7oAQiln3Sdny6I03xtjWfSO4 t11S/3QGsYWV2BnugGlB8mLqViHSzPkgi6EKxlItt1LYZraJIecs90zfilH4+aWkuKq0 I38sTjrCwRakEVEfu/kfI4s5wa9437NhcOlDxG/8ZT3UcBb3cHFFCxvMmYFYNVHbi3hw VNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=upN7NId7waDqdq/y54Hzrsu+F+aVKMHy5OMUTW9rDEw=; b=nxgHgqHZBDRieKF3fFgHh2xHf4/LBkEd8vCi5VK0c/BEva/fa9RYoNCPXwJFVvk+U4 ru6sEUar9xFcq7+VCstXTFy9/f7yeuvkj1Xf7T2JNfHd8h54C7CsYwGSf+GRu9SdFw5q 86OBfD8sjWU42TQZIhxUHJvU+u1ueBfsiXor7NTxerdzvCcO68Tt2eZ+Dz6lKf0Zy9F1 TDqEnZod87AioWSsbyYmPK3dm9eu42rIcEAh272pjIHSgu/azh3+8BYSbbv32+TL04Pq X+a4WsseIK62L/GGlyx30bVqL+vqD9V7XOSjNq6ULcOLmutBghehXhJCsvsX/Z6Gv2nf 9scw== X-Gm-Message-State: AOAM532Txj0AxE6kuzerX6YJFbQ2ltjafHqwxfxZV59cq21pzaPbWbDR sk/GyVuiJpQsXtRgQyf/d4FI1c+6qJiSZw== X-Google-Smtp-Source: ABdhPJyYWPeD96pTaj0aV0nL8Ev8OprHynYHbCPzOpziSnqAewyJM8u5fh0paz6SPgIOA/xFqA9W+g== X-Received: by 2002:adf:cc81:: with SMTP id p1mr858184wrj.339.1611255987447; Thu, 21 Jan 2021 11:06:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 02/25] clock: Add new clock_has_source() function Date: Thu, 21 Jan 2021 19:05:59 +0000 Message-Id: <20210121190622.22000-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:03 -0000 Add a function for checking whether a clock has a source. This is useful for devices which have input clocks that must be wired up by the board as it allows them to fail in realize rather than ploughing on with a zero-period clock. Signed-off-by: Peter Maydell --- docs/devel/clocks.rst | 16 ++++++++++++++++ include/hw/clock.h | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 2548d842322..c54bbb82409 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -235,6 +235,22 @@ object during device instance init. For example: /* set initial value to 10ns / 100MHz */ clock_set_ns(clk, 10); +To enforce that the clock is wired up by the board code, you can +call ``clock_has_source()`` in your device's realize method: + +.. code-block:: c + + if (!clock_has_source(s->clk)) { + error_setg(errp, "MyDevice: clk input must be connected"); + return; + } + +Note that this only checks that the clock has been wired up; it is +still possible that the output clock connected to it is disabled +or has not yet been configured, in which case the period will be +zero. You should use the clock callback to find out when the clock +period changes. + Fetching clock frequency/period ------------------------------- diff --git a/include/hw/clock.h b/include/hw/clock.h index 6382f346569..e5f45e2626d 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk); */ void clock_set_source(Clock *clk, Clock *src); +/** + * clock_has_source: + * @clk: the clock + * + * Returns true if the clock has a source clock connected to it. + * This is useful for devices which have input clocks which must + * be connected by the board/SoC code which creates them. The + * device code can use this to check in its realize method that + * the clock has been connected. + */ +static inline bool clock_has_source(const Clock *clk) +{ + return clk->source != NULL; +} + /** * clock_set: * @clk: the clock to initialize. -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIQ-0002Sm-Ss for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIN-0002PJ-OQ for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005oe-2p for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: by mail-wm1-x32b.google.com with SMTP id y187so2436343wmd.3 for ; Thu, 21 Jan 2021 11:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8qYEJ7vFQTOhZhRO/AtRAFtnFxVNIz2T8FPyZBXE8CU=; b=rq2x7PKzCDz83IUDc0edd0kgJTuBpexH0TnVe/OCkjZzPAqY9WrnD4/IuGCGFuVXJE Xj7ei0j7aPYJMKijAp9pldq0MvQvokHMWI8GrdgDFXMV+cQCF1bKtMu98QSJ/VrFB0PY vnXJBbUHWXpJyryN0xv1Ej896E75b+uR7ZDTov3ZiquH7+ShKwC17jb/+QwG8nrzyALS RqtaMlHhx3ka6UieK7Kz27HiTM4zQwA6WL6CzkPoW75K54OBk/QoYAGNz7STL04ux3vi blTglX95MhCZGeGQUHs8KSVR1SW+KDK8rWMb58MxpYHe5C8xNy31cAFIbvx4x0MR86Eb 26ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qYEJ7vFQTOhZhRO/AtRAFtnFxVNIz2T8FPyZBXE8CU=; b=Y5VdmO6Qd4F723kyatsIRvA1aqXeJfvN5+qx6/w5gkGtYByWwQw1xz8zPKYJtxorxF ZjJlIx0tNXhAWfVQKtI6F8cFHo20WK+5PyiYCp0MUEZ3Dm1KDsO6WCmhsnkBI+7gh5V5 74XreAGxMxN6UajlosRD3cRdfLoF1ykexc+uGPDbXfUoA1ErU/atMrB3tF8jvPVpV3jo eChd0tmBTQzsI06WUcmrwjKWs7vKBb2RjDMdZImbWHiZ+zMV5MiYJBB9WsNptjER4KHD Cd60gFmME1xQFBzWpZunthfXq+Ujf+3jnsfC11OB7H6HVkHA0hk/uFTEkgT55cdje5k+ BhEg== X-Gm-Message-State: AOAM530WMDV56rcRbEqfPCvK5quXo2ANu6DaXWc/NAdEnvN6bSVkMYKr jQ+UoxdDSrtZ5pBf4u+uH3gWkAEKd7b7LQ== X-Google-Smtp-Source: ABdhPJxktaBdtjDFDggb1DzlFO7Vfvdpq8WjaqpWcFuwTqh5r+Guj1sOi9hGmBbOX/6XjiEfUreK4Q== X-Received: by 2002:a1c:e902:: with SMTP id q2mr690920wmc.143.1611255995115; Thu, 21 Jan 2021 11:06:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Date: Thu, 21 Jan 2021 19:06:07 +0000 Message-Id: <20210121190622.22000-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:04 -0000 While we transition the ARMSSE code from integer properties specifying clock frequencies to Clock objects, we want to have the device provide both at once. We want the final name of the main input Clock to be "MAINCLK", following the hardware name. Unfortunately creating an input Clock with a name X creates an under-the-hood QOM property X; for "MAINCLK" this clashes with the existing UINT32 property of that name. Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be deleted. Commit created with: perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 2 +- hw/arm/armsse.c | 6 +++--- hw/arm/mps2-tz.c | 2 +- hw/arm/musca.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 83f5e28c16e..4860a793f4b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -39,7 +39,7 @@ * QEMU interface: * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK" is the frequency of the main system clock + * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index baac027659d..d2ba0459c44 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -47,7 +47,7 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -59,7 +59,7 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), @@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) } if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK property was not set"); + error_setg(errp, "MAINCLK_FRQ property was not set"); return; } diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3707876d6d4..6a9eed9022a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* diff --git a/hw/arm/musca.c b/hw/arm/musca.c index b50157f63a6..d82bef11cf2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -375,7 +375,7 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIS-0002Up-MC for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIC-0002IF-VY for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:54 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005o5-Gb for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:52 -0500 Received: by mail-wm1-x32c.google.com with SMTP id c124so2396886wma.5 for ; Thu, 21 Jan 2021 11:06:33 -0800 (PST) DKIM-Signature: v=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Date: Thu, 21 Jan 2021 19:06:04 +0000 Message-Id: <20210121190622.22000-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:56 -0000 As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. Since the device doesn't already have a doc comment for its "QEMU interface", we add one including the new Clock. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++ hw/timer/cmsdk-apb-timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index baa009bb2da..fc2aa97acac 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -15,11 +15,19 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) +/* + * QEMU interface: + * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "pclk": clock for the timer + * + sysbus MMIO region 0: the register bank + * + sysbus IRQ 0: timer interrupt TIMERINT + */ struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; @@ -29,6 +37,7 @@ struct CMSDKAPBTimer { qemu_irq timerint; uint32_t pclk_frq; struct ptimer_state *timer; + Clock *pclk; uint32_t ctrl; uint32_t value; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index ae9c5422540..c63145ff553 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -35,6 +35,7 @@ #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-timer.h" #include "migration/vmstate.h" @@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) @@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_timer_vmstate = { .name = "cmsdk-apb-timer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_CLOCK(pclk, CMSDKAPBTimer), VMSTATE_UINT32(ctrl, CMSDKAPBTimer), VMSTATE_UINT32(value, CMSDKAPBTimer), VMSTATE_UINT32(reload, CMSDKAPBTimer), -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIT-0002Vh-RA for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIC-0002IJ-W6 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:54 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:45322) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005pd-Gd for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:52 -0500 Received: by mail-wr1-x432.google.com with SMTP id m1so2128650wrq.12 for ; Thu, 21 Jan 2021 11:06:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HsBmuYHOmkArh8+q9PdOyKcEeylmhF/poYkrDZaJKS8=; b=yisn4cUGdww2SlwDR5c54nQMqTTYh8EOQhrsJdfyPmvpyRwCE4n9L7WBTuUtLtCA3C WOYyIvqlt49QfbiliXLikJBY8lUhhUi/1TPb98YY5RYpUUXHg39iN4RgC8ZuuQoYzwS1 8E4yWg5nDiapQt03a3FT35rlSoWzWIVpL7xut+bnmMs+/tDyeOUhEe7lq1t2XZKyNwTu P3amsZQnvd6TFsZPQXZ5ht9fmyFYuQtDlmdzPicSkT8s6qZS4lWElGFNDUOYj+WQsoq9 4V1rqC/6OgbVHtBm+OJtevMXKPxxFXz+WjlN99igzXoo5Bthw1EstlGNvFmvqsqowCq/ RZWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HsBmuYHOmkArh8+q9PdOyKcEeylmhF/poYkrDZaJKS8=; b=nXjZbpRDbd5QGls0bganqGpOHL8Y58XHAB8CsN4tjO7xukbjC41nmabLdTfByrP27E O0hm03qGFdN8ZlyoXb5kVUe5IYAyVaDWy36cwSIk67S+kJ8VLn430eVwbig9MjIfKmsj bMm0J2YGI2PNu1htQUkhEeW9J6MnTjVgmLZCdKYKgiaanF8YmPgpu8co6P9VN1OFvdfJ mFialwz2ypLv/GpgYTk5fmFkjsny7xAUtyrJgQL/BHiqn5+UkH7+dLqIpQMuCPxNoc4c Sa78elK8tppqVuvDUMMWahMpw6Mk7/5zTvOx5KuXUzv0zW3ITp3gZLUmZc+GHpM+3nWu KCLg== X-Gm-Message-State: AOAM532Gd10/kVylwE62l+IYZODKh3596Wd+Y0aC1EYSYXk1oeKYLK2f 8yX+t9TP2AubOPMPwrWaVM0BslcQuKLP4Q== X-Google-Smtp-Source: ABdhPJzCOY3Tpk8wDFnDTt2e2WcOYscY7KjjSu3EgsAMGKKY4ihR+p2gphdTxZi6Mv2o/Gprbp5eVA== X-Received: by 2002:adf:f512:: with SMTP id q18mr900026wro.55.1611255997892; Thu, 21 Jan 2021 11:06:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Date: Thu, 21 Jan 2021 19:06:10 +0000 Message-Id: <20210121190622.22000-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:56 -0000 Create a fixed-frequency Clock object to be the SYSCLK, and wire it up to the devices that require it. Signed-off-by: Peter Maydell --- hw/arm/mps2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index f762d1b46af..cd1c215f941 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -46,6 +46,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" +#include "hw/qdev-clock.h" #include "qom/object.h" typedef enum MPS2FPGAType { @@ -84,6 +85,7 @@ struct MPS2MachineState { CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; + Clock *sysclk; }; #define TYPE_MPS2_MACHINE "mps2" @@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* This clock doesn't need migration because it is fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine) TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); @@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, qdev_get_gpio_in(armv7m, 10)); @@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, qdev_get_gpio_in_named(armv7m, "NMI", 0)); -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIU-0002WF-As for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIG-0002JC-Mb for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:56 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:52018) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005qJ-0e for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:54 -0500 Received: by mail-wm1-x331.google.com with SMTP id m2so2404923wmm.1 for ; Thu, 21 Jan 2021 11:06:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z/cipOte9qBYkDz6GvPRQ6o8HFNldLG8VuXdickyLI0=; b=oWQf5mXQjxxvNIvb4Vaxap6AVWNDVlMKT+WWVO2mo9tc1gY0eby3GoYw3X8XfVN74Y nQ6fuO4uAV7UsGcYnXNLQposNWFbqizkA9je55Eq/4hNS0qukhUp7XjGxqP/adIK5yhQ 4zYpvbQ1jPkqV73THeoIkWrMVM6O0ab7hADHX8zeHgZrFHCtZqQ83np4KlnpvEthekil IZ5P3/xlhHZN2WxKhJQCs0Veh7dgu1HLg4SNq0U4Iy9WTYNl1CSxnEACe0HFGTNHSG5O 1H+mp0Mj5e6T5Wg5h0fpJv7D5pUuNyUhRU1TRrs0MSNv3LWbZsL0toT4/0acnWtY7r/l Pypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z/cipOte9qBYkDz6GvPRQ6o8HFNldLG8VuXdickyLI0=; b=djDEnfG7pHEvCUBMcOkKFOzZ5wZ3cMVr55M8+KBaQn1u4f6mKJxmxVWYxmEskxkCia 8qc70Xw2kjcNxwII1CkMb9osvq6kEQ5CAgvZyjTBtf7wcAMsnc8het2ISZqYypzlwE59 yXp53oNvKBrtEenuuolGPbtACJAPG4SYRhWKmbiovRraAgafGIoWdAujBupcwswd/TPS P6wOXGUZ2gFV96pFlonvBso52RccPzFscUAVzQ3DRmzAdTR2uX2Bn6uMwv4T80m/dJcS SmLsm3y9sOKZeqjzjmfLZUCYO0vsr1Gl5BBAkyWRS6rOt5dy+UXngCRn+mvzFDyDwGe/ 3SCw== X-Gm-Message-State: AOAM530XoDjYldbkKpY+2kRhRFTy1DRZkZKOqwk+McKbvHC9wJ0CctUr 0Cj4QHsq92IkIZeR0/KOFD6sg97bVZLI3Q== X-Google-Smtp-Source: ABdhPJz3akt48jtK3aT1obs1Uz17ludihQAskpWYXUKtsAqAHJ+DXwhQ/gJK45l+rKifRVgTBvlKxw== X-Received: by 2002:a1c:de09:: with SMTP id v9mr790569wmg.0.1611255998800; Thu, 21 Jan 2021 11:06:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Date: Thu, 21 Jan 2021 19:06:11 +0000 Message-Id: <20210121190622.22000-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:57 -0000 Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6a9eed9022a..7acdf490f28 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -62,6 +62,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/core/split-irq.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MPS2TZ_NUMIRQ 92 @@ -100,6 +101,8 @@ struct MPS2TZMachineState { qemu_or_irq uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 20000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. @@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* These clocks don't need migration because they are fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, mmc->armsse_type); iotkitdev = DEVICE(&mms->iotkit); @@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine) OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIU-0002Wr-Gj for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIG-0002Jf-Pc for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:56 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005n9-1o for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:06:56 -0500 Received: by mail-wr1-x42f.google.com with SMTP id a12so2816276wrv.8 for ; Thu, 21 Jan 2021 11:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jof7Fo3+SWgxMSAxHIHQk0SnRA/MK6xgKMN5PCrEdn4=; b=PEMWggmtPQvZUQmsl2AhjBvXnR7M7NGjsP2U0Hv96ihz0G0p6si77+eAoImqx6xvXg M7w9OG4Fs31uyDWbexjSX/mBVrrAFA9hSMEuGPzdWVUsT2/IB4aMGVJ5aHkDZPCpFBFL 35DehO7LQbdBMJTU1WU9Mc1ipnOJaz3cEnl4wmyk2yZlz3PouUG+ogeb5p5arM/irKmE RsQ9zid23b1HmwlMguRMoVG5Ks4MmTqGiyXcYXtXzwS+9fbgPQr5Nldziieq2joJpT97 gJJHc9v2IDJ8X96vwutfqWjYf3ZF6/zsEVfBX244sVB7G1WSyslt/guwKKKUmcTQQE/y wP0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jof7Fo3+SWgxMSAxHIHQk0SnRA/MK6xgKMN5PCrEdn4=; b=TFBIMAVzAkF6eLv41gWyih3LYxLtubuuTp84g/oQ2ZJLKJKSLK/yxScTM7a7QuncPf NCKkXXo8xBqLygRPazXUF0cH3jUMJGIuSfcrHBN9bFzgjNkb+kMwC/PMvmL4V+9leZ9b G2Hs7eoYW+kq35/B2Wq9G7ExvYVbT+CkTjirPi4b+rAz4G1JBYMiy1VE2fJTzn5nLvOb mJohs3X8eobLocggEfaTvGPKlR/ffDsfwI+o1htEU0mrcb28wz/KfatLa9gGkzJzh5RY dVSTGuCA6DfVfmRXpE0qWfTWs5cvMZ4lESGmg4ZcOkmvRudFJAWENh17SLig2zcB7Xdd c71Q== X-Gm-Message-State: AOAM5300Sh0SCUyV0zGi1VNTt4kIBjYqayJh7b6asOipKBSCVlznXpbX NneMSMWOoE11224QeMLTCycg1tlI1P1aeA== X-Google-Smtp-Source: ABdhPJwnkjBMykUyy9sp94kP/fpkHLzP/Ue9TZSrCdY/Nnf62seQCYwGyljPPBSUdRNFcvhMHOXGyg== X-Received: by 2002:adf:d20b:: with SMTP id j11mr889515wrh.318.1611255991376; Thu, 21 Jan 2021 11:06:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Date: Thu, 21 Jan 2021 19:06:03 +0000 Message-Id: <20210121190622.22000-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:06:59 -0000 The state struct for the CMSDK APB timer device doesn't follow our usual naming convention of camelcase -- "CMSDK" and "APB" are both acronyms, but "TIMER" is not so should not be all-uppercase. Globally rename the struct to "CMSDKAPBTimer" (bringing it into line with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains as-is because "UART" is an acronym). Commit created with: perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 6 +++--- include/hw/timer/cmsdk-apb-timer.h | 4 ++-- hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++-------------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 77f86771c30..83f5e28c16e 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -153,9 +153,9 @@ struct ARMSSE { TZPPC apb_ppc0; TZPPC apb_ppc1; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTIMER timer0; - CMSDKAPBTIMER timer1; - CMSDKAPBTIMER s32ktimer; + CMSDKAPBTimer timer0; + CMSDKAPBTimer timer1; + CMSDKAPBTimer s32ktimer; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 0d80b2a48cd..baa009bb2da 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -18,9 +18,9 @@ #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" -OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER) +OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) -struct CMSDKAPBTIMER { +struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f85f1309f37..ae9c5422540 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -67,14 +67,14 @@ static const int timer_id[] = { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; -static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) +static void cmsdk_apb_timer_update(CMSDKAPBTimer *s) { qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); } static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); uint64_t r; switch (offset) { @@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); trace_cmsdk_apb_timer_write(offset, value, size); @@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = { static void cmsdk_apb_timer_tick(void *opaque) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); if (s->ctrl & R_CTRL_IRQEN_MASK) { s->intstatus |= R_INTSTATUS_IRQ_MASK; @@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque) static void cmsdk_apb_timer_reset(DeviceState *dev) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); trace_cmsdk_apb_timer_reset(); s->ctrl = 0; @@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj); memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, s, "cmsdk-apb-timer", 0x1000); @@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj) static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); if (s->pclk_frq == 0) { error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); @@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_PTIMER(timer, CMSDKAPBTIMER), - VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), - VMSTATE_UINT32(value, CMSDKAPBTIMER), - VMSTATE_UINT32(reload, CMSDKAPBTIMER), - VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), + VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_UINT32(ctrl, CMSDKAPBTimer), + VMSTATE_UINT32(value, CMSDKAPBTimer), + VMSTATE_UINT32(reload, CMSDKAPBTimer), + VMSTATE_UINT32(intstatus, CMSDKAPBTimer), VMSTATE_END_OF_LIST() } }; static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), + DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo cmsdk_apb_timer_info = { .name = TYPE_CMSDK_APB_TIMER, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(CMSDKAPBTIMER), + .instance_size = sizeof(CMSDKAPBTimer), .instance_init = cmsdk_apb_timer_init, .class_init = cmsdk_apb_timer_class_init, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks Date: Thu, 21 Jan 2021 19:06:12 +0000 Message-Id: <20210121190622.22000-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:05 -0000 Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell --- hw/arm/musca.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index d82bef11cf2..a9292482a06 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -33,6 +33,7 @@ #include "hw/misc/tz-ppc.h" #include "hw/misc/unimp.h" #include "hw/rtc/pl031.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MUSCA_NUMIRQ_MAX 96 @@ -82,6 +83,8 @@ struct MuscaMachineState { UnimplementedDeviceState sdio; UnimplementedDeviceState gpio; UnimplementedDeviceState cryptoisland; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MUSCA_MACHINE "musca" @@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) * don't model that in our SSE-200 model yet. */ #define SYSCLK_FRQ 40000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) { @@ -367,6 +372,11 @@ static void musca_init(MachineState *machine) exit(1); } + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, TYPE_SSE200); ssedev = DEVICE(&mms->sse); @@ -376,6 +386,8 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIW-0002d1-QF for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIS-0002VS-UH for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0005t4-8f for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:08 -0500 Received: by mail-wm1-x336.google.com with SMTP id i63so2398534wma.4 for ; Thu, 21 Jan 2021 11:06:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MnpjFP3ps33JvLWa6qS6ae0tBST2dCJ7w+wCFqGW/AY=; b=Wag0SSdrcMiEPLYPyl0mMDvSadxhITLWfdxIl9cR+2zvXqIpILOD8BOY98hXMZ1Dw3 uUb94vRzzld8HaF+DlY/PmHlLlKaP0Mem7gL+uqYDQqK3U+Qdux8c5ik3LGuFoMTpNgQ We+UGJz+57cvimuqwrZ7jG6zTokQpD/LgQya6c4F/VoaQSqrDvS5FQaJgnFjXGXwz/rz 0ch4G6dMERxGVy/27PsCfiPQoyQVCGDzsjp36O4Xz+OI8Qsc2K9iAhSkm0sf+xcHu2iq TctxS2tTssFoIDubJT/C6MG3ZiuBwJ020AgRoBjiqQi9vdmM/kpyPtumiqVLr7AVYtn3 9ZAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MnpjFP3ps33JvLWa6qS6ae0tBST2dCJ7w+wCFqGW/AY=; b=GIpDD4H9dwHNcntmtQMF4aBdGT4ANASq+GRkuFB0uI3drJGJFZ34hGPxqNeQ1D0DG4 pKcHPPEZD5bqj0lkk+CsxnqodkuUhvmYCz5XY+TqGygyQRhvwSNUvfrcjEMCK+yxCKpw SuCHACIxflHeNuo/c8fKOnWME7Bqlk8EHePqjfT5tfTPFfrjFBrdmDq5d09FgUyw4qza BFeCW+WOX4i2R/6WRrnv0Jfpc1RFLFxKsJ/ZfNDgLQGw/wC0vMAfTdgsKKb/2EE9GwRl MTv25fo9ElQgk0T4b8oYrdOM6rNqJ27Q9jhINOzNjeppUI0CdStj/TiQH3IR5IUQ8oEA MvSw== X-Gm-Message-State: AOAM531wjx0rHHCponqiw3N81hNQD+Jl3tTv4+2bVmf0RxpoFrNOspmb ZE5uvlpsFLluNebg1E6XvYwgsets6yLDRw== X-Google-Smtp-Source: ABdhPJybOZfUpn6fV8h5i8R9s5zL/Trxcw1Dq09oFOM2MQRQRFhsGbqOxNIPb3KkHviy/dmOUmVCVQ== X-Received: by 2002:a1c:cb:: with SMTP id 194mr779126wma.30.1611256001728; Thu, 21 Jan 2021 11:06:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Date: Thu, 21 Jan 2021 19:06:14 +0000 Message-Id: <20210121190622.22000-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:09 -0000 Create and connect the Clock input for the watchdog device on the Stellaris boards. Because the Stellaris boards model the ability to change the clock rate by programming PLL registers, we have to create an output Clock on the ssys_state device and wire it up to the watchdog. Note that the old comment on ssys_calculate_system_clock() got the units wrong -- system_clock_scale is in nanoseconds, not milliseconds. Improve the commentary to clarify how we are calculating the period. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 0194ede2fe0..9b67c739ef2 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -26,6 +26,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "cpu.h" #include "qom/object.h" @@ -377,6 +378,7 @@ struct ssys_state { uint32_t clkvclr; uint32_t ldoarst; qemu_irq irq; + Clock *sysclk; /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; @@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s) } /* - * Caculate the sys. clock period in ms. + * Calculate the system clock period. We only want to propagate + * this change to the rest of the system if we're not being called + * from migration post-load. */ -static void ssys_calculate_system_clock(ssys_state *s) +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) { + /* + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input + * clock is 200MHz, which is a period of 5 ns. Dividing the clock + * frequency by X is the same as multiplying the period by X. + */ if (ssys_use_rcc2(s)) { system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); } else { system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); } + clock_set_ns(s->sysclk, system_clock_scale); + if (propagate_clock) { + clock_propagate(s->sysclk); + } } static void ssys_write(void *opaque, hwaddr offset, @@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x070: /* RCC2 */ if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { @@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc2 = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x100: /* RCGC0 */ s->rcgc[0] = value; @@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj) { ssys_state *s = STELLARIS_SYS(obj); - ssys_calculate_system_clock(s); + /* OK to propagate clocks from the hold phase */ + ssys_calculate_system_clock(s, true); } static void stellaris_sys_reset_exit(Object *obj) @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, false); return 0; } @@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = { VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), VMSTATE_UINT32(clkvclr, ssys_state), VMSTATE_UINT32(ldoarst, ssys_state), + /* No field for sysclk -- handled in post-load instead */ VMSTATE_END_OF_LIST() } }; @@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj) memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); } -static int stellaris_sys_init(uint32_t base, qemu_irq irq, - stellaris_board_info * board, - uint8_t *macaddr) +static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, + stellaris_board_info *board, + uint8_t *macaddr) { DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, */ device_cold_reset(dev); - return 0; + return dev; } /* I2C controller. */ @@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) int flash_size; I2CBus *i2c; DeviceState *dev; + DeviceState *ssys_dev; int i; int j; @@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), - board, nd_table[0].macaddr.a); + ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), + board, nd_table[0].macaddr.a); if (board->dc1 & (1 << 3)) { /* watchdog present */ @@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* system_clock_scale is valid now */ uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); + qdev_connect_clock_in(dev, "WDOGCLK", + qdev_get_clock_out(ssys_dev, "SYSCLK")); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIX-0002dk-1u for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIU-0002WG-AR for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:36981) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0005uU-W2 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: by mail-wm1-x32c.google.com with SMTP id c128so2437800wme.2 for ; Thu, 21 Jan 2021 11:06:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:15 +0000 Message-Id: <20210121190622.22000-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:10 -0000 Switch the CMSDK APB timer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell --- hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c63145ff553..f053146d88f 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_timer_clk_update(void *opaque) +{ + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", + cmsdk_apb_timer_clk_update, s); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->pclk)) { + error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); return; } @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->pclk_frq); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); ptimer_transaction_commit(s->timer); } -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIX-0002eg-CS for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIN-0002PF-IJ for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005oK-2b for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: by mail-wr1-x431.google.com with SMTP id c12so2815966wrc.7 for ; Thu, 21 Jan 2021 11:06:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0rKrl7iJBderO7McLU9xdXqR32edl/U7+oETLREFgpc=; b=o5xVGYj6fJqYPGJqArDxdJUlPmUJ6v3eebK0MQPMjvr5Mq1HJ/phxgK3X11dcErZDc nIklC5LhCi7P8IeWH8JoxCJz1dJ0r0e+tT3YA3zkr15HbUKNyVwc33WvI+D73cFEvLH5 4+SdU2CFDMCTtw0FMGw+hqqSdUvzkiGR6TzOr5RnSQQ2h8YyChyFM0K1I9/okg+88jn4 tPo9v+u14kTXVc0Ur31wPHr/6UQmhkSqyJPWy0Hs3+0unVr/xPgeMAaODONR6Rpb9u33 5I0t14ZtLGyO9ca+rOEfi/lTzMh09F3csoxmoTgFnrbW31iKRvwFWrcUewAxOUvmOu8A xVoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0rKrl7iJBderO7McLU9xdXqR32edl/U7+oETLREFgpc=; b=Q38cBr0mpYSGM1moxX0qyQOkVsC8XENqXGn+g9taZRn9Fx+4p445Rx5tJEjTJqIhn8 0rxLy/inhS4fREiRLot6ADqfdrQNph6Qd3WpMOuwkkkAfP0MzuvfpsEbuY0nyirLI9Cw 2PTDtVvtYvM61QTukYxtn6XOb7HwHwNZfJFlDHDCPKG4VfRMf/omJLjKFW3rP6zs6iDC wr8eSuEOOcMiNvwwK+zJVhOi7/kjjPu1MlPSvlyqAUi1nos7RSvn3aT0ETYcE180aVsb NLSq37J54S8wb0YLdHAva3WNl0o9WIvamK4MdeIX4llV1ia/TZU6GKp0wRMYrkwlLYvT oONg== X-Gm-Message-State: AOAM53123qurgQvELVyxXjjaQjiax2Pum4ewKYXK2j0sXJBaKod1Y9HG ueIBMEuEQav7/UkIkK54ZF/ZuqWJwnoM3Q== X-Google-Smtp-Source: ABdhPJxlG6Vd9vpqtzsXEBmbnSaJS/I58lwnGyTXDabkF47dh2Y4VWcC3veHQHWGJyDv1wz39H0PMA== X-Received: by 2002:a5d:4ccb:: with SMTP id c11mr872864wrt.324.1611255993206; Thu, 21 Jan 2021 11:06:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input Date: Thu, 21 Jan 2021 19:06:05 +0000 Message-Id: <20210121190622.22000-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:03 -0000 As the first step in converting the CMSDK_APB_DUALTIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. We take the opportunity to correct the name of the clock input to match the hardware -- the dual timer names the clock which drives the timers TIMCLK. (It does also have a 'pclk' input, which is used only for the register and APB bus logic; on the SSE-200 these clocks are both connected together.) This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++ hw/timer/cmsdk-apb-dualtimer.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 08d9e6fa3d5..3adbb01dd34 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC * + sysbus IRO 1: timer block 1 interrupt TIMINT1 @@ -28,6 +29,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer" @@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer { MemoryRegion iomem; qemu_irq timerintc; uint32_t pclk_frq; + Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; uint32_t timeritcr; diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index f6534241b94..781b496037b 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "migration/vmstate.h" @@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = { static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { .name = "cmsdk-apb-dualtimer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer), VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER_NUM_MODULES, 1, cmsdk_dualtimermod_vmstate, -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIZ-0002jL-6p for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIV-0002aX-L3 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:11 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:40584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI5-0005uo-6W for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:11 -0500 Received: by mail-wm1-x329.google.com with SMTP id c127so2435418wmf.5 for ; Thu, 21 Jan 2021 11:06:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l+C2gTVos115dMvtdyIN+AXfuTec5f/EcGemGRxkJo4=; b=vadlG+WXak4otfF4yCJv1/Wzh3To5b4qBkBVhGiDSjUUjQPxo26gOMK5vZlnQx1+Lt ygQahyaanc9Lpp9w0bzOZlY72EhPksbX0QihXx56BkbSIr69F4lcu4spWMqzuvz56DT9 dOEK44cS008YLgKf/yyToiZNtUw94biV3bhXiLmXjPrwKclFrWD1t2KDG5zuRVcEUzdP /w+J54TtldYuFV+eC0px/EzWGKLxAka/iSLL3uvbO0Dw7vozAxbc9SZoeaQXZkfTZxp0 KCfzfd4fL9ZKo4r9SCl8w72KpDVqexQTLej5NbLlVzrm0miJ2eUpqmEb7xXSk83hsGI0 jdVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l+C2gTVos115dMvtdyIN+AXfuTec5f/EcGemGRxkJo4=; b=iCMmgxxaFfQuUc2B8GVIsDO0Np/lFFTF0U439wAlOV4n/IsHOqbdDFilbcMVOYbQAk ijoPBew+IzTYpS+Miufq8DarxNYhiRu8hCp1K7tOeVEV2l21byzIs9LAD715b2Li/gQy keRFHPfSUBcufs75n1gtUub8jhv7UeAQ1Tfnv+O2OGDnm5h4qBzZbNGrEV3QJzfmklN6 /QAdDoCYwHeXBb0LtN+Z9pyHHewlVTngVsq907tozBzef5CvtS5cXdfcdPiRSD8ig54m LavNpEDB8v2ujV6ruxI+Kx4tl/RhgJ2FLDrjTrmqTtBdGEFkCgaV4o+5nrsfIaPHiroc givw== X-Gm-Message-State: AOAM53337ntOF4rRhWZCFuyZaYz34yyPar3km02+X5EHcNG1sDoH4IBP wYOyibSyptq0ND+FDrs12uhqgt0PLHmCaA== X-Google-Smtp-Source: ABdhPJyK8BwPSgUR5vPlUddZ/7vtlYLLnQIYDqXqDtm8ylLI7NhNZcrjAxsukr+geINN9p4FR+wlcA== X-Received: by 2002:a1c:9609:: with SMTP id y9mr703365wmd.75.1611256003595; Thu, 21 Jan 2021 11:06:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:16 +0000 Message-Id: <20210121190622.22000-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:12 -0000 Switch the CMSDK APB dualtimer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell --- hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 781b496037b..828127b366f 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) qemu_set_irq(s->timerintc, timintc); } +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) +{ + /* Return the divisor set by the current CONTROL.PRESCALE value */ + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { + case 0: + return 1; + case 1: + return 16; + case 2: + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ + return 256; + default: + g_assert_not_reached(); + } +} + static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, uint32_t newctrl) { @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, default: g_assert_not_reached(); } - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); } if (changed & R_CONTROL_MODE_MASK) { @@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) * limit must both be set to 0xffff, so we wrap at 16 bits. */ ptimer_set_limit(m->timer, 0xffff, 1); - ptimer_set_freq(m->timer, m->parent->pclk_frq); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); ptimer_transaction_commit(m->timer); } @@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) s->timeritop = 0; } +static void cmsdk_apb_dualtimer_clk_update(void *opaque) +{ + CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque); + int i; + + for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { + CMSDKAPBDualTimerModule *m = &s->timermod[i]; + ptimer_transaction_begin(m->timer); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); + ptimer_transaction_commit(m->timer); + } +} + static void cmsdk_apb_dualtimer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } - s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", + cmsdk_apb_dualtimer_clk_update, s); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev); int i; - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->timclk)) { + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected"); return; } -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIa-0002mp-Ei for mharc-qemu-arm@gnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Date: Thu, 21 Jan 2021 19:06:13 +0000 Message-Id: <20210121190622.22000-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:06 -0000 Convert the SSYS code in the Stellaris boards (which encapsulates the system registers) to a proper QOM device. This will provide us with somewhere to put the output Clock whose frequency depends on the setting of the PLL configuration registers. This is a migration compatibility break for lm3s811evb, lm3s6965evb. We use 3-phase reset here because the Clock will need to propagate its value in the hold phase. For the moment we reset the device during the board creation so that the system_clock_scale global gets set; this will be removed in a subsequent commit. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 107 insertions(+), 25 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 652823195b1..0194ede2fe0 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp) /* System controller. */ -typedef struct { +#define TYPE_STELLARIS_SYS "stellaris-sys" +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) + +struct ssys_state { + SysBusDevice parent_obj; + MemoryRegion iomem; uint32_t pborctl; uint32_t ldopctl; @@ -371,11 +376,18 @@ typedef struct { uint32_t dcgc[3]; uint32_t clkvclr; uint32_t ldoarst; + qemu_irq irq; + /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; - qemu_irq irq; - stellaris_board_info *board; -} ssys_state; + uint32_t did0; + uint32_t did1; + uint32_t dc0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; +}; static void ssys_update(ssys_state *s) { @@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = { static int ssys_board_class(const ssys_state *s) { - uint32_t did0 = s->board->did0; + uint32_t did0 = s->did0; switch (did0 & DID0_VER_MASK) { case DID0_VER_0: return DID0_CLASS_SANDSTORM; @@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset, switch (offset) { case 0x000: /* DID0 */ - return s->board->did0; + return s->did0; case 0x004: /* DID1 */ - return s->board->did1; + return s->did1; case 0x008: /* DC0 */ - return s->board->dc0; + return s->dc0; case 0x010: /* DC1 */ - return s->board->dc1; + return s->dc1; case 0x014: /* DC2 */ - return s->board->dc2; + return s->dc2; case 0x018: /* DC3 */ - return s->board->dc3; + return s->dc3; case 0x01c: /* DC4 */ - return s->board->dc4; + return s->dc4; case 0x030: /* PBORCTL */ return s->pborctl; case 0x034: /* LDOPCTL */ @@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void ssys_reset(void *opaque) +static void stellaris_sys_reset_enter(Object *obj, ResetType type) { - ssys_state *s = (ssys_state *)opaque; + ssys_state *s = STELLARIS_SYS(obj); s->pborctl = 0x7ffd; s->rcc = 0x078e3ac0; @@ -661,9 +673,19 @@ static void ssys_reset(void *opaque) s->rcgc[0] = 1; s->scgc[0] = 1; s->dcgc[0] = 1; +} + +static void stellaris_sys_reset_hold(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + ssys_calculate_system_clock(s); } +static void stellaris_sys_reset_exit(Object *obj) +{ +} + static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; @@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = { } }; +static Property stellaris_sys_properties[] = { + DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), + DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), + DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), + DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), + DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), + DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), + DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), + DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), + DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void stellaris_sys_instance_init(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(s); + + memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + static int stellaris_sys_init(uint32_t base, qemu_irq irq, stellaris_board_info * board, uint8_t *macaddr) { - ssys_state *s; + DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - s = g_new0(ssys_state, 1); - s->irq = irq; - s->board = board; /* Most devices come preprogrammed with a MAC address in the user data. */ - s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); - s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); + qdev_prop_set_uint32(dev, "user0", + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); + qdev_prop_set_uint32(dev, "user1", + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); + qdev_prop_set_uint32(dev, "did0", board->did0); + qdev_prop_set_uint32(dev, "did1", board->did1); + qdev_prop_set_uint32(dev, "dc0", board->dc0); + qdev_prop_set_uint32(dev, "dc1", board->dc1); + qdev_prop_set_uint32(dev, "dc2", board->dc2); + qdev_prop_set_uint32(dev, "dc3", board->dc3); + qdev_prop_set_uint32(dev, "dc4", board->dc4); + + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, irq); + + /* + * Normally we should not be resetting devices like this during + * board creation. For the moment we need to do so, because + * system_clock_scale will only get set when the STELLARIS_SYS + * device is reset, and we need its initial value to pass to + * the watchdog device. This hack can be removed once the + * watchdog has been converted to use a Clock input instead. + */ + device_cold_reset(dev); - memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); - memory_region_add_subregion(get_system_memory(), base, &s->iomem); - ssys_reset(s); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s); return 0; } - /* I2C controller. */ #define TYPE_STELLARIS_I2C "stellaris-i2c" @@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = { .class_init = stellaris_adc_class_init, }; +static void stellaris_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->vmsd = &vmstate_stellaris_sys; + rc->phases.enter = stellaris_sys_reset_enter; + rc->phases.hold = stellaris_sys_reset_hold; + rc->phases.exit = stellaris_sys_reset_exit; + device_class_set_props(dc, stellaris_sys_properties); +} + +static const TypeInfo stellaris_sys_info = { + .name = TYPE_STELLARIS_SYS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ssys_state), + .instance_init = stellaris_sys_instance_init, + .class_init = stellaris_sys_class_init, +}; + static void stellaris_register_types(void) { type_register_static(&stellaris_i2c_info); type_register_static(&stellaris_gptm_info); type_register_static(&stellaris_adc_info); + type_register_static(&stellaris_sys_info); } type_init(stellaris_register_types) -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIb-0002oy-5V for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIV-0002a6-Hl for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:11 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:36985) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI7-0005v8-31 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:11 -0500 Received: by mail-wm1-x330.google.com with SMTP id c128so2437886wme.2 for ; Thu, 21 Jan 2021 11:06:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uDxVLnL9xv9QeWzNKaXg1U1KaegZzyNUwA1UoAWaXas=; b=XZhC+Xrx9Ww1AlqhNOlETwxevwiCnjLdAIp1pjcgbcGVsD92fuKCGyiUz3TBe92YZn sTog1D1Fay1tTvbP2YBT31aqr/rnKy+OjqLty4wKss8KagBRAvNarGbCpBCC3CwFz6sL 26pWQBVzXQcWXn9wwDDuMQctqKac76px5OglnGulWMUSej2YwQrr4p/dumOgY+8zSmVy Bq2uNk1pyzuT81BHRHC9H2DoWlMk/8irKrT+i8i4GwP0amtV0/UdN7qyFEAw30Y9ZhRt +rYPAXvW6gXz/PWLFnCHnfVLuvv4rfWkutr1sIJ+lH9nooNEJo6+vtjeVRJDK+GrY0pE sSUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uDxVLnL9xv9QeWzNKaXg1U1KaegZzyNUwA1UoAWaXas=; b=bu03OLD28K7v+77evAMf3SP5+3di3QUXAgHicKSnaKIEigCbr55/EWP+kCB9Nuz5k+ w9oTyBrGpRNz+ou/QZu7HUZVXnz8rARA1bYMu1m1J4S/vXPuhgw92JeT43pBIXI41bgP ekiaciqAxxfHx12IVWlWyiSzNhSoyBBIvOrTBF9Yi3g/FTe5qPsQMrRChkPdxI+CUB2V /5qjroPWGljQqMM0DpipWk9hw3K3cyA5Mg2WhIRGuIwogyhcZiiNyg4PpIP75FDpoE70 iWpvrD15ELWqiN/vSvzgzlQCvTt2LnJg7ygTTyIhV3tEsIK88OhTSE6JjijXOLBti7Ht ho4A== X-Gm-Message-State: AOAM530xyrH34kk3OzHKqMc+/6v3Nlj6s/Zr7DtPgr4QcYPAOnKv6UTN E3kK5JhzkJ5SE8+aHhChI18s9UZb4LS3AA== X-Google-Smtp-Source: ABdhPJyPVYG14xA0tYXYc4qeZamF5KlHQKDgB/GyQh0CEN1NJ8PLkIwtISAgBUWcj437lMYri433JQ== X-Received: by 2002:a1c:9cc5:: with SMTP id f188mr674223wme.171.1611256004490; Thu, 21 Jan 2021 11:06:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:17 +0000 Message-Id: <20210121190622.22000-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:11 -0000 Switch the CMSDK APB watchdog device over to using its Clock input; the wdogclk_frq property is now ignored. Signed-off-by: Peter Maydell --- hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index b03bcb73628..9cad0c67da4 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_watchdog_clk_update(void *opaque) +{ + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_watchdog_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); - s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", + cmsdk_apb_watchdog_clk_update, s); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) { CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); - if (s->wdogclk_frq == 0) { + if (!clock_has_source(s->wdogclk)) { error_setg(errp, - "CMSDK APB watchdog: wdogclk-frq property must be set"); + "CMSDK APB watchdog: WDOGCLK clock must be connected"); return; } @@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->wdogclk_frq); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); ptimer_transaction_commit(s->timer); } -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIb-0002pb-Bx for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIW-0002cb-JR for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:12 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35045) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI7-0005wg-2T for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:12 -0500 Received: by mail-wr1-x42d.google.com with SMTP id l12so2831617wry.2 for ; Thu, 21 Jan 2021 11:06:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=drkjv5Dr4fNxDyNRqjV5mGa+nW4Kje9Rbck6xlQDEzo=; b=YHf0cUWqP75ModYpAPc8KsC8hT4kMqRKyGlWW9/za7CxJLWzpPZWtgsmH4nraxh6l7 cSEJv6v/joGmXITlKI6RKW92Mpxko0Jrmipncc9MX2UcEJFF5rN1rz4sCdr5mlnW1OuL 8w3FBu7AMx42+MV4315utqfjdZk20tulI7QsZGAwGfNwtmIgrLjQ5gTrepqwTY5jfaMS 3M6/7PruEd8btc1aNZuM2f0SYAUSpJEa0m1eCfCMigRwc6uvFpccNSEBmGsu25en1A6Q 7dYicb01BEBDeQMGMEb1C0vXNoBatu4jcCWpaapo2w4oBMWEarlQTsuMLeB7rMmee5YS bEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=drkjv5Dr4fNxDyNRqjV5mGa+nW4Kje9Rbck6xlQDEzo=; b=pG6asjoUuzAJQXyy3DxNEemc7fU4h4PkRgpY1gb7Lk9LSxRgTNj29BfxzK4DmmBXrm zIRMaxGuo7TOXeuahVTYHrs3Q9UIaaiD++lA6vMF6eFf/uDXMy0GtwzgKGP+fjdAX0Tr 3AcWcD+arpHUIiuM5DFb+RoldVWD8jyvUv+95LpuKpKsbiCEJ7WEN7KCyLENF9AegQ7N GLYUQtVOb94EHJY41lVsQlBUfWQl/J1+iEdBR/eSe7SRjjjfg1ItVnNA5aNuUzhsYnOk OhSceWonS9qOdZD7oQpAXNWtx8m/0Q/k10Xwgu/bqPr3k5CRyuaETHSoIPDhrxxqW7nM VTiA== X-Gm-Message-State: AOAM532K3EedxvcIqwuqzf2hcPQIDU52myLMtVHq369xrYA3tLc9YOzW RnAyGzKJG291awPbo3gDt9yJf+/RipG9kg== X-Google-Smtp-Source: ABdhPJxN2ScO4ZhhqNnJ0dhyxsakpBE11cXKA/UCwVX84Drb+XB55pEsNlTXjXc3/4u3f9pIdtrVCA== X-Received: by 2002:adf:dc89:: with SMTP id r9mr933062wrj.52.1611256005478; Thu, 21 Jan 2021 11:06:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Date: Thu, 21 Jan 2021 19:06:18 +0000 Message-Id: <20210121190622.22000-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:13 -0000 Now that the CMSDK APB watchdog uses its Clock input, it will correctly respond when the system clock frequency is changed using the RCC register on in the Stellaris board system registers. Test that when the RCC register is written it causes the watchdog timer to change speed. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c index c6add1fee85..9a4873a8314 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -15,6 +15,7 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "libqtest-single.h" /* @@ -31,6 +32,11 @@ #define WDOGMIS 0x14 #define WDOGLOCK 0xc00 +#define SSYS_BASE 0x400fe000 +#define RCC 0x60 +#define SYSDIV_SHIFT 23 +#define SYSDIV_LENGTH 4 + static void test_watchdog(void) { g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); @@ -61,6 +67,50 @@ static void test_watchdog(void) g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); } +static void test_clock_change(void) +{ + uint32_t rcc; + + /* + * Test that writing to the stellaris board's RCC register to + * change the system clock frequency causes the watchdog + * to change the speed it counts at. + */ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(80 * 500 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */ + rcc = readl(SSYS_BASE + RCC); + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); + writel(SSYS_BASE + RCC, rcc); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(41); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + int main(int argc, char **argv) { QTestState *s; @@ -71,6 +121,8 @@ int main(int argc, char **argv) s = qtest_start("-machine lm3s811evb"); qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", + test_clock_change); r = g_test_run(); -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIf-0002tY-Hr for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIZ-0002kc-K4 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:15 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:32892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI8-0005wx-Ml for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:15 -0500 Received: by mail-wr1-x42b.google.com with SMTP id 7so2831654wrz.0 for ; Thu, 21 Jan 2021 11:06:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o6QQiJy5R4qmIV1z0aGnCLcQYm3mM8qRJ5jTAs1T+H8=; b=ZIts7p2SirGlVpgj+pmUABXAwdDoIRnny+XuuK8dCw7Oj7KL/umjn2C7T/UKu+qgal ZT2o4cpO0L55LtHBgOxX5qkFLrEd9/bJjkOzUzvZIuPv1CbN6LelHBLwX+gfOPaOsWCu YfI8Thho5dRD3GM24zPrJVh0At82R4bstvG2zvnDBCc4KiE8MMa8Uvr0G5fezNagRa2v 4ddl4ooHQX6PlVt3GdSobGFUd0xQZEPcAaSYsq7N4owfe2glYhCvGf7WAs+1meSTF0pW IpJxs8Zho3c3ZM00PARP1LVjxSoJpSetBhHye5ELdEFbUq/XjbPYAOhCnfInSL9CLT2V V7yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o6QQiJy5R4qmIV1z0aGnCLcQYm3mM8qRJ5jTAs1T+H8=; b=t6e0Pj6jp8o12SKKvXuQ0rQuulSTEBCwyfDwgi+5ESHJko+14m0KK3Psg/4mQzFykI ig+ZolxmP3LuHSGRScU6i3Xd0sIcHAMucW+Dn+HPB6kJM1Lj/VprE8NlzHckDvbI7QC1 Y9oR6stxPGHSR5iTAhPiX14fIFG4i29XgRsFCnqWoPPqO7pXVXb9Xr9mcI7mJ2mZ7Vh5 ZiGMWzSP+NaTt2jkn7GdkO9e6HThVlR307WVyu2JKqlV7lIjWZxw5EUGLeOQNLVPOGu5 ZUn9y7K8zElNUy7OZiDBkg7nBdmGgtx5iMWVOZnIlhH8yQkDB/B3eM1m9LXmVN+0CwvR yDTQ== X-Gm-Message-State: AOAM530bEEHhs8qrIxhGHF6jEUk/Vas2tWGxuDDB2LRuF8gAJ2jpDFKj CTEW6ier7lYbpXS8kSOVJF4wZ0r+mMGoig== X-Google-Smtp-Source: ABdhPJxOZyH1FrB5HFrUtW87qkTcOr49W8I81GLHxRqJf+kxWJgPXNpehcEBp28Mv7dh2xACmaPn3g== X-Received: by 2002:a5d:6204:: with SMTP id y4mr941451wru.48.1611256006367; Thu, 21 Jan 2021 11:06:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Date: Thu, 21 Jan 2021 19:06:19 +0000 Message-Id: <20210121190622.22000-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:16 -0000 Use the MAINCLK Clock input to set the system_clock_scale variable rather than using the mainclk_frq property. Signed-off-by: Peter Maydell --- At some point we should make the SysTick take a Clock itself so that we can get rid of the system_clock_scale global entirely. (In fact we want two Clocks: one that is the CPU clock and one for the 'external reference clock' whose period is currently hardcoded at 1000ns in systick_scale()...) --- hw/arm/armsse.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4349ce9bfdb..1da0c1be4c7 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } +static void armsse_mainclk_update(void *opaque) +{ + ARMSSE *s = ARM_SSE(opaque); + /* + * Set system_clock_scale from our Clock input; this is what + * controls the tick rate of the CPU SysTick timer. + */ + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); +} + static void armsse_init(Object *obj) { ARMSSE *s = ARM_SSE(obj); @@ -451,9 +461,11 @@ static void armsse_realize(DeviceState *dev, Error **errp) return; } - if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK_FRQ property was not set"); - return; + if (!clock_has_source(s->mainclk)) { + error_setg(errp, "MAINCLK clock was not connected"); + } + if (!clock_has_source(s->s32kclk)) { + error_setg(errp, "S32KCLK clock was not connected"); } assert(info->num_cpus <= SSE_MAX_CPUS); @@ -1115,7 +1127,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; + /* Set initial system_clock_scale from MAINCLK */ + armsse_mainclk_update(s); } static void armsse_idau_check(IDAUInterface *ii, uint32_t address, -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIi-0002va-K7 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIY-0002hj-I8 for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:14 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:33947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI9-0005x4-1S for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:14 -0500 Received: by mail-wr1-x436.google.com with SMTP id g10so2828484wrx.1 for ; Thu, 21 Jan 2021 11:06:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YCoEevXZLQxxQgAERiSPZQlFXrrGQIKv0sEF5uZH6HM=; b=h5Wza61KoGm9iDnKB7703GCM/t5IJ/EW2sCh1Mny+TLUdq8RJBDeH4qn59br2K65oc 3oDNvM3MaQ2kQkxCJI2jFcU3F/e1CxhzU5LA2+wOucxKe3Hshuwm59p2uuVVEDSjts68 z+igabGujM/LKnvm8Q8UTL91x04vVJcs7h66N4F24BNuyPS1gqLtaAkrbXyaom7Vw4M8 I8NGi+oYYhfWdVrx70u7jumAsLiS1ZV8pZcy/8ALqIIvTec0Z7Cf9UHfNbFzllzBdmBX KxmJ6oGD5c/aMgKb+tCNPNTBRaen7omeeA57TAZ/F5Sti4hT7kxYEL2YNDyVZs+WXTxB iM5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YCoEevXZLQxxQgAERiSPZQlFXrrGQIKv0sEF5uZH6HM=; b=PeVMMkKgiF3cv6EQvXZEcF3rwQ3AlD+ZfP4nOCymy13Qq9pSOA3sI6+dUCiBUb/HLQ Ir7SaBuEk86P+vt0VcTvOa9rM9by0qtutupodcHYVVq1hTiL14FQGcH+xgN0E3OAfatk y8S8pSX3igLpG6pHRBlRq2OURpETRCdqJwZbARuXBEp6lQF+D4sZfpDqZY61+Yvm7/tT k37C5pyRTKbgQQ8aQ+Bd6wH70xM9OvVDoD1A7HVhRukzGZ7hmz2TBD+bt2CUXF3Ygt9N OiYqp8DjqPGUR/5GGaEBz8G6UOmGncBGoaQ9EChDOBkvSE3JMWgCWuq5Rf8yrwPVhf5l uGnQ== X-Gm-Message-State: AOAM531hs43HUyEpc4NoRnVbT1sLE++KX0G6VAqyKMBrekGA4qIfIMjr jmkXaRzcDp9LYFo3hs6pFlWtFdtbJtn5vA== X-Google-Smtp-Source: ABdhPJxZ/bqgw7Gz0gqkVXrDy4OLKxXDTLIOkwIXWVxWVGET7fM9bPY/2S52yduM+f8X7o5QxAD6Mw== X-Received: by 2002:adf:d20b:: with SMTP id j11mr890437wrh.318.1611256007320; Thu, 21 Jan 2021 11:06:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 21 Jan 2021 19:06:20 +0000 Message-Id: <20210121190622.22000-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:14 -0000 Remove all the code that sets frequency properties on the CMSDK timer, dualtimer and watchdog devices and on the ARMSSE SoC device: these properties are unused now that the devices rely on their Clock inputs instead. Signed-off-by: Peter Maydell --- hw/arm/armsse.c | 7 ------- hw/arm/mps2-tz.c | 1 - hw/arm/mps2.c | 3 --- hw/arm/musca.c | 1 - hw/arm/stellaris.c | 3 --- 5 files changed, 15 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1da0c1be4c7..7494afc630e 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -726,7 +726,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. */ - qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; @@ -737,7 +736,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; @@ -748,7 +746,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; @@ -907,7 +904,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Devices behind APB PPC1: * 0x4002f000: S32K timer */ - qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; @@ -1001,7 +997,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); - qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; @@ -1012,7 +1007,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ - qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; @@ -1021,7 +1015,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) armsse_get_common_irq_in(s, 1)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); - qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7acdf490f28..90caa914934 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index cd1c215f941..39add416db5 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), name, &mms->timer[i], TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); - qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); @@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); - qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, @@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); - qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a9292482a06..945643c3cd7 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,7 +385,6 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 9b67c739ef2..5acb043a07e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) if (board->dc1 & (1 << 3)) { /* watchdog present */ dev = qdev_new(TYPE_LUMINARY_WATCHDOG); - /* system_clock_scale is valid now */ - uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; - qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); qdev_connect_clock_in(dev, "WDOGCLK", qdev_get_clock_out(ssys_dev, "SYSCLK")); -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIj-0002w2-3v for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIZ-0002kA-Fr for qemu-arm@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 21 Jan 2021 19:06:21 +0000 Message-Id: <20210121190622.22000-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:15 -0000 Now no users are setting the frq properties on the CMSDK timer, dualtimer, watchdog or ARMSSE SoC devices, we can remove the properties and the struct fields that back them. Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 2 -- include/hw/timer/cmsdk-apb-dualtimer.h | 2 -- include/hw/timer/cmsdk-apb-timer.h | 2 -- include/hw/watchdog/cmsdk-apb-watchdog.h | 2 -- hw/arm/armsse.c | 2 -- hw/timer/cmsdk-apb-dualtimer.c | 6 ------ hw/timer/cmsdk-apb-timer.c | 6 ------ hw/watchdog/cmsdk-apb-watchdog.c | 6 ------ 8 files changed, 28 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index bfa1e79c4fe..676cd4f36b0 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -41,7 +41,6 @@ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to @@ -218,7 +217,6 @@ struct ARMSSE { /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; - uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; bool cpu_fpu[SSE_MAX_CPUS]; diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 3adbb01dd34..f3ec86c00b5 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerintc; - uint32_t pclk_frq; Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 54f7ec8c502..c4c7eae8499 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) /* * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "pclk": clock for the timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: timer interrupt TIMERINT @@ -35,7 +34,6 @@ struct CMSDKAPBTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerint; - uint32_t pclk_frq; struct ptimer_state *timer; Clock *pclk; diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 34069ca6969..c6b3e78731e 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog { /*< public >*/ MemoryRegion iomem; qemu_irq wdogint; - uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; Clock *wdogclk; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 7494afc630e..513caa33a9a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -48,7 +48,6 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -60,7 +59,6 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 828127b366f..ef49f5852d3 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { } }; -static Property cmsdk_apb_dualtimer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_dualtimer_realize; dc->vmsd = &cmsdk_apb_dualtimer_vmstate; dc->reset = cmsdk_apb_dualtimer_reset; - device_class_set_props(dc, cmsdk_apb_dualtimer_properties); } static const TypeInfo cmsdk_apb_dualtimer_info = { diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f053146d88f..ee51ce3369c 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { } }; -static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_timer_realize; dc->vmsd = &cmsdk_apb_timer_vmstate; dc->reset = cmsdk_apb_timer_reset; - device_class_set_props(dc, cmsdk_apb_timer_properties); } static const TypeInfo cmsdk_apb_timer_info = { diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 9cad0c67da4..302f1711738 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = { } }; -static Property cmsdk_apb_watchdog_properties[] = { - DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_watchdog_realize; dc->vmsd = &cmsdk_apb_watchdog_vmstate; dc->reset = cmsdk_apb_watchdog_reset; - device_class_set_props(dc, cmsdk_apb_watchdog_properties); } static const TypeInfo cmsdk_apb_watchdog_info = { -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:07:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2fIh-0002uO-4b for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:07:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIa-0002ln-2v for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:16 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:44048) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fIC-0005xT-NE for qemu-arm@nongnu.org; Thu, 21 Jan 2021 14:07:15 -0500 Received: by mail-wr1-x436.google.com with SMTP id d16so2145405wro.11 for ; Thu, 21 Jan 2021 11:06:50 -0800 (PST) DKIM-Signature: v=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel Subject: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Date: Thu, 21 Jan 2021 19:06:22 +0000 Message-Id: <20210121190622.22000-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:07:16 -0000 Now that the watchdog device uses its Clock input rather than being passed the value of system_clock_scale at creation time, we can remove the hack where we reset the STELLARIS_SYS at board creation time to force it to set system_clock_scale. Instead it will be reset at the usual point in startup and will inform the watchdog of the clock frequency at that point. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 5acb043a07e..ad72c0959f1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); - /* - * Normally we should not be resetting devices like this during - * board creation. For the moment we need to do so, because - * system_clock_scale will only get set when the STELLARIS_SYS - * device is reset, and we need its initial value to pass to - * the watchdog device. This hack can be removed once the - * watchdog has been converted to use a Clock input instead. - */ - device_cold_reset(dev); - return dev; } -- 2.20.1 From MAILER-DAEMON Thu Jan 21 14:56:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2g4M-0001eB-7V for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 14:56:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2g4J-0001Zx-UQ; Thu, 21 Jan 2021 14:56:35 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:46033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2g4I-0001jm-BD; Thu, 21 Jan 2021 14:56:35 -0500 Received: by mail-ej1-x630.google.com with SMTP id ke15so4335205ejc.12; Thu, 21 Jan 2021 11:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=cvn36IjyNWynqnj0NTdBbXAB8BctJx158QAFYSxox8w=; b=cnQ2tVJpIMV/JFxmlxB7co281zlyeF9I2o9cWiKDoMIKqDg7mZOacjr9MN2c/4PuNv Vc3+Z5X4BLm7kYgw7L6DtFhhgAKMBd8YPK91gwPAhanXsQ3/J8DJmpZAdCT+bGeS5sAc UdzKUcDhYahC9JToVa4SjOUeGUS4HPAZHjpeSHK+Jw+ldWx5YzP/CUnT3SBq32s9GeXq cpEdlJ6WNH0a6DK526mffFfgp2pCRnP9qUp3MGItefRbpzno3QNji5gu5hKMQUN2iw3x jMu5PZUGVwi4qwnk6HbVMJ2dZYxvbk28gr2swocTZM7qLMYPyPpHlPe1dybd7vJCLYwf EJvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=cvn36IjyNWynqnj0NTdBbXAB8BctJx158QAFYSxox8w=; b=aKh5NTPaP6PiKipFKWGlW0AZ7M7V68dtcZqoV6C4cDV12yYuNvJHRdp6hDjrk3og/2 xDzpZDzVEz5ygDi0iJ/HhRoDbN4x0qdsBDXaDwLu8HwSz4zklSwHKuej76qRV/37dKBB rYyvREfK8rwkyo0WeS9IY47LiqRywqbFPn0GXJcsRygkf1RH462sHIuzbRyzjl/+X4js KGQAVmET13bf6dVVU0YXpVAUX5fm4oScLRufVlrUPAc+PIq+8ugPonrrF08qeFgdaBGm zQC4CF0dzTRInATQtcwQw9V8sN3vxKL2oBQiiZlv3J0E3SDI0s8xAPt0jNTUz0EJebBK EmIw== X-Gm-Message-State: AOAM533rxnfT8fVCjr0t5KslYogTqAjeCeyS1/RIJijO9KWcLrlHu4cW k+/h/4jlhFSsSRS/khebXOs= X-Google-Smtp-Source: ABdhPJyCNpUVGDJDY/BlnFN288A0JGrs56mX4yKMCAwOTpMLeX2d9IiBvzamDv6qwAlYJ5GPzQ1j4A== X-Received: by 2002:a17:906:3a55:: with SMTP id a21mr754578ejf.516.1611258992212; Thu, 21 Jan 2021 11:56:32 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id ke7sm2684276ejc.7.2021.01.21.11.56.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 11:56:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-4-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <962827b1-af36-b15b-2b2f-1db8459a6d25@amsat.org> Date: Thu, 21 Jan 2021 20:56:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-4-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 19:56:36 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Add a simple test of the CMSDK APB timer, since we're about to do > some refactoring of how it is clocked. > > Signed-off-by: Peter Maydell > --- > tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 78 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-timer-test.c Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 15:21:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2gSA-0006tH-5o for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 15:21:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2gS8-0006ss-EG; Thu, 21 Jan 2021 15:21:13 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:41908) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2gS5-0004AK-Sn; Thu, 21 Jan 2021 15:21:11 -0500 Received: by mail-ed1-x52f.google.com with SMTP id bx12so4017342edb.8; Thu, 21 Jan 2021 12:21:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=NSTvq2STd6U2RpvgIeu3fQA6GEXSLfXZ1us/azMianM=; b=k8Mxl0U0Xw2T/lcSfR0KBb2sttFYTuXZ9oo4vgg+oNjdfz3gkRfj8xyd6aeA9vPdZZ 3guWWEOb2HKiuxtOpz2gQctfUGqO6kaAQdgO3pvzOFvvM4DJWaCK3Z1iszH5vzQxsyb/ /ag6WbMMbosTDTvqVudxHm1xhqHezoTL9PP1zeUPeaZ6nybwFrjjW8CF+rV9qSL5RWI9 u0hbaUYf2SMezi1zNBgaIdpykxNRQkMsXsPNop75wcNaHAtRJgnOC8cXMHmFINTjK1dh ubjMsskvLHSPxmDcKSETAatJjM0S9i2MVDlcjzb3qRi9Ylj81DKhaZYI0GPpiwjBo7wb +gdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=NSTvq2STd6U2RpvgIeu3fQA6GEXSLfXZ1us/azMianM=; b=W14r+GZJ91QjSSdE/kpsB9s7ExdyldYSgeT4An0rktJFavOV8WtnERXbYqoQ4fxw3m RhXifCDm75838bUijA+Uz8jZxlVJSxyeIUSx8cDec7O+uPA5dJWGz4KGn6rzdLZYzuEL ueBh9QSydMeAX2OTfxlBr47S0vDXwnO3ErPvNgIU93zNVdJhoDpPjZR4W97gO/aZHP/A 4nyJ05ALV7/RISMpsjSD324GfbpuVgMLHQ/jnbo7yU00ek02OMxbu/W2lK9QazIQNnG+ g6clyoch0+iPwk9noZB37v38uhbwCHGIYWwZ5lrSA4YQXa11OEe/xS7qNn95QyNhHlNU ChdQ== X-Gm-Message-State: AOAM530ExZXp9pjhDDXHO/tQpPxf9TGx61FdDqg1PsDW51Q+DXs9lYC1 CgZW80ToD8q3Ua7CF7AJMuU= X-Google-Smtp-Source: ABdhPJwGNKPjirRmOk9E6VhEXe8YF2PPENn1UCJtwkm6i7R6ytI6QupwMq+EiaO+uP4phcxk92/zsQ== X-Received: by 2002:aa7:c34f:: with SMTP id j15mr700520edr.120.1611260465751; Thu, 21 Jan 2021 12:21:05 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id f9sm3343214edm.6.2021.01.21.12.21.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 12:21:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-7-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <0541fd0b-28be-b0f1-aafb-5a30a1bd1f96@amsat.org> Date: Thu, 21 Jan 2021 21:21:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 20:21:13 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > The state struct for the CMSDK APB timer device doesn't follow our > usual naming convention of camelcase -- "CMSDK" and "APB" are both > acronyms, but "TIMER" is not so should not be all-uppercase. > Globally rename the struct to "CMSDKAPBTimer" (bringing it into line > with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains > as-is because "UART" is an acronym). > > Commit created with: > perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h > > Signed-off-by: Peter Maydell > --- > include/hw/arm/armsse.h | 6 +++--- > include/hw/timer/cmsdk-apb-timer.h | 4 ++-- > hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++-------------- > 3 files changed, 19 insertions(+), 19 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 15:22:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2gTO-0007uu-Ve for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 15:22:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2gTH-0007rQ-A0; Thu, 21 Jan 2021 15:22:23 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:38913) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2gTF-0004lB-KO; Thu, 21 Jan 2021 15:22:23 -0500 Received: by mail-ed1-x535.google.com with SMTP id b21so4027351edy.6; Thu, 21 Jan 2021 12:22:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=BUyioOXyxpJhXE0jFgEZtyk4nWwaFvEEbfgUCv81KuI=; b=O5NZF3QfRB3617JnvXplSyMWVTbQ/mCT1XL3cX8JmJOK+hUbCUUpNvkewty9eShycf Tq2CKFMuWksEnfcjC80kopq87CL19GJutG8FKtTxXk4JVJwBXFNK7GN/Yeh//rs0BssJ /6HEkxFJCYaYZI0NHNNkvjRowYR1V1LSSJ5iBBrxd+ksHnza9KEjxOpWZ1wwG4ycLI37 sSskUn8VmVCjSMBWpU3Es2N0zjore/gE8LE5C7s9ffLONi5M8WbxLwPl5FoRHlS21yQM 7oaelFcpjGCOPOcqz72Dl/nWfy88IvNPful8I+o1wnjmJPuELkeJPBZVvcydL5Q5p27K 3K4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=BUyioOXyxpJhXE0jFgEZtyk4nWwaFvEEbfgUCv81KuI=; b=Qei1pEwBUctAoG7NlLieNZo8qGe6uq3eTvM4IDsRq96djzWHMgowxLEvQ9v0VZnwcf D/IpqXYCHDSyiyTEIhe/iQirQ+42JUB/gIAGZnlNGbbZgyvRHV1lQkDuizh4/CeUrTQt ZVgbfVnkWnV6jdPFHg6dqAGoO8wOMXJzdXtSlY7VieQCbdn1t+/+8Nly5IeHRfRdQ+Jf BmhEXhhwa/rLXvFeQpmfMnfjqocpKetI2bOWKh5FgHie5TTraXbfjq0WKl0aL+u5eGmw au1n/MFiGFn5c0/ITy1tA5ZCHuMA12TYv5rOiuVWZzfV74lYOTbc2Rf759TsBP8l19Yl eimg== X-Gm-Message-State: AOAM530qeVwfuu28ERVT/wj+yonIzFoCRqb6RdgrlouhLd26iuM5gqy5 UzZhej5LLuWHuoxRK07srGE= X-Google-Smtp-Source: ABdhPJzijagVKMsogEnOALFE5wDW0CahpFbUT/UHzc/M5Lr2nQmhQls0Gd/QYuFi90eYg+BATZyeyw== X-Received: by 2002:aa7:d94b:: with SMTP id l11mr696768eds.1.1611260539945; Thu, 21 Jan 2021 12:22:19 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s1sm2710726ejx.25.2021.01.21.12.22.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 12:22:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-8-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <197be2f1-7f89-4669-bf65-2d175753ac5e@amsat.org> Date: Thu, 21 Jan 2021 21:22:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-8-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 20:22:28 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > As the first step in converting the CMSDK_APB_TIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the pclk-frq > property to using the Clock once all the users of this device have > been converted to wire up the Clock. > > Since the device doesn't already have a doc comment for its "QEMU > interface", we add one including the new Clock. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell > --- > include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++ > hw/timer/cmsdk-apb-timer.c | 7 +++++-- > 2 files changed, 14 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 15:27:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2gYQ-0001i3-28 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 15:27:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2gYO-0001hg-Fh; Thu, 21 Jan 2021 15:27:40 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:32769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2gYM-0007AE-Ve; Thu, 21 Jan 2021 15:27:40 -0500 Received: by mail-ed1-x536.google.com with SMTP id c6so4093344ede.0; Thu, 21 Jan 2021 12:27:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=oMvVL1Lu7AD1uYUS2/jecpUu9ul0KAUMMVu3woq/YQY=; b=J+vohOxsMv0S6yy8cPw5t91i8xsFo7AsOTwAwDV/0dGdmOVCCai480jPJiDTQtrvef 5fHCLzPfhJHcjU4SjwRxfxiFLpI3l5kQHtqDg3EExSBkf8JlDnPJtHXwM5hUZt3yhjYv Mow4wpnpGWYDtD3BUA5UJQf3Wng3EA8mbZ6yDe/s9JRtq1q7mulz7+BcMZ4+SxRDLvby T9+C+X7g5RDvVn8Fr2l8tab2mOjvz5teM0oInS9ABLzLiua9Lgb+XQLJzorwFMW8gTce xLO0mB0LTVeKF3zY5hF84z6cBGaHyn41FnOe6lmFezfxSgTi61VoFD5vi1Df2b77ja3b Pe6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=oMvVL1Lu7AD1uYUS2/jecpUu9ul0KAUMMVu3woq/YQY=; b=emRGcWCrKbaINrDp8ELilIqMT80BH4ed6NALbm6JQ/dR+UAySDvdz0bUPspCjTnzVV nCt3OFcB0QfX/yNrjiWzwF4ckdZOJrvbMqiArJJTshSHXdu7JFmRU09GfWjqV8Iem8ky ymmYYvaSNdy7N5XhWj8P9JML04uBaV/afv4ZWcbhGK/5NTC+rq2R5FcZvDMcBdny8Fml yyfVR8+eKBjPAN71BXXFsOqT+4kSbrbaoGhjTfVAadaDg2pyIL2BVVmpog1pMS50NnsZ xKRMxztV4Rrb6DBv9CmcoMULiNpPOEOqPcAJFEpKomHMxnwq9PXAfdiLPdWgXhST1Mh3 crrA== X-Gm-Message-State: AOAM530hw/k1V0ROZh9ZdER5qIl/yVB272iHthP7Itt4JOv2iLLgA/7y yx+MkIz32JOjI55pkosiPm4= X-Google-Smtp-Source: ABdhPJyd6ihm22RlHwcwL602KhDdwT5CYMEEZUcxaiVdN4njLnZ+nQkPJpHam43zBCi4CiB5v7zmUg== X-Received: by 2002:a05:6402:3487:: with SMTP id v7mr751496edc.68.1611260857186; Thu, 21 Jan 2021 12:27:37 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id bd5sm2868776edb.86.2021.01.21.12.27.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 12:27:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-10-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1bec0b11-e749-6e04-17c8-373872f4bd60@amsat.org> Date: Thu, 21 Jan 2021 21:27:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-10-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 20:27:40 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > As the first step in converting the CMSDK_APB_TIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the > wdogclk-frq property to using the Clock once all the users of this > device have been converted to wire up the Clock. > > This is a migration compatibility break for machines mps2-an385, > mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, > musca-b1, lm3s811evb, lm3s6965evb. > > Signed-off-by: Peter Maydell > --- > include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++ > hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++-- > 2 files changed, 8 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 15:28:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2gZ0-0002IH-9W for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 15:28:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2gYx-0002Ha-F3; Thu, 21 Jan 2021 15:28:16 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:41973) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2gYw-0007Pt-1l; Thu, 21 Jan 2021 15:28:15 -0500 Received: by mail-ed1-x534.google.com with SMTP id bx12so4039182edb.8; Thu, 21 Jan 2021 12:28:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Oh/NnJGDSierQ7PoEE81Y5MP/2Ltap5XEIJcCO5sGlE=; b=ArpaNl0IIQ66K/yol85mxaGnKmixDSSzOrqGoNlWGibtLLWFViGkZQlEN0yvM9o++0 XYhWA8tdS+PSQJhM2M/ka2KTbCy4sTOQAB5EGY4Bj6l8TFqqUi2zz6FyF1+rVHkyukGD 9e6u1N9ymwfcyBvqtSsyH8Vb7QwkaHv1mSdPZJ0eEXE3/VCNJ7Cvqdsk4TJOyVXiMrys q0dDudRdpMiECXmipkMHDdXEKC2zi0+ChmvHHaE7+tw4n1PPy9mw/QqiEW5QfTzWok9A 5CBfFbLpJBX+q5HwHhRrIV+BiHZCYFZ3qkkL8Yen/qdXnIAoQRxO6YqdfyKJq5n6wWmP V4FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Oh/NnJGDSierQ7PoEE81Y5MP/2Ltap5XEIJcCO5sGlE=; b=U6M7nB0iS4/2yQrqFQFiMmOi+LNG3LFEoMQDXzdCThxBAnRWXHjUneisYvczuJiEXF QImC/DSvN2UqsZUKk1GLn5lwTUPfMgnGGqe02pSIPLs4yNpZJos1EV4csiFxMPwRVLXq zAPRs86LDaThPW+hbOsZl6LfI1bNEokAthf/IizfL3w+dhoFDRTrxESaz4ZyLXF35f2f Q1rtXV+otywx9ixpdReaXhtwVl6MbuG4BTrnwwRR26+WYJLEXm2D2lop4Go5Wnfd2nqP T+ikeiM0bNpwlWDRZQ6r1VCHjDIiw6BOVjEsqA0ScgkjmmmZ8rVsS6vltkaKJKnM4HBf krlA== X-Gm-Message-State: AOAM532EgBFbmoqxSD8m+Ps1fZPPDkSscwaj5HBANVxqR6PCzeE3FRO+ Ws5wj60VENKB46OThrbqsMk= X-Google-Smtp-Source: ABdhPJwilVMJx5iTwQyRhTn8fUFvlSG4e5LhTM3zLnohUMmJFhwy/VS7wKjh+qTu1+n4sCLzQw3pCA== X-Received: by 2002:aa7:c3d9:: with SMTP id l25mr761063edr.188.1611260892394; Thu, 21 Jan 2021 12:28:12 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id lv13sm2686465ejb.55.2021.01.21.12.28.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 12:28:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-11-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 21:28:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-11-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 20:28:16 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > While we transition the ARMSSE code from integer properties > specifying clock frequencies to Clock objects, we want to have the > device provide both at once. We want the final name of the main > input Clock to be "MAINCLK", following the hardware name. > Unfortunately creating an input Clock with a name X creates an > under-the-hood QOM property X; for "MAINCLK" this clashes with the > existing UINT32 property of that name. > > Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the > MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be > deleted. > > Commit created with: > perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h > > Signed-off-by: Peter Maydell > --- > include/hw/arm/armsse.h | 2 +- > hw/arm/armsse.c | 6 +++--- > hw/arm/mps2-tz.c | 2 +- > hw/arm/musca.c | 2 +- > 4 files changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 15:30:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2gb2-0004kp-L0 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 15:30:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2gau-0004j1-KH; Thu, 21 Jan 2021 15:30:18 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:42717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2gas-0008JK-S1; Thu, 21 Jan 2021 15:30:16 -0500 Received: by mail-ed1-x52f.google.com with SMTP id g24so4033643edw.9; Thu, 21 Jan 2021 12:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=fjpwmmROr2uPaXVHrxB53gZ6I7CkzrjK2iZvLXPSC3o=; b=EggsfCnJ2h9eEMQJm3YaDhJGz0bVU7G9ewGGOil5MEP39+8o7FQLF4mkMDpCTofq3p frtF0L9ruDb8gJl3DdrAm3jrHuR31Hi1JOeKByxrcp72A0eszIgMLSy3VzKDIkZie0Zn zAJ/Dkc8jMMSFg+QiQWwFTBxAeQExvk2Ufp1pkXFmBlM4gIda/6f/+43wqJG1hFsdkcG v4F7IdSsJo5WhhipgLda+C0ti+efjorFbvxDLaEoTHG0/izAMEx8Z7Tir6fx9RZcAE2a HbSdxkImRbZjC11G/7/A+LxOE2qGnSu9oMAM3T5jhWvrS5+UIKnd3eOK6U9n0SXoBRv0 slew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=fjpwmmROr2uPaXVHrxB53gZ6I7CkzrjK2iZvLXPSC3o=; b=DCsoBvmLmQcx5xwtE22vOeniLkECimN/XL5j2AgagIsBCCmGTCNDH+8r35MFKo4KJd LIkcR3VARhfGlQ4+I3jwIYLfBmL2qwnbc/rgWrok5fJ/HDuf56OgdpYpYchuRpcg3Omb lFyFu2fiCGGVIJkDQcKRUjm9nE9MrPKqRJ+3RdLMWboCyrv0vWuISAgPxMc0Aff4BMFZ z0tfNqF5XPM4ckcUlw5Zk55qNtIVQQU8/yskUEd8Az3/opJ0kiee1qzXZ+F/cbMdd38p tUICyWUVUIQOeKFIgLPmZVxFRc7+RDU5OAYYb2VdFVGDf2uhdgpFtgvdvIfqI0C5jGdd kt+g== X-Gm-Message-State: AOAM531fsnKBreBAqRR/XmmSlzTMw7GnT4PeA+9P1/ySfDgMZnFwZEgn UUS0lei+vd1BTRgKGFkNOWk= X-Google-Smtp-Source: ABdhPJxXC3j4OXLkJzFXdqqfqWhdnbyBqJBips1foQKpXjmJqCDbnPzsz5/lo/LYgEGqzgep5XBfHQ== X-Received: by 2002:a50:8757:: with SMTP id 23mr715300edv.294.1611261013355; Thu, 21 Jan 2021 12:30:13 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id j23sm3386245edv.45.2021.01.21.12.30.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 12:30:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 11/25] hw/arm/armsse: Wire up clocks To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-12-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9554cdbb-e00c-7470-9323-acf24d7b99b1@amsat.org> Date: Thu, 21 Jan 2021 21:30:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-12-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 20:30:19 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Create two input clocks on the ARMSSE devices, one for the normal > MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the > appropriate devices. The old property-based clock frequency setting > will remain in place until conversion is complete. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell > --- > include/hw/arm/armsse.h | 6 ++++++ > hw/arm/armsse.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 16:24:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2hRR-0003tJ-Sa for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 16:24:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2hRP-0003sN-VI; Thu, 21 Jan 2021 16:24:32 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:45228) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2hRJ-0008Lw-1e; Thu, 21 Jan 2021 16:24:27 -0500 Received: by mail-ed1-x529.google.com with SMTP id f1so4181787edr.12; Thu, 21 Jan 2021 13:24:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ktvptkmbOc3LIbss4D7YnGlDoURR3Z5R/uvzj8wLRmo=; b=RaXIuUyGFX5Gw1vsS1n+9F0BLKVyZd2K67doAEPdhZTrD+J7PuA+iBXpCRkPhcMP8b h21r8F3/+wz2vdqBGwtXP5ss2XVNURIFOiem8FBPTQ1Mz8dDHb8hi4qY3cRU9gqT1ujQ 1ij1Sid8MtU+GcU3axeTMbxiUi+IN+I2GjQK0IQEg7qCgiyaNSskYRFaPrdZvmwb2SWs bhvwiIhhItDdLJQlJwIpoJyeH7GH49uSB0S1jtpf34NPbTHvFuhKQUxXeCzLe/ZhMxVj L6GvaNzOctrlsetOFgMd2fCFKMqjuvzXqByb+6LE3IyC7wALCDQmQblUlHUpX7/mtXS8 EQXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ktvptkmbOc3LIbss4D7YnGlDoURR3Z5R/uvzj8wLRmo=; b=qzCvmB9IrQN+hJfEwYv35rrYeVRiOUZlMrflf2Mu49m1lJhtVX4wy6KmlyLZ/qosov 3oGW6B23Fwit9ZpbBEyimrz45FymfLLW9urLv/2S+POyzMt73ldYfXXbIpFa8FJP76hW GOfXXsoTXYMRUS9c7xre6MSSmy10hDgxR8Oi0fPEvZkHKSTYIHAzPyqd67CO9grOHiub er3jGra4g7yKzFTEivYRCk+rcCgEeftRnLvZmTtwCy81stB/iRL6yTu+jk5V8BMixqSQ 231ShPdC4LqUw+Wn/TbKJ1lTsvGOY5cWzlawS/BM8sigahmz0cT7aGG1jM81b29tk1EN Qllg== X-Gm-Message-State: AOAM5315obWrDBdB6QnrdyUEcIHEMRlfpXlM5B6yV1a6JGrH/hjv8wOL 2l7UFZJDI9nLkl+jY6IlxGM= X-Google-Smtp-Source: ABdhPJwOJweMjI7v8tg5UlASyVHqf/ik0blB6ehVwLDQ9dFRDpxSXOOcXPl3Im6YToVyPNvZkRq6qg== X-Received: by 2002:aa7:d148:: with SMTP id r8mr857092edo.127.1611264261523; Thu, 21 Jan 2021 13:24:21 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id w4sm3460329eds.40.2021.01.21.13.24.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 13:24:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-14-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 22:24:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-14-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 21:24:32 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Create a fixed-frequency Clock object to be the SYSCLK, and wire it > up to the devices that require it. > > Signed-off-by: Peter Maydell > --- > hw/arm/mps2.c | 9 +++++++++ > 1 file changed, 9 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 16:30:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2hXM-0007ui-Q2 for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 16:30:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2hXK-0007sQ-GV; Thu, 21 Jan 2021 16:30:38 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:34165) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2hXJ-0002iJ-2U; Thu, 21 Jan 2021 16:30:38 -0500 Received: by mail-ej1-x62b.google.com with SMTP id hs11so4746196ejc.1; Thu, 21 Jan 2021 13:30:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sXZlqrgkOFwHCKdSvPskOVNqifgwnVfhLMXVsd1Xjlo=; b=rOuJsSGUcsHdMzADX0+UsSdjO2T7uDb81yV5kL1YK6t9K+el0uT6swta1LOSa5zBbz lRmp68Xl/0H+9kVFtCeU9BEy3Or3guUnqF1eOQslL50RQr6nlOivdF8QUiUrg2Zsbhgw +9TOHXTUa0IsFz0UcPA3XcuKSc7ROg7g5D/y7m3stvBUZmI+W20b9MuWJqg7KY+u/YZG BZgsIQAzK0yBaU3i7Z9LeH+ovGRGeVadr10PnpN6JjqCDq/E3h263Wa6JqN8PML1LkEf LvYUm/vLABqNLuRRhhvoxNZjsyuQlwkXe+gWJ3n2jYox9rLUnkOedW08HmrrKwCTl0Ys AjJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=sXZlqrgkOFwHCKdSvPskOVNqifgwnVfhLMXVsd1Xjlo=; b=uZxaOM9toYu8h07gOIeB6hOItkeLoy3F9PeSl47YYT7ea6clzIFoZkVX/gWMu1c+2u akUP0uVH/1ejc9qPsJb+0MwPicqnW2xmYUBOeiWcMqHuN0FXiU58DBC/csB6rudU125q 3iOxPU12V7XNZtKLaBcyJlEADhlgYp4/Pz9sFUAiYNJ+niUM+JdNodUqaxYWY5XhyZEi BSmA0+FxDqXEHRHXmwd6WtGmOxihgDL5XIO0c0HlfAajqGBVItVMJDFzlfHVCNijUzM3 POivgQqQ7zsrXCwiyoOF7Pd8cpQi51tAQ4SBfCzaQS7KO9qcxIMOXm4lj3+VGGZB/g1F avpA== X-Gm-Message-State: AOAM5324rkdS/pXdV60jAvqP7QTFdiEGOKBFvk903O7WJaWhu7IMjCQ3 4EgjrU3P25mlUk41ZDIwhKQ= X-Google-Smtp-Source: ABdhPJyBlK4W7fY3QOjjC8Do6SB9mKzYl3USWQFn9b/Y0LFuL8SVQeMXs0LgpIjYpOsF8NArMoo0mw== X-Received: by 2002:a17:907:d27:: with SMTP id gn39mr911811ejc.152.1611264635467; Thu, 21 Jan 2021 13:30:35 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id i26sm3482324eds.55.2021.01.21.13.30.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 13:30:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-15-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <14467f6f-97c5-37e5-2371-118af184ca41@amsat.org> Date: Thu, 21 Jan 2021 22:30:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-15-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 21:30:39 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Create and connect the two clocks needed by the ARMSSE. > > Signed-off-by: Peter Maydell > --- > hw/arm/mps2-tz.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 16:31:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2hXr-0008A3-0L for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 16:31:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2hXl-00086x-UK; Thu, 21 Jan 2021 16:31:07 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:36216) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2hXi-0002w4-OI; Thu, 21 Jan 2021 16:31:04 -0500 Received: by mail-ej1-x631.google.com with SMTP id l9so4737435ejx.3; Thu, 21 Jan 2021 13:31:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=4/iUgRtZ+SdfZuLBX06+kzSTOFhrQyTCfQBm5lELLK0=; b=oppMkzrSPBxAAvFtwBvggNqVmI/8KkFOYgeniCnvii09RRkM0DY8d8GkrD3LMhVlmM vHc1D9ra34BwZuRm9HQYSyfsWFw9/29zvxNAffZk8yTthcccVB0Dj3WqLp8tA+2sx4eo FCfcWu5UafcWoOhko+MCyxZKyPK2qRQ5EP4wpbSt5m+zVAVFU4LnSILIRyoOylLM2+X5 no4Q4e62I+7814VvN1jOPqWKrfUzDQMOAcuk1yrEM5TDsaZIzhSn+acduP44tcjDKwXP 5arNGgqatXNTHPbkYcb8i9CLFEKHVYUmkk15yYNgqj7zLTrC4IDVWwXfEq0Ku3/OwD4H TuOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4/iUgRtZ+SdfZuLBX06+kzSTOFhrQyTCfQBm5lELLK0=; b=XQd0lZ+VJbSn+itLCc8Y6qywP9Y6ghpgBeAJd2CJuvJ8UriM12bqz6DadyacRsTLtR 9O6PTrpicsmfifRTOjfZUnQ5B0JfpGxxPsFlU5HAZD1O9jumrrGGvaPRSoeLZdnjHTCZ RBD5pz1rYWRdIgwfvoF/+JM+xyKF6eRdgMik8pJI1dp18NK93JMO08v4gPdhs2R0r6Tz TBzW02wSUq7z8mzOWSaCSdraSiEFsWKo0SZThgPCp8ZF5kiVyiJwF2FuWHbONS5h2/LY uuSk3PJpVRbfAiUql+Sw5M8kTSHiElWuyUkWKw64D8k31qC1EHUvNvblbk1olK/jegNZ Nq4w== X-Gm-Message-State: AOAM531e3InHFQX0pwrDRJyD1gq+VnOrPDfZyQiijjfWMAF6YngvMH08 l2EuilbbyK9CEZXc5FBLzmji/42vowQ= X-Google-Smtp-Source: ABdhPJwqz8yVyLgGrfaCwPX5bOJcVTB4iyZSKA9o8huoa84cUKzfsek6TDDIpSg21Us3tUWXZpFw5A== X-Received: by 2002:a17:906:958f:: with SMTP id r15mr923901ejx.360.1611264660808; Thu, 21 Jan 2021 13:31:00 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id bd5sm2970988edb.86.2021.01.21.13.30.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 13:31:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-16-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <50daef47-3304-7395-b9b9-c32823c04324@amsat.org> Date: Thu, 21 Jan 2021 22:30:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-16-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 21:31:09 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Create and connect the two clocks needed by the ARMSSE. > > Signed-off-by: Peter Maydell > --- > hw/arm/musca.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 16:49:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2hpr-0007kq-5d for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 16:49:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2hpp-0007k9-Eb; Thu, 21 Jan 2021 16:49:45 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:43882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2hpn-0001n6-Te; Thu, 21 Jan 2021 16:49:45 -0500 Received: by mail-ej1-x62c.google.com with SMTP id a10so4762267ejg.10; Thu, 21 Jan 2021 13:49:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=NZRv8c56LxDFfvf4ediy/CV9SnfkpLYQikuf+TGdR8w=; b=fmIXTZXwnAzzIhvMdTjwJFBKWV4jIQXhIGfOsWt0r626EW6yajkl7jGB/ey45+HHgA q4mWc8ZjcsUc0wJP0fP5tBkf+GP2cvI5ReghIr+AmF5AEsOahw256Ph4RIIArW7ncN7l VpmmbySO3G4JhTgI1Tf3jB73A90HXvU9hK570O4mqoCAWLga9ZFvAOrt7RGF5cv0ebDN UNd/0/VyR7P1hgnzaVdo6ZvTnN6m9ywp8y7ZADG10NXhpAtimye8Y4A6y2ZacCshp2pW qu7/Mi+126cRtSbxxM+3/SUcyAtgcTwHy06gTDlUfuZ/O+/QltFBeKqnoDxjRviOlpFC XkhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=NZRv8c56LxDFfvf4ediy/CV9SnfkpLYQikuf+TGdR8w=; b=uKmI2dZI6vA+E4+XPGGXURxSMFFNo0+q07YMbCJ/cntvEXm2RGpk5sP64k76D23GyE Xb6ftWX3KoY6jnkr52DZtP938El1G4pEV3uGRBIj5ysPvsJQaUOO1Rn9fm870TFGqXe5 BaJ4EmjgRdpQ3hqAVCpTYZ/6oyDLTCDDJ5v2YdWL88FVC5KLvyegTnrZqTExGf0YUaRk zF1tPGP7cbG/YYksthH1RfOXpOcbqbTI5FULY7YacUXxXZ3CXDTpri8+1YdKkrlf3Ocu K6LZqF8WT4lt+4HB/16phJiCOzSZXQFV6I87cNUQ+LzIfvD+cwnOaGYjkNBWbMqyAxIq XuhA== X-Gm-Message-State: AOAM533lMJ+6BqbV5woDKrZ7xQD00jrNuRzr9D0oIzSWUYI04klLQqOS qarkdfoVcNTJjEdjcsLJNcs= X-Google-Smtp-Source: ABdhPJx9/Evzjj6GxD8jpApr1LvN0L87tPEAYCUPAwpvsQPNMEky/1VxfrCx3r1xCPJGSB5RDP2UbA== X-Received: by 2002:a17:906:11d6:: with SMTP id o22mr1039569eja.106.1611265782143; Thu, 21 Jan 2021 13:49:42 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id h12sm2869385ejx.81.2021.01.21.13.49.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 13:49:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-9-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <34e1d477-ccb5-2dab-ede8-54349e1b1cbf@amsat.org> Date: Thu, 21 Jan 2021 22:49:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-9-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 21:49:45 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > As the first step in converting the CMSDK_APB_DUALTIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the pclk-frq > property to using the Clock once all the users of this device have > been converted to wire up the Clock. > > We take the opportunity to correct the name of the clock input to > match the hardware -- the dual timer names the clock which drives the > timers TIMCLK. (It does also have a 'pclk' input, which is used only > for the register and APB bus logic; on the SSE-200 these clocks are > both connected together.) > > This is a migration compatibility break for machines mps2-an385, > mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, > musca-b1. > > Signed-off-by: Peter Maydell > --- > include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++ > hw/timer/cmsdk-apb-dualtimer.c | 7 +++++-- > 2 files changed, 8 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 16:59:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2hz5-0006Lo-1f for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 16:59:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2hz3-0006Jp-Cy; Thu, 21 Jan 2021 16:59:17 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]:39689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2hz0-0005Il-Rp; Thu, 21 Jan 2021 16:59:17 -0500 Received: by mail-ed1-x52d.google.com with SMTP id b21so4306334edy.6; Thu, 21 Jan 2021 13:59:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=h4M1rJIQpG8KOnehG+d4P5qGua0+3zSUZCd4tyULlTI=; b=qmd4mEPFFWsLfKHpBboyXCF3QF6Jjf0BKLsG1sRD2rTgIuIg8GNb/MbjNDqfDe7lKM 9PrLEP7A7YUDwQUrXT3XGIbGDqe2Xl/Lss6LQ+gQTsBTJK59R5cyhv4PwRBsFiJ25Fb5 X/19618iXnzyvekn8H7iLPGy+fR4RmgK3EZ0RN7/Z1AUF5C8MXKCZRMdipS+F6ukow8T LLxOfy+b26aC6l+rEMhobTksaF8lJZXbbcQw7Iw6bTX5l7myUNrhQ2//eMnE621rlSnY 6nriVwXvDpsopwW82D/TtaknCABzrlQBKRZ+ox7BQhxq1PndbWRhbyo7jb8ROHoJRPez HXLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=h4M1rJIQpG8KOnehG+d4P5qGua0+3zSUZCd4tyULlTI=; b=E1IjSvDnl8bIheWjn7Acq1iZcartxEJyo4Tk5UE9O1RwwouXoiQu1EtiFZjjnqHqL/ ZcVnxwmotplJaU686EbYAKGbhXtEkukjB6mWj2YBOCu6qd7jf+rAoIOfAW7JicWmtvrv bXPjLE7FSwxqQOn9M/81hkQOWV0JPnKX68zwPbLJYGm91cOv2B1frSw1dSF5JMBNcu3q YzOIQvgDUaXQAgr8p2nZ2zC7gM5s/VTEfSn7O5GF5yRx0x847axLFjKmfyFXbekPCtRj 9gWUfYYMOlMnnwNMal8qmzFR/nCNmVRfBQ+Nhc7Tj1A/kDzV4xHdd9PxHj/c2z8hJZbn DZWg== X-Gm-Message-State: AOAM532Pt+q+vm4Vn9LEC7bOzGv9N/XW5bBzl6cTyhghQIVedKOvJM8h L/JjGrBDJ21YuG8Suommk68= X-Google-Smtp-Source: ABdhPJzGJItK2eRG9Xrfs55EZie36oiSJOnAOixamWt6ElY53YnHZB5F0QYTnR1rd9M0hFkO/Z2iPA== X-Received: by 2002:aa7:da41:: with SMTP id w1mr996738eds.24.1611266352708; Thu, 21 Jan 2021 13:59:12 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id r7sm2851863ejo.20.2021.01.21.13.59.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 13:59:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-18-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <5ee67f0e-fcda-22bb-2001-109e488cd632@amsat.org> Date: Thu, 21 Jan 2021 22:59:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-18-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 21:59:17 -0000 Hi Peter, On 1/21/21 8:06 PM, Peter Maydell wrote: > Create and connect the Clock input for the watchdog device on the > Stellaris boards. Because the Stellaris boards model the ability to > change the clock rate by programming PLL registers, we have to create > an output Clock on the ssys_state device and wire it up to the > watchdog. > > Note that the old comment on ssys_calculate_system_clock() got the > units wrong -- system_clock_scale is in nanoseconds, not > milliseconds. Improve the commentary to clarify how we are > calculating the period. > > Signed-off-by: Peter Maydell > --- > hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ > 1 file changed, 31 insertions(+), 12 deletions(-) ... > /* > - * Caculate the sys. clock period in ms. > + * Calculate the system clock period. We only want to propagate > + * this change to the rest of the system if we're not being called > + * from migration post-load. This part was not trivial to understand. I read the Clock API doc again then found: Care should be taken not to use ``clock_update[_ns|_hz]()`` or ``clock_propagate()`` during the whole migration procedure because it will trigger side effects to other devices in an unknown state. > */ > -static void ssys_calculate_system_clock(ssys_state *s) > +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) > { > + /* > + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input > + * clock is 200MHz, which is a period of 5 ns. Dividing the clock > + * frequency by X is the same as multiplying the period by X. > + */ > if (ssys_use_rcc2(s)) { > system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); > } else { > system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); > } > + clock_set_ns(s->sysclk, system_clock_scale); > + if (propagate_clock) { > + clock_propagate(s->sysclk); > + } > } ... > static void stellaris_sys_reset_exit(Object *obj) > @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) > { > ssys_state *s = opaque; > > - ssys_calculate_system_clock(s); > + ssys_calculate_system_clock(s, false); So this makes sense. I'll keep reviewing and come back to this patch later. Regards, Phil. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id di28sm3496425edb.71.2021.01.21.14.01.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:01:09 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-19-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 23:01:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-19-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:01:14 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Switch the CMSDK APB timer device over to using its Clock input; the > pclk-frq property is now ignored. > > Signed-off-by: Peter Maydell > --- > hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c > index c63145ff553..f053146d88f 100644 > --- a/hw/timer/cmsdk-apb-timer.c > +++ b/hw/timer/cmsdk-apb-timer.c > @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) > ptimer_transaction_commit(s->timer); > } > > +static void cmsdk_apb_timer_clk_update(void *opaque) > +{ > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); > + > + ptimer_transaction_begin(s->timer); > + ptimer_set_period_from_clock(s->timer, s->pclk, 1); > + ptimer_transaction_commit(s->timer); > +} > + > static void cmsdk_apb_timer_init(Object *obj) > { > SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj) > s, "cmsdk-apb-timer", 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->timerint); > - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); > + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", > + cmsdk_apb_timer_clk_update, s); > } > > static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > { > CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); > > - if (s->pclk_frq == 0) { > - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); > + if (!clock_has_source(s->pclk)) { > + error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); > return; > } > > @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); > > ptimer_transaction_begin(s->timer); > - ptimer_set_freq(s->timer, s->pclk_frq); > + ptimer_set_period_from_clock(s->timer, s->pclk, 1); > ptimer_transaction_commit(s->timer); > } Nice to see how ptimer_set_period_from_clock() fits :) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:02:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2i1f-000870-SL for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id w11sm3610421edj.8.2021.01.21.14.01.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:01:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-21-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <4aa239a1-c958-498e-e2e8-1bb61876c9b4@amsat.org> Date: Thu, 21 Jan 2021 23:01:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-21-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:01:56 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Switch the CMSDK APB watchdog device over to using its Clock input; > the wdogclk_frq property is now ignored. > > Signed-off-by: Peter Maydell > --- > hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:04:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2i4V-0002Tu-JW for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:04:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2i4S-0002QJ-9l; Thu, 21 Jan 2021 17:04:53 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:42477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2i4Q-0006wL-LQ; Thu, 21 Jan 2021 17:04:51 -0500 Received: by mail-ed1-x52f.google.com with SMTP id g24so4303785edw.9; Thu, 21 Jan 2021 14:04:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=vuwzp+KofayMUt7tPD5F1m553xJPWL58EvfiWDj4T4A=; b=WMCJM4u4SiuKzCnholzsfKQlKdfXlekg0WZrNt2aT1qSU6tg/162fx7HOw2wB9sNSx 7bqw0nkH38itiJhKqvctXAf9A74Dk3l7n944Ud1fenvfObHjmPMkJE2vNa8MjVaCvT5Q 5SR/LAqVW9qNOG94FEoNwT9ReqSY3lMkbzLqyNqcJNMBzBWlsWkxOd7L6gyl1oTV9eIk V8IRZATg8yEOYYlDsp9C3mqaHUVI/QMqBTcF0fHmAHtOQRQCtG5LfOv6/MmJncUHiOzJ Lcxxa7Q59f/IFH9ad+9iDOo0roE9BV01SfCLRjDm182vs0zARhixAu4T6Bf4nCdrGEWz gebw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=vuwzp+KofayMUt7tPD5F1m553xJPWL58EvfiWDj4T4A=; b=ab3ubxrM2IlXeLavvPYJ8LhbWIWyhgJTOlIFiqGtXSityV1kwRUZR1gsLC3zwNPS8L NjxHRkOKTxnSJ5WJFbnKW58/xZmr3wBuprY1UrsQzgyLeOpq2zjON6ZZhTLVbpoFAJia Iuj2NhGfXKVcA1Jolt+c6kyF1Bbt63luOlhZfRlTVG5JU/I+ouGfva6xccdRmd26xIzJ h2pnP0c4Y+Ede8RXsoTaTMN/O5s4vKf1mqBrSccVHtus5/w5eL4ol13nH/8JBXMRcDwb RAUJbtJ0j2j7BIxvhzXIrxRPCHzsCtqmvFhMZ0x4952w//+VpPk4CH2AHBdSVIi4GL3F WiYQ== X-Gm-Message-State: AOAM532OzwDTfyck1oOwkoeamXdzQ+QDrArETFNGXtfQjnwSqJP8lJW8 VFGhy/QVf6+PiWAOEWiYT0k= X-Google-Smtp-Source: ABdhPJy2xe7iRON3CvtHBFB48QglpaGgMjfAUH6aq7uc7jqZXWiwh/pTlfcDiMSLBwGTD+wjvwEZQQ== X-Received: by 2002:aa7:d352:: with SMTP id m18mr972891edr.190.1611266688845; Thu, 21 Jan 2021 14:04:48 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z1sm3593401edm.89.2021.01.21.14.04.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:04:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-22-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <25e41627-e6a0-1754-6f75-0819219dc2e5@amsat.org> Date: Thu, 21 Jan 2021 23:04:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-22-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:04:54 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Now that the CMSDK APB watchdog uses its Clock input, it will > correctly respond when the system clock frequency is changed using > the RCC register on in the Stellaris board system registers. Test > that when the RCC register is written it causes the watchdog timer to > change speed. > > Signed-off-by: Peter Maydell > --- > tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) ... > +static void test_clock_change(void) > +{ > + uint32_t rcc; > + > + /* > + * Test that writing to the stellaris board's RCC register to > + * change the system clock frequency causes the watchdog > + * to change the speed it counts at. > + */ > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > + > + writel(WDOG_BASE + WDOGCONTROL, 1); > + writel(WDOG_BASE + WDOGLOAD, 1000); > + > + /* Step to just past the 500th tick */ > + clock_step(80 * 500 + 1); I was wondering about asking you to change that 40000 in patch #3. Since you use that clearer form here, it would be nice to have it in #3 too. Otherwise, Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:06:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2i5Z-0002z9-WD for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:06:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2i5X-0002v5-G7; Thu, 21 Jan 2021 17:05:59 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:46736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2i5U-0007I2-Fd; Thu, 21 Jan 2021 17:05:57 -0500 Received: by mail-ej1-x62e.google.com with SMTP id rv9so4806193ejb.13; Thu, 21 Jan 2021 14:05:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ePNJAgxjaVPgOhZLR3Q/I8O50UumMpXbnpxBGQ2QcF4=; b=ca7ry6l6abY3ogQXSglhpriwAlgojeaO8qDN/TKtGTVMptaCy5bmQYDouN/syCkt5B s8Fo3QiIIj+VUyotyyfWBDaT4uORx/gxXCntGdeuDByRK9vbdxipLUGgSTwsW/wn7dfn mZnPs08xgnnsVwFhmptrEaMXnkjQ4uIdZnnuni02Gp3UOh/5SJL9OaVJE9eHQSM66G16 vqULV0QEOMuF2DevbR1VLS70OARJtu1fmm7pB2SX3xCw/GJ+kiOIfjeR/A4dVmLJ0X4Z RPSKsN8DT5uD8aL8rp5WtabKcaTnDWfTdwy2SYk25SIDJfYWwSGtvcP06ac3K68hFQYC cfpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ePNJAgxjaVPgOhZLR3Q/I8O50UumMpXbnpxBGQ2QcF4=; b=Nqq8aGVsY7Qdc0Rxe3tgc2ZE8cKKgCcbaYyfpxqCdXHIfFAvysu/N3pmVNex0FNmpG y5EPYzbuAyGGa4ZvItbS5hJ5f3EhpLLGPDNQQzltcksXhj10gH59+GhoAA3jw2oIX73g lQUVqctiUM5hGvEHWBpsAwe68B73C4Z/MDaVrEHLoPi4CoVtKhOtm7ZiiiZ7f6w44U0n PmXhx4CJKGE0zWVEPHiDC4h2ywICbHftEAPQNcY5fPB8PvmCCQnwDeFJGolc/0RsyLIl gJdeIKTxaz9MX9asPZX0A3MGK6Ve+WCDTHdqbxO10CwanllK6OfpZP3O4EMA272e0tt9 jjHA== X-Gm-Message-State: AOAM533sIRj2/3i6WTSXmyVfVjJI45SvLv4Aik4lBhWdzgY5ZqPPL4HY L6rNDcrO2kh9GQVI0batvDE= X-Google-Smtp-Source: ABdhPJyuaDRwl4qjEKabIjK4Tnv0TvuHVVBBGj8oh39B/6srrZuY6vTTh5TdzH142U2KC6qN7ZBGpg== X-Received: by 2002:a17:906:a1c5:: with SMTP id bx5mr1059378ejb.284.1611266754789; Thu, 21 Jan 2021 14:05:54 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id ke7sm2863264ejc.7.2021.01.21.14.05.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:05:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-23-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 23:05:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-23-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:06:00 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Use the MAINCLK Clock input to set the system_clock_scale variable > rather than using the mainclk_frq property. > > Signed-off-by: Peter Maydell > --- > At some point we should make the SysTick take a Clock itself so > that we can get rid of the system_clock_scale global entirely. > (In fact we want two Clocks: one that is the CPU clock and one > for the 'external reference clock' whose period is currently > hardcoded at 1000ns in systick_scale()...) > --- > hw/arm/armsse.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:07:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2i6V-0003w1-7Y for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:07:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2i6Q-0003uK-HF; Thu, 21 Jan 2021 17:06:54 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:38667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2i6P-0007lH-0v; Thu, 21 Jan 2021 17:06:54 -0500 Received: by mail-ej1-x62b.google.com with SMTP id 6so4850992ejz.5; Thu, 21 Jan 2021 14:06:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=FD/Lnz0jfyE5PYoSqi6tgXnBD0e6UQNzBm9X8MeVZpo=; b=PmjuTGQrYjA/clv6anJK6+KvW/R1bGgoTGPU98q7BvCKBm/7lsjhyKNpfKHQeZZTNc WcLcudQg8YLEOPie1hl3UkWzTGxqtIvgHALXfV5fBjmWgZdRYq3Huf4qYr0I51nlWriu d19QUbMTYAyyvHLsTHJ18zYoBhSJ5PH1akoipsXjEfdf9yfoweSm/Wk4mqgPfrxT/Ac2 sAdWUyuiIRMC63mfxq55ws5DCY3oo8XXNWyZ8qVNqUQfhGFgEXS5ulU/gVTUkG5vt4TA +zj/qq9f/6wEP6XLNoc7o5OeFxf6IEvM4dsfEvX1AlCP/4OWIAp+1pIoVD9JogKh3Qfz ciUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=FD/Lnz0jfyE5PYoSqi6tgXnBD0e6UQNzBm9X8MeVZpo=; b=jJgdDfQfKdZS7Wwx51OfU7ijvMhzmtBVJDXpANFDEdPnNLQJJKhoVPqZXfTYH9uh0A wdy4+/0BBrohUS2hV1lNvIgV/QSzamqpeGlWIQwud+j8zvR6bB3Y97GcXsFxRFs7HlOa +PnRHcN/GTzpL9GfH5qACOu2Ii7DT2+a/F/4E5ofFjDZzE4rEi5REbO+ZBkjXALTM/IS RwH2aFlydRXUQ0Ly8LQhE2pLxgHuZtXSwiduB7vLnyq40LVtSOzIRcWLSY6Mr4FOMN48 tNA94b3qEu1Vt/oiaiz+mQkaqqrrtsWMB+BK5pzN6j2VNqlio9te2O8F5s7HmkaWWyzR H6vA== X-Gm-Message-State: AOAM533XwsjR8GnUt7+Dy+sov5IuJWX7RcTgs/Z7xQT+5cZUCcAE4x1y O7acFB2qwpMHF88lvKDiqzg= X-Google-Smtp-Source: ABdhPJyJYxchzRBjiThgFR1AoH1W8Ex95ekJzQXViv75PXP3DqfrbIt9v0jfG6Y+kk3c1LfcBctYBg== X-Received: by 2002:a17:907:2651:: with SMTP id ar17mr1009019ejc.98.1611266811013; Thu, 21 Jan 2021 14:06:51 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id da26sm3550938edb.36.2021.01.21.14.06.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:06:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-24-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <8028e020-168c-e7b0-3f83-f5176aeaa049@amsat.org> Date: Thu, 21 Jan 2021 23:06:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-24-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:06:56 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Remove all the code that sets frequency properties on the CMSDK > timer, dualtimer and watchdog devices and on the ARMSSE SoC device: > these properties are unused now that the devices rely on their Clock > inputs instead. > > Signed-off-by: Peter Maydell > --- > hw/arm/armsse.c | 7 ------- > hw/arm/mps2-tz.c | 1 - > hw/arm/mps2.c | 3 --- > hw/arm/musca.c | 1 - > hw/arm/stellaris.c | 3 --- > 5 files changed, 15 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:09:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2i8l-0006DO-Em for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:09:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2i8j-0006AW-Sv; Thu, 21 Jan 2021 17:09:17 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:42443) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2i8c-0000Fd-Gr; Thu, 21 Jan 2021 17:09:13 -0500 Received: by mail-ej1-x62c.google.com with SMTP id r12so4819547ejb.9; Thu, 21 Jan 2021 14:09:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=LQypYJU7QQfNLIjMpe0ACD2LECqAVbbVWOCOEkL2EsE=; b=LGYBDp6LeaTMiKdyEkP57IL0HH+RXVrSOq511bBSH1DgNZ/bPdYTDIFDthCpyG4+DY uHR0R5btgEItuxKj8tI+tt7/80oEV5yTp0jZHjs6tYj4th6lTE9gLAc2ZSrVQ5XlYZDa dyRO+DD2Q2TklGzKS2mqwD5+qxuCnjgRGazev3EQ41apl/0GDEY6sN3srEXjYIGaH1Od N6EetSPbU35dUJ1eZ+2QC66AYqxgdyjxh68+lZf5eYhO27BM0kNcuIQ2m9a7arXRc0FW 5GyfsLczqPXscoxcBqFbD/DbfBl6S6+05jjK7EymF0HAmYX8oG3pI+ozwVEHd8zEhyrl f8HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=LQypYJU7QQfNLIjMpe0ACD2LECqAVbbVWOCOEkL2EsE=; b=PNAIcuSqEA3OUsN6Eu/br93SOXSrmE/y522ko1dTdRv8PqTay3/TTXweXVuZY5L3ZT QxkP75Qy9sB+WTQvezmc7bqKeA/4zpqUPJSrXB1PDPBNeqe8u3+2hOJZnkv3hod1SlNk Pm0GguzN+DAB8ILTmlY95KQImZ87CHoc+8RXnVIYFcai4mNpF0z1iohkdFfwEj2MyDr4 5U7NNF91z6J9Xzop73KLD/duvK5pijnVLNPQz7T38vLWNasPc07cBwriLdNHQClQaNz9 QEE5+Nw/itZq66tC4Bw/WWIrspwMR80jGfERUEGyFGTFqW3pCcZ3m3YBuhFsl9lGlrqS mbJA== X-Gm-Message-State: AOAM533re4x/PTzrAONt5wodAstvqiq5ispahfjNraNQwreYAJ/iaBtE U+rKxuUlNa5Lv3R1rSpfXzU= X-Google-Smtp-Source: ABdhPJwmV0uws8hf0OBey5BHS4pe2pVNIh9d0bYO9jfBfX858WHGUnu4cv07AHdGY9rBrgXuJrYDNw== X-Received: by 2002:a17:906:a48:: with SMTP id x8mr1012469ejf.444.1611266948537; Thu, 21 Jan 2021 14:09:08 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id k6sm2818481ejb.84.2021.01.21.14.09.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:09:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-25-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <2e0d6341-0e62-4d4c-6ffd-4dbd5895f918@amsat.org> Date: Thu, 21 Jan 2021 23:09:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-25-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:09:18 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Now no users are setting the frq properties on the CMSDK timer, "Now that no ..."? No clue, double "no*" sounds odd to me :) > dualtimer, watchdog or ARMSSE SoC devices, we can remove the > properties and the struct fields that back them. > > Signed-off-by: Peter Maydell > --- > include/hw/arm/armsse.h | 2 -- > include/hw/timer/cmsdk-apb-dualtimer.h | 2 -- > include/hw/timer/cmsdk-apb-timer.h | 2 -- > include/hw/watchdog/cmsdk-apb-watchdog.h | 2 -- > hw/arm/armsse.c | 2 -- > hw/timer/cmsdk-apb-dualtimer.c | 6 ------ > hw/timer/cmsdk-apb-timer.c | 6 ------ > hw/watchdog/cmsdk-apb-watchdog.c | 6 ------ > 8 files changed, 28 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 21 17:13:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2iCd-0002vW-6v for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:13:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2iCS-0002u8-IM; Thu, 21 Jan 2021 17:13:09 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:46810) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2iCP-0001hs-Ak; Thu, 21 Jan 2021 17:13:07 -0500 Received: by mail-ej1-x635.google.com with SMTP id rv9so4828818ejb.13; Thu, 21 Jan 2021 14:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=lcpszUVkJpoXgMWaOzutK+jh7v2iR8cuwcMoxYzVo1E=; b=L98LJyHYhFsvHmexdj649+FSpfltU0XU1glqrASTfmpeJh6vvJCeDmWxhki2qR1j3B 7wUt8/le0Wd/fiasFA9nHLodqB8M/WtyQl9Tvnpj3aUFp5bWjBJCkcLy/BzztvBc0XPN wI3nQ9zCHNJhFWGae6Pk97wGXNPSjBBStbF/hOb/cduV1fEPtneaxNzFC00S3xIXSJo2 X5UaWYH+TXp1dX05XcuvmpPkX5kneiQEcJxp1Lb5o2gxIhApRKTEqvlP6kXfdp01d6I4 NjfZi8g1K3XvYCP49pMRtZXOkdbp1C4QheNyQCNXtbfP/Hk1b8Ug1yA/YuFRDmNP9Xwn NCTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=lcpszUVkJpoXgMWaOzutK+jh7v2iR8cuwcMoxYzVo1E=; b=byFrDlTD3ZKJKG3Z4BpU3lKJ5g4g6klkRkx3VAYfMujxTUZFvZ9tESf3gx5dwvMw7G lu/T2r++9UqHVVPkM3x2acJGobV1iJeBkwxLOr/Aa41566Nsh/9Mt8BUYBWfuH9sNj9Y Ol2ipmQErRLGkgKf+0kkVpsOMe61i9+KPgpEyUkqOog7TbYuhERhW8kqEG7ZmnW3wGez tVC0iO/chJ1kUImCsFbvkn3MM0wo0NsMALhiV4v7CEuTMLlCAEgkQRPk3PcveWVUa6NQ Z3YbHaPqmWcu55rZiieLVL/oKB+0aNwszRa5uz7PIdGCTGxEeo7P1AQVNVxV0KBDd2Y3 d/gQ== X-Gm-Message-State: AOAM530wUxl8Of62lZfb2nNaUd8u4gymCnXo+nLx2aAt9n2vIs42g5dN ObW8ykDKQpNzyrTyQTBX95g= X-Google-Smtp-Source: ABdhPJwBCRE3wG8drUy3DgWl7kWwpXwnWsW41Ri8vLnxRcyKnu2mPF3dr5P+0gj8JUGsl5HWGbYHEw== X-Received: by 2002:a17:906:95cf:: with SMTP id n15mr1082883ejy.178.1611267183507; Thu, 21 Jan 2021 14:13:03 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id hs18sm2758287ejc.45.2021.01.21.14.13.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:13:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-17-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 21 Jan 2021 23:13:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-17-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:13:09 -0000 Hi Peter, On 1/21/21 8:06 PM, Peter Maydell wrote: > Convert the SSYS code in the Stellaris boards (which encapsulates the > system registers) to a proper QOM device. This will provide us with > somewhere to put the output Clock whose frequency depends on the > setting of the PLL configuration registers. > > This is a migration compatibility break for lm3s811evb, lm3s6965evb. > > We use 3-phase reset here because the Clock will need to propagate > its value in the hold phase. > > For the moment we reset the device during the board creation so that > the system_clock_scale global gets set; this will be removed in a > subsequent commit. > > Signed-off-by: Peter Maydell > --- > hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 107 insertions(+), 25 deletions(-) > > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 652823195b1..0194ede2fe0 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp) > > /* System controller. */ > > -typedef struct { > +#define TYPE_STELLARIS_SYS "stellaris-sys" > +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) > + > +struct ssys_state { > + SysBusDevice parent_obj; > + > MemoryRegion iomem; > uint32_t pborctl; > uint32_t ldopctl; > @@ -371,11 +376,18 @@ typedef struct { > uint32_t dcgc[3]; > uint32_t clkvclr; > uint32_t ldoarst; > + qemu_irq irq; > + /* Properties (all read-only registers) */ > uint32_t user0; > uint32_t user1; > - qemu_irq irq; > - stellaris_board_info *board; > -} ssys_state; > + uint32_t did0; > + uint32_t did1; > + uint32_t dc0; > + uint32_t dc1; > + uint32_t dc2; > + uint32_t dc3; > + uint32_t dc4; Shouldn't these be class properties? > +}; From MAILER-DAEMON Thu Jan 21 17:15:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2iEJ-00040C-Fg for mharc-qemu-arm@gnu.org; Thu, 21 Jan 2021 17:15:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2iEB-0003vG-Tt; Thu, 21 Jan 2021 17:14:56 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:45611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2iE7-0002Df-58; Thu, 21 Jan 2021 17:14:54 -0500 Received: by mail-ed1-x531.google.com with SMTP id f1so4315201edr.12; Thu, 21 Jan 2021 14:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qhjvOrM3e9WjgJRCDQKUOvjbiN5WhZOEqeBHljKHNSU=; b=q/v3ynFARuvpvq1nERpaJvJ2gV9y/Kt5Iz07DZoTAPAyRhVV5DgNAwxRmzX8Ncvqi7 TQEYPNWNbn6wd+NSASa2TB4KPd1xY6fxirAYoXz+1byYSjhq6TyRff+QvA3z+9gCKrf5 XqRUVF1e6Mpg4CLF7P/dX5VdyjAihOjJz6NvJ6+YTlYNl1s/O6JuOdp/0g8q1ryqv22h 4Nj9AhDQhUeUFd7LgaHx98ESCZqB50RFJVOlOOia7bYiJATZfhdPYphzGZiLoesI2cVI 5T8FnUTm66ELUbl/EMZ0wzkCIMN457avE82bYGX8gjX5yKhnbRSajs19Et1I7mx8pOkD ZD3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qhjvOrM3e9WjgJRCDQKUOvjbiN5WhZOEqeBHljKHNSU=; b=V1zL1dwqnzUiatk+XxyzagdXr+f6kN6XxU6agW9miQIe0/1dFYZ7CwXDBW42YxXgMr 4ER+EF3eMc/z3VfRQFJJihX2T64BDVy7pqBwGSGs5s4h9qWZ0FSm5/1zwU+pLJQ1VJJZ JqHu3H0gGFVO+5L6hZVF2J8Ar3a8ULsj3MtloFR5sPPa9ETBQPpUdk2lB3uAbFErfreJ ybjUVbUqgNr7hHUWu68oNh/RmVLHTgSc3hJeTcPRbc0VS64ILq7C8UhDB1pHYDzbgWjP lh4OABxQH/z+hUhRfTI3X9gtn2FsmqiPCQvWugaTwuTR2PxP/qTv34dVEJrgzLPZN/hA VtnQ== X-Gm-Message-State: AOAM530/IshhzLT2DTUgqVzezS2+HW459E5Fan9s1dwM/LrLfsI9nv+s 1DAqbuWhFfXzj3XPW+hCvAFYryLGkw8= X-Google-Smtp-Source: ABdhPJw014kunSy5i4iRsQVc1qQbDDIVHuglpYnMpSS6jeAQIEvvF+FJx2K57ZIOq3nHn62uG5qmRw== X-Received: by 2002:a05:6402:1819:: with SMTP id g25mr971654edy.46.1611267289051; Thu, 21 Jan 2021 14:14:49 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id r22sm3596005edp.9.2021.01.21.14.14.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jan 2021 14:14:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-13-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <75d9c510-9bba-1eff-c442-bca862c3d7e7@amsat.org> Date: Thu, 21 Jan 2021 23:14:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-13-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2021 22:15:01 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > The old-style convenience function cmsdk_apb_timer_create() for > creating CMSDK_APB_TIMER objects is used in only two places in > mps2.c. Most of the rest of the code in that file uses the new > "initialize in place" coding style. > > We want to connect up a Clock object which should be done between the > object creation and realization; rather than adding a Clock* argument > to the convenience function, convert the timer creation code in > mps2.c to the same style as is used already for the watchdog, > dualtimer and other devices, and delete the now-unused convenience > function. > > Signed-off-by: Peter Maydell > --- > include/hw/timer/cmsdk-apb-timer.h | 21 --------------------- > hw/arm/mps2.c | 18 ++++++++++++++++-- > 2 files changed, 16 insertions(+), 23 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Fri Jan 22 03:07:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2rTc-0007kU-4T for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 03:07:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2rTZ-0007kM-SO for qemu-arm@nongnu.org; Fri, 22 Jan 2021 03:07:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:36062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l2rTX-0001AE-C1 for qemu-arm@nongnu.org; Fri, 22 Jan 2021 03:07:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611302842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wceigeWi447uFqqOJBTYIF2O1oO/W+rRjQCaPdz1EqM=; b=fW7GrR+6C4YVWeIqdKqCgj55ZujYSUB/+tl640rS8WOwvvOLzRo0R2ZHxUPxbiZZNkBcZS 9P67KxMtGm/f1nMQJRyfPM6nnYLfDjJShT91MLrBVUij/EZ9DfQJ9wAXBLOnvLyEqrqjke hgywAiHn29dsk6qGIUT9nHmqqvtcL7I= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-327-pqCwM7fwNsuwkhRTXI3Ppg-1; Fri, 22 Jan 2021 03:07:18 -0500 X-MC-Unique: pqCwM7fwNsuwkhRTXI3Ppg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 353AC15725; Fri, 22 Jan 2021 08:07:17 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.40.192.139]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E430A2C6BF; Fri, 22 Jan 2021 08:07:14 +0000 (UTC) Date: Fri, 22 Jan 2021 09:07:12 +0100 From: Andrew Jones To: Maxim Uvarov Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, Jose.Marinho@arm.com, f4bug@amsat.org, tf-a@lists.trustedfirmware.org Subject: Re: [PATCHv8 2/3] arm-virt: refactor gpios creation Message-ID: <20210122080712.bwkjyyanwdv22eqd@kamzik.brq.redhat.com> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> <20210120092748.14789-3-maxim.uvarov@linaro.org> MIME-Version: 1.0 In-Reply-To: <20210120092748.14789-3-maxim.uvarov@linaro.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.168, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 08:07:26 -0000 On Wed, Jan 20, 2021 at 12:27:47PM +0300, Maxim Uvarov wrote: > No functional change. Just refactor code to better > support secure and normal world gpios. > > Signed-off-by: Maxim Uvarov > --- > hw/arm/virt.c | 64 ++++++++++++++++++++++++++++++++++----------------- > 1 file changed, 43 insertions(+), 21 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 96985917d3..c427ce5f81 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -820,17 +820,43 @@ static void virt_powerdown_req(Notifier *n, void *opaque) > } > } > > -static void create_gpio(const VirtMachineState *vms) > +static void create_gpio_keys(const VirtMachineState *vms, > + DeviceState *pl061_dev, > + uint32_t phandle) > +{ > + gpio_key_dev = sysbus_create_simple("gpio-key", -1, > + qdev_get_gpio_in(pl061_dev, 3)); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", > + "label", "GPIO Key Poweroff"); > + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", > + KEY_POWER); > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", > + "gpios", phandle, 3, 0); > +} > + > +static void create_gpio_devices(const VirtMachineState *vms, int gpio, > + MemoryRegion *mem) > { > char *nodename; > DeviceState *pl061_dev; > - hwaddr base = vms->memmap[VIRT_GPIO].base; > - hwaddr size = vms->memmap[VIRT_GPIO].size; > - int irq = vms->irqmap[VIRT_GPIO]; > + hwaddr base = vms->memmap[gpio].base; > + hwaddr size = vms->memmap[gpio].size; > + int irq = vms->irqmap[gpio]; > const char compat[] = "arm,pl061\0arm,primecell"; > + SysBusDevice *s; > > - pl061_dev = sysbus_create_simple("pl061", base, > - qdev_get_gpio_in(vms->gic, irq)); > + pl061_dev = qdev_new("pl061"); > + s = SYS_BUS_DEVICE(pl061_dev); > + sysbus_realize_and_unref(s, &error_fatal); > + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); > + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); > > uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); > nodename = g_strdup_printf("/pl061@%" PRIx64, base); > @@ -847,21 +873,17 @@ static void create_gpio(const VirtMachineState *vms) > qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); > qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); > > - gpio_key_dev = sysbus_create_simple("gpio-key", -1, > - qdev_get_gpio_in(pl061_dev, 3)); > - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); > - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); > - > - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); > - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", > - "label", "GPIO Key Poweroff"); > - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", > - KEY_POWER); > - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", > - "gpios", phandle, 3, 0); > + if (gpio != VIRT_GPIO) { > + /* Mark as not usable by the normal world */ > + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); > + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); > + } nit: The above if-block could/should have waited until the next patch to be added. > g_free(nodename); > + > + /* Child gpio devices */ > + if (gpio == VIRT_GPIO) { Same nit as above, the next patch is where we should start conditionally doing stuff based on the gpio type. > + create_gpio_keys(vms, pl061_dev, phandle); > + } > } > > static void create_virtio_devices(const VirtMachineState *vms) > @@ -1990,7 +2012,7 @@ static void machvirt_init(MachineState *machine) > if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { > vms->acpi_dev = create_acpi_ged(vms); > } else { > - create_gpio(vms); > + create_gpio_devices(vms, VIRT_GPIO, sysmem); > } > > /* connect powerdown request */ > -- > 2.17.1 > > Reviewed-by: Andrew Jones Thanks, drew From MAILER-DAEMON Fri Jan 22 03:29:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2rp7-000454-W2 for mharc-qemu-arm@gnu.org; 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Fri, 22 Jan 2021 03:29:32 -0500 X-MC-Unique: hKc6mSqzPQKW8fmtGzvBdA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7B0CF1005504; Fri, 22 Jan 2021 08:29:31 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.40.192.139]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7386D5D9E8; Fri, 22 Jan 2021 08:29:29 +0000 (UTC) Date: Fri, 22 Jan 2021 09:29:26 +0100 From: Andrew Jones To: Maxim Uvarov Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, Jose.Marinho@arm.com, f4bug@amsat.org, tf-a@lists.trustedfirmware.org Subject: Re: [PATCHv8 3/3] arm-virt: add secure pl061 for reset/power down Message-ID: <20210122082926.nakttrh53zzt6d2x@kamzik.brq.redhat.com> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> <20210120092748.14789-4-maxim.uvarov@linaro.org> MIME-Version: 1.0 In-Reply-To: <20210120092748.14789-4-maxim.uvarov@linaro.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.168, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 08:29:40 -0000 On Wed, Jan 20, 2021 at 12:27:48PM +0300, Maxim Uvarov wrote: > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). Connect it > with gpio-pwr driver. > > Signed-off-by: Maxim Uvarov > --- > hw/arm/Kconfig | 1 + > hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++++ > include/hw/arm/virt.h | 2 ++ > 3 files changed, 50 insertions(+) > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 0a242e4c5d..13cc42dcc8 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -17,6 +17,7 @@ config ARM_VIRT > select PL011 # UART > select PL031 # RTC > select PL061 # GPIO > + select GPIO_PWR > select PLATFORM_BUS > select SMBIOS > select VIRTIO_MMIO > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index c427ce5f81..060a5f492e 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { > [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, > [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, > [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, > + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ > [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, > @@ -841,6 +842,43 @@ static void create_gpio_keys(const VirtMachineState *vms, > "gpios", phandle, 3, 0); > } > > +#define SECURE_GPIO_POWEROFF 0 > +#define SECURE_GPIO_REBOOT 1 > + > +static void create_gpio_pwr(const VirtMachineState *vms, This function is specific to the secure view. I think it should have "secure" in its name. > + DeviceState *pl061_dev, > + uint32_t phandle) > +{ > + DeviceState *gpio_pwr_dev; > + > + /* gpio-pwr */ > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); Should this device be in secure memory? > + > + /* connect secure pl061 to gpio-pwr */ > + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_REBOOT, > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, > + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-poweroff"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "compatible", > + "gpio-poweroff"); > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-poweroff", > + "gpios", phandle, SECURE_GPIO_POWEROFF, 0); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "status", "disabled"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "secure-status", > + "okay"); > + > + qemu_fdt_add_subnode(vms->fdt, "/gpio-restart"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "compatible", > + "gpio-restart"); > + qemu_fdt_setprop_cells(vms->fdt, "/gpio-restart", > + "gpios", phandle, SECURE_GPIO_REBOOT, 0); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "status", "disabled"); > + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "secure-status", > + "okay"); > +} > + > static void create_gpio_devices(const VirtMachineState *vms, int gpio, > MemoryRegion *mem) > { > @@ -883,6 +921,8 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio, > /* Child gpio devices */ > if (gpio == VIRT_GPIO) { > create_gpio_keys(vms, pl061_dev, phandle); > + } else { > + create_gpio_pwr(vms, pl061_dev, phandle); > } > } > > @@ -2015,6 +2055,10 @@ static void machvirt_init(MachineState *machine) > create_gpio_devices(vms, VIRT_GPIO, sysmem); > } > > + if (vms->secure && !vmc->no_secure_gpio) { > + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); > + } > + > /* connect powerdown request */ > vms->powerdown_notifier.notify = virt_powerdown_req; > qemu_register_powerdown_notifier(&vms->powerdown_notifier); > @@ -2630,8 +2674,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) > > static void virt_machine_5_2_options(MachineClass *mc) > { > + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); > + > virt_machine_6_0_options(mc); > compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); > + vmc->no_secure_gpio = true; > } > DEFINE_VIRT_MACHINE(5, 2) > > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h > index abf54fab49..6f6c85ffcf 100644 > --- a/include/hw/arm/virt.h > +++ b/include/hw/arm/virt.h > @@ -81,6 +81,7 @@ enum { > VIRT_GPIO, > VIRT_SECURE_UART, > VIRT_SECURE_MEM, > + VIRT_SECURE_GPIO, > VIRT_PCDIMM_ACPI, > VIRT_ACPI_GED, > VIRT_NVDIMM_ACPI, > @@ -127,6 +128,7 @@ struct VirtMachineClass { > bool kvm_no_adjvtime; > bool no_kvm_steal_time; > bool acpi_expose_flash; > + bool no_secure_gpio; > }; > > struct VirtMachineState { > -- > 2.17.1 > > Thanks, drew From MAILER-DAEMON Fri Jan 22 05:09:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2tO9-0001ea-68 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 05:09:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2tO7-0001eE-8K for qemu-arm@nongnu.org; Fri, 22 Jan 2021 05:09:55 -0500 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]:42466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2tO0-0007Jw-Jy for qemu-arm@nongnu.org; Fri, 22 Jan 2021 05:09:54 -0500 Received: by mail-ed1-x52e.google.com with SMTP id g24so5856711edw.9 for ; Fri, 22 Jan 2021 02:09:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pz2BAK6BIJ0piLML6OEwXDhTyZhnyFCBijcWaayNwTw=; b=GDqPPUaGRBwC+bua0rI+yw+HOo+xic4uGmAJlkVX/61KhXdLo1GNnCARcLFqIrCItV 2huGAxPDXyfoIvHLtIH2gKv4UHIqs30Qg0u7sUSVWf0+rzxyNDSqOhu3Rpl9gCnVcxM3 wkCnXMv9KPERY8Y2JUra3/Kbyyj3kqCwt+enj9fUEGHgtB5sudI03fqYX/uduHxr8aKx s054lDY0Fro6e/pJEkssf/mXV7vCVBn4Y0NtTRH4kaL6eGGtTztOtCkaeKaWixdTOWZZ L6RdaabxerBfsF9k0CN/CEZSFzHKSOVJlnuErer+XFQNDnmoMUnDTvwMbGt2pyYRWmL3 WIkw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 10:09:55 -0000 On Fri, 22 Jan 2021 at 08:29, Andrew Jones wrote: > > On Wed, Jan 20, 2021 at 12:27:48PM +0300, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > > the secure world (Arm Trusted Firmware). Connect it > > with gpio-pwr driver. > > > > Signed-off-by: Maxim Uvarov > > --- > > hw/arm/Kconfig | 1 + > > hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++++ > > include/hw/arm/virt.h | 2 ++ > > 3 files changed, 50 insertions(+) > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index 0a242e4c5d..13cc42dcc8 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -17,6 +17,7 @@ config ARM_VIRT > > select PL011 # UART > > select PL031 # RTC > > select PL061 # GPIO > > + select GPIO_PWR > > select PLATFORM_BUS > > select SMBIOS > > select VIRTIO_MMIO > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > > index c427ce5f81..060a5f492e 100644 > > --- a/hw/arm/virt.c > > +++ b/hw/arm/virt.c > > @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { > > [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, > > [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, > > [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, > > + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ > > [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, > > @@ -841,6 +842,43 @@ static void create_gpio_keys(const VirtMachineState *vms, > > "gpios", phandle, 3, 0); > > } > > > > +#define SECURE_GPIO_POWEROFF 0 > > +#define SECURE_GPIO_REBOOT 1 > > + > > +static void create_gpio_pwr(const VirtMachineState *vms, > > This function is specific to the secure view. I think it should have > "secure" in its name. > > > + DeviceState *pl061_dev, > > + uint32_t phandle) > > +{ > > + DeviceState *gpio_pwr_dev; > > + > > + /* gpio-pwr */ > > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); > > Should this device be in secure memory? It's not in any memory at all -- -1 as the address argument to sysbus_create_simple() means "no MMIO regions to map". The only way it's connected to the rest of the system is via the secure-only PL061, so the NS world can't get at it. (sysbus_create_simple("device", -1, NULL) is equivalent to: dev = qdev_new("device"); sysbus_realize_and_unref(SYSBUS_DEVICE(dev), &error_fatal); ) thanks -- PMM From MAILER-DAEMON Fri Jan 22 05:17:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2tVj-000515-Ag for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 05:17:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2tVh-0004xe-CD for qemu-arm@nongnu.org; Fri, 22 Jan 2021 05:17:45 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:43922) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l2tVe-0001zE-G9 for qemu-arm@nongnu.org; Fri, 22 Jan 2021 05:17:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611310661; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=uOGq1pf/oSqwehpeVVjmz839Z/VDxUSKqGp7ob3DT14=; b=UwvyV/53oAhfL6wrHD4bqqZmVa140i16sOUN9jaA5JtURig/pexsw/vKbFiHpc58SLMnRK 4GwpHA6COYPLI5UExN4CgsFfZr9dGDGLhj6Y9rRjpOELq/Ed3IxWwHTev+giGzk9wFvnSz sBl7OgJhv7nXXJ3FUb5LUtAWaiIdKbY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-597-8qABLODOOv-w0fch2GHv6Q-1; Fri, 22 Jan 2021 05:17:39 -0500 X-MC-Unique: 8qABLODOOv-w0fch2GHv6Q-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9D448107ACE3; Fri, 22 Jan 2021 10:17:32 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.40.192.139]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 70CAF19C59; Fri, 22 Jan 2021 10:17:30 +0000 (UTC) Date: Fri, 22 Jan 2021 11:17:27 +0100 From: Andrew Jones To: Peter Maydell Cc: Maxim Uvarov , qemu-arm , QEMU Developers , Jose Marinho , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , tf-a@lists.trustedfirmware.org Subject: Re: [PATCHv8 3/3] arm-virt: add secure pl061 for reset/power down Message-ID: <20210122101727.6sf6x6wrpjwo2h34@kamzik.brq.redhat.com> References: <20210120092748.14789-1-maxim.uvarov@linaro.org> <20210120092748.14789-4-maxim.uvarov@linaro.org> <20210122082926.nakttrh53zzt6d2x@kamzik.brq.redhat.com> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.168, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 10:17:45 -0000 On Fri, Jan 22, 2021 at 10:09:35AM +0000, Peter Maydell wrote: > On Fri, 22 Jan 2021 at 08:29, Andrew Jones wrote: > > > > On Wed, Jan 20, 2021 at 12:27:48PM +0300, Maxim Uvarov wrote: > > > Add secure pl061 for reset/power down machine from > > > the secure world (Arm Trusted Firmware). Connect it > > > with gpio-pwr driver. > > > > > > Signed-off-by: Maxim Uvarov > > > --- > > > hw/arm/Kconfig | 1 + > > > hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++++ > > > include/hw/arm/virt.h | 2 ++ > > > 3 files changed, 50 insertions(+) > > > > > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > > index 0a242e4c5d..13cc42dcc8 100644 > > > --- a/hw/arm/Kconfig > > > +++ b/hw/arm/Kconfig > > > @@ -17,6 +17,7 @@ config ARM_VIRT > > > select PL011 # UART > > > select PL031 # RTC > > > select PL061 # GPIO > > > + select GPIO_PWR > > > select PLATFORM_BUS > > > select SMBIOS > > > select VIRTIO_MMIO > > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > > > index c427ce5f81..060a5f492e 100644 > > > --- a/hw/arm/virt.c > > > +++ b/hw/arm/virt.c > > > @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { > > > [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, > > > [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, > > > [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, > > > + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, > > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > > /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ > > > [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, > > > @@ -841,6 +842,43 @@ static void create_gpio_keys(const VirtMachineState *vms, > > > "gpios", phandle, 3, 0); > > > } > > > > > > +#define SECURE_GPIO_POWEROFF 0 > > > +#define SECURE_GPIO_REBOOT 1 > > > + > > > +static void create_gpio_pwr(const VirtMachineState *vms, > > > > This function is specific to the secure view. I think it should have > > "secure" in its name. > > > > > + DeviceState *pl061_dev, > > > + uint32_t phandle) > > > +{ > > > + DeviceState *gpio_pwr_dev; > > > + > > > + /* gpio-pwr */ > > > + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); > > > > Should this device be in secure memory? > > It's not in any memory at all -- -1 as the address argument > to sysbus_create_simple() means "no MMIO regions to map". The > only way it's connected to the rest of the system is via the > secure-only PL061, so the NS world can't get at it. > > (sysbus_create_simple("device", -1, NULL) is equivalent to: > dev = qdev_new("device"); > sysbus_realize_and_unref(SYSBUS_DEVICE(dev), &error_fatal); > ) > Thanks, I should have looked more closely at that. With the function name change to include "secure". Reviewed-by: Andrew Jones From MAILER-DAEMON Fri Jan 22 06:37:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2ukX-0001iZ-Kf for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 06:37:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2ukW-0001g6-7j for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:37:08 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:32913) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2ukU-0004c9-Gf for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:37:07 -0500 Received: by mail-ej1-x635.google.com with SMTP id by1so7236101ejc.0 for ; Fri, 22 Jan 2021 03:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yRxDPann/7bwjlu5VchBcHrH73lxDT9XO/l8WhnUvYw=; b=ZEC+LFyIQ1iO/c7vKx9FTIDNAs4CN/joYZLsdhGwH1xo6py6brkEr6NLc/h0lwhNAs vE56lDyloVQLII4d8cqnzkG/aGkt9AXSyKVCE5hnEK30LHD6Dn9MTOD97GG0pRyavPYa 6+r2t87dcfCLnIiHVQxsO+bJ3DEuwHeEK0SSxJ0e0gVP8L7mmPFtqyVy2yHzkwhjQnBH goUrUHTMtqwVbhYvHyXDztdxqUbTALJR+Ke9dICGpezB5fOJagWWrBjrsv9zuB7JgpEy biq1USvQhiduRD6DpD7az3ZGy2aEELKAYC3RIfkeUx9PqgC9+ALU2YCsMFAoBdp2fvVF 2gcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yRxDPann/7bwjlu5VchBcHrH73lxDT9XO/l8WhnUvYw=; b=HGz5lpKyy5orM/nRd3K7bZHwzIGXq3+yQfK6L+M5hXpVBdURU2KyzxLH//k8r2GZsN TIpxeZodQhi8M3bj8w5Lh34O4Tkk+R9de3OjGqPYydTsaM/ffzJWJ9UJn+P3Ehpul2AZ fATc2zHPIHxhAlOzMRNnGsRqmvytykp/L9jVbmmFuyFHZOFWz5inhFnln+Ct5w2sjCUi QVYDUqO62x3+W/wZOXJE/v56UfjvFYVYqAeHY8CBJ4esrzsqihlyQXmOQSIrsfMsP0fl QE/OQ/mv/J04+n2oUGTLuHxEqd6CL8MTrHROSSmEE/F87OIy+Jdfkn6OjujAQPtiOdbJ CXRQ== X-Gm-Message-State: AOAM533Yza9l2U/1omgtkrENxnotRJE517o74qu40uiolOij+5pKyJU7 zcVLQLM/gcc9xKZWPo3zNBzqmM9UE502G6GZAZz/HQ== X-Google-Smtp-Source: ABdhPJzM6UtkSjJEQq5NFGyFeOyEtDowtAVAVkT72+Elklzzo7n97iukWMZ1dIj2nZ3T8VZ3d0YnDFDLvMf5Q1Q7xn0= X-Received: by 2002:a17:906:494c:: with SMTP id f12mr2787100ejt.56.1611315424620; Fri, 22 Jan 2021 03:37:04 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-13-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-13-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 11:36:53 +0000 Message-ID: Subject: Re: [PATCH v3 12/21] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 11:37:08 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > This is the prctl bit that controls whether syscalls accept tagged > addresses. See Documentation/arm64/tagged-address-abi.rst in the > linux kernel. > > Signed-off-by: Richard Henderson > --- > linux-user/aarch64/target_syscall.h | 4 ++++ > target/arm/cpu-param.h | 3 +++ > target/arm/cpu.h | 23 +++++++++++++++++++++++ > linux-user/syscall.c | 25 +++++++++++++++++++++++++ > target/arm/cpu.c | 3 +++ > 5 files changed, 58 insertions(+) > > diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h > index 3194e6b009..820601dfcc 100644 > --- a/linux-user/aarch64/target_syscall.h > +++ b/linux-user/aarch64/target_syscall.h > @@ -30,4 +30,8 @@ struct target_pt_regs { > # define TARGET_PR_PAC_APDBKEY (1 << 3) > # define TARGET_PR_PAC_APGAKEY (1 << 4) > > +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 > +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 > +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) Stray extra space. Otherwise Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 06:49:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2uw5-0005Wr-Lv for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 06:49:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2uw1-0005VX-5y for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:49:02 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:35814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2uvy-0001eY-4B for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:49:00 -0500 Received: by mail-ej1-x635.google.com with SMTP id ox12so7288642ejb.2 for ; Fri, 22 Jan 2021 03:48:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=da1D08BSFwrFl+/DOs3EwV7BlyBgYJnhBZVQpyydfnM=; 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Fri, 22 Jan 2021 03:48:56 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-14-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-14-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 11:48:45 +0000 Message-ID: Subject: Re: [PATCH v3 13/21] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 11:49:03 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > These prctl fields are required for the function of MTE. > > Signed-off-by: Richard Henderson > --- > linux-user/aarch64/target_syscall.h | 9 ++++++ > linux-user/syscall.c | 44 +++++++++++++++++++++++++++++ > 2 files changed, 53 insertions(+) > > diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h > index 820601dfcc..76f6c3391d 100644 > --- a/linux-user/aarch64/target_syscall.h > +++ b/linux-user/aarch64/target_syscall.h > @@ -33,5 +33,14 @@ struct target_pt_regs { > #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 > #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 > # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) > +/* MTE tag check fault modes */ > +# define TARGET_PR_MTE_TCF_SHIFT 1 > +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) > +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) > +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) > +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) > +/* MTE tag inclusion mask */ > +# define TARGET_PR_MTE_TAG_SHIFT 3 > +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 06:53:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2v0H-0000aj-QY for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 06:53:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2v0H-0000Zw-3s for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:53:25 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:36656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2v0F-0003gD-DI for qemu-arm@nongnu.org; Fri, 22 Jan 2021 06:53:24 -0500 Received: by mail-ej1-x629.google.com with SMTP id l9so7280545ejx.3 for ; Fri, 22 Jan 2021 03:53:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=S/niuOmXyqXBJZ6gv5bg6OJguEBxsoTsFEx93XPe4cU=; b=FuA93NIt3+g1bPxHi0uu4mi5HiFXM3ff9lfAGMTU+Q0jvUCQ6iwn0rY1PTjutH7kil tt83YYGdOA8tjS3AFeLWrzW3rPQhuRLuq76Av7gI9x2yxLul2MrhInTfkY0TUHSJSFir 6vDeMIRNySsI1SFEGXS4oq5thKkgredcSnLF9orfUghc63Pe/jyXf1Z3GJ5JZiqLCdyv qLADIpZuYS4hOEYgJf+9tuM3rZ0hRyj+uRdXW7xFNOA9vu95CSxltoFTEC48hWSN4icT fXqJb9L2N8gR5HhI1XeX4+OUO+228UBpqC4zQsaenoiD4aJiOjBbfJydmiCdKJLsb6Bd 9+mw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 11:53:25 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > This is the prctl bit that controls whether syscalls accept tagged > addresses. See Documentation/arm64/tagged-address-abi.rst in the > linux kernel. > +#ifdef TARGET_TAGGED_ADDRESSES > +/** > + * cpu_untagged_addr: > + * @cs: CPU context > + * @x: tagged address > + * > + * Remove any address tag from @x. This is explicitly related to the > + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. > + * > + * There should be a better place to put this, but we need this in > + * include/exec/cpu_ldst.h, and not some place linux-user specific. > + */ > +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + return x & cpu->env.untagged_addr_mask; > +} > +#endif Forgot to mention: this only does the right thing on addresses in the lower half of the address space. I guess that's mostly OK for our purposes? It probably means that if a guest program deliberately dereferences a bad address in the top half of the address space we'll report the wrong (ie different to what a real kernel reports) address value to it in the SEGV signal handler. The kernel's "untagged_addr()" implementation: https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/memory.h#L203 slightly confusingly does "untag the addr if it's in the userspace half, leave the tag bits alone if in the kernel half". thanks -- PMM From MAILER-DAEMON Fri Jan 22 07:02:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2v8x-0005Dt-Tg for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 07:02:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2v8v-0005C7-VQ for qemu-arm@nongnu.org; Fri, 22 Jan 2021 07:02:21 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:38931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2v8u-0007ci-50 for qemu-arm@nongnu.org; Fri, 22 Jan 2021 07:02:21 -0500 Received: by mail-ed1-x530.google.com with SMTP id b21so6248013edy.6 for ; Fri, 22 Jan 2021 04:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NTZPY6WkVFpXEUfb1dEykbGXS9p/chRYJl8UuYW5kC4=; b=nHlen25YPrzO7A3I+8QFk9oxK74aiFK1fi2sWtxk4fVvLEM03YTomS+bcomz1Y5uc8 mXaXn5Xkrovo1bRvattmUBirk6S8Hb+6/iTrntBrCrIBVY7yxo+OqTzet/RXT/CGD4AD H27bFjOgbhEO7yK1xXFkAFInNyQ18yVdHswdKyHpYDPN+X1HEA8dvf8IOTzNCdmnRFj2 21lyzp86AgdO1hgWpPbbmZEfoO92xSIe0YuIR2L6vdbydEyYyxpfwnbf0qJY4A9eeziO zrmBuNAVdtLvWxAYoGsWj1OkMD8+JeQCQ7phP7T+lNg7zLkng6okR2uM2y1efIAw2l9v 3d6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NTZPY6WkVFpXEUfb1dEykbGXS9p/chRYJl8UuYW5kC4=; b=TEokfO/lnN8KzpYxF0Klq9qcdRAthAf+qgwOpodNIOmmQ70MqX8sdpmaELz/VaE+Pm /vx0WMM2K2KJVXR6/B2ugSduNGclS0WSu6ja3TqX+Aj8a94rMM6sbvcAkE9OjvqZuyOz 0x0TCmQKf8YgFZ6sfB7ujiELrpzDl58OUrznX6gnIO9Kuv88IU4T3eQychcRG3/rt9FW EBYCqSSVgT1/ihJkqI2PUeVT2IhFjyZj9NdwbDC3phz1NsuIs5idDzoXPQ4pMFvDgXxY nPwGQCQ8vcOfqkqVfpTSRKxIwB6lu0qWOO1qRfA80BxRfBXKMuVAr5epUYYlnocAw0Fx dVEg== X-Gm-Message-State: AOAM532sNTEiM/+wgQ1PqbwOaIZFw291f1WtaFPs2WF6hi08Cqea8QOF 52TANmwcGpsIDQWTtc4pFFhRZvLBpTbWkzdztC/wnA== X-Google-Smtp-Source: ABdhPJxA2aD7GFCHyW38XcARuxaJPdqPOWUhMNb81VfjMO/FwdwMBpuCnTOidL4SvScN+Nz31/J05c01yLDZ9J17vx4= X-Received: by 2002:a05:6402:31ac:: with SMTP id dj12mr2886276edb.44.1611316938439; Fri, 22 Jan 2021 04:02:18 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-13-richard.henderson@linaro.org> In-Reply-To: From: Peter Maydell Date: Fri, 22 Jan 2021 12:02:07 +0000 Message-ID: Subject: Re: [PATCH v3 12/21] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 12:02:22 -0000 On Fri, 22 Jan 2021 at 11:53, Peter Maydell wrote: > The kernel's "untagged_addr()" implementation: > https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/memory.h#L203 > slightly confusingly does "untag the addr if it's in the userspace > half, leave the tag bits alone if in the kernel half". ...and a kernel person has just explained to me the rationale: TBI is always enabled for userspace and never for the kernel, so "always clear tag bits for a userspace address, never clear them for a kernel address" is the right behaviour. I think we should have the same logic. -- PMM From MAILER-DAEMON Fri Jan 22 07:03:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2vAG-0006ZT-Cw for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 07:03:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2vAE-0006XU-Lh for qemu-arm@nongnu.org; Fri, 22 Jan 2021 07:03:42 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]:37397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2vAD-0008Av-7d for qemu-arm@nongnu.org; Fri, 22 Jan 2021 07:03:42 -0500 Received: by mail-ej1-x632.google.com with SMTP id kg20so6830102ejc.4 for ; Fri, 22 Jan 2021 04:03:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=n+Ij7T8O3IU04/0swRAjJER9rbY3TfzLGvMT8dFj48k=; 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Fri, 22 Jan 2021 04:03:39 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-18-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-18-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 12:03:28 +0000 Message-ID: Subject: Re: [PATCH v3 17/21] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 12:03:42 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > linux-user/aarch64/target_signal.h | 2 ++ > linux-user/aarch64/cpu_loop.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h > index ddd73169f0..777fb667fe 100644 > --- a/linux-user/aarch64/target_signal.h > +++ b/linux-user/aarch64/target_signal.h > @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { > > #include "../generic/signal.h" > > +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ > + > #define TARGET_ARCH_HAS_SETUP_FRAME > #endif /* AARCH64_TARGET_SIGNAL_H */ > diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c > index 7811440c68..6867f0db2b 100644 > --- a/linux-user/aarch64/cpu_loop.c > +++ b/linux-user/aarch64/cpu_loop.c > @@ -133,6 +133,9 @@ void cpu_loop(CPUARMState *env) > case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ > info.si_code = TARGET_SEGV_ACCERR; > break; > + case 0x11: /* Synchronous Tag Check Fault */ > + info.si_code = TARGET_SEGV_MTESERR; > + break; > default: > g_assert_not_reached(); > } > -- > 2.25.1 Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 08:36:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2wcJ-0007kx-TJ for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 08:36:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2wcI-0007iu-NA; Fri, 22 Jan 2021 08:36:46 -0500 Received: from mail-yb1-xb2f.google.com ([2607:f8b0:4864:20::b2f]:44753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2wcG-0007jI-Sw; Fri, 22 Jan 2021 08:36:46 -0500 Received: by mail-yb1-xb2f.google.com with SMTP id x78so5435615ybe.11; Fri, 22 Jan 2021 05:36:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; 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Fri, 22 Jan 2021 05:36:43 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> From: Bin Meng Date: Fri, 22 Jan 2021 21:36:28 +0800 Message-ID: Subject: Re: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2f; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 13:36:47 -0000 On Tue, Jan 19, 2021 at 9:40 PM Bin Meng wrote: > > From: Bin Meng > > This v8 series is based on the following 2 versions: > > - v5 series sent from Bin > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 > - v7 series sent from Philippe > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 > > This series fixes a bunch of bugs in current implementation of the imx > spi controller, including the following issues: > > - remove imx_spi_update_irq() in imx_spi_reset() > - chip select signal was not lower down when spi controller is disabled > - round up the tx burst length to be multiple of 8 > - transfer incorrect data when the burst length is larger than 32 bit > - spi controller tx and rx fifo endianness is incorrect > - remove pointless variable (s->burst_length) initialization (Philippe) > - rework imx_spi_reset() to keep CONREG register value (Philippe) > - rework imx_spi_read() to handle block disabled (Philippe) > - rework imx_spi_write() to handle block disabled (Philippe) > > Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 > (interrupt mode). > > Changes in v8: > - keep the controller disable logic in the ECSPI_CONREG case > in imx_spi_write() Ping? From MAILER-DAEMON Fri Jan 22 08:59:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2wyc-0004kL-GE for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 08:59:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2wya-0004jz-RY for qemu-arm@nongnu.org; Fri, 22 Jan 2021 08:59:48 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:44100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2wyY-0001C1-Rz for qemu-arm@nongnu.org; Fri, 22 Jan 2021 08:59:48 -0500 Received: by mail-ed1-x52f.google.com with SMTP id c2so6386514edr.11 for ; Fri, 22 Jan 2021 05:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=avzrptPOJ9pgDyMN2OCjX1Y5GkkZ4pXRJNWy+8IWXbE=; b=dR9lxxpjEsubN6nd4IqwAhNCehatGst/oAI2rtWgvY+AEFstBBC7Ci6ctLIBx7DNIc oZVtmsVY/zZnC+dIbmr473dmF6Q6+NEIqsVCIdIjKhXWAau3wFazEhEAN29KAUunQGcl o/KQWopwWXniyD8L3gpsTBTWMclojVp8B4OjK+HPuVinxiq8Lql3ml6ieYdhgKdyLcv2 7ERXkG1joHYQboxMeEarLKsMAOSrs9I5dQFlJpyzk1poWIsgMuRNj/MhtIkZ/SynHDIh 7s6X4y7yyeQ1Fqw2/JHRZskwL9d48qtAjoo12cKZJ40q3+X8w9OGZYHRq50T2LFEZdne Q75g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=avzrptPOJ9pgDyMN2OCjX1Y5GkkZ4pXRJNWy+8IWXbE=; b=CTBXq38HnCjezKqGiwSq8rWmo8Ct6tGpUv5eba8EDxnMdP+otHxnsrqsuxY778X8cJ oCKpMyEPW7czAPjUHH5eW5ECV209CV6Z1fPJTrkwlNFhgEBvDomYdE8qO0ZzHLC5gPwI WPcasji2ODol4aGZMU25QqWh0ImqaFpcvkbrYsAV/v7SdboXuKcQmpz5mNHLeALuQEKG ARGTOcS8N4SGPyKS4cy2i4dndavEsMlf2/+DYa+2i/aNgB7pwEX70D9k+9shQab5NQY4 R7caDJUHeqdydI/vaX1xgaZTnKkeTo2dlq+ZgArxLeJhAeMTZvfNj42nxXAIZUvvwi5F jpjA== X-Gm-Message-State: AOAM5327WGPGdbT/e7qUlzY/wPghtihctewZ7BgIfKqBYjdI1iCL8Tqf YzKr0CeRmgZ5j07AxOHECHyz5mCIHavBH3YrpmMEhQ== X-Google-Smtp-Source: ABdhPJyhUVv6OJcolVzJdjL+VtbuagdM86d33CUryyFoBL3CDq6sUzm+FkLMoJoYALBs07SOVvedFNqFDO8zdP7qJBA= X-Received: by 2002:a05:6402:31ac:: with SMTP id dj12mr3253164edb.44.1611323985331; Fri, 22 Jan 2021 05:59:45 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-19-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-19-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 13:59:33 +0000 Message-ID: Subject: Re: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 13:59:49 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Signed-off-by: Richard Henderson So when does the real kernel report async MTE exceptions to userspace? The commit message would be a good place to briefly describe the kernel's strategy and where QEMU differs from it (if anywhere)... > --- > linux-user/aarch64/target_signal.h | 1 + > linux-user/aarch64/cpu_loop.c | 34 +++++++++++++++++++++--------- > target/arm/mte_helper.c | 10 +++++++++ > 3 files changed, 35 insertions(+), 10 deletions(-) > > diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h > index 777fb667fe..18013e1b23 100644 > --- a/linux-user/aarch64/target_signal.h > +++ b/linux-user/aarch64/target_signal.h > @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { > > #include "../generic/signal.h" > > +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ > #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ > > #define TARGET_ARCH_HAS_SETUP_FRAME > diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c > index 6867f0db2b..6160a401bd 100644 > --- a/linux-user/aarch64/cpu_loop.c > +++ b/linux-user/aarch64/cpu_loop.c > @@ -72,6 +72,21 @@ > put_user_u16(__x, (gaddr)); \ > }) > > +static bool check_mte_async_fault(CPUARMState *env, target_siginfo_t *info) > +{ > + if (likely(env->cp15.tfsr_el[0] == 0)) { > + return false; > + } > + > + env->cp15.tfsr_el[0] = 0; > + info->si_signo = TARGET_SIGSEGV; > + info->si_errno = 0; > + info->_sifields._sigfault._addr = 0; > + info->si_code = TARGET_SEGV_MTEAERR; > + queue_signal(env, info->si_signo, QEMU_SI_FAULT, info); > + return true; > +} > + > /* AArch64 main loop */ > void cpu_loop(CPUARMState *env) > { > @@ -88,15 +103,13 @@ void cpu_loop(CPUARMState *env) > > switch (trapnr) { > case EXCP_SWI: > - ret = do_syscall(env, > - env->xregs[8], > - env->xregs[0], > - env->xregs[1], > - env->xregs[2], > - env->xregs[3], > - env->xregs[4], > - env->xregs[5], > - 0, 0); > + if (check_mte_async_fault(env, &info)) { > + ret = -TARGET_ERESTARTSYS; > + } else { > + ret = do_syscall(env, env->xregs[8], env->xregs[0], > + env->xregs[1], env->xregs[2], env->xregs[3], > + env->xregs[4], env->xregs[5], 0, 0); > + } > if (ret == -TARGET_ERESTARTSYS) { > env->pc -= 4; > } else if (ret != -TARGET_QEMU_ESIGRETURN) { > @@ -104,7 +117,8 @@ void cpu_loop(CPUARMState *env) > } > break; > case EXCP_INTERRUPT: > - /* just indicate that signals should be handled asap */ > + /* Just indicate that signals should be handled asap. */ > + check_mte_async_fault(env, &info); > break; > case EXCP_UDEF: > info.si_signo = TARGET_SIGILL; So this doesn't guarantee to check the async-fault status on every exit from cpu_exec(), which means we might miss things. For instance I think this slightly contrived example would not ever take the SEGV: STR x0, [x1] # with a bad tag YIELD l: B l because the STR and YIELD go into the same TB, the YIELD causes us to leave the TB with EXCP_YIELD, we don't check for an async fault in that code path, and then we'll go into the infinite loop and have nothing to prompt us to come out and look at the async fault flags. Does it work if we just always queue the SEGV on exit from cpu_exec() and let the signal handling machinery prioritize if we also pend some other signal because this was an EXCP_UDEF or whatever? It would be neater if we could keep the fault-check outside the switch (trapnr) somehow. > diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c > index 153bd1e9df..d55f8d1e1e 100644 > --- a/target/arm/mte_helper.c > +++ b/target/arm/mte_helper.c > @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, > select = 0; > } > env->cp15.tfsr_el[el] |= 1 << select; > +#ifdef CONFIG_USER_ONLY > + /* > + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, > + * which then sends a SIGSEGV when the thread is next scheduled. > + * This cpu will return to the main loop at the end of the TB, > + * which is rather sooner than "normal". But the alternative > + * is waiting until the next syscall. > + */ > + qemu_cpu_kick(env_cpu(env)); > +#endif > break; This does the right thing, but qemu_cpu_kick() is one of those functions that's in a category of "not used much at all in the codebase" and which always make me wonder if there's a reason. (In particular there's exactly one use in the whole of target/ right now.) I suppose the case of "helper function wants to cause us to leave the TB loop but not to abort the current insn" is an unusual one... thanks -- PMM From MAILER-DAEMON Fri Jan 22 09:02:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2x1E-0006Hh-37 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:02:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2x1C-0006H9-Kz for qemu-arm@nongnu.org; Fri, 22 Jan 2021 09:02:30 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:43881) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2x1A-0002NR-Pq for qemu-arm@nongnu.org; Fri, 22 Jan 2021 09:02:30 -0500 Received: by mail-ed1-x52f.google.com with SMTP id n6so6647987edt.10 for ; Fri, 22 Jan 2021 06:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; 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Fri, 22 Jan 2021 06:02:27 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-21-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-21-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 14:02:16 +0000 Message-ID: Subject: Re: [PATCH v3 20/21] target/arm: Enable MTE for user-only To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:02:30 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index abc0affd00..5e613a747a 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -208,6 +208,22 @@ static void arm_cpu_reset(DeviceState *dev) > * Do not modify this without other changes. > */ > env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); > + > + /* Enable MTE */ > + if (cpu_isar_feature(aa64_mte, cpu)) { > + /* Enable tag access, but leave TCF0 as No Effect (0). */ > + env->cp15.sctlr_el[1] |= SCTLR_ATA0; > + /* > + * Exclude all tags, so that tag 0 is always used. > + * This corresponds to Linux current->thread.gcr_incl = 0. > + * > + * Set RRND, so that helper_irg() will generate a seed later. > + * Here in cpu_reset(), the crypto subsystem has not yet been > + * initialized. > + */ > + env->cp15.gcr_el1 = 0x1ffff; > + } > + > # ifdef TARGET_TAGGED_ADDRESSES > env->untagged_addr_mask = -1; > # endif > -- Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 09:04:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2x3L-0007DS-Fg for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:04:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2x3D-0007BX-VK for qemu-arm@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:04:36 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tests/tcg/aarch64/mte.h | 53 +++++++++++++++++++++++++++++++ > tests/tcg/aarch64/mte-1.c | 25 +++++++++++++++ > tests/tcg/aarch64/mte-2.c | 42 ++++++++++++++++++++++++ > tests/tcg/aarch64/mte-3.c | 47 +++++++++++++++++++++++++++ > tests/tcg/aarch64/mte-4.c | 42 ++++++++++++++++++++++++ > tests/tcg/aarch64/Makefile.target | 6 ++++ > tests/tcg/configure.sh | 4 +++ > 7 files changed, 219 insertions(+) > create mode 100644 tests/tcg/aarch64/mte.h > create mode 100644 tests/tcg/aarch64/mte-1.c > create mode 100644 tests/tcg/aarch64/mte-2.c > create mode 100644 tests/tcg/aarch64/mte-3.c > create mode 100644 tests/tcg/aarch64/mte-4.c > > diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h > new file mode 100644 > index 0000000000..038d33ab6c > --- /dev/null > +++ b/tests/tcg/aarch64/mte.h > @@ -0,0 +1,53 @@ > +#include > +#include > +#include > +#include All new files need the usual copyright-and-license header comment, please. thanks -- PMM From MAILER-DAEMON Fri Jan 22 09:06:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2x4e-00087W-Px for mharc-qemu-arm@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:06:02 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > Use the now-saved PAGE_ANON and PAGE_MTE bits, > and the per-page saved data. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 09:08:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2x7B-0002yh-AT for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:08:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2x79-0002tt-49; Fri, 22 Jan 2021 09:08:39 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:34040) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2x76-0004ue-Cy; Fri, 22 Jan 2021 09:08:38 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 9B6ACC602E6; Fri, 22 Jan 2021 15:08:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611324508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=c9D47Z2ircPJwyM8GEdhkkR3j3y0zUdEBXNz0rVILSA=; b=fWyRJ/tU2+yavzqJAr45HbqU10apqO0LzjD7YLy1TnMVhf1pyQpzqrZ3yL2kKdtYijF8+m 9H5hqdzsN73PxEXm9MjpYEjMBTfEBfV56tD4fwfrc/9wkPMP9KTh02fP2BDMLyzpT9k6Xu aGlqo8+05Ix5le7mvUgnOGSv9hqamxlsJHDs5K7ESrbW8qsdGaKGtWK3U11IFsSzBSvXKK SA/jlnPzK3yfbfUtBJDO5aTxBwQRtDtwB5LTOmGD+60TOeZjcUHFhVaTfjCeuwWy8JmlMD JzcLXtU7GJo4Iiq0NFslO+oGhWtn+bTfOBNuu302yPNsNnkEQ3DbGxnUvzBErw== Date: Fri, 22 Jan 2021 15:08:49 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Message-ID: <20210122140849.26kssn6kfh5av6a6@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-2-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-2-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:08:39 -0000 On 19:05 Thu 21 Jan , Peter Maydell wrote: > The ptimer API currently provides two methods for setting the period: > ptimer_set_period(), which takes a period in nanoseconds, and > ptimer_set_freq(), which takes a frequency in Hz. Neither of these > lines up nicely with the Clock API, because although both the Clock > and the ptimer track the frequency using a representation of whole > and fractional nanoseconds, conversion via either period-in-ns or > frequency-in-Hz will introduce a rounding error. > > Add a new function ptimer_set_period_from_clock() which takes the > Clock object directly to avoid the rounding issues. This includes a > facility for the user to specify that there is a frequency divider > between the Clock proper and the timer, as some timer devices like > the CMSDK APB dualtimer need this. > > To avoid having to drag in clock.h from ptimer.h we add the Clock > type to typedefs.h. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > Side note, I forget why we didn't go for 64.32 fixedpoint for the > Clock too. I kinda feel we might run into the "clocks can't handle > periods greater than 4 seconds" limit some day. Hopefully we can > backwards-compatibly expand it if that day ever comes... > > The 'divisor' functionality seemed like the simplest way to get > to what I needed for the dualtimer; perhaps we should think about > whether we can have generic lightweight support for clock > frequency divider/multipliers... > --- > include/hw/ptimer.h | 22 ++++++++++++++++++++++ > include/qemu/typedefs.h | 1 + > hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++ > 3 files changed, 57 insertions(+) > > diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h > index 412763fffb2..c443218475b 100644 > --- a/include/hw/ptimer.h > +++ b/include/hw/ptimer.h > @@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s); > */ > void ptimer_set_period(ptimer_state *s, int64_t period); > > +/** > + * ptimer_set_period_from_clock - Set counter increment from a Clock > + * @s: ptimer to configure > + * @clk: pointer to Clock object to take period from > + * @divisor: value to scale the clock frequency down by > + * > + * If the ptimer is being driven from a Clock, this is the preferred > + * way to tell the ptimer about the period, because it avoids any > + * possible rounding errors that might happen if the internal > + * representation of the Clock period was converted to either a period > + * in ns or a frequency in Hz. > + * > + * If the ptimer should run at the same frequency as the clock, > + * pass 1 as the @divisor; if the ptimer should run at half the > + * frequency, pass 2, and so on. > + * > + * This function will assert if it is called outside a > + * ptimer_transaction_begin/commit block. > + */ > +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock, > + unsigned int divisor); > + > /** > * ptimer_set_freq - Set counter frequency in Hz > * @s: ptimer to configure > diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h > index 976b529dfb5..68deb74ef6f 100644 > --- a/include/qemu/typedefs.h > +++ b/include/qemu/typedefs.h > @@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState; > typedef struct BusClass BusClass; > typedef struct BusState BusState; > typedef struct Chardev Chardev; > +typedef struct Clock Clock; > typedef struct CompatProperty CompatProperty; > typedef struct CoMutex CoMutex; > typedef struct CPUAddressSpace CPUAddressSpace; > diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c > index 2aa97cb665c..6ba19fd9658 100644 > --- a/hw/core/ptimer.c > +++ b/hw/core/ptimer.c > @@ -15,6 +15,7 @@ > #include "sysemu/qtest.h" > #include "block/aio.h" > #include "sysemu/cpus.h" > +#include "hw/clock.h" > > #define DELTA_ADJUST 1 > #define DELTA_NO_ADJUST -1 > @@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period) > } > } > > +/* Set counter increment interval from a Clock */ > +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk, > + unsigned int divisor) > +{ > + /* > + * The raw clock period is a 64-bit value in units of 2^-32 ns; > + * put another way it's a 32.32 fixed-point ns value. Our internal > + * representation of the period is 64.32 fixed point ns, so > + * the conversion is simple. > + */ > + uint64_t raw_period = clock_get(clk); > + uint64_t period_frac; > + > + assert(s->in_transaction); > + s->delta = ptimer_get_count(s); > + s->period = extract64(raw_period, 32, 32); > + period_frac = extract64(raw_period, 0, 32); > + /* > + * divisor specifies a possible frequency divisor between the > + * clock and the timer, so it is a multiplier on the period. > + * We do the multiply after splitting the raw period out into > + * period and frac to avoid having to do a 32*64->96 multiply. > + */ > + s->period *= divisor; > + period_frac *= divisor; > + s->period += extract64(period_frac, 32, 32); > + s->period_frac = (uint32_t)period_frac; > + > + if (s->enabled) { > + s->need_reload = true; > + } > +} > + > /* Set counter frequency in Hz. */ > void ptimer_set_freq(ptimer_state *s, uint32_t freq) > { > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 09:14:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2xCX-0000Zy-QB for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:14:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2xCW-0000X0-7e for qemu-arm@nongnu.org; Fri, 22 Jan 2021 09:14:12 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:42531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2xCU-0007Yb-D5 for qemu-arm@nongnu.org; Fri, 22 Jan 2021 09:14:11 -0500 Received: by mail-ej1-x634.google.com with SMTP id r12so7824041ejb.9 for ; Fri, 22 Jan 2021 06:14:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yts383Q/+RypgJ2WWaN857rGSO/qQt0rWIi4lgSBZXY=; b=DB9ULNZ+HUVPxQvyhe3q2qQaGg7hfa7Q2Tz2BGvoMeVpAj65WvalyOKyhphh9Uc++c agfLNWrATeDwJxAIgqmVu2XtJDSMSHXGuxz6fqEXR7TcMpVnyouPo7aMC2F835mgHIkm w3UoyIecwJouRHzZyNfEuwKvgVcuyN/m4X85YdFR9+3wc4cK+GSPDk5XTQQvb+TL84R6 M+gaaW4zaJVd/3wjVZpwUOfmuhTMaGMDHd0B68kxMdwmqsolUJJUpOk5Q87VXMgJpj+F NagPbUITw+E2M4ryRHUmzdmQCTPRrLHrNSZDZh2hUxJh1fpMwjRshMX8oWUPd0mTQKbc mJbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yts383Q/+RypgJ2WWaN857rGSO/qQt0rWIi4lgSBZXY=; b=fhxFhQLH6I/CqWIQpjderIIbZ4J71TgCGZn2ISDTtBjMVqD0a+Z9Tt3hidXrGHEDHn zAtj5ZdWZGIiXPb150KVANA5wUZTka7gMSEjt/gm32wc5+ofa1gxOKViWqKs17aoCmp6 cYfbSywOILm+TZ4n7X89aPTmOMzKKz/J3lkenLiW5UgWFPK5lWjiggcLVcrB6Y638XKR 1i1ZZTeZxdHrg9TK4p2dCqPr5i97vCkGJ91I80z6HCROrpeT8JMgavfx2lgHlsQyHXY9 /OeaA8pJmaNJhj3VqdY5/eleSpKIJx9ZPKoIi1eQS0Tlf2B0Z1dKQOCvIjDG+yr7eqq5 WgnA== X-Gm-Message-State: AOAM533SZLDGU7NDiBnMh6QfDi17Q35Mq6GiQ1pAL+QbKSJdkmXs9ghH qe+xeP3gWuL/u3kCA7wvvh02q/apzvhDyfUPqQb4Nw== X-Google-Smtp-Source: ABdhPJxEhc0+RGdI1nhSbo7eQrEtTx3tIYuOE9j879neeIrpgkeuxeoqn5/sG+YdzsjOuDg9P3RxLDbmCWTRXSFZKHA= X-Received: by 2002:a17:906:3603:: with SMTP id q3mr2989396ejb.382.1611324848796; Fri, 22 Jan 2021 06:14:08 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-12-richard.henderson@linaro.org> In-Reply-To: <20210115224645.1196742-12-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 14:13:57 +0000 Message-ID: Subject: Re: [PATCH v3 11/21] exec: Add support for TARGET_TAGGED_ADDRESSES To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:14:12 -0000 On Fri, 15 Jan 2021 at 22:47, Richard Henderson wrote: > > The AArch64 Linux ABI has always enabled TBI, but has historically > required that pointer tags be removed before a syscall. This has > changed in the lead-up to ARMv8.5-MTE, in a way that affects the > ABI generically and not specifically to MTE. > > This patch allows the target to indicate that (1) there are tags > and (2) whether or not they should be taken into account at the > syscall level. > > Adjust g2h, guest_addr_valid, and guest_range_valid to ignore > pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok > in the arm64 kernel source. > > The prctl syscall is not not yet updated, so this change by itself > has no visible effect. > > Signed-off-by: Richard Henderson > --- > include/exec/cpu_ldst.h | 20 +++++++++++++++++--- > 1 file changed, 17 insertions(+), 3 deletions(-) > > diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h > index e62f4fba00..1df9b93e59 100644 > --- a/include/exec/cpu_ldst.h > +++ b/include/exec/cpu_ldst.h > @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; > #define TARGET_ABI_FMT_ptr "%"PRIx64 > #endif > > +static inline abi_ptr untagged_addr(abi_ptr x) > +{ > +#ifdef TARGET_TAGGED_ADDRESSES > + if (current_cpu) { > + return cpu_untagged_addr(current_cpu, x); > + } > +#endif > + return x; > +} The current_cpu global is a nasty hack and I don't like seeing new usages of it. In particular, it's very difficult to analyse in what places this will get called when current_cpu is NULL and whether it's always OK to not clean the tag in that situation. thanks -- PMM From MAILER-DAEMON Fri Jan 22 09:15:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2xDe-0001z6-GS for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:15:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2xDc-0001wo-Ph; Fri, 22 Jan 2021 09:15:20 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:34446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2xDa-00081s-23; Fri, 22 Jan 2021 09:15:20 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 46680C602E6; Fri, 22 Jan 2021 15:15:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611324915; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Hj31JtBA8JkF+nolfAcP7G8osTbcEoYpDkFcINBCRDk=; b=dLq9OhoRb6vHTLjPaSRnZe1f8HuJVO/e+X/E5ksv5UYUXgw4AQrNy7aek9qx6m/8H1A06t zL4IKftqTIwBOZPs2ghrHvly7zt9L5LOcEwCJ5wrdDIrU7lzymV2LLYIGXNEHO3Zs5z8tH GiZAp8uUyHI/2osJo0AgJRp4CAvCeM3mfBcdrfEx4I1a3OAaXCuXw22Y5FBtWz3JlbrBtw PSPoVxlgtmhjb6M1+gpb2c/lLye9XzxsbyxUc5puziW7jpxUh5YStR7/u2mJP/zo/zjzlj bZhatJmuOXeWvZofIeuoDO5a/c24QO5qrTmrdkfUivYzSnn9iHr02V2K1xchhg== Date: Fri, 22 Jan 2021 15:15:36 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 02/25] clock: Add new clock_has_source() function Message-ID: <20210122141536.n6mplt2z7ckv3izc@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-3-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-3-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:15:21 -0000 On 19:05 Thu 21 Jan , Peter Maydell wrote: > Add a function for checking whether a clock has a source. This is > useful for devices which have input clocks that must be wired up by > the board as it allows them to fail in realize rather than ploughing > on with a zero-period clock. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > docs/devel/clocks.rst | 16 ++++++++++++++++ > include/hw/clock.h | 15 +++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst > index 2548d842322..c54bbb82409 100644 > --- a/docs/devel/clocks.rst > +++ b/docs/devel/clocks.rst > @@ -235,6 +235,22 @@ object during device instance init. For example: > /* set initial value to 10ns / 100MHz */ > clock_set_ns(clk, 10); > > +To enforce that the clock is wired up by the board code, you can > +call ``clock_has_source()`` in your device's realize method: > + > +.. code-block:: c > + > + if (!clock_has_source(s->clk)) { > + error_setg(errp, "MyDevice: clk input must be connected"); > + return; > + } > + > +Note that this only checks that the clock has been wired up; it is > +still possible that the output clock connected to it is disabled > +or has not yet been configured, in which case the period will be > +zero. You should use the clock callback to find out when the clock > +period changes. > + > Fetching clock frequency/period > ------------------------------- > > diff --git a/include/hw/clock.h b/include/hw/clock.h > index 6382f346569..e5f45e2626d 100644 > --- a/include/hw/clock.h > +++ b/include/hw/clock.h > @@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk); > */ > void clock_set_source(Clock *clk, Clock *src); > > +/** > + * clock_has_source: > + * @clk: the clock > + * > + * Returns true if the clock has a source clock connected to it. > + * This is useful for devices which have input clocks which must > + * be connected by the board/SoC code which creates them. The > + * device code can use this to check in its realize method that > + * the clock has been connected. > + */ > +static inline bool clock_has_source(const Clock *clk) > +{ > + return clk->source != NULL; > +} > + > /** > * clock_set: > * @clk: the clock to initialize. > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 09:22:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2xKN-0007px-M9 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 09:22:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2xKM-0007ph-7E; Fri, 22 Jan 2021 09:22:18 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:34798) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2xKF-0002rB-34; Fri, 22 Jan 2021 09:22:17 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 5B35AC602E6; Fri, 22 Jan 2021 15:22:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611325327; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=BZr6sDNcCgeUlARkGZE2pYefUM9XfWaCmA93O5S/HHA=; b=G0dK7tmiMpwnrHC8gYBiajH/YnjnyumuiKvWDNUvjnB31N0MQNU1hrLhIJOjDpIa/DWFdY OrAIuq4MBJi0MnXXEq+8Wk3nZx9P1f6Mn8UvdMtTy+V/nUIiUFtMSHuf0jSNdJCYFmj8ii 7HY9TH1lhEvMTHR+1sE2TfF/HJUEwqz5r3Xwb9GLke3diiasVKKK+iJOb8TX9pt/z1CELd NK2rLP6rWzqRc9zI6S8iWIgDWbuHciCkYDpreG32+y10bm65+p4CW3xfUBuLKqeshj7xXI N5uUQ9bkDdq7kEbbX/P/0HJjaoUOgOqKG2FT+yQUQkrE1tT6XMvE09LnjXWmgQ== Date: Fri, 22 Jan 2021 15:22:28 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Message-ID: <20210122142228.v3wnfzz447j5w6nj@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-7-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-7-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 14:22:18 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > The state struct for the CMSDK APB timer device doesn't follow our > usual naming convention of camelcase -- "CMSDK" and "APB" are both > acronyms, but "TIMER" is not so should not be all-uppercase. > Globally rename the struct to "CMSDKAPBTimer" (bringing it into line > with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains > as-is because "UART" is an acronym). > > Commit created with: > perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/arm/armsse.h | 6 +++--- > include/hw/timer/cmsdk-apb-timer.h | 4 ++-- > hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++-------------- > 3 files changed, 19 insertions(+), 19 deletions(-) > > diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h > index 77f86771c30..83f5e28c16e 100644 > --- a/include/hw/arm/armsse.h > +++ b/include/hw/arm/armsse.h > @@ -153,9 +153,9 @@ struct ARMSSE { > TZPPC apb_ppc0; > TZPPC apb_ppc1; > TZMPC mpc[IOTS_NUM_MPC]; > - CMSDKAPBTIMER timer0; > - CMSDKAPBTIMER timer1; > - CMSDKAPBTIMER s32ktimer; > + CMSDKAPBTimer timer0; > + CMSDKAPBTimer timer1; > + CMSDKAPBTimer s32ktimer; > qemu_or_irq ppc_irq_orgate; > SplitIRQ sec_resp_splitter; > SplitIRQ ppc_irq_splitter[NUM_PPCS]; > diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h > index 0d80b2a48cd..baa009bb2da 100644 > --- a/include/hw/timer/cmsdk-apb-timer.h > +++ b/include/hw/timer/cmsdk-apb-timer.h > @@ -18,9 +18,9 @@ > #include "qom/object.h" > > #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" > -OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER) > +OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) > > -struct CMSDKAPBTIMER { > +struct CMSDKAPBTimer { > /*< private >*/ > SysBusDevice parent_obj; > > diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c > index f85f1309f37..ae9c5422540 100644 > --- a/hw/timer/cmsdk-apb-timer.c > +++ b/hw/timer/cmsdk-apb-timer.c > @@ -67,14 +67,14 @@ static const int timer_id[] = { > 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ > }; > > -static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) > +static void cmsdk_apb_timer_update(CMSDKAPBTimer *s) > { > qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); > } > > static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) > { > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); > uint64_t r; > > switch (offset) { > @@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) > static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, > unsigned size) > { > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); > > trace_cmsdk_apb_timer_write(offset, value, size); > > @@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = { > > static void cmsdk_apb_timer_tick(void *opaque) > { > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); > > if (s->ctrl & R_CTRL_IRQEN_MASK) { > s->intstatus |= R_INTSTATUS_IRQ_MASK; > @@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque) > > static void cmsdk_apb_timer_reset(DeviceState *dev) > { > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); > > trace_cmsdk_apb_timer_reset(); > s->ctrl = 0; > @@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) > static void cmsdk_apb_timer_init(Object *obj) > { > SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj); > > memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, > s, "cmsdk-apb-timer", 0x1000); > @@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj) > > static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > { > - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); > > if (s->pclk_frq == 0) { > error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); > @@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { > .version_id = 1, > .minimum_version_id = 1, > .fields = (VMStateField[]) { > - VMSTATE_PTIMER(timer, CMSDKAPBTIMER), > - VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), > - VMSTATE_UINT32(value, CMSDKAPBTIMER), > - VMSTATE_UINT32(reload, CMSDKAPBTIMER), > - VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), > + VMSTATE_PTIMER(timer, CMSDKAPBTimer), > + VMSTATE_UINT32(ctrl, CMSDKAPBTimer), > + VMSTATE_UINT32(value, CMSDKAPBTimer), > + VMSTATE_UINT32(reload, CMSDKAPBTimer), > + VMSTATE_UINT32(intstatus, CMSDKAPBTimer), > VMSTATE_END_OF_LIST() > } > }; > > static Property cmsdk_apb_timer_properties[] = { > - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), > + DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), > DEFINE_PROP_END_OF_LIST(), > }; > > @@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) > static const TypeInfo cmsdk_apb_timer_info = { > .name = TYPE_CMSDK_APB_TIMER, > .parent = TYPE_SYS_BUS_DEVICE, > - .instance_size = sizeof(CMSDKAPBTIMER), > + .instance_size = sizeof(CMSDKAPBTimer), > .instance_init = cmsdk_apb_timer_init, > .class_init = cmsdk_apb_timer_class_init, > }; > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:10:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2y5R-00072J-1n for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:10:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2y5P-0006zN-Qm; Fri, 22 Jan 2021 10:10:55 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:37104) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2y5M-00008k-8l; Fri, 22 Jan 2021 10:10:55 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 380C3C602E6; Fri, 22 Jan 2021 16:10:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611328249; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=U5Mp5i+Beskuw5QIaO3QIgdUSiNWtRWABsRDVUwBegg=; b=DRjSJqH/ApRlyI6cWO6wReNxNDkYlu2KrkznEo8b4dQ6VcvdfUN/PsHx8g/6G/N6InUgXW jNRNJ87SmC0g6EeAWzhUhtNFMEEofGjb93sMKT5Yzm/NEuwamoBZ1UZW2dECnTKHJKFgSj C1JXmXhufrpY67ubZxipPCjMLqgDxMbfuHzvqMkFAG/BUOF9Fwh4NN8sarb4m3wVSPmbnV +ohLAI3JwKBwYY+dviGzyvRmNJUmYBSmlYa9kl/JGbTZ6YKO3+j0a+dGrod2t82UgelSQO /5A9SZL/by1QR/zRnHrq2l1p3U8LUDmdpNGM/nlwN6f02/2cJp+IJh6RwDO4qg== Date: Fri, 22 Jan 2021 16:11:10 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Message-ID: <20210122151110.oznikz7qcc2tyrsz@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-8-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-8-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:10:56 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > As the first step in converting the CMSDK_APB_TIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the pclk-frq > property to using the Clock once all the users of this device have > been converted to wire up the Clock. > > Since the device doesn't already have a doc comment for its "QEMU > interface", we add one including the new Clock. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++ > hw/timer/cmsdk-apb-timer.c | 7 +++++-- > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h > index baa009bb2da..fc2aa97acac 100644 > --- a/include/hw/timer/cmsdk-apb-timer.h > +++ b/include/hw/timer/cmsdk-apb-timer.h > @@ -15,11 +15,19 @@ > #include "hw/qdev-properties.h" > #include "hw/sysbus.h" > #include "hw/ptimer.h" > +#include "hw/clock.h" > #include "qom/object.h" > > #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" > OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) > > +/* > + * QEMU interface: > + * + QOM property "pclk-frq": frequency at which the timer is clocked > + * + Clock input "pclk": clock for the timer > + * + sysbus MMIO region 0: the register bank > + * + sysbus IRQ 0: timer interrupt TIMERINT > + */ > struct CMSDKAPBTimer { > /*< private >*/ > SysBusDevice parent_obj; > @@ -29,6 +37,7 @@ struct CMSDKAPBTimer { > qemu_irq timerint; > uint32_t pclk_frq; > struct ptimer_state *timer; > + Clock *pclk; > > uint32_t ctrl; > uint32_t value; > diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c > index ae9c5422540..c63145ff553 100644 > --- a/hw/timer/cmsdk-apb-timer.c > +++ b/hw/timer/cmsdk-apb-timer.c > @@ -35,6 +35,7 @@ > #include "hw/sysbus.h" > #include "hw/irq.h" > #include "hw/registerfields.h" > +#include "hw/qdev-clock.h" > #include "hw/timer/cmsdk-apb-timer.h" > #include "migration/vmstate.h" > > @@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj) > s, "cmsdk-apb-timer", 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->timerint); > + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); > } > > static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > @@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > > static const VMStateDescription cmsdk_apb_timer_vmstate = { > .name = "cmsdk-apb-timer", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > VMSTATE_PTIMER(timer, CMSDKAPBTimer), > + VMSTATE_CLOCK(pclk, CMSDKAPBTimer), > VMSTATE_UINT32(ctrl, CMSDKAPBTimer), > VMSTATE_UINT32(value, CMSDKAPBTimer), > VMSTATE_UINT32(reload, CMSDKAPBTimer), > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:17:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yBO-0001ym-Io for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:17:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yBJ-0001w5-WC; Fri, 22 Jan 2021 10:17:02 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:37382) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yBE-00032d-EA; Fri, 22 Jan 2021 10:17:01 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 26D47C602E6; Fri, 22 Jan 2021 16:16:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611328613; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=aDeRcbRcSdeYQMiBxaM0MtdLiWNQTQc9AATAIzjTG3I=; b=WwIbZ92krjPfgIxBYuuWsvuqP+s/jeh1l99E3tMh6hFLXvtKnnQTfbsPB9qgSadhM3HXDk LEONa8zvijkvC6PFaz1/re7Q0ISUH0maBIZc1evCDYVSR62QnHWiGvIBugxCpHV8CfFUBI XsqhxvcgSstBJ/Jjj1yjIz/b2CH76OOirqvg3FoiHpFVbA9AxVHLwUJcQSmatW1WPIHnIu kI9nfxAEkcjaVoGkmoRj/e2iJ8Q44Ea64WCQ9KrE3CtMlk4ngHmv1QKoNKt2rStLWMxeBY /PtfbUcIFViRTgR+gdg6u35RxHCcF06O+xah04SRV/58O18pItvQH/GZJ7cqig== Date: Fri, 22 Jan 2021 16:17:14 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input Message-ID: <20210122151714.7gd7a3r6oipciw4u@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-9-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-9-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:17:03 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > As the first step in converting the CMSDK_APB_DUALTIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the pclk-frq > property to using the Clock once all the users of this device have > been converted to wire up the Clock. > > We take the opportunity to correct the name of the clock input to > match the hardware -- the dual timer names the clock which drives the > timers TIMCLK. (It does also have a 'pclk' input, which is used only > for the register and APB bus logic; on the SSE-200 these clocks are > both connected together.) > > This is a migration compatibility break for machines mps2-an385, > mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, > musca-b1. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++ > hw/timer/cmsdk-apb-dualtimer.c | 7 +++++-- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h > index 08d9e6fa3d5..3adbb01dd34 100644 > --- a/include/hw/timer/cmsdk-apb-dualtimer.h > +++ b/include/hw/timer/cmsdk-apb-dualtimer.h > @@ -17,6 +17,7 @@ > * > * QEMU interface: > * + QOM property "pclk-frq": frequency at which the timer is clocked > + * + Clock input "TIMCLK": clock (for both timers) > * + sysbus MMIO region 0: the register bank > * + sysbus IRQ 0: combined timer interrupt TIMINTC > * + sysbus IRO 1: timer block 1 interrupt TIMINT1 > @@ -28,6 +29,7 @@ > > #include "hw/sysbus.h" > #include "hw/ptimer.h" > +#include "hw/clock.h" > #include "qom/object.h" > > #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer" > @@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer { > MemoryRegion iomem; > qemu_irq timerintc; > uint32_t pclk_frq; > + Clock *timclk; > > CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; > uint32_t timeritcr; > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c > index f6534241b94..781b496037b 100644 > --- a/hw/timer/cmsdk-apb-dualtimer.c > +++ b/hw/timer/cmsdk-apb-dualtimer.c > @@ -25,6 +25,7 @@ > #include "hw/irq.h" > #include "hw/qdev-properties.h" > #include "hw/registerfields.h" > +#include "hw/qdev-clock.h" > #include "hw/timer/cmsdk-apb-dualtimer.h" > #include "migration/vmstate.h" > > @@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj) > for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { > sysbus_init_irq(sbd, &s->timermod[i].timerint); > } > + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); > } > > static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) > @@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = { > > static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { > .name = "cmsdk-apb-dualtimer", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > + VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer), > VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer, > CMSDK_APB_DUALTIMER_NUM_MODULES, > 1, cmsdk_dualtimermod_vmstate, > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:18:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yCH-0003ae-PP for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:18:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yCG-0003YH-An; Fri, 22 Jan 2021 10:18:00 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:37446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yCE-0003XV-IT; Fri, 22 Jan 2021 10:18:00 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 06186C602E6; Fri, 22 Jan 2021 16:17:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611328676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=5H9QuNwEAPkFYnOSl+IeanFyazg/L2M2wvzM1W0QBzs=; b=ESgwxSJKqbdKG9NTmfBjR2Nhs9XrHDN08LpC5Q+/m8kMYQaizGD4C1ZwaWkfPKfi/dokpO TbrHgSufrUmPUFv64XqBWhKbom12e29EtFNXlPPsngvbmpcjSrdu36Hr30rdk2+8gyHp3g g778T2pC0OgyTf+JlmzynwphYsKdkzI8rp6ERRi3Wx/emEr/WldkTrv770tBY2Wcz64y1V HLxniR5k3ZMSBH5b/YGG3i8alMIisEsotTpuyJVdM8sI93wdRKwjzfji/1yayyVdHeJ7XS YX39g1XmsohMityffMJEdxZePxSiSLUYE+KM5hURSdE1BDmcc3vzWEq4SEBAAQ== Date: Fri, 22 Jan 2021 16:18:17 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input Message-ID: <20210122151817.5tze5qxc6dp3lhkr@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-10-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-10-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:18:00 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > As the first step in converting the CMSDK_APB_TIMER device to the > Clock framework, add a Clock input. For the moment we do nothing > with this clock; we will change the behaviour from using the > wdogclk-frq property to using the Clock once all the users of this > device have been converted to wire up the Clock. > > This is a migration compatibility break for machines mps2-an385, > mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, > musca-b1, lm3s811evb, lm3s6965evb. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++ > hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++-- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h > index 3da0d43e355..34069ca6969 100644 > --- a/include/hw/watchdog/cmsdk-apb-watchdog.h > +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h > @@ -17,6 +17,7 @@ > * > * QEMU interface: > * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked > + * + Clock input "WDOGCLK": clock for the watchdog's timer > * + sysbus MMIO region 0: the register bank > * + sysbus IRQ 0: watchdog interrupt > * > @@ -33,6 +34,7 @@ > > #include "hw/sysbus.h" > #include "hw/ptimer.h" > +#include "hw/clock.h" > #include "qom/object.h" > > #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" > @@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog { > uint32_t wdogclk_frq; > bool is_luminary; > struct ptimer_state *timer; > + Clock *wdogclk; > > uint32_t control; > uint32_t intstatus; > diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c > index 5bbadadfa68..b03bcb73628 100644 > --- a/hw/watchdog/cmsdk-apb-watchdog.c > +++ b/hw/watchdog/cmsdk-apb-watchdog.c > @@ -30,6 +30,7 @@ > #include "hw/irq.h" > #include "hw/qdev-properties.h" > #include "hw/registerfields.h" > +#include "hw/qdev-clock.h" > #include "hw/watchdog/cmsdk-apb-watchdog.h" > #include "migration/vmstate.h" > > @@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj) > s, "cmsdk-apb-watchdog", 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->wdogint); > + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); > > s->is_luminary = false; > s->id = cmsdk_apb_watchdog_id; > @@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) > > static const VMStateDescription cmsdk_apb_watchdog_vmstate = { > .name = "cmsdk-apb-watchdog", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > + VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog), > VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), > VMSTATE_UINT32(control, CMSDKAPBWatchdog), > VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:22:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yGi-0000R6-6D for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:22:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yGf-0000NV-NK; Fri, 22 Jan 2021 10:22:33 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:37712) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yGc-0005my-8l; Fri, 22 Jan 2021 10:22:33 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 95D2FC602E6; Fri, 22 Jan 2021 16:22:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611328946; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=15fOifz/s2qaB9c3W+VK6YNYLcyJJVryTUTa8SIj7dw=; b=iUHmCl5dPn3QfSUvxZ+T28QitJ0CYlioBNp0x7DTWkfcmxZrzsAo7tHv/kMlnDtkTHEWPk gjRedd09/zvWQIIk4ClBWmxlOG3kYvjGwWWhWOSa5wMu7gNWtpwi4wQ+2CnEsgYZ+qPmdk twZmq6w//qVBcJ9Uxc4KPCjWu6KQYPzgfa9DgZkL9EH2Piawj4kG7H2ergptcEMIUvoW9D vfcFsEEClMHcTy14q8Jme8J/3SKNwVnwpP1l4hcMRR/MnpEc+lrLIlzUu3kPYDDugL+taI phIChPLS3HxJ/IUYhoZYxK7y85LklUVG5IVQ7T7+7PFQRWLBo9jvzcBeGtgUqQ== Date: Fri, 22 Jan 2021 16:22:47 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Message-ID: <20210122152247.pjqnmrccj2i3wc2n@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-11-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-11-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:22:34 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > While we transition the ARMSSE code from integer properties > specifying clock frequencies to Clock objects, we want to have the > device provide both at once. We want the final name of the main > input Clock to be "MAINCLK", following the hardware name. > Unfortunately creating an input Clock with a name X creates an > under-the-hood QOM property X; for "MAINCLK" this clashes with the > existing UINT32 property of that name. > > Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the > MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be > deleted. > > Commit created with: > perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/arm/armsse.h | 2 +- > hw/arm/armsse.c | 6 +++--- > hw/arm/mps2-tz.c | 2 +- > hw/arm/musca.c | 2 +- > 4 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h > index 83f5e28c16e..4860a793f4b 100644 > --- a/include/hw/arm/armsse.h > +++ b/include/hw/arm/armsse.h > @@ -39,7 +39,7 @@ > * QEMU interface: > * + QOM property "memory" is a MemoryRegion containing the devices provided > * by the board model. > - * + QOM property "MAINCLK" is the frequency of the main system clock > + * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock > * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. > * (In hardware, the SSE-200 permits the number of expansion interrupts > * for the two CPUs to be configured separately, but we restrict it to > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index baac027659d..d2ba0459c44 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -47,7 +47,7 @@ static Property iotkit_properties[] = { > DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, > MemoryRegion *), > DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), > - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), > + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), > DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), > DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), > DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), > @@ -59,7 +59,7 @@ static Property armsse_properties[] = { > DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, > MemoryRegion *), > DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), > - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), > + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), > DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), > DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), > DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), > @@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > } > > if (!s->mainclk_frq) { > - error_setg(errp, "MAINCLK property was not set"); > + error_setg(errp, "MAINCLK_FRQ property was not set"); > return; > } > > diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c > index 3707876d6d4..6a9eed9022a 100644 > --- a/hw/arm/mps2-tz.c > +++ b/hw/arm/mps2-tz.c > @@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine) > object_property_set_link(OBJECT(&mms->iotkit), "memory", > OBJECT(system_memory), &error_abort); > qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); > - qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); > + qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); > sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); > > /* > diff --git a/hw/arm/musca.c b/hw/arm/musca.c > index b50157f63a6..d82bef11cf2 100644 > --- a/hw/arm/musca.c > +++ b/hw/arm/musca.c > @@ -375,7 +375,7 @@ static void musca_init(MachineState *machine) > qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); > qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); > qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); > - qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); > + qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); > /* > * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for > * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:33:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yRX-0004mB-1d for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:33:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yRU-0004lt-B7; Fri, 22 Jan 2021 10:33:44 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:38202) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yRO-0002Ih-4M; Fri, 22 Jan 2021 10:33:44 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id EFA32C602E6; Fri, 22 Jan 2021 16:33:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611329615; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=xeg4i8QeVQjatmW7drF6t6jp9MeDNxVlNliXw5wlWCc=; b=MgYycpkRyYvt+Pps7DVFFWLHsGFWqM6Szcr+vhFi7YLUA5SbtPmyz/y1qclYWQ6MnPiFvw 68cXxT0k95nfZaF4xH1En6KkxuBnvStHquowX5x+db6Qncp7BNenN5PfwtSWgekxl1Qgba N7hUHSEwlYrEZ8HsxsuX9sFFoGflWRL75NBASlKUZQD+A2Z1KV0O/TNRZj7z7hK2AEIww/ 7Iz+YuGufYqBehIw10OcAxRrGZbF4yIt9u5wOU4ekJmktCg1J392d36CVg5rvP8HGWyzjf uByZ5287xkCaiMyqDC1j9n10f1VFT+g4jsXeTMLb0knWQs+EikN+Irvw0nufVg== Date: Fri, 22 Jan 2021 16:33:56 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Message-ID: <20210122153356.vngi3pmohaxvmb3k@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-13-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-13-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:33:45 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > The old-style convenience function cmsdk_apb_timer_create() for > creating CMSDK_APB_TIMER objects is used in only two places in > mps2.c. Most of the rest of the code in that file uses the new > "initialize in place" coding style. > > We want to connect up a Clock object which should be done between the > object creation and realization; rather than adding a Clock* argument > to the convenience function, convert the timer creation code in > mps2.c to the same style as is used already for the watchdog, > dualtimer and other devices, and delete the now-unused convenience > function. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/timer/cmsdk-apb-timer.h | 21 --------------------- > hw/arm/mps2.c | 18 ++++++++++++++++-- > 2 files changed, 16 insertions(+), 23 deletions(-) > > diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h > index fc2aa97acac..54f7ec8c502 100644 > --- a/include/hw/timer/cmsdk-apb-timer.h > +++ b/include/hw/timer/cmsdk-apb-timer.h > @@ -45,25 +45,4 @@ struct CMSDKAPBTimer { > uint32_t intstatus; > }; > > -/** > - * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER > - * @addr: location in system memory to map registers > - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate) > - */ > -static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr, > - qemu_irq timerint, > - uint32_t pclk_frq) > -{ > - DeviceState *dev; > - SysBusDevice *s; > - > - dev = qdev_new(TYPE_CMSDK_APB_TIMER); > - s = SYS_BUS_DEVICE(dev); > - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); > - sysbus_realize_and_unref(s, &error_fatal); > - sysbus_mmio_map(s, 0, addr); > - sysbus_connect_irq(s, 0, timerint); > - return dev; > -} > - > #endif > diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c > index 9a8b23c64ce..f762d1b46af 100644 > --- a/hw/arm/mps2.c > +++ b/hw/arm/mps2.c > @@ -83,6 +83,7 @@ struct MPS2MachineState { > /* CMSDK APB subsystem */ > CMSDKAPBDualTimer dualtimer; > CMSDKAPBWatchdog watchdog; > + CMSDKAPBTimer timer[2]; > }; > > #define TYPE_MPS2_MACHINE "mps2" > @@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine) > } > > /* CMSDK APB subsystem */ > - cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); > - cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); > + for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { > + g_autofree char *name = g_strdup_printf("timer%d", i); > + hwaddr base = 0x40000000 + i * 0x1000; > + int irqno = 8 + i; > + SysBusDevice *sbd; > + > + object_initialize_child(OBJECT(mms), name, &mms->timer[i], > + TYPE_CMSDK_APB_TIMER); > + sbd = SYS_BUS_DEVICE(&mms->timer[i]); > + qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); > + sysbus_realize_and_unref(sbd, &error_fatal); > + sysbus_mmio_map(sbd, 0, base); > + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); > + } > + > object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, > TYPE_CMSDK_APB_DUALTIMER); > qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:33:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yRh-0004y0-1a for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:33:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yRg-0004wb-6t; Fri, 22 Jan 2021 10:33:56 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:38232) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yRe-0002QT-8F; Fri, 22 Jan 2021 10:33:55 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 1F63DC602E6; Fri, 22 Jan 2021 16:33:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611329632; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=LQI+a1eEM5tuxsSegx9KtrBu9puU3YV07VoG4tvtOqo=; b=PCjNaZMdYZcR1Zcy1oXiQFtyQHxCX9ukjSLfIMCqgL/rSLOhS3JUCCbExaxQGCEA/fNSwP 4J3RKpkc297gfutrzoXbxWHG06NqqDmHNi3D4hoqSZNbHX1xS07AzG6HXxcp4/mmbHLIPR 8YV3qVaYQRW01S/k7QbyuqX/BzFe75gK2rlr06Ydzec1lmAzsw8so+OZ2TwvK3cvyb0pst CMBwYe/zgfPbmbxCxnOr9LhyOH6r1ItEMqFBfe9/OLOMlvn3VIVlSQt+R23LeEgMI4goLl U9hL6A4Sl8WLiVD4IgPyrCy5v9QZLD63oDXK7enRN/HSr/tO6lbSwd/p8ZmL9A== Date: Fri, 22 Jan 2021 16:34:13 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 11/25] hw/arm/armsse: Wire up clocks Message-ID: <20210122153413.srcx5vcwnidkb5nb@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-12-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-12-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:33:56 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create two input clocks on the ARMSSE devices, one for the normal > MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the > appropriate devices. The old property-based clock frequency setting > will remain in place until conversion is complete. > > This is a migration compatibility break for machines mps2-an505, > mps2-an521, musca-a, musca-b1. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/arm/armsse.h | 6 ++++++ > hw/arm/armsse.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h > index 4860a793f4b..bfa1e79c4fe 100644 > --- a/include/hw/arm/armsse.h > +++ b/include/hw/arm/armsse.h > @@ -37,6 +37,8 @@ > * per-CPU identity and control register blocks > * > * QEMU interface: > + * + Clock input "MAINCLK": clock for CPUs and most peripherals > + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals > * + QOM property "memory" is a MemoryRegion containing the devices provided > * by the board model. > * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock > @@ -103,6 +105,7 @@ > #include "hw/misc/armsse-mhu.h" > #include "hw/misc/unimp.h" > #include "hw/or-irq.h" > +#include "hw/clock.h" > #include "hw/core/split-irq.h" > #include "hw/cpu/cluster.h" > #include "qom/object.h" > @@ -209,6 +212,9 @@ struct ARMSSE { > > uint32_t nsccfg; > > + Clock *mainclk; > + Clock *s32kclk; > + > /* Properties */ > MemoryRegion *board_memory; > uint32_t exp_numirq; > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index d2ba0459c44..4349ce9bfdb 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -21,6 +21,7 @@ > #include "hw/arm/armsse.h" > #include "hw/arm/boot.h" > #include "hw/irq.h" > +#include "hw/qdev-clock.h" > > /* Format of the System Information block SYS_CONFIG register */ > typedef enum SysConfigFormat { > @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) > assert(info->sram_banks <= MAX_SRAM_BANKS); > assert(info->num_cpus <= SSE_MAX_CPUS); > > + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); > + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); > + > memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); > > for (i = 0; i < info->num_cpus; i++) { > @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > * map its upstream ends to the right place in the container. > */ > qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { > return; > } > @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > &error_abort); > > qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { > return; > } > @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > &error_abort); > > qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { > return; > } > @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > * 0x4002f000: S32K timer > */ > qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); > + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { > return; > } > @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); > > qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); > + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { > return; > } > @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ > > qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { > return; > } > @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); > > qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); > + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { > return; > } > @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, > > static const VMStateDescription armsse_vmstate = { > .name = "iotkit", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > + VMSTATE_CLOCK(mainclk, ARMSSE), > + VMSTATE_CLOCK(s32kclk, ARMSSE), > VMSTATE_UINT32(nsccfg, ARMSSE), > VMSTATE_END_OF_LIST() > } > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 10:47:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yeb-0002oc-Gr for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:47:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yeZ-0002o8-PN for qemu-arm@nongnu.org; Fri, 22 Jan 2021 10:47:15 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:33417) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2yeY-0008RX-1B for qemu-arm@nongnu.org; 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Fri, 22 Jan 2021 07:47:12 -0800 (PST) MIME-Version: 1.0 References: <20210120092748.14789-1-maxim.uvarov@linaro.org> <20210120092748.14789-4-maxim.uvarov@linaro.org> In-Reply-To: <20210120092748.14789-4-maxim.uvarov@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 15:47:01 +0000 Message-ID: Subject: Re: [PATCHv8 3/3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:47:16 -0000 On Wed, 20 Jan 2021 at 09:27, Maxim Uvarov wrote: > > Add secure pl061 for reset/power down machine from > the secure world (Arm Trusted Firmware). Connect it > with gpio-pwr driver. > > Signed-off-by: Maxim Uvarov A nit, which I raise only because you'll need a respin anyway: > + /* connect secure pl061 to gpio-pwr */ > + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_REBOOT, > + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); > + qemu_fdt_add_subnode(vms->fdt, "/gpio-restart"); We have three different names for the same thing here: 'reboot', 'reset' and 'restart'. If we name the GPIO line SECURE_GPIO_RESET we can at least get that down to two. thanks -- PMM From MAILER-DAEMON Fri Jan 22 10:48:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l2yfc-0003da-Cr for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 10:48:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2yfb-0003bk-2x for qemu-arm@nongnu.org; Fri, 22 Jan 2021 10:48:19 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:43537) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2yfY-0000Sq-0c for qemu-arm@nongnu.org; Fri, 22 Jan 2021 10:48:18 -0500 Received: by mail-ej1-x630.google.com with SMTP id a10so8291244ejg.10 for ; Fri, 22 Jan 2021 07:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=z+lz8JO+Ur8AgDwxtMFIGokAEwyuOa+bOuNenLzyYco=; b=Aep3mZRsiMe9ttRwraKqqP72qmMxfNNGabRyJFuBlUzRxtFcOl3Jbxe59YzDV6oRgp +MeJmMPX4ju/tgkbV4/NT5NRNIr7kOXk/QiKHwnDIKZVl9p13zHwIDXEcjEfIHpyl7el 9DhsFoaFL2bYxTulOZQhrOAQx5p0fQEBBw0sjD3Fti8gMG8klvLMfeK6xW8dJxoOwx/2 2oUBrqy7Jfg5s3Jz2XKgg11shvSn/Wkm17WlzygORVorw0aJB1VrwijCRQxn/gWkpCq4 uuigEwwZHfqH1rI/2hy1JjFdvzNZuiVpmSuMzpGBwvQwzTBH7KaC0XtOdUh7wszkb85J cKSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=z+lz8JO+Ur8AgDwxtMFIGokAEwyuOa+bOuNenLzyYco=; b=gB38CTur8ovy+Slwiap65rXVpJ8VNVMoMjnYXiHTOZQ1vnZ4aeLVwxhwiFYTsOz58V ZToljOm5An/rbTAszCfkWVrN4c8YmkT5DvUw/EeKUBinlcA0uBLjU5koQ3GLO9pNPSq5 B6BVjs1mlEIaFj5D+chmYg9pzrSThOhYhLTaB34VN/In608vmqk+BKqhN86IrteAFp3b uNUS5i3x87YhMbhucQWkk7dI2ALhi0Xs1XW3Nwy+FTBkulzT+MBf76Z8T5qv07h9NVKy k9T9YGI4qdj2/HrQIe3eB+S9KFluGmkx/WBA1TUB/FGncY0hfQ8qL+OGlQe4bodZKi5A ++aw== X-Gm-Message-State: AOAM531tpxB3Zk7yAF8xhbuGmduvs8TJ29tDBfdsA9tRoYgfbJ2q8Ozs usiHChL8BVYvmW07o14itsTYg+iN8ZYDSLrRgnvpWw== X-Google-Smtp-Source: ABdhPJyNUD+5fUu7DEyETI62VUqIgflgAMvr1xzPfl9mHoimnNbH37rGTi+W3nlrZmqpjRSzQWOXyKu9JpBwcUi+OiI= X-Received: by 2002:a17:906:2747:: with SMTP id a7mr3516829ejd.250.1611330494472; Fri, 22 Jan 2021 07:48:14 -0800 (PST) MIME-Version: 1.0 References: <20210120092748.14789-1-maxim.uvarov@linaro.org> <20210120092748.14789-2-maxim.uvarov@linaro.org> In-Reply-To: <20210120092748.14789-2-maxim.uvarov@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 15:48:03 +0000 Message-ID: Subject: Re: [PATCHv8 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 15:48:19 -0000 On Wed, 20 Jan 2021 at 09:27, Maxim Uvarov wrote: > > Implement gpio-pwr driver to allow reboot and poweroff machine. > This is simple driver with just 2 gpios lines. Current use case > is to reboot and poweroff virt machine in secure mode. Secure > pl066 gpio chip is needed for that. > > Signed-off-by: Maxim Uvarov > Reviewed-by: Hao Wu > --- > hw/gpio/Kconfig | 3 ++ > hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > 3 files changed, 74 insertions(+) > create mode 100644 hw/gpio/gpio_pwr.c Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Fri Jan 22 14:52:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l32TU-0005dq-Ob for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 14:52:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32TS-0005by-W1; Fri, 22 Jan 2021 14:52:03 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:49606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32TQ-0005Gr-JP; Fri, 22 Jan 2021 14:52:02 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 17A2BC602E6; Fri, 22 Jan 2021 20:51:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611345114; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Wmcscl1Xb9UoU4w05+zUFfzC7ziHZySaeSCTfo7Q0ys=; b=bW0B7YaJs8tHKwiUR83xhfiKwkZYM0HJk5Gw8OUgd45aHow2Sbq+Lr5mLsYX6qECt8vULG G4cFQ6/Jk9bajQdKqbDWRf0deDLwFZF8ZXBjIwH6lKoe9+2Rw0DCix17AGGvJuMzIZKuZd N6uBuiUtHDKpfNPdnwvL1xlbhwqkhwH5bLTunR9BYsrVoq+Sd3Enq2hffjPlps+29U6AgG O4dpbbJ2Eaacggor6W3xOGaB/nCR1juMQ4oSRxSCYMBIyVx4SP+NR/cDlV0FeEvvToW0Rr DfWGdH74TwMJCefE0Ma4iGM+HLGuG8v6/6V+RAgYj7Y2CwZshbAeH+GpXKvKng== Date: Fri, 22 Jan 2021 20:52:15 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Message-ID: <20210122195215.yw7qoldfdyojsaxn@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-14-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-14-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 19:52:03 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create a fixed-frequency Clock object to be the SYSCLK, and wire it > up to the devices that require it. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/mps2.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c > index f762d1b46af..cd1c215f941 100644 > --- a/hw/arm/mps2.c > +++ b/hw/arm/mps2.c > @@ -46,6 +46,7 @@ > #include "hw/net/lan9118.h" > #include "net/net.h" > #include "hw/watchdog/cmsdk-apb-watchdog.h" > +#include "hw/qdev-clock.h" > #include "qom/object.h" > > typedef enum MPS2FPGAType { > @@ -84,6 +85,7 @@ struct MPS2MachineState { > CMSDKAPBDualTimer dualtimer; > CMSDKAPBWatchdog watchdog; > CMSDKAPBTimer timer[2]; > + Clock *sysclk; > }; > > #define TYPE_MPS2_MACHINE "mps2" > @@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine) > exit(EXIT_FAILURE); > } > > + /* This clock doesn't need migration because it is fixed-frequency */ > + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); > + clock_set_hz(mms->sysclk, SYSCLK_FRQ); > + > /* The FPGA images have an odd combination of different RAMs, > * because in hardware they are different implementations and > * connected to different buses, giving varying performance/size > @@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine) > TYPE_CMSDK_APB_TIMER); > sbd = SYS_BUS_DEVICE(&mms->timer[i]); > qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); > + qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); > sysbus_realize_and_unref(sbd, &error_fatal); > sysbus_mmio_map(sbd, 0, base); > sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); > @@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine) > object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, > TYPE_CMSDK_APB_DUALTIMER); > qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); > + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); > sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, > qdev_get_gpio_in(armv7m, 10)); > @@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine) > object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, > TYPE_CMSDK_APB_WATCHDOG); > qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); > + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); > sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, > qdev_get_gpio_in_named(armv7m, "NMI", 0)); > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 14:52:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l32U7-00068W-8h for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 14:52:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32U6-000670-Dj; Fri, 22 Jan 2021 14:52:42 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:49658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32Ty-0005T9-4Y; Fri, 22 Jan 2021 14:52:42 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 1D6BDC602E6; Fri, 22 Jan 2021 20:52:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611345151; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=XOypW6orXQcKL1DdZ6guwBXdmIKbtJmsHqcnKk03GLg=; b=LfPQBSc8HLx2/MQSAQa3BWMJn9Ye9goxsabsRmI44zDh2dvj3ZExzqREfxSxTsCKyYaezY atf5P5ZHwTDSn7o8iaO+RQNeroJEJMQqwILFY/mLTC40q2W6VsjIY30eh+TEbyLMTR3pSc 08d1tTsx6gC7F9lamT8W59boLs1xN4A7q1R2t3h2PaRY+6sF8nHs94p5Q3P3A0fXPLmZsB y7h0mQek8ZeUmf8nulVv2iC4REEDQ/91InAk3ZDDRgmVLuTv+TEscJFhN22xlygYEmtRrY YkgHGeWtNmG++XC4BSgOlDqp5/KU6+LmeVP0pufdXiVB9JQWOj8zk9ux6Gx6VQ== Date: Fri, 22 Jan 2021 20:52:52 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Message-ID: <20210122195252.vq6jmtdqkqgv53jt@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-15-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-15-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 19:52:42 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create and connect the two clocks needed by the ARMSSE. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/mps2-tz.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c > index 6a9eed9022a..7acdf490f28 100644 > --- a/hw/arm/mps2-tz.c > +++ b/hw/arm/mps2-tz.c > @@ -62,6 +62,7 @@ > #include "hw/net/lan9118.h" > #include "net/net.h" > #include "hw/core/split-irq.h" > +#include "hw/qdev-clock.h" > #include "qom/object.h" > > #define MPS2TZ_NUMIRQ 92 > @@ -100,6 +101,8 @@ struct MPS2TZMachineState { > qemu_or_irq uart_irq_orgate; > DeviceState *lan9118; > SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; > + Clock *sysclk; > + Clock *s32kclk; > }; > > #define TYPE_MPS2TZ_MACHINE "mps2tz" > @@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) > > /* Main SYSCLK frequency in Hz */ > #define SYSCLK_FRQ 20000000 > +/* Slow 32Khz S32KCLK frequency in Hz */ > +#define S32KCLK_FRQ (32 * 1000) > > /* Create an alias of an entire original MemoryRegion @orig > * located at @base in the memory map. > @@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine) > exit(EXIT_FAILURE); > } > > + /* These clocks don't need migration because they are fixed-frequency */ > + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); > + clock_set_hz(mms->sysclk, SYSCLK_FRQ); > + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); > + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); > + > object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, > mmc->armsse_type); > iotkitdev = DEVICE(&mms->iotkit); > @@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine) > OBJECT(system_memory), &error_abort); > qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); > qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); > + qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); > + qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); > > /* > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:00:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l32bw-0000SU-Vq for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:00:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32bu-0000S4-T7; Fri, 22 Jan 2021 15:00:47 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:50026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l32br-0008Uw-Lp; Fri, 22 Jan 2021 15:00:46 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 41BC2C602E6; Fri, 22 Jan 2021 21:00:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611345640; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=+/F7BJg3mZoz1KfDT2WZeYlQBEptz0kAFjeoVnX11wY=; b=d6ZT2chsWAOM+R4moGuNKoO0KRtrt54sEcOS4/tMCaXdwmoaipqaA5se3i54cldeXVqb+j RHctyopjrKk5iUqskKLOO2IC+ZpEVjnr6IJLkIhGBWGf/1ql3sXQDCHmZ/XE2LenkJngQ+ w/LdmiQmMynvuOjzA20sF2iHFRGIV5IfE+XL0HziG+9dijO2s7x7r3/U9A/UuBvCH6D7UE BzA7t/JmMqhY895YLn4YDsnFm0RsUhoPp/XIIbufheBW2e5trEeCYCcsJYlLgXZ2NJKE0m Ec+zEjqNC7D+Efr7M4AzYJ0aifsr3DBp+2jaWeEN0ElWROqm73VarR5/voeZYQ== Date: Fri, 22 Jan 2021 21:01:01 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks Message-ID: <20210122200101.6ebkvkwntmatnwm3@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-16-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-16-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:00:47 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create and connect the two clocks needed by the ARMSSE. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/musca.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/hw/arm/musca.c b/hw/arm/musca.c > index d82bef11cf2..a9292482a06 100644 > --- a/hw/arm/musca.c > +++ b/hw/arm/musca.c > @@ -33,6 +33,7 @@ > #include "hw/misc/tz-ppc.h" > #include "hw/misc/unimp.h" > #include "hw/rtc/pl031.h" > +#include "hw/qdev-clock.h" > #include "qom/object.h" > > #define MUSCA_NUMIRQ_MAX 96 > @@ -82,6 +83,8 @@ struct MuscaMachineState { > UnimplementedDeviceState sdio; > UnimplementedDeviceState gpio; > UnimplementedDeviceState cryptoisland; > + Clock *sysclk; > + Clock *s32kclk; > }; > > #define TYPE_MUSCA_MACHINE "musca" > @@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) > * don't model that in our SSE-200 model yet. > */ > #define SYSCLK_FRQ 40000000 > +/* Slow 32Khz S32KCLK frequency in Hz */ > +#define S32KCLK_FRQ (32 * 1000) > > static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) > { > @@ -367,6 +372,11 @@ static void musca_init(MachineState *machine) > exit(1); > } > > + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); > + clock_set_hz(mms->sysclk, SYSCLK_FRQ); > + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); > + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); > + > object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, > TYPE_SSE200); > ssedev = DEVICE(&mms->sse); > @@ -376,6 +386,8 @@ static void musca_init(MachineState *machine) > qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); > qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); > qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); > + qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); > + qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); > /* > * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for > * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:25:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l330D-0003ZV-6f for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:25:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l330C-0003YX-65; Fri, 22 Jan 2021 15:25:52 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:54336) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3307-0002Xj-Pp; Fri, 22 Jan 2021 15:25:51 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 9428FC602E6; Fri, 22 Jan 2021 21:25:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611347143; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=TdVsPbk1jIzS4QbhB9Mfj4Vc6c2hc42I8DGaj20yQdY=; b=eW0HOg0QFRTvy06az+9ztXTeJmCZiVD9vecBzmvLXfWKxouHPNQbcQZKsE1RGS80wxJgjB 8Jq/EYS6dJQnrWfkX6i4HRaZ5YmAQ/PBK3IjPAZy49SzdaAyISZWyYNywaSUhG1p8Wteip LI9AUr7zGHn1rYfeQZwJQfbREHwuG5NDCiUHGw9xNK+XAsGvXU/4Zbl2O5SZyC6z/WGg2N 2bs7xiNJ8qLoMVvxoMbZgHrLORhOUUqn0t8wOdr8T7arHdJfxPB5PQOiXhs7ciBjIZVwuR kLfZNSpgBlnUTG/KZRhUrHRZWyRG+Bf6Gu4gbhIEV4v0iMfkXE05ypzCNgcLog== Date: Fri, 22 Jan 2021 21:26:04 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Message-ID: <20210122202604.r6e3nyyueqa57nm2@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-17-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-17-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:25:52 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Convert the SSYS code in the Stellaris boards (which encapsulates the > system registers) to a proper QOM device. This will provide us with > somewhere to put the output Clock whose frequency depends on the > setting of the PLL configuration registers. > > This is a migration compatibility break for lm3s811evb, lm3s6965evb. > > We use 3-phase reset here because the Clock will need to propagate > its value in the hold phase. > > For the moment we reset the device during the board creation so that > the system_clock_scale global gets set; this will be removed in a > subsequent commit. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 107 insertions(+), 25 deletions(-) > > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 652823195b1..0194ede2fe0 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp) > > /* System controller. */ > > -typedef struct { > +#define TYPE_STELLARIS_SYS "stellaris-sys" > +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) > + > +struct ssys_state { > + SysBusDevice parent_obj; > + > MemoryRegion iomem; > uint32_t pborctl; > uint32_t ldopctl; > @@ -371,11 +376,18 @@ typedef struct { > uint32_t dcgc[3]; > uint32_t clkvclr; > uint32_t ldoarst; > + qemu_irq irq; > + /* Properties (all read-only registers) */ > uint32_t user0; > uint32_t user1; > - qemu_irq irq; > - stellaris_board_info *board; > -} ssys_state; > + uint32_t did0; > + uint32_t did1; > + uint32_t dc0; > + uint32_t dc1; > + uint32_t dc2; > + uint32_t dc3; > + uint32_t dc4; > +}; > > static void ssys_update(ssys_state *s) > { > @@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = { > > static int ssys_board_class(const ssys_state *s) > { > - uint32_t did0 = s->board->did0; > + uint32_t did0 = s->did0; > switch (did0 & DID0_VER_MASK) { > case DID0_VER_0: > return DID0_CLASS_SANDSTORM; > @@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset, > > switch (offset) { > case 0x000: /* DID0 */ > - return s->board->did0; > + return s->did0; > case 0x004: /* DID1 */ > - return s->board->did1; > + return s->did1; > case 0x008: /* DC0 */ > - return s->board->dc0; > + return s->dc0; > case 0x010: /* DC1 */ > - return s->board->dc1; > + return s->dc1; > case 0x014: /* DC2 */ > - return s->board->dc2; > + return s->dc2; > case 0x018: /* DC3 */ > - return s->board->dc3; > + return s->dc3; > case 0x01c: /* DC4 */ > - return s->board->dc4; > + return s->dc4; > case 0x030: /* PBORCTL */ > return s->pborctl; > case 0x034: /* LDOPCTL */ > @@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = { > .endianness = DEVICE_NATIVE_ENDIAN, > }; > > -static void ssys_reset(void *opaque) > +static void stellaris_sys_reset_enter(Object *obj, ResetType type) > { > - ssys_state *s = (ssys_state *)opaque; > + ssys_state *s = STELLARIS_SYS(obj); > > s->pborctl = 0x7ffd; > s->rcc = 0x078e3ac0; > @@ -661,9 +673,19 @@ static void ssys_reset(void *opaque) > s->rcgc[0] = 1; > s->scgc[0] = 1; > s->dcgc[0] = 1; > +} > + > +static void stellaris_sys_reset_hold(Object *obj) > +{ > + ssys_state *s = STELLARIS_SYS(obj); > + > ssys_calculate_system_clock(s); > } > > +static void stellaris_sys_reset_exit(Object *obj) > +{ > +} > + > static int stellaris_sys_post_load(void *opaque, int version_id) > { > ssys_state *s = opaque; > @@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = { > } > }; > > +static Property stellaris_sys_properties[] = { > + DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), > + DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), > + DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), > + DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), > + DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), > + DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), > + DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), > + DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), > + DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), > + DEFINE_PROP_END_OF_LIST() > +}; > + > +static void stellaris_sys_instance_init(Object *obj) > +{ > + ssys_state *s = STELLARIS_SYS(obj); > + SysBusDevice *sbd = SYS_BUS_DEVICE(s); > + > + memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); > + sysbus_init_mmio(sbd, &s->iomem); > + sysbus_init_irq(sbd, &s->irq); > +} > + > static int stellaris_sys_init(uint32_t base, qemu_irq irq, > stellaris_board_info * board, > uint8_t *macaddr) > { > - ssys_state *s; > + DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > > - s = g_new0(ssys_state, 1); > - s->irq = irq; > - s->board = board; > /* Most devices come preprogrammed with a MAC address in the user data. */ > - s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); > - s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); > + qdev_prop_set_uint32(dev, "user0", > + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); > + qdev_prop_set_uint32(dev, "user1", > + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); > + qdev_prop_set_uint32(dev, "did0", board->did0); > + qdev_prop_set_uint32(dev, "did1", board->did1); > + qdev_prop_set_uint32(dev, "dc0", board->dc0); > + qdev_prop_set_uint32(dev, "dc1", board->dc1); > + qdev_prop_set_uint32(dev, "dc2", board->dc2); > + qdev_prop_set_uint32(dev, "dc3", board->dc3); > + qdev_prop_set_uint32(dev, "dc4", board->dc4); > + > + sysbus_realize_and_unref(sbd, &error_fatal); > + sysbus_mmio_map(sbd, 0, base); > + sysbus_connect_irq(sbd, 0, irq); > + > + /* > + * Normally we should not be resetting devices like this during > + * board creation. For the moment we need to do so, because > + * system_clock_scale will only get set when the STELLARIS_SYS > + * device is reset, and we need its initial value to pass to > + * the watchdog device. This hack can be removed once the > + * watchdog has been converted to use a Clock input instead. > + */ > + device_cold_reset(dev); > > - memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); > - memory_region_add_subregion(get_system_memory(), base, &s->iomem); > - ssys_reset(s); > - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s); > return 0; > } > > - > /* I2C controller. */ > > #define TYPE_STELLARIS_I2C "stellaris-i2c" > @@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = { > .class_init = stellaris_adc_class_init, > }; > > +static void stellaris_sys_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + > + dc->vmsd = &vmstate_stellaris_sys; > + rc->phases.enter = stellaris_sys_reset_enter; > + rc->phases.hold = stellaris_sys_reset_hold; > + rc->phases.exit = stellaris_sys_reset_exit; > + device_class_set_props(dc, stellaris_sys_properties); > +} > + > +static const TypeInfo stellaris_sys_info = { > + .name = TYPE_STELLARIS_SYS, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(ssys_state), > + .instance_init = stellaris_sys_instance_init, > + .class_init = stellaris_sys_class_init, > +}; > + > static void stellaris_register_types(void) > { > type_register_static(&stellaris_i2c_info); > type_register_static(&stellaris_gptm_info); > type_register_static(&stellaris_adc_info); > + type_register_static(&stellaris_sys_info); > } > > type_init(stellaris_register_types) > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:30:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l334Q-0005af-Ic for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:30:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l334P-0005ZD-4M; Fri, 22 Jan 2021 15:30:13 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:55240) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l334N-0004Jn-5B; Fri, 22 Jan 2021 15:30:12 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 2CED5C602E6; Fri, 22 Jan 2021 21:30:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611347408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IBJCMswZP72Qvpkt33ZfcEZ1JJdqFZlP9yhSaRGcdf4=; b=IyfkNHo5QGq3OOuh54bKt3NBCOcUJ4h83FG/TKZbpckzYmuK9rWEXhNxuhqD1H1bwDYLDu ig4h3OQw8zTnq3LWUWSoUC5XyvxehlT7H1LngwX1zncXDlgQBwmVlOrmZ3riPNBbXZj6k0 hkbzdHujq3uj+xjfluChjUAoDk/gOUJdIhEC5ars2Acr41n7JSFd9FexLpTWCg0J3ajwzj FENwJpEyv2BH+usDwpQSMxJAuFviE//0Ji7V/SkPOOy38UUN4wsE/daF+x1x1J6IvEsqQm Ww9KESHnGxuU2qUXUm0UXeRVXRmpYWBlt+XmzKvhN/YSScnNlHp93LHRtjqJJg== Date: Fri, 22 Jan 2021 21:30:29 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Message-ID: <20210122203029.kw74t4lfsbcpufyi@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-18-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-18-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:30:13 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Create and connect the Clock input for the watchdog device on the > Stellaris boards. Because the Stellaris boards model the ability to > change the clock rate by programming PLL registers, we have to create > an output Clock on the ssys_state device and wire it up to the > watchdog. > > Note that the old comment on ssys_calculate_system_clock() got the > units wrong -- system_clock_scale is in nanoseconds, not > milliseconds. Improve the commentary to clarify how we are > calculating the period. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ > 1 file changed, 31 insertions(+), 12 deletions(-) > > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 0194ede2fe0..9b67c739ef2 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -26,6 +26,7 @@ > #include "hw/watchdog/cmsdk-apb-watchdog.h" > #include "migration/vmstate.h" > #include "hw/misc/unimp.h" > +#include "hw/qdev-clock.h" > #include "cpu.h" > #include "qom/object.h" > > @@ -377,6 +378,7 @@ struct ssys_state { > uint32_t clkvclr; > uint32_t ldoarst; > qemu_irq irq; > + Clock *sysclk; > /* Properties (all read-only registers) */ > uint32_t user0; > uint32_t user1; > @@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s) > } > > /* > - * Caculate the sys. clock period in ms. > + * Calculate the system clock period. We only want to propagate > + * this change to the rest of the system if we're not being called > + * from migration post-load. > */ > -static void ssys_calculate_system_clock(ssys_state *s) > +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) > { > + /* > + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input > + * clock is 200MHz, which is a period of 5 ns. Dividing the clock > + * frequency by X is the same as multiplying the period by X. > + */ > if (ssys_use_rcc2(s)) { > system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); > } else { > system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); > } > + clock_set_ns(s->sysclk, system_clock_scale); > + if (propagate_clock) { > + clock_propagate(s->sysclk); > + } > } > > static void ssys_write(void *opaque, hwaddr offset, > @@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset, > s->int_status |= (1 << 6); > } > s->rcc = value; > - ssys_calculate_system_clock(s); > + ssys_calculate_system_clock(s, true); > break; > case 0x070: /* RCC2 */ > if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { > @@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset, > s->int_status |= (1 << 6); > } > s->rcc2 = value; > - ssys_calculate_system_clock(s); > + ssys_calculate_system_clock(s, true); > break; > case 0x100: /* RCGC0 */ > s->rcgc[0] = value; > @@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj) > { > ssys_state *s = STELLARIS_SYS(obj); > > - ssys_calculate_system_clock(s); > + /* OK to propagate clocks from the hold phase */ > + ssys_calculate_system_clock(s, true); > } > > static void stellaris_sys_reset_exit(Object *obj) > @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) > { > ssys_state *s = opaque; > > - ssys_calculate_system_clock(s); > + ssys_calculate_system_clock(s, false); > > return 0; > } > @@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = { > VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), > VMSTATE_UINT32(clkvclr, ssys_state), > VMSTATE_UINT32(ldoarst, ssys_state), > + /* No field for sysclk -- handled in post-load instead */ > VMSTATE_END_OF_LIST() > } > }; > @@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj) > memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->irq); > + s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); > } > > -static int stellaris_sys_init(uint32_t base, qemu_irq irq, > - stellaris_board_info * board, > - uint8_t *macaddr) > +static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, > + stellaris_board_info *board, > + uint8_t *macaddr) > { > DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); > SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > @@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, > */ > device_cold_reset(dev); > > - return 0; > + return dev; > } > > /* I2C controller. */ > @@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > int flash_size; > I2CBus *i2c; > DeviceState *dev; > + DeviceState *ssys_dev; > int i; > int j; > > @@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > } > } > > - stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), > - board, nd_table[0].macaddr.a); > + ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), > + board, nd_table[0].macaddr.a); > > > if (board->dc1 & (1 << 3)) { /* watchdog present */ > @@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > /* system_clock_scale is valid now */ > uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; > qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); > + qdev_connect_clock_in(dev, "WDOGCLK", > + qdev_get_clock_out(ssys_dev, "SYSCLK")); > > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > sysbus_mmio_map(SYS_BUS_DEVICE(dev), > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:33:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l337C-0007oH-D3 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:33:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l337A-0007lu-Am; Fri, 22 Jan 2021 15:33:04 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:55856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3378-0005Yi-5j; Fri, 22 Jan 2021 15:33:03 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id AFDA3C602E6; Fri, 22 Jan 2021 21:32:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611347579; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=faOVIinSqea55p9lVc+8t9GiMOiIjuL60TaUy5QwqYQ=; b=NthCbdQ7dkhnqagpBskgROsqy0FiM6tFIDmXtf2rQMomEc+zlFr+ObmF5Q2H3evtW4Yrf7 Z340F6d+v/FNafmRkFYT8qxiWwYNAXBBHTNwqLwspBBgWJDlEuHo5XQKmFp7qaQblXk9df hZbTmURETBJ/n+KqtygrzAbmHjSRvp8dQo0UKrAX/JvH0yqcySMa6XfKcoRgkdnu8PQNU2 PRQ/xUhHLKr+Xc4AfEQls+O/SzHtNxex0ThH9WBqrj2tSt4sS44KkkyXbTRxBJ199UMHkx iRDTBKOtruwcfMNWQP7e8L5/sMqTBRid4AkNPs+L48BEpT5/5TFvn7YNiwPaWQ== Date: Fri, 22 Jan 2021 21:33:21 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Message-ID: <20210122203321.ondgckxsqdcnksld@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-19-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-19-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:33:04 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Switch the CMSDK APB timer device over to using its Clock input; the > pclk-frq property is now ignored. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c > index c63145ff553..f053146d88f 100644 > --- a/hw/timer/cmsdk-apb-timer.c > +++ b/hw/timer/cmsdk-apb-timer.c > @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) > ptimer_transaction_commit(s->timer); > } > > +static void cmsdk_apb_timer_clk_update(void *opaque) > +{ > + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); > + > + ptimer_transaction_begin(s->timer); > + ptimer_set_period_from_clock(s->timer, s->pclk, 1); > + ptimer_transaction_commit(s->timer); > +} > + > static void cmsdk_apb_timer_init(Object *obj) > { > SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj) > s, "cmsdk-apb-timer", 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->timerint); > - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); > + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", > + cmsdk_apb_timer_clk_update, s); > } > > static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > { > CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); > > - if (s->pclk_frq == 0) { > - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); > + if (!clock_has_source(s->pclk)) { > + error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); > return; > } > > @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) > PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); > > ptimer_transaction_begin(s->timer); > - ptimer_set_freq(s->timer, s->pclk_frq); > + ptimer_set_period_from_clock(s->timer, s->pclk, 1); > ptimer_transaction_commit(s->timer); > } > > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:48:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l33MW-0008SA-HP for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:48:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l33MU-0008Nx-Oq; Fri, 22 Jan 2021 15:48:54 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:59148) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l33MS-00043L-5t; Fri, 22 Jan 2021 15:48:54 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 40339C602E6; Fri, 22 Jan 2021 21:48:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611348529; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=chIzq8MEXdiAW6O6Ymh0ZQmZM6DvTGAkWe/ozEQ+0lY=; b=CsYsbXavSj9HGbLQ0yZY/pHBO8o9xPw09mpXXU0Ne2JjWFtb+sdSLKMiq4XQNZZYYxALst lPL3WeoNw+xMN8wpL5GWD3LE8gjf/uPLY6rYD5tYSKYtC/Tr++I+8R1KWsv1gNdqow2nvC YdI6FFqWpeeKUGPpDFfsnoiXn76qQs4GwJjlYIAUofkC7WiWoqI9Ruq9JwdhEmEWidQh99 X3mYvbQwNfB44So5byw8kQqarpSpmeaV8AW0bkBKN4019AABvandBqZDXBV+6zRUrBL/KD Yii2U/fhwJ45Ndesn5+XMtJeECuJHggvNm1svu+VsSBz5gSNrt2mNKfDiWLXfQ== Date: Fri, 22 Jan 2021 21:49:10 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input Message-ID: <20210122204910.xadaf4zutpbu4qp5@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-20-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-20-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:48:55 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Switch the CMSDK APB dualtimer device over to using its Clock input; > the pclk-frq property is now ignored. > > Signed-off-by: Peter Maydell > --- > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 5 deletions(-) > > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c > index 781b496037b..828127b366f 100644 > --- a/hw/timer/cmsdk-apb-dualtimer.c > +++ b/hw/timer/cmsdk-apb-dualtimer.c > @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) > qemu_set_irq(s->timerintc, timintc); > } > > +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) > +{ > + /* Return the divisor set by the current CONTROL.PRESCALE value */ > + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { > + case 0: > + return 1; > + case 1: > + return 16; > + case 2: > + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ > + return 256; > + default: > + g_assert_not_reached(); > + } > +} > + > static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > uint32_t newctrl) > { > @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > default: > g_assert_not_reached(); > } > - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); Just a small cosmetic note, maybe you can use your new cmsdk_dualtimermod_divisor function to factor out the switch above? Something like: if (changed & R_CONTROL_PRESCALE_MASK) { if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) { qemu_log_mask(LOG_GUEST_ERROR, "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11" " is undefined behaviour\n"); } ptimer_set_period_from_clock(m->timer, m->parent->timclk, cmsdk_dualtimermod_divisor(m)); } With or without this modification: Reviewed-by: Luc Michel Luc > } > > if (changed & R_CONTROL_MODE_MASK) { > @@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) > * limit must both be set to 0xffff, so we wrap at 16 bits. > */ > ptimer_set_limit(m->timer, 0xffff, 1); > - ptimer_set_freq(m->timer, m->parent->pclk_frq); > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, > + cmsdk_dualtimermod_divisor(m)); > ptimer_transaction_commit(m->timer); > } > > @@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) > s->timeritop = 0; > } > > +static void cmsdk_apb_dualtimer_clk_update(void *opaque) > +{ > + CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque); > + int i; > + > + for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { > + CMSDKAPBDualTimerModule *m = &s->timermod[i]; > + ptimer_transaction_begin(m->timer); > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, > + cmsdk_dualtimermod_divisor(m)); > + ptimer_transaction_commit(m->timer); > + } > +} > + > static void cmsdk_apb_dualtimer_init(Object *obj) > { > SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > @@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) > for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { > sysbus_init_irq(sbd, &s->timermod[i].timerint); > } > - s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); > + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", > + cmsdk_apb_dualtimer_clk_update, s); > } > > static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) > @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) > CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev); > int i; > > - if (s->pclk_frq == 0) { > - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); > + if (!clock_has_source(s->timclk)) { > + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected"); > return; > } > > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 15:51:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l33OX-0002ST-S7 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 15:51:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l33OW-0002Qu-0e; Fri, 22 Jan 2021 15:51:00 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:59586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l33OS-0004yF-TC; Fri, 22 Jan 2021 15:50:59 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id BAC03C602E6; Fri, 22 Jan 2021 21:50:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611348653; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=nwhTb5hRhE9sP4Jq8+AVrFKAdewtctj+NqJl54WNC5Q=; b=O3GKEaHH+EESnikQTNOqpJQSEM06Gebuo/cLdJg0ffRW1m1zV1EAjx6mdQlZ+KgCX1EM+P ypeCvBN/rrpnNO3sCz272YF11sL4BRzO6EXiLnaNT8L3NqV9VPvYVYIYSR1lUcEJiw6eEu UbqaIv/oGecxhHlOq5sLhILUmC5BY4kgOgiJ6Qb1sZlLDmdiNYEr+MSzh1/Ky20ob3ZLXq 9t+Q68NvcZCibV27kYZulTwAt0gvTAbixqXgzUnnf9ldAKyX38NHxB4ejDtruFQjNlzYCM F4Q6SjA/jxd9tgkus8Dspk2dEjRwiJehHR++RcN2Fd0X7jpDqf4qr0ZrjabDLw== Date: Fri, 22 Jan 2021 21:51:15 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input Message-ID: <20210122205115.e7b3dhu5jm7gblta@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-21-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-21-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 20:51:00 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Switch the CMSDK APB watchdog device over to using its Clock input; > the wdogclk_frq property is now ignored. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c > index b03bcb73628..9cad0c67da4 100644 > --- a/hw/watchdog/cmsdk-apb-watchdog.c > +++ b/hw/watchdog/cmsdk-apb-watchdog.c > @@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) > ptimer_transaction_commit(s->timer); > } > > +static void cmsdk_apb_watchdog_clk_update(void *opaque) > +{ > + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); > + > + ptimer_transaction_begin(s->timer); > + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); > + ptimer_transaction_commit(s->timer); > +} > + > static void cmsdk_apb_watchdog_init(Object *obj) > { > SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > @@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) > s, "cmsdk-apb-watchdog", 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > sysbus_init_irq(sbd, &s->wdogint); > - s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); > + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", > + cmsdk_apb_watchdog_clk_update, s); > > s->is_luminary = false; > s->id = cmsdk_apb_watchdog_id; > @@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) > { > CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); > > - if (s->wdogclk_frq == 0) { > + if (!clock_has_source(s->wdogclk)) { > error_setg(errp, > - "CMSDK APB watchdog: wdogclk-frq property must be set"); > + "CMSDK APB watchdog: WDOGCLK clock must be connected"); > return; > } > > @@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) > PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); > > ptimer_transaction_begin(s->timer); > - ptimer_set_freq(s->timer, s->wdogclk_frq); > + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); > ptimer_transaction_commit(s->timer); > } > > -- > 2.20.1 > -- From MAILER-DAEMON Fri Jan 22 16:41:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l34BV-00041g-9o for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 16:41:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l34BS-00040d-JA for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:41:34 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:43129) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l34BQ-0002XT-OX for qemu-arm@nongnu.org; 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Fri, 22 Jan 2021 13:41:29 -0800 (PST) MIME-Version: 1.0 References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-20-peter.maydell@linaro.org> <20210122204910.xadaf4zutpbu4qp5@sekoia-pc.home.lmichel.fr> In-Reply-To: <20210122204910.xadaf4zutpbu4qp5@sekoia-pc.home.lmichel.fr> From: Peter Maydell Date: Fri, 22 Jan 2021 21:41:18 +0000 Message-ID: Subject: Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input To: Luc Michel Cc: qemu-arm , QEMU Developers , Damien Hedde , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 21:41:34 -0000 On Fri, 22 Jan 2021 at 20:48, Luc Michel wrote: > > On 19:06 Thu 21 Jan , Peter Maydell wrote: > > Switch the CMSDK APB dualtimer device over to using its Clock input; > > the pclk-frq property is now ignored. > > > > Signed-off-by: Peter Maydell > > --- > > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- > > 1 file changed, 37 insertions(+), 5 deletions(-) > > > > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c > > index 781b496037b..828127b366f 100644 > > --- a/hw/timer/cmsdk-apb-dualtimer.c > > +++ b/hw/timer/cmsdk-apb-dualtimer.c > > @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) > > qemu_set_irq(s->timerintc, timintc); > > } > > > > +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) > > +{ > > + /* Return the divisor set by the current CONTROL.PRESCALE value */ > > + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { > > + case 0: > > + return 1; > > + case 1: > > + return 16; > > + case 2: > > + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ > > + return 256; > > + default: > > + g_assert_not_reached(); > > + } > > +} > > + > > static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > > uint32_t newctrl) > > { > > @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > > default: > > g_assert_not_reached(); > > } > > - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); > > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); > > Just a small cosmetic note, maybe you can use your new > cmsdk_dualtimermod_divisor function to factor out the switch above? > Something like: > > if (changed & R_CONTROL_PRESCALE_MASK) { > if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) { > qemu_log_mask(LOG_GUEST_ERROR, > "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11" > " is undefined behaviour\n"); > } > > ptimer_set_period_from_clock(m->timer, m->parent->timclk, > cmsdk_dualtimermod_divisor(m)); > } Nope, because cmsdk_dualtimermod_divisor() uses the current m->control value, and at this point in the code we need the divisor from the new control value which isn't in m->control yet. I liked the slight duplication better than either having to pass m->control in in all the other callsites or trying to refactor the control write handling so that m->control is updated before this point in the code. thanks -- PMM From MAILER-DAEMON Fri Jan 22 16:52:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l34M8-0000Ta-BA for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 16:52:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l34M4-0000Sd-Nn for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:33 -0500 Received: from mail-lj1-x230.google.com ([2a00:1450:4864:20::230]:44316) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l34M2-0007GY-8s for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:32 -0500 Received: by mail-lj1-x230.google.com with SMTP id f2so3009011ljp.11 for ; Fri, 22 Jan 2021 13:52:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F3NmXY82AVsBjMLhUcX3GeVAxWcAOFNsrsf94y63Cq0=; b=pRFYWlBCZbepop+QMXe9sLJGi2YLCVzJ2inK2+C0xo8fpz5ZEMHKbGgtSK0sN0KUC3 WYf5UqV+6HW5fX9RQMnQt+ryXl8zAriZx57RgrXXqy7my92f/CQtx/lVpokQhF+gbfOo FL7ROmgPh+SM48wMuAf+NJwOnyPS7Aj/IeN7apxNmtRR3yGLeoxVD3K9DEUha4QSpsiX aMNVswN5ApqFeAMDppx77/QO7yk02KrEEwU1Cw964dplfy/jCGzCddrbyIWJD+P+r0dH ooXBCAMrevPFUXFGMpHffJ/LetDzUYkoY90hATKU2O3a3bcy6jN9Bhtn6HOryTGtdLY8 32sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F3NmXY82AVsBjMLhUcX3GeVAxWcAOFNsrsf94y63Cq0=; b=uDIiXPflGoKZk8kANIWjjp2y/h76KB7buL9hnDvk2v73noJdgLZLgFSqq6Z8NprwjG w5U7+Jb/+KxSQrsPoPXPSgJ40q3RJ9nNKnV0zXkpuINCGsslkJm845IMdhzyDStrnWgz Pa79QxoPmH8SIHjPaiPH9ptnDeqvBvV/8OEdYrLqr1TTo+6nYoD4V/F5inJuN/rlDz/8 mhb088fm46/l3qWCD1MSGdDca7Jl0iCXS1oCDkCbmCvIsJ73Uh1pkIRdpB2cycBn7hZQ NFw1dt55y7zQWR1RHvlbkUUxlNeIv03xlDti+LmJfnQjKsZ/pUM7eGGcAnobMaWee7jm dEjg== X-Gm-Message-State: AOAM531iiMXYTvplQOlXJeHGYXSNk3SF6N27bgM7iSKOoM95TGyZEaoE ZrqxjLy7/WgyMKiIDJpjg1q9K7pN9znM0g== X-Google-Smtp-Source: ABdhPJw9vqgajjbc+EKO0WgYhB80EQqZSlG82msKcTCUHfy07xEyaaF/pYqXXQ2cyBbfDmkXk+zVJQ== X-Received: by 2002:a2e:96d8:: with SMTP id d24mr1586288ljj.62.1611352346168; Fri, 22 Jan 2021 13:52:26 -0800 (PST) Received: from localhost.localdomain ([176.59.42.245]) by smtp.gmail.com with ESMTPSA id a11sm1019890lfl.22.2021.01.22.13.52.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 13:52:25 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv9 0/3] arm-virt: add secure pl061 for reset/power down Date: Sat, 23 Jan 2021 00:52:19 +0300 Message-Id: <20210122215222.8320-1-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 21:52:34 -0000 v9: - cosmetic changes (move if from patch2 to patch3, rename function name and define). v8: - use gpio 0 and 1, align dtb with kernel gpio-restart, gpio-poweroff, change define names, trigger on upper front. (Peter Maydell). v7: - same as v6, but resplit patches: patch 2 no function changes and refactor gpio setup for virt platfrom and patch 3 adds secure gpio. v6: - 64k align gpio memory region (Andrew Jones) - adjusted memory region to map this address in the corresponding atf patch v5: - removed vms flag, added fdt (Andrew Jones) - added patch3 to combine secure and non secure pl061. It has to be more easy to review if this changes are in the separate patch. v4: rework patches accodring to Peter Maydells comments: - split patches on gpio-pwr driver and arm-virt integration. - start secure gpio only from virt-6.0. - rework qemu interface for gpio-pwr to use 2 named gpio. - put secure gpio to secure name space. v3: added missed include qemu/log.h for qemu_log(.. v2: replace printf with qemu_log (Philippe Mathieu-Daudé) This patch works together with ATF patch: https://github.com/muvarov/arm-trusted-firmware/commit/886965bddb0624bdf85103efb2b39fd4eb73d89b Maxim Uvarov (3): hw: gpio: implement gpio-pwr driver for qemu reset/poweroff arm-virt: refactor gpios creation arm-virt: add secure pl061 for reset/power down hw/arm/Kconfig | 1 + hw/arm/virt.c | 111 ++++++++++++++++++++++++++++++++++-------- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 ++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + include/hw/arm/virt.h | 2 + 6 files changed, 167 insertions(+), 21 deletions(-) create mode 100644 hw/gpio/gpio_pwr.c -- 2.17.1 From MAILER-DAEMON Fri Jan 22 16:52:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l34MC-0000WR-JR for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 16:52:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l34M7-0000T9-4v for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:35 -0500 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]:39423) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l34M5-0007IW-5P for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:34 -0500 Received: by mail-lf1-x130.google.com with SMTP id h7so9601220lfc.6 for ; Fri, 22 Jan 2021 13:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iEyWJZhAZPnLFDMgDIpbGYkV2+NYdmfH2gdbQlh81PQ=; b=x1VB69CEfqvH9ZKopFDbeFrgpyFv3/alukJxhChqnrbFmVYswJ/YZ5GEYvLRjOZ+ys 3iqxdCKmuEVEXEwpZqgxboa2tA6IhodXppBGFUWdhpYk4t4zVU1OyRP8mCIARJIeoHn/ PaaaYe0gsPLipDB3llTTFwFe8cxOOMjQLDwErVLGHDYwjIZIfcXCiGzlqpLGrcFi1VQS 7K6M94OFL4OG8OFcTIrD0pljjK3dVQj1BNi8z8xU8wCxrDsPE/ISxIvD9HpsDoscY5y+ 41IfLRKq3ISjLHLUb6VsH1Wb6M06gIzuEtcVn4p57EjsDTRe8t6/hYKwwEBrzyidhAzT XsOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iEyWJZhAZPnLFDMgDIpbGYkV2+NYdmfH2gdbQlh81PQ=; b=Vbms9XmtisOhIoQMV8an6IRXcIfXTRj4s1lzakrSD/PyB7ucoiO230OPdx4/QgTQmG Zu44ClMz9to5Rhv/hbPYjsM2Aqx2qcxmDecymk2nZ4sLSpiuXTr7B28nGo1LrWqzIVia c9LT+ArLUyun4jjzNPmwLk8DkgVwQcxZf1/Uj3SCQOxr2cFMPtGX3Aj7k7O2TDAiCUxP 0BFOPa9tIUbFhoMHPWn+4r7yGKB72CAJI/sHO/YbxADbAV9yFxjSoNNBp+JX9pnNRSRq Z9PfPHjHx+uvR5pYzzJxUmQUOpVSNA6Jp5ENkEPlU3pUEnhypur/elSwvb7fpmQqKpmw 519g== X-Gm-Message-State: AOAM531eXQ0Q1OFwmlNTVGfgANJRVhlu8GMmJQ6EG9p6e05NKlT9ZmAn /rrADz+qyMDvAvyKVxVqbaSot3T8Idk/rw== X-Google-Smtp-Source: ABdhPJwnQFj586CwgXNThKYZDdLaYntRpu+M4FBTB0mDZIUGJS4LSUryP7vbHgrLfoHiAJwWbtUimw== X-Received: by 2002:a19:a0a:: with SMTP id 10mr250338lfk.397.1611352351093; Fri, 22 Jan 2021 13:52:31 -0800 (PST) Received: from localhost.localdomain ([176.59.42.245]) by smtp.gmail.com with ESMTPSA id a11sm1019890lfl.22.2021.01.22.13.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 13:52:30 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv9 1/3] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff Date: Sat, 23 Jan 2021 00:52:20 +0300 Message-Id: <20210122215222.8320-2-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122215222.8320-1-maxim.uvarov@linaro.org> References: <20210122215222.8320-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 21:52:36 -0000 Implement gpio-pwr driver to allow reboot and poweroff machine. This is simple driver with just 2 gpios lines. Current use case is to reboot and poweroff virt machine in secure mode. Secure pl066 gpio chip is needed for that. Signed-off-by: Maxim Uvarov Reviewed-by: Hao Wu Reviewed-by: Peter Maydell --- hw/gpio/Kconfig | 3 ++ hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 74 insertions(+) create mode 100644 hw/gpio/gpio_pwr.c diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..f0e7405f6e 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -8,5 +8,8 @@ config PL061 config GPIO_KEY bool +config GPIO_PWR + bool + config SIFIVE_GPIO bool diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c new file mode 100644 index 0000000000..7714fa0dc4 --- /dev/null +++ b/hw/gpio/gpio_pwr.c @@ -0,0 +1,70 @@ +/* + * GPIO qemu power controller + * + * Copyright (c) 2020 Linaro Limited + * + * Author: Maxim Uvarov + * + * Virtual gpio driver which can be used on top of pl061 + * to reboot and shutdown qemu virtual machine. One of use + * case is gpio driver for secure world application (ARM + * Trusted Firmware.). + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * QEMU interface: + * two named input GPIO lines: + * 'reset' : when asserted, trigger system reset + * 'shutdown' : when asserted, trigger system shutdown + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "sysemu/runstate.h" + +#define TYPE_GPIOPWR "gpio-pwr" +OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR) + +struct GPIO_PWR_State { + SysBusDevice parent_obj; +}; + +static void gpio_pwr_reset(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + +static void gpio_pwr_shutdown(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void gpio_pwr_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1); + qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1); +} + +static const TypeInfo gpio_pwr_info = { + .name = TYPE_GPIOPWR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(GPIO_PWR_State), + .instance_init = gpio_pwr_init, +}; + +static void gpio_pwr_register_types(void) +{ + type_register_static(&gpio_pwr_info); +} + +type_init(gpio_pwr_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 5c0a7d7b95..79568f00ce 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -1,5 +1,6 @@ softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) -- 2.17.1 From MAILER-DAEMON Fri Jan 22 16:52:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l34MF-0000c4-CW for mharc-qemu-arm@gnu.org; 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Fri, 22 Jan 2021 13:52:31 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv9 2/3] arm-virt: refactor gpios creation Date: Sat, 23 Jan 2021 00:52:21 +0300 Message-Id: <20210122215222.8320-3-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122215222.8320-1-maxim.uvarov@linaro.org> References: <20210122215222.8320-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=maxim.uvarov@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 21:52:38 -0000 No functional change. Just refactor code to better support secure and normal world gpios. Signed-off-by: Maxim Uvarov Reviewed-by: Andrew Jones --- hw/arm/virt.c | 57 ++++++++++++++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96985917d3..a135316741 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -820,17 +820,43 @@ static void virt_powerdown_req(Notifier *n, void *opaque) } } -static void create_gpio(const VirtMachineState *vms) +static void create_gpio_keys(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + gpio_key_dev = sysbus_create_simple("gpio-key", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", + "label", "GPIO Key Poweroff"); + qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", + KEY_POWER); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", + "gpios", phandle, 3, 0); +} + +static void create_gpio_devices(const VirtMachineState *vms, int gpio, + MemoryRegion *mem) { char *nodename; DeviceState *pl061_dev; - hwaddr base = vms->memmap[VIRT_GPIO].base; - hwaddr size = vms->memmap[VIRT_GPIO].size; - int irq = vms->irqmap[VIRT_GPIO]; + hwaddr base = vms->memmap[gpio].base; + hwaddr size = vms->memmap[gpio].size; + int irq = vms->irqmap[gpio]; const char compat[] = "arm,pl061\0arm,primecell"; + SysBusDevice *s; - pl061_dev = sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); + pl061_dev = qdev_new("pl061"); + s = SYS_BUS_DEVICE(pl061_dev); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); nodename = g_strdup_printf("/pl061@%" PRIx64, base); @@ -847,21 +873,10 @@ static void create_gpio(const VirtMachineState *vms) qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); - gpio_key_dev = sysbus_create_simple("gpio-key", -1, - qdev_get_gpio_in(pl061_dev, 3)); - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); - - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", - "label", "GPIO Key Poweroff"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", - KEY_POWER); - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", - "gpios", phandle, 3, 0); g_free(nodename); + + /* Child gpio devices */ + create_gpio_keys(vms, pl061_dev, phandle); } static void create_virtio_devices(const VirtMachineState *vms) @@ -1990,7 +2005,7 @@ static void machvirt_init(MachineState *machine) if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev = create_acpi_ged(vms); } else { - create_gpio(vms); + create_gpio_devices(vms, VIRT_GPIO, sysmem); } /* connect powerdown request */ -- 2.17.1 From MAILER-DAEMON Fri Jan 22 16:52:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l34MG-0000df-38 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 16:52:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l34MB-0000VY-7o for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:40 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:36808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l34M8-0007K7-6Z for qemu-arm@nongnu.org; Fri, 22 Jan 2021 16:52:39 -0500 Received: by mail-lf1-x131.google.com with SMTP id o13so9616408lfr.3 for ; Fri, 22 Jan 2021 13:52:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; 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Fri, 22 Jan 2021 13:52:34 -0800 (PST) Received: from localhost.localdomain ([176.59.42.245]) by smtp.gmail.com with ESMTPSA id a11sm1019890lfl.22.2021.01.22.13.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 13:52:33 -0800 (PST) From: Maxim Uvarov To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, tf-a@lists.trustedfirmware.org, Jose.Marinho@arm.com, f4bug@amsat.org, drjones@redhat.com, Maxim Uvarov Subject: [PATCHv9 3/3] arm-virt: add secure pl061 for reset/power down Date: Sat, 23 Jan 2021 00:52:22 +0300 Message-Id: <20210122215222.8320-4-maxim.uvarov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122215222.8320-1-maxim.uvarov@linaro.org> References: <20210122215222.8320-1-maxim.uvarov@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=maxim.uvarov@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 21:52:40 -0000 Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov Reviewed-by: Andrew Jones --- hw/arm/Kconfig | 1 + hw/arm/virt.c | 56 ++++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 2 ++ 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0a242e4c5d..13cc42dcc8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -17,6 +17,7 @@ config ARM_VIRT select PL011 # UART select PL031 # RTC select PL061 # GPIO + select GPIO_PWR select PLATFORM_BUS select SMBIOS select VIRTIO_MMIO diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a135316741..bc99b5419d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -153,6 +153,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, + [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -841,6 +842,43 @@ static void create_gpio_keys(const VirtMachineState *vms, "gpios", phandle, 3, 0); } +#define SECURE_GPIO_POWEROFF 0 +#define SECURE_GPIO_RESET 1 + +static void create_secure_gpio_pwr(const VirtMachineState *vms, + DeviceState *pl061_dev, + uint32_t phandle) +{ + DeviceState *gpio_pwr_dev; + + /* gpio-pwr */ + gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); + + /* connect secure pl061 to gpio-pwr */ + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, + qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); + qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, + qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-poweroff"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "compatible", + "gpio-poweroff"); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-poweroff", + "gpios", phandle, SECURE_GPIO_POWEROFF, 0); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "secure-status", + "okay"); + + qemu_fdt_add_subnode(vms->fdt, "/gpio-restart"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "compatible", + "gpio-restart"); + qemu_fdt_setprop_cells(vms->fdt, "/gpio-restart", + "gpios", phandle, SECURE_GPIO_RESET, 0); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "secure-status", + "okay"); +} + static void create_gpio_devices(const VirtMachineState *vms, int gpio, MemoryRegion *mem) { @@ -873,10 +911,19 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio, qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); + if (gpio != VIRT_GPIO) { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); + } g_free(nodename); /* Child gpio devices */ - create_gpio_keys(vms, pl061_dev, phandle); + if (gpio == VIRT_GPIO) { + create_gpio_keys(vms, pl061_dev, phandle); + } else { + create_secure_gpio_pwr(vms, pl061_dev, phandle); + } } static void create_virtio_devices(const VirtMachineState *vms) @@ -2008,6 +2055,10 @@ static void machvirt_init(MachineState *machine) create_gpio_devices(vms, VIRT_GPIO, sysmem); } + if (vms->secure && !vmc->no_secure_gpio) { + create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); + } + /* connect powerdown request */ vms->powerdown_notifier.notify = virt_powerdown_req; qemu_register_powerdown_notifier(&vms->powerdown_notifier); @@ -2623,8 +2674,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0) static void virt_machine_5_2_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_6_0_options(mc); compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); + vmc->no_secure_gpio = true; } DEFINE_VIRT_MACHINE(5, 2) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab49..6f6c85ffcf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -81,6 +81,7 @@ enum { VIRT_GPIO, VIRT_SECURE_UART, VIRT_SECURE_MEM, + VIRT_SECURE_GPIO, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, @@ -127,6 +128,7 @@ struct VirtMachineClass { bool kvm_no_adjvtime; bool no_kvm_steal_time; bool acpi_expose_flash; + bool no_secure_gpio; }; struct VirtMachineState { -- 2.17.1 From MAILER-DAEMON Fri Jan 22 18:34:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l35x2-00055M-V3 for mharc-qemu-arm@gnu.org; Fri, 22 Jan 2021 18:34:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l35wy-00054w-Rz for qemu-arm@nongnu.org; Fri, 22 Jan 2021 18:34:45 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:35976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l35ww-0007zX-Fg for qemu-arm@nongnu.org; Fri, 22 Jan 2021 18:34:44 -0500 Received: by mail-ed1-x536.google.com with SMTP id d2so4887452edz.3 for ; Fri, 22 Jan 2021 15:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; 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Fri, 22 Jan 2021 15:34:40 -0800 (PST) MIME-Version: 1.0 References: <20210122215222.8320-1-maxim.uvarov@linaro.org> In-Reply-To: <20210122215222.8320-1-maxim.uvarov@linaro.org> From: Peter Maydell Date: Fri, 22 Jan 2021 23:34:29 +0000 Message-ID: Subject: Re: [PATCHv9 0/3] arm-virt: add secure pl061 for reset/power down To: Maxim Uvarov Cc: qemu-arm , QEMU Developers , tf-a@lists.trustedfirmware.org, Jose Marinho , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2021 23:34:45 -0000 On Fri, 22 Jan 2021 at 21:52, Maxim Uvarov wrote: > > v9: - cosmetic changes (move if from patch2 to patch3, rename function n= ame > and define). > v8: - use gpio 0 and 1, align dtb with kernel gpio-restart, gpio-powerof= f, > change define names, trigger on upper front. (Peter Maydell). > v7: - same as v6, but resplit patches: patch 2 no function changes and r= efactor > gpio setup for virt platfrom and patch 3 adds secure gpio. > v6: - 64k align gpio memory region (Andrew Jones) > - adjusted memory region to map this address in the corresponding at= f patch > v5: - removed vms flag, added fdt (Andrew Jones) > - added patch3 to combine secure and non secure pl061. It has to be > more easy to review if this changes are in the separate patch. > v4: rework patches accodring to Peter Maydells comments: > - split patches on gpio-pwr driver and arm-virt integration. > - start secure gpio only from virt-6.0. > - rework qemu interface for gpio-pwr to use 2 named gpio. > - put secure gpio to secure name space. > v3: added missed include qemu/log.h for qemu_log(.. > v2: replace printf with qemu_log (Philippe Mathieu-Daud=C3=A9) > > This patch works together with ATF patch: > https://github.com/muvarov/arm-trusted-firmware/commit/886965bddb= 0624bdf85103efb2b39fd4eb73d89b > > Maxim Uvarov (3): > hw: gpio: implement gpio-pwr driver for qemu reset/poweroff > arm-virt: refactor gpios creation > arm-virt: add secure pl061 for reset/power down Applied to target-arm.next, thanks. I realized we forgot the documentation, so I'm going to squash this change in to patch 3: --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -43,6 +43,8 @@ The virt board supports: - Secure-World-only devices if the CPU has TrustZone: - A second PL011 UART + - A second PL061 GPIO controller, with GPIO lines for triggering + a system reset or system poweroff - A secure flash memory - 16MB of secure RAM -- PMM From MAILER-DAEMON Sat Jan 23 14:58:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3P3e-00017A-0J for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 14:58:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3P3Z-00016e-TM; Sat, 23 Jan 2021 14:58:50 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:51834) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3P3U-0005Um-2v; Sat, 23 Jan 2021 14:58:48 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id F1386C602E6; Sat, 23 Jan 2021 20:58:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611431918; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=FaDpLnjgBAc1P1v9+G3Z98irkzGLB2axmdOyN1CrnMQ=; b=cziHh6YbnJGkDgtP1bWUuyZNYDnoWreem1XpiZ3YMK0mc8Je9UHrxiXuuxOtXw1HGvJtp7 AgdRscHEiQG88Dt/fBFD3cV/1h4fMD5Mw4D8Xdo0cKf3Ueo8J2sA1gs0EBanDenGlcDezs K2lq/B93Co5yTogoQKl+TeRvVt2Yu0qRhb4x3WDC9T13dVqmDF0aHOcMCVFXyGPOAdhWFD /aBLPynRbTDSjhjouX3oHsymsGjKorOSQDr+j8um+WrpS/XerlC/OFcYRJ0cMbozr2cufd a7f11hlo2lE3gr7dBvH5N9WGNBXFmfCfuIZYqInpGMzg7JUHt6tB1Fs3KSNNYg== Date: Sat, 23 Jan 2021 20:58:59 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm , QEMU Developers , Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input Message-ID: <20210123195859.btxj66mgka4c7s62@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-20-peter.maydell@linaro.org> <20210122204910.xadaf4zutpbu4qp5@sekoia-pc.home.lmichel.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 19:58:52 -0000 On 21:41 Fri 22 Jan , Peter Maydell wrote: > On Fri, 22 Jan 2021 at 20:48, Luc Michel wrote: > > > > On 19:06 Thu 21 Jan , Peter Maydell wrote: > > > Switch the CMSDK APB dualtimer device over to using its Clock input; > > > the pclk-frq property is now ignored. > > > > > > Signed-off-by: Peter Maydell > > > --- > > > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- > > > 1 file changed, 37 insertions(+), 5 deletions(-) > > > > > > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c > > > index 781b496037b..828127b366f 100644 > > > --- a/hw/timer/cmsdk-apb-dualtimer.c > > > +++ b/hw/timer/cmsdk-apb-dualtimer.c > > > @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) > > > qemu_set_irq(s->timerintc, timintc); > > > } > > > > > > +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) > > > +{ > > > + /* Return the divisor set by the current CONTROL.PRESCALE value */ > > > + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { > > > + case 0: > > > + return 1; > > > + case 1: > > > + return 16; > > > + case 2: > > > + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ > > > + return 256; > > > + default: > > > + g_assert_not_reached(); > > > + } > > > +} > > > + > > > static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > > > uint32_t newctrl) > > > { > > > @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, > > > default: > > > g_assert_not_reached(); > > > } > > > - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); > > > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); > > > > Just a small cosmetic note, maybe you can use your new > > cmsdk_dualtimermod_divisor function to factor out the switch above? > > Something like: > > > > if (changed & R_CONTROL_PRESCALE_MASK) { > > if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) { > > qemu_log_mask(LOG_GUEST_ERROR, > > "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11" > > " is undefined behaviour\n"); > > } > > > > ptimer_set_period_from_clock(m->timer, m->parent->timclk, > > cmsdk_dualtimermod_divisor(m)); > > } > > Nope, because cmsdk_dualtimermod_divisor() uses the current > m->control value, and at this point in the code we need the > divisor from the new control value which isn't in m->control yet. > I liked the slight duplication better than either having to > pass m->control in in all the other callsites or trying to > refactor the control write handling so that m->control is > updated before this point in the code. Oops yes I missed that. Sure make sense, forget what I said. > > thanks > -- PMM -- From MAILER-DAEMON Sat Jan 23 15:31:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3PYi-00054v-EX for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 15:31:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PYh-00054f-Bs; Sat, 23 Jan 2021 15:30:59 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58286) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PYf-0003QE-7G; Sat, 23 Jan 2021 15:30:59 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 9A9E8C602E6; Sat, 23 Jan 2021 21:30:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611433853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Up9eZMVcclbqdpC4POjfNn3Ho4ZJEmSotsDbxz+VVAA=; b=jTvjIQ6pYgggpDprkxXxi0cu9yA/zHuZ0lNsIRATt2ct5bnjtUii8ogmayYgM8zn+lMri0 H8u7wCGvwnSPQG+UL/9oMC1CD2GNjCILrA7DsfLLI0nabhHwOwlI56Ljsz1c4Rl5KcffYU M/XU7lyqypmK+YUwodHgcbays/LgCrSz0Gw8isUMBvBxcJiF2Hv9AAhFEh7BkS9ys/wZ6e BMBNoVoeZAjBQUgoecfGIb/+LdHWYFRrpsKQb8Pp+HMNh2pYwhzPT14CuUrQgGRkwXMOK5 QIbrdJyUXQUkDw9Z6uAhRQiOX5RaaJ+uoGILF0iG/opAoy3aaj3giBkw8CJi9g== Date: Sat, 23 Jan 2021 21:31:15 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Message-ID: <20210123203115.5wz66nu5z3faj3no@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-23-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-23-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 20:30:59 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Use the MAINCLK Clock input to set the system_clock_scale variable > rather than using the mainclk_frq property. > > Signed-off-by: Peter Maydell > --- > At some point we should make the SysTick take a Clock itself so > that we can get rid of the system_clock_scale global entirely. > (In fact we want two Clocks: one that is the CPU clock and one > for the 'external reference clock' whose period is currently > hardcoded at 1000ns in systick_scale()...) > --- > hw/arm/armsse.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index 4349ce9bfdb..1da0c1be4c7 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) > qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); > } > > +static void armsse_mainclk_update(void *opaque) > +{ > + ARMSSE *s = ARM_SSE(opaque); > + /* > + * Set system_clock_scale from our Clock input; this is what > + * controls the tick rate of the CPU SysTick timer. > + */ > + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); > +} > + I think you forgot to connect this callback to the clock itself (the `qdev_init_clock_in` call in `armsse_init`). Moreover on a clock change event, shouldn't the SysTick timer be recomputed? I guess this will be better fixed in the SysTick itself once it takes the two Clock inputs as you said. -- Luc > static void armsse_init(Object *obj) > { > ARMSSE *s = ARM_SSE(obj); > @@ -451,9 +461,11 @@ static void armsse_realize(DeviceState *dev, Error **errp) > return; > } > > - if (!s->mainclk_frq) { > - error_setg(errp, "MAINCLK_FRQ property was not set"); > - return; > + if (!clock_has_source(s->mainclk)) { > + error_setg(errp, "MAINCLK clock was not connected"); > + } > + if (!clock_has_source(s->s32kclk)) { > + error_setg(errp, "S32KCLK clock was not connected"); > } > > assert(info->num_cpus <= SSE_MAX_CPUS); > @@ -1115,7 +1127,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) > */ > sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); > > - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; > + /* Set initial system_clock_scale from MAINCLK */ > + armsse_mainclk_update(s); > } > > static void armsse_idau_check(IDAUInterface *ii, uint32_t address, > -- > 2.20.1 > -- From MAILER-DAEMON Sat Jan 23 15:32:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3PZy-0005eu-Jd for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 15:32:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PZw-0005dT-7U; Sat, 23 Jan 2021 15:32:17 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58560) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PZp-0003yT-CL; Sat, 23 Jan 2021 15:32:16 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 0A9B2C602E6; Sat, 23 Jan 2021 21:32:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611433927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=zZoN0v7rmxAScNwjyaP5Vs3snrK3aFC32pqDZKZCyRI=; b=ZFMOx2KIebFXoDwEQF452PGxtcOshcB/Nb+pWQp4eCk8MmazFjG9eX7peOrv40Fb1pTgvd fS/OZA9tjcjh1gi6B5vNGQ+J3RFZ3KtE6hd9erC0aYaErSWA9xHzXgcNKb1FcU39n95TCa GvMPeCoaP+84uJ0ZCSfn21GfeqvWpNb0tnreBhx+NTZMsqsBNPbzBvYbO9H3BV8orRROQL PZ4uJ9RaO0mJ4xR31kdGJ3lrvfZcKCrkbKX5fMbOVdukHjSwGeiKOYTJO1MzNbxYgCOUh6 iqryG9ov2h22ufP/DFWpBQ1p+Tc17NVbvgE+0OpSsA8BioOkT36BDXPnh5L8YQ== Date: Sat, 23 Jan 2021 21:32:28 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Message-ID: <20210123203228.nt3l7wvon3lub5bi@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-24-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-24-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 20:32:17 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Remove all the code that sets frequency properties on the CMSDK > timer, dualtimer and watchdog devices and on the ARMSSE SoC device: > these properties are unused now that the devices rely on their Clock > inputs instead. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/armsse.c | 7 ------- > hw/arm/mps2-tz.c | 1 - > hw/arm/mps2.c | 3 --- > hw/arm/musca.c | 1 - > hw/arm/stellaris.c | 3 --- > 5 files changed, 15 deletions(-) > > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index 1da0c1be4c7..7494afc630e 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -726,7 +726,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > * it to the appropriate PPC port; then we can realize the PPC and > * map its upstream ends to the right place in the container. > */ > - qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); > qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { > return; > @@ -737,7 +736,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), > &error_abort); > > - qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); > qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { > return; > @@ -748,7 +746,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), > &error_abort); > > - qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); > qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { > return; > @@ -907,7 +904,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > /* Devices behind APB PPC1: > * 0x4002f000: S32K timer > */ > - qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); > qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { > return; > @@ -1001,7 +997,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, > qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); > > - qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); > qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { > return; > @@ -1012,7 +1007,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > > /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ > > - qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); > qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { > return; > @@ -1021,7 +1015,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) > armsse_get_common_irq_in(s, 1)); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); > > - qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); > qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { > return; > diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c > index 7acdf490f28..90caa914934 100644 > --- a/hw/arm/mps2-tz.c > +++ b/hw/arm/mps2-tz.c > @@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine) > object_property_set_link(OBJECT(&mms->iotkit), "memory", > OBJECT(system_memory), &error_abort); > qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); > - qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); > qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); > qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); > diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c > index cd1c215f941..39add416db5 100644 > --- a/hw/arm/mps2.c > +++ b/hw/arm/mps2.c > @@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine) > object_initialize_child(OBJECT(mms), name, &mms->timer[i], > TYPE_CMSDK_APB_TIMER); > sbd = SYS_BUS_DEVICE(&mms->timer[i]); > - qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); > qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); > sysbus_realize_and_unref(sbd, &error_fatal); > sysbus_mmio_map(sbd, 0, base); > @@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine) > > object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, > TYPE_CMSDK_APB_DUALTIMER); > - qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); > qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); > sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, > @@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine) > sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); > object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, > TYPE_CMSDK_APB_WATCHDOG); > - qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); > qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); > sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); > sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, > diff --git a/hw/arm/musca.c b/hw/arm/musca.c > index a9292482a06..945643c3cd7 100644 > --- a/hw/arm/musca.c > +++ b/hw/arm/musca.c > @@ -385,7 +385,6 @@ static void musca_init(MachineState *machine) > qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); > qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); > qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); > - qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); > qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); > qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); > /* > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 9b67c739ef2..5acb043a07e 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > if (board->dc1 & (1 << 3)) { /* watchdog present */ > dev = qdev_new(TYPE_LUMINARY_WATCHDOG); > > - /* system_clock_scale is valid now */ > - uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; > - qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); > qdev_connect_clock_in(dev, "WDOGCLK", > qdev_get_clock_out(ssys_dev, "SYSCLK")); > > -- > 2.20.1 > -- From MAILER-DAEMON Sat Jan 23 15:33:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3Pao-0006Re-QK for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 15:33:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Pam-0006Q9-5m; Sat, 23 Jan 2021 15:33:08 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Pai-0004M0-NA; Sat, 23 Jan 2021 15:33:07 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id E6E27C602E6; Sat, 23 Jan 2021 21:33:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611433982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=o0MhxP2amAO2wmCkP5GQa9QYhvVkmkT5o+o/3r+w3LM=; b=RPOCR4ewsFmmlX7ZSZ2btX7iFJbtxAiUA6HBwz8zfHTH1ofOw2QniarLcrJYaBAQylf+tc 3o5uBkKmz7qtBqUnfx9jFjyG9SeSf/PNiF31dTzh42Kdhg0ziKA/M0iebmeGmbr8DLGCDl sRz2rXP+mNQe8VaVkETicJooPO/CBE4wnD7qJI4noEMDc8RjICk1DGOMkfOK6GqI8xHE/w JazGcBk825xe5YC05BEaG9Rlqdrp3IsNupProfFoDD0HF/R9lYJweh9vEst0yQj+OP6C/k +XCfwo0cP6MYj7npzbfC7uvrIaIJdH2z4LAMl3pA9Gm4YH6KPABmPTCn7CY3Xw== Date: Sat, 23 Jan 2021 21:33:24 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Message-ID: <20210123203324.wgzlgcyxclyo6i4i@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-25-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-25-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 20:33:08 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Now no users are setting the frq properties on the CMSDK timer, > dualtimer, watchdog or ARMSSE SoC devices, we can remove the > properties and the struct fields that back them. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > include/hw/arm/armsse.h | 2 -- > include/hw/timer/cmsdk-apb-dualtimer.h | 2 -- > include/hw/timer/cmsdk-apb-timer.h | 2 -- > include/hw/watchdog/cmsdk-apb-watchdog.h | 2 -- > hw/arm/armsse.c | 2 -- > hw/timer/cmsdk-apb-dualtimer.c | 6 ------ > hw/timer/cmsdk-apb-timer.c | 6 ------ > hw/watchdog/cmsdk-apb-watchdog.c | 6 ------ > 8 files changed, 28 deletions(-) > > diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h > index bfa1e79c4fe..676cd4f36b0 100644 > --- a/include/hw/arm/armsse.h > +++ b/include/hw/arm/armsse.h > @@ -41,7 +41,6 @@ > * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals > * + QOM property "memory" is a MemoryRegion containing the devices provided > * by the board model. > - * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock > * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. > * (In hardware, the SSE-200 permits the number of expansion interrupts > * for the two CPUs to be configured separately, but we restrict it to > @@ -218,7 +217,6 @@ struct ARMSSE { > /* Properties */ > MemoryRegion *board_memory; > uint32_t exp_numirq; > - uint32_t mainclk_frq; > uint32_t sram_addr_width; > uint32_t init_svtor; > bool cpu_fpu[SSE_MAX_CPUS]; > diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h > index 3adbb01dd34..f3ec86c00b5 100644 > --- a/include/hw/timer/cmsdk-apb-dualtimer.h > +++ b/include/hw/timer/cmsdk-apb-dualtimer.h > @@ -16,7 +16,6 @@ > * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit > * > * QEMU interface: > - * + QOM property "pclk-frq": frequency at which the timer is clocked > * + Clock input "TIMCLK": clock (for both timers) > * + sysbus MMIO region 0: the register bank > * + sysbus IRQ 0: combined timer interrupt TIMINTC > @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer { > /*< public >*/ > MemoryRegion iomem; > qemu_irq timerintc; > - uint32_t pclk_frq; > Clock *timclk; > > CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; > diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h > index 54f7ec8c502..c4c7eae8499 100644 > --- a/include/hw/timer/cmsdk-apb-timer.h > +++ b/include/hw/timer/cmsdk-apb-timer.h > @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) > > /* > * QEMU interface: > - * + QOM property "pclk-frq": frequency at which the timer is clocked > * + Clock input "pclk": clock for the timer > * + sysbus MMIO region 0: the register bank > * + sysbus IRQ 0: timer interrupt TIMERINT > @@ -35,7 +34,6 @@ struct CMSDKAPBTimer { > /*< public >*/ > MemoryRegion iomem; > qemu_irq timerint; > - uint32_t pclk_frq; > struct ptimer_state *timer; > Clock *pclk; > > diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h > index 34069ca6969..c6b3e78731e 100644 > --- a/include/hw/watchdog/cmsdk-apb-watchdog.h > +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h > @@ -16,7 +16,6 @@ > * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit > * > * QEMU interface: > - * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked > * + Clock input "WDOGCLK": clock for the watchdog's timer > * + sysbus MMIO region 0: the register bank > * + sysbus IRQ 0: watchdog interrupt > @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog { > /*< public >*/ > MemoryRegion iomem; > qemu_irq wdogint; > - uint32_t wdogclk_frq; > bool is_luminary; > struct ptimer_state *timer; > Clock *wdogclk; > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index 7494afc630e..513caa33a9a 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -48,7 +48,6 @@ static Property iotkit_properties[] = { > DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, > MemoryRegion *), > DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), > - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), > DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), > DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), > DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), > @@ -60,7 +59,6 @@ static Property armsse_properties[] = { > DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, > MemoryRegion *), > DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), > - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), > DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), > DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), > DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c > index 828127b366f..ef49f5852d3 100644 > --- a/hw/timer/cmsdk-apb-dualtimer.c > +++ b/hw/timer/cmsdk-apb-dualtimer.c > @@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { > } > }; > > -static Property cmsdk_apb_dualtimer_properties[] = { > - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) > dc->realize = cmsdk_apb_dualtimer_realize; > dc->vmsd = &cmsdk_apb_dualtimer_vmstate; > dc->reset = cmsdk_apb_dualtimer_reset; > - device_class_set_props(dc, cmsdk_apb_dualtimer_properties); > } > > static const TypeInfo cmsdk_apb_dualtimer_info = { > diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c > index f053146d88f..ee51ce3369c 100644 > --- a/hw/timer/cmsdk-apb-timer.c > +++ b/hw/timer/cmsdk-apb-timer.c > @@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { > } > }; > > -static Property cmsdk_apb_timer_properties[] = { > - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) > dc->realize = cmsdk_apb_timer_realize; > dc->vmsd = &cmsdk_apb_timer_vmstate; > dc->reset = cmsdk_apb_timer_reset; > - device_class_set_props(dc, cmsdk_apb_timer_properties); > } > > static const TypeInfo cmsdk_apb_timer_info = { > diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c > index 9cad0c67da4..302f1711738 100644 > --- a/hw/watchdog/cmsdk-apb-watchdog.c > +++ b/hw/watchdog/cmsdk-apb-watchdog.c > @@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = { > } > }; > > -static Property cmsdk_apb_watchdog_properties[] = { > - DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > @@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) > dc->realize = cmsdk_apb_watchdog_realize; > dc->vmsd = &cmsdk_apb_watchdog_vmstate; > dc->reset = cmsdk_apb_watchdog_reset; > - device_class_set_props(dc, cmsdk_apb_watchdog_properties); > } > > static const TypeInfo cmsdk_apb_watchdog_info = { > -- > 2.20.1 > -- From MAILER-DAEMON Sat Jan 23 15:33:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3PbD-0006k4-5D for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 15:33:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PbC-0006i4-4B; Sat, 23 Jan 2021 15:33:34 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3PbA-0004Xs-DN; Sat, 23 Jan 2021 15:33:33 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id B9F75C602E6; Sat, 23 Jan 2021 21:33:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611434009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=6e+z3MckAZFaGT703sf2KecvlXuBkoiUJcmnxnowGZU=; b=SChU8k6SM9NnCFHEQHpuh0aNi1kxogPietfj30yXmO0XnEFPP/nAyDoK475RrRewytZ7+y nWyV8HKaCaKMqzx7S5UsXGYJPfnZ6vcRZKwu+rLBMHUenkWk1fV6ZsVtW7x1Xj3jQ9c4zM wkKbw0mN0yStHF95UYpeNLIdVHukHvmvnCIkiMAhoEPX5WkzevpoVgRPMIdobCC2dfZsIy lo+e7wTrjh+k4FowAbV/MPObi8G1bdUFIySDZkY31pkpj9irQUlnzdITzcn6YvAedMIe6r hdBO3tRH7JBBWVSzUY+vmulu6ABrFV3OlTQy3QLvTa7wDh/zkCe9WMpwzVSO+A== Date: Sat, 23 Jan 2021 21:33:51 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Message-ID: <20210123203351.453pcpozshxiwlxg@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-26-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-26-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 20:33:34 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Now that the watchdog device uses its Clock input rather than being > passed the value of system_clock_scale at creation time, we can > remove the hack where we reset the STELLARIS_SYS at board creation > time to force it to set system_clock_scale. Instead it will be reset > at the usual point in startup and will inform the watchdog of the > clock frequency at that point. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > hw/arm/stellaris.c | 10 ---------- > 1 file changed, 10 deletions(-) > > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 5acb043a07e..ad72c0959f1 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, > sysbus_mmio_map(sbd, 0, base); > sysbus_connect_irq(sbd, 0, irq); > > - /* > - * Normally we should not be resetting devices like this during > - * board creation. For the moment we need to do so, because > - * system_clock_scale will only get set when the STELLARIS_SYS > - * device is reset, and we need its initial value to pass to > - * the watchdog device. This hack can be removed once the > - * watchdog has been converted to use a Clock input instead. > - */ > - device_cold_reset(dev); > - > return dev; > } > > -- > 2.20.1 > -- From MAILER-DAEMON Sat Jan 23 17:33:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3RTO-0000uU-6J for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 17:33:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3RTG-0000tV-4m for qemu-arm@nongnu.org; Sat, 23 Jan 2021 17:33:30 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:45575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3RT9-0008Nf-KI for qemu-arm@nongnu.org; Sat, 23 Jan 2021 17:33:29 -0500 Received: by mail-ed1-x531.google.com with SMTP id f1so10791269edr.12 for ; Sat, 23 Jan 2021 14:33:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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Sat, 23 Jan 2021 14:33:21 -0800 (PST) MIME-Version: 1.0 References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-23-peter.maydell@linaro.org> <20210123203115.5wz66nu5z3faj3no@sekoia-pc.home.lmichel.fr> In-Reply-To: <20210123203115.5wz66nu5z3faj3no@sekoia-pc.home.lmichel.fr> From: Peter Maydell Date: Sat, 23 Jan 2021 22:33:10 +0000 Message-ID: Subject: Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale To: Luc Michel Cc: qemu-arm , QEMU Developers , Damien Hedde , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Jan 2021 22:33:35 -0000 On Sat, 23 Jan 2021 at 20:30, Luc Michel wrote: > > On 19:06 Thu 21 Jan , Peter Maydell wrote: > > Use the MAINCLK Clock input to set the system_clock_scale variable > > rather than using the mainclk_frq property. > > > > Signed-off-by: Peter Maydell > > --- > > At some point we should make the SysTick take a Clock itself so > > that we can get rid of the system_clock_scale global entirely. > > (In fact we want two Clocks: one that is the CPU clock and one > > for the 'external reference clock' whose period is currently > > hardcoded at 1000ns in systick_scale()...) > > --- > > hw/arm/armsse.c | 21 +++++++++++++++++---- > > 1 file changed, 17 insertions(+), 4 deletions(-) > > > > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > > index 4349ce9bfdb..1da0c1be4c7 100644 > > --- a/hw/arm/armsse.c > > +++ b/hw/arm/armsse.c > > @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) > > qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); > > } > > > > +static void armsse_mainclk_update(void *opaque) > > +{ > > + ARMSSE *s = ARM_SSE(opaque); > > + /* > > + * Set system_clock_scale from our Clock input; this is what > > + * controls the tick rate of the CPU SysTick timer. > > + */ > > + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); > > +} > > + > I think you forgot to connect this callback to the clock itself (the > `qdev_init_clock_in` call in `armsse_init`). Whoops, yes :-) As it happens all ARMSSE users are fixed-frequency so this doesn't make a guest-visible difference, but it was definitely my intention that this was a clock update callback. > Moreover on a clock change event, shouldn't the SysTick timer be > recomputed? Systick correctly handles the system_clock_scale global being changed at runtime, so once this callback is actually wired up to its Clock that should just work. thanks -- PMM From MAILER-DAEMON Sat Jan 23 21:53:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VWb-0006hS-5a for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 21:53:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3VWZ-0006g9-Up for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:11 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3VWX-000396-TH for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:11 -0500 Received: by mail-wr1-x42d.google.com with SMTP id l12so8834611wry.2 for ; Sat, 23 Jan 2021 18:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s7PJ51jzBATxkQNcxoYSFNAfapcaizQoguoJb33d/p4=; b=T2CoCfMb1gR6oyxekb5GASUG88x1gpHBrhPLEMk1MkAUx8yM391S+lAGxZTdrAX0++ fCbTTEY9JJOhIpZ64OcE9v/+1jzj5itI+om+8fpxZPC88DojttcvfeoQrpJGpWJo9ORs 9EadpxYoGpyVU8XoWD6Jk57FNuSsHFZ0RJJPjKmiJvo0/3U4bGCh7jRn6fd3dNFvTgdw lC2JNT2Nz+vRPNvUkcCwDd5i8rtztGwziXgE/HRgvEq0X+2nFIVqf8oxybmbwoOnh5kP WNEgCTpehcihntc8bkeqBIqagqfg3bkR9LBDh7/AXSt2ooDcovQyQtE/PMuAjQP9x9ZL 4mrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s7PJ51jzBATxkQNcxoYSFNAfapcaizQoguoJb33d/p4=; b=maLMONesRzVL48Q2Z3tOdJYfWj2yRBZWK9r1FLoGka0IOOLxLK108rMPiBFVem35eK pnCY1awnVhmxXOPPBn9ckJKprqvEYoponadw63XGvCeBv+GmyU9jprWTRw0EMStkDNTl aUc/fNBByUr+rioeWsBwSKcGuyiRJgvqme73ScssOsSGJty4B6gDFvrk4e9mrr1T7QJj nNzVr97jI9UvEH5y9jzCpVexIDJ/yILeAIZsDvO9MRqunol+fXFBhCDDK/TekLiA2VaP QYdrUpwv68HrskZ/2F5nkm7EWc4MsEN7V5JoIsm5SYLmFF5c1jIYpBAkTwATdho5ld0t cbeg== X-Gm-Message-State: AOAM531dQOqwOqUIR4nVrhMEXsuV+pFYJvD7gawvX4rIUFY6/A8KBQhm PBVcxFthPhD1yj9zpc14evRLCgo2qVEXUuboETXdzgSstaWgk2dsNLzr6+SNCnqqJYp0yEBh9yu F3xmBsoR10LM62OO55MQmwiNXn2hNSUZrIeQy8PF7AObw7yGIIQkInWgrWvryBTVroio= X-Google-Smtp-Source: ABdhPJwmJvFoqrupjRpYqmBPUVhmrD1pAbYz6xWYlJkq5iqmdsMsQmBsGyW4YKVlY0r4cCz8NyVMAA== X-Received: by 2002:adf:c454:: with SMTP id a20mr10937019wrg.314.1611456788006; Sat, 23 Jan 2021 18:53:08 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:07 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Shashi Mallela Subject: [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Date: Sun, 24 Jan 2021 02:53:02 +0000 Message-Id: <20210124025306.3949-1-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 02:53:12 -0000 GICv4 sets aside 256K per redistributor configuration block, whereas GICv3 only uses 128K. However, some codebases (like TF-A, EDK2) will happily use the GICv3 functionality only. This set aims at enabling these codebases to run, without actually enabling full support for GICv4. This creates a ... problematic ... system, which will misbehave if you try to use the virtual LPIs. But it does help with letting me use QEMU for modelling a platform containing a GICv4, and share firmware images with other prototyping platforms. Leif Lindholm (4): hw/intc: don't bail out gicv3 model init for revision 4 hw/intc: add helper function to determine gicv3 redistributor size hw/intc: set GICD_TYPER.DVIS for GICv4 hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4 hw/intc/arm_gicv3_common.c | 4 ++-- hw/intc/arm_gicv3_dist.c | 5 ++++- hw/intc/arm_gicv3_redist.c | 15 ++++++++++----- hw/intc/gicv3_internal.h | 12 ++++++++++-- include/hw/intc/arm_gicv3_common.h | 3 +++ 5 files changed, 29 insertions(+), 10 deletions(-) -- 2.20.1 From MAILER-DAEMON Sat Jan 23 21:53:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VWd-0006lp-Eg for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 21:53:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3VWb-0006hn-Bg for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:13 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:50255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3VWY-00039Q-GL for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:13 -0500 Received: by mail-wm1-x333.google.com with SMTP id 190so7603276wmz.0 for ; Sat, 23 Jan 2021 18:53:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/3jk8M7uoiqLp/tnXbSwyohY/WHN9zW+icvpVea9Usg=; b=roFpZmyiSKl9huM8e2oNrGsfF5eSooqjrmSfVqkBIBZzL7m0SvS8FIjvzABndSBSjz KoU+jvVC1SXsURWjFCLaqvRfKEBKMDSEJpHn4ME0w1wIMcA1JqCdzOpJ034Ck2Uz7CuP IA5ItyYeVz2ATUjMBx6a7DWkpmgZZK4GhmUK6TXI9NvziwkMYVuiYSqWTBBixMGXjFHh Pv1S1UdpYV8z2csB3cU/qCvStcNrkk7VblVss9gszRegkT0LmvtMNJF397SF6HoRFKR0 EhrsqUTEeQ7By+iRxXVrb9VMmJpVuCbwkPdURT1u37YFD2BRKgrpgnEcF8oX894735Mx 3WBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/3jk8M7uoiqLp/tnXbSwyohY/WHN9zW+icvpVea9Usg=; b=sv+SPGgU/pLlVKVdbdb/5Bu6feD6pbshmaaw9B1ei/jhl20I9bwU5mWr8JH3DOTwMm Pz+qec+NPx65DEQshPMF0+VxG85L11oltgbF+YJm47cJpOdNRASg698A+r+GpBcEaAl3 rjkIfXlGEYB7o9tdkW7XO8DrQ0Z+bwokzCWcs4RVCwQl3M9p1bolDx78+MZJ5JrdtYxV d2feUWGtaEWN9ydgB8B4wAPR/krWtfcp+R3viZrzD2qFKA0HwA6Ix4/RrbfrdAiRQmVr W8lFvqZhpSSKdBGmxLyCVQfWJm6CsP9yEceDrcASC7uKeVoQpmciDpqC8BMNx9gK+P8T 3o5w== X-Gm-Message-State: AOAM531UBVB5vMq3slcjq6csm2CDT5mldJQFpamAemMqzRTG4r23gBjk 77rthBqLlpuVIXoRSI3Al1r1Vxf9PKOazhgXPTIBvpnNGLnlEjNmyH5F/O0Si9JD1a2btUc+e92 /js+CrYuf8IoDR6TKubxKNOmlR21bKBWsl8hMr021uQCmeGEbgfu406BZeQPzYadDTGc= X-Google-Smtp-Source: ABdhPJyJMVlYuJ3OBPpG0cZH4Bcrda00vx/uHGFsc18tNGT+KsxSB9jhgzROuwU/8PLHRH1oje86RQ== X-Received: by 2002:a05:600c:618:: with SMTP id o24mr10294828wmm.82.1611456788844; Sat, 23 Jan 2021 18:53:08 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:08 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Shashi Mallela Subject: [RFC PATCH 1/4] hw/intc: don't bail out gicv3 model init for revision 4 Date: Sun, 24 Jan 2021 02:53:03 +0000 Message-Id: <20210124025306.3949-2-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=leif@nuviainc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 02:53:13 -0000 As a first step towards GICv4 compatibility, add support for gic revision 4 to GICv3 driver (i.e. don't bail out if revision 4 is encountered). Signed-off-by: Leif Lindholm --- hw/intc/arm_gicv3_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 58ef65f589..7365d24873 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -315,7 +315,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) * conditions. However, in future it could be used, for example, if we * implement GICv4. */ - if (s->revision != 3) { + if (s->revision != 3 && s->revision != 4) { error_setg(errp, "unsupported GIC revision %d", s->revision); return; } -- 2.20.1 From MAILER-DAEMON Sat Jan 23 21:53:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VWi-0006q1-Qi for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 21:53:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3VWc-0006jy-HA for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:14 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:46921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3VWa-00039l-5E for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:14 -0500 Received: by mail-wr1-x429.google.com with SMTP id q7so8799724wre.13 for ; Sat, 23 Jan 2021 18:53:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uxfJzCYb9p3cDULfc+U2nLGno8Z8Z8cB17iO0MBRYWA=; b=xNxrfNaOcK5gmJCVPvh42++lq5RdzVi6TTbW75rStHU0DCYBILzCj1Ovmw4ugmtqhd pbOBYpGbQ9+ofj6BK+8Ko0c/tkF4YhtWKoKfLoXEDWZunYtqLRdKSsA3EGvXCVH8eV6l If+Ye3DJx4BJlT218BIDh32yJ9Iu91Icqt9nIg5pZuxXK+aUihupExTh8/J9s0jdC+vZ VYsf5MRJVENPSJF+OF7mbtFjLgCZn0h2pVZ1dh1CpH3qkrXiKi6/2ffowQGp+a7HDIHo N+E1qssB8XnMy7GWmmXCt8Eo6MKKW+1CmI2D9Qv21gqFoELYO1dWQDeB2M1NL5BhvF5E D51Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uxfJzCYb9p3cDULfc+U2nLGno8Z8Z8cB17iO0MBRYWA=; b=rnKo+lT1v832xnsZlYPzigvKcKR/hkqV5SMhF6SPpS4CNlljHmxyMbUFjNIRHPsqtt gWYWbG3wNbC8kbQtp527u6Tdm8LA6OX9ghsYo3iXKxPrbXbyLjiaJsZIlVgT/WiqfTOQ 1zTip+aeQLaDNXsoTy1OS8Oa8HZ7MM3OkaYQy7DDjacRXrmAhHbKirdMFsAOWgBQV7II 7Al9lBS8PO4Y7JrdGv6zVU1mYVoq60b7bI+oMBjzdar0juWi9/yxrkyYcvLuN4BYeG2o TVXcsK7ykdRcxnDvq2I3Bo4uwGCxgHhLj6fWNMKiTfkQCaHAo8G+fAVJfMzodTZmKza5 fCng== X-Gm-Message-State: AOAM530YBR10T57t5cYGIRVKGIPKa65X1lTjEV+v3ApXVhWd0MO9wwCZ OfJqJYC4z5UTV36hrPRwKO0Uw2U3D6AwIV0vZ5ZWJ90C2QiDfIjaXSwOZ9LIVUY+oAFQWwR7bVy 3gxgYdjpKy8CTNWRJroD1HOZIpcrs+wUXGD+YMKP3HnG9ApEYvBrYqF7DrPqBxxOKn0A= X-Google-Smtp-Source: ABdhPJyBKOLKEbyk5J5HsPuXEyM68tEy6mq+dh0X/dTMIIqQXT7cDx93vqvtTEQWVEI4vHp87zsgNQ== X-Received: by 2002:adf:9526:: with SMTP id 35mr11011348wrs.399.1611456790684; Sat, 23 Jan 2021 18:53:10 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:10 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Shashi Mallela Subject: [RFC PATCH 3/4] hw/intc: set GICD_TYPER.DVIS for GICv4 Date: Sun, 24 Jan 2021 02:53:05 +0000 Message-Id: <20210124025306.3949-4-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=leif@nuviainc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 02:53:14 -0000 The VLPI frames are what make the redistributor size change, so ensure we state in GICD_TYPER that we have them. Signed-off-by: Leif Lindholm --- hw/intc/arm_gicv3_dist.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index b65f56f903..833deb0a74 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -387,6 +387,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | (0xf << 19) | itlinesnumber; + if (s->revision == 4) { + *data |= (1 << 18);; + } return MEMTX_OK; } case GICD_IIDR: -- 2.20.1 From MAILER-DAEMON Sat Jan 23 21:53:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VWj-0006qZ-13 for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 21:53:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3VWc-0006kk-Tk for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:14 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:44797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3VWa-0003Ar-Sg for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:14 -0500 Received: by mail-wr1-x42b.google.com with SMTP id d16so8146554wro.11 for ; Sat, 23 Jan 2021 18:53:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hvTez/HngdMR8Bp4hJmsxx6LvZR0P6LerCwHXuYSqjg=; b=Rny/TWwVpFgoB+k7tCEU3sQr68GNvPhfpYKgn//MyeKMNTXcWtgyw394aFpYY14fo8 1RSjZor71rt6ZqXIAjbOSw7AjU52cGHZgnU3ewihfAEAqzsJOfz/UIXYbguwtdVTGOyu M+rYSylN8/A0VFGxIEM4hb2gFCUSJVwfGU2bl0JrZVR77i5V/7blYXPeFUiXsoONt1N/ KmbeWpL1QNkT2hVLV+1E1vZpjNMC3aruaaSlempNFmWcDGH1XOD3Kns4tiLofXeHrW9g K1g9qVI/Ln4gX7Dih+7OJLGDSgx2FJTHvQyvNCKQeszau80yaM2XK2zj4SeYRv+b9ZWN 6gXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hvTez/HngdMR8Bp4hJmsxx6LvZR0P6LerCwHXuYSqjg=; b=qpkGGs4YsrfCn0U2dUfPQ0ZcULdzzq2l+FzATKOtcNTew6o8GiW5hSOvQMDGZHhtpc WMT/zIWHcENVOO0THz5IxoqF5PG73o460i/YFXFhH6sT4CY5LCbzSlO7siXXCPPXGSPI BgYU+fKsIpfhddJ/zA1+CdbEmlcMIM13btS3T9s/dbe7OKlCbfk6qQII5tfRIdhsiWAP ee1DqlOEMwo84v5QJXo8CY8TLZ7a0FimnXhaUgTdmLCDLdjVzyWS/l5d4CH8tzJVVPNK RV628l0nfUCwJq+TGHj+IjPrO0HqNoD41tX2Y4mHBbJx5hYlO18RHCUXdxuzXqr9SGm0 l8uA== X-Gm-Message-State: AOAM5339OTn4OKcau3H3/S0L1m6TRXsiguWQj0VRwViEgZ53jh+rztc0 ZLxNWAS1hF1M8kX2giVd6KVRP+V/jhuxf2zPOykreFMxX8DVmATkg+Ns31Mz2p2hac9DQiqvz7p puEd839jK7ttO6pTGaypAdfVA+rPS36+A/ScKTmhi9xV9KDxDugmpijaXO6a0BKXaPN4= X-Google-Smtp-Source: ABdhPJwKQedSnOlWF1q62HU0eV7pFj9XlNbkKYzhcAaIXw0aSQu9lGu5EqssuDaJs+kL43/9zi05/Q== X-Received: by 2002:adf:dd83:: with SMTP id x3mr8134808wrl.421.1611456791456; Sat, 23 Jan 2021 18:53:11 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:11 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Shashi Mallela Subject: [RFC PATCH 4/4] hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4 Date: Sun, 24 Jan 2021 02:53:06 +0000 Message-Id: <20210124025306.3949-5-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 02:53:15 -0000 Make gicv3_idreg() able to return either gicv3 or gicv4 data. Add a parameter to specify gic version. Signed-off-by: Leif Lindholm --- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 2 +- hw/intc/gicv3_internal.h | 12 ++++++++++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 833deb0a74..d32a1d5f48 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -544,7 +544,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GICD_IDREGS); + *data = gicv3_idreg(offset - GICD_IDREGS, s->revision); return MEMTX_OK; case GICD_SGIR: /* WO registers, return unknown value */ diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 544f4d82ff..faa68c9a71 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -239,7 +239,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, *data = cs->gicr_nsacr; return MEMTX_OK; case GICR_IDREGS ... GICR_IDREGS + 0x2f: - *data = gicv3_idreg(offset - GICR_IDREGS); + *data = gicv3_idreg(offset - GICR_IDREGS, cs->gic->revision); return MEMTX_OK; default: return MEMTX_ERROR; diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 05303a55c8..ded2df66eb 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -321,7 +321,7 @@ static inline uint32_t gicv3_iidr(void) return 0x43b; } -static inline uint32_t gicv3_idreg(int regoffset) +static inline uint32_t gicv3_idreg(int regoffset, int revision) { /* Return the value of the CoreSight ID register at the specified * offset from the first ID register (as found in the distributor @@ -331,7 +331,15 @@ static inline uint32_t gicv3_idreg(int regoffset) static const uint8_t gicd_ids[] = { 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 }; - return gicd_ids[regoffset / 4]; + static const uint8_t gicdv4_ids[] = { + 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x4B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 + }; + + if (revision == 3) { + return gicd_ids[regoffset / 4]; + } else { + return gicdv4_ids[regoffset / 4]; + } } /** -- 2.20.1 From MAILER-DAEMON Sat Jan 23 21:53:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VWk-0006tQ-6V for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 21:53:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3VWe-0006oA-9T for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:16 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41293) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3VWZ-00039d-RF for qemu-arm@nongnu.org; Sat, 23 Jan 2021 21:53:16 -0500 Received: by mail-wr1-x42b.google.com with SMTP id p15so2174100wrq.8 for ; Sat, 23 Jan 2021 18:53:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vCib2bK8ZRs2GnL3ZDKcV/vqIXCDzjV3kKl0ikqzRig=; b=LLMgbORQec2Dr4WSi01vJWcBOvpgSpJQ2j3cj/NkQnSiXBP9kzw6HoB+MtzPw6zqVO gvftycDy3K+tD1XWM8vIR0Q/3NiggDJOnzpk1LOW8n6SlI8sDuqS/9kheDr335tPxOki BoCFY12rRUPOP9Jer+05qAkJpEWYxD0pj/trXJYNfTpuNygLws1vP65r7emrWeANfio4 TqU4lwf3NgjjuULU6miWOBI3GgzJ/aJXL4Zr/QmT7NNzTKxGnVn54I6NN26jwd5QSBdW 6WFDUc8UBk2cW89q7B6jAx7e/X+Qj8hNDbwJssNXVB5z8IkAbnGj+cJhItpLCXr1DeZd kV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vCib2bK8ZRs2GnL3ZDKcV/vqIXCDzjV3kKl0ikqzRig=; b=RhG3v2y3qdmik2t4DaHPKEWsXY029hke6lqusEWihtL9ynbxAkvM/SyCZ5rVInBV+/ TrGvw/57yuobGTaD+s6yzwWuvQIPdI1/IyJDDAFA1RD3pbknJUkGb1tQeWs5UoRC1IDy ybmPsvEF7HG99r6WlkU6Uj5b57cjTJxRq3I0Md7oZm/FjA8FWruuvj11kIvb+Go104kM c1i8zPBP1WG7cu9Y/oIeBC1WUwku8J1bB1KrarEVoLjye1WaMnwhguTCh7pmvat6EPnx BJn7WMSzqsI8+GLvm+PAh36vDxIKRlyZ7ao6QkOsPQbkpjTzfeBbMH/1fkM3WuKi+WSV MdvA== X-Gm-Message-State: AOAM531kSBlzPGlNUuVRz5nLLmKNvFnqwVNVG7HMeMUdPjyLAbLzaSOw pSPncJexgC4Ee8MuqfaeWSswhuww13X8Mx/rr/8KOdE7Z2jantOZ9xYMFgGUKCVNrxzN1+Zgm5i 1qiYvndMF8n80Pb38fYJfrcklN6BFhTOuNaNzPtcE9qXORUkIMMp4TLadb6WyQB8jOgw= X-Google-Smtp-Source: ABdhPJyNzHATEC8dTuxFUFwDmfDzPV0676+iaT56j2ywiTDUteFdiwPgkdyO690XmVXalsZNHW+2bg== X-Received: by 2002:a5d:6588:: with SMTP id q8mr1091823wru.294.1611456790038; Sat, 23 Jan 2021 18:53:10 -0800 (PST) Received: from vanye.hemma.eciton.net (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:09 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Shashi Mallela Subject: [RFC PATCH 2/4] hw/intc: add helper function to determine gicv3 redistributor size Date: Sun, 24 Jan 2021 02:53:04 +0000 Message-Id: <20210124025306.3949-3-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 02:53:16 -0000 GICv3 sets aside 128K for each redistributor block, whereas GICv4 sets aside 256K. To enable use of the gicv3 model for gicv4, abstract this away as the helper function gicv3_redist_size() and replace the current hardcoded locations with calls to this function. Signed-off-by: Leif Lindholm --- hw/intc/arm_gicv3_common.c | 2 +- hw/intc/arm_gicv3_redist.c | 13 +++++++++---- include/hw/intc/arm_gicv3_common.h | 3 +++ 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 7365d24873..a8510b39a1 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -299,7 +299,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, memory_region_init_io(&s->iomem_redist[i], OBJECT(s), ops ? &ops[1] : NULL, s, name, - s->redist_region_count[i] * GICV3_REDIST_SIZE); + s->redist_region_count[i] * gicv3_redist_size(s)); sysbus_init_mmio(sbd, &s->iomem_redist[i]); g_free(name); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 8645220d61..544f4d82ff 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -14,6 +14,11 @@ #include "trace.h" #include "gicv3_internal.h" +int gicv3_redist_size(GICv3State *s) +{ + return (s->revision == 3 ? GICV3_REDIST_SIZE : GICV4_REDIST_SIZE); +} + static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) { /* Return a 32-bit mask which should be applied for this set of 32 @@ -429,8 +434,8 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, * want to allow splitting of redistributor pages into several * blocks so we can support more CPUs. */ - cpuidx = offset / 0x20000; - offset %= 0x20000; + cpuidx = offset / gicv3_redist_size(s); + offset %= gicv3_redist_size(s); assert(cpuidx < s->num_cpu); cs = &s->cpu[cpuidx]; @@ -486,8 +491,8 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, * want to allow splitting of redistributor pages into several * blocks so we can support more CPUs. */ - cpuidx = offset / 0x20000; - offset %= 0x20000; + cpuidx = offset / gicv3_redist_size(s); + offset %= gicv3_redist_size(s); assert(cpuidx < s->num_cpu); cs = &s->cpu[cpuidx]; diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 91491a2f66..ab88d14867 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -37,6 +37,7 @@ #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) #define GICV3_REDIST_SIZE 0x20000 +#define GICV4_REDIST_SIZE (GICV3_REDIST_SIZE + 0x20000) /* Number of SGI target-list bits */ #define GICV3_TARGETLIST_BITS 16 @@ -295,4 +296,6 @@ struct ARMGICv3CommonClass { void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, const MemoryRegionOps *ops, Error **errp); +int gicv3_redist_size(GICv3State *s); + #endif -- 2.20.1 From MAILER-DAEMON Sat Jan 23 22:01:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3VeD-0007Gv-Nr for mharc-qemu-arm@gnu.org; Sat, 23 Jan 2021 22:01:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Ve7-0007F5-G3; Sat, 23 Jan 2021 22:00:59 -0500 Resent-Date: Sat, 23 Jan 2021 22:00:59 -0500 Resent-Message-Id: Received: from sender4-of-o53.zoho.com ([136.143.188.53]:21308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3Ve4-0005Kc-0Q; Sat, 23 Jan 2021 22:00:59 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1611457249; cv=none; d=zohomail.com; s=zohoarc; b=N9WI0oUSAf8a7jw4nKduJjnVm92pRCcDOfAlu6vAVVNp21XcTuOHbJU9E5r3dMuq1dFz0ai75ffjbgVOVP2vWX13Z7rxWzd8eEWgvo/0ZDu4mOrixKCwQlUKjf8mJVZSkg77Yua6p3h1cWOtrNKuE7Sa42EiI8Ygy1SgO92sKwg= ARC-Message-Signature: i=1; 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Sat, 23 Jan 2021 22:39:55 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-78-g36b56e88ef-fm-20210120.001-g36b56e88 Mime-Version: 1.0 Message-Id: <994f40e1-2a5b-4b7a-a4aa-23f824881d8a@www.fastmail.com> Date: Sun, 24 Jan 2021 14:39:02 +1100 From: "Berto Furth" To: qemu-arm@nongnu.org Subject: KVM guests reading/writing guest memory directly and accurately Content-Type: text/plain Received-SPF: pass client-ip=66.111.4.29; envelope-from=bertofurth@sent.com; helo=out5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 24 Jan 2021 02:22:19 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 03:40:01 -0000 Hi qemu-arm, Can anyone give me some advice on how a machine or device can read and write kvm guest ram memory and get a guaranteed up to date result? Can someone point me at an example in the latest QEMU source code? I'm working with an ARM-32 guest (-cpu host,aarch64=off) running on an ARM-64 host (Cortex A72 - Raspberry Pi4b). I have a problem where if I write directly to my guest RAM, (such as a DMA transfer) then the guest can't see the change straight away. Similarly when the host writes memory, the guest doesn't see the change until much later. If during a KVM_EXIT_MMIO the qemu host changes some values in guest ram memory (via address_space_write() or cpu_physical_memory_rw() etc...) , is there a way to make the guest be able to accurately read that memory as soon as the exit is complete. Additionally if a guest changes a value in ram just before a KVM_EXIT_MMIO, is there a way to ensure that the QEMU host can then read the up to date newly set values? Is there a function I can call to get any memory caches sitting in between the QEMU host program and the guest to be flushed? Should a region of guest ram be set up any differently than calling the normal functions like memory_region_init_ram() and memory_region_add_subregion() to facilitate this? I see that there are some memory initialization functions that deal with logging dirty memory but from what I can see they're only used by VGA displays and for VM migration. I understand that the proper thing to do is to set up the memory region in question as MMIO so that when the guest accesses this memory a KVM_EXIT_MMIO will occur but the memory region in question has to be executable and MMIO memory areas are not executable in QEMU. In addition it's not easily possible to predict before hand exactly what memory addresses are going to be involved in DMA, so I'd prefer to avoid having to dynamically construct little MMIO memory islands inside the main guest ram space as the guest runs. I'm assuming that the guest could be modified to disable d-caching (modify the ARM register SCTLR / p15 ?) and that may help but I'm desperately trying to avoid that if possible because I'm working with a proprietary "blob" on the guest that I don't have all the source code for. I know it's not very professional of me to make an emotional plea, but I've been working on this for weeks and I am desperately hoping someone can point to a solution for me. I am not a KVM expert and so I'm hoping I'm just missing something simple and obvious that one of you can quickly point out for me. If I have missed something obvious then I'm more than open to taking your abuse, mockery, insults and derision in exchange for some guidance!! Thanks so much for your help! From MAILER-DAEMON Sun Jan 24 07:50:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3eqs-0002fk-Lv for mharc-qemu-arm@gnu.org; Sun, 24 Jan 2021 07:50:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3eql-0002f9-RM; Sun, 24 Jan 2021 07:50:40 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:54686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3eqf-00063Q-Fv; Sun, 24 Jan 2021 07:50:39 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 0AA47C602E6; Sun, 24 Jan 2021 13:50:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611492629; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=R3s8A5Yh8OftKPGYZSQKQA6eXhSEdXN+oI0P0Yi0+ew=; b=AzdRa/iEsQMW3ynK32YKbLJQ1/WCy7w2Hv9Ccz3giu4A5jx9jkO/YkCgUIg2/Gz/XBk6Ds U2OJf1KTn2ACXaesASn7B9QbsCu1qR7qBzdKEbjeDEn6hJdg4X7uckFR/ySs8PPsxCg1Ba YXAz3E6RoLLJJa3uQBaCFhhRFTkoVa1d+fasPTo8wJRtHa+dGH4LF84sAmaROTuwUmiv8T uSBsAvoS4D9tBwXK8eX5VkeNaUbmrIBCzugz60x5b2f/y++NqYpALAVCynbZUoQxXKiUsM pyX088zzMF4qpOgOHJuldvhhufrw4gtRSzjxgMoLwaGyLNzFz11hh6ProGWSvw== Date: Sun, 24 Jan 2021 13:50:51 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Message-ID: <20210124125051.kof2wza52touyxl3@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-4-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-4-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 12:50:40 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Add a simple test of the CMSDK APB timer, since we're about to do > some refactoring of how it is clocked. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 78 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-timer-test.c > > diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c > new file mode 100644 > index 00000000000..085005cce99 > --- /dev/null > +++ b/tests/qtest/cmsdk-apb-timer-test.c > @@ -0,0 +1,76 @@ > +/* > + * QTest testcase for the CMSDK APB timer device > + * > + * Copyright (c) 2021 Linaro Limited > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest-single.h" > + > +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */ > +#define TIMER_BASE 0x40000000 > + > +#define CTRL 0 > +#define VALUE 4 > +#define RELOAD 8 > +#define INTSTATUS 0xc > + > +static void test_timer(void) > +{ > + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0); > + > + /* Start timer: will fire after 40000 ns */ > + writel(TIMER_BASE + RELOAD, 1000); > + writel(TIMER_BASE + CTRL, 9); > + > + /* Step to just past the 500th tick and check VALUE */ > + clock_step(20001); > + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); > + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(20000); > + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); > + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0); > + > + /* VALUE reloads at the following tick */ > + clock_step(40); > + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); > + > + /* Check write-1-to-clear behaviour of INTSTATUS */ > + writel(TIMER_BASE + INTSTATUS, 0); > + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); > + writel(TIMER_BASE + INTSTATUS, 1); > + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); > + > + /* Turn off the timer */ > + writel(TIMER_BASE + CTRL, 0); > +} > + > +int main(int argc, char **argv) > +{ > + QTestState *s; > + int r; > + > + g_test_init(&argc, &argv, NULL); > + > + s = qtest_start("-machine mps2-an385"); > + > + qtest_add_func("/cmsdk-apb-timer/timer", test_timer); > + > + r = g_test_run(); > + > + qtest_end(); > + > + return r; > +} > diff --git a/MAINTAINERS b/MAINTAINERS > index 3216387521d..010405b0884 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h > F: include/hw/arm/primecell.h > F: hw/timer/cmsdk-apb-timer.c > F: include/hw/timer/cmsdk-apb-timer.h > +F: tests/qtest/cmsdk-apb-timer-test.c > F: hw/timer/cmsdk-apb-dualtimer.c > F: include/hw/timer/cmsdk-apb-dualtimer.h > F: hw/char/cmsdk-apb-uart.c > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 16d04625b8b..74addd74868 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -141,6 +141,7 @@ qtests_npcm7xx = \ > 'npcm7xx_timer-test', > 'npcm7xx_watchdog_timer-test'] > qtests_arm = \ > + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ > (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ > ['arm-cpu-features', > -- > 2.20.1 > -- From MAILER-DAEMON Sun Jan 24 08:10:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3f9p-0007ox-Ku for mharc-qemu-arm@gnu.org; Sun, 24 Jan 2021 08:10:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3f9m-0007oW-6h; Sun, 24 Jan 2021 08:10:18 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:55530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3f9g-0006Bn-WA; Sun, 24 Jan 2021 08:10:17 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 0A361C602E6; Sun, 24 Jan 2021 14:10:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611493808; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=SJyJcEvUt69BxmSu6MT1J+V50x+xt2q+A8wKVTuROlw=; b=YD1EKqg/PUdPpjOHlQJOUWZ30hLgP8nBU1AW6sXPOyK0XNoulVcmsbcj0UKfqW22Vif+/C xwaRypccpQmLfN5eAsSVlebJ/t6rpemMmQnRYGQ54SdR8X6ZbWFQBxDNzAI2GUNgUTy0Al gBeDYuK7+8VNBrb9GTcHdZ3hlh5TFg/UDpqsltml7M34I+DI7d6NNJP3GEzcCGpGEdgObc TfG1Rt9PEzVQ3f9zRbjG1XYHr5n+9/VVFJezvf2onl0E70M8gsEkQZkWnRWeGEu9fbSXzj G5bchaOlXyiykSzH7+86p9jhiwrh6HZub+SN+UN8C5c4UbDj4+wUy7Q25j+78w== Date: Sun, 24 Jan 2021 14:10:30 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Message-ID: <20210124131030.dxvcid4i6j7kmt4r@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-5-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-5-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 13:10:18 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Add a simple test of the CMSDK watchdog, since we're about to do some > refactoring of how it is clocked. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 82 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c > > diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c > new file mode 100644 > index 00000000000..c6add1fee85 > --- /dev/null > +++ b/tests/qtest/cmsdk-apb-watchdog-test.c > @@ -0,0 +1,80 @@ > +/* > + * QTest testcase for the CMSDK APB watchdog device > + * > + * Copyright (c) 2021 Linaro Limited > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest-single.h" > + > +/* > + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz, > + * which is 80ns per tick. > + */ > +#define WDOG_BASE 0x40000000 > + > +#define WDOGLOAD 0 > +#define WDOGVALUE 4 > +#define WDOGCONTROL 8 > +#define WDOGINTCLR 0xc > +#define WDOGRIS 0x10 > +#define WDOGMIS 0x14 > +#define WDOGLOCK 0xc00 > + > +static void test_watchdog(void) > +{ > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > + > + writel(WDOG_BASE + WDOGCONTROL, 1); > + writel(WDOG_BASE + WDOGLOAD, 1000); > + > + /* Step to just past the 500th tick */ > + clock_step(500 * 80 + 1); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(500 * 80); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); > + > + /* VALUE reloads at following tick */ > + clock_step(80); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); > + > + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ > + clock_step(500 * 80); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); > + writel(WDOG_BASE + WDOGINTCLR, 0); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > +} > + > +int main(int argc, char **argv) > +{ > + QTestState *s; > + int r; > + > + g_test_init(&argc, &argv, NULL); > + > + s = qtest_start("-machine lm3s811evb"); > + > + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); > + > + r = g_test_run(); > + > + qtest_end(); > + > + return r; > +} > diff --git a/MAINTAINERS b/MAINTAINERS > index 010405b0884..58956497888 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c > F: include/hw/char/cmsdk-apb-uart.h > F: hw/watchdog/cmsdk-apb-watchdog.c > F: include/hw/watchdog/cmsdk-apb-watchdog.h > +F: tests/qtest/cmsdk-apb-watchdog-test.c > F: hw/misc/tz-ppc.c > F: include/hw/misc/tz-ppc.h > F: hw/misc/tz-mpc.c > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 74addd74868..9e2ebc47041 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -142,6 +142,7 @@ qtests_npcm7xx = \ > 'npcm7xx_watchdog_timer-test'] > qtests_arm = \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ > + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ > (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ > (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ > ['arm-cpu-features', > -- > 2.20.1 > -- From MAILER-DAEMON Sun Jan 24 08:24:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3fNJ-000284-5o for mharc-qemu-arm@gnu.org; Sun, 24 Jan 2021 08:24:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3fND-00027A-AT; Sun, 24 Jan 2021 08:24:11 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:56126) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3fN5-0003m5-Qf; Sun, 24 Jan 2021 08:24:10 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id E63DCC602E6; Sun, 24 Jan 2021 14:23:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611494638; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=3o34+lAU4XY1/GFF+V3mC8w1b7OeDIpR8jzDQe+IAic=; b=GRSEd2wd5UbATzP2fHeZGAlLFHDPvWZISkFELmtIJlyyupKWtuyG+gozI5+3fP3wiXBmwE DDy6NOGoCAt6ydF8scS4AnkQ/hcT3dR4ra4ECP0o5FzVtuyf+f8i4EHmwYWNQ/+YbbZpSl dhdV5KxKbDjr1uGJWQpqH+7T+c/nd2EMTMweBvVwVkNHA1K1aV+yMu20Xgosjes6GQXmVa A85KALMgc4sGNZuYbYEWh8BpBypr/ehgvYsjKMygCQ9mWBSfY5bO1kBqVDDF6WH6RhRKLM a5abx+Na/8JewMfjr1EyR3czan8ATnKsHk8jOsqWa9nlhsLNx0Dtm8H/7pflAg== Date: Sun, 24 Jan 2021 14:24:21 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Message-ID: <20210124132421.f6k25f2dcjm6cnsb@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-6-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-6-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 13:24:12 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Add a simple test of the CMSDK dual timer, since we're about to do > some refactoring of how it is clocked. > > Signed-off-by: Peter Maydell > --- > tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 133 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c > > diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c > new file mode 100644 > index 00000000000..5a29d65fd6d > --- /dev/null > +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c > @@ -0,0 +1,131 @@ > +/* > + * QTest testcase for the CMSDK APB dualtimer device > + * > + * Copyright (c) 2021 Linaro Limited > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest-single.h" > + > +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ > +#define TIMER_BASE 0x40002000 > + > +#define TIMER1LOAD 0 > +#define TIMER1VALUE 4 > +#define TIMER1CONTROL 8 > +#define TIMER1INTCLR 0xc > +#define TIMER1RIS 0x10 > +#define TIMER1MIS 0x14 > +#define TIMER1BGLOAD 0x18 > + > +#define TIMER2LOAD 0x20 > +#define TIMER2VALUE 0x24 > +#define TIMER2CONTROL 0x28 > +#define TIMER2INTCLR 0x2c > +#define TIMER2RIS 0x30 > +#define TIMER2MIS 0x34 > +#define TIMER2BGLOAD 0x38 > + > +#define CTRL_ENABLE (1 << 7) > +#define CTRL_PERIODIC (1 << 6) > +#define CTRL_INTEN (1 << 5) > +#define CTRL_PRESCALE_1 (0 << 2) > +#define CTRL_PRESCALE_16 (1 << 2) > +#define CTRL_PRESCALE_256 (2 << 2) > +#define CTRL_32BIT (1 << 1) > +#define CTRL_ONESHOT (1 << 0) > + > +static void test_dualtimer(void) > +{ > + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); > + > + /* Start timer: will fire after 40000 ns */ > + writel(TIMER_BASE + TIMER1LOAD, 1000); > + /* enable in free-running, wrapping, interrupt mode */ > + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); > + > + /* Step to just past the 500th tick and check VALUE */ > + clock_step(20001); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(20000); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); > + > + /* > + * We are in free-running wrapping 16-bit mode, so on the following > + * tick VALUE should have wrapped round to 0xffff. > + */ > + clock_step(40); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); > + > + /* Check that any write to INTCLR clears interrupt */ > + writel(TIMER_BASE + TIMER1INTCLR, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); > + > + /* Turn off the timer */ > + writel(TIMER_BASE + TIMER1CONTROL, 0); > +} > + > +static void test_prescale(void) > +{ > + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); > + > + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ > + writel(TIMER_BASE + TIMER2LOAD, 1000); > + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ > + writel(TIMER_BASE + TIMER2CONTROL, > + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); > + > + /* Step to just past the 500th tick and check VALUE */ > + clock_step(40 * 256 * 501); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(40 * 256 * 500); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); > + > + /* In periodic mode the tick VALUE now reloads */ > + clock_step(256); Shouldn't it be "clock_step(40 * 256)", i.e. 1 tick? > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); > + > + /* Check that any write to INTCLR clears interrupt */ > + writel(TIMER_BASE + TIMER2INTCLR, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); > + > + /* Turn off the timer */ > + writel(TIMER_BASE + TIMER2CONTROL, 0); > +} > + > +int main(int argc, char **argv) > +{ > + QTestState *s; > + int r; > + > + g_test_init(&argc, &argv, NULL); > + > + s = qtest_start("-machine mps2-an385"); > + > + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); > + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); > + > + r = g_test_run(); > + > + qtest_end(); > + > + return r; > +} > diff --git a/MAINTAINERS b/MAINTAINERS > index 58956497888..118f70e47fb 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h > F: tests/qtest/cmsdk-apb-timer-test.c > F: hw/timer/cmsdk-apb-dualtimer.c > F: include/hw/timer/cmsdk-apb-dualtimer.h > +F: tests/qtest/cmsdk-apb-dualtimer-test.c > F: hw/char/cmsdk-apb-uart.c > F: include/hw/char/cmsdk-apb-uart.h > F: hw/watchdog/cmsdk-apb-watchdog.c > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 9e2ebc47041..69dd4a8547c 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -141,6 +141,7 @@ qtests_npcm7xx = \ > 'npcm7xx_timer-test', > 'npcm7xx_watchdog_timer-test'] > qtests_arm = \ > + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ > (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ > -- > 2.20.1 > -- From MAILER-DAEMON Sun Jan 24 08:34:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3fXQ-0004xU-Vp for mharc-qemu-arm@gnu.org; Sun, 24 Jan 2021 08:34:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3fXQ-0004xI-0y; Sun, 24 Jan 2021 08:34:44 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:56602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3fXN-00080t-MW; Sun, 24 Jan 2021 08:34:43 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 3B211C602E6; Sun, 24 Jan 2021 14:34:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611495278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=DnEB7eCvT+FDDOw6DNNPM1u7lv33jN4hxVUC4ix651M=; b=ZVzqNh/7ovJLeGgrahAH4yNO3Tr7UwxJmJcQ1aAks65D9mgm4v6/YXLshTuUbJW+/ei95Q tnpKxu7Oj/eHikiUoTFhccQGZ1jXKGtrlJAXBXi1BuD//dccD0Y9Zupft3rI+0++W1Hm93 uo+L8HxVTmhmogiKDyjYS7SSJhz8Wg7fc/CcVDUZx3ET1/vLYFFI+xe84IrL2Aj6V7yKeu 6QropEbyLo/tFU7LsyiC1l3BDaf8LZNKlq8rhAFAexTAS5YEJySrKB6baPMxZvWPTYIzX5 ch84g/YAjVbQ5koiDeH6UIIRLdeybTD0dX0fpBXmJgx0CyLDRga9Up9A7bBAcQ== Date: Sun, 24 Jan 2021 14:35:00 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Damien Hedde , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Message-ID: <20210124133500.utnoaefyfozwg64e@sekoia-pc.home.lmichel.fr> References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-22-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210121190622.22000-22-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 13:34:44 -0000 On 19:06 Thu 21 Jan , Peter Maydell wrote: > Now that the CMSDK APB watchdog uses its Clock input, it will > correctly respond when the system clock frequency is changed using > the RCC register on in the Stellaris board system registers. Test > that when the RCC register is written it causes the watchdog timer to > change speed. > > Signed-off-by: Peter Maydell Reviewed-by: Luc Michel > --- > tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c > index c6add1fee85..9a4873a8314 100644 > --- a/tests/qtest/cmsdk-apb-watchdog-test.c > +++ b/tests/qtest/cmsdk-apb-watchdog-test.c > @@ -15,6 +15,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/bitops.h" > #include "libqtest-single.h" > > /* > @@ -31,6 +32,11 @@ > #define WDOGMIS 0x14 > #define WDOGLOCK 0xc00 > > +#define SSYS_BASE 0x400fe000 > +#define RCC 0x60 > +#define SYSDIV_SHIFT 23 > +#define SYSDIV_LENGTH 4 > + > static void test_watchdog(void) > { > g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > @@ -61,6 +67,50 @@ static void test_watchdog(void) > g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > } > > +static void test_clock_change(void) > +{ > + uint32_t rcc; > + > + /* > + * Test that writing to the stellaris board's RCC register to > + * change the system clock frequency causes the watchdog > + * to change the speed it counts at. > + */ > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > + > + writel(WDOG_BASE + WDOGCONTROL, 1); > + writel(WDOG_BASE + WDOGLOAD, 1000); > + > + /* Step to just past the 500th tick */ > + clock_step(80 * 500 + 1); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); > + > + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */ > + rcc = readl(SSYS_BASE + RCC); > + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); > + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); > + writel(SSYS_BASE + RCC, rcc); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(40 * 500); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); > + > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); > + > + /* VALUE reloads at following tick */ > + clock_step(41); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); > + > + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ > + clock_step(40 * 500); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); > + writel(WDOG_BASE + WDOGINTCLR, 0); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); > + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); > +} > + > int main(int argc, char **argv) > { > QTestState *s; > @@ -71,6 +121,8 @@ int main(int argc, char **argv) > s = qtest_start("-machine lm3s811evb"); > > qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); > + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", > + test_clock_change); > > r = g_test_run(); > > -- > 2.20.1 > -- From MAILER-DAEMON Sun Jan 24 11:08:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3hvq-00008q-Mh for mharc-qemu-arm@gnu.org; Sun, 24 Jan 2021 11:08:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3hvl-000089-Fe for qemu-arm@nongnu.org; Sun, 24 Jan 2021 11:08:04 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:45329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3hvg-0002ZI-8z for qemu-arm@nongnu.org; Sun, 24 Jan 2021 11:08:01 -0500 Received: by mail-ej1-x629.google.com with SMTP id ke15so14458166ejc.12 for ; Sun, 24 Jan 2021 08:07:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=tNu9hFqN2gGcAA7+goDvjENW5QyDLv05V0Gd8G9L/UM=; b=B3rVvUP2/A5lAd3QaAYa1WO3w0rPFHSXE3KxyRrLcpDzi65WWb0QyGgjVWlWsC5w/F 4z76r1MI8HgCSuErqKm4ogJG7gybB/nFa6Jg5PWBJBOEcFp1j3pmJ4NeBs5QvdC2u8EE wJeeQ8JwV36gJ1kXCjmNj8tNPek7rNPBkIRKhapaKecNfr02u42y2+U85GV1ByHhQJSl YpwihLd96nUoIuIwbZtkhEUFCA0+4+H//eIT1aHcs690QdoDyblvQ8OvHnGn7A+Yq8aD zCWJPX6zJmJ2+BouKSWlltJWGM+lLX0j8UpMPyxQd4ZynZrMwk/d2dV+WhLcWDN3RbO/ V0Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=tNu9hFqN2gGcAA7+goDvjENW5QyDLv05V0Gd8G9L/UM=; b=WwBxkoJKPgMqnRClvCP8gGVS/u46q0uUdtedoWX1zwWiBI9h6EubJ3NKAHz7WVOjLj P7/++1X/DaKZIiu8S4Z+sh8u11VeVgTY6ydZk1rFT9i1jGb2hyR+eIiBpad+2qtevNCQ 5qVzHqKM+A1t4+AAYp+bQMDuMbA8u5U4+KPz5PXEXHR3nMgN0p7RRO4bjv6ppBrXauF+ zotCNwr178BR3cA4/+8UsXGnc9fXFZdCWHnhsqGGwwbzF7AqhuK5XOCqa9xpilgkixVM 7tLSpTnNTvsvzNQkjwxHiGcTjSVzP1+cVSootx8goIlWEi1V+K35GJQBvKz20HvqLI2M mfLA== X-Gm-Message-State: AOAM530B5z7ubTfMGBfAAS0RqDLq01330rHF0BEV5s4blb+3by2PzLO+ FX/9nadTo/EzlGLLfRPJhmwbJJlqq4T2WKsr1b1ipA== X-Google-Smtp-Source: ABdhPJyUjQvfmqFgAwzzy6ZvLRPZ24mf7h2n2doU65TGbgE4XzDHLJriWlqTlTbJ9tiDno++0fwljERCRYw8/bNmF5w= X-Received: by 2002:a17:906:494c:: with SMTP id f12mr121208ejt.56.1611504474126; Sun, 24 Jan 2021 08:07:54 -0800 (PST) MIME-Version: 1.0 References: <994f40e1-2a5b-4b7a-a4aa-23f824881d8a@www.fastmail.com> In-Reply-To: <994f40e1-2a5b-4b7a-a4aa-23f824881d8a@www.fastmail.com> From: Peter Maydell Date: Sun, 24 Jan 2021 16:07:42 +0000 Message-ID: Subject: Re: KVM guests reading/writing guest memory directly and accurately To: Berto Furth Cc: qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jan 2021 16:08:05 -0000 On Sun, 24 Jan 2021 at 07:22, Berto Furth wrote: > Can anyone give me some advice on how a machine or device can read and wr= ite kvm guest ram memory and get a guaranteed up to date result? Can someon= e point me at an example in the latest QEMU source code? I'm working with a= n ARM-32 guest (-cpu host,aarch64=3Doff) running on an ARM-64 host (Cortex = A72 - Raspberry Pi4b). > > I have a problem where if I write directly to my guest RAM, (such as a DM= A transfer) then the guest can't see the change straight away. Similarly wh= en the host writes memory, the guest doesn't see the change until much late= r. > > If during a KVM_EXIT_MMIO the qemu host changes some values in guest ram = memory (via address_space_write() or cpu_physical_memory_rw() etc...) , is = there a way to make the guest be able to accurately read that memory as soo= n as the exit is complete. Additionally if a guest changes a value in ram j= ust before a KVM_EXIT_MMIO, is there a way to ensure that the QEMU host can= then read the up to date newly set values? With KVM I think this is just normal "multiple threads/CPUs both accessing one in-memory data structure" effects, so you need a memory barrier to ensure that what one thread has written is visible to the other. I think that the idea is that the functions in include/sysemu/dma.h provide a dma_barrier() (which is just a CPU memory barrier) and some wrapper functions which put in the barrier on the right side of a read or write operation. On the guest side it should already be using the right barrier insns in order to ensure that real hardware DMA sees the right view of RAM... We're very inconsistent about using these -- I've never liked the way we have separate 'dma' operations here rather than having the normal functions Just Work. But I haven't ever looked very deeply into what the requirements in this area are. > I understand that the proper thing to do is to set up the memory region i= n question as MMIO so that when the guest accesses this memory a KVM_EXIT_M= MIO will occur but the memory region in question has to be executable and M= MIO memory areas are not executable in QEMU. In addition it's not easily po= ssible to predict before hand exactly what memory addresses are going to be= involved in DMA, so I'd prefer to avoid having to dynamically construct li= ttle MMIO memory islands inside the main guest ram space as the guest runs. You only want to mark regions as MMIO if they need to actually come out to QEMU for the guest memory access to be handled -- typically this is device MMIO-mapped register banks. Normal RAM isn't mapped as MMIO. > I'm assuming that the guest could be modified to disable d-caching (modif= y the ARM register SCTLR / p15 ?) and that may help but I'm desperately try= ing to avoid that if possible because I'm working with a proprietary "blob"= on the guest that I don't have all the source code for. With Arm KVM doing this wouldn't help; in fact it would make things worse, because then the view of guest RAM that the guest sees has the non-cacheable attribute, but the view of guest RAM that QEMU has mapped is still cacheable, so the two get hopelessly mismatched ideas of what the RAM contents are. (Side note: if the guest wants to map RAM as non-cacheable, this won't work with Arm KVM (unless the host CPU supports FEAT_S2FWB, which is an Armv8.4 feature), for the same "QEMU and guest view of the same block of RAM disagree about whether it's cached" reason. The most commonly encountered case of this is that you can't use a normal VGA PCI graphics device model with KVM, because the guest maps the graphics RAM on the device non-cacheable.) > I know it's not very professional of me to make an emotional plea, but I'= ve been working on this for weeks and I am desperately hoping someone can p= oint to a solution for me. I am not a KVM expert and so I'm hoping I'm just= missing something simple and obvious that one of you can quickly point out= for me. Nah, this isn't obvious stuff -- a lot of QEMU's internals aren't very well documented and often are inconsistent about whether they do things correctly or not... thanks -- PMM From MAILER-DAEMON Mon Jan 25 02:51:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l3wf6-0004Ms-1q for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 02:51:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3wf4-0004Mi-NU; Mon, 25 Jan 2021 02:51:46 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3wet-00013M-68; Mon, 25 Jan 2021 02:51:43 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DPMV15ksmzjC3G; Mon, 25 Jan 2021 15:50:17 +0800 (CST) Received: from [10.174.184.42] (10.174.184.42) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Jan 2021 15:51:04 +0800 Subject: Re: [PATCH v2 0/2] accel: kvm: Some bugfixes for kvm dirty log To: Paolo Bonzini References: <20201217014941.22872-1-zhukeqian1@huawei.com> CC: Peter Maydell , "Dr . David Alan Gilbert" , Andrew Jones , Peter Xu , , , , Zenghui Yu , From: Keqian Zhu Message-ID: Date: Mon, 25 Jan 2021 15:51:03 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <20201217014941.22872-1-zhukeqian1@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhukeqian1@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 07:51:46 -0000 Hi Paolo, Any suggestions on this patch series :-) ? Thanks, Keqian On 2020/12/17 9:49, Keqian Zhu wrote: > Hi all, > > This series fixes memory waste and adds alignment check for unmatched > qemu_real_host_page_size and TARGET_PAGE_SIZE. > > Thanks. > > Keqian Zhu (2): > accel: kvm: Fix memory waste under mismatch page size > accel: kvm: Add aligment assert for kvm_log_clear_one_slot > > accel/kvm/kvm-all.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > From MAILER-DAEMON Mon Jan 25 06:48:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l40M7-0002UZ-8w for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 06:48:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l40M5-0002QI-Bt for qemu-arm@nongnu.org; Mon, 25 Jan 2021 06:48:25 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:34928) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l40M2-0000R5-Mg for qemu-arm@nongnu.org; Mon, 25 Jan 2021 06:48:25 -0500 Received: by mail-ej1-x62a.google.com with SMTP id ox12so17615137ejb.2 for ; Mon, 25 Jan 2021 03:48:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Gug9XGBPh/3SURIJqxVQnavvgMf6gEGJyHA8magW3t4=; b=xRO0RLl406myh08XXu2RoQSK8uj4+vwn47HTFALH2LkTdA1LH1ZjiDKciUN3sIvQMe GIIXzBB9c1LTnoa0wh0NsdOJnpZvvpgxxVrrc8Wuym5O8U223inqJI0LyKJ7E8jIbgMv PzyQH2gywhlV5+YcnJxl5z40owvDdE4mg6++qcSxo70nAX8xqYoQ58O7twuNfZVmV3IL 0R+XgGtKwIbn3znKuYZrmKzpHjovfn5Klf1V4Xtj03+8+CL47im3+m/RTvQa6VEPJszj RMaB/JaJfKIDEdn87mfBzRvJzlUZr+R+C/8fVTkYPrLGLnpzkemT5K3swp7aylYnS/Sr c3Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Gug9XGBPh/3SURIJqxVQnavvgMf6gEGJyHA8magW3t4=; b=cSItaBLISQguJdILfLbabNxVNY/yeVvNqRTXpfTJwFycosKa3eENXE1WRwFOLp9uSo 6zH9RD1sM29duvCYoOIOLOK531i9vc8y71mC9usY/eJO+48VfuVxB8avLvRYB+PdLmRZ kkavN/A46Cr49ok+y1TydRzCcsOp19G62CMvj+TRNBly5AQpJfitsW5Y9YA/Ke54ohiH yOzKvkngy2DEKc3y/NKbcaoWHn2FyGlwscx+FYScVqQG7+Bci8wec4Am4mSoZI9vOoOY gPTSGj6bpxwKBHXanNW9AfKh1IYTjygOxHblttos5rwGe1p+1/xS2FMVzJxfyCtof15K x8Mg== X-Gm-Message-State: AOAM532MlCXuwweTiMAQqZq2oCt8uHM2HRXjyXzFjL4jZkYwfOBAxqAh JUf5JrLNBhO3bCtyQ6weznxh5r22GyhBIS3nLqeasQ== X-Google-Smtp-Source: ABdhPJwx48fSmemx+AQCLN7/iG+QOi6SurCXCrwEktsF/D7Xu/Wof7b2B6tb0haJdLzezm4kIcFWUGTr/ZXFlm+UNEw= X-Received: by 2002:a17:907:1b10:: with SMTP id mp16mr116599ejc.482.1611575300559; Mon, 25 Jan 2021 03:48:20 -0800 (PST) MIME-Version: 1.0 References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-17-peter.maydell@linaro.org> In-Reply-To: From: Peter Maydell Date: Mon, 25 Jan 2021 11:48:09 +0000 Message-ID: Subject: Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-arm , QEMU Developers , Damien Hedde , Luc Michel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 11:48:26 -0000 On Thu, 21 Jan 2021 at 22:13, Philippe Mathieu-Daud=C3=A9 = wrote: > > Hi Peter, > > On 1/21/21 8:06 PM, Peter Maydell wrote: > > Convert the SSYS code in the Stellaris boards (which encapsulates the > > system registers) to a proper QOM device. This will provide us with > > somewhere to put the output Clock whose frequency depends on the > > setting of the PLL configuration registers. > > > > This is a migration compatibility break for lm3s811evb, lm3s6965evb. > > > > We use 3-phase reset here because the Clock will need to propagate > > its value in the hold phase. > > > > For the moment we reset the device during the board creation so that > > the system_clock_scale global gets set; this will be removed in a > > subsequent commit. > > + > > +struct ssys_state { > > + SysBusDevice parent_obj; > > + > > MemoryRegion iomem; > > uint32_t pborctl; > > uint32_t ldopctl; > > @@ -371,11 +376,18 @@ typedef struct { > > uint32_t dcgc[3]; > > uint32_t clkvclr; > > uint32_t ldoarst; > > + qemu_irq irq; > > + /* Properties (all read-only registers) */ > > uint32_t user0; > > uint32_t user1; > > - qemu_irq irq; > > - stellaris_board_info *board; > > -} ssys_state; > > + uint32_t did0; > > + uint32_t did1; > > + uint32_t dc0; > > + uint32_t dc1; > > + uint32_t dc2; > > + uint32_t dc3; > > + uint32_t dc4; > > Shouldn't these be class properties? Could you elaborate on what you think the code ought to look like? I just used the usual thing of defining uint32 qdev properties so we can set these values when we create the device, as a replacement for the existing code which either reaches directly into the state struct to set the user0/user1 values or sets the stellaris_board_info pointer in the state struct. thanks -- PMM From MAILER-DAEMON Mon Jan 25 10:26:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l43lQ-0004IC-V1 for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 10:26:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l3wnx-0006gB-Az for qemu-arm@nongnu.org; Mon, 25 Jan 2021 03:00:57 -0500 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]:35195) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l3wnv-0005BY-F2 for qemu-arm@nongnu.org; Mon, 25 Jan 2021 03:00:57 -0500 Received: by mail-ot1-x330.google.com with SMTP id 36so11954561otp.2 for ; Mon, 25 Jan 2021 00:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=GZ6hekqvldG8gMXqvg5p3uquzGRoC6fT/s0PAZ6iU4E=; b=cwI7pd2qxUW2atpX9r4oKTlej4g1m1MY/f56Dv7gygIaH2XhL6fJtA+R52sAgMAym4 3377PjLcytg94stXYz/5+AgyksqN6jJZOj6LCNn9iSOnYavPqdG8G+gN4Sj5Ph3TDHYZ s3Xdp7Gpx4QfY+GV/2PN73qnUnsRGXpd6hxCUwh7/KMGVIX2JBKkJxqCmFGISNIoK7vt hQOUDZi03pTw82UMeJx+HHI6on8f52+T4308Fd8jenS2Vh+0ll8aaQca0uB7UXKAkFYH KJ37UGHJXnXsggiy67L3gsLP69Q6RSI3jw4lgXzVLKEViSQaWCbNIt4OSKgZ6d4kYKCE LHXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=GZ6hekqvldG8gMXqvg5p3uquzGRoC6fT/s0PAZ6iU4E=; b=RmgKpuA2GArBRJrNWqzXle0l4P0q0Y7KHXfJzCoa7aeXXHkPqxAF9qVycf6rCWJe4Z 7t19iTPLyLn0q0W5v498FXZos5vTICzy1vKNPrIslS0zcYGQCkmIaOnWXoViMvhixMur EgtVrIVBdG/Bo47tWuPc0M6awNSL3ughzX53OdpyHQjxDM1ZK+lOOsCGieC1eQrHWsHd AoCvAsw2n7UgLrTtPTakhNmu+QGHAteTsKDwDootGnxk9oCL0FUAS17JLVBOq6JFMBgu RbwsQIywUB5f5UT5JpH34gt2/XgimTKjjJ1ReGZWsFWLV5MGxiCgIaqgYH7aWW5FLuMZ 3XjA== X-Gm-Message-State: AOAM532vWP2cunkkVSAenDEg3jpHaioL0pkE29gtyzbglT67/eU86Dzv JTLALI0jIBmDzmjXJNq3WUnzK8k4903Mz/dq/5r79RWJ9tI= X-Google-Smtp-Source: ABdhPJzGr0TLBHMxXhn6motorHxB2JLA+347UfRZJsuc6f4Yd4B0QYSchq4NITMox573AqUBceTeQi6lGsl95EjjT9w= X-Received: by 2002:a9d:313:: with SMTP id 19mr607405otv.147.1611561649651; Mon, 25 Jan 2021 00:00:49 -0800 (PST) MIME-Version: 1.0 From: =?UTF-8?B?2KfZhNin2K3Yqtix2KfZgdmK2Kkgw4Y=?= Date: Mon, 25 Jan 2021 11:00:36 +0300 Message-ID: Subject: question about qemu user static To: qemu-arm@nongnu.org Content-Type: multipart/alternative; boundary="000000000000af82f305b9b4ef11" Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=po99h6@gmail.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Jan 2021 10:26:47 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 08:00:57 -0000 --000000000000af82f305b9b4ef11 Content-Type: text/plain; charset="UTF-8" why is qemu-x86_64 user emulation is 64bit only like if I wanted to install wine and wine has 32bit libraries or if I want to run a program that has 32bit libraries so I don't know what's going on with that x86_64 emulator can someone tell me? --000000000000af82f305b9b4ef11 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
why is qemu-x86_64 user emulation is 64= bit only
like if I wanted to install wine and wine h= as 32bit libraries=C2=A0
or if I want to run a progr= am that has 32bit libraries
so I don't know what= 's going on with that x86_64 emulator can someone tell me?
--000000000000af82f305b9b4ef11-- From MAILER-DAEMON Mon Jan 25 10:59:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l44HQ-0002Mn-EG for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 10:59:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l44HP-0002Mh-O8 for qemu-arm@nongnu.org; Mon, 25 Jan 2021 10:59:51 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:37848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l44HO-0002qE-BL for qemu-arm@nongnu.org; Mon, 25 Jan 2021 10:59:51 -0500 Received: by mail-ed1-x52f.google.com with SMTP id g1so15997599edu.4 for ; Mon, 25 Jan 2021 07:59:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=hB06iBXWfdKSRbIxnh8gRXNg4Z/CV1FQ8+9uIrzX4dY=; b=CYcSHC/JoZz5zdvAbJBWtuE7ON2Cfw3W+WN98RdVF/KBLUr1wkI4dZWaRWxHjQbsQK msjDBqfm/ULHuxWuscHsXLcsR25GFcpW7vZBBJ7GfGGi+MAPfbK0EvoEjOsT6N8wbXPf MSC1EGGVfikOwpeSlN+/iqcMt4Y8+ZqkHXamZTyXmiwnKK9NANaXWsD3+/Az2TW2HDzU DYIP+5FDQBU/4twGfkRUn8G+518+KHiTZLA7QdLeROm4wfdzieIRtfzhUckqqrBtEnQk vx5tRPYgsErdQDZh8agAbtTRoLuUpk0Gvr0lXxNUS2Hqrywx2iiGNBiK2w9+VKf4ReLU 6yCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=hB06iBXWfdKSRbIxnh8gRXNg4Z/CV1FQ8+9uIrzX4dY=; b=iQcw/jxU+4g+alG08GWjbUSWhIt2y4iYsJrcEWqHeD4g2wxiSu5E4KwuEogyqe8Q6w XzJP5L2gfsgqOFccJKYBU1l0ZKqX9YbNB8iLfnBU6+TV41txTlhDm9VWq6GrEV9JXpZM IbYOAhU7U1tGzn4d5xcx2rgPgEPm5oRhcmq3HN0CHouRPgChL+wl0vBDrMoh/j5qhg3j ZTNWYc7By3Db9MtGZaPVDBiLh0oHl4Nc01pZ0SZIJ5ubYpicm4YrnHsavItefEPatrca fZctaUmt14cDb+RvQ/k02vEHwJDFamZunACjWwITYDHWq23Hia7+OJK65sBhlaxVh1V0 AjPA== X-Gm-Message-State: AOAM533w7QbPqfaFkyK7cJYakH2Sa9AyBCxjlF1vMST/zUx9qR2l4Y0K Vdm/eQdEK5k3yul3UZzVzuJj/kptznknQxogoFQo/A== X-Google-Smtp-Source: ABdhPJzGZJ55f+EIFjF5buw41h3bOTfnd5302TrqPJRpmNj/HkyHQ1wGQv+ZX0/xH4GyxD+Jkx0M26BELF9p31Vk2A0= X-Received: by 2002:aa7:dd12:: with SMTP id i18mr1041374edv.36.1611590388415; Mon, 25 Jan 2021 07:59:48 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Peter Maydell Date: Mon, 25 Jan 2021 15:59:37 +0000 Message-ID: Subject: Re: question about qemu user static To: =?UTF-8?B?2KfZhNin2K3Yqtix2KfZgdmK2Kkgw4Y=?= Cc: qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 15:59:51 -0000 =E2=80=AAOn Mon, 25 Jan 2021 at 15:28, =E2=80=AB=D8=A7=D9=84=D8=A7=D8=AD=D8= =AA=D8=B1=D8=A7=D9=81=D9=8A=D8=A9 =C3=86=E2=80=AC=E2=80=8E wrote:=E2=80=AC > why is qemu-x86_64 user emulation is 64bit only Because the user-emulator binaries are specifically "implement this kernel ABI", which includes not just the general CPU architecture but also whether it is 64 bit or 32 bit. You can see this also on other architectures like qemu-arm and qemu-aarch64. It's also why there are lots of mips user-mode emulators: qemu-mips, qemu-mipsel, qemu-mipsn32, qemu-mipsn32el, qemu-mips64, etc, etc: these all represent different and incompatible ABIs. > like if I wanted to install wine and wine has 32bit libraries > or if I want to run a program that has 32bit libraries If you want to run a guest program built for the 32-bit x86 ABI, use qemu-i386. thanks -- PMM From MAILER-DAEMON Mon Jan 25 16:47:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l49hb-0007iZ-OM for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 16:47:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l49Tp-0004dO-BB for qemu-arm@nongnu.org; Mon, 25 Jan 2021 16:33:01 -0500 Received: from 66-220-144-178.mail-mxout.facebook.com ([66.220.144.178]:37861) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l49Tn-0002zB-S4 for qemu-arm@nongnu.org; Mon, 25 Jan 2021 16:33:01 -0500 Received: by devvm2477.prn0.facebook.com (Postfix, from userid 221162) id C517B43DB0C7; Mon, 25 Jan 2021 13:08:42 -0800 (PST) From: =?UTF-8?q?Daniel=20M=C3=BCller?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, =?UTF-8?q?Daniel=20M=C3=BCller?= Subject: [PATCH] target/arm: Correctly initialize MDCR_EL2.HPMN Date: Mon, 25 Jan 2021 13:08:17 -0800 Message-Id: <20210125210817.2564212-1-muellerd@fb.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: none client-ip=66.220.144.178; envelope-from=muellerd@devvm2477.prn0.facebook.com; helo=66-220-144-178.mail-mxout.facebook.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NO_DNS_FOR_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_DYNAMIC=0.982, SPF_HELO_PASS=-0.001, SPF_NONE=0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Jan 2021 16:47:12 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 21:33:02 -0000 When working with performance monitoring counters, we look at MDCR_EL2.HPMN as part of the check whether a counter is enabled. This check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no counters are "enabled" for < EL2. That's in violation of the Arm specification, which states that > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > PMCR_EL0.N That's also what a comment in the code acknowledges, but the necessary adjustment seems to have been forgotten when support for more counters was added. This change fixes the issue by setting the reset value to PMCR.N, which is four. Signed-off-by: Daniel M=C3=BCller --- target/arm/helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ead3fcbd..195db4d378 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5705,13 +5705,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, #endif /* The only field of MDCR_EL2 that has a defined architectural reset= value - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; b= ut we - * don't implement any PMU event counters, so using zero as a reset - * value for MDCR_EL2 is okay + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 4, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, --=20 2.24.1 From MAILER-DAEMON Mon Jan 25 18:32:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4BLk-0000rG-6I for mharc-qemu-arm@gnu.org; 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Mon, 25 Jan 2021 18:32:42 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-78-g36b56e88ef-fm-20210120.001-g36b56e88 Mime-Version: 1.0 Message-Id: <083767b3-3621-4735-9f05-77153f6894a1@www.fastmail.com> In-Reply-To: References: <994f40e1-2a5b-4b7a-a4aa-23f824881d8a@www.fastmail.com> Date: Tue, 26 Jan 2021 10:32:21 +1100 From: "Berto Furth" To: "Peter Maydell" Cc: qemu-arm , "QEMU Developers" Subject: Re: KVM guests reading/writing guest memory directly and accurately Content-Type: text/plain Received-SPF: pass client-ip=64.147.123.25; envelope-from=bertofurth@sent.com; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 23:32:47 -0000 Thanks so much for your help and encouragement Peter. I really appreciate it. All the best! On Mon, 25 Jan 2021, at 03:07, Peter Maydell wrote: > On Sun, 24 Jan 2021 at 07:22, Berto Furth wrote: > > Can anyone give me some advice on how a machine or device can read and write kvm guest ram memory and get a guaranteed up to date result? Can someone point me at an example in the latest QEMU source code? I'm working with an ARM-32 guest (-cpu host,aarch64=off) running on an ARM-64 host (Cortex A72 - Raspberry Pi4b). > > > > I have a problem where if I write directly to my guest RAM, (such as a DMA transfer) then the guest can't see the change straight away. Similarly when the host writes memory, the guest doesn't see the change until much later. > > > > If during a KVM_EXIT_MMIO the qemu host changes some values in guest ram memory (via address_space_write() or cpu_physical_memory_rw() etc...) , is there a way to make the guest be able to accurately read that memory as soon as the exit is complete. Additionally if a guest changes a value in ram just before a KVM_EXIT_MMIO, is there a way to ensure that the QEMU host can then read the up to date newly set values? > > With KVM I think this is just normal "multiple threads/CPUs both > accessing one in-memory data structure" effects, so you need a > memory barrier to ensure that what one thread has written is > visible to the other. I think that the idea is that > the functions in include/sysemu/dma.h provide a dma_barrier() (which is > just a CPU memory barrier) and some wrapper functions which put in the > barrier on the right side of a read or write operation. On the guest > side it should already be using the right barrier insns in order > to ensure that real hardware DMA sees the right view of RAM... > > We're very inconsistent about using these -- I've never liked the way > we have separate 'dma' operations here rather than having the normal > functions Just Work. But I haven't ever looked very deeply into what > the requirements in this area are. > > > I understand that the proper thing to do is to set up the memory region in question as MMIO so that when the guest accesses this memory a KVM_EXIT_MMIO will occur but the memory region in question has to be executable and MMIO memory areas are not executable in QEMU. In addition it's not easily possible to predict before hand exactly what memory addresses are going to be involved in DMA, so I'd prefer to avoid having to dynamically construct little MMIO memory islands inside the main guest ram space as the guest runs. > > You only want to mark regions as MMIO if they need to actually come > out to QEMU for the guest memory access to be handled -- typically > this is device MMIO-mapped register banks. Normal RAM isn't mapped > as MMIO. > > > I'm assuming that the guest could be modified to disable d-caching (modify the ARM register SCTLR / p15 ?) and that may help but I'm desperately trying to avoid that if possible because I'm working with a proprietary "blob" on the guest that I don't have all the source code for. > > With Arm KVM doing this wouldn't help; in fact it would make things > worse, because then the view of guest RAM that the guest sees has > the non-cacheable attribute, but the view of guest RAM that QEMU > has mapped is still cacheable, so the two get hopelessly mismatched > ideas of what the RAM contents are. > > (Side note: if the guest wants to map RAM as non-cacheable, this > won't work with Arm KVM (unless the host CPU supports FEAT_S2FWB, > which is an Armv8.4 feature), for the same "QEMU and guest view > of the same block of RAM disagree about whether it's cached" reason. > The most commonly encountered case of this is that you can't use a > normal VGA PCI graphics device model with KVM, because the guest maps > the graphics RAM on the device non-cacheable.) > > > I know it's not very professional of me to make an emotional plea, but I've been working on this for weeks and I am desperately hoping someone can point to a solution for me. I am not a KVM expert and so I'm hoping I'm just missing something simple and obvious that one of you can quickly point out for me. > > Nah, this isn't obvious stuff -- a lot of QEMU's internals aren't > very well documented and often are inconsistent about whether they > do things correctly or not... > > thanks > -- PMM > From MAILER-DAEMON Mon Jan 25 18:49:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4BbS-0006Nt-UJ for mharc-qemu-arm@gnu.org; Mon, 25 Jan 2021 18:49:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <35lgPYAgKCNsTRE7LQPEDLLDIB.9LJNBJR-7OJKLKDKR.LOD@flex--wuhaotsh.bounces.google.com>) id 1l4BbS-0006MH-1x for qemu-arm@nongnu.org; Mon, 25 Jan 2021 18:49:02 -0500 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]:42253) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <35lgPYAgKCNsTRE7LQPEDLLDIB.9LJNBJR-7OJKLKDKR.LOD@flex--wuhaotsh.bounces.google.com>) id 1l4BbN-00038d-27 for qemu-arm@nongnu.org; Mon, 25 Jan 2021 18:49:01 -0500 Received: by mail-pg1-x549.google.com with SMTP id j37so8950769pgb.9 for ; Mon, 25 Jan 2021 15:48:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:message-id:mime-version:subject:from:to:cc; bh=I+jzqQbXvQgWEuHn+S1cGshEJkxZZv/tRlV4YBUAhVY=; b=mRCTh8N3GYdCOaCaGlFqMFUkJp0rJ0i4BEUeKzpQ9hW1vK8AcNT6ij0J4irEMjEZCJ 5OnxJb4TbhFrboNDKEKYjKt9fV9NXN9dXUfEO9nNVGvrQF14SRBaQOby/0GMs1NyZ9Zg Njr0zji/DBdO2OlHsbc5ZZm6W6Xx5bjuxsF8f92NjBhPMGoAqxgmqm7ah9UQ0ghxHBH9 56S+JOH6KhFVlcvUiFGPT9T9MU+xzYYxDQkgRudf34NRoFy0skXb/CzQhjY6TLPfe+01 hDsdhJ+mg35SNprl5yqHAS+g2TpEX7IlvJAigpSV+KxlBrfB5P7fTxrjOAt8rZW+FQvB MNVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:message-id:mime-version:subject:from :to:cc; bh=I+jzqQbXvQgWEuHn+S1cGshEJkxZZv/tRlV4YBUAhVY=; b=RBQlvqyanFlgqjHQR5R3RD6mU3ay1KdsKMHED4P+845zGM/s8q9CBST1IP0QAUffaZ NM0y64DIX9oIuWp0R4hVY1uVhibmVfdbC6A8dJaw4CQUYbEQHb8SMBga/1aRwUd28tQX GiO/U9wEnZgQ8WhvGy0Gq8b3xUhX4dygmfhzKntgE1J34RWaFcwkkMUjhnzvB+f4yev3 xsfem/gaqsPVv6NJj1XUBbtNxBfxcoR1TWLdCoezSOBaEsSgoMwizoS+2y5BA2wVrcaN VKArT1nivOHyJf1jvrAulPMRbsNyA2ByrM2UDbtiuXCRfujDmYUXUECR0rHY8Jztr+4h 8pgw== X-Gm-Message-State: AOAM533XsZHp9JFvYE/L1cBTVRoSyGw0rbAcjt6pU6w3bae+lYlRSmyU XUZrMbnob2o/Cpgw2SvLTLTZjs4fuQyPqg== X-Google-Smtp-Source: ABdhPJwCxBtjWpteiEJxI0dYDZjWQ7m1nZJzBi5EzLtJpn2EhrpC7Eacsrozx1WxSGDUTLbnLkB4YDowN4VNMA== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:902:b189:b029:dc:4102:4edf with SMTP id s9-20020a170902b189b02900dc41024edfmr3086577plr.80.1611618534131; Mon, 25 Jan 2021 15:48:54 -0800 (PST) Date: Mon, 25 Jan 2021 15:48:36 -0800 Message-Id: <20210125234836.607233-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.30.0.280.ga3ce27912f-goog Subject: [PATCH] hw/misc: Fix arith overflow in NPCM7XX PWM module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-trivial@nongnu.org, wuhaotsh@google.com, hskinnemoen@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=35lgPYAgKCNsTRE7LQPEDLLDIB.9LJNBJR-7OJKLKDKR.LOD@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Jan 2021 23:49:02 -0000 There's a potential arith overflow in npcm7xx_pwm_calculate_duty. This patch fixes it. Thanks Peter for finding this out. Signed-off-by: Hao Wu --- hw/misc/npcm7xx_pwm.c | 4 ++-- tests/qtest/npcm7xx_pwm-test.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c index e99e3cc7ef..90b4f630a0 100644 --- a/hw/misc/npcm7xx_pwm.c +++ b/hw/misc/npcm7xx_pwm.c @@ -102,9 +102,9 @@ static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) if (p->cnr == 0) { duty = 0; } else if (p->cmr >= p->cnr) { - duty = NPCM7XX_PWM_MAX_DUTY; + duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY; } else { - duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); + duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); } } else { duty = 0; diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c index 63557d2c06..f55571b31d 100644 --- a/tests/qtest/npcm7xx_pwm-test.c +++ b/tests/qtest/npcm7xx_pwm-test.c @@ -280,7 +280,7 @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) } else if (cmr >= cnr) { duty = MAX_DUTY; } else { - duty = MAX_DUTY * (cmr + 1) / (cnr + 1); + duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1); } if (inverted) { -- 2.30.0.280.ga3ce27912f-goog From MAILER-DAEMON Tue Jan 26 01:04:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4HSe-0005lV-5b for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 01:04:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4HSc-0005gO-BA; Tue, 26 Jan 2021 01:04:18 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4HSZ-0002fl-PW; Tue, 26 Jan 2021 01:04:17 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DPx3t1fYbzjCLX; Tue, 26 Jan 2021 14:03:06 +0800 (CST) Received: from [10.174.186.182] (10.174.186.182) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Tue, 26 Jan 2021 14:03:55 +0800 Subject: Re: [RFC PATCH v2 0/3] vfio: Some fixes and optimizations for VFIO migration To: Alex Williamson CC: Cornelia Huck , Kirti Wankhede , "Dr . David Alan Gilbert" , , Eric Auger , , , "Neo Jia" , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> From: Shenming Lu Message-ID: <76b14984-3574-6093-238a-9b9eb4b2ef2d@huawei.com> Date: Tue, 26 Jan 2021 14:03:54 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <20201209080919.156-1-lushenming@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.186.182] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=lushenming@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 06:04:18 -0000 On 2020/12/9 16:09, Shenming Lu wrote: > This patch set includes two fixes and one optimization for VFIO migration > as blew: > Patch 1-2: > - Fix two ordering problems in migration. > > Patch 3: > - Optimize the enabling process of the MSI-X vectors in migration. > Hi, Friendly ping, is there any further comments on this series (especially for patch 1 and 3)? :-) Thanks, Shenming > > Shenming Lu (3): > vfio: Move the saving of the config space to the right place in VFIO > migration > vfio: Set the priority of the VFIO VM state change handler explicitly > vfio: Avoid disabling and enabling vectors repeatedly in VFIO > migration > > hw/pci/msix.c | 17 +++++++++++++++++ > hw/vfio/migration.c | 28 +++++++++++++++++----------- > hw/vfio/pci.c | 10 ++++++++-- > include/hw/pci/msix.h | 2 ++ > 4 files changed, 44 insertions(+), 13 deletions(-) > From MAILER-DAEMON Tue Jan 26 01:56:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4IGt-00052k-AL for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 01:56:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4IGr-0004xp-7W; Tue, 26 Jan 2021 01:56:13 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:42062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4IGp-0003N2-IW; Tue, 26 Jan 2021 01:56:12 -0500 Received: by mail-ej1-x62a.google.com with SMTP id r12so21455565ejb.9; Mon, 25 Jan 2021 22:56:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=32aGueFSV2uVi9yEC9Wg3aow+A/sRmFRH4xj/YR6gpA=; b=GVN7V7DrjgwXM4VzwvVuI+INA8c/TpTy8XP3jd+5je+AwKZgaW/wEqRY0GqprihO+k 0asLviPRdMjGGe+TdgblyCx9rDbsbOnbRDJNq8s10XDRu59tG+CE+OR4/0HUUtY+KL2U RVVPpuBpdht+ISkeapnzfOgbcR1lKXZH6dWAWvh0D8DhXS4n5TlxPzUDw44KD53DBsmg xKD0tdVSagY+YzqGSJAYH2UAOFl6xJrV2/Rj3pgDXxbdFJUs1ZtE08+MZwhlHIX+RnnJ elKWTEQ9VrjH84NqCjVH1RkJoxKOyT0qinqXdRJ7CuhhW9HAk+wrp/2kE58jTK8x7uby u+/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=32aGueFSV2uVi9yEC9Wg3aow+A/sRmFRH4xj/YR6gpA=; b=QfgL+ZfbBh0lZf61VUrWMdNa1zB1v+xwqCBpqYnO5mjt4qx3o9+WYN8M2ri0ZCbYAV QeRHxgJ92mFZX32H3V4f9CcOQ96YQt2VrKBm8HHnogzMBrU6O2JBzUx1tPzmOAlewUcJ SwzN/JVKRU5v+I3I5Fw6MbMRIeYb6EZ+W9RKy9Seuv2SABmyMpj8opqevVxnPoTWbSjN LALKenJFq0Z4VHA1hziYWaESYK1KPtvXI3JeThLzmrJc5AzHDbY/9doEyMIVzTsfQdRU C9AhjOF/v7OyjprQhlX8Q8lMeRUN8kzKS62PfCOSvV6+3qoh+2Ev9UgZmu/KIii6DAG2 GnZg== X-Gm-Message-State: AOAM531rtqUidPkJ995pJocEeSEcNFHYfEa8HGKur6v+UENGhjUDqCGD GewyZ/0DBJM7HWYc27/IhAk= X-Google-Smtp-Source: ABdhPJzU0/TLsKEkB+nlv/JMFOmqA3kRrgoCEZvWTViPOMBbAwJUWK2GStxJzBkLSJb0VQmNSh5xVA== X-Received: by 2002:a17:906:f0c3:: with SMTP id dk3mr2529601ejb.540.1611644168883; Mon, 25 Jan 2021 22:56:08 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id y59sm12447442ede.59.2021.01.25.22.56.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Jan 2021 22:56:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH] hw/misc: Fix arith overflow in NPCM7XX PWM module To: Hao Wu , peter.maydell@linaro.org Cc: qemu-trivial@nongnu.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, hskinnemoen@google.com References: <20210125234836.607233-1-wuhaotsh@google.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <52a16c14-820b-762c-d74f-e29fac912beb@amsat.org> Date: Tue, 26 Jan 2021 07:56:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210125234836.607233-1-wuhaotsh@google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 06:56:13 -0000 Hi Hao Wu, On 1/26/21 12:48 AM, wuhaotsh--- via wrote: > There's a potential arith overflow in npcm7xx_pwm_calculate_duty. > This patch fixes it. ^ not very useful information ;) What about the simplest approach Peter suggested, a 32-bit duty? > Thanks Peter for finding this out. Technically Coverity found this out. Using QEMU git tags, this is: Fixes: CID 1442342 Suggested-by: Peter Maydell > Signed-off-by: Hao Wu > --- > hw/misc/npcm7xx_pwm.c | 4 ++-- > tests/qtest/npcm7xx_pwm-test.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c > index e99e3cc7ef..90b4f630a0 100644 > --- a/hw/misc/npcm7xx_pwm.c > +++ b/hw/misc/npcm7xx_pwm.c > @@ -102,9 +102,9 @@ static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) > if (p->cnr == 0) { > duty = 0; > } else if (p->cmr >= p->cnr) { > - duty = NPCM7XX_PWM_MAX_DUTY; > + duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY; > } else { > - duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); > + duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); > } > } else { > duty = 0; > diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c > index 63557d2c06..f55571b31d 100644 > --- a/tests/qtest/npcm7xx_pwm-test.c > +++ b/tests/qtest/npcm7xx_pwm-test.c > @@ -280,7 +280,7 @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) > } else if (cmr >= cnr) { > duty = MAX_DUTY; > } else { > - duty = MAX_DUTY * (cmr + 1) / (cnr + 1); > + duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1); > } > > if (inverted) { > From MAILER-DAEMON Tue Jan 26 02:09:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4IU0-0006E4-Ex for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 02:09:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4ITy-0006BM-CC; Tue, 26 Jan 2021 02:09:46 -0500 Received: from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]:51157) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4ITv-0007oQ-P5; Tue, 26 Jan 2021 02:09:45 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.108.1.141]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 647777F4D16C; Tue, 26 Jan 2021 08:09:39 +0100 (CET) Received: from kaod.org (37.59.142.105) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 26 Jan 2021 08:09:38 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-105G0066d7b8d4f-3e69-48f2-93ca-e44363ec3563, 5D556FFD98B84F2EA34A7A8BED120B5F5B9D3368) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Subject: Re: [RFC PATCH v2 04/20] hw/arm/aspeed_soc: Mark the device with no migratable fields To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , "Dr. David Alan Gilbert" , CC: Mark Cave-Ayland , , Marcel Apfelbaum , Artyom Tarasenko , Paolo Bonzini , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Peter Maydell , Subbaraya Sundeep , Andrew Jeffery , Juan Quintela , Eduardo Habkost , Andrew Baumann , Gerd Hoffmann , Joel Stanley , Laurent Vivier References: <20210117192446.23753-1-f4bug@amsat.org> <20210117192446.23753-5-f4bug@amsat.org> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <2314bde6-58da-fde4-885a-1df380be766b@kaod.org> Date: Tue, 26 Jan 2021 08:09:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210117192446.23753-5-f4bug@amsat.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [37.59.142.105] X-ClientProxiedBy: DAG2EX1.mxp5.local (172.16.2.11) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: 7cb56b63-8a51-4b8c-807c-7abb7bb3ea6d X-Ovh-Tracer-Id: 13849413280123685834 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduledrvdeggddutddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepuffvfhfhkffffgggjggtgfhisehtkeertddtfeejnecuhfhrohhmpeevrogurhhitggpnfgvpgfiohgrthgvrhcuoegtlhhgsehkrghougdrohhrgheqnecuggftrfgrthhtvghrnhepjeekudeuudevleegudeugeekleffveeludejteffiedvledvgfekueefudehheefnecukfhppedtrddtrddtrddtpdefjedrheelrddugedvrddutdehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehfgegsuhhgsegrmhhsrghtrdhorhhg Received-SPF: pass client-ip=178.32.125.2; envelope-from=clg@kaod.org; helo=smtpout1.mo529.mail-out.ovh.net X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_SBL=0.141, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 07:09:46 -0000 On 1/17/21 8:24 PM, Philippe Mathieu-Daudé wrote: > This device doesn't have fields to migrate. Be explicit > by using vmstate_qdev_no_state_to_migrate. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Thanks, C. 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id j5sm2848494pjf.47.2021.01.26.09.10.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Jan 2021 09:10:53 -0800 (PST) Subject: Re: [PATCH v3 11/21] exec: Add support for TARGET_TAGGED_ADDRESSES To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-12-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 26 Jan 2021 07:10:50 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 17:10:58 -0000 On 1/22/21 4:13 AM, Peter Maydell wrote: > On Fri, 15 Jan 2021 at 22:47, Richard Henderson > wrote: >> >> The AArch64 Linux ABI has always enabled TBI, but has historically >> required that pointer tags be removed before a syscall. This has >> changed in the lead-up to ARMv8.5-MTE, in a way that affects the >> ABI generically and not specifically to MTE. >> >> This patch allows the target to indicate that (1) there are tags >> and (2) whether or not they should be taken into account at the >> syscall level. >> >> Adjust g2h, guest_addr_valid, and guest_range_valid to ignore >> pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok >> in the arm64 kernel source. >> >> The prctl syscall is not not yet updated, so this change by itself >> has no visible effect. >> >> Signed-off-by: Richard Henderson >> --- >> include/exec/cpu_ldst.h | 20 +++++++++++++++++--- >> 1 file changed, 17 insertions(+), 3 deletions(-) >> >> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h >> index e62f4fba00..1df9b93e59 100644 >> --- a/include/exec/cpu_ldst.h >> +++ b/include/exec/cpu_ldst.h >> @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; >> #define TARGET_ABI_FMT_ptr "%"PRIx64 >> #endif >> >> +static inline abi_ptr untagged_addr(abi_ptr x) >> +{ >> +#ifdef TARGET_TAGGED_ADDRESSES >> + if (current_cpu) { >> + return cpu_untagged_addr(current_cpu, x); >> + } >> +#endif >> + return x; >> +} > > The current_cpu global is a nasty hack and I don't like seeing > new usages of it. In particular, it's very difficult to > analyse in what places this will get called when current_cpu is > NULL and whether it's always OK to not clean the tag in that > situation. Well, that'll be a really lot of changes to add cpu/env as an argument to get_user et al. Let's see how easily coccinelle can fix em all up for me... r~ From MAILER-DAEMON Tue Jan 26 14:33:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5I-0004WM-CB for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3ZG4QYAgKCIk97un165ut11tyr.p1z3rz7-n4z010t07.14t@flex--wuhaotsh.bounces.google.com>) id 1l4U5C-0004Uk-TV for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:00 -0500 Received: from mail-qk1-x749.google.com ([2607:f8b0:4864:20::749]:34658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3ZG4QYAgKCIk97un165ut11tyr.p1z3rz7-n4z010t07.14t@flex--wuhaotsh.bounces.google.com>) id 1l4U59-00045z-M3 for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:32:58 -0500 Received: by mail-qk1-x749.google.com with SMTP id v82so13237247qka.1 for ; Tue, 26 Jan 2021 11:32:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:message-id:mime-version:subject:from:to:cc; bh=/JN1lLN3S8bni2bQFj3ryjv5Yrpf4V6ED6Yz/THzn/I=; b=S/h35lygBa8LOjiZFqhtQYoAExcr9YMxB/0ZxMAHF+umcEUt0SqPXOfJJZ5apslxBi aDZDK8K6aHB0waTBqJtUgv3GCG/KjAlI6aRcEDGVmN++p6FViJJ8ue5X3fOikRHFqlOt uPoWO9KwGOFOrfFJBJ38oZ/sCvSYJ4oMo6DKyaLhkZpTiUjihw6WZnhwaia6LDM21Elu zqOl3X8rm/CqJDU+lFtlGUWxhxQq3fIoDnF5bgO70n4LuiQjE+JJwCrduiVWNQI55FO6 D+qCRf72MAAaNc9auWhzWz8XlnABgh8pDkuBcOo0AZGsCaL7YoUQJY3N7iO71xxIDIFI JXcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:message-id:mime-version:subject:from :to:cc; bh=/JN1lLN3S8bni2bQFj3ryjv5Yrpf4V6ED6Yz/THzn/I=; b=VFB7HtHnTJaYP2aWv8ZNLKz5zYdwjbklyM2k+lfKYF4r2eX4UyMExjEKyuknJcTaWw x2zNC2Bz+J3z1YlKDN9u5rVGGagyHfYN17SFVpObzJJwJo3Ca4vowx+h6qEBOHYY03bN 56oIk0Wrq4p3OzWSmROJbUIzcy/WpxWtBWsk8anPNELTnn2+ls60v1ANzaA2WBH9Zog/ sRqkN+86sSU0OO9Brq/ItKczYyhOnNu+PLt2EkmM48ZKSyiTdFIJU9humBf4kf1XjLPM ttUKorIBfhjJls1nX5yJiZ5Q2KFj/xcceBN2OIk3G2bxiRCuGTTVPvdsn0D3uU0DQhSP pnWg== X-Gm-Message-State: AOAM530NMihkEJJZaJupUgArb27xQ7GJ0uhbI9GjH4q1gLsrme8v6m+F U0OoV+Es/mFFZgIo0X33zPFt4kxzrbbj5w== X-Google-Smtp-Source: ABdhPJyeePfjJIMAgx5WryzSRlGl1dLA7U0JqTfkU6SRbDghaFQUG57nlD1c8M3Yf6XopIPjkgki7TI7/dvdVQ== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a0c:bf12:: with SMTP id m18mr7138242qvi.40.1611689572143; Tue, 26 Jan 2021 11:32:52 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:31 -0800 Message-Id: <20210126193237.1534208-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 0/6] hw/i2c: Add NPCM7XX SMBus Device From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::749; envelope-from=3ZG4QYAgKCIk97un165ut11tyr.p1z3rz7-n4z010t07.14t@flex--wuhaotsh.bounces.google.com; helo=mail-qk1-x749.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:00 -0000 This patch set implements the System manager bus (SMBus) module in NPCM7XX SoC. Basically, it emulates the data transactions of the module, not the SDA/SCL levels. We have also added a QTest which contains read and write operations for both single-byte and FIFO mode, and added basic I2C device trees for npcm750-evb and quanta-gsj boards. We also cleaned up the unimplemented GPIO devices in npcm7xx.c since they are already implemented. Hao Wu (6): hw/arm: Remove GPIO from unimplemented NPCM7XX hw/i2c: Implement NPCM7XX SMBus Module Single Mode hw/arm: Add I2C device tree for NPCM750 eval board hw/arm: Add I2C device tree for Quanta GSJ hw/i2c: Add a QTest for NPCM7XX SMBus Device hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 76 ++- hw/arm/npcm7xx_boards.c | 32 + hw/i2c/meson.build | 1 + hw/i2c/npcm7xx_smbus.c | 1071 ++++++++++++++++++++++++++++++ hw/i2c/trace-events | 12 + include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 113 ++++ tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_smbus-test.c | 495 ++++++++++++++ 10 files changed, 1780 insertions(+), 25 deletions(-) create mode 100644 hw/i2c/npcm7xx_smbus.c create mode 100644 include/hw/i2c/npcm7xx_smbus.h create mode 100644 tests/qtest/npcm7xx_smbus-test.c -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5J-0004XW-Ht for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3ZW4QYAgKCIoA8vo276vu22uzs.q204s08-o50121u18.25u@flex--wuhaotsh.bounces.google.com>) id 1l4U5G-0004VZ-Dg for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:03 -0500 Received: from mail-qv1-xf49.google.com ([2607:f8b0:4864:20::f49]:51527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3ZW4QYAgKCIoA8vo276vu22uzs.q204s08-o50121u18.25u@flex--wuhaotsh.bounces.google.com>) id 1l4U5C-00046C-CU for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:01 -0500 Received: by mail-qv1-xf49.google.com with SMTP id h13so12178348qvo.18 for ; Tue, 26 Jan 2021 11:32:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=MXpYq4rGrYnKEV9MTkJ+FJRm52fVhSZVjQB4Boy0H48=; b=uU0WUUwpdX3IZlYrrj1mvLpU5jPBGleS0tjUfD9ccfsMVIzHNWrQ4+unNqiyKMfFyf wmUrAaQ7tBG328TbAIVVz0lmUZTF8CEmdAPoTp11pt+eV/4LXItPTRo5b0XIVXZRrNIx poD9iliNfKc5VvMOtbn5lXkRkTmHJZrVvNV5XZHgb9mIEr+SF2c+r/UAKAELs1Na8Vw2 WEiuejXlLnA4ftPZDBGvsGq7bdLxzuFI0vpdVWtM0eQCiiFGWzViErbdCVvOVnsbBYXJ iVOLyQgl5xshDtBEH7Oi3wg4CHf237BsLi03eUF/OL0pmQL5qDDjxMRGYPwwk3vk+u5r KVRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=MXpYq4rGrYnKEV9MTkJ+FJRm52fVhSZVjQB4Boy0H48=; b=O4SVWvTRppR7hGkOcCmkb78sBBIVFPQX7Ert0D+wR2b+JrmGEhLIDLhgvsbw7szWrg zOM6XqvWJORAhKHOiLwXdsNLytVL1rNUCPz7+aDEHXeV0HQUpbrHLMZjJFzDcjV5KRBV ruC4bReRDbyct2cXZC6zP5OyAF5ElDKEHwm8XUjTAQFUvBY63EKaX86bHdKr2OJkcJ6K 2iKE6CB14YMEW7pTbGFkMTols3PZOtNeXljcnXjdjFlDe73M9AN9KwVLnZl2X+MmkQUP RAYd6Dag8FzeIgp4O6hp44jV4wjC+RI78mEFKjcLXuvHxFH1l4/MAO1J7cjFr/oROuh3 7Wbg== X-Gm-Message-State: AOAM530oH2Oh5hcdbUg7qthowtivgGzXusXnA8CCG8fMqh2aiTRmQ7uY nr/+DdTTmCPeTqplv5AHr1wsleRpxMGiSw== X-Google-Smtp-Source: ABdhPJyyqfMJP7CxNqTlls3KR4GAc7WWQ/JFkRdHIt9A5hHPLlBxlVA4AYQrEjaKuBzWLjUmQ5Z06I5yVvVjmg== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a0c:ab1a:: with SMTP id h26mr7122375qvb.26.1611689573821; Tue, 26 Jan 2021 11:32:53 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:32 -0800 In-Reply-To: <20210126193237.1534208-1-wuhaotsh@google.com> Message-Id: <20210126193237.1534208-2-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 1/6] hw/arm: Remove GPIO from unimplemented NPCM7XX From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::f49; envelope-from=3ZW4QYAgKCIoA8vo276vu22uzs.q204s08-o50121u18.25u@flex--wuhaotsh.bounces.google.com; helo=mail-qv1-xf49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:03 -0000 NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 72040d4079..d1fe9bd1df 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -576,14 +576,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5T-0004bn-HV for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3am4QYAgKCI8FD0t7CB0z77z4x.v759x5D-tA5676z6D.7Az@flex--wuhaotsh.bounces.google.com>) id 1l4U5P-0004YZ-9c for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:11 -0500 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]:36971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3am4QYAgKCI8FD0t7CB0z77z4x.v759x5D-tA5676z6D.7Az@flex--wuhaotsh.bounces.google.com>) id 1l4U5H-00047a-3U for qemu-arm@nongnu.org; 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Tue, 26 Jan 2021 11:32:58 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:35 -0800 In-Reply-To: <20210126193237.1534208-1-wuhaotsh@google.com> Message-Id: <20210126193237.1534208-5-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 4/6] hw/arm: Add I2C device tree for Quanta GSJ From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3am4QYAgKCI8FD0t7CB0z77z4x.v759x5D-tA5676z6D.7Az@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:11 -0000 Add an I2C device tree for Quanta GSJ. We only included devices with existing QEMU implementation, including AT24 EEPROM and temperature sensors. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx_boards.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2d82f48848..1418629e06 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -19,6 +19,7 @@ #include "exec/address-spaces.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" +#include "hw/i2c/smbus_eeprom.h" #include "hw/loader.h" #include "hw/qdev-properties.h" #include "qapi/error.h" @@ -112,6 +113,21 @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc) i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); } +static void quanta_gsj_i2c_init(NPCM7xxState *soc) +{ + uint8_t *eeprom_buf0 = g_malloc0(32 * 1024); + uint8_t *eeprom_buf1 = g_malloc0(32 * 1024); + + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x48); + smbus_eeprom_init_one(npcm7xx_i2c_get_bus(soc, 9), 0x55, eeprom_buf0); + smbus_eeprom_init_one(npcm7xx_i2c_get_bus(soc, 10), 0x55, eeprom_buf1); + + /* TODO: Add addtional i2c devices. */ +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -137,6 +153,7 @@ static void quanta_gsj_init(MachineState *machine) npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", drive_get(IF_MTD, 0, 0)); + quanta_gsj_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5U-0004c6-Cy for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3aW4QYAgKCI4ECzs6BAzy66y3w.u648w4C-s94565y5C.69y@flex--wuhaotsh.bounces.google.com>) id 1l4U5O-0004YT-Bg for qemu-arm@nongnu.org; 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Tue, 26 Jan 2021 11:32:57 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:34 -0800 In-Reply-To: <20210126193237.1534208-1-wuhaotsh@google.com> Message-Id: <20210126193237.1534208-4-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 3/6] hw/arm: Add I2C device tree for NPCM750 eval board From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3aW4QYAgKCI4ECzs6BAzy66y3w.u648w4C-s94565y5C.69y@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:11 -0000 Add an I2C device tree for NPCM750 evaluation board. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx_boards.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 3fdd5cab01..2d82f48848 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -98,6 +98,20 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, return NPCM7XX(obj); } +static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) +{ + g_assert(num < ARRAY_SIZE(soc->smbus)); + return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); +} + +static void npcm750_evb_i2c_init(NPCM7xxState *soc) +{ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -108,6 +122,7 @@ static void npcm750_evb_init(MachineState *machine) npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); + npcm750_evb_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5Y-0004j7-H8 for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Z24QYAgKCIwCAxq498xw44w1u.s426u2A-q72343w3A.47w@flex--wuhaotsh.bounces.google.com>) id 1l4U5S-0004ag-Ma for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:14 -0500 Received: from mail-qt1-x849.google.com ([2607:f8b0:4864:20::849]:38001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Z24QYAgKCIwCAxq498xw44w1u.s426u2A-q72343w3A.47w@flex--wuhaotsh.bounces.google.com>) id 1l4U5D-00046K-4W for qemu-arm@nongnu.org; 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Tue, 26 Jan 2021 11:32:55 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:33 -0800 In-Reply-To: <20210126193237.1534208-1-wuhaotsh@google.com> Message-Id: <20210126193237.1534208-3-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 2/6] hw/i2c: Implement NPCM7XX SMBus Module Single Mode From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::849; envelope-from=3Z24QYAgKCIwCAxq498xw44w1u.s426u2A-q72343w3A.47w@flex--wuhaotsh.bounces.google.com; helo=mail-qt1-x849.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:15 -0000 This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 68 ++- hw/i2c/meson.build | 1 + hw/i2c/npcm7xx_smbus.c | 766 +++++++++++++++++++++++++++++++++ hw/i2c/trace-events | 11 + include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 88 ++++ 7 files changed, 921 insertions(+), 17 deletions(-) create mode 100644 hw/i2c/npcm7xx_smbus.c create mode 100644 include/hw/i2c/npcm7xx_smbus.h diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index a1786342e2..34fc799b2d 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -43,6 +43,7 @@ Supported devices * GPIO controller * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) + * SMBus controller (SMBF) Missing devices --------------- @@ -58,7 +59,6 @@ Missing devices * Ethernet controllers (GMAC and EMC) * USB device (USBD) - * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d1fe9bd1df..8f596ffd69 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -104,6 +104,22 @@ enum NPCM7xxInterrupt { NPCM7XX_OHCI_IRQ = 62, NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ + NPCM7XX_SMBUS0_IRQ = 64, + NPCM7XX_SMBUS1_IRQ, + NPCM7XX_SMBUS2_IRQ, + NPCM7XX_SMBUS3_IRQ, + NPCM7XX_SMBUS4_IRQ, + NPCM7XX_SMBUS5_IRQ, + NPCM7XX_SMBUS6_IRQ, + NPCM7XX_SMBUS7_IRQ, + NPCM7XX_SMBUS8_IRQ, + NPCM7XX_SMBUS9_IRQ, + NPCM7XX_SMBUS10_IRQ, + NPCM7XX_SMBUS11_IRQ, + NPCM7XX_SMBUS12_IRQ, + NPCM7XX_SMBUS13_IRQ, + NPCM7XX_SMBUS14_IRQ, + NPCM7XX_SMBUS15_IRQ, NPCM7XX_GPIO0_IRQ = 116, NPCM7XX_GPIO1_IRQ, NPCM7XX_GPIO2_IRQ, @@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] = { 0xf0104000, }; +/* Direct memory-mapped access to each SMBus Module. */ +static const hwaddr npcm7xx_smbus_addr[] = { + 0xf0080000, + 0xf0081000, + 0xf0082000, + 0xf0083000, + 0xf0084000, + 0xf0085000, + 0xf0086000, + 0xf0087000, + 0xf0088000, + 0xf0089000, + 0xf008a000, + 0xf008b000, + 0xf008c000, + 0xf008d000, + 0xf008e000, + 0xf008f000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -353,6 +389,11 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); } + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { + object_initialize_child(obj, "smbus[*]", &s->smbus[i], + TYPE_NPCM7XX_SMBUS); + } + object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); @@ -509,6 +550,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); } + /* SMBus modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { + Object *obj = OBJECT(&s->smbus[i]); + + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); + } + /* USB Host */ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, &error_abort); @@ -576,22 +628,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build index 3a511539ad..cdcd694a7f 100644 --- a/hw/i2c/meson.build +++ b/hw/i2c/meson.build @@ -9,6 +9,7 @@ i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c')) i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) +i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c')) i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c')) i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c')) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c new file mode 100644 index 0000000000..e8a8fdbaff --- /dev/null +++ b/hw/i2c/npcm7xx_smbus.c @@ -0,0 +1,766 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/i2c/npcm7xx_smbus.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/guest-random.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#include "trace.h" + +#define NPCM7XX_SMBUS_VERSION 1 +#define NPCM7XX_SMBUS_FIFO_EN 0 + +enum NPCM7xxSMBusCommonRegister { + NPCM7XX_SMB_SDA = 0x0, + NPCM7XX_SMB_ST = 0x2, + NPCM7XX_SMB_CST = 0x4, + NPCM7XX_SMB_CTL1 = 0x6, + NPCM7XX_SMB_ADDR1 = 0x8, + NPCM7XX_SMB_CTL2 = 0xa, + NPCM7XX_SMB_ADDR2 = 0xc, + NPCM7XX_SMB_CTL3 = 0xe, + NPCM7XX_SMB_CST2 = 0x18, + NPCM7XX_SMB_CST3 = 0x19, + NPCM7XX_SMB_VER = 0x1f, +}; + +enum NPCM7xxSMBusBank0Register { + NPCM7XX_SMB_ADDR3 = 0x10, + NPCM7XX_SMB_ADDR7 = 0x11, + NPCM7XX_SMB_ADDR4 = 0x12, + NPCM7XX_SMB_ADDR8 = 0x13, + NPCM7XX_SMB_ADDR5 = 0x14, + NPCM7XX_SMB_ADDR9 = 0x15, + NPCM7XX_SMB_ADDR6 = 0x16, + NPCM7XX_SMB_ADDR10 = 0x17, + NPCM7XX_SMB_CTL4 = 0x1a, + NPCM7XX_SMB_CTL5 = 0x1b, + NPCM7XX_SMB_SCLLT = 0x1c, + NPCM7XX_SMB_FIF_CTL = 0x1d, + NPCM7XX_SMB_SCLHT = 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + NPCM7XX_SMB_FIF_CTS = 0x10, + NPCM7XX_SMB_FAIR_PER = 0x11, + NPCM7XX_SMB_TXF_CTL = 0x12, + NPCM7XX_SMB_T_OUT = 0x14, + NPCM7XX_SMB_TXF_STS = 0x1a, + NPCM7XX_SMB_RXF_STS = 0x1c, + NPCM7XX_SMB_RXF_CTL = 0x1e, +}; + +/* ST fields */ +#define NPCM7XX_SMBST_STP BIT(7) +#define NPCM7XX_SMBST_SDAST BIT(6) +#define NPCM7XX_SMBST_BER BIT(5) +#define NPCM7XX_SMBST_NEGACK BIT(4) +#define NPCM7XX_SMBST_STASTR BIT(3) +#define NPCM7XX_SMBST_NMATCH BIT(2) +#define NPCM7XX_SMBST_MODE BIT(1) +#define NPCM7XX_SMBST_XMIT BIT(0) + +/* CST fields */ +#define NPCM7XX_SMBCST_ARPMATCH BIT(7) +#define NPCM7XX_SMBCST_MATCHAF BIT(6) +#define NPCM7XX_SMBCST_TGSCL BIT(5) +#define NPCM7XX_SMBCST_TSDA BIT(4) +#define NPCM7XX_SMBCST_GCMATCH BIT(3) +#define NPCM7XX_SMBCST_MATCH BIT(2) +#define NPCM7XX_SMBCST_BB BIT(1) +#define NPCM7XX_SMBCST_BUSY BIT(0) + +/* CST2 fields */ +#define NPCM7XX_SMBCST2_INTSTS BIT(7) +#define NPCM7XX_SMBCST2_MATCH7F BIT(6) +#define NPCM7XX_SMBCST2_MATCH6F BIT(5) +#define NPCM7XX_SMBCST2_MATCH5F BIT(4) +#define NPCM7XX_SMBCST2_MATCH4F BIT(3) +#define NPCM7XX_SMBCST2_MATCH3F BIT(2) +#define NPCM7XX_SMBCST2_MATCH2F BIT(1) +#define NPCM7XX_SMBCST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define NPCM7XX_SMBCST3_EO_BUSY BIT(7) +#define NPCM7XX_SMBCST3_MATCH10F BIT(2) +#define NPCM7XX_SMBCST3_MATCH9F BIT(1) +#define NPCM7XX_SMBCST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define NPCM7XX_SMBCTL1_STASTRE BIT(7) +#define NPCM7XX_SMBCTL1_NMINTE BIT(6) +#define NPCM7XX_SMBCTL1_GCMEN BIT(5) +#define NPCM7XX_SMBCTL1_ACK BIT(4) +#define NPCM7XX_SMBCTL1_EOBINTE BIT(3) +#define NPCM7XX_SMBCTL1_INTEN BIT(2) +#define NPCM7XX_SMBCTL1_STOP BIT(1) +#define NPCM7XX_SMBCTL1_START BIT(0) + +/* CTL2 fields */ +#define NPCM7XX_SMBCTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define NPCM7XX_SMBCTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define NPCM7XX_SMBCTL3_SCL_LVL BIT(7) +#define NPCM7XX_SMBCTL3_SDA_LVL BIT(6) +#define NPCM7XX_SMBCTL3_BNK_SEL BIT(5) +#define NPCM7XX_SMBCTL3_400K_MODE BIT(4) +#define NPCM7XX_SMBCTL3_IDL_START BIT(3) +#define NPCM7XX_SMBCTL3_ARPMEN BIT(2) +#define NPCM7XX_SMBCTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define NPCM7XX_ADDR_EN BIT(7) +#define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) + +#define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) +#define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) + +#define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) + +/* Reset values */ +#define NPCM7XX_SMB_ST_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST_INIT_VAL 0x10 +#define NPCM7XX_SMB_CST2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST3_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL1_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL3_INIT_VAL 0xc0 +#define NPCM7XX_SMB_CTL4_INIT_VAL 0x07 +#define NPCM7XX_SMB_CTL5_INIT_VAL 0x00 +#define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 + +static uint8_t npcm7xx_smbus_get_version(void) +{ + return NPCM7XX_SMBUS_FIFO_EN << 7 | NPCM7XX_SMBUS_VERSION; +} + +static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) +{ + int level; + + if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { + level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && + s->st & NPCM7XX_SMBST_NMATCH) || + (s->st & NPCM7XX_SMBST_BER) || + (s->st & NPCM7XX_SMBST_NEGACK) || + (s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && + s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + + if (level) { + s->cst2 |= NPCM7XX_SMBCST2_INTSTS; + } else { + s->cst2 &= ~NPCM7XX_SMBCST2_INTSTS; + } + qemu_set_irq(s->irq, level); + } +} + +static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) +{ + s->st &= ~NPCM7XX_SMBST_SDAST; + s->st |= NPCM7XX_SMBST_NEGACK; + s->status = NPCM7XX_SMBUS_STATUS_NEGACK; +} + +static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) +{ + int rv = i2c_send(s->bus, value); + + if (rv) { + npcm7xx_smbus_nack(s); + } else { + s->st |= NPCM7XX_SMBST_SDAST; + } + trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) +{ + s->sda = i2c_recv(s->bus); + s->st |= NPCM7XX_SMBST_SDAST; + if (s->st & NPCM7XX_SMBCTL1_ACK) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->st &= NPCM7XX_SMBCTL1_ACK; + } + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), s->sda); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) +{ + /* + * We can start the bus if one of these is true: + * 1. The bus is idle (so we can request it) + * 2. We are the occupier (it's a repeated start condition.) + */ + int available = !i2c_bus_busy(s->bus) || + s->status != NPCM7XX_SMBUS_STATUS_IDLE; + + if (available) { + s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; + s->cst |= NPCM7XX_SMBCST_BUSY; + } else { + s->st &= ~NPCM7XX_SMBST_MODE; + s->cst &= ~NPCM7XX_SMBCST_BUSY; + s->st |= NPCM7XX_SMBST_BER; + } + + trace_npcm7xx_smbus_start(DEVICE(s)->canonical_path, available); + s->cst |= NPCM7XX_SMBCST_BB; + s->status = NPCM7XX_SMBUS_STATUS_IDLE; + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) +{ + int recv; + int rv; + + recv = value & BIT(0); + rv = i2c_start_transfer(s->bus, value >> 1, recv); + trace_npcm7xx_smbus_send_address(DEVICE(s)->canonical_path, + value >> 1, recv, !rv); + if (rv) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: requesting i2c bus for 0x%02x failed: %d\n", + DEVICE(s)->canonical_path, value, rv); + /* Failed to start transfer. NACK to reject.*/ + if (recv) { + s->st &= ~NPCM7XX_SMBST_XMIT; + } else { + s->st |= NPCM7XX_SMBST_XMIT; + } + npcm7xx_smbus_nack(s); + npcm7xx_smbus_update_irq(s); + return; + } + + s->st &= ~NPCM7XX_SMBST_NEGACK; + if (recv) { + s->status = NPCM7XX_SMBUS_STATUS_RECEIVING; + s->st &= ~NPCM7XX_SMBST_XMIT; + } else { + s->status = NPCM7XX_SMBUS_STATUS_SENDING; + s->st |= NPCM7XX_SMBST_XMIT; + } + + if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { + s->st |= NPCM7XX_SMBST_STASTR; + if (!recv) { + s->st |= NPCM7XX_SMBST_SDAST; + } + } else if (recv) { + npcm7xx_smbus_recv_byte(s); + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_execute_stop(NPCM7xxSMBusState *s) +{ + i2c_end_transfer(s->bus); + s->st = 0; + s->cst = 0; + s->status = NPCM7XX_SMBUS_STATUS_IDLE; + s->cst3 |= NPCM7XX_SMBCST3_EO_BUSY; + trace_npcm7xx_smbus_stop(DEVICE(s)->canonical_path); + npcm7xx_smbus_update_irq(s); +} + + +static void npcm7xx_smbus_stop(NPCM7xxSMBusState *s) +{ + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_RECEIVING: + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE; + break; + + case NPCM7XX_SMBUS_STATUS_NEGACK: + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK; + break; + + default: + npcm7xx_smbus_execute_stop(s); + break; + } + } +} + +static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) +{ + uint8_t value = s->sda; + + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + npcm7xx_smbus_execute_stop(s); + break; + + case NPCM7XX_SMBUS_STATUS_RECEIVING: + npcm7xx_smbus_recv_byte(s); + break; + + default: + /* Do nothing */ + break; + } + + return value; +} + +static void npcm7xx_smbus_write_sda(NPCM7xxSMBusState *s, uint8_t value) +{ + s->sda = value; + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_IDLE: + npcm7xx_smbus_send_address(s, value); + break; + case NPCM7XX_SMBUS_STATUS_SENDING: + npcm7xx_smbus_send_byte(s, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to SDA in invalid status %d: %u\n", + DEVICE(s)->canonical_path, s->status, value); + break; + } + } +} + +static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) +{ + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STP); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_BER); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STASTR); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_NMATCH); + + if (value & NPCM7XX_SMBST_NEGACK) { + s->st &= ~NPCM7XX_SMBST_NEGACK; + if (s->status == NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK) { + npcm7xx_smbus_execute_stop(s); + } + } + + if (value & NPCM7XX_SMBST_STASTR && + s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_byte(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_value = s->cst; + + s->cst = WRITE_ONE_CLEAR(new_value, value, NPCM7XX_SMBCST_BB); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst3(NPCM7xxSMBusState *s, uint8_t value) +{ + s->cst3 = WRITE_ONE_CLEAR(s->cst3, value, NPCM7XX_SMBCST3_EO_BUSY); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl1(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, + NPCM7XX_SMBCTL1_START | NPCM7XX_SMBCTL1_STOP | NPCM7XX_SMBCTL1_ACK); + + if (value & NPCM7XX_SMBCTL1_START) { + npcm7xx_smbus_start(s); + } + + if (value & NPCM7XX_SMBCTL1_STOP) { + npcm7xx_smbus_stop(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl2 = value; + + if (!NPCM7XX_SMBUS_ENABLED(s)) { + /* Disable this SMBus module. */ + s->ctl1 = 0; + s->st = 0; + s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); + s->cst = 0; + } +} + +static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t old_ctl3 = s->ctl3; + + /* Write to SDA and SCL bits are ignored. */ + s->ctl3 = KEEP_OLD_BIT(old_ctl3, value, + NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_LVL); +} + +static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCM7xxSMBusState *s = opaque; + uint64_t value = 0; + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + switch (offset) { + case NPCM7XX_SMB_SDA: + value = npcm7xx_smbus_read_sda(s); + break; + + case NPCM7XX_SMB_ST: + value = s->st; + break; + + case NPCM7XX_SMB_CST: + value = s->cst; + break; + + case NPCM7XX_SMB_CTL1: + value = s->ctl1; + break; + + case NPCM7XX_SMB_ADDR1: + value = s->addr[0]; + break; + + case NPCM7XX_SMB_CTL2: + value = s->ctl2; + break; + + case NPCM7XX_SMB_ADDR2: + value = s->addr[1]; + break; + + case NPCM7XX_SMB_CTL3: + value = s->ctl3; + break; + + case NPCM7XX_SMB_CST2: + value = s->cst2; + break; + + case NPCM7XX_SMB_CST3: + value = s->cst3; + break; + + case NPCM7XX_SMB_VER: + value = npcm7xx_smbus_get_version(); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + value = s->addr[2]; + break; + + case NPCM7XX_SMB_ADDR7: + value = s->addr[6]; + break; + + case NPCM7XX_SMB_ADDR4: + value = s->addr[3]; + break; + + case NPCM7XX_SMB_ADDR8: + value = s->addr[7]; + break; + + case NPCM7XX_SMB_ADDR5: + value = s->addr[4]; + break; + + case NPCM7XX_SMB_ADDR9: + value = s->addr[8]; + break; + + case NPCM7XX_SMB_ADDR6: + value = s->addr[5]; + break; + + case NPCM7XX_SMB_ADDR10: + value = s->addr[9]; + break; + + case NPCM7XX_SMB_CTL4: + value = s->ctl4; + break; + + case NPCM7XX_SMB_CTL5: + value = s->ctl5; + break; + + case NPCM7XX_SMB_SCLLT: + value = s->scllt; + break; + + case NPCM7XX_SMB_SCLHT: + value = s->sclht; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } + + trace_npcm7xx_smbus_read(DEVICE(s)->canonical_path, offset, value, size); + + return value; +} + +static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + NPCM7xxSMBusState *s = opaque; + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + trace_npcm7xx_smbus_write(DEVICE(s)->canonical_path, offset, value, size); + + switch (offset) { + case NPCM7XX_SMB_SDA: + npcm7xx_smbus_write_sda(s, value); + break; + + case NPCM7XX_SMB_ST: + npcm7xx_smbus_write_st(s, value); + break; + + case NPCM7XX_SMB_CST: + npcm7xx_smbus_write_cst(s, value); + break; + + case NPCM7XX_SMB_CTL1: + npcm7xx_smbus_write_ctl1(s, value); + break; + + case NPCM7XX_SMB_ADDR1: + s->addr[0] = value; + break; + + case NPCM7XX_SMB_CTL2: + npcm7xx_smbus_write_ctl2(s, value); + break; + + case NPCM7XX_SMB_ADDR2: + s->addr[1] = value; + break; + + case NPCM7XX_SMB_CTL3: + npcm7xx_smbus_write_ctl3(s, value); + break; + + case NPCM7XX_SMB_CST2: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + case NPCM7XX_SMB_CST3: + npcm7xx_smbus_write_cst3(s, value); + break; + + case NPCM7XX_SMB_VER: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + s->addr[2] = value; + break; + + case NPCM7XX_SMB_ADDR7: + s->addr[6] = value; + break; + + case NPCM7XX_SMB_ADDR4: + s->addr[3] = value; + break; + + case NPCM7XX_SMB_ADDR8: + s->addr[7] = value; + break; + + case NPCM7XX_SMB_ADDR5: + s->addr[4] = value; + break; + + case NPCM7XX_SMB_ADDR9: + s->addr[8] = value; + break; + + case NPCM7XX_SMB_ADDR6: + s->addr[5] = value; + break; + + case NPCM7XX_SMB_ADDR10: + s->addr[9] = value; + break; + + case NPCM7XX_SMB_CTL4: + s->ctl4 = value; + break; + + case NPCM7XX_SMB_CTL5: + s->ctl5 = value; + break; + + case NPCM7XX_SMB_SCLLT: + s->scllt = value; + break; + + case NPCM7XX_SMB_SCLHT: + s->sclht = value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } +} + +static const MemoryRegionOps npcm7xx_smbus_ops = { + .read = npcm7xx_smbus_read, + .write = npcm7xx_smbus_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 1, + .unaligned = false, + }, +}; + +static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + + s->st = NPCM7XX_SMB_ST_INIT_VAL; + s->cst = NPCM7XX_SMB_CST_INIT_VAL; + s->cst2 = NPCM7XX_SMB_CST2_INIT_VAL; + s->cst3 = NPCM7XX_SMB_CST3_INIT_VAL; + s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; + s->ctl2 = NPCM7XX_SMB_CTL2_INIT_VAL; + s->ctl3 = NPCM7XX_SMB_CTL3_INIT_VAL; + s->ctl4 = NPCM7XX_SMB_CTL4_INIT_VAL; + s->ctl5 = NPCM7XX_SMB_CTL5_INIT_VAL; + + for (int i = 0; i < NPCM7XX_SMBUS_NR_ADDRS; ++i) { + s->addr[i] = NPCM7XX_SMB_ADDR_INIT_VAL; + } + s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; + s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; + + s->status = NPCM7XX_SMBUS_STATUS_IDLE; +} + +static void npcm7xx_smbus_hold_reset(Object *obj) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_smbus_init(Object *obj) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + sysbus_init_irq(sbd, &s->irq); + memory_region_init_io(&s->iomem, obj, &npcm7xx_smbus_ops, s, + "regs", 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + + s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); + s->status = NPCM7XX_SMBUS_STATUS_IDLE; +} + +static const VMStateDescription vmstate_npcm7xx_smbus = { + .name = "npcm7xx-smbus", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_smbus_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx System Management Bus"; + dc->vmsd = &vmstate_npcm7xx_smbus; + rc->phases.enter = npcm7xx_smbus_enter_reset; + rc->phases.hold = npcm7xx_smbus_hold_reset; +} + +static const TypeInfo npcm7xx_smbus_types[] = { + { + .name = TYPE_NPCM7XX_SMBUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxSMBusState), + .class_init = npcm7xx_smbus_class_init, + .instance_init = npcm7xx_smbus_init, + }, +}; +DEFINE_TYPES(npcm7xx_smbus_types); diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 08db8fa689..c3bb70ad04 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -14,3 +14,14 @@ aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t val aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x" aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x" + +# npcm7xx_smbus.c + +npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_start(const char *id, int success) "%s starting, success: %d" +npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int success) "%s sending address: 0x%02x, recv: %d, success: %d" +npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byte: 0x%02x, success: %d" +npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x" +npcm7xx_smbus_stop(const char *id) "%s stopping" +npcm7xx_smbus_nack(const char *id) "%s nacking" diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f6227aa8aa..cea1bd1f62 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/adc/npcm7xx_adc.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" +#include "hw/i2c/npcm7xx_smbus.h" #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" @@ -85,6 +86,7 @@ typedef struct NPCM7xxState { NPCM7xxMCState mc; NPCM7xxRNGState rng; NPCM7xxGPIOState gpio[8]; + NPCM7xxSMBusState smbus[16]; EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h new file mode 100644 index 0000000000..b9761a6993 --- /dev/null +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -0,0 +1,88 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_SMBUS_H +#define NPCM7XX_SMBUS_H + +#include "exec/memory.h" +#include "hw/i2c/i2c.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +/* + * Number of addresses this module contains. Do not change this without + * incrementing the version_id in the vmstate. + */ +#define NPCM7XX_SMBUS_NR_ADDRS 10 + +typedef enum NPCM7xxSMBusStatus { + NPCM7XX_SMBUS_STATUS_IDLE, + NPCM7XX_SMBUS_STATUS_SENDING, + NPCM7XX_SMBUS_STATUS_RECEIVING, + NPCM7XX_SMBUS_STATUS_NEGACK, + NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, + NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, +} NPCM7xxSMBusStatus; + +/* + * struct NPCM7xxSMBusState - System Management Bus device state. + * @bus: The underlying I2C Bus. + * @irq: GIC interrupt line to fire on events (if enabled). + * @sda: The serial data register. + * @st: The status register. + * @cst: The control status register. + * @cst2: The control status register 2. + * @cst3: The control status register 3. + * @ctl1: The control register 1. + * @ctl2: The control register 2. + * @ctl3: The control register 3. + * @ctl4: The control register 4. + * @ctl5: The control register 5. + * @addr: The SMBus module's own addresses on the I2C bus. + * @scllt: The SCL low time register. + * @sclht: The SCL high time register. + * @status: The current status of the SMBus. + */ +typedef struct NPCM7xxSMBusState { + SysBusDevice parent; + + MemoryRegion iomem; + + I2CBus *bus; + qemu_irq irq; + + uint8_t sda; + uint8_t st; + uint8_t cst; + uint8_t cst2; + uint8_t cst3; + uint8_t ctl1; + uint8_t ctl2; + uint8_t ctl3; + uint8_t ctl4; + uint8_t ctl5; + uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; + + uint8_t scllt; + uint8_t sclht; + + NPCM7xxSMBusStatus status; +} NPCM7xxSMBusState; + +#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" +#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ + TYPE_NPCM7XX_SMBUS) + +#endif /* NPCM7XX_SMBUS_H */ -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5Y-0004jh-OV for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3bW4QYAgKCJIIG3wAFE32AA270.yA8C08G-wD89A929G.AD2@flex--wuhaotsh.bounces.google.com>) id 1l4U5T-0004bi-AT for qemu-arm@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::84a; envelope-from=3bW4QYAgKCJIIG3wAFE32AA270.yA8C08G-wD89A929G.AD2@flex--wuhaotsh.bounces.google.com; helo=mail-qt1-x84a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:16 -0000 This patch implements the FIFO mode of the SMBus module. In FIFO, the user transmits or receives at most 16 bytes at a time. The FIFO mode allows the module to transmit large amount of data faster than single byte mode. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/i2c/npcm7xx_smbus.c | 331 +++++++++++++++++++++++++++++-- hw/i2c/trace-events | 1 + include/hw/i2c/npcm7xx_smbus.h | 25 +++ tests/qtest/npcm7xx_smbus-test.c | 149 +++++++++++++- 4 files changed, 490 insertions(+), 16 deletions(-) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index e8a8fdbaff..19a9cdb179 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -27,7 +27,7 @@ #include "trace.h" #define NPCM7XX_SMBUS_VERSION 1 -#define NPCM7XX_SMBUS_FIFO_EN 0 +#define NPCM7XX_SMBUS_FIFO_EN 1 enum NPCM7xxSMBusCommonRegister { NPCM7XX_SMB_SDA = 0x0, @@ -132,10 +132,41 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_ADDR_EN BIT(7) #define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) +/* FIFO Mode Register Fields */ +/* FIF_CTL fields */ +#define NPCM7XX_SMBFIF_CTL_FIFO_EN BIT(4) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY_IE BIT(2) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY BIT(1) +#define NPCM7XX_SMBFIF_CTL_FAIR_BUSY BIT(0) +/* FIF_CTS fields */ +#define NPCM7XX_SMBFIF_CTS_STR BIT(7) +#define NPCM7XX_SMBFIF_CTS_CLR_FIFO BIT(6) +#define NPCM7XX_SMBFIF_CTS_RFTE_IE BIT(3) +#define NPCM7XX_SMBFIF_CTS_RXF_TXE BIT(1) +/* TXF_CTL fields */ +#define NPCM7XX_SMBTXF_CTL_THR_TXIE BIT(6) +#define NPCM7XX_SMBTXF_CTL_TX_THR(rv) extract8((rv), 0, 5) +/* T_OUT fields */ +#define NPCM7XX_SMBT_OUT_ST BIT(7) +#define NPCM7XX_SMBT_OUT_IE BIT(6) +#define NPCM7XX_SMBT_OUT_CLKDIV(rv) extract8((rv), 0, 6) +/* TXF_STS fields */ +#define NPCM7XX_SMBTXF_STS_TX_THST BIT(6) +#define NPCM7XX_SMBTXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_STS fields */ +#define NPCM7XX_SMBRXF_STS_RX_THST BIT(6) +#define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_CTL fields */ +#define NPCM7XX_SMBRXF_CTL_THR_RXIE BIT(6) +#define NPCM7XX_SMBRXF_CTL_LAST BIT(5) +#define NPCM7XX_SMBRXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + #define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) #define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) +#define NPCM7XX_SMBUS_FIFO_ENABLED(s) (NPCM7XX_SMBUS_FIFO_EN && \ + (s)->fif_ctl & NPCM7XX_SMBFIF_CTL_FIFO_EN) /* Reset values */ #define NPCM7XX_SMB_ST_INIT_VAL 0x00 @@ -150,6 +181,14 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTS_INIT_VAL 0x00 +#define NPCM7XX_SMB_FAIR_PER_INIT_VAL 0x00 +#define NPCM7XX_SMB_TXF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_T_OUT_INIT_VAL 0x3f +#define NPCM7XX_SMB_TXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_CTL_INIT_VAL 0x01 static uint8_t npcm7xx_smbus_get_version(void) { @@ -169,7 +208,13 @@ static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && s->st & NPCM7XX_SMBST_SDAST) || (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && - s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY) || + (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE && + s->rxf_sts & NPCM7XX_SMBRXF_STS_RX_THST) || + (s->txf_ctl & NPCM7XX_SMBTXF_CTL_THR_TXIE && + s->txf_sts & NPCM7XX_SMBTXF_STS_TX_THST) || + (s->fif_cts & NPCM7XX_SMBFIF_CTS_RFTE_IE && + s->fif_cts & NPCM7XX_SMBFIF_CTS_RXF_TXE)); if (level) { s->cst2 |= NPCM7XX_SMBCST2_INTSTS; @@ -187,6 +232,13 @@ static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) s->status = NPCM7XX_SMBUS_STATUS_NEGACK; } +static void npcm7xx_smbus_clear_buffer(NPCM7xxSMBusState *s) +{ + s->fif_cts &= ~NPCM7XX_SMBFIF_CTS_RXF_TXE; + s->txf_sts = 0; + s->rxf_sts = 0; +} + static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) { int rv = i2c_send(s->bus, value); @@ -195,6 +247,15 @@ static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) npcm7xx_smbus_nack(s); } else { s->st |= NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + if (NPCM7XX_SMBTXF_STS_TX_BYTES(s->txf_sts) == + NPCM7XX_SMBTXF_CTL_TX_THR(s->txf_ctl)) { + s->txf_sts = NPCM7XX_SMBTXF_STS_TX_THST; + } else { + s->txf_sts = 0; + } + } } trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); npcm7xx_smbus_update_irq(s); @@ -213,6 +274,67 @@ static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) npcm7xx_smbus_update_irq(s); } +static void npcm7xx_smbus_recv_fifo(NPCM7xxSMBusState *s) +{ + uint8_t expected_bytes = NPCM7XX_SMBRXF_CTL_RX_THR(s->rxf_ctl); + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + uint8_t pos; + + if (received_bytes == expected_bytes) { + return; + } + + while (received_bytes < expected_bytes && + received_bytes < NPCM7XX_SMBUS_FIFO_SIZE) { + pos = (s->rx_cur + received_bytes) % NPCM7XX_SMBUS_FIFO_SIZE; + s->rx_fifo[pos] = i2c_recv(s->bus); + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), + s->rx_fifo[pos]); + ++received_bytes; + } + + trace_npcm7xx_smbus_recv_fifo((DEVICE(s)->canonical_path), + received_bytes, expected_bytes); + s->rxf_sts = received_bytes; + if (unlikely(received_bytes < expected_bytes)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid rx_thr value: 0x%02x\n", + DEVICE(s)->canonical_path, expected_bytes); + return; + } + + s->rxf_sts |= NPCM7XX_SMBRXF_STS_RX_THST; + if (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_LAST) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->rxf_ctl &= ~NPCM7XX_SMBRXF_CTL_LAST; + } + if (received_bytes == NPCM7XX_SMBUS_FIFO_SIZE) { + s->st |= NPCM7XX_SMBST_SDAST; + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + } else if (!(s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE)) { + s->st |= NPCM7XX_SMBST_SDAST; + } else { + s->st &= ~NPCM7XX_SMBST_SDAST; + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) +{ + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + + if (received_bytes == 0) { + npcm7xx_smbus_recv_fifo(s); + return; + } + + s->sda = s->rx_fifo[s->rx_cur]; + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; + --s->rxf_sts; + npcm7xx_smbus_update_irq(s); +} + static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) { /* @@ -226,6 +348,9 @@ static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) if (available) { s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; s->cst |= NPCM7XX_SMBCST_BUSY; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + } } else { s->st &= ~NPCM7XX_SMBST_MODE; s->cst &= ~NPCM7XX_SMBCST_BUSY; @@ -277,7 +402,15 @@ static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) s->st |= NPCM7XX_SMBST_SDAST; } } else if (recv) { - npcm7xx_smbus_recv_byte(s); + s->st |= NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } + } else if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->st |= NPCM7XX_SMBST_SDAST; + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; } npcm7xx_smbus_update_irq(s); } @@ -320,11 +453,31 @@ static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) switch (s->status) { case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: - npcm7xx_smbus_execute_stop(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) <= 1) { + npcm7xx_smbus_execute_stop(s); + } + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) == 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read to SDA with an empty rx-fifo buffer, " + "result undefined: %u\n", + DEVICE(s)->canonical_path, s->sda); + break; + } + npcm7xx_smbus_read_byte_fifo(s); + value = s->sda; + } else { + npcm7xx_smbus_execute_stop(s); + } break; case NPCM7XX_SMBUS_STATUS_RECEIVING: - npcm7xx_smbus_recv_byte(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_read_byte_fifo(s); + value = s->sda; + } else { + npcm7xx_smbus_recv_byte(s); + } break; default: @@ -370,8 +523,12 @@ static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) } if (value & NPCM7XX_SMBST_STASTR && - s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { - npcm7xx_smbus_recv_byte(s); + s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } } npcm7xx_smbus_update_irq(s); @@ -417,6 +574,7 @@ static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) s->st = 0; s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); s->cst = 0; + npcm7xx_smbus_clear_buffer(s); } } @@ -429,6 +587,70 @@ static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_LVL); } +static void npcm7xx_smbus_write_fif_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_ctl = value; + + new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_RDY); + new_ctl = WRITE_ONE_CLEAR(new_ctl, value, NPCM7XX_SMBFIF_CTL_FAIR_RDY); + new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_BUSY); + s->fif_ctl = new_ctl; +} + +static void npcm7xx_smbus_write_fif_cts(NPCM7xxSMBusState *s, uint8_t value) +{ + s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_STR); + s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_RXF_TXE); + s->fif_cts = KEEP_OLD_BIT(value, s->fif_cts, NPCM7XX_SMBFIF_CTS_RFTE_IE); + + if (value & NPCM7XX_SMBFIF_CTS_CLR_FIFO) { + npcm7xx_smbus_clear_buffer(s); + } +} + +static void npcm7xx_smbus_write_txf_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + s->txf_ctl = value; +} + +static void npcm7xx_smbus_write_t_out(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_t_out = value; + + if ((value & NPCM7XX_SMBT_OUT_ST) || (!(s->t_out & NPCM7XX_SMBT_OUT_ST))) { + new_t_out &= ~NPCM7XX_SMBT_OUT_ST; + } else { + new_t_out |= NPCM7XX_SMBT_OUT_ST; + } + + s->t_out = new_t_out; +} + +static void npcm7xx_smbus_write_txf_sts(NPCM7xxSMBusState *s, uint8_t value) +{ + s->txf_sts = WRITE_ONE_CLEAR(s->txf_sts, value, NPCM7XX_SMBTXF_STS_TX_THST); +} + +static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t value) +{ + if (value & NPCM7XX_SMBRXF_STS_RX_THST) { + s->rxf_sts &= ~NPCM7XX_SMBRXF_STS_RX_THST; + if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_fifo(s); + } + } +} + +static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_ctl = value; + + if (!(value & NPCM7XX_SMBRXF_CTL_LAST)) { + new_ctl = KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_LAST); + } + s->rxf_ctl = new_ctl; +} + static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) { NPCM7xxSMBusState *s = opaque; @@ -484,9 +706,41 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + value = s->fif_cts; + break; + + case NPCM7XX_SMB_FAIR_PER: + value = s->fair_per; + break; + + case NPCM7XX_SMB_TXF_CTL: + value = s->txf_ctl; + break; + + case NPCM7XX_SMB_T_OUT: + value = s->t_out; + break; + + case NPCM7XX_SMB_TXF_STS: + value = s->txf_sts; + break; + + case NPCM7XX_SMB_RXF_STS: + value = s->rxf_sts; + break; + + case NPCM7XX_SMB_RXF_CTL: + value = s->rxf_ctl; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -534,6 +788,10 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) value = s->scllt; break; + case NPCM7XX_SMB_FIF_CTL: + value = s->fif_ctl; + break; + case NPCM7XX_SMB_SCLHT: value = s->sclht; break; @@ -614,9 +872,41 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + npcm7xx_smbus_write_fif_cts(s, value); + break; + + case NPCM7XX_SMB_FAIR_PER: + s->fair_per = value; + break; + + case NPCM7XX_SMB_TXF_CTL: + npcm7xx_smbus_write_txf_ctl(s, value); + break; + + case NPCM7XX_SMB_T_OUT: + npcm7xx_smbus_write_t_out(s, value); + break; + + case NPCM7XX_SMB_TXF_STS: + npcm7xx_smbus_write_txf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_STS: + npcm7xx_smbus_write_rxf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_CTL: + npcm7xx_smbus_write_rxf_ctl(s, value); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -664,6 +954,10 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, s->scllt = value; break; + case NPCM7XX_SMB_FIF_CTL: + npcm7xx_smbus_write_fif_ctl(s, value); + break; + case NPCM7XX_SMB_SCLHT: s->sclht = value; break; @@ -710,7 +1004,18 @@ static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; + s->fif_ctl = NPCM7XX_SMB_FIF_CTL_INIT_VAL; + s->fif_cts = NPCM7XX_SMB_FIF_CTS_INIT_VAL; + s->fair_per = NPCM7XX_SMB_FAIR_PER_INIT_VAL; + s->txf_ctl = NPCM7XX_SMB_TXF_CTL_INIT_VAL; + s->t_out = NPCM7XX_SMB_T_OUT_INIT_VAL; + s->txf_sts = NPCM7XX_SMB_TXF_STS_INIT_VAL; + s->rxf_sts = NPCM7XX_SMB_RXF_STS_INIT_VAL; + s->rxf_ctl = NPCM7XX_SMB_RXF_CTL_INIT_VAL; + + npcm7xx_smbus_clear_buffer(s); s->status = NPCM7XX_SMBUS_STATUS_IDLE; + s->rx_cur = 0; } static void npcm7xx_smbus_hold_reset(Object *obj) diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index c3bb70ad04..82fe6f965f 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -25,3 +25,4 @@ npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byt npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x" npcm7xx_smbus_stop(const char *id) "%s stopping" npcm7xx_smbus_nack(const char *id) "%s nacking" +npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected) "%s recv fifo: received %u, expected %u" diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index b9761a6993..7d59ee917e 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -27,6 +27,9 @@ */ #define NPCM7XX_SMBUS_NR_ADDRS 10 +/* Size of the FIFO buffer. */ +#define NPCM7XX_SMBUS_FIFO_SIZE 16 + typedef enum NPCM7xxSMBusStatus { NPCM7XX_SMBUS_STATUS_IDLE, NPCM7XX_SMBUS_STATUS_SENDING, @@ -53,6 +56,16 @@ typedef enum NPCM7xxSMBusStatus { * @addr: The SMBus module's own addresses on the I2C bus. * @scllt: The SCL low time register. * @sclht: The SCL high time register. + * @fif_ctl: The FIFO control register. + * @fif_cts: The FIFO control status register. + * @fair_per: The fair preriod register. + * @txf_ctl: The transmit FIFO control register. + * @t_out: The SMBus timeout register. + * @txf_sts: The transmit FIFO status register. + * @rxf_sts: The receive FIFO status register. + * @rxf_ctl: The receive FIFO control register. + * @rx_fifo: The FIFO buffer for receiving in FIFO mode. + * @rx_cur: The current position of rx_fifo. * @status: The current status of the SMBus. */ typedef struct NPCM7xxSMBusState { @@ -78,6 +91,18 @@ typedef struct NPCM7xxSMBusState { uint8_t scllt; uint8_t sclht; + uint8_t fif_ctl; + uint8_t fif_cts; + uint8_t fair_per; + uint8_t txf_ctl; + uint8_t t_out; + uint8_t txf_sts; + uint8_t rxf_sts; + uint8_t rxf_ctl; + + uint8_t rx_fifo[NPCM7XX_SMBUS_FIFO_SIZE]; + uint8_t rx_cur; + NPCM7xxSMBusStatus status; } NPCM7xxSMBusState; diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-test.c index 4594b107df..4f9f493872 100644 --- a/tests/qtest/npcm7xx_smbus-test.c +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -132,6 +132,44 @@ enum NPCM7xxSMBusBank1Register { #define ADDR_EN BIT(7) #define ADDR_A(rv) extract8((rv), 0, 6) +/* FIF_CTL fields */ +#define FIF_CTL_FIFO_EN BIT(4) + +/* FIF_CTS fields */ +#define FIF_CTS_CLR_FIFO BIT(6) +#define FIF_CTS_RFTE_IE BIT(3) +#define FIF_CTS_RXF_TXE BIT(1) + +/* TXF_CTL fields */ +#define TXF_CTL_THR_TXIE BIT(6) +#define TXF_CTL_TX_THR(rv) extract8((rv), 0, 5) + +/* TXF_STS fields */ +#define TXF_STS_TX_THST BIT(6) +#define TXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) + +/* RXF_CTL fields */ +#define RXF_CTL_THR_RXIE BIT(6) +#define RXF_CTL_LAST BIT(5) +#define RXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + +/* RXF_STS fields */ +#define RXF_STS_RX_THST BIT(6) +#define RXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) + + +static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) +{ + uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3); + + if (bank) { + ctl3 |= CTL3_BNK_SEL; + } else { + ctl3 &= ~CTL3_BNK_SEL; + } + + qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); +} static void check_running(QTestState *qts, uint64_t base_addr) { @@ -203,10 +241,33 @@ static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) qtest_writeb(qts, base_addr + OFFSET_SDA, byte); } +static bool check_recv(QTestState *qts, uint64_t base_addr) +{ + uint8_t st, fif_ctl, rxf_ctl, rxf_sts; + bool fifo; + + st = qtest_readb(qts, base_addr + OFFSET_ST); + choose_bank(qts, base_addr, 0); + fif_ctl = qtest_readb(qts, base_addr + OFFSET_FIF_CTL); + fifo = fif_ctl & FIF_CTL_FIFO_EN; + if (!fifo) { + return st == (ST_MODE | ST_SDAST); + } + + choose_bank(qts, base_addr, 1); + rxf_ctl = qtest_readb(qts, base_addr + OFFSET_RXF_CTL); + rxf_sts = qtest_readb(qts, base_addr + OFFSET_RXF_STS); + + if ((rxf_ctl & RXF_CTL_THR_RXIE) && RXF_STS_RX_BYTES(rxf_sts) < 16) { + return st == ST_MODE; + } else { + return st == (ST_MODE | ST_SDAST); + } +} + static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) { - g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, - ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); return qtest_readb(qts, base_addr + OFFSET_SDA); } @@ -229,7 +290,7 @@ static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); st = qtest_readb(qts, base_addr + OFFSET_ST); if (recv) { - g_assert_cmphex(st, ==, ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); } else { g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST); } @@ -251,6 +312,29 @@ static void send_nack(QTestState *qts, uint64_t base_addr) qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); } +static void start_fifo_mode(QTestState *qts, uint64_t base_addr) +{ + choose_bank(qts, base_addr, 0); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTL, FIF_CTL_FIFO_EN); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTL) & + FIF_CTL_FIFO_EN); + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, + FIF_CTS_CLR_FIFO | FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_FIF_CTS), ==, + FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), ==, 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), ==, 0); +} + +static void start_recv_fifo(QTestState *qts, uint64_t base_addr, uint8_t bytes) +{ + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0); + qtest_writeb(qts, base_addr + OFFSET_RXF_CTL, + RXF_CTL_THR_RXIE | RXF_CTL_LAST | bytes); +} + /* Check the SMBus's status is set correctly when disabled. */ static void test_disable_bus(gconstpointer data) { @@ -324,6 +408,64 @@ static void test_single_mode(gconstpointer data) qtest_quit(qts); } +/* Check the SMBus can send and receive bytes in FIFO mode. */ +static void test_fifo_mode(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + uint8_t value = 0x60; + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + start_fifo_mode(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + + /* Sending */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + choose_bank(qts, base_addr, 1); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, TXF_CTL_THR_TXIE); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_TXF_STS) & + TXF_STS_TX_THST); + g_assert_cmpuint(TXF_STS_TX_BYTES( + qtest_readb(qts, base_addr + OFFSET_TXF_STS)), ==, 0); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_fifo_mode(qts, base_addr); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, FIF_CTS_RXF_TXE); + start_recv_fifo(qts, base_addr, 1); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_RXF_STS) & + RXF_STS_RX_THST); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 1); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), ==, value); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 0); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + static void smbus_add_test(const char *name, int index, GTestDataFunc fn) { g_autofree char *full_name = g_strdup_printf( @@ -346,6 +488,7 @@ int main(int argc, char **argv) for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) { add_test(single_mode, evb_bus_list[i]); + add_test(fifo_mode, evb_bus_list[i]); } return g_test_run(); -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 14:33:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4U5Z-0004lh-IW for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 14:33:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3bG4QYAgKCJEHF2v9ED219916z.x97Bz7F-vC789818F.9C1@flex--wuhaotsh.bounces.google.com>) id 1l4U5T-0004bl-As for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:16 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]:56726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3bG4QYAgKCJEHF2v9ED219916z.x97Bz7F-vC789818F.9C1@flex--wuhaotsh.bounces.google.com>) id 1l4U5H-00048X-Al for qemu-arm@nongnu.org; Tue, 26 Jan 2021 14:33:14 -0500 Received: by mail-pl1-x649.google.com with SMTP id n4so5887538plx.23 for ; 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Tue, 26 Jan 2021 11:33:00 -0800 (PST) Date: Tue, 26 Jan 2021 11:32:36 -0800 In-Reply-To: <20210126193237.1534208-1-wuhaotsh@google.com> Message-Id: <20210126193237.1534208-6-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH 5/6] hw/i2c: Add a QTest for NPCM7XX SMBus Device From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3bG4QYAgKCJEHF2v9ED219916z.x97Bz7F-vC789818F.9C1@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 19:33:16 -0000 This patch adds a QTest for NPCM7XX SMBus's single byte mode. It sends a byte to a device in the evaluation board, and verify the retrieved value is equivalent to the sent value. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_smbus-test.c | 352 +++++++++++++++++++++++++++++++ 2 files changed, 353 insertions(+) create mode 100644 tests/qtest/npcm7xx_smbus-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8..aa62d59817 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -138,6 +138,7 @@ qtests_npcm7xx = \ 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', + 'npcm7xx_smbus-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-test.c new file mode 100644 index 0000000000..4594b107df --- /dev/null +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -0,0 +1,352 @@ +/* + * QTests for Nuvoton NPCM7xx SMBus Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/i2c.h" +#include "libqos/libqtest.h" +#include "hw/misc/tmp105_regs.h" + +#define NR_SMBUS_DEVICES 16 +#define SMBUS_ADDR(x) (0xf0080000 + 0x1000 * (x)) +#define SMBUS_IRQ(x) (64 + (x)) + +#define EVB_DEVICE_ADDR 0x48 +#define INVALID_DEVICE_ADDR 0x01 + +const int evb_bus_list[] = {0, 1, 2, 6}; + +/* Offsets */ +enum CommonRegister { + OFFSET_SDA = 0x0, + OFFSET_ST = 0x2, + OFFSET_CST = 0x4, + OFFSET_CTL1 = 0x6, + OFFSET_ADDR1 = 0x8, + OFFSET_CTL2 = 0xa, + OFFSET_ADDR2 = 0xc, + OFFSET_CTL3 = 0xe, + OFFSET_CST2 = 0x18, + OFFSET_CST3 = 0x19, +}; + +enum NPCM7xxSMBusBank0Register { + OFFSET_ADDR3 = 0x10, + OFFSET_ADDR7 = 0x11, + OFFSET_ADDR4 = 0x12, + OFFSET_ADDR8 = 0x13, + OFFSET_ADDR5 = 0x14, + OFFSET_ADDR9 = 0x15, + OFFSET_ADDR6 = 0x16, + OFFSET_ADDR10 = 0x17, + OFFSET_CTL4 = 0x1a, + OFFSET_CTL5 = 0x1b, + OFFSET_SCLLT = 0x1c, + OFFSET_FIF_CTL = 0x1d, + OFFSET_SCLHT = 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + OFFSET_FIF_CTS = 0x10, + OFFSET_FAIR_PER = 0x11, + OFFSET_TXF_CTL = 0x12, + OFFSET_T_OUT = 0x14, + OFFSET_TXF_STS = 0x1a, + OFFSET_RXF_STS = 0x1c, + OFFSET_RXF_CTL = 0x1e, +}; + +/* ST fields */ +#define ST_STP BIT(7) +#define ST_SDAST BIT(6) +#define ST_BER BIT(5) +#define ST_NEGACK BIT(4) +#define ST_STASTR BIT(3) +#define ST_NMATCH BIT(2) +#define ST_MODE BIT(1) +#define ST_XMIT BIT(0) + +/* CST fields */ +#define CST_ARPMATCH BIT(7) +#define CST_MATCHAF BIT(6) +#define CST_TGSCL BIT(5) +#define CST_TSDA BIT(4) +#define CST_GCMATCH BIT(3) +#define CST_MATCH BIT(2) +#define CST_BB BIT(1) +#define CST_BUSY BIT(0) + +/* CST2 fields */ +#define CST2_INSTTS BIT(7) +#define CST2_MATCH7F BIT(6) +#define CST2_MATCH6F BIT(5) +#define CST2_MATCH5F BIT(4) +#define CST2_MATCH4F BIT(3) +#define CST2_MATCH3F BIT(2) +#define CST2_MATCH2F BIT(1) +#define CST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define CST3_EO_BUSY BIT(7) +#define CST3_MATCH10F BIT(2) +#define CST3_MATCH9F BIT(1) +#define CST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define CTL1_STASTRE BIT(7) +#define CTL1_NMINTE BIT(6) +#define CTL1_GCMEN BIT(5) +#define CTL1_ACK BIT(4) +#define CTL1_EOBINTE BIT(3) +#define CTL1_INTEN BIT(2) +#define CTL1_STOP BIT(1) +#define CTL1_START BIT(0) + +/* CTL2 fields */ +#define CTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define CTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define CTL3_SCL_LVL BIT(7) +#define CTL3_SDA_LVL BIT(6) +#define CTL3_BNK_SEL BIT(5) +#define CTL3_400K_MODE BIT(4) +#define CTL3_IDL_START BIT(3) +#define CTL3_ARPMEN BIT(2) +#define CTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define ADDR_EN BIT(7) +#define ADDR_A(rv) extract8((rv), 0, 6) + + +static void check_running(QTestState *qts, uint64_t base_addr) +{ + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); +} + +static void check_stopped(QTestState *qts, uint64_t base_addr) +{ + uint8_t cst3; + + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); + + cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_true(cst3 & CST3_EO_BUSY); + qtest_writeb(qts, base_addr + OFFSET_CST3, cst3); + cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_false(cst3 & CST3_EO_BUSY); +} + +static void enable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 |= CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); +} + +static void disable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 &= ~CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); +} + +static void start_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1; + + ctl1 = CTL1_START | CTL1_INTEN | CTL1_STASTRE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, + CTL1_INTEN | CTL1_STASTRE | CTL1_INTEN); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_XMIT | ST_SDAST); + check_running(qts, base_addr); +} + +static void stop_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &= ~(CTL1_START | CTL1_ACK); + ctl1 |= CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + g_assert_false(ctl1 & CTL1_STOP); +} + +static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_XMIT | ST_SDAST); + qtest_writeb(qts, base_addr + OFFSET_SDA, byte); +} + +static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_SDAST); + return qtest_readb(qts, base_addr + OFFSET_SDA); +} + +static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, + bool recv, bool valid) +{ + uint8_t encoded_addr = (addr << 1) | (recv ? 1 : 0); + uint8_t st; + + qtest_writeb(qts, base_addr + OFFSET_SDA, encoded_addr); + st = qtest_readb(qts, base_addr + OFFSET_ST); + + if (valid) { + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_SDAST | ST_STASTR); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST | ST_STASTR); + } + + qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); + st = qtest_readb(qts, base_addr + OFFSET_ST); + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_SDAST); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST); + } + } else { + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_NEGACK); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_NEGACK); + } + } +} + +static void send_nack(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &= ~(CTL1_START | CTL1_STOP); + ctl1 |= CTL1_ACK | CTL1_INTEN; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); +} + +/* Check the SMBus's status is set correctly when disabled. */ +static void test_disable_bus(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + QTestState *qts = qtest_init("-machine npcm750-evb"); + + disable_bus(qts, base_addr); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST3) & CST3_EO_BUSY); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), ==, 0); + qtest_quit(qts); +} + +/* Check the SMBus returns a NACK for an invalid address. */ +static void test_invalid_addr(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + send_address(qts, base_addr, INVALID_DEVICE_ADDR, false, false); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_ST, ST_NEGACK); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_ST) & ST_NEGACK); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +/* Check the SMBus can send and receive bytes to a device in single mode. */ +static void test_single_mode(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + uint8_t value = 0x60; + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + + /* Sending */ + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + g_assert_true(qtest_get_irq(qts, irq)); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), ==, value); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +static void smbus_add_test(const char *name, int index, GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf( + "npcm7xx_smbus[%d]/%s", index, name); + qtest_add_data_func(full_name, (void *)(intptr_t)index, fn); +} +#define add_test(name, td) smbus_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + int i; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + + for (i = 0; i < NR_SMBUS_DEVICES; ++i) { + add_test(disable_bus, i); + add_test(invalid_addr, i); + } + + for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) { + add_test(single_mode, evb_bus_list[i]); + } + + return g_test_run(); +} -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Tue Jan 26 16:36:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4W0d-0006sl-HV for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 16:36:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4W0b-0006s6-Mf for qemu-arm@nongnu.org; Tue, 26 Jan 2021 16:36:21 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:29473) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4W0a-0003fG-39 for qemu-arm@nongnu.org; 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Tue, 26 Jan 2021 21:36:09 +0000 (UTC) Received: from omen.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id CA7036F978; Tue, 26 Jan 2021 21:36:02 +0000 (UTC) Date: Tue, 26 Jan 2021 14:36:02 -0700 From: Alex Williamson To: Shenming Lu Cc: Cornelia Huck , Kirti Wankhede , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , Subject: Re: [RFC PATCH v2 1/3] vfio: Move the saving of the config space to the right place in VFIO migration Message-ID: <20210126143602.0dac239f@omen.home.shazbot.org> In-Reply-To: <3f7db9e7-3c98-5022-e907-e6214815fae9@huawei.com> References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-2-lushenming@huawei.com> <20201209132947.3177f130.cohuck@redhat.com> <20201209113431.5b252e93@omen.home> <3f7db9e7-3c98-5022-e907-e6214815fae9@huawei.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.255, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 21:36:21 -0000 On Thu, 10 Dec 2020 10:21:21 +0800 Shenming Lu wrote: > On 2020/12/10 2:34, Alex Williamson wrote: > > On Wed, 9 Dec 2020 13:29:47 +0100 > > Cornelia Huck wrote: > > > >> On Wed, 9 Dec 2020 16:09:17 +0800 > >> Shenming Lu wrote: > >> > >>> On ARM64 the VFIO SET_IRQS ioctl is dependent on the VM interrupt > >>> setup, if the restoring of the VFIO PCI device config space is > >>> before the VGIC, an error might occur in the kernel. > >>> > >>> So we move the saving of the config space to the non-iterable > >>> process, so that it will be called after the VGIC according to > >>> their priorities. > >>> > >>> As for the possible dependence of the device specific migration > >>> data on it's config space, we can let the vendor driver to > >>> include any config info it needs in its own data stream. > >>> (Should we note this in the header file linux-headers/linux/vfio.h?) > >> > >> Given that the header is our primary source about how this interface > >> should act, we need to properly document expectations about what will > >> be saved/restored when there (well, in the source file in the kernel.) > >> That goes in both directions: what a userspace must implement, and what > >> a vendor driver can rely on. > > Yeah, in order to make the vendor driver and QEMU cooperate better, we might > need to document some expectations about the data section in the migration > region... > >> > >> [Related, but not a todo for you: I think we're still missing proper > >> documentation of the whole migration feature.] > > > > Yes, we never saw anything past v1 of the documentation patch. Thanks, > > > > By the way, is there anything unproper with this patch? Wish your suggestion. :-) I'm really hoping for some feedback from Kirti, I understand the NVIDIA vGPU driver to have some dependency on this. Thanks, Alex > >>> Signed-off-by: Shenming Lu > >>> --- > >>> hw/vfio/migration.c | 25 +++++++++++++++---------- > >>> 1 file changed, 15 insertions(+), 10 deletions(-) > > > > . > > > From MAILER-DAEMON Tue Jan 26 16:36:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4W0k-0006zR-Ne for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 16:36:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4W0j-0006yc-RC for qemu-arm@nongnu.org; Tue, 26 Jan 2021 16:36:29 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:31221) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4W0h-0003mJ-PC for qemu-arm@nongnu.org; Tue, 26 Jan 2021 16:36:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611696987; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t8msAROHyVbSt0cYlNfVVA//kSOL7L8UBGXBIpVNpzM=; b=YBcLAnV7awPwk84b06uYTW6+8jyZIhPefKMoztmpbXSs08HJWmDy8Ex8edvxSue3wBPttf WAcj3ZuD9PcXE03qM+hr7ZrkH1ci3xREazJSHFx8heeovFbU8N+HmgAKFiV0t2EvxRsNpa 0PgEfmWbLbQxmSbNLCX23y41MdoPzBo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-203-RBIv0YQSNM-aixkQY35WHw-1; Tue, 26 Jan 2021 16:36:23 -0500 X-MC-Unique: RBIv0YQSNM-aixkQY35WHw-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E7D661927800; Tue, 26 Jan 2021 21:36:20 +0000 (UTC) Received: from omen.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5E41960C5F; Tue, 26 Jan 2021 21:36:14 +0000 (UTC) Date: Tue, 26 Jan 2021 14:36:14 -0700 From: Alex Williamson To: Shenming Lu Cc: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , Subject: Re: [RFC PATCH v2 3/3] vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration Message-ID: <20210126143614.175e271c@omen.home.shazbot.org> In-Reply-To: <20201209080919.156-4-lushenming@huawei.com> References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-4-lushenming@huawei.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.255, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 21:36:30 -0000 On Wed, 9 Dec 2020 16:09:19 +0800 Shenming Lu wrote: > Different from the normal situation when the guest starts, we can > know the max unmasked vetctor (at the beginning) after msix_load() > in VFIO migration. So in order to avoid ineffectively disabling and s/ineffectively/inefficiently/? It's "effective" either way I think. > enabling vectors repeatedly, let's allocate all needed vectors first > and then enable these unmasked vectors one by one without disabling. > > Signed-off-by: Shenming Lu > --- > hw/pci/msix.c | 17 +++++++++++++++++ > hw/vfio/pci.c | 10 ++++++++-- > include/hw/pci/msix.h | 2 ++ > 3 files changed, 27 insertions(+), 2 deletions(-) > > diff --git a/hw/pci/msix.c b/hw/pci/msix.c > index 67e34f34d6..bf291d3ff8 100644 > --- a/hw/pci/msix.c > +++ b/hw/pci/msix.c > @@ -557,6 +557,23 @@ unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) > return dev->msix_entries_nr; > } > > +int msix_get_max_unmasked_vector(PCIDevice *dev) > +{ > + int max_unmasked_vector = -1; > + int vector; > + > + if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & > + (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { > + for (vector = 0; vector < dev->msix_entries_nr; vector++) { > + if (!msix_is_masked(dev, vector)) { > + max_unmasked_vector = vector; > + } > + } > + } > + > + return max_unmasked_vector; > +} Comments from QEMU PCI folks? > + > static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) > { > MSIMessage msg; > diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c > index 51dc373695..e755ed2514 100644 > --- a/hw/vfio/pci.c > +++ b/hw/vfio/pci.c > @@ -568,6 +568,9 @@ static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) > > static void vfio_msix_enable(VFIOPCIDevice *vdev) > { > + int max_unmasked_vector = msix_get_max_unmasked_vector(&vdev->pdev); > + unsigned int used_vector = MAX(max_unmasked_vector, 0); > + The above PCI function could also be done inline here pretty easily too: unsigned int nr, max_vec = 0; if (!msix_masked(&vdev->pdev)) for (nr = 0; nr < msix_nr_vectors_allocated(&vdev->pdev); nr++) { if (!msix_is_masked(&vdev->pdev, nr)) { max_vec = nr; } } } It's a bit cleaner than the msix utility function, imo. > vfio_disable_interrupts(vdev); > > vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); > @@ -586,9 +589,12 @@ static void vfio_msix_enable(VFIOPCIDevice *vdev) > * triggering to userspace, then immediately release the vector, leaving > * the physical device with no vectors enabled, but MSI-X enabled, just > * like the guest view. > + * If there are unmasked vectors (such as in migration) which will be > + * enabled soon, we can allocate them here to avoid ineffectively disabling > + * and enabling vectors repeatedly later. It just happens that migration triggers this usage model where the MSI-X enable bit is set with vectors unmasked in the vector table, but this is not unique to migration, guests can follow this pattern as well. Has this been tested with a variety of guests? Logically it seems correct, but always good to prove so. Thanks, Alex > */ > - vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); > - vfio_msix_vector_release(&vdev->pdev, 0); > + vfio_msix_vector_do_use(&vdev->pdev, used_vector, NULL, NULL); > + vfio_msix_vector_release(&vdev->pdev, used_vector); > > if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, > vfio_msix_vector_release, NULL)) { > diff --git a/include/hw/pci/msix.h b/include/hw/pci/msix.h > index 4c4a60c739..4bfb463fa6 100644 > --- a/include/hw/pci/msix.h > +++ b/include/hw/pci/msix.h > @@ -23,6 +23,8 @@ void msix_uninit_exclusive_bar(PCIDevice *dev); > > unsigned int msix_nr_vectors_allocated(const PCIDevice *dev); > > +int msix_get_max_unmasked_vector(PCIDevice *dev); > + > void msix_save(PCIDevice *dev, QEMUFile *f); > void msix_load(PCIDevice *dev, QEMUFile *f); > From MAILER-DAEMON Tue Jan 26 16:36:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4W0w-0007J2-GY for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 16:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4W0v-0007GQ-3N for qemu-arm@nongnu.org; Tue, 26 Jan 2021 16:36:41 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:28174) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4W0s-0003pm-Mo for qemu-arm@nongnu.org; Tue, 26 Jan 2021 16:36:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611696998; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xwKZdxfl2BD5jdE0BuNGoIuKx58HeI7MN7LvxdIxtzA=; b=D19xl7g9D0F00cNex6uROqztbxa/TkUhbwtbqQ8nEfuDOohm2DS45jtUMwW+ikV3tQ0MlW 24CI7YSe+mrFbpVCAUX5TZqQZ0gZ3yIItu6l8dovvohEkgn11vb61GJs/+zSxHWO2shMy/ Py6f64rOiYMhSWPwwm+YyNYRmWTYtyA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-472-9b3An5ctM26dwFxBUgMtIw-1; Tue, 26 Jan 2021 16:36:36 -0500 X-MC-Unique: 9b3An5ctM26dwFxBUgMtIw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 805CEA0C04; Tue, 26 Jan 2021 21:36:34 +0000 (UTC) Received: from omen.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id CED655D9DE; Tue, 26 Jan 2021 21:36:27 +0000 (UTC) Date: Tue, 26 Jan 2021 14:36:05 -0700 From: Alex Williamson To: Shenming Lu Cc: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , Subject: Re: [RFC PATCH v2 2/3] vfio: Set the priority of the VFIO VM state change handler explicitly Message-ID: <20210126143605.4f9d5b25@omen.home.shazbot.org> In-Reply-To: <20201209080919.156-3-lushenming@huawei.com> References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-3-lushenming@huawei.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.255, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 21:36:41 -0000 On Wed, 9 Dec 2020 16:09:18 +0800 Shenming Lu wrote: > In the VFIO VM state change handler, VFIO devices are transitioned > in the _SAVING state, which should keep them from sending interrupts. Is this comment accurate? It's my expectation that _SAVING has no bearing on a device generating interrupts. Interrupt generation must be allowed to continue so long as the device is _RUNNING. Thanks, Alex > Then we can save the pending states of all interrupts in the GIC VM > state change handler (on ARM). > > So we have to set the priority of the VFIO VM state change handler > explicitly (like virtio devices) to ensure it is called before the > GIC's in saving. > > Signed-off-by: Shenming Lu > Reviewed-by: Kirti Wankhede > --- > hw/vfio/migration.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c > index 3b9de1353a..97ea82b100 100644 > --- a/hw/vfio/migration.c > +++ b/hw/vfio/migration.c > @@ -862,7 +862,8 @@ static int vfio_migration_init(VFIODevice *vbasedev, > register_savevm_live(id, VMSTATE_INSTANCE_ID_ANY, 1, &savevm_vfio_handlers, > vbasedev); > > - migration->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change, > + migration->vm_state = qdev_add_vm_change_state_handler(vbasedev->dev, > + vfio_vmstate_change, > vbasedev); > migration->migration_state.notify = vfio_migration_state_notifier; > add_migration_state_change_notifier(&migration->migration_state); From MAILER-DAEMON Tue Jan 26 17:30:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4WqV-0002wu-TK for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 17:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4WqT-0002w2-Su for qemu-arm@nongnu.org; Tue, 26 Jan 2021 17:29:57 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:46067) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4WqP-0005Pg-LW for qemu-arm@nongnu.org; Tue, 26 Jan 2021 17:29:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611700192; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1OHnnppItEHa7Ul9xTQcaH0lLol0YTC2DtfRl89I/0k=; b=bE6U5wGvPrJXYkCrrTTyf/S7pxez10axdAn5hS2I32L+rPoK+AJ/A2wrc/lHhDQvqZmLep l/IeAoWeHwa8Nsh+iFehjkloGA7kmqxPfrvJa2ELd3pE4s6CI0Iszj6tkoZqZN/1sHUmPX AARQCeyqYMetNc19tGdPSbzvUIIUtQE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-371-mfIRZBBQMfCRlW_i-HMvOg-1; Tue, 26 Jan 2021 17:29:49 -0500 X-MC-Unique: mfIRZBBQMfCRlW_i-HMvOg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CB7F591220; Tue, 26 Jan 2021 22:29:47 +0000 (UTC) Received: from omen.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12EC46F927; Tue, 26 Jan 2021 22:29:40 +0000 (UTC) Date: Tue, 26 Jan 2021 15:29:39 -0700 From: Alex Williamson To: Keqian Zhu Cc: Kirti Wankhede , , , Paolo Bonzini , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= , "Stefan Hajnoczi" , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , "Dr . David Alan Gilbert" , Igor Mammedov , , Zenghui Yu , Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener Message-ID: <20210126152940.17a4cf7e@omen.home.shazbot.org> In-Reply-To: <20210111073439.20236-1-zhukeqian1@huawei.com> References: <20210111073439.20236-1-zhukeqian1@huawei.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.255, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 22:29:58 -0000 Kirti? Migration experts? Thanks, Alex On Mon, 11 Jan 2021 15:34:39 +0800 Keqian Zhu wrote: > For now the switch of vfio dirty page tracking is integrated into > the vfio_save_handler, it causes some problems [1]. > > The object of dirty tracking is guest memory, but the object of > the vfio_save_handler is device state. This mixed logic produces > unnecessary coupling and conflicts: > > 1. Coupling: Their saving granule is different (perVM vs perDevice). > vfio will enable dirty_page_tracking for each devices, actually > once is enough. > 2. Conflicts: The ram_save_setup() traverses all memory_listeners > to execute their log_start() and log_sync() hooks to get the > first round dirty bitmap, which is used by the bulk stage of > ram saving. However, it can't get dirty bitmap from vfio, as > @savevm_ram_handlers is registered before @vfio_save_handler. > > Move the switch of vfio dirty_page_tracking into vfio_memory_listener > can solve above problems. Besides, Do not require devices in SAVING > state for vfio_sync_dirty_bitmap(). > > [1] https://www.spinics.net/lists/kvm/msg229967.html > > Reported-by: Zenghui Yu > Signed-off-by: Keqian Zhu > --- > hw/vfio/common.c | 53 +++++++++++++++++++++++++++++++++++++-------- > hw/vfio/migration.c | 35 ------------------------------ > 2 files changed, 44 insertions(+), 44 deletions(-) > > diff --git a/hw/vfio/common.c b/hw/vfio/common.c > index 6ff1daa763..9128cd7ee1 100644 > --- a/hw/vfio/common.c > +++ b/hw/vfio/common.c > @@ -311,7 +311,7 @@ bool vfio_mig_active(void) > return true; > } > > -static bool vfio_devices_all_saving(VFIOContainer *container) > +static bool vfio_devices_all_dirty_tracking(VFIOContainer *container) > { > VFIOGroup *group; > VFIODevice *vbasedev; > @@ -329,13 +329,8 @@ static bool vfio_devices_all_saving(VFIOContainer *container) > return false; > } > > - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { > - if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) > - && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { > - return false; > - } > - continue; > - } else { > + if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) > + && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { > return false; > } > } > @@ -987,6 +982,44 @@ static void vfio_listener_region_del(MemoryListener *listener, > } > } > > +static void vfio_set_dirty_page_tracking(VFIOContainer *container, bool start) > +{ > + int ret; > + struct vfio_iommu_type1_dirty_bitmap dirty = { > + .argsz = sizeof(dirty), > + }; > + > + if (start) { > + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; > + } else { > + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; > + } > + > + ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); > + if (ret) { > + error_report("Failed to set dirty tracking flag 0x%x errno: %d", > + dirty.flags, errno); > + } > +} > + > +static void vfio_listener_log_start(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, true); > +} > + > +static void vfio_listener_log_stop(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, false); > +} > + > static int vfio_get_dirty_bitmap(VFIOContainer *container, uint64_t iova, > uint64_t size, ram_addr_t ram_addr) > { > @@ -1128,7 +1161,7 @@ static void vfio_listerner_log_sync(MemoryListener *listener, > return; > } > > - if (vfio_devices_all_saving(container)) { > + if (vfio_devices_all_dirty_tracking(container)) { > vfio_sync_dirty_bitmap(container, section); > } > } > @@ -1136,6 +1169,8 @@ static void vfio_listerner_log_sync(MemoryListener *listener, > static const MemoryListener vfio_memory_listener = { > .region_add = vfio_listener_region_add, > .region_del = vfio_listener_region_del, > + .log_start = vfio_listener_log_start, > + .log_stop = vfio_listener_log_stop, > .log_sync = vfio_listerner_log_sync, > }; > > diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c > index 00daa50ed8..c0f646823a 100644 > --- a/hw/vfio/migration.c > +++ b/hw/vfio/migration.c > @@ -395,40 +395,10 @@ static int vfio_load_device_config_state(QEMUFile *f, void *opaque) > return qemu_file_get_error(f); > } > > -static int vfio_set_dirty_page_tracking(VFIODevice *vbasedev, bool start) > -{ > - int ret; > - VFIOMigration *migration = vbasedev->migration; > - VFIOContainer *container = vbasedev->group->container; > - struct vfio_iommu_type1_dirty_bitmap dirty = { > - .argsz = sizeof(dirty), > - }; > - > - if (start) { > - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { > - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; > - } else { > - return -EINVAL; > - } > - } else { > - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; > - } > - > - ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); > - if (ret) { > - error_report("Failed to set dirty tracking flag 0x%x errno: %d", > - dirty.flags, errno); > - return -errno; > - } > - return ret; > -} > - > static void vfio_migration_cleanup(VFIODevice *vbasedev) > { > VFIOMigration *migration = vbasedev->migration; > > - vfio_set_dirty_page_tracking(vbasedev, false); > - > if (migration->region.mmaps) { > vfio_region_unmap(&migration->region); > } > @@ -469,11 +439,6 @@ static int vfio_save_setup(QEMUFile *f, void *opaque) > return ret; > } > > - ret = vfio_set_dirty_page_tracking(vbasedev, true); > - if (ret) { > - return ret; > - } > - > qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE); > > ret = qemu_file_get_error(f); From MAILER-DAEMON Tue Jan 26 18:00:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4XKM-00026B-W3 for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 18:00:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4XKL-00025x-Lm; Tue, 26 Jan 2021 18:00:49 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]:40598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4XKI-0007eT-9a; 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[2001:470:b8f6:1b::1]) by smtp.gmail.com with ESMTPSA id l12sm75400oov.37.2021.01.26.15.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 15:00:42 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:2d17:e42b:3add:fd]) by serve.minyard.net (Postfix) with ESMTPSA id 8000D18055B; Tue, 26 Jan 2021 23:00:41 +0000 (UTC) Date: Tue, 26 Jan 2021 17:00:40 -0600 From: Corey Minyard To: Hao Wu Cc: peter.maydell@linaro.org, venture@google.com, hskinnemoen@google.com, qemu-devel@nongnu.org, kfting@nuvoton.com, qemu-arm@nongnu.org, Avi.Fishman@nuvoton.com, dje@google.com Subject: Re: [PATCH 2/6] hw/i2c: Implement NPCM7XX SMBus Module Single Mode Message-ID: <20210126230040.GA2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-3-wuhaotsh@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210126193237.1534208-3-wuhaotsh@google.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=tcminyard@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 23:00:49 -0000 On Tue, Jan 26, 2021 at 11:32:33AM -0800, wuhaotsh--- via wrote: > This commit implements the single-byte mode of the SMBus. > > Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses > compliant with SMBus and I2C protocol. > > This patch implements the single-byte mode of the SMBus. In this mode, > the user sends or receives a byte each time. The SMBus device transmits > it to the underlying i2c device and sends an interrupt back to the QEMU > guest. I don't see any functional issues with this. The register order in the switch statements is rather confusing. I see that it's the order of the registers in memory, but it kind of threw me at first. That's ok, I think, though a comment might be welcome. The VMStateDescription structure is not necessary, and is misleading, as there's no support for VMState transfer on this system, and you haven't put anything into it, anyway. So you should probably remove that. Reviewed-by: Corey Minyard -corey > > Reviewed-by: Doug Evans > Reviewed-by: Tyrong Ting > Signed-off-by: Hao Wu > --- > docs/system/arm/nuvoton.rst | 2 +- > hw/arm/npcm7xx.c | 68 ++- > hw/i2c/meson.build | 1 + > hw/i2c/npcm7xx_smbus.c | 766 +++++++++++++++++++++++++++++++++ > hw/i2c/trace-events | 11 + > include/hw/arm/npcm7xx.h | 2 + > include/hw/i2c/npcm7xx_smbus.h | 88 ++++ > 7 files changed, 921 insertions(+), 17 deletions(-) > create mode 100644 hw/i2c/npcm7xx_smbus.c > create mode 100644 include/hw/i2c/npcm7xx_smbus.h > > diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst > index a1786342e2..34fc799b2d 100644 > --- a/docs/system/arm/nuvoton.rst > +++ b/docs/system/arm/nuvoton.rst > @@ -43,6 +43,7 @@ Supported devices > * GPIO controller > * Analog to Digital Converter (ADC) > * Pulse Width Modulation (PWM) > + * SMBus controller (SMBF) > > Missing devices > --------------- > @@ -58,7 +59,6 @@ Missing devices > > * Ethernet controllers (GMAC and EMC) > * USB device (USBD) > - * SMBus controller (SMBF) > * Peripheral SPI controller (PSPI) > * SD/MMC host > * PECI interface > diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c > index d1fe9bd1df..8f596ffd69 100644 > --- a/hw/arm/npcm7xx.c > +++ b/hw/arm/npcm7xx.c > @@ -104,6 +104,22 @@ enum NPCM7xxInterrupt { > NPCM7XX_OHCI_IRQ = 62, > NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ > NPCM7XX_PWM1_IRQ, /* PWM module 1 */ > + NPCM7XX_SMBUS0_IRQ = 64, > + NPCM7XX_SMBUS1_IRQ, > + NPCM7XX_SMBUS2_IRQ, > + NPCM7XX_SMBUS3_IRQ, > + NPCM7XX_SMBUS4_IRQ, > + NPCM7XX_SMBUS5_IRQ, > + NPCM7XX_SMBUS6_IRQ, > + NPCM7XX_SMBUS7_IRQ, > + NPCM7XX_SMBUS8_IRQ, > + NPCM7XX_SMBUS9_IRQ, > + NPCM7XX_SMBUS10_IRQ, > + NPCM7XX_SMBUS11_IRQ, > + NPCM7XX_SMBUS12_IRQ, > + NPCM7XX_SMBUS13_IRQ, > + NPCM7XX_SMBUS14_IRQ, > + NPCM7XX_SMBUS15_IRQ, > NPCM7XX_GPIO0_IRQ = 116, > NPCM7XX_GPIO1_IRQ, > NPCM7XX_GPIO2_IRQ, > @@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] = { > 0xf0104000, > }; > > +/* Direct memory-mapped access to each SMBus Module. */ > +static const hwaddr npcm7xx_smbus_addr[] = { > + 0xf0080000, > + 0xf0081000, > + 0xf0082000, > + 0xf0083000, > + 0xf0084000, > + 0xf0085000, > + 0xf0086000, > + 0xf0087000, > + 0xf0088000, > + 0xf0089000, > + 0xf008a000, > + 0xf008b000, > + 0xf008c000, > + 0xf008d000, > + 0xf008e000, > + 0xf008f000, > +}; > + > static const struct { > hwaddr regs_addr; > uint32_t unconnected_pins; > @@ -353,6 +389,11 @@ static void npcm7xx_init(Object *obj) > object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); > } > > + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { > + object_initialize_child(obj, "smbus[*]", &s->smbus[i], > + TYPE_NPCM7XX_SMBUS); > + } > + > object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); > object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); > > @@ -509,6 +550,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) > npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); > } > > + /* SMBus modules. Cannot fail. */ > + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); > + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { > + Object *obj = OBJECT(&s->smbus[i]); > + > + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); > + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, > + npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); > + } > + > /* USB Host */ > object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, > &error_abort); > @@ -576,22 +628,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); > create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); > create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); > - create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); > create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); > create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); > create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); > diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build > index 3a511539ad..cdcd694a7f 100644 > --- a/hw/i2c/meson.build > +++ b/hw/i2c/meson.build > @@ -9,6 +9,7 @@ i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c')) > i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) > i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) > i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) > +i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c')) > i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) > i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c')) > i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c')) > diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c > new file mode 100644 > index 0000000000..e8a8fdbaff > --- /dev/null > +++ b/hw/i2c/npcm7xx_smbus.c > @@ -0,0 +1,766 @@ > +/* > + * Nuvoton NPCM7xx SMBus Module. > + * > + * Copyright 2020 Google LLC > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/i2c/npcm7xx_smbus.h" > +#include "migration/vmstate.h" > +#include "qemu/bitops.h" > +#include "qemu/guest-random.h" > +#include "qemu/log.h" > +#include "qemu/module.h" > +#include "qemu/units.h" > + > +#include "trace.h" > + > +#define NPCM7XX_SMBUS_VERSION 1 > +#define NPCM7XX_SMBUS_FIFO_EN 0 > + > +enum NPCM7xxSMBusCommonRegister { > + NPCM7XX_SMB_SDA = 0x0, > + NPCM7XX_SMB_ST = 0x2, > + NPCM7XX_SMB_CST = 0x4, > + NPCM7XX_SMB_CTL1 = 0x6, > + NPCM7XX_SMB_ADDR1 = 0x8, > + NPCM7XX_SMB_CTL2 = 0xa, > + NPCM7XX_SMB_ADDR2 = 0xc, > + NPCM7XX_SMB_CTL3 = 0xe, > + NPCM7XX_SMB_CST2 = 0x18, > + NPCM7XX_SMB_CST3 = 0x19, > + NPCM7XX_SMB_VER = 0x1f, > +}; > + > +enum NPCM7xxSMBusBank0Register { > + NPCM7XX_SMB_ADDR3 = 0x10, > + NPCM7XX_SMB_ADDR7 = 0x11, > + NPCM7XX_SMB_ADDR4 = 0x12, > + NPCM7XX_SMB_ADDR8 = 0x13, > + NPCM7XX_SMB_ADDR5 = 0x14, > + NPCM7XX_SMB_ADDR9 = 0x15, > + NPCM7XX_SMB_ADDR6 = 0x16, > + NPCM7XX_SMB_ADDR10 = 0x17, > + NPCM7XX_SMB_CTL4 = 0x1a, > + NPCM7XX_SMB_CTL5 = 0x1b, > + NPCM7XX_SMB_SCLLT = 0x1c, > + NPCM7XX_SMB_FIF_CTL = 0x1d, > + NPCM7XX_SMB_SCLHT = 0x1e, > +}; > + > +enum NPCM7xxSMBusBank1Register { > + NPCM7XX_SMB_FIF_CTS = 0x10, > + NPCM7XX_SMB_FAIR_PER = 0x11, > + NPCM7XX_SMB_TXF_CTL = 0x12, > + NPCM7XX_SMB_T_OUT = 0x14, > + NPCM7XX_SMB_TXF_STS = 0x1a, > + NPCM7XX_SMB_RXF_STS = 0x1c, > + NPCM7XX_SMB_RXF_CTL = 0x1e, > +}; > + > +/* ST fields */ > +#define NPCM7XX_SMBST_STP BIT(7) > +#define NPCM7XX_SMBST_SDAST BIT(6) > +#define NPCM7XX_SMBST_BER BIT(5) > +#define NPCM7XX_SMBST_NEGACK BIT(4) > +#define NPCM7XX_SMBST_STASTR BIT(3) > +#define NPCM7XX_SMBST_NMATCH BIT(2) > +#define NPCM7XX_SMBST_MODE BIT(1) > +#define NPCM7XX_SMBST_XMIT BIT(0) > + > +/* CST fields */ > +#define NPCM7XX_SMBCST_ARPMATCH BIT(7) > +#define NPCM7XX_SMBCST_MATCHAF BIT(6) > +#define NPCM7XX_SMBCST_TGSCL BIT(5) > +#define NPCM7XX_SMBCST_TSDA BIT(4) > +#define NPCM7XX_SMBCST_GCMATCH BIT(3) > +#define NPCM7XX_SMBCST_MATCH BIT(2) > +#define NPCM7XX_SMBCST_BB BIT(1) > +#define NPCM7XX_SMBCST_BUSY BIT(0) > + > +/* CST2 fields */ > +#define NPCM7XX_SMBCST2_INTSTS BIT(7) > +#define NPCM7XX_SMBCST2_MATCH7F BIT(6) > +#define NPCM7XX_SMBCST2_MATCH6F BIT(5) > +#define NPCM7XX_SMBCST2_MATCH5F BIT(4) > +#define NPCM7XX_SMBCST2_MATCH4F BIT(3) > +#define NPCM7XX_SMBCST2_MATCH3F BIT(2) > +#define NPCM7XX_SMBCST2_MATCH2F BIT(1) > +#define NPCM7XX_SMBCST2_MATCH1F BIT(0) > + > +/* CST3 fields */ > +#define NPCM7XX_SMBCST3_EO_BUSY BIT(7) > +#define NPCM7XX_SMBCST3_MATCH10F BIT(2) > +#define NPCM7XX_SMBCST3_MATCH9F BIT(1) > +#define NPCM7XX_SMBCST3_MATCH8F BIT(0) > + > +/* CTL1 fields */ > +#define NPCM7XX_SMBCTL1_STASTRE BIT(7) > +#define NPCM7XX_SMBCTL1_NMINTE BIT(6) > +#define NPCM7XX_SMBCTL1_GCMEN BIT(5) > +#define NPCM7XX_SMBCTL1_ACK BIT(4) > +#define NPCM7XX_SMBCTL1_EOBINTE BIT(3) > +#define NPCM7XX_SMBCTL1_INTEN BIT(2) > +#define NPCM7XX_SMBCTL1_STOP BIT(1) > +#define NPCM7XX_SMBCTL1_START BIT(0) > + > +/* CTL2 fields */ > +#define NPCM7XX_SMBCTL2_SCLFRQ(rv) extract8((rv), 1, 6) > +#define NPCM7XX_SMBCTL2_ENABLE BIT(0) > + > +/* CTL3 fields */ > +#define NPCM7XX_SMBCTL3_SCL_LVL BIT(7) > +#define NPCM7XX_SMBCTL3_SDA_LVL BIT(6) > +#define NPCM7XX_SMBCTL3_BNK_SEL BIT(5) > +#define NPCM7XX_SMBCTL3_400K_MODE BIT(4) > +#define NPCM7XX_SMBCTL3_IDL_START BIT(3) > +#define NPCM7XX_SMBCTL3_ARPMEN BIT(2) > +#define NPCM7XX_SMBCTL3_SCLFRQ(rv) extract8((rv), 0, 2) > + > +/* ADDR fields */ > +#define NPCM7XX_ADDR_EN BIT(7) > +#define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) > + > +#define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) > +#define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) > + > +#define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) > + > +/* Reset values */ > +#define NPCM7XX_SMB_ST_INIT_VAL 0x00 > +#define NPCM7XX_SMB_CST_INIT_VAL 0x10 > +#define NPCM7XX_SMB_CST2_INIT_VAL 0x00 > +#define NPCM7XX_SMB_CST3_INIT_VAL 0x00 > +#define NPCM7XX_SMB_CTL1_INIT_VAL 0x00 > +#define NPCM7XX_SMB_CTL2_INIT_VAL 0x00 > +#define NPCM7XX_SMB_CTL3_INIT_VAL 0xc0 > +#define NPCM7XX_SMB_CTL4_INIT_VAL 0x07 > +#define NPCM7XX_SMB_CTL5_INIT_VAL 0x00 > +#define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 > +#define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 > +#define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 > + > +static uint8_t npcm7xx_smbus_get_version(void) > +{ > + return NPCM7XX_SMBUS_FIFO_EN << 7 | NPCM7XX_SMBUS_VERSION; > +} > + > +static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) > +{ > + int level; > + > + if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { > + level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && > + s->st & NPCM7XX_SMBST_NMATCH) || > + (s->st & NPCM7XX_SMBST_BER) || > + (s->st & NPCM7XX_SMBST_NEGACK) || > + (s->st & NPCM7XX_SMBST_SDAST) || > + (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && > + s->st & NPCM7XX_SMBST_SDAST) || > + (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && > + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); > + > + if (level) { > + s->cst2 |= NPCM7XX_SMBCST2_INTSTS; > + } else { > + s->cst2 &= ~NPCM7XX_SMBCST2_INTSTS; > + } > + qemu_set_irq(s->irq, level); > + } > +} > + > +static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) > +{ > + s->st &= ~NPCM7XX_SMBST_SDAST; > + s->st |= NPCM7XX_SMBST_NEGACK; > + s->status = NPCM7XX_SMBUS_STATUS_NEGACK; > +} > + > +static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) > +{ > + int rv = i2c_send(s->bus, value); > + > + if (rv) { > + npcm7xx_smbus_nack(s); > + } else { > + s->st |= NPCM7XX_SMBST_SDAST; > + } > + trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) > +{ > + s->sda = i2c_recv(s->bus); > + s->st |= NPCM7XX_SMBST_SDAST; > + if (s->st & NPCM7XX_SMBCTL1_ACK) { > + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); > + i2c_nack(s->bus); > + s->st &= NPCM7XX_SMBCTL1_ACK; > + } > + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), s->sda); > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) > +{ > + /* > + * We can start the bus if one of these is true: > + * 1. The bus is idle (so we can request it) > + * 2. We are the occupier (it's a repeated start condition.) > + */ > + int available = !i2c_bus_busy(s->bus) || > + s->status != NPCM7XX_SMBUS_STATUS_IDLE; > + > + if (available) { > + s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; > + s->cst |= NPCM7XX_SMBCST_BUSY; > + } else { > + s->st &= ~NPCM7XX_SMBST_MODE; > + s->cst &= ~NPCM7XX_SMBCST_BUSY; > + s->st |= NPCM7XX_SMBST_BER; > + } > + > + trace_npcm7xx_smbus_start(DEVICE(s)->canonical_path, available); > + s->cst |= NPCM7XX_SMBCST_BB; > + s->status = NPCM7XX_SMBUS_STATUS_IDLE; > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) > +{ > + int recv; > + int rv; > + > + recv = value & BIT(0); > + rv = i2c_start_transfer(s->bus, value >> 1, recv); > + trace_npcm7xx_smbus_send_address(DEVICE(s)->canonical_path, > + value >> 1, recv, !rv); > + if (rv) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: requesting i2c bus for 0x%02x failed: %d\n", > + DEVICE(s)->canonical_path, value, rv); > + /* Failed to start transfer. NACK to reject.*/ > + if (recv) { > + s->st &= ~NPCM7XX_SMBST_XMIT; > + } else { > + s->st |= NPCM7XX_SMBST_XMIT; > + } > + npcm7xx_smbus_nack(s); > + npcm7xx_smbus_update_irq(s); > + return; > + } > + > + s->st &= ~NPCM7XX_SMBST_NEGACK; > + if (recv) { > + s->status = NPCM7XX_SMBUS_STATUS_RECEIVING; > + s->st &= ~NPCM7XX_SMBST_XMIT; > + } else { > + s->status = NPCM7XX_SMBUS_STATUS_SENDING; > + s->st |= NPCM7XX_SMBST_XMIT; > + } > + > + if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { > + s->st |= NPCM7XX_SMBST_STASTR; > + if (!recv) { > + s->st |= NPCM7XX_SMBST_SDAST; > + } > + } else if (recv) { > + npcm7xx_smbus_recv_byte(s); > + } > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_execute_stop(NPCM7xxSMBusState *s) > +{ > + i2c_end_transfer(s->bus); > + s->st = 0; > + s->cst = 0; > + s->status = NPCM7XX_SMBUS_STATUS_IDLE; > + s->cst3 |= NPCM7XX_SMBCST3_EO_BUSY; > + trace_npcm7xx_smbus_stop(DEVICE(s)->canonical_path); > + npcm7xx_smbus_update_irq(s); > +} > + > + > +static void npcm7xx_smbus_stop(NPCM7xxSMBusState *s) > +{ > + if (s->st & NPCM7XX_SMBST_MODE) { > + switch (s->status) { > + case NPCM7XX_SMBUS_STATUS_RECEIVING: > + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: > + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE; > + break; > + > + case NPCM7XX_SMBUS_STATUS_NEGACK: > + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK; > + break; > + > + default: > + npcm7xx_smbus_execute_stop(s); > + break; > + } > + } > +} > + > +static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) > +{ > + uint8_t value = s->sda; > + > + switch (s->status) { > + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: > + npcm7xx_smbus_execute_stop(s); > + break; > + > + case NPCM7XX_SMBUS_STATUS_RECEIVING: > + npcm7xx_smbus_recv_byte(s); > + break; > + > + default: > + /* Do nothing */ > + break; > + } > + > + return value; > +} > + > +static void npcm7xx_smbus_write_sda(NPCM7xxSMBusState *s, uint8_t value) > +{ > + s->sda = value; > + if (s->st & NPCM7XX_SMBST_MODE) { > + switch (s->status) { > + case NPCM7XX_SMBUS_STATUS_IDLE: > + npcm7xx_smbus_send_address(s, value); > + break; > + case NPCM7XX_SMBUS_STATUS_SENDING: > + npcm7xx_smbus_send_byte(s, value); > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to SDA in invalid status %d: %u\n", > + DEVICE(s)->canonical_path, s->status, value); > + break; > + } > + } > +} > + > +static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) > +{ > + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STP); > + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_BER); > + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STASTR); > + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_NMATCH); > + > + if (value & NPCM7XX_SMBST_NEGACK) { > + s->st &= ~NPCM7XX_SMBST_NEGACK; > + if (s->status == NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK) { > + npcm7xx_smbus_execute_stop(s); > + } > + } > + > + if (value & NPCM7XX_SMBST_STASTR && > + s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { > + npcm7xx_smbus_recv_byte(s); > + } > + > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_write_cst(NPCM7xxSMBusState *s, uint8_t value) > +{ > + uint8_t new_value = s->cst; > + > + s->cst = WRITE_ONE_CLEAR(new_value, value, NPCM7XX_SMBCST_BB); > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_write_cst3(NPCM7xxSMBusState *s, uint8_t value) > +{ > + s->cst3 = WRITE_ONE_CLEAR(s->cst3, value, NPCM7XX_SMBCST3_EO_BUSY); > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_write_ctl1(NPCM7xxSMBusState *s, uint8_t value) > +{ > + s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, > + NPCM7XX_SMBCTL1_START | NPCM7XX_SMBCTL1_STOP | NPCM7XX_SMBCTL1_ACK); > + > + if (value & NPCM7XX_SMBCTL1_START) { > + npcm7xx_smbus_start(s); > + } > + > + if (value & NPCM7XX_SMBCTL1_STOP) { > + npcm7xx_smbus_stop(s); > + } > + > + npcm7xx_smbus_update_irq(s); > +} > + > +static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) > +{ > + s->ctl2 = value; > + > + if (!NPCM7XX_SMBUS_ENABLED(s)) { > + /* Disable this SMBus module. */ > + s->ctl1 = 0; > + s->st = 0; > + s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); > + s->cst = 0; > + } > +} > + > +static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) > +{ > + uint8_t old_ctl3 = s->ctl3; > + > + /* Write to SDA and SCL bits are ignored. */ > + s->ctl3 = KEEP_OLD_BIT(old_ctl3, value, > + NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_LVL); > +} > + > +static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) > +{ > + NPCM7xxSMBusState *s = opaque; > + uint64_t value = 0; > + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; > + > + switch (offset) { > + case NPCM7XX_SMB_SDA: > + value = npcm7xx_smbus_read_sda(s); > + break; > + > + case NPCM7XX_SMB_ST: > + value = s->st; > + break; > + > + case NPCM7XX_SMB_CST: > + value = s->cst; > + break; > + > + case NPCM7XX_SMB_CTL1: > + value = s->ctl1; > + break; > + > + case NPCM7XX_SMB_ADDR1: > + value = s->addr[0]; > + break; > + > + case NPCM7XX_SMB_CTL2: > + value = s->ctl2; > + break; > + > + case NPCM7XX_SMB_ADDR2: > + value = s->addr[1]; > + break; > + > + case NPCM7XX_SMB_CTL3: > + value = s->ctl3; > + break; > + > + case NPCM7XX_SMB_CST2: > + value = s->cst2; > + break; > + > + case NPCM7XX_SMB_CST3: > + value = s->cst3; > + break; > + > + case NPCM7XX_SMB_VER: > + value = npcm7xx_smbus_get_version(); > + break; > + > + /* This register is either invalid or banked at this point. */ > + default: > + if (bank) { > + /* Bank 1 */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + } else { > + /* Bank 0 */ > + switch (offset) { > + case NPCM7XX_SMB_ADDR3: > + value = s->addr[2]; > + break; > + > + case NPCM7XX_SMB_ADDR7: > + value = s->addr[6]; > + break; > + > + case NPCM7XX_SMB_ADDR4: > + value = s->addr[3]; > + break; > + > + case NPCM7XX_SMB_ADDR8: > + value = s->addr[7]; > + break; > + > + case NPCM7XX_SMB_ADDR5: > + value = s->addr[4]; > + break; > + > + case NPCM7XX_SMB_ADDR9: > + value = s->addr[8]; > + break; > + > + case NPCM7XX_SMB_ADDR6: > + value = s->addr[5]; > + break; > + > + case NPCM7XX_SMB_ADDR10: > + value = s->addr[9]; > + break; > + > + case NPCM7XX_SMB_CTL4: > + value = s->ctl4; > + break; > + > + case NPCM7XX_SMB_CTL5: > + value = s->ctl5; > + break; > + > + case NPCM7XX_SMB_SCLLT: > + value = s->scllt; > + break; > + > + case NPCM7XX_SMB_SCLHT: > + value = s->sclht; > + break; > + > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + break; > + } > + } > + break; > + } > + > + trace_npcm7xx_smbus_read(DEVICE(s)->canonical_path, offset, value, size); > + > + return value; > +} > + > +static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, > + unsigned size) > +{ > + NPCM7xxSMBusState *s = opaque; > + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; > + > + trace_npcm7xx_smbus_write(DEVICE(s)->canonical_path, offset, value, size); > + > + switch (offset) { > + case NPCM7XX_SMB_SDA: > + npcm7xx_smbus_write_sda(s, value); > + break; > + > + case NPCM7XX_SMB_ST: > + npcm7xx_smbus_write_st(s, value); > + break; > + > + case NPCM7XX_SMB_CST: > + npcm7xx_smbus_write_cst(s, value); > + break; > + > + case NPCM7XX_SMB_CTL1: > + npcm7xx_smbus_write_ctl1(s, value); > + break; > + > + case NPCM7XX_SMB_ADDR1: > + s->addr[0] = value; > + break; > + > + case NPCM7XX_SMB_CTL2: > + npcm7xx_smbus_write_ctl2(s, value); > + break; > + > + case NPCM7XX_SMB_ADDR2: > + s->addr[1] = value; > + break; > + > + case NPCM7XX_SMB_CTL3: > + npcm7xx_smbus_write_ctl3(s, value); > + break; > + > + case NPCM7XX_SMB_CST2: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + break; > + > + case NPCM7XX_SMB_CST3: > + npcm7xx_smbus_write_cst3(s, value); > + break; > + > + case NPCM7XX_SMB_VER: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + break; > + > + /* This register is either invalid or banked at this point. */ > + default: > + if (bank) { > + /* Bank 1 */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + } else { > + /* Bank 0 */ > + switch (offset) { > + case NPCM7XX_SMB_ADDR3: > + s->addr[2] = value; > + break; > + > + case NPCM7XX_SMB_ADDR7: > + s->addr[6] = value; > + break; > + > + case NPCM7XX_SMB_ADDR4: > + s->addr[3] = value; > + break; > + > + case NPCM7XX_SMB_ADDR8: > + s->addr[7] = value; > + break; > + > + case NPCM7XX_SMB_ADDR5: > + s->addr[4] = value; > + break; > + > + case NPCM7XX_SMB_ADDR9: > + s->addr[8] = value; > + break; > + > + case NPCM7XX_SMB_ADDR6: > + s->addr[5] = value; > + break; > + > + case NPCM7XX_SMB_ADDR10: > + s->addr[9] = value; > + break; > + > + case NPCM7XX_SMB_CTL4: > + s->ctl4 = value; > + break; > + > + case NPCM7XX_SMB_CTL5: > + s->ctl5 = value; > + break; > + > + case NPCM7XX_SMB_SCLLT: > + s->scllt = value; > + break; > + > + case NPCM7XX_SMB_SCLHT: > + s->sclht = value; > + break; > + > + default: > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", > + DEVICE(s)->canonical_path, offset); > + break; > + } > + } > + break; > + } > +} > + > +static const MemoryRegionOps npcm7xx_smbus_ops = { > + .read = npcm7xx_smbus_read, > + .write = npcm7xx_smbus_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 1, > + .unaligned = false, > + }, > +}; > + > +static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) > +{ > + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); > + > + s->st = NPCM7XX_SMB_ST_INIT_VAL; > + s->cst = NPCM7XX_SMB_CST_INIT_VAL; > + s->cst2 = NPCM7XX_SMB_CST2_INIT_VAL; > + s->cst3 = NPCM7XX_SMB_CST3_INIT_VAL; > + s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; > + s->ctl2 = NPCM7XX_SMB_CTL2_INIT_VAL; > + s->ctl3 = NPCM7XX_SMB_CTL3_INIT_VAL; > + s->ctl4 = NPCM7XX_SMB_CTL4_INIT_VAL; > + s->ctl5 = NPCM7XX_SMB_CTL5_INIT_VAL; > + > + for (int i = 0; i < NPCM7XX_SMBUS_NR_ADDRS; ++i) { > + s->addr[i] = NPCM7XX_SMB_ADDR_INIT_VAL; > + } > + s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; > + s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; > + > + s->status = NPCM7XX_SMBUS_STATUS_IDLE; > +} > + > +static void npcm7xx_smbus_hold_reset(Object *obj) > +{ > + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); > + > + qemu_irq_lower(s->irq); > +} > + > +static void npcm7xx_smbus_init(Object *obj) > +{ > + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); > + > + sysbus_init_irq(sbd, &s->irq); > + memory_region_init_io(&s->iomem, obj, &npcm7xx_smbus_ops, s, > + "regs", 4 * KiB); > + sysbus_init_mmio(sbd, &s->iomem); > + > + s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); > + s->status = NPCM7XX_SMBUS_STATUS_IDLE; > +} > + > +static const VMStateDescription vmstate_npcm7xx_smbus = { > + .name = "npcm7xx-smbus", > + .version_id = 0, > + .minimum_version_id = 0, > + .fields = (VMStateField[]) { > + VMSTATE_END_OF_LIST(), > + }, > +}; > + > +static void npcm7xx_smbus_class_init(ObjectClass *klass, void *data) > +{ > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->desc = "NPCM7xx System Management Bus"; > + dc->vmsd = &vmstate_npcm7xx_smbus; > + rc->phases.enter = npcm7xx_smbus_enter_reset; > + rc->phases.hold = npcm7xx_smbus_hold_reset; > +} > + > +static const TypeInfo npcm7xx_smbus_types[] = { > + { > + .name = TYPE_NPCM7XX_SMBUS, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(NPCM7xxSMBusState), > + .class_init = npcm7xx_smbus_class_init, > + .instance_init = npcm7xx_smbus_init, > + }, > +}; > +DEFINE_TYPES(npcm7xx_smbus_types); > diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events > index 08db8fa689..c3bb70ad04 100644 > --- a/hw/i2c/trace-events > +++ b/hw/i2c/trace-events > @@ -14,3 +14,14 @@ aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t val > aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 > aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x" > aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x" > + > +# npcm7xx_smbus.c > + > +npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" > +npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" > +npcm7xx_smbus_start(const char *id, int success) "%s starting, success: %d" > +npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int success) "%s sending address: 0x%02x, recv: %d, success: %d" > +npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byte: 0x%02x, success: %d" > +npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x" > +npcm7xx_smbus_stop(const char *id) "%s stopping" > +npcm7xx_smbus_nack(const char *id) "%s nacking" > diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h > index f6227aa8aa..cea1bd1f62 100644 > --- a/include/hw/arm/npcm7xx.h > +++ b/include/hw/arm/npcm7xx.h > @@ -20,6 +20,7 @@ > #include "hw/adc/npcm7xx_adc.h" > #include "hw/cpu/a9mpcore.h" > #include "hw/gpio/npcm7xx_gpio.h" > +#include "hw/i2c/npcm7xx_smbus.h" > #include "hw/mem/npcm7xx_mc.h" > #include "hw/misc/npcm7xx_clk.h" > #include "hw/misc/npcm7xx_gcr.h" > @@ -85,6 +86,7 @@ typedef struct NPCM7xxState { > NPCM7xxMCState mc; > NPCM7xxRNGState rng; > NPCM7xxGPIOState gpio[8]; > + NPCM7xxSMBusState smbus[16]; > EHCISysBusState ehci; > OHCISysBusState ohci; > NPCM7xxFIUState fiu[2]; > diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h > new file mode 100644 > index 0000000000..b9761a6993 > --- /dev/null > +++ b/include/hw/i2c/npcm7xx_smbus.h > @@ -0,0 +1,88 @@ > +/* > + * Nuvoton NPCM7xx SMBus Module. > + * > + * Copyright 2020 Google LLC > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > +#ifndef NPCM7XX_SMBUS_H > +#define NPCM7XX_SMBUS_H > + > +#include "exec/memory.h" > +#include "hw/i2c/i2c.h" > +#include "hw/irq.h" > +#include "hw/sysbus.h" > + > +/* > + * Number of addresses this module contains. Do not change this without > + * incrementing the version_id in the vmstate. > + */ > +#define NPCM7XX_SMBUS_NR_ADDRS 10 > + > +typedef enum NPCM7xxSMBusStatus { > + NPCM7XX_SMBUS_STATUS_IDLE, > + NPCM7XX_SMBUS_STATUS_SENDING, > + NPCM7XX_SMBUS_STATUS_RECEIVING, > + NPCM7XX_SMBUS_STATUS_NEGACK, > + NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, > + NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, > +} NPCM7xxSMBusStatus; > + > +/* > + * struct NPCM7xxSMBusState - System Management Bus device state. > + * @bus: The underlying I2C Bus. > + * @irq: GIC interrupt line to fire on events (if enabled). > + * @sda: The serial data register. > + * @st: The status register. > + * @cst: The control status register. > + * @cst2: The control status register 2. > + * @cst3: The control status register 3. > + * @ctl1: The control register 1. > + * @ctl2: The control register 2. > + * @ctl3: The control register 3. > + * @ctl4: The control register 4. > + * @ctl5: The control register 5. > + * @addr: The SMBus module's own addresses on the I2C bus. > + * @scllt: The SCL low time register. > + * @sclht: The SCL high time register. > + * @status: The current status of the SMBus. > + */ > +typedef struct NPCM7xxSMBusState { > + SysBusDevice parent; > + > + MemoryRegion iomem; > + > + I2CBus *bus; > + qemu_irq irq; > + > + uint8_t sda; > + uint8_t st; > + uint8_t cst; > + uint8_t cst2; > + uint8_t cst3; > + uint8_t ctl1; > + uint8_t ctl2; > + uint8_t ctl3; > + uint8_t ctl4; > + uint8_t ctl5; > + uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; > + > + uint8_t scllt; > + uint8_t sclht; > + > + NPCM7xxSMBusStatus status; > +} NPCM7xxSMBusState; > + > +#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" > +#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ > + TYPE_NPCM7XX_SMBUS) > + > +#endif /* NPCM7XX_SMBUS_H */ > -- > 2.30.0.365.g02bc693789-goog > > From MAILER-DAEMON Tue Jan 26 18:05:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4XOj-0003UZ-B2 for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 18:05:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4XOd-0003U6-4g; Tue, 26 Jan 2021 18:05:15 -0500 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]:35424) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4XOb-0000iY-MU; Tue, 26 Jan 2021 18:05:14 -0500 Received: by mail-ot1-x32f.google.com with SMTP id 36so17974026otp.2; Tue, 26 Jan 2021 15:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:date:from:to:cc:subject:message-id:reply-to:references :mime-version:content-disposition:in-reply-to; bh=70wjpOoxSHNYu/4QktbvF2y/JLdTpdDsZuCErOKdUbw=; b=KXmBxIObxrqUxHeotVAPWmazWUu/K0K9sMlRr/DDzWeqtCQg9s6ICyb/OB04GfXJPc p0SY0xgVsca17Hi4ZCB37lNx7VMdrmRhQd/Pztx8XhXE97WAg1fCPx6wgfuOBcNjwzhc UMhaOi+bKbD8UOONkrdqGI5AvN34lBJYhu5HhEHPt3kcOt1oaWm5OsGZi+k0MYz0DhW0 GpXuubTAcsSFdm3EJJ0en0iEghrglJSwWIRol4xf0yppjTbrsgT18WtCrob58SDEVBwy VXoJKwlyt4i+VYLRrzC/DRVBRq8GgCImtZ3qbTcV01ekz5GbZZ0dPTzH7ClQXherx8uv FVyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :reply-to:references:mime-version:content-disposition:in-reply-to; bh=70wjpOoxSHNYu/4QktbvF2y/JLdTpdDsZuCErOKdUbw=; b=EkoCUUff7bfc2FOim47CRh1Mgy8ekWGSJMO2Xg2AJUgEj9IFrgfqZnbRElK9ABzMmV jh+dXtb5NRap3NILeVjSPuVMeozgOeghs/adHLawRyqIjzGdtO0w4DzrxBAuEU8BRdLP kL9diNPrTb3TcOTzb5sWDdgnw13VCn9EwiM+ed3wZOz+PXtgfRCtZb9SDnvG1Z5AwIa2 kuawUVYiJ2PjcK9HHwESMYnTsveejPc8yqgxhnqeyFnWT1Gu5+unzqwP9OZA617y73LY U83imuEiRdNv939pQr7I09w5sVXw1HSXa3TNt3UoRv6jFXrLVBjoOKTgW1tgODMmAD1Y liaw== X-Gm-Message-State: AOAM532kV9OnOSYbaXzzLupHm0ccPSI9Hs7I+vkBGfm+VkLh6xydEEBY kaPpAWNcE5Stnfox+7sKKw== X-Google-Smtp-Source: ABdhPJwD1wXXHqoTc36wySdFYxFrVGPLoq+8600t7Iomd3BUyC/ZxmScxd6Pb8eZJQZuVFsLTQCOrA== X-Received: by 2002:a9d:5d07:: with SMTP id b7mr2778080oti.368.1611702311956; Tue, 26 Jan 2021 15:05:11 -0800 (PST) Received: from serve.minyard.net (serve.minyard.net. [2001:470:b8f6:1b::1]) by smtp.gmail.com with ESMTPSA id g195sm75104oib.10.2021.01.26.15.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 15:05:11 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:2d17:e42b:3add:fd]) by serve.minyard.net (Postfix) with ESMTPSA id 7911C18055B; Tue, 26 Jan 2021 23:05:10 +0000 (UTC) Date: Tue, 26 Jan 2021 17:05:09 -0600 From: Corey Minyard To: Hao Wu Cc: peter.maydell@linaro.org, venture@google.com, hskinnemoen@google.com, qemu-devel@nongnu.org, kfting@nuvoton.com, qemu-arm@nongnu.org, Avi.Fishman@nuvoton.com, dje@google.com Subject: Re: [PATCH 4/6] hw/arm: Add I2C device tree for Quanta GSJ Message-ID: <20210126230509.GB2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-5-wuhaotsh@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210126193237.1534208-5-wuhaotsh@google.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=tcminyard@gmail.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 23:05:16 -0000 On Tue, Jan 26, 2021 at 11:32:35AM -0800, wuhaotsh--- via wrote: > Add an I2C device tree for Quanta GSJ. We only included devices with > existing QEMU implementation, including AT24 EEPROM and temperature > sensors. > > Reviewed-by: Doug Evans > Reviewed-by: Tyrong Ting > Signed-off-by: Hao Wu > --- > hw/arm/npcm7xx_boards.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c > index 2d82f48848..1418629e06 100644 > --- a/hw/arm/npcm7xx_boards.c > +++ b/hw/arm/npcm7xx_boards.c > @@ -19,6 +19,7 @@ > #include "exec/address-spaces.h" > #include "hw/arm/npcm7xx.h" > #include "hw/core/cpu.h" > +#include "hw/i2c/smbus_eeprom.h" > #include "hw/loader.h" > #include "hw/qdev-properties.h" > #include "qapi/error.h" > @@ -112,6 +113,21 @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc) > i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); > } > > +static void quanta_gsj_i2c_init(NPCM7xxState *soc) > +{ > + uint8_t *eeprom_buf0 = g_malloc0(32 * 1024); > + uint8_t *eeprom_buf1 = g_malloc0(32 * 1024); This is kind of pointless because the smbus eeprom is 256 bytes. It would be nice to modify the smbus eeprom code to take different sizes, if you want to submit a patch. -corey > + > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x48); > + smbus_eeprom_init_one(npcm7xx_i2c_get_bus(soc, 9), 0x55, eeprom_buf0); > + smbus_eeprom_init_one(npcm7xx_i2c_get_bus(soc, 10), 0x55, eeprom_buf1); > + > + /* TODO: Add addtional i2c devices. */ > +} > + > static void npcm750_evb_init(MachineState *machine) > { > NPCM7xxState *soc; > @@ -137,6 +153,7 @@ static void quanta_gsj_init(MachineState *machine) > npcm7xx_load_bootrom(machine, soc); > npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", > drive_get(IF_MTD, 0, 0)); > + quanta_gsj_i2c_init(soc); > npcm7xx_load_kernel(machine, soc); > } > > -- > 2.30.0.365.g02bc693789-goog > > From MAILER-DAEMON Tue Jan 26 18:47:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4Y3Y-0003rx-EA for mharc-qemu-arm@gnu.org; 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Tue, 26 Jan 2021 15:47:26 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:2d17:e42b:3add:fd]) by serve.minyard.net (Postfix) with ESMTPSA id F34401801B2; Tue, 26 Jan 2021 23:47:25 +0000 (UTC) Date: Tue, 26 Jan 2021 17:47:24 -0600 From: Corey Minyard To: Hao Wu Cc: peter.maydell@linaro.org, venture@google.com, hskinnemoen@google.com, qemu-devel@nongnu.org, kfting@nuvoton.com, qemu-arm@nongnu.org, Avi.Fishman@nuvoton.com, dje@google.com Subject: Re: [PATCH 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode Message-ID: <20210126234724.GC2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-7-wuhaotsh@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210126193237.1534208-7-wuhaotsh@google.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=tcminyard@gmail.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 23:47:31 -0000 On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote: > + > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) > +{ > + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > + > + if (received_bytes == 0) { > + npcm7xx_smbus_recv_fifo(s); > + return; > + } > + > + s->sda = s->rx_fifo[s->rx_cur]; > + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; > + --s->rxf_sts; This open-coded decrement seems a little risky. Are you sure in every case that s->rxf_sts > 0? There's no way what's running in the VM can game this and cause a buffer overrun? One caller to this function seems to protect against this, and another does not. Other than this, I didn't see any issues with this patch. -corey From MAILER-DAEMON Tue Jan 26 20:11:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4ZNF-0004Xm-O6 for mharc-qemu-arm@gnu.org; Tue, 26 Jan 2021 20:11:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <30b0QYAgKCJYMK70EJI76EE6B4.2ECG4CK-0HCDED6DK.EH6@flex--wuhaotsh.bounces.google.com>) id 1l4ZNA-0004Wm-Sm for qemu-arm@nongnu.org; Tue, 26 Jan 2021 20:11:53 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]:39675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <30b0QYAgKCJYMK70EJI76EE6B4.2ECG4CK-0HCDED6DK.EH6@flex--wuhaotsh.bounces.google.com>) id 1l4ZN7-0001eF-UD for qemu-arm@nongnu.org; Tue, 26 Jan 2021 20:11:52 -0500 Received: by mail-pj1-x1049.google.com with SMTP id t10so150994pjw.4 for ; Tue, 26 Jan 2021 17:11:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:message-id:mime-version:subject:from:to:cc; bh=CYEX7CEkLzQdqs4pMJDm4ewLslaQwNz5Up0FfqGNcqc=; b=slN3QB5ZyBQvCoFgPJ5OUpGvtfwH0lUOesuoir0crXVHGLdA66VsBFkomEFxOFb2R6 Ga+6VJvxr2qpgf16vkpCR2fZkLavQkmvfpkiaB+LXyTx9az36BUhEe+J+VSCmp1Ub8BW zAOiclf3b0Tg/nJbrG6oJn3YTIvstbQF/DwzaKt2Lnp45G4/kc9EsnixuTLtOTetd3wv COnKsRpfqp5YdY5ghxMYfNwVDwv1A4XKY/Z3zc4IQsYO5AJPIlpiWz9rE5JFu4uC5bf+ F6RW8roCKq3UQ4ZUtgTrucZf9Eb2U1Jq6+1Y9DMoYjiIPP2Q/MYEsnfemu2ey/DzNfSh co8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:message-id:mime-version:subject:from :to:cc; bh=CYEX7CEkLzQdqs4pMJDm4ewLslaQwNz5Up0FfqGNcqc=; b=b/KLCTBaChbEX3Iy4xOg7htjfQQq2valy/76Zz/hPSjD4Wk+i92AYktJBOfEEHn8Vx M4x1wIstZ48W/juiQJVyiTlbpA+MnhUOEsC2Oh0pnRdaJTIn972CHoU41Sn8omBLkj9O o6PWsz9Y5n7ETdWv8+77Eqh9fpluwAoZ2m3tTNQ6iBEQQtkAoGRq8Pgx9BP2bN6NleZC eaxptGd+huhDBLsZQVlkQXIiEUeh+mRnvipqaRgBKECGYDUPfmRKZrv+v5Qi8WCrhqvL OPivz42/cwZRZZqb7opSuL0Ra2OIf/WPgu1eqI0gvk5Sro8J9iNfAVt9hzyBkkPPAL9s q4Vw== X-Gm-Message-State: AOAM533w1hflRjT0e9TKXxD/HXbeZ1GBAXZakHTYS5t4w5sR7VgWiBjE efbsY4Mn3frkqr0Sclio/OoKNmAvFQ5K7g== X-Google-Smtp-Source: ABdhPJwznUEZj+z8rnLvfXQzOFxLYzXhUaSc9kJk+Y+SmW/4UAYa7/OZIG+jIigwyQzkaCwyJ0mgSnc9ehGdVw== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:902:d48a:b029:de:ae4d:2c7b with SMTP id c10-20020a170902d48ab02900deae4d2c7bmr8559923plg.62.1611709905391; Tue, 26 Jan 2021 17:11:45 -0800 (PST) Date: Tue, 26 Jan 2021 17:11:42 -0800 Message-Id: <20210127011142.2122790-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2] hw/misc: Fix arith overflow in NPCM7XX PWM module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-trivial@nongnu.org, wuhaotsh@google.com, hskinnemoen@google.com, f4bug@amsat.org, dje@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=30b0QYAgKCJYMK70EJI76EE6B4.2ECG4CK-0HCDED6DK.EH6@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 01:11:53 -0000 Fix potential overflow problem when calculating pwm_duty. 1. Ensure p->cmr and p->cnr to be from [0,65535], according to the hardware specification. 2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1) can excceed UINT32_MAX, we convert them to uint64_t in computation and converted them back to uint32_t. (duty is guaranteed to be <= MAX_DUTY so it won't overflow.) Fixes: CID 1442342 Suggested-by: Peter Maydell Reviewed-by: Doug Evans Signed-off-by: Hao Wu --- hw/misc/npcm7xx_pwm.c | 23 +++++++++++++++++++---- tests/qtest/npcm7xx_pwm-test.c | 4 ++-- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c index e99e3cc7ef..dabcb6c0f9 100644 --- a/hw/misc/npcm7xx_pwm.c +++ b/hw/misc/npcm7xx_pwm.c @@ -58,6 +58,9 @@ REG32(NPCM7XX_PWM_PWDR3, 0x50); #define NPCM7XX_CH_INV BIT(2) #define NPCM7XX_CH_MOD BIT(3) +#define NPCM7XX_MAX_CMR 65535 +#define NPCM7XX_MAX_CNR 65535 + /* Offset of each PWM channel's prescaler in the PPR register. */ static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 }; /* Offset of each PWM channel's clock selector in the CSR register. */ @@ -96,7 +99,7 @@ static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p) static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) { - uint64_t duty; + uint32_t duty; if (p->running) { if (p->cnr == 0) { @@ -104,7 +107,7 @@ static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) } else if (p->cmr >= p->cnr) { duty = NPCM7XX_PWM_MAX_DUTY; } else { - duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); + duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); } } else { duty = 0; @@ -357,7 +360,13 @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset, case A_NPCM7XX_PWM_CNR2: case A_NPCM7XX_PWM_CNR3: p = &s->pwm[npcm7xx_cnr_index(offset)]; - p->cnr = value; + if (value > NPCM7XX_MAX_CNR) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid cnr value: %u", __func__, value); + p->cnr = NPCM7XX_MAX_CNR; + } else { + p->cnr = value; + } npcm7xx_pwm_update_output(p); break; @@ -366,7 +375,13 @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset, case A_NPCM7XX_PWM_CMR2: case A_NPCM7XX_PWM_CMR3: p = &s->pwm[npcm7xx_cmr_index(offset)]; - p->cmr = value; + if (value > NPCM7XX_MAX_CMR) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid cmr value: %u", __func__, value); + p->cmr = NPCM7XX_MAX_CMR; + } else { + p->cmr = value; + } npcm7xx_pwm_update_output(p); break; diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c index 63557d2c06..3d82654b81 100644 --- a/tests/qtest/npcm7xx_pwm-test.c +++ b/tests/qtest/npcm7xx_pwm-test.c @@ -272,7 +272,7 @@ static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) { - uint64_t duty; + uint32_t duty; if (cnr == 0) { /* PWM is stopped. */ @@ -280,7 +280,7 @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) } else if (cmr >= cnr) { duty = MAX_DUTY; } else { - duty = MAX_DUTY * (cmr + 1) / (cnr + 1); + duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1); } if (inverted) { -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Wed Jan 27 06:20:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4isN-0001fZ-Ei for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 06:20:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4isL-0001dx-Pw; Wed, 27 Jan 2021 06:20:41 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4isI-00061Q-2s; Wed, 27 Jan 2021 06:20:41 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DQh2758xGz7bmk; Wed, 27 Jan 2021 19:19:11 +0800 (CST) Received: from [10.174.186.182] (10.174.186.182) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Wed, 27 Jan 2021 19:20:17 +0800 Subject: Re: [RFC PATCH v2 2/3] vfio: Set the priority of the VFIO VM state change handler explicitly To: Alex Williamson CC: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-3-lushenming@huawei.com> <20210126143605.4f9d5b25@omen.home.shazbot.org> From: Shenming Lu Message-ID: <153c36e0-3c7d-cbce-3f37-9ba8c36ce1ca@huawei.com> Date: Wed, 27 Jan 2021 19:20:06 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <20210126143605.4f9d5b25@omen.home.shazbot.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.186.182] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.35; envelope-from=lushenming@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 11:20:42 -0000 On 2021/1/27 5:36, Alex Williamson wrote: > On Wed, 9 Dec 2020 16:09:18 +0800 > Shenming Lu wrote: > >> In the VFIO VM state change handler, VFIO devices are transitioned >> in the _SAVING state, which should keep them from sending interrupts. > > Is this comment accurate? It's my expectation that _SAVING has no > bearing on a device generating interrupts. Interrupt generation must > be allowed to continue so long as the device is _RUNNING. Thanks, > To be more accurate, the _RUNNING bit in device_state is cleared in the VFIO VM state change handler when stopping the VM. And if the device continues to send interrupts after this, how can we save the states of device interrupts in the stop-and-copy phase?... Thanks, Shenming > Alex > >> Then we can save the pending states of all interrupts in the GIC VM >> state change handler (on ARM). >> >> So we have to set the priority of the VFIO VM state change handler >> explicitly (like virtio devices) to ensure it is called before the >> GIC's in saving. >> >> Signed-off-by: Shenming Lu >> Reviewed-by: Kirti Wankhede >> --- >> hw/vfio/migration.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c >> index 3b9de1353a..97ea82b100 100644 >> --- a/hw/vfio/migration.c >> +++ b/hw/vfio/migration.c >> @@ -862,7 +862,8 @@ static int vfio_migration_init(VFIODevice *vbasedev, >> register_savevm_live(id, VMSTATE_INSTANCE_ID_ANY, 1, &savevm_vfio_handlers, >> vbasedev); >> >> - migration->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change, >> + migration->vm_state = qdev_add_vm_change_state_handler(vbasedev->dev, >> + vfio_vmstate_change, >> vbasedev); >> migration->migration_state.notify = vfio_migration_state_notifier; >> add_migration_state_change_notifier(&migration->migration_state); > > . > From MAILER-DAEMON Wed Jan 27 06:28:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4izT-0004oq-I8 for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 06:28:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4izP-0004oT-8i; Wed, 27 Jan 2021 06:27:59 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2597) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4izI-0000yY-L1; Wed, 27 Jan 2021 06:27:59 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DQhBw2YdLzjCxF; Wed, 27 Jan 2021 19:26:48 +0800 (CST) Received: from [10.174.186.182] (10.174.186.182) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 27 Jan 2021 19:27:35 +0800 Subject: Re: [RFC PATCH v2 3/3] vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration To: Alex Williamson CC: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-4-lushenming@huawei.com> <20210126143614.175e271c@omen.home.shazbot.org> From: Shenming Lu Message-ID: <7e61e7ae-e351-4228-d250-660251dcb0c0@huawei.com> Date: Wed, 27 Jan 2021 19:27:35 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <20210126143614.175e271c@omen.home.shazbot.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.186.182] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=lushenming@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 11:27:59 -0000 On 2021/1/27 5:36, Alex Williamson wrote: > On Wed, 9 Dec 2020 16:09:19 +0800 > Shenming Lu wrote: > >> Different from the normal situation when the guest starts, we can >> know the max unmasked vetctor (at the beginning) after msix_load() >> in VFIO migration. So in order to avoid ineffectively disabling and > > s/ineffectively/inefficiently/? It's "effective" either way I think. Yeah, I should say "inefficiently". :-) > >> enabling vectors repeatedly, let's allocate all needed vectors first >> and then enable these unmasked vectors one by one without disabling. >> >> Signed-off-by: Shenming Lu >> --- >> hw/pci/msix.c | 17 +++++++++++++++++ >> hw/vfio/pci.c | 10 ++++++++-- >> include/hw/pci/msix.h | 2 ++ >> 3 files changed, 27 insertions(+), 2 deletions(-) >> >> diff --git a/hw/pci/msix.c b/hw/pci/msix.c >> index 67e34f34d6..bf291d3ff8 100644 >> --- a/hw/pci/msix.c >> +++ b/hw/pci/msix.c >> @@ -557,6 +557,23 @@ unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) >> return dev->msix_entries_nr; >> } >> >> +int msix_get_max_unmasked_vector(PCIDevice *dev) >> +{ >> + int max_unmasked_vector = -1; >> + int vector; >> + >> + if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & >> + (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { >> + for (vector = 0; vector < dev->msix_entries_nr; vector++) { >> + if (!msix_is_masked(dev, vector)) { >> + max_unmasked_vector = vector; >> + } >> + } >> + } >> + >> + return max_unmasked_vector; >> +} > > Comments from QEMU PCI folks? > >> + >> static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) >> { >> MSIMessage msg; >> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c >> index 51dc373695..e755ed2514 100644 >> --- a/hw/vfio/pci.c >> +++ b/hw/vfio/pci.c >> @@ -568,6 +568,9 @@ static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) >> >> static void vfio_msix_enable(VFIOPCIDevice *vdev) >> { >> + int max_unmasked_vector = msix_get_max_unmasked_vector(&vdev->pdev); >> + unsigned int used_vector = MAX(max_unmasked_vector, 0); >> + > > The above PCI function could also be done inline here pretty easily too: > > unsigned int nr, max_vec = 0; > > if (!msix_masked(&vdev->pdev)) > for (nr = 0; nr < msix_nr_vectors_allocated(&vdev->pdev); nr++) { > if (!msix_is_masked(&vdev->pdev, nr)) { > max_vec = nr; > } > } > } > > It's a bit cleaner than the msix utility function, imo. Yeah, it makes sense. > >> vfio_disable_interrupts(vdev); >> >> vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); >> @@ -586,9 +589,12 @@ static void vfio_msix_enable(VFIOPCIDevice *vdev) >> * triggering to userspace, then immediately release the vector, leaving >> * the physical device with no vectors enabled, but MSI-X enabled, just >> * like the guest view. >> + * If there are unmasked vectors (such as in migration) which will be >> + * enabled soon, we can allocate them here to avoid ineffectively disabling >> + * and enabling vectors repeatedly later. > > It just happens that migration triggers this usage model where the > MSI-X enable bit is set with vectors unmasked in the vector table, but > this is not unique to migration, guests can follow this pattern as well. > Has this been tested with a variety of guests? Logically it seems > correct, but always good to prove so. Thanks, I have tested it in migration and normal guest startup (only the latest Linux). And I can try to test with some other kernels, could you be more specific about this? Thanks, Shenming > > Alex > >> */ >> - vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); >> - vfio_msix_vector_release(&vdev->pdev, 0); >> + vfio_msix_vector_do_use(&vdev->pdev, used_vector, NULL, NULL); >> + vfio_msix_vector_release(&vdev->pdev, used_vector); >> >> if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, >> vfio_msix_vector_release, NULL)) { >> diff --git a/include/hw/pci/msix.h b/include/hw/pci/msix.h >> index 4c4a60c739..4bfb463fa6 100644 >> --- a/include/hw/pci/msix.h >> +++ b/include/hw/pci/msix.h >> @@ -23,6 +23,8 @@ void msix_uninit_exclusive_bar(PCIDevice *dev); >> >> unsigned int msix_nr_vectors_allocated(const PCIDevice *dev); >> >> +int msix_get_max_unmasked_vector(PCIDevice *dev); >> + >> void msix_save(PCIDevice *dev, QEMUFile *f); >> void msix_load(PCIDevice *dev, QEMUFile *f); >> > > . > From MAILER-DAEMON Wed Jan 27 07:46:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4kDZ-0006hE-87 for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 07:46:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4kDX-0006ff-Ja for qemu-arm@nongnu.org; Wed, 27 Jan 2021 07:46:39 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:31543) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4kDW-0004av-2a for qemu-arm@nongnu.org; Wed, 27 Jan 2021 07:46:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611751597; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CIwJVP8XTwkEwGc2lclH4Er1kq3hZ3+j54OcUbnlBHg=; b=Pzp+aeXxBmBYV7mntgSMpqCyPFpyp3RKg37/9H4tZ0t8fs1PzXgUZxFc3LA+6mJqMUe5Fk fhVG3RkQIq/mYHkVFAljZJgTzbuW3/O8RJccH/gA2Q4YRKs3F4A7WqQ+fiDoZT2s+tadAk CnCj2GpubBnI6HoO1a18lumBfAalzNs= Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-583-onFWom5jMHC4BuV1NUlJXg-1; Wed, 27 Jan 2021 07:46:35 -0500 X-MC-Unique: onFWom5jMHC4BuV1NUlJXg-1 Received: by mail-ej1-f71.google.com with SMTP id gt18so600220ejb.18 for ; Wed, 27 Jan 2021 04:46:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=CIwJVP8XTwkEwGc2lclH4Er1kq3hZ3+j54OcUbnlBHg=; b=NWHZK2Vg4Z+wpVZBTW60+WenHgNuGWWLAiKluTBQA3cNcjI9IMAS5gg7CdlABlMlrA HzI5CBgQ/R+96OL8kG7tUW35oEPojzlRIrme0Z46CA3cqwiBn6lFofhFiC1YrWbsupqy +OQZEWtu4d3eGi8PzPVQxlOcBnp+U2pNuJcv6m4n1ltIQOxzDWeisXwKpac8uHyJEeBS dwaoNuxH7mhrKi7tnLRHAypHsxEXKol0rdS5JZMtU7z0KN0nauotTfhCuftQc4lWi2kd ZoV27atmK2Pz9XXEzJIbsYCuds7ztEWU52Jh4elJGhAxLSyaDZIMHrBppoYQNCDBzHza 3niQ== X-Gm-Message-State: AOAM531yJmvKNxZvcL4qpFZ5C7WXqQFsdfN0qUtgfBoFe7RjeNAiDkOd HMm258jzX3OjZRDHHWNGAterjUTSgp+Hgm1HJjN55nqBMbqBxXFlOw+1vLDCzKE4ADBIrMDPGBP Tvz5PyWxVwcDJ X-Received: by 2002:a17:907:abc:: with SMTP id bz28mr6621379ejc.395.1611751594510; Wed, 27 Jan 2021 04:46:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJwoNhz1iXYRhUf4kCC7BjSULN/ZeQcsZzH2UDs+AKVcAfx8bgZUAv4L3XEkarx+Z1X5+Koukg== X-Received: by 2002:a17:907:abc:: with SMTP id bz28mr6621359ejc.395.1611751594318; Wed, 27 Jan 2021 04:46:34 -0800 (PST) Received: from ?IPv6:2001:b07:6468:f312:c8dd:75d4:99ab:290a? ([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id p27sm769172ejd.72.2021.01.27.04.46.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 04:46:33 -0800 (PST) Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: Keqian Zhu , Kirti Wankhede , Alex Williamson , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , "Dr . David Alan Gilbert" , Igor Mammedov , wanghaibin.wang@huawei.com, Zenghui Yu , jiangkunkun@huawei.com References: <20210111073439.20236-1-zhukeqian1@huawei.com> From: Paolo Bonzini Message-ID: Date: Wed, 27 Jan 2021 13:46:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210111073439.20236-1-zhukeqian1@huawei.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 12:46:39 -0000 On 11/01/21 08:34, Keqian Zhu wrote: > +static void vfio_listener_log_start(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, true); > +} > + > +static void vfio_listener_log_stop(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, false); > +} > + This would enable dirty page tracking also just for having a framebuffer (DIRTY_MEMORY_VGA). Technically it would be correct, but it would also be more heavyweight than expected. In order to only cover live migration, you can use the log_global_start and log_global_stop callbacks instead. If you want to use log_start and log_stop, you need to add respectively if (old != 0) { return; } and if (new != 0) { return; } before the calls to vfio_set_dirty_page_tracking. But I think it's more appropriate for VFIO to use log_global_*. Thanks, Paolo From MAILER-DAEMON Wed Jan 27 09:20:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4lgd-000576-27 for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 09:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4lgZ-00055A-Ng for qemu-arm@nongnu.org; Wed, 27 Jan 2021 09:20:44 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:30547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4lgQ-00050A-Nr for qemu-arm@nongnu.org; Wed, 27 Jan 2021 09:20:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611757233; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PV28gQcNZLdGQSNdPYf9VNAdRCWLVY3IDHnJ2TlKBBw=; b=OBeGAf0ICN02H8cJw9ye5jbtduSy8QRDNJ6xQHNoiD2256BpYcBpbRcuSFy0T7qkQIRpRC K1GTzlGXF5I8qR7i0BiQ5JEOiIaPcJP2lknERwHuiL+h0rz6DCZKs1HLnalg1PhGwPNF23 hY0CpJfo9ejKfziDDfb5jYgODh5xqL4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-23-G8w1Ljf8Pda-x4Y9QHHnAg-1; Wed, 27 Jan 2021 09:20:29 -0500 X-MC-Unique: G8w1Ljf8Pda-x4Y9QHHnAg-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BD7111014E63; Wed, 27 Jan 2021 14:20:27 +0000 (UTC) Received: from x1.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id DE9C360C62; Wed, 27 Jan 2021 14:20:20 +0000 (UTC) Date: Wed, 27 Jan 2021 07:20:14 -0700 From: Alex Williamson To: Shenming Lu Cc: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , Subject: Re: [RFC PATCH v2 2/3] vfio: Set the priority of the VFIO VM state change handler explicitly Message-ID: <20210127072014.6ed9ff04@x1.home.shazbot.org> In-Reply-To: <153c36e0-3c7d-cbce-3f37-9ba8c36ce1ca@huawei.com> References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-3-lushenming@huawei.com> <20210126143605.4f9d5b25@omen.home.shazbot.org> <153c36e0-3c7d-cbce-3f37-9ba8c36ce1ca@huawei.com> Organization: Red Hat MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 14:20:44 -0000 On Wed, 27 Jan 2021 19:20:06 +0800 Shenming Lu wrote: > On 2021/1/27 5:36, Alex Williamson wrote: > > On Wed, 9 Dec 2020 16:09:18 +0800 > > Shenming Lu wrote: > > > >> In the VFIO VM state change handler, VFIO devices are transitioned > >> in the _SAVING state, which should keep them from sending interrupts. > > > > Is this comment accurate? It's my expectation that _SAVING has no > > bearing on a device generating interrupts. Interrupt generation must > > be allowed to continue so long as the device is _RUNNING. Thanks, > > > > To be more accurate, the _RUNNING bit in device_state is cleared in the > VFIO VM state change handler when stopping the VM. And if the device continues > to send interrupts after this, how can we save the states of device interrupts > in the stop-and-copy phase?... Exactly, it's clearing the _RUNNING bit that makes the device stop, including no longer generating interrupts. Perhaps I incorrectly inferred "_SAVING state" as referring to the _SAVING bit when you actually intended: * +------- _RESUMING * |+------ _SAVING * ||+----- _RUNNING * ||| * 000b => Device Stopped, not saving or resuming * 001b => Device running, which is the default state -> * 010b => Stop the device & save the device state, stop-and-copy state ie. the full state when only _SAVING is set. Could we make the comment more clear to avoid this confusion? Thanks, Alex > >> Then we can save the pending states of all interrupts in the GIC VM > >> state change handler (on ARM). > >> > >> So we have to set the priority of the VFIO VM state change handler > >> explicitly (like virtio devices) to ensure it is called before the > >> GIC's in saving. > >> > >> Signed-off-by: Shenming Lu > >> Reviewed-by: Kirti Wankhede > >> --- > >> hw/vfio/migration.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c > >> index 3b9de1353a..97ea82b100 100644 > >> --- a/hw/vfio/migration.c > >> +++ b/hw/vfio/migration.c > >> @@ -862,7 +862,8 @@ static int vfio_migration_init(VFIODevice *vbasedev, > >> register_savevm_live(id, VMSTATE_INSTANCE_ID_ANY, 1, &savevm_vfio_handlers, > >> vbasedev); > >> > >> - migration->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change, > >> + migration->vm_state = qdev_add_vm_change_state_handler(vbasedev->dev, > >> + vfio_vmstate_change, > >> vbasedev); > >> migration->migration_state.notify = vfio_migration_state_notifier; > >> add_migration_state_change_notifier(&migration->migration_state); > > > > . > > > From MAILER-DAEMON Wed Jan 27 09:21:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4lhg-0005wi-T6 for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 09:21:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4lhf-0005vL-G0 for qemu-arm@nongnu.org; Wed, 27 Jan 2021 09:21:51 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:29398) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l4lhd-0005Wi-JZ for qemu-arm@nongnu.org; Wed, 27 Jan 2021 09:21:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611757308; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2Niz399/BYlmCEs5CQLjTynYv5WHBFXxlRWI3ExuFy4=; b=TXOqSWXpqj3YUbKCb8XV5gTj9sM8iA1qCCj0Lp3EY9ulLihFlDAJVchixBxk2l7dwmMOun 28GkKkN/V3+ClACZsuXn4wc+BetA1/o35Xh9yAmYt+U3RYomeiXefgW+0wg45BJFv2eaDS d3CsfSk6Uzzf4EmXBpbrP4+g+zxkkfE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-334-4IRsKCy-Mm-Ks42Vq8TlKw-1; Wed, 27 Jan 2021 09:21:47 -0500 X-MC-Unique: 4IRsKCy-Mm-Ks42Vq8TlKw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7B951801AA7; Wed, 27 Jan 2021 14:21:45 +0000 (UTC) Received: from x1.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9F4CD5D9CA; Wed, 27 Jan 2021 14:21:37 +0000 (UTC) Date: Wed, 27 Jan 2021 07:21:31 -0700 From: Alex Williamson To: Shenming Lu Cc: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , Subject: Re: [RFC PATCH v2 3/3] vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration Message-ID: <20210127072131.1c778247@x1.home.shazbot.org> In-Reply-To: <7e61e7ae-e351-4228-d250-660251dcb0c0@huawei.com> References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-4-lushenming@huawei.com> <20210126143614.175e271c@omen.home.shazbot.org> <7e61e7ae-e351-4228-d250-660251dcb0c0@huawei.com> Organization: Red Hat MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 14:21:51 -0000 On Wed, 27 Jan 2021 19:27:35 +0800 Shenming Lu wrote: > On 2021/1/27 5:36, Alex Williamson wrote: > > On Wed, 9 Dec 2020 16:09:19 +0800 > > Shenming Lu wrote: > > > >> Different from the normal situation when the guest starts, we can > >> know the max unmasked vetctor (at the beginning) after msix_load() > >> in VFIO migration. So in order to avoid ineffectively disabling and > > > > s/ineffectively/inefficiently/? It's "effective" either way I think. > > Yeah, I should say "inefficiently". :-) > > > > >> enabling vectors repeatedly, let's allocate all needed vectors first > >> and then enable these unmasked vectors one by one without disabling. > >> > >> Signed-off-by: Shenming Lu > >> --- > >> hw/pci/msix.c | 17 +++++++++++++++++ > >> hw/vfio/pci.c | 10 ++++++++-- > >> include/hw/pci/msix.h | 2 ++ > >> 3 files changed, 27 insertions(+), 2 deletions(-) > >> > >> diff --git a/hw/pci/msix.c b/hw/pci/msix.c > >> index 67e34f34d6..bf291d3ff8 100644 > >> --- a/hw/pci/msix.c > >> +++ b/hw/pci/msix.c > >> @@ -557,6 +557,23 @@ unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) > >> return dev->msix_entries_nr; > >> } > >> > >> +int msix_get_max_unmasked_vector(PCIDevice *dev) > >> +{ > >> + int max_unmasked_vector = -1; > >> + int vector; > >> + > >> + if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & > >> + (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { > >> + for (vector = 0; vector < dev->msix_entries_nr; vector++) { > >> + if (!msix_is_masked(dev, vector)) { > >> + max_unmasked_vector = vector; > >> + } > >> + } > >> + } > >> + > >> + return max_unmasked_vector; > >> +} > > > > Comments from QEMU PCI folks? > > > >> + > >> static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) > >> { > >> MSIMessage msg; > >> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c > >> index 51dc373695..e755ed2514 100644 > >> --- a/hw/vfio/pci.c > >> +++ b/hw/vfio/pci.c > >> @@ -568,6 +568,9 @@ static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) > >> > >> static void vfio_msix_enable(VFIOPCIDevice *vdev) > >> { > >> + int max_unmasked_vector = msix_get_max_unmasked_vector(&vdev->pdev); > >> + unsigned int used_vector = MAX(max_unmasked_vector, 0); > >> + > > > > The above PCI function could also be done inline here pretty easily too: > > > > unsigned int nr, max_vec = 0; > > > > if (!msix_masked(&vdev->pdev)) > > for (nr = 0; nr < msix_nr_vectors_allocated(&vdev->pdev); nr++) { > > if (!msix_is_masked(&vdev->pdev, nr)) { > > max_vec = nr; > > } > > } > > } > > > > It's a bit cleaner than the msix utility function, imo. > > Yeah, it makes sense. > > > > >> vfio_disable_interrupts(vdev); > >> > >> vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); > >> @@ -586,9 +589,12 @@ static void vfio_msix_enable(VFIOPCIDevice *vdev) > >> * triggering to userspace, then immediately release the vector, leaving > >> * the physical device with no vectors enabled, but MSI-X enabled, just > >> * like the guest view. > >> + * If there are unmasked vectors (such as in migration) which will be > >> + * enabled soon, we can allocate them here to avoid ineffectively disabling > >> + * and enabling vectors repeatedly later. > > > > It just happens that migration triggers this usage model where the > > MSI-X enable bit is set with vectors unmasked in the vector table, but > > this is not unique to migration, guests can follow this pattern as well. > > Has this been tested with a variety of guests? Logically it seems > > correct, but always good to prove so. Thanks, > > I have tested it in migration and normal guest startup (only the latest Linux). > And I can try to test with some other kernels, could you be more specific about this? Minimally also Windows, ideally a BSD as well. Thanks, Alex > >> */ > >> - vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); > >> - vfio_msix_vector_release(&vdev->pdev, 0); > >> + vfio_msix_vector_do_use(&vdev->pdev, used_vector, NULL, NULL); > >> + vfio_msix_vector_release(&vdev->pdev, used_vector); > >> > >> if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, > >> vfio_msix_vector_release, NULL)) { > >> diff --git a/include/hw/pci/msix.h b/include/hw/pci/msix.h > >> index 4c4a60c739..4bfb463fa6 100644 > >> --- a/include/hw/pci/msix.h > >> +++ b/include/hw/pci/msix.h > >> @@ -23,6 +23,8 @@ void msix_uninit_exclusive_bar(PCIDevice *dev); > >> > >> unsigned int msix_nr_vectors_allocated(const PCIDevice *dev); > >> > >> +int msix_get_max_unmasked_vector(PCIDevice *dev); > >> + > >> void msix_save(PCIDevice *dev, QEMUFile *f); > >> void msix_load(PCIDevice *dev, QEMUFile *f); > >> > > > > . > > > From MAILER-DAEMON Wed Jan 27 15:38:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4rZm-0007Ev-MW for mharc-qemu-arm@gnu.org; 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boundary="000000000000281d0d05b9e7bfa6" Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x12e.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 20:38:05 -0000 --000000000000281d0d05b9e7bfa6 Content-Type: text/plain; charset="UTF-8" On Tue, Jan 26, 2021 at 3:47 PM Corey Minyard wrote: > On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote: > > + > > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) > > +{ > > + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > > + > > + if (received_bytes == 0) { > > + npcm7xx_smbus_recv_fifo(s); > > + return; > > + } > > + > > + s->sda = s->rx_fifo[s->rx_cur]; > > + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; > > + --s->rxf_sts; > > This open-coded decrement seems a little risky. Are you sure in every > case that s->rxf_sts > 0? There's no way what's running in the VM can > game this and cause a buffer overrun? One caller to this function seems > to protect against this, and another does not. > s->rxf_sts is uint8_t so it's guaranteed to be >=0. In the case s->rxf_sts == 0, NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) is also 0, so it'll take the if-branch and return without running --s->rxf_sts. I'll probably add "g_assert(s->rxf_sts > 0)" to clarify. > > Other than this, I didn't see any issues with this patch. > > -corey > --000000000000281d0d05b9e7bfa6 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On = Tue, Jan 26, 2021 at 3:47 PM Corey Minyard <minyard@acm.org> wrote:
On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh---= via wrote:
> +
> +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s)
> +{
> +=C2=A0 =C2=A0 uint8_t received_bytes =3D NPCM7XX_SMBRXF_STS_RX_BYTES(= s->rxf_sts);
> +
> +=C2=A0 =C2=A0 if (received_bytes =3D=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 npcm7xx_smbus_recv_fifo(s);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 s->sda =3D s->rx_fifo[s->rx_cur];
> +=C2=A0 =C2=A0 s->rx_cur =3D (s->rx_cur + 1u) % NPCM7XX_SMBUS_FI= FO_SIZE;
> +=C2=A0 =C2=A0 --s->rxf_sts;

This open-coded decrement seems a little risky.=C2=A0 Are you sure in every=
case that s->rxf_sts > 0?=C2=A0 There's no way what's running= in the VM can
game this and cause a buffer overrun?=C2=A0 One caller to this function see= ms
to protect against this, and another does not.
s->r= xf_sts is uint8_t so it's guaranteed to be >=3D0.
In the c= ase s->rxf_sts =3D=3D 0,=C2=A0 NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts= ) is also 0, so it'll take the if-branch and return without running --s= ->rxf_sts.
I'll probably add "g_assert(s->rxf_sts = > 0)" to clarify.

Other than this, I didn't see any issues with this patch.

-corey
--000000000000281d0d05b9e7bfa6-- From MAILER-DAEMON Wed Jan 27 16:19:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4sDi-0005Q8-Vh for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:19:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4sDh-0005Q0-Hy for qemu-arm@nongnu.org; Wed, 27 Jan 2021 16:19:21 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:4577) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4sDf-00006Z-3j for qemu-arm@nongnu.org; Wed, 27 Jan 2021 16:19:21 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 27 Jan 2021 13:04:07 -0800 Received: from [10.40.102.156] (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Jan 2021 21:03:59 +0000 Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: Keqian Zhu , Alex Williamson , , CC: Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , "Dr . David Alan Gilbert" , "Igor Mammedov" , , Zenghui Yu , References: <20210111073439.20236-1-zhukeqian1@huawei.com> X-Nvconfidentiality: public From: Kirti Wankhede Message-ID: <590a2752-9bba-6971-51b0-a8accee6e814@nvidia.com> Date: Thu, 28 Jan 2021 02:33:55 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: <20210111073439.20236-1-zhukeqian1@huawei.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611781447; bh=SWA4c2DL1jtbVjyAynnMSN8GPaTlkiWjh97GtplZftE=; h=Subject:To:CC:References:X-Nvconfidentiality:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:Content-Type:Content-Language: Content-Transfer-Encoding:X-Originating-IP:X-ClientProxiedBy; b=C2OvG8fQl5TiwgTAiVfmKhE+tTXFFKTuwfcVjAGurIfhJU/ZxW72wf4fOA5BzXj0P GPkNyHlXCiY6VxhnpddTJOWvehnv3/GeZc0XkwVI0qKBIvuTGYOOvyt8VNq3GrI81C NGKlFEca6xQj3mNf3rUJ81E0F5K1xgJeUYcVlQz9w5MkFAAhIOEVIuzMfnD5B3T0MW dV6k2SLQ2m6RoRbRPBVOyHbV6s8o8t5KhwfiQ7SvwNZRMLkPXbNcSgGQRVsv4CnHVk 6nUfNrt9z0EoJ8kiKAaK+3yEq06nGqf+5OSdUeoIJOr+jOek1HIt+VSHmfoziM/PV5 i49ezNXWOsCEg== Received-SPF: pass client-ip=216.228.121.143; envelope-from=kwankhede@nvidia.com; helo=hqnvemgate24.nvidia.com X-Spam_score_int: -73 X-Spam_score: -7.4 X-Spam_bar: ------- X-Spam_report: (-7.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:19:21 -0000 On 1/11/2021 1:04 PM, Keqian Zhu wrote: > For now the switch of vfio dirty page tracking is integrated into > the vfio_save_handler, it causes some problems [1]. > Sorry, I missed [1] mail, somehow it didn't landed in my inbox. > The object of dirty tracking is guest memory, but the object of > the vfio_save_handler is device state. This mixed logic produces > unnecessary coupling and conflicts: > > 1. Coupling: Their saving granule is different (perVM vs perDevice). > vfio will enable dirty_page_tracking for each devices, actually > once is enough. That's correct, enabling dirty page tracking once is enough. But log_start and log_stop gets called on address space update transaction, region_add() or region_del(), at this point migration may not be active. We don't want to allocate bitmap memory in kernel for lifetime of VM, without knowing migration will be happen or not. vfio_iommu_type1 module should allocate bitmap memory only while migration is active. Paolo's suggestion here to use log_global_start and log_global_stop callbacks seems correct here. But at this point vfio device state is not yet changed to |_SAVING as you had identified it in [1]. May be we can start tracking bitmap in iommu_type1 module while device is not yet _SAVING, but getting dirty bitmap while device is yet not in _SAVING|_RUNNING state doesn't seem optimal solution. Pasting here your question from [1] > Before start dirty tracking, we will check and ensure that the device > is at _SAVING state and return error otherwise. But the question is > that what is the rationale? Why does the VFIO_IOMMU_DIRTY_PAGES > ioctl have something to do with the device state? Lets walk through the types of devices we are supporting: 1. mdev devices without IOMMU backed device Vendor driver pins pages as and when required during runtime. We can say that vendor driver is smart which identifies the pages to pin. We are good here. 2. mdev device with IOMMU backed device This is similar to vfio-pci, direct assigned device, where all pages are pinned at VM bootup. Vendor driver is not smart, so bitmap query will report all pages dirty always. If --auto-converge is not set, VM stucks infinitely in pre-copy phase. This is known to us. 3. mdev device with IOMMU backed device with smart vendor driver In this case as well all pages are pinned at VM bootup, but vendor driver is smart to identify the pages and pin them explicitly. Pages can be pinned anytime, i.e. during normal VM runtime or on setting _SAVING flag (entering pre-copy phase) or while in iterative pre-copy phase. There is no restriction based on these phases for calling vfio_pin_pages(). Vendor driver can start pinning pages based on its device state when _SAVING flag is set. In that case, if dirty bitmap is queried before that then it will report all sysmem as dirty with an unnecessary copy of sysmem. As an optimal solution, I think its better to query bitmap only after all vfio devices are in pre-copy phase, i.e. after _SAVING flag is set. > 2. Conflicts: The ram_save_setup() traverses all memory_listeners > to execute their log_start() and log_sync() hooks to get the > first round dirty bitmap, which is used by the bulk stage of > ram saving. However, it can't get dirty bitmap from vfio, as > @savevm_ram_handlers is registered before @vfio_save_handler. > Right, but it can get dirty bitmap from vfio device in it's iterative callback ram_save_pending -> migration_bitmap_sync_precopy() .. -> vfio_listerner_log_sync Thanks, Kirti > Move the switch of vfio dirty_page_tracking into vfio_memory_listener > can solve above problems. Besides, Do not require devices in SAVING > state for vfio_sync_dirty_bitmap(). > > [1] https://www.spinics.net/lists/kvm/msg229967.html > > Reported-by: Zenghui Yu > Signed-off-by: Keqian Zhu > --- > hw/vfio/common.c | 53 +++++++++++++++++++++++++++++++++++++-------- > hw/vfio/migration.c | 35 ------------------------------ > 2 files changed, 44 insertions(+), 44 deletions(-) > > diff --git a/hw/vfio/common.c b/hw/vfio/common.c > index 6ff1daa763..9128cd7ee1 100644 > --- a/hw/vfio/common.c > +++ b/hw/vfio/common.c > @@ -311,7 +311,7 @@ bool vfio_mig_active(void) > return true; > } > > -static bool vfio_devices_all_saving(VFIOContainer *container) > +static bool vfio_devices_all_dirty_tracking(VFIOContainer *container) > { > VFIOGroup *group; > VFIODevice *vbasedev; > @@ -329,13 +329,8 @@ static bool vfio_devices_all_saving(VFIOContainer *container) > return false; > } > > - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { > - if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) > - && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { > - return false; > - } > - continue; > - } else { > + if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) > + && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { > return false; > } > } > @@ -987,6 +982,44 @@ static void vfio_listener_region_del(MemoryListener *listener, > } > } > > +static void vfio_set_dirty_page_tracking(VFIOContainer *container, bool start) > +{ > + int ret; > + struct vfio_iommu_type1_dirty_bitmap dirty = { > + .argsz = sizeof(dirty), > + }; > + > + if (start) { > + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; > + } else { > + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; > + } > + > + ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); > + if (ret) { > + error_report("Failed to set dirty tracking flag 0x%x errno: %d", > + dirty.flags, errno); > + } > +} > + > +static void vfio_listener_log_start(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, true); > +} > + > +static void vfio_listener_log_stop(MemoryListener *listener, > + MemoryRegionSection *section, > + int old, int new) > +{ > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > + > + vfio_set_dirty_page_tracking(container, false); > +} > + > static int vfio_get_dirty_bitmap(VFIOContainer *container, uint64_t iova, > uint64_t size, ram_addr_t ram_addr) > { > @@ -1128,7 +1161,7 @@ static void vfio_listerner_log_sync(MemoryListener *listener, > return; > } > > - if (vfio_devices_all_saving(container)) { > + if (vfio_devices_all_dirty_tracking(container)) { > vfio_sync_dirty_bitmap(container, section); > } > } > @@ -1136,6 +1169,8 @@ static void vfio_listerner_log_sync(MemoryListener *listener, > static const MemoryListener vfio_memory_listener = { > .region_add = vfio_listener_region_add, > .region_del = vfio_listener_region_del, > + .log_start = vfio_listener_log_start, > + .log_stop = vfio_listener_log_stop, > .log_sync = vfio_listerner_log_sync, > }; > > diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c > index 00daa50ed8..c0f646823a 100644 > --- a/hw/vfio/migration.c > +++ b/hw/vfio/migration.c > @@ -395,40 +395,10 @@ static int vfio_load_device_config_state(QEMUFile *f, void *opaque) > return qemu_file_get_error(f); > } > > -static int vfio_set_dirty_page_tracking(VFIODevice *vbasedev, bool start) > -{ > - int ret; > - VFIOMigration *migration = vbasedev->migration; > - VFIOContainer *container = vbasedev->group->container; > - struct vfio_iommu_type1_dirty_bitmap dirty = { > - .argsz = sizeof(dirty), > - }; > - > - if (start) { > - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { > - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; > - } else { > - return -EINVAL; > - } > - } else { > - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; > - } > - > - ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); > - if (ret) { > - error_report("Failed to set dirty tracking flag 0x%x errno: %d", > - dirty.flags, errno); > - return -errno; > - } > - return ret; > -} > - > static void vfio_migration_cleanup(VFIODevice *vbasedev) > { > VFIOMigration *migration = vbasedev->migration; > > - vfio_set_dirty_page_tracking(vbasedev, false); > - > if (migration->region.mmaps) { > vfio_region_unmap(&migration->region); > } > @@ -469,11 +439,6 @@ static int vfio_save_setup(QEMUFile *f, void *opaque) > return ret; > } > > - ret = vfio_set_dirty_page_tracking(vbasedev, true); > - if (ret) { > - return ret; > - } > - > qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE); > > ret = qemu_file_get_error(f); > From MAILER-DAEMON Wed Jan 27 16:43:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4saf-0001XE-Pl for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:43:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4saZ-0001Vq-L8; Wed, 27 Jan 2021 16:43:01 -0500 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]:33869) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4saX-0002sL-Pw; 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Wed, 27 Jan 2021 13:42:54 -0800 (PST) Received: from serve.minyard.net ([47.184.170.156]) by smtp.gmail.com with ESMTPSA id d3sm682676ooi.42.2021.01.27.13.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 13:42:53 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:84df:dff0:9fb7:e686]) by serve.minyard.net (Postfix) with ESMTPSA id 8D06818055B; Wed, 27 Jan 2021 21:42:52 +0000 (UTC) Date: Wed, 27 Jan 2021 15:42:51 -0600 From: Corey Minyard To: Hao Wu Cc: Peter Maydell , Patrick Venture , QEMU Developers , Havard Skinnemoen , CS20 KFTing , qemu-arm , IS20 Avi Fishman , Doug Evans Subject: Re: [PATCH 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode Message-ID: <20210127214251.GE2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-7-wuhaotsh@google.com> <20210126234724.GC2057975@minyard.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=tcminyard@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:43:01 -0000 On Wed, Jan 27, 2021 at 12:37:46PM -0800, wuhaotsh--- via wrote: > On Tue, Jan 26, 2021 at 3:47 PM Corey Minyard wrote: > > > On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote: > > > + > > > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) > > > +{ > > > + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > > > + > > > + if (received_bytes == 0) { > > > + npcm7xx_smbus_recv_fifo(s); > > > + return; > > > + } > > > + > > > + s->sda = s->rx_fifo[s->rx_cur]; > > > + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; > > > + --s->rxf_sts; > > > > This open-coded decrement seems a little risky. Are you sure in every > > case that s->rxf_sts > 0? There's no way what's running in the VM can > > game this and cause a buffer overrun? One caller to this function seems > > to protect against this, and another does not. > > > s->rxf_sts is uint8_t so it's guaranteed to be >=0. > In the case s->rxf_sts == 0, NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) is > also 0, so it'll take the if-branch and return without running --s->rxf_sts. That is true if called from the NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE case. There is no such check in the NPCM7XX_SMBUS_STATUS_RECEIVING case. > I'll probably add "g_assert(s->rxf_sts > 0)" to clarify. You never want to do an assert if the hosted system can do something to cause it. If you add the check to the NPCM7XX_SMBUS_STATUS_RECEIVING case, it would be ok, but really unnecessary. If it's fine if s->rxf_sts wraps to 0xff, then this all doesn't matter, but you want to add a comment to that effect if so. These sorts of things look dangerous. There is also the question about who takes these patches in. I'm the I2C maintainer, but there's other code in this series. Once everything is ready, I can ack them if we take it through the ARM tree. Or I can take it through my tree with the proper acks. -corey > > > > > Other than this, I didn't see any issues with this patch. > > > > -corey > > From MAILER-DAEMON Wed Jan 27 16:53:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4skQ-00012J-Rb for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:53:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4skO-0000zt-G2; Wed, 27 Jan 2021 16:53:08 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:6821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4skM-0004K3-6f; Wed, 27 Jan 2021 16:53:07 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 27 Jan 2021 13:53:03 -0800 Received: from [10.40.102.156] (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Jan 2021 21:52:50 +0000 Subject: Re: [RFC PATCH v2 1/3] vfio: Move the saving of the config space to the right place in VFIO migration To: Alex Williamson , Shenming Lu CC: Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-2-lushenming@huawei.com> <20201209132947.3177f130.cohuck@redhat.com> <20201209113431.5b252e93@omen.home> <3f7db9e7-3c98-5022-e907-e6214815fae9@huawei.com> <20210126143602.0dac239f@omen.home.shazbot.org> X-Nvconfidentiality: public From: Kirti Wankhede Message-ID: Date: Thu, 28 Jan 2021 03:22:47 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: <20210126143602.0dac239f@omen.home.shazbot.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611784383; bh=3fB8raZFnOV40ct2MT96BSTKTS97g8mPuG6zACe83OI=; h=Subject:To:CC:References:X-Nvconfidentiality:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:Content-Type:Content-Language: Content-Transfer-Encoding:X-Originating-IP:X-ClientProxiedBy; b=bJQ9y4em+YLwADcav8HG7l05fmna51NfccQ0L4x7cbspCnz881ufv2NqMNsUR7gfN EnMYhvsKjUxLsKAXYdkF5pB9oT8O0CyoXBPwOHahHgD65X8ls8XS8A4+kGv4n3KE1U DgDUHwkNFUYZ4/q6cd99sIquaKobTMuKTeXeOrBDaTI2AKkqfp54v4MnOq1tVWJL57 38FL48w36xKxYmIwZn9OVNA1NTLGOkN97rHsZxuJNDX8dgDsIUnAempn0yTEcLdr49 p0EA7tqvgy5Yi2BFNgOjP/uROwR5dco8jAG4a8+i24i5oIQLG8rQoiXwz3SGNzb6Sb iuNA7b/sQe0eA== Received-SPF: pass client-ip=216.228.121.143; envelope-from=kwankhede@nvidia.com; helo=hqnvemgate24.nvidia.com X-Spam_score_int: -73 X-Spam_score: -7.4 X-Spam_bar: ------- X-Spam_report: (-7.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:53:08 -0000 On 1/27/2021 3:06 AM, Alex Williamson wrote: > On Thu, 10 Dec 2020 10:21:21 +0800 > Shenming Lu wrote: > >> On 2020/12/10 2:34, Alex Williamson wrote: >>> On Wed, 9 Dec 2020 13:29:47 +0100 >>> Cornelia Huck wrote: >>> >>>> On Wed, 9 Dec 2020 16:09:17 +0800 >>>> Shenming Lu wrote: >>>> >>>>> On ARM64 the VFIO SET_IRQS ioctl is dependent on the VM interrupt >>>>> setup, if the restoring of the VFIO PCI device config space is >>>>> before the VGIC, an error might occur in the kernel. >>>>> >>>>> So we move the saving of the config space to the non-iterable >>>>> process, so that it will be called after the VGIC according to >>>>> their priorities. >>>>> >>>>> As for the possible dependence of the device specific migration >>>>> data on it's config space, we can let the vendor driver to >>>>> include any config info it needs in its own data stream. >>>>> (Should we note this in the header file linux-headers/linux/vfio.h?) >>>> >>>> Given that the header is our primary source about how this interface >>>> should act, we need to properly document expectations about what will >>>> be saved/restored when there (well, in the source file in the kernel.) >>>> That goes in both directions: what a userspace must implement, and what >>>> a vendor driver can rely on. >> >> Yeah, in order to make the vendor driver and QEMU cooperate better, we might >> need to document some expectations about the data section in the migration >> region... >>>> >>>> [Related, but not a todo for you: I think we're still missing proper >>>> documentation of the whole migration feature.] >>> >>> Yes, we never saw anything past v1 of the documentation patch. Thanks, >>> >> >> By the way, is there anything unproper with this patch? Wish your suggestion. :-) > > I'm really hoping for some feedback from Kirti, I understand the NVIDIA > vGPU driver to have some dependency on this. Thanks, > I need to verify this patch. Spare me a day to verify this. Thanks, Kirti > Alex > >>>>> Signed-off-by: Shenming Lu >>>>> --- >>>>> hw/vfio/migration.c | 25 +++++++++++++++---------- >>>>> 1 file changed, 15 insertions(+), 10 deletions(-) >>> >>> . >>> >> > From MAILER-DAEMON Wed Jan 27 16:54:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4slY-00029N-Ls for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:54:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4slQ-00026e-2S; Wed, 27 Jan 2021 16:54:12 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:37998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4slO-0004OV-Ew; Wed, 27 Jan 2021 16:54:11 -0500 Received: by mail-wm1-x32d.google.com with SMTP id y187so2909960wmd.3; Wed, 27 Jan 2021 13:54:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=On9OY9uCLuCBNzOxWP54fsp2GjDNAkYk/TSaplVUQNM=; b=jWa7QoHa5yGk/gNnns4Ckx5YgfVsR3JMwWbtzoR3WC92wO3FDdQ1Z4qznHcO3wGEWm rHuU8C6Hmthe7hX6l3tcml+kyCE7GniMA+dCrU2JxnBBiy6lXVTbZr8iQ5TrlUJFMGvS 0DilJl0cfzSUYe/fx3SYOf94SomnIWO73evv0NJWvqL1QTXYTB3GIMtyWxdyzWOv+Inb xIEEqh+HQBiLj2HTX8HWF8sV/DRZTV10kpRBPQsKX70GoiDc2gfSkDyAcvGGdydDdFhO 92m1Pm+wfxAaXFJ5hD8rowF7ildPwg6E6JdKcyFmQTb7SLrmKpto30366JNZ8sq9L5qR bkOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=On9OY9uCLuCBNzOxWP54fsp2GjDNAkYk/TSaplVUQNM=; b=izybi0XAoKPyetNwTxKKAPgMVBj0RLLwZKByvSP7YyrgKW/B9+SfOYIFgHQ4oytJey MBuE/sMcWgXiJBo8Az0/MY+lukiOPA2rA8HyoZlJi3TSh2GNa4gCGkO81PrxVJpRNYy6 weDU4facUOS+UoaEvlLxRWO6KCvweMpXwRSvHzP8mqojC1x4NmnohMHbHi2d15UhZbMc zkgdA5PNZDhr0TVNOpEhipELSDssqw30QLQ0/Fg8AvLisn49R/oVXDYO6oH+VEgDHHMp VcLEVbiKohRArGTo13toKliedU7GiCrENVFcY0mv7gMQODgYCWx67E3zpr5YQsT7hPcq tFAQ== X-Gm-Message-State: AOAM532BJh5kz6D8VFr/DfiYvNcVwme9VvhD64Vdw5Ku4f/I6CO8Ayda S2p2jyZDg1TtFRuYVQIKztk= X-Google-Smtp-Source: ABdhPJyHKSxJhwlqml9962W8mcneMr/OyAapH8kpi0wuasdexIFZLY2FNloBamdxi6CuIvict5AaJA== X-Received: by 2002:a1c:df04:: with SMTP id w4mr5685493wmg.66.1611784448710; Wed, 27 Jan 2021 13:54:08 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z4sm4482159wrw.38.2021.01.27.13.54.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 13:54:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-5-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 27 Jan 2021 22:54:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:54:12 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Add a simple test of the CMSDK watchdog, since we're about to do some > refactoring of how it is clocked. > > Signed-off-by: Peter Maydell > --- > tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 82 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 16:57:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4soB-0004NZ-Qk for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:57:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4so7-0004M9-Pm; Wed, 27 Jan 2021 16:57:01 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44442) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4so1-0004ei-Ly; Wed, 27 Jan 2021 16:56:58 -0500 Received: by mail-wr1-x42f.google.com with SMTP id d16so3423159wro.11; Wed, 27 Jan 2021 13:56:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sOqH3ausLFrKn5ovRJAgVsa8REkaF6VtAspx+wVS2rA=; b=nVd3ba0z8GAeDqOfO33sTo3i2I5K/oYXVgu8BBxX2C1PkR+uW1U0A5F6z98vbsfVL8 SAg1COmSNXFlJ6IKxMPGqFefnFuvUeHfMfz/f5RGVrrvC5yr1QjXRCAFqMZN4d6yVkYF xyW4nTREvkSIl+TzNBbISWBVXDJnbvPwTqWI7rBxtpx3u49Zn+QuqM399FXYQfFWTkPr A1q2EZgf0XrnY2pSCpHlGqice2fpm7OtRtx1nesi/RFdrWkPCH1JIvcn27in+S2yeZz+ pi/YMiee7RPljgYOq+WxecbGWkl8LpXYvUpQLM+4J6Ehpd8Dtj0QVDlkA9QeSn5MtIT5 KK5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=sOqH3ausLFrKn5ovRJAgVsa8REkaF6VtAspx+wVS2rA=; b=fKwkS9NmbL7WfSWCxqpvhyCTfvikZGlWkPEcl+Vg7Bf2YqWXmO1VK/RDZAO+Hcxw3Q z5pU7iDW/4Pr8F6a4/NZrOvpdVu5xKJNCMLoi0R16MTM6pl/FNe0C9eECTBMlDOK4eVw Yc8PRHhiWUblrAY+nJ7xvE/UZxi888aIcNltDclqAT8c+SAShwg31/DxKgVY4Q4gIoy0 b/LpG+M06KkXSFXW/5U0pUzy+/R4O6zJTLsEi/cHsfYDFXF0vITq38CcjBxOyjhUmJWB Fe1YHNvdn/1tQQpA5VT3RLN3ok8uUdbxOjPkqTLFgEHAt08RXBIJYXK261AELkmNnbJY Kxag== X-Gm-Message-State: AOAM533kBGW5sxQune4BfrLGvroefYh5uYTkv17tkdhwaoqM6LVDHBey k0tl07SnJl9URqzfWUN/1ipjDsDImBc= X-Google-Smtp-Source: ABdhPJz0VyH3gljvUsHwTVkG7hpp58xfAizjxZqQMnzw7xfSK/KyIoF539aHHKWGx2L4Ung0xiV1ig== X-Received: by 2002:a5d:55c6:: with SMTP id i6mr13572646wrw.145.1611784611650; Wed, 27 Jan 2021 13:56:51 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z63sm3724567wme.8.2021.01.27.13.56.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 13:56:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 02/25] clock: Add new clock_has_source() function To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-3-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1917a3bd-4b4c-e4f8-1c0e-9efef18d80f4@amsat.org> Date: Wed, 27 Jan 2021 22:56:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:57:03 -0000 On 1/21/21 8:05 PM, Peter Maydell wrote: > Add a function for checking whether a clock has a source. This is > useful for devices which have input clocks that must be wired up by > the board as it allows them to fail in realize rather than ploughing > on with a zero-period clock. > > Signed-off-by: Peter Maydell > --- > docs/devel/clocks.rst | 16 ++++++++++++++++ > include/hw/clock.h | 15 +++++++++++++++ > 2 files changed, 31 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 16:59:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4sqS-000717-QL for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 16:59:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4sqR-0006yw-5V for qemu-arm@nongnu.org; Wed, 27 Jan 2021 16:59:23 -0500 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]:35440) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4sqP-0004wY-7m for qemu-arm@nongnu.org; Wed, 27 Jan 2021 16:59:22 -0500 Received: by mail-lf1-x136.google.com with SMTP id u25so4853603lfc.2 for ; Wed, 27 Jan 2021 13:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=c/AUicp4Jps+a+9iFuaHW/434K31+hit+WIM8bi5iNg=; b=hOYn4ET9Rtc0sKJnhX2FLqJ58EIfMUG7GMWemfuBVsazwkUMJupcqAOuz9aZig+sn1 Vn5JUHjL+QNtz8vizcDMrjq3afuoNzACp3n/2aTWRZgYBhulWlxRkHkcCsN/wVm7JnBl hRDAd7Ge8JEDr9vrrW2P7UCv3TvQCB3AWMrIAHKJwvDTxLjUf3lT1BYHd6KU3glc808C OXEUdSy/4kmQIf8ywwr7QDFhgCeAhbsmlEmr4faUhnMAZfT12pwOyzTQg1JGJswGn66P OAI9nz+YEp3+ZkZZta+Of14YnbaturaX3I/2vtv068lDj+pYk4ujzrAB98aFAdb8/uwJ BEnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=c/AUicp4Jps+a+9iFuaHW/434K31+hit+WIM8bi5iNg=; b=rcMPfycdvDg6CveKS7Gn3T+mini2UoE2tqXKMx+gWnVIjQQLp0vJVEfBgPZdE2YJ03 YP7VTDcaJqToEDGmjdb6RIz4b6yD3hsfZe7kGgbgBtED+4qdrAgkNldrOGtZgXNoozZr fIk6kpCY4q5Ua8uiSCPeq1XodV/W/O89zD6b6B5ZIzO2cflbtdi94OAmZuxbG6jnwO8K qdSFPT2ilWIF0btZdOjHQaePjMyBCAB+6het2uGBdxOzTguw9RvI3McdLrlejnjgeqeH ReYGaRj+/LnLfjwPjbRIkvMX+lTHy56+6tdgvF12a1l/b59tb2bTsu7fR9PA9Yn56h0V QvRA== X-Gm-Message-State: AOAM532WfxEeUnvK0LCCEXQ+68u8qnSwmNYUgAHnP3cbDL7yaotXKRUo blWYEIN9bQv19A5mwi4xb/+zRGuxj39ANhELrUw7Ag== X-Google-Smtp-Source: ABdhPJxYhD7PahV1vyhen0uFbsnKQh1EQdGYnGMcg8uk8H9oSEX8/5Xc4JYToNzIpkJBGpmE8AgUZm33XnV9low0jYk= X-Received: by 2002:a19:5052:: with SMTP id z18mr6101504lfj.554.1611784759112; Wed, 27 Jan 2021 13:59:19 -0800 (PST) MIME-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-7-wuhaotsh@google.com> <20210126234724.GC2057975@minyard.net> <20210127214251.GE2057975@minyard.net> In-Reply-To: <20210127214251.GE2057975@minyard.net> From: Hao Wu Date: Wed, 27 Jan 2021 13:59:07 -0800 Message-ID: Subject: Re: [PATCH 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode To: Corey Minyard Cc: Peter Maydell , Patrick Venture , QEMU Developers , Havard Skinnemoen , CS20 KFTing , qemu-arm , IS20 Avi Fishman , Doug Evans Content-Type: multipart/alternative; boundary="00000000000005e1db05b9e8e2b7" Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 21:59:23 -0000 --00000000000005e1db05b9e8e2b7 Content-Type: text/plain; charset="UTF-8" On Wed, Jan 27, 2021 at 1:42 PM Corey Minyard wrote: > On Wed, Jan 27, 2021 at 12:37:46PM -0800, wuhaotsh--- via wrote: > > On Tue, Jan 26, 2021 at 3:47 PM Corey Minyard wrote: > > > > > On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote: > > > > + > > > > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) > > > > +{ > > > > + uint8_t received_bytes = > NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > > > > + > > > > + if (received_bytes == 0) { > > > > + npcm7xx_smbus_recv_fifo(s); > > > > + return; > > > > + } > > > > + > > > > + s->sda = s->rx_fifo[s->rx_cur]; > > > > + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; > > > > + --s->rxf_sts; > > > > > > This open-coded decrement seems a little risky. Are you sure in every > > > case that s->rxf_sts > 0? There's no way what's running in the VM can > > > game this and cause a buffer overrun? One caller to this function > seems > > > to protect against this, and another does not. > > > > > s->rxf_sts is uint8_t so it's guaranteed to be >=0. > > In the case s->rxf_sts == 0, NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) is > > also 0, so it'll take the if-branch and return without running > --s->rxf_sts. > > That is true if called from the > NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE case. There is no such check > in the NPCM7XX_SMBUS_STATUS_RECEIVING case. > I don't understand the reasoning here. The caller doesn't matter. Previous code has: #define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) So uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); is guaranteed to be 0 if s->rxf_sts == 0. As a result the code will take the following branch and returns: if (received_bytes == 0) { npcm7xx_smbus_recv_fifo(s); return; } And will not execute the --s->rxf_sts sentence. Please let me know if I missed anything here. > > > I'll probably add "g_assert(s->rxf_sts > 0)" to clarify. > > You never want to do an assert if the hosted system can do something to > cause it. If you add the check to the NPCM7XX_SMBUS_STATUS_RECEIVING > case, it would be ok, but really unnecessary. > > If it's fine if s->rxf_sts wraps to 0xff, then this all doesn't matter, > but you want to add a comment to that effect if so. These sorts of > things look dangerous. > > There is also the question about who takes these patches in. I'm the > I2C maintainer, but there's other code in this series. Once everything > is ready, I can ack them if we take it through the ARM tree. Or I can > take it through my tree with the proper acks. > I think either way is fine. Previous NPCM7XX patch series were taken in the ARM tree. But as i2c code taking into your tree is also fine. > > -corey > > > > > > > > > Other than this, I didn't see any issues with this patch. > > > > > > -corey > > > > --00000000000005e1db05b9e8e2b7 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Jan 27, 2021 at 1:42 PM Corey= Minyard <minyard@a= cm.org> wrote:
On Wed, Jan 27, 2021 at 12:37:46PM -0800, wuhaotsh--- via wrote:
> On Tue, Jan 26, 2021 at 3:47 PM Corey Minyard <minyard@acm.org> wrote:
>
> > On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote:<= br> > > > +
> > > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState = *s)
> > > +{
> > > +=C2=A0 =C2=A0 uint8_t received_bytes =3D NPCM7XX_SMBRXF_STS= _RX_BYTES(s->rxf_sts);
> > > +
> > > +=C2=A0 =C2=A0 if (received_bytes =3D=3D 0) {
> > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 npcm7xx_smbus_recv_fifo(s);
> > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> > > +=C2=A0 =C2=A0 }
> > > +
> > > +=C2=A0 =C2=A0 s->sda =3D s->rx_fifo[s->rx_cur]; > > > +=C2=A0 =C2=A0 s->rx_cur =3D (s->rx_cur + 1u) % NPCM7X= X_SMBUS_FIFO_SIZE;
> > > +=C2=A0 =C2=A0 --s->rxf_sts;
> >
> > This open-coded decrement seems a little risky.=C2=A0 Are you sur= e in every
> > case that s->rxf_sts > 0?=C2=A0 There's no way what'= ;s running in the VM can
> > game this and cause a buffer overrun?=C2=A0 One caller to this fu= nction seems
> > to protect against this, and another does not.
> >
> s->rxf_sts is uint8_t so it's guaranteed to be >=3D0.
> In the case s->rxf_sts =3D=3D 0,=C2=A0 NPCM7XX_SMBRXF_STS_RX_BYTES(= s->rxf_sts) is
> also 0, so it'll take the if-branch and return without running --s= ->rxf_sts.

That is true if called from the
NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE case.=C2=A0 There is no such che= ck
in the NPCM7XX_SMBUS_STATUS_RECEIVING case.
I don'= t understand the reasoning here. The caller doesn't matter.
P= revious code has:
=C2=A0#define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) = =C2=A0 =C2=A0 extract8((rv), 0, 5)=C2=A0
So=C2=A0
=C2= =A0uint8_t received_bytes =3D NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts);
is guaranteed to be 0 if s->rxf_sts =3D=3D 0.
As = a result the code will take the following branch and returns:
=C2= =A0if (received_bytes =3D=3D 0) {
=C2=A0 =C2=A0 npcm7xx_smbus_recv_fifo(= s);
=C2=A0 =C2=A0 return;
=C2=A0}
And will not execute the = --s->rxf_sts sentence.
Please let me know if I missed anything= here.

> I'll probably add "g_assert(s->rxf_sts > 0)" to cl= arify.

You never want to do an assert if the hosted system can do something to
cause it.=C2=A0 If you add the check to the NPCM7XX_SMBUS_STATUS_RECEIVING<= br> case, it would be ok, but really unnecessary.

If it's fine if s->rxf_sts wraps to 0xff, then this all doesn't = matter,
but you want to add a comment to that effect if so.=C2=A0 These sorts of things look dangerous.

There is also the question about who takes these patches in.=C2=A0 I'm = the
I2C maintainer, but there's other code in this series.=C2=A0 Once every= thing
is ready, I can ack them if we take it through the ARM tree.=C2=A0 Or I can=
take it through my tree with the proper acks.
I think = either=C2=A0 way is fine. Previous NPCM7XX patch series were taken in the A= RM tree. But as i2c code taking into your tree is also fine.

-corey

>
> >
> > Other than this, I didn't see any issues with this patch.
> >
> > -corey
> >
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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id s19sm4964346wrf.72.2021.01.27.14.00.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 14:00:04 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-20-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <867464b2-576c-588e-3890-a0a78d5dc710@amsat.org> Date: Wed, 27 Jan 2021 23:00:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-20-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 22:00:08 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Switch the CMSDK APB dualtimer device over to using its Clock input; > the pclk-frq property is now ignored. > > Signed-off-by: Peter Maydell > --- > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- > 1 file changed, 37 insertions(+), 5 deletions(-) ... > @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) > CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev); > int i; > > - if (s->pclk_frq == 0) { > - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); > + if (!clock_has_source(s->timclk)) { > + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected"); > return; > } Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 17:10:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4t10-0003cd-SW for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 17:10:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4t0x-0003av-UC; Wed, 27 Jan 2021 17:10:15 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:46518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4t0w-0006Hs-45; Wed, 27 Jan 2021 17:10:15 -0500 Received: by mail-wr1-x430.google.com with SMTP id q7so3462782wre.13; Wed, 27 Jan 2021 14:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=Vy1Nf4PodWV+2JODGG7IeRZfWJk43JfzCSwvbK9HNqE=; b=KQ8y6wa/OsOP7+n4Ev3SUkqRZUk9qytm03SeUmCJk1yhPgcclvV3SkSnP94eJBCNRw u+qS0G4KU7gws+zaUtu2MHTKkneNaQGr8esQbcf1xjvfA9EAR8eEDyU2lKAdwKaXJS1r HfCH+DGwS/mXihtEY5Fsf9J1T+lhJtJSH0pSxKuCkFEqlBxUVhAw+XNzuO73yJnEgfvo YGSMakUI7CEg8OHo5bX65U+hDDfV/IVpIg0cOFYCSfdQAwVEDMiexfvdyiVDVD8lR5p6 24rZ2o5qmNiFqwa6vesMA0+X22rMFfDN3fkzsA0xkSk1e3w1yuRExz1W/Kc4EjVPfBLN 67pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Vy1Nf4PodWV+2JODGG7IeRZfWJk43JfzCSwvbK9HNqE=; b=T2dy/RU1nQO7qVfDvFAKkwAaeoH2gjGlxDO37xkfVqZdaMWFjXQCYQWhLUXx6PnW+P c5znTC1mNWWmZcmMfMY+m369k4oMTmhrrsHMLrgREmkX6IWSj53Pjl7L9GCH54mtMTZQ BRFWGbnP2QReL61q9EVJaCiD9rvtIjjQA+5dUVy7Mk79LZYcMTI9UB+3IsTYINU0eSZt Fsqtr9gm+FACH5/LNlsGsGjhEBoJ/+Sp/9VYl3Edju3Tl2i0LOXEcmMv7/+PZ0NZI1Y6 LKYyIJyOgyZD5Q+r2xkvjuGnW/YaALJFxuiMoAcXbv7eHf2AV6Uz9idjPRrT8jSoMgCg tzOA== X-Gm-Message-State: AOAM533dCf21hXrWMjI0zaPXkr6vexwpneJv4Tz/Sq+INOd+au0fyJ/j q3KNaWdMhLGSRAadtdxPMR3g0oE02ys= X-Google-Smtp-Source: ABdhPJyZzIRqUtlxO/7sn+JD23O4V29kSdXg6YC9nwq6oy/U5c0DAxUYp2GvPlVRIzbvxp2sg82ziQ== X-Received: by 2002:adf:c14d:: with SMTP id w13mr12924457wre.383.1611785411650; Wed, 27 Jan 2021 14:10:11 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id o12sm4459553wrx.82.2021.01.27.14.10.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 14:10:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device To: Peter Maydell Cc: Damien Hedde , qemu-arm , Luc Michel , QEMU Developers References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-17-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9a64e598-91e8-7547-3b5c-ad2a8c8496e3@amsat.org> Date: Wed, 27 Jan 2021 23:10:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 22:10:16 -0000 On 1/25/21 12:48 PM, Peter Maydell wrote: > On Thu, 21 Jan 2021 at 22:13, Philippe Mathieu-Daudé wrote: >> On 1/21/21 8:06 PM, Peter Maydell wrote: >>> Convert the SSYS code in the Stellaris boards (which encapsulates the >>> system registers) to a proper QOM device. This will provide us with >>> somewhere to put the output Clock whose frequency depends on the >>> setting of the PLL configuration registers. >>> >>> This is a migration compatibility break for lm3s811evb, lm3s6965evb. >>> >>> We use 3-phase reset here because the Clock will need to propagate >>> its value in the hold phase. >>> >>> For the moment we reset the device during the board creation so that >>> the system_clock_scale global gets set; this will be removed in a >>> subsequent commit. > >>> + >>> +struct ssys_state { >>> + SysBusDevice parent_obj; >>> + >>> MemoryRegion iomem; >>> uint32_t pborctl; >>> uint32_t ldopctl; >>> @@ -371,11 +376,18 @@ typedef struct { >>> uint32_t dcgc[3]; >>> uint32_t clkvclr; >>> uint32_t ldoarst; >>> + qemu_irq irq; >>> + /* Properties (all read-only registers) */ >>> uint32_t user0; >>> uint32_t user1; >>> - qemu_irq irq; >>> - stellaris_board_info *board; >>> -} ssys_state; >>> + uint32_t did0; >>> + uint32_t did1; >>> + uint32_t dc0; >>> + uint32_t dc1; >>> + uint32_t dc2; >>> + uint32_t dc3; >>> + uint32_t dc4; >> >> Shouldn't these be class properties? > > Could you elaborate on what you think the code ought to look like? I am thinking something similar how Igor asked me to implement RaspiMachineClass::board_rev in hw/arm/raspi.c, as the did/dc registers are read-only. Anyhow this is 1/ probably not necessary and 2/ out of the scope of this series, this patch is already complex enough, and the work is done. > I just used the usual thing of defining uint32 qdev properties so we > can set these values when we create the device, as a replacement > for the existing code which either reaches directly into the > state struct to set the user0/user1 values or sets the > stellaris_board_info pointer in the state struct. No problem. Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 17:11:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4t1k-0003yk-JM for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 17:11:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4t1h-0003xa-Of; Wed, 27 Jan 2021 17:11:02 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33478) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4t1f-0006SQ-Rv; Wed, 27 Jan 2021 17:11:01 -0500 Received: by mail-wr1-x42e.google.com with SMTP id 7so3512941wrz.0; Wed, 27 Jan 2021 14:10:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qd/PUZyZLreEzQbUiisMF4yo6oOEpNQQcPsYP3MH6ec=; b=DLVRBTIWjKuK+xvNrzpNicEgNfU5RcZIw4s8aLjkJ5LZN7PP59c3Y/Eu0lPEa1/U0P Sf0N0+xVZoW1TH/6JM7m5ZQZSJ4z6MYCPytRM1/nR5sdZLPyY4SHVKVhMlCLFCC4+2rg iZvuwYVsKBJsOeeFGvPQBsMoAuBCWdg2Znl+kj17A/MCgaEDaiEwfAUp9k+gstegvjnd FTlam8zmMv4MDXpRXEXrqOo3rAgphOBe6EjPZ5Te694i923Wkj1r4/KykRNR5HJ0Q2bY Wqcux5KRsJ3CTO18Vv99uow24L5/kY4xdGj1h4z3MOnsi6Rmlj4hhDNt3TJkOq6dzOyy siCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qd/PUZyZLreEzQbUiisMF4yo6oOEpNQQcPsYP3MH6ec=; b=sSX+Bsnys0YSDrt7Hry2tL5LXarREThYed+Wt6gLQIlwQbkcVWeFq6h0Y/NaZmzSJb taRnD/tcgEIjkMQ0mb/+4HmH8PZyLD1OPOG6MEBkOp0C6rgP1P2s5utLtz8q35angGzK slGmn3So/UyXvySlgTJ/25ufHUH6cmea5qXnVpS7XfcKNnJUbOBboYtLB35zmjA4d/6u LL8MXDfdU0xHMx46+hh1Qo2tfju8i65XeP7THbNI54fDNdGuoHF8bvwBMdQS5FkJ/L7S VKxYV35b0dwqPfCK8tUMjboaMZYXxUzzgSvJ61LNatx9vIglhp96bYmTZXMKBpSgb9TV wZnQ== X-Gm-Message-State: AOAM532gQ0LI2PI8qi0h2cDmCBC73TZ6R6J7onP55Y1AyvY37kp3noBM hkPBPwfZWdtu1vfZT6OlrnScqB2SXj0= X-Google-Smtp-Source: ABdhPJx0ePWX4IhUKogr6KLO8pRZ+jmHmTS4aRYPN12jePhq+wubXuurxTfIZYJ+SO2tyapzvfOSKg== X-Received: by 2002:a05:6000:1788:: with SMTP id e8mr13224883wrg.171.1611785458260; Wed, 27 Jan 2021 14:10:58 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c11sm4334396wrs.28.2021.01.27.14.10.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 14:10:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-26-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <53675a31-3af0-e4d9-62a8-bd1e4636b8cf@amsat.org> Date: Wed, 27 Jan 2021 23:10:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210121190622.22000-26-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 22:11:02 -0000 On 1/21/21 8:06 PM, Peter Maydell wrote: > Now that the watchdog device uses its Clock input rather than being > passed the value of system_clock_scale at creation time, we can > remove the hack where we reset the STELLARIS_SYS at board creation > time to force it to set system_clock_scale. Instead it will be reset > at the usual point in startup and will inform the watchdog of the > clock frequency at that point. > > Signed-off-by: Peter Maydell > --- > hw/arm/stellaris.c | 10 ---------- > 1 file changed, 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 17:17:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4t7a-0007ll-Oj for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 17:17:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4t7T-0007l6-Ae; Wed, 27 Jan 2021 17:17:00 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:37356) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4t7R-0007Fj-4P; Wed, 27 Jan 2021 17:16:58 -0500 Received: by mail-wr1-x436.google.com with SMTP id v15so3520708wrx.4; Wed, 27 Jan 2021 14:16:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=OTuEjDC5K6UsCHMjmJcHO+UyZ528TXMXVDTN+oruipQ=; b=olL+uqIlMjicg1X6Clpb/GX0bpsJvAU0r3puKuHh6TsH/jsPKm9Go2hqPV/TofGJIh a7s98nG/4X3BdNAb0oct4Fdthw6M4U88oFdT9bzQ0Ic5KnOVUtQXzxt33JX0OrBRgSfK +oIh/1NWKGUBOI7jeILdzqxDqRjmqLx6YiWasLIugjs9xZER+BC5V7ZKnPun9LDemo5v 2ARCFfSw5oyB2t97ApUQ8t8K4+GmoeouoeFN8UWSp2+zI3TVTDWQDCg9/1dMFSvO4uoN HvULSwuVWgAKa+dhL4uoDpu86FpzPmswDTozHargZjQkGcGwRyxBK6irqnkcTLzqwQYQ 2NHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:from:to:cc:references:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=OTuEjDC5K6UsCHMjmJcHO+UyZ528TXMXVDTN+oruipQ=; b=JT68fTc7ldiIU+QT4LZ+rtgWl4nCvUhTR3HPH0dNMDzn3fhvx9E/fTfN3ZzkytdBzE 1hMVLsfobezKuvnFh3oza83xp7woOzbrXnyyqQwHYd7fZ45b5jAl8AXu7WLHfAxM/ztQ xENs0yEFN90uNDfEmC+w9CjJqVg1TCRDF8pLJ0+Qn/SBKR1KeeTNdcImuv8PPTyEZyIy 6QnuzfJAO4vn6qWo4fs9c2y0Q84E5Fmz+PsImo5z52OjCYRw7rqqmpibYh70tnEbtUf/ OH6mMPkpDr21uvQBbAIEvmdzQOdVPkNSvbq+L1JB5M6XvRqmSPM5uljIuwG6QZ82+fYR 2cAA== X-Gm-Message-State: AOAM53386N3ppewPPP6hRmTD4ZzApuSP1UlevmN2WziJyKF9Fm3ZZ+sD Mm2Sw+jcJ3w+HtXaOB43yWg= X-Google-Smtp-Source: ABdhPJzxjCgzgKYZ/a+jec6DhUMGJiC9cC//u4stoLBb2A5YqUqX3WzVMYVtjvHoTo3nSit43toXqw== X-Received: by 2002:adf:eb05:: with SMTP id s5mr13194981wrn.333.1611785814972; Wed, 27 Jan 2021 14:16:54 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s24sm3747148wmh.22.2021.01.27.14.16.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 14:16:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Damien Hedde , Luc Michel References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-18-peter.maydell@linaro.org> <5ee67f0e-fcda-22bb-2001-109e488cd632@amsat.org> Message-ID: <83870454-4d8b-bb1e-7449-9edd18618b51@amsat.org> Date: Wed, 27 Jan 2021 23:16:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <5ee67f0e-fcda-22bb-2001-109e488cd632@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 22:17:04 -0000 On 1/21/21 10:59 PM, Philippe Mathieu-Daudé wrote: > On 1/21/21 8:06 PM, Peter Maydell wrote: >> Create and connect the Clock input for the watchdog device on the >> Stellaris boards. Because the Stellaris boards model the ability to >> change the clock rate by programming PLL registers, we have to create >> an output Clock on the ssys_state device and wire it up to the >> watchdog. >> >> Note that the old comment on ssys_calculate_system_clock() got the >> units wrong -- system_clock_scale is in nanoseconds, not >> milliseconds. Improve the commentary to clarify how we are >> calculating the period. >> >> Signed-off-by: Peter Maydell >> --- >> hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ >> 1 file changed, 31 insertions(+), 12 deletions(-) > ... > >> /* >> - * Caculate the sys. clock period in ms. >> + * Calculate the system clock period. We only want to propagate >> + * this change to the rest of the system if we're not being called >> + * from migration post-load. > > This part was not trivial to understand. I read the Clock API > doc again then found: > > Care should be taken not to use ``clock_update[_ns|_hz]()`` or > ``clock_propagate()`` during the whole migration procedure because it > will trigger side effects to other devices in an unknown state. > >> */ >> -static void ssys_calculate_system_clock(ssys_state *s) >> +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) >> { >> + /* >> + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input >> + * clock is 200MHz, which is a period of 5 ns. Dividing the clock >> + * frequency by X is the same as multiplying the period by X. >> + */ >> if (ssys_use_rcc2(s)) { >> system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); >> } else { >> system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); >> } >> + clock_set_ns(s->sysclk, system_clock_scale); >> + if (propagate_clock) { >> + clock_propagate(s->sysclk); >> + } >> } > ... >> static void stellaris_sys_reset_exit(Object *obj) >> @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) >> { >> ssys_state *s = opaque; >> >> - ssys_calculate_system_clock(s); >> + ssys_calculate_system_clock(s, false); > > So this makes sense. > > I'll keep reviewing and come back to this patch later. Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 27 18:28:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4uEi-0007fP-RD for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 18:28:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4uEf-0007e9-3J; Wed, 27 Jan 2021 18:28:29 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4uEc-0006re-RR; Wed, 27 Jan 2021 18:28:28 -0500 Received: by mail-wm1-x32c.google.com with SMTP id z16so529506wml.2; Wed, 27 Jan 2021 15:28:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=wvjU515Spj3A6CDw5WT0Qql1F2X6k6eBgld4h9Q3aTY=; b=QslmrtenSqE+UQ/I5U0seLfuh5vVJj48pVeD/EgSl2hcng1f7oCcD8IKmoKa8tuXHe h5nIOI18XP5/NRHAPeqJbU7nGPHXDICqLDTsYslHDBnGa/3qbPGvTYH10u6AnR+n9mwo xvgvn7NVymvpXztbdZjJDa9A9QezOOYej4V9475XcpHFtBopKXjcYjEew8IgM2o9tSyx BBpgozV//eumobKuBkOT6TF8NlNn9IF8XU4TCSU6syh+FMrVFoN/hB6ofAxXZeaVcyS5 86AFHSnD4APi6IBcnVif9s/yy3aGTQETXdZ2c1git0Q1vorjTsOjbnASouQ5xzLrANb3 Ou5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=wvjU515Spj3A6CDw5WT0Qql1F2X6k6eBgld4h9Q3aTY=; b=isonr9Y/thgVA8jUuv8/47MklwLqvGn3vX1a4q7VZ4drjp6PZzfGLMZT5h6ZqANfMB WL3rHsQtg2Ai62tTIrlOE+a+gKBgrLSFVp75fMwLBNn2yztOOs8CTqxwHW7ahn5NIikR FvEqqPpub6RgjpMQ/fRdfmDITiCnLug2hhy38wxGHCkZBNfyQS09rCPXVW4X+u+JHJeI NDdtZ2f4t8OUXSECuDC/te/viJyaH1tbI0tK9gfYBFW7XeaQzFg+kZna2I0fd5+ODtBD e3UtU+Kkd5nISlnSmLeBEZdSLBGnaSbpGYJda6P13r+Dj5fl2rnGBzdpriagGVtw2zBC aPJw== X-Gm-Message-State: AOAM5306R7SZzHFbPzmQSrV5mCYyjRJcG98Enw9aQId9kDsKYRy7SgMT jkRJYSla+rMKDDdg3bhMP4wTCTlXVko= X-Google-Smtp-Source: ABdhPJxRSCIOmVrGp3wYYbtJ1fjTJB1yMe4D63whcmRzdqEwmRc4s7HSVfkqyPccp8JJ4nhco9U6tw== X-Received: by 2002:a05:600c:21d8:: with SMTP id x24mr6049698wmj.27.1611790104950; Wed, 27 Jan 2021 15:28:24 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id z130sm3634316wmb.33.2021.01.27.15.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 15:28:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Joe Komlodi , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] target/arm: Replace magic value by MMU_DATA_LOAD definition Date: Thu, 28 Jan 2021 00:28:22 +0100 Message-Id: <20210127232822.3530782-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 23:28:30 -0000 cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ead3fcbdb..766ca8b5c78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12409,7 +12409,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, *attrs = (MemTxAttrs) {}; - ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, + ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, attrs, &prot, &page_size, &fi, &cacheattrs); if (ret) { -- 2.26.2 From MAILER-DAEMON Wed Jan 27 18:37:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4uNS-0004Bb-H4 for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 18:37:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4uNP-0004AA-9Z; Wed, 27 Jan 2021 18:37:32 -0500 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:34573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4uNN-0007yE-Ko; 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Wed, 27 Jan 2021 15:37:27 -0800 (PST) Received: from serve.minyard.net ([47.184.170.156]) by smtp.gmail.com with ESMTPSA id 189sm734626oie.23.2021.01.27.15.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 15:37:26 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:84df:dff0:9fb7:e686]) by serve.minyard.net (Postfix) with ESMTPSA id 6254B18055B; Wed, 27 Jan 2021 23:37:25 +0000 (UTC) Date: Wed, 27 Jan 2021 17:37:24 -0600 From: Corey Minyard To: Hao Wu Cc: Peter Maydell , Patrick Venture , QEMU Developers , Havard Skinnemoen , CS20 KFTing , qemu-arm , IS20 Avi Fishman , Doug Evans Subject: Re: [PATCH 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode Message-ID: <20210127233724.GF2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-7-wuhaotsh@google.com> <20210126234724.GC2057975@minyard.net> <20210127214251.GE2057975@minyard.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=tcminyard@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jan 2021 23:37:32 -0000 On Wed, Jan 27, 2021 at 01:59:07PM -0800, Hao Wu wrote: > On Wed, Jan 27, 2021 at 1:42 PM Corey Minyard wrote: > > > On Wed, Jan 27, 2021 at 12:37:46PM -0800, wuhaotsh--- via wrote: > > > On Tue, Jan 26, 2021 at 3:47 PM Corey Minyard wrote: > > > > > > > On Tue, Jan 26, 2021 at 11:32:37AM -0800, wuhaotsh--- via wrote: > > > > > + > > > > > +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) > > > > > +{ > > > > > + uint8_t received_bytes = > > NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > > > > > + > > > > > + if (received_bytes == 0) { > > > > > + npcm7xx_smbus_recv_fifo(s); > > > > > + return; > > > > > + } > > > > > + > > > > > + s->sda = s->rx_fifo[s->rx_cur]; > > > > > + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; > > > > > + --s->rxf_sts; > > > > > > > > This open-coded decrement seems a little risky. Are you sure in every > > > > case that s->rxf_sts > 0? There's no way what's running in the VM can > > > > game this and cause a buffer overrun? One caller to this function > > seems > > > > to protect against this, and another does not. > > > > > > > s->rxf_sts is uint8_t so it's guaranteed to be >=0. > > > In the case s->rxf_sts == 0, NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) is > > > also 0, so it'll take the if-branch and return without running > > --s->rxf_sts. > > > > That is true if called from the > > NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE case. There is no such check > > in the NPCM7XX_SMBUS_STATUS_RECEIVING case. > > > I don't understand the reasoning here. The caller doesn't matter. > Previous code has: > #define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) > So > uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); > is guaranteed to be 0 if s->rxf_sts == 0. > As a result the code will take the following branch and returns: > if (received_bytes == 0) { > npcm7xx_smbus_recv_fifo(s); > return; > } > And will not execute the --s->rxf_sts sentence. > Please let me know if I missed anything here. Ah, sorry, I missed that. Yes, this is ok. So... Reviewed-by: Corey Minyard > > > > > > I'll probably add "g_assert(s->rxf_sts > 0)" to clarify. > > > > You never want to do an assert if the hosted system can do something to > > cause it. If you add the check to the NPCM7XX_SMBUS_STATUS_RECEIVING > > case, it would be ok, but really unnecessary. > > > > If it's fine if s->rxf_sts wraps to 0xff, then this all doesn't matter, > > but you want to add a comment to that effect if so. These sorts of > > things look dangerous. > > > > There is also the question about who takes these patches in. I'm the > > I2C maintainer, but there's other code in this series. Once everything > > is ready, I can ack them if we take it through the ARM tree. Or I can > > take it through my tree with the proper acks. > > > I think either way is fine. Previous NPCM7XX patch series were taken in > the ARM tree. But as i2c code taking into your tree is also fine. > > > > > -corey > > > > > > > > > > > > > Other than this, I didn't see any issues with this patch. > > > > > > > > -corey > > > > > > From MAILER-DAEMON Wed Jan 27 19:42:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4vOl-0003eg-By for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 19:42:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4vOg-0003dS-C5 for qemu-arm@nongnu.org; Wed, 27 Jan 2021 19:42:55 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:38738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4vOd-0006Pk-Mq for qemu-arm@nongnu.org; Wed, 27 Jan 2021 19:42:54 -0500 Received: by mail-wm1-x32d.google.com with SMTP id y187so3183152wmd.3 for ; Wed, 27 Jan 2021 16:42:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=4FUggc4yzu1KtYVghJzSJJr7MdA1Yc7w8ID3X4Mlw2M=; b=F+xs49xd/VAG5Vm+qCegbXtUW14C8tNcQpSgLW1vJ1JJutem1Z8oCxoGrjVvzuNnso 8TIGOGC0dpl9msUfrnnUGuUXKX01aPdNT9kfZfuelfGz9zk/6VLsdMMdIH5ZugakqQOx eHLRXeBdi60nTXcku9IMazLo73M/8Mx8B16qQQj5N2zQHvP8xpDQdQ9O9E6/1B/PNeaH RLOtfxQ6+ywxN7t6rkj58wXxjCVJVFznAjYAI6EaqbWRE2fUSwi+HA+TKtCRf1n9V5qE 50qtkx0TN2giWRnjzSsfiCzUccjz0IY3rTLlbG7/jVZhd/hLvOf2hTAOzxZShl7Gen3y zw/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=4FUggc4yzu1KtYVghJzSJJr7MdA1Yc7w8ID3X4Mlw2M=; b=EnjZEPGuy51kQga3qr+LjmhSHEBIPxThMEAhs89TfEvZJatgZ7iUNpaHA1kl1ISm3M uS7PbWrcpIzIjrQAEGM9UIs6UC0C8fpB/MYYcEBXYJ4YP67WQu3Hg0wsd3Yy0XpCl7yj 9FJ1R+7tzQlohpG31Yn1+X79jtlZCNK19YSThP46u2EovjJFPugSoMwX2TU237gGh8/H Byjah3BeFLJObD9ZxqvIlSf69M9ka77k85h3Zy7nMsYq5cQwxzoGPYnDVBzPNK0N0ZWe 6dqJbJNnp+9M0yevhYQqGLKC2EbKqO2R/6fKIFv7iQajVYRicRV8+lH7KJ2BAxMFP/7k 8Jxg== X-Gm-Message-State: AOAM530X+xVMqOBRRVl6q8SULLbmwY4iSccZsQJvbImiYLeCHiCXG7/P 1Q1fqzmRjWMQ1IDdLvbDJs2QBw== X-Google-Smtp-Source: ABdhPJybTXFN9BRWqacIhqXMQQBrv/YSjbVjMcWL1N4zB9EwkDozKrP6iQxgjot5N25UyTcAVhw9sw== X-Received: by 2002:a1c:f706:: with SMTP id v6mr6301059wmh.85.1611794569066; Wed, 27 Jan 2021 16:42:49 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s24sm4020238wmh.22.2021.01.27.16.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 16:42:47 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 050D81FF7E; Thu, 28 Jan 2021 00:42:47 +0000 (GMT) References: <20200929224355.1224017-1-philmd@redhat.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Thomas Huth , Paolo Bonzini , Richard Henderson , Fam Zheng , Peter Maydell , kvm@vger.kernel.org, qemu-arm@nongnu.org, Richard Henderson Subject: Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Date: Thu, 28 Jan 2021 00:41:50 +0000 In-reply-to: <20200929224355.1224017-1-philmd@redhat.com> Message-ID: <87r1m5x56h.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 00:42:55 -0000 Philippe Mathieu-Daud=C3=A9 writes: > Cover from Samuel Ortiz from (part 1) [1]: > > This patchset allows for building and running ARM targets with TCG > disabled. [...] > > The rationale behind this work comes from the NEMU project where we're > trying to only support x86 and ARM 64-bit architectures, without > including the TCG code base. We can only do so if we can build and run > ARM binaries with TCG disabled. > > v4 almost 2 years later... [2]: > - Rebased on Meson > - Addressed Richard review comments > - Addressed Claudio review comments Have you re-based recently because I was having a look but ran into merge conflicts. I'd like to get the merged at some point because I ran into similar issues with the Xen only build without TCG. > > v3 almost 18 months later [3]: > - Rebased > - Addressed Thomas review comments > - Added Travis-CI job to keep building --disable-tcg on ARM > > v2 [4]: > - Addressed review comments from Richard and Thomas from v1 [1] > > Regards, > > Phil. > > [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html > [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html > [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html > [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html > > Green CI: > - https://cirrus-ci.com/build/4572961761918976 > - https://gitlab.com/philmd/qemu/-/pipelines/196047779 > - https://travis-ci.org/github/philmd/qemu/builds/731370972 > > Based-on: <20200929125609.1088330-1-philmd@redhat.com> > "hw/arm: Restrict APEI tables generation to the 'virt' machine" > https://www.mail-archive.com/qemu-devel@nongnu.org/msg745792.html > > Philippe Mathieu-Daud=C3=A9 (10): > accel/tcg: Add stub for cpu_loop_exit() > meson: Allow optional target/${ARCH}/Kconfig > target/arm: Select SEMIHOSTING if TCG is available > target/arm: Restrict ARMv4 cpus to TCG accel > target/arm: Restrict ARMv5 cpus to TCG accel > target/arm: Restrict ARMv6 cpus to TCG accel > target/arm: Restrict ARMv7 R-profile cpus to TCG accel > target/arm: Restrict ARMv7 M-profile cpus to TCG accel > target/arm: Reorder meson.build rules > .travis.yml: Add a KVM-only Aarch64 job > > Samuel Ortiz (1): > target/arm: Do not build TCG objects when TCG is off > > Thomas Huth (1): > target/arm: Make m_helper.c optional via CONFIG_ARM_V7M > > default-configs/arm-softmmu.mak | 3 -- > meson.build | 8 +++- > target/arm/cpu.h | 12 ------ > accel/stubs/tcg-stub.c | 5 +++ > target/arm/cpu_tcg.c | 4 +- > target/arm/helper.c | 7 ---- > target/arm/m_helper-stub.c | 73 +++++++++++++++++++++++++++++++++ > .travis.yml | 35 ++++++++++++++++ > hw/arm/Kconfig | 32 +++++++++++++++ > target/arm/Kconfig | 4 ++ > target/arm/meson.build | 40 +++++++++++------- > 11 files changed, 184 insertions(+), 39 deletions(-) > create mode 100644 target/arm/m_helper-stub.c > create mode 100644 target/arm/Kconfig --=20 Alex Benn=C3=A9e From MAILER-DAEMON Wed Jan 27 21:36:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4xAV-0008LQ-Lz for mharc-qemu-arm@gnu.org; Wed, 27 Jan 2021 21:36:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4xAT-0008L9-Jw; Wed, 27 Jan 2021 21:36:21 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4xAQ-0002fP-QM; Wed, 27 Jan 2021 21:36:21 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DR4M43CPSzjCJ4; Thu, 28 Jan 2021 10:35:12 +0800 (CST) Received: from [10.174.184.214] (10.174.184.214) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Thu, 28 Jan 2021 10:36:01 +0800 Subject: Re: [RFC PATCH v2 2/3] vfio: Set the priority of the VFIO VM state change handler explicitly To: Alex Williamson CC: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-3-lushenming@huawei.com> <20210126143605.4f9d5b25@omen.home.shazbot.org> <153c36e0-3c7d-cbce-3f37-9ba8c36ce1ca@huawei.com> <20210127072014.6ed9ff04@x1.home.shazbot.org> From: Shenming Lu Message-ID: <87643ae9-1c4d-a612-61cc-510b8d60a329@huawei.com> Date: Thu, 28 Jan 2021 10:35:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <20210127072014.6ed9ff04@x1.home.shazbot.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.214] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=lushenming@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 02:36:21 -0000 On 2021/1/27 22:20, Alex Williamson wrote: > On Wed, 27 Jan 2021 19:20:06 +0800 > Shenming Lu wrote: > >> On 2021/1/27 5:36, Alex Williamson wrote: >>> On Wed, 9 Dec 2020 16:09:18 +0800 >>> Shenming Lu wrote: >>> >>>> In the VFIO VM state change handler, VFIO devices are transitioned >>>> in the _SAVING state, which should keep them from sending interrupts. >>> >>> Is this comment accurate? It's my expectation that _SAVING has no >>> bearing on a device generating interrupts. Interrupt generation must >>> be allowed to continue so long as the device is _RUNNING. Thanks, >>> >> >> To be more accurate, the _RUNNING bit in device_state is cleared in the >> VFIO VM state change handler when stopping the VM. And if the device continues >> to send interrupts after this, how can we save the states of device interrupts >> in the stop-and-copy phase?... > > Exactly, it's clearing the _RUNNING bit that makes the device stop, > including no longer generating interrupts. Perhaps I incorrectly > inferred "_SAVING state" as referring to the _SAVING bit when you > actually intended: > > * +------- _RESUMING > * |+------ _SAVING > * ||+----- _RUNNING > * ||| > * 000b => Device Stopped, not saving or resuming > * 001b => Device running, which is the default state > -> * 010b => Stop the device & save the device state, stop-and-copy state > > ie. the full state when only _SAVING is set. > > Could we make the comment more clear to avoid this confusion? Thanks, > OK, sorry for the confusion. I will modify the comment to: In the VFIO VM state change handler when stopping the VM, the _RUNNING bit in device_state is cleared which makes the VFIO device stop, including no longer generating interrupts. Thanks, Shenming > Alex > >>>> Then we can save the pending states of all interrupts in the GIC VM >>>> state change handler (on ARM). >>>> >>>> So we have to set the priority of the VFIO VM state change handler >>>> explicitly (like virtio devices) to ensure it is called before the >>>> GIC's in saving. >>>> >>>> Signed-off-by: Shenming Lu >>>> Reviewed-by: Kirti Wankhede >>>> --- >>>> hw/vfio/migration.c | 3 ++- >>>> 1 file changed, 2 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c >>>> index 3b9de1353a..97ea82b100 100644 >>>> --- a/hw/vfio/migration.c >>>> +++ b/hw/vfio/migration.c >>>> @@ -862,7 +862,8 @@ static int vfio_migration_init(VFIODevice *vbasedev, >>>> register_savevm_live(id, VMSTATE_INSTANCE_ID_ANY, 1, &savevm_vfio_handlers, >>>> vbasedev); >>>> >>>> - migration->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change, >>>> + migration->vm_state = qdev_add_vm_change_state_handler(vbasedev->dev, >>>> + vfio_vmstate_change, >>>> vbasedev); >>>> migration->migration_state.notify = vfio_migration_state_notifier; >>>> add_migration_state_change_notifier(&migration->migration_state); >>> >>> . >>> >> > > . > From MAILER-DAEMON Thu Jan 28 00:36:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l4zyz-0006kx-AN for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 00:36:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4zyx-0006kS-Bq; Thu, 28 Jan 2021 00:36:39 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]:35278) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4zyv-00084D-M0; Thu, 28 Jan 2021 00:36:39 -0500 Received: by mail-oi1-x22f.google.com with SMTP id w8so4872523oie.2; Wed, 27 Jan 2021 21:36:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:date:from:to:cc:subject:message-id:reply-to:references :mime-version:content-disposition:in-reply-to; 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Wed, 27 Jan 2021 21:36:36 -0800 (PST) Received: from serve.minyard.net ([47.184.170.156]) by smtp.gmail.com with ESMTPSA id m7sm815945otq.33.2021.01.27.21.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 21:36:35 -0800 (PST) Sender: Corey Minyard Received: from minyard.net (unknown [IPv6:2001:470:b8f6:1b:d0e0:7e1d:debb:57fe]) by serve.minyard.net (Postfix) with ESMTPSA id B817A180042; Thu, 28 Jan 2021 05:36:33 +0000 (UTC) Date: Wed, 27 Jan 2021 23:36:32 -0600 From: Corey Minyard To: Hao Wu Cc: Peter Maydell , Patrick Venture , QEMU Developers , Havard Skinnemoen , CS20 KFTing , qemu-arm , IS20 Avi Fishman , Doug Evans Subject: Re: [PATCH 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode Message-ID: <20210128053632.GG2057975@minyard.net> Reply-To: minyard@acm.org References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-7-wuhaotsh@google.com> <20210126234724.GC2057975@minyard.net> <20210127214251.GE2057975@minyard.net> <20210127233724.GF2057975@minyard.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210127233724.GF2057975@minyard.net> Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=tcminyard@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 05:36:39 -0000 On Wed, Jan 27, 2021 at 05:37:25PM -0600, Corey Minyard wrote: > On Wed, Jan 27, 2021 at 01:59:07PM -0800, Hao Wu wrote: > > > > > > There is also the question about who takes these patches in. I'm the > > > I2C maintainer, but there's other code in this series. Once everything > > > is ready, I can ack them if we take it through the ARM tree. Or I can > > > take it through my tree with the proper acks. > > > > > I think either way is fine. Previous NPCM7XX patch series were taken in > > the ARM tree. But as i2c code taking into your tree is also fine. > > Let's go through the ARM tree, then. So you have an: Acked-by: Corey Minyard For patches 2 and 6. Patch 4 still has the issue with the eeprom size. If you are expecting a 32K eeprom to work, it's not going to, you are only going to get 256 bytes. -corey From MAILER-DAEMON Thu Jan 28 02:15:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l51Wj-0007RH-L9 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 02:15:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l51Wh-0007QP-Lg; Thu, 28 Jan 2021 02:15:35 -0500 Received: from mail-yb1-xb33.google.com ([2607:f8b0:4864:20::b33]:44080) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l51Wc-0007wf-SZ; Thu, 28 Jan 2021 02:15:35 -0500 Received: by mail-yb1-xb33.google.com with SMTP id x78so4502109ybe.11; Wed, 27 Jan 2021 23:15:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3su8nERs1WgrjvXCCzyVB6guaBvShP0tnVo3ZULSKhs=; b=HwC4esHM2smkho3SLW/8Gh1SdZSVyEzkJOjtEthOjNHi5sqD8bAgXRixU8jsjIq5Ac cp3+pq0v1zx5J3QUQpA0P3W7P1hw0xqORv76HJb/pUYD/ZimzZWZEgi2DrSUVLlk+QUs nqEVgNW8JkVqySNIHP0LVBWTg8PA4FGUqfpoWkc2uXszIPcpb3k/gaRwhMZpML+Nisit N/D+wx5anCEcFRDVFSISa/1KH3kGaJBWfy9rnZuyTTq4mE60lkdAKc7htwVdto9ifeJH ornoPpzLPFxjdsVWfVBgHiGDL2oDn26pF1IzcfterS0TmBwk+1FvhkhKvWuX97bhDjzX enwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3su8nERs1WgrjvXCCzyVB6guaBvShP0tnVo3ZULSKhs=; b=IzRSuT29bLvkgU64hKj/FVJpuvMxo/iuNSitcqSNd35b65GGu9sm7er2OpOPiWGjEX NWvCZg/iqTK0Qtjmeu9sQNnP5yeE4SBE553RXZNy/D+RfeSiH8y4twooEa9NdBXdL4Cl 1IqVCnhJs2kNPvdTmAeM9fV2d/cB+1eTEMMpCkfa/fNiGYsTZXx9liKl9SPsR/1WQeAq o1H2MGOxiZpUiEIt2QnjccCOgQRJbmX5AJr8wHqKyTzUxpA5HnTUWajGoslZiYxFwzir Aihlz/2az+RfzpKZQUMQ9XpySRWpwCdNZp1aErB+lm25gup60KGBZdAyUXiUu0FxU8NH MGEg== X-Gm-Message-State: AOAM5333nEZi3sVpcnGKjX9/C8NJ2NkxR84F0d0u4lvbqkvmA/hzgLWb KQgIRvr5eL8a07Smt5aLahgmFT2db9iRuZWwYE4= X-Google-Smtp-Source: ABdhPJzRBpUeYJo4B4LqtnKY9u+fq1A7XKMlDWudA6rQf17IxrOQoJP8ADS/3Wnu0jO5Jl2QWT2mw2KakAbOAD/qJPw= X-Received: by 2002:a25:cc3:: with SMTP id 186mr1718436ybm.306.1611818129404; Wed, 27 Jan 2021 23:15:29 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Thu, 28 Jan 2021 15:15:18 +0800 Message-ID: Subject: Re: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b33; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 07:15:36 -0000 On Fri, Jan 22, 2021 at 9:36 PM Bin Meng wrote: > > On Tue, Jan 19, 2021 at 9:40 PM Bin Meng wrote: > > > > From: Bin Meng > > > > This v8 series is based on the following 2 versions: > > > > - v5 series sent from Bin > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 > > - v7 series sent from Philippe > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 > > > > This series fixes a bunch of bugs in current implementation of the imx > > spi controller, including the following issues: > > > > - remove imx_spi_update_irq() in imx_spi_reset() > > - chip select signal was not lower down when spi controller is disabled > > - round up the tx burst length to be multiple of 8 > > - transfer incorrect data when the burst length is larger than 32 bit > > - spi controller tx and rx fifo endianness is incorrect > > - remove pointless variable (s->burst_length) initialization (Philippe) > > - rework imx_spi_reset() to keep CONREG register value (Philippe) > > - rework imx_spi_read() to handle block disabled (Philippe) > > - rework imx_spi_write() to handle block disabled (Philippe) > > > > Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 > > (interrupt mode). > > > > Changes in v8: > > - keep the controller disable logic in the ECSPI_CONREG case > > in imx_spi_write() > > Ping? Could we get this applied soon if no more comments? Regards, Bin From MAILER-DAEMON Thu Jan 28 03:25:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l52ce-0007T4-KV for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 03:25:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l52cY-0007PT-Jg for qemu-arm@nongnu.org; Thu, 28 Jan 2021 03:25:44 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:38471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l52cW-00064F-0Q for qemu-arm@nongnu.org; Thu, 28 Jan 2021 03:25:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611822336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d60H5iJE6DqO6YJE0NvquIcUnf8D8LVoXKX3SQW4Pu4=; b=VXUAtpIcVMhZoEMKVQHTwGrD8Yik2b8nMaD8n/2sGLw+Qm5WXj/7TstlPOBK8cdCe8sTVF hw9vglcaZ4WpHrDHtmSB671XVKsR1VzrD+WFQoJaW6zRSaFrLUOEdWUaGpkAjvaWwUfeXN 9UHR3QoUIQnKQRxGwQsgfVXHm7WTTUg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-309-c9VQPkRlOv-QgfpVYq1ZKQ-1; Thu, 28 Jan 2021 03:25:35 -0500 X-MC-Unique: c9VQPkRlOv-QgfpVYq1ZKQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9AB771842140; Thu, 28 Jan 2021 08:25:33 +0000 (UTC) Received: from [10.36.113.217] (ovpn-113-217.ams2.redhat.com [10.36.113.217]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 347C31992D; Thu, 28 Jan 2021 08:25:32 +0000 (UTC) Subject: Re: [PATCH] hw/arm/smmuv3: Fix addr_mask for range-based invalidation To: Zenghui Yu , qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: wanghaibin.wang@huawei.com References: <20201225095015.609-1-yuzenghui@huawei.com> From: Auger Eric Message-ID: <4e114709-e5c2-1860-c760-c05aa3ed5388@redhat.com> Date: Thu, 28 Jan 2021 09:25:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20201225095015.609-1-yuzenghui@huawei.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 08:25:44 -0000 Hi Zenghui, On 12/25/20 10:50 AM, Zenghui Yu wrote: > When performing range-based IOTLB invalidation, we should decode the TG > field into the corresponding translation granule size so that we can pass > the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to > properly emulate the architecture. > > Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") > Signed-off-by: Zenghui Yu Good catch! I tested with older guest kernels though. I wonder how I did not face the bug? > --- > hw/arm/smmuv3.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index bbca0e9f20..65231c7d52 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > { > SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > IOMMUTLBEvent event; > - uint8_t granule = tg; > + uint8_t granule; > > if (!tg) { > SMMUEventInfo event = {.inval_ste_allowed = true}; > @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > return; > } > granule = tt->granule_sz; > + } else { > + guanule = tg * 2 + 10; maybe just init granule to this value above while fixing the typo. Thanks Eric > } > > event.type = IOMMU_NOTIFIER_UNMAP; > From MAILER-DAEMON Thu Jan 28 03:49:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l52zw-0006QV-VD for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 03:49:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l52zv-0006P2-Jd for qemu-arm@nongnu.org; Thu, 28 Jan 2021 03:49:51 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:38457) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l52zt-0005Pi-FA for qemu-arm@nongnu.org; Thu, 28 Jan 2021 03:49:51 -0500 Received: by mail-pg1-x532.google.com with SMTP id o16so3848742pgg.5 for ; Thu, 28 Jan 2021 00:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=45HKNy8WCWZ85KF+zg6eFv2F4jWYn8ochLvmD9tik2A=; b=euVZ3zin8JKLNWj9sD3kyR/aaGs+X6STYIqLK6zWJghX91prPrnhNMz/DCLENGjJQ0 u2UGDidDdbwJQAFefWYY6YbL8hhduMZaGlAlYCCZCVWIf6KzITs1Q6lm+NYtZKUhYaSg cRa9+abo0qhtdsjHsPmQ9jQskdAhukFOaSLvHRjqJts1DZRL+oNYv/cYm6EaypC/3drE 0KidiI0Q0Bye57+b3Bsvw6cg8WDcf1OjojPIhqm+yGW1Jv6uQV2aHIbhNVgfiPvjPbzI LhBcRH4AbQ2nOKzhqnWuFfzeb00s05ac5wxpkxv36xR4RUMsAh3c8gidCGfLXxMZI2fz bXnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=45HKNy8WCWZ85KF+zg6eFv2F4jWYn8ochLvmD9tik2A=; b=VUqm2o/A6ClxM9Wr1Gr3MmfQ8LNh3w8U/DSM8xE8Gg/kKG4X/NvqPpfht6aBQNvqwO 3X0vykR6RebRwlu2G6bS8VTolsyFsBbY978NWtA/Ci0Cm0gdQfo6Hkz0TFUchF58Esod WSOFJakKF6fakQ5Z8m3yNW/t4fKGpnd5gCxoRboC4Q5r7eumuHYcfRZgTv7Js2mdyeE5 ao1BFe9WymyO1LS78zBdMuTc0wMH8/YuPRd9rc4o727crmx63D7w+I+MZ8oB7zy7fZta 3aZzcjIruZOKtKt7NIzipvy9yf4VUj/4z5IbmVoxsnAv9HnRqgyOTnwohaqgqo6cOJZS BF+w== X-Gm-Message-State: AOAM532bOyMc8CJu+aWsKx7rD8XIYcNzsz/Qb5e9zazno1YQNBCb4cFm hXW174e6J0YCunIa1Y8fDU/af/DJ22LdL1LJ X-Google-Smtp-Source: ABdhPJxQ/KagAed0nIPsV7U+svgePfgT/SHnPnWyLG1lbyNXSzVoipxwPaFaIEwIm3euwcRHUYoqGw== X-Received: by 2002:a05:6a00:15c8:b029:1b7:d521:32e9 with SMTP id o8-20020a056a0015c8b02901b7d52132e9mr14663350pfu.22.1611823787585; Thu, 28 Jan 2021 00:49:47 -0800 (PST) Received: from [192.168.3.43] (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm4326994pjn.53.2021.01.28.00.49.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 00:49:46 -0800 (PST) Subject: Re: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error To: Peter Maydell Cc: QEMU Developers , qemu-arm References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-19-richard.henderson@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 27 Jan 2021 22:49:43 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 08:49:51 -0000 On 1/22/21 3:59 AM, Peter Maydell wrote: > On Fri, 15 Jan 2021 at 22:47, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson > > So when does the real kernel report async MTE exceptions to userspace? > The commit message would be a good place to briefly describe the > kernel's strategy and where QEMU differs from it (if anywhere)... I can add that, sure. >> case EXCP_INTERRUPT: >> - /* just indicate that signals should be handled asap */ >> + /* Just indicate that signals should be handled asap. */ >> + check_mte_async_fault(env, &info); >> break; >> case EXCP_UDEF: >> info.si_signo = TARGET_SIGILL; > > So this doesn't guarantee to check the async-fault status on > every exit from cpu_exec(), which means we might miss things. > For instance I think this slightly contrived example would not > ever take the SEGV: > STR x0, [x1] # with a bad tag > YIELD > l: B l > > because the STR and YIELD go into the same TB, the YIELD causes us > to leave the TB with EXCP_YIELD, we don't check for an async fault > in that code path, and then we'll go into the infinite loop and > have nothing to prompt us to come out and look at the async fault flags. I'll add that test case to the smoke test. > Does it work if we just always queue the SEGV on exit from cpu_exec() > and let the signal handling machinery prioritize if we also pend > some other signal because this was an EXCP_UDEF or whatever? > It would be neater if we could keep the fault-check outside the > switch (trapnr) somehow. I would think so. I'll try that. >> +#ifdef CONFIG_USER_ONLY >> + /* >> + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, >> + * which then sends a SIGSEGV when the thread is next scheduled. >> + * This cpu will return to the main loop at the end of the TB, >> + * which is rather sooner than "normal". But the alternative >> + * is waiting until the next syscall. >> + */ >> + qemu_cpu_kick(env_cpu(env)); >> +#endif >> break; > > This does the right thing, but qemu_cpu_kick() is one of those > functions that's in a category of "not used much at all in the > codebase" and which always make me wonder if there's a reason. > (In particular there's exactly one use in the whole of target/ > right now.) I suppose the case of "helper function wants to cause > us to leave the TB loop but not to abort the current insn" is > an unusual one... Exactly. Usually something in target/ calls (via mmio or whatnot) something in hw/ which raises an interrupt, which does the kick. r~ From MAILER-DAEMON Thu Jan 28 05:22:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l54Rf-0001pH-ID for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 05:22:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4y7C-000080-9X for qemu-arm@nongnu.org; Wed, 27 Jan 2021 22:37:02 -0500 Received: from mail-il1-x129.google.com ([2607:f8b0:4864:20::129]:43829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4y79-000120-UI for qemu-arm@nongnu.org; Wed, 27 Jan 2021 22:37:02 -0500 Received: by mail-il1-x129.google.com with SMTP id q5so3969754ilc.10 for ; Wed, 27 Jan 2021 19:36:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=modwiz-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2TvIvkeqlt7iKDLohob+JM0A4aIwF+QFrj6135CGq/o=; b=ezFEoVJlu1HONc/2FSW4Q07HerF6LF49Vt9zLypK7idXSS7Oc7Xu0o4cg/Wt/3+v63 ic+bI2XVf6nreJfLDJFpXMESncFt+UAYOmHbt9Spxoyj+gj5xVsBQdAKFoSJntvA2UbV uY+3zMMFGzkXn4Oz49q6xwSoo8MXhgb3xNwKTkkpavxijm2OJoYI42utYpr3RLJQBBkG ligCLFGfPCWBX7VSvSt/2D3jsVfRyMo02UicHdKkiK96oZhMnEhRaI7dtrHOVugx5xlF 6gTzf9thiByJzpzV/gRgC5gVjK3f2MAbcU63DVU/RoHGVGyvVuwEqha8GnKo6DQEgZbp O2BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2TvIvkeqlt7iKDLohob+JM0A4aIwF+QFrj6135CGq/o=; b=FbExzb+cL4VFC8klNbDzCYqaWGGX9/RxU9tYVzxc28db5Rk/aEEGN01YaaKkKxNqXU RkfFyVt3Zf1e2AvVeWpFkxaMUooqSbevQcCV7eNyjl/7hf50OdrHbiS9CWV0qGFKWLFo 39+GzsVUczo+tMhmHHr7/gGk4t3hundOVAMkB4Sw3+/5x3Jd/dyp6AYTAKVOMDCXeJC9 KFvhbb12edj+fAJruNkdwTuwlyfppOHlOCBDC75jYTtKRk7xwV8UyIUENd9LAe64XXm2 tvkx8gSxA6gs4Pn9WnfQ6gLOH4FRZaN4/wqzmtmgPyjOnP+9YbsjkMJf89sPlxs+q3Zc 8rJg== X-Gm-Message-State: AOAM532ehKG0zZldJa5XMz8+QXXeKnlbENz/jP8EMwibmDw8W1rI2bY1 xxEhJrFKEA81IlAYVUQdWhl3OA== X-Google-Smtp-Source: ABdhPJyRuXKVO4Nfhs0C7249adNGpLhnWPTYeYIQz6xBtvA22uFRfobeQsx+wTdO9v31djWbO11xrQ== X-Received: by 2002:a92:bbcb:: with SMTP id x72mr10897395ilk.104.1611805018277; Wed, 27 Jan 2021 19:36:58 -0800 (PST) Received: from localhost.localdomain (c-98-223-182-45.hsd1.il.comcast.net. [98.223.182.45]) by smtp.gmail.com with ESMTPSA id y1sm1984027ioj.32.2021.01.27.19.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 19:36:57 -0800 (PST) From: Iris Johnson To: Iris Johnson Cc: Igor Mitsyanko , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , qemu-arm@nongnu.org (open list:Exynos), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled Date: Thu, 28 Jan 2021 03:36:55 +0000 Message-Id: <20210128033655.1029577-1-iris@modwiz.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::129; envelope-from=iris@modwiz.com; helo=mail-il1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 28 Jan 2021 05:22:34 -0500 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 03:37:02 -0000 Currently the Exynos 4210 UART code always reports available FIFO space when the backend checks for buffer space. When the FIFO is disabled this is behavior causes the backend chardev code to replace the data before the guest can read it. This patch changes adds the logic to report the capacity properly when the FIFO is not being used. Buglink: https://bugs.launchpad.net/qemu/+bug/1913344 Signed-off-by: Iris Johnson --- hw/char/exynos4210_uart.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index 6361df2ad3..9b21d201b3 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -553,7 +553,11 @@ static int exynos4210_uart_can_receive(void *opaque) { Exynos4210UartState *s = (Exynos4210UartState *)opaque; - return fifo_empty_elements_number(&s->rx); + if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { + return fifo_empty_elements_number(&s->rx); + } else { + return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY); + } } static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) -- 2.25.1 From MAILER-DAEMON Thu Jan 28 05:44:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l54mr-0001Ko-8w for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 05:44:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l54mp-0001K1-Uf for qemu-arm@nongnu.org; Thu, 28 Jan 2021 05:44:27 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:40775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l54mo-0002uP-2J for qemu-arm@nongnu.org; Thu, 28 Jan 2021 05:44:27 -0500 Received: by mail-ej1-x636.google.com with SMTP id gx5so7006951ejb.7 for ; Thu, 28 Jan 2021 02:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hwxWhuPAeBOGG7cxyNlAbfsJe23zd190HfsFXc5SNv0=; b=TT+1b72xpvG43lT3FgHLt1u44+bwNkKZyv7VGVRiYe3vkd+5wEyAr2Hl6IMqJQ/21d P0q+z12TwsxsYsMNSj2p5lUs+dxw6tqgAYKVyK3gFtmzrNtKQIe4kHPoCUBuSFo8wQ83 ljEjCxiEVHMHmspItr7qV7aCFsmOyCVwWwuiBmXWsxLLRhyFfdhQDpTOxmAUm73fqQzd QYZAYpry0GuqhFDKoK+6Ooef2ErvcbRnqYQQJuuaueaglAzehsBJAJQxIOv0WoKQ9NFr lTFlOW0WVJRtooRfYwJMmEgn+davoNwnEccdw1bMS/TWUa75jv7XQqXqHh0HL/W61G+c jsyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hwxWhuPAeBOGG7cxyNlAbfsJe23zd190HfsFXc5SNv0=; b=uXc8tc8H5t8V0bZJEXVQsjsjXdwzOKRvxFK+t9YC2t3VL/4BAbNI4SBBr3BRAKQRp1 U8m+SJYxgJJFGzdqWLwgxjhbM0dKgNJ+3bTWk7IdfKuUO7TWTUbzW95Mc369j1cozu// SE4ikNVIdNZiP8i+kzek0SqyXPKC+EwUXxV2eiUKNSKZlPBlstF0gKAG+ZC3MJUklLLK 6q+ygcBn0G0P4QS2Cvzae4jYHdtyfc9sDOY/JKY+nIecWRQqhaVIMNeciFrXwy/n0DQh hVPFVc6d2MOAo5fKjYRJST+zTJH/Ia3wZOz2P8DyjiIRMzEYSFivz6eHdNTUv/lR+h+j OfJA== X-Gm-Message-State: AOAM533ou+j+r4jca6kSDw+T6u1txTHYMo5wmCKl0ohYra/SFQ19CaDI itxPlkSPs+TCBPaIY19iHJpdpT9HjgD1CpxGwEmAFQ== X-Google-Smtp-Source: ABdhPJxZDsq1yHO8WIHLriNMQdyPFE5TJ2S+pRVK3vGazE9pk4bvAI3GQMZnhgEjq1l0QQSfAJNid67JflJrpdYseew= X-Received: by 2002:a17:906:4002:: with SMTP id v2mr6504423ejj.85.1611830664023; Thu, 28 Jan 2021 02:44:24 -0800 (PST) MIME-Version: 1.0 References: <20210115224645.1196742-1-richard.henderson@linaro.org> <20210115224645.1196742-19-richard.henderson@linaro.org> In-Reply-To: From: Peter Maydell Date: Thu, 28 Jan 2021 10:44:13 +0000 Message-ID: Subject: Re: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error To: Richard Henderson Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 10:44:28 -0000 On Thu, 28 Jan 2021 at 08:49, Richard Henderson wrote: > > On 1/22/21 3:59 AM, Peter Maydell wrote: > > Does it work if we just always queue the SEGV on exit from cpu_exec() > > and let the signal handling machinery prioritize if we also pend > > some other signal because this was an EXCP_UDEF or whatever? > > It would be neater if we could keep the fault-check outside the > > switch (trapnr) somehow. > > I would think so. I'll try that. In particular it seems worth testing whether 'singlestep in gdbstub over an insn that takes an async MTE fault' has reasonable user-facing behaviour. thanks -- PMM From MAILER-DAEMON Thu Jan 28 06:02:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l554a-0000GE-Iw for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:02:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l554Y-0000EG-TP for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:02:46 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:55062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l554W-0000qc-RD for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:02:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611831763; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=a1m/cLEY13tDBo0h/pnmMRjcNA7DsFWhW2/f2XTrp0s=; b=DfJWTj6TqHXXPx4ljIjNyHRdISoA+vYnoJKfqPCFiUIKjrVes7+vZneQ/CGbZnLu315rpe P+aU9EfXYyYaYCByqUaoxyvjixjTIDa+9q1RSz096+hSzYTjQSc2OXSCudBHi/GNTYE074 DyfPfeZR+FfnOf++2nG+n7XcNnnM/Uo= Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-447-JahQdtVxOUafrPTqHpovng-1; Thu, 28 Jan 2021 06:02:41 -0500 X-MC-Unique: JahQdtVxOUafrPTqHpovng-1 Received: by mail-ed1-f71.google.com with SMTP id f21so3009188edx.23 for ; Thu, 28 Jan 2021 03:02:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=a1m/cLEY13tDBo0h/pnmMRjcNA7DsFWhW2/f2XTrp0s=; b=PmR3h0cyX2l0btXDksmrpzQnwhcFuLq0/0s2flROozda1gGF1ZcpvmbaR5TblbdDdP 1ySPcCs3VtnS4rsLkmBrvvgolueY1sJujfoufyAmuI7VIu8X5xkfiSnCMjCLDhxNmtq1 B3LyFq/DJf7hsk+yg52VHJ8tiYZRD0JJcrjlWRvvQeLdhuoyabDQSow3MOyUSxoHvWXU pVqE5pmZ4FgEmNh4/isRQgPE8qg83aOohcu/ZaayNAU+oYhqW9Ki94qncmySMAb9EHqz 3X/Js1jLwRl+kkkf++gqASun8D81nRU/ZD57Izhy0OnrUgIjn8Od5F8fQ1SziMg8XcDt GEGg== X-Gm-Message-State: AOAM530lxohgU4Tck0Tc12D35JnT3E63Dv8IoEwuDx72AjHnE/0CO4+0 fMpxfWWMdF1ADaX6ugDXJnh9Kh4VXSSDg37W6faNYH2k5CyXtmbrtp+tgvUU5fII8wQVMjfCi9l VhaKmZOovNtRR X-Received: by 2002:a50:a684:: with SMTP id e4mr13175049edc.148.1611831760143; Thu, 28 Jan 2021 03:02:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJx5o0yFDHCP7AW+sMzk1kU26igHGH7CIrhoMMQUw8WORBv6tISsBZGWNtT/9Otdx6ekWCpc4w== X-Received: by 2002:a50:a684:: with SMTP id e4mr13175005edc.148.1611831759796; Thu, 28 Jan 2021 03:02:39 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id e27sm2164457ejl.122.2021.01.28.03.02.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 03:02:39 -0800 (PST) Subject: Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2) To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Claudio Fontana Cc: qemu-devel@nongnu.org, Thomas Huth , Paolo Bonzini , Richard Henderson , Fam Zheng , Peter Maydell , kvm@vger.kernel.org, qemu-arm@nongnu.org, Richard Henderson References: <20200929224355.1224017-1-philmd@redhat.com> <87r1m5x56h.fsf@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <98f06a0a-efe6-c630-8e68-0e4559f04d58@redhat.com> Date: Thu, 28 Jan 2021 12:02:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <87r1m5x56h.fsf@linaro.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.308, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:02:47 -0000 Hi Alex, On 1/28/21 1:41 AM, Alex Bennée wrote: > Philippe Mathieu-Daudé writes: > >> Cover from Samuel Ortiz from (part 1) [1]: >> >> This patchset allows for building and running ARM targets with TCG >> disabled. [...] >> >> The rationale behind this work comes from the NEMU project where we're >> trying to only support x86 and ARM 64-bit architectures, without >> including the TCG code base. We can only do so if we can build and run >> ARM binaries with TCG disabled. >> >> v4 almost 2 years later... [2]: >> - Rebased on Meson >> - Addressed Richard review comments >> - Addressed Claudio review comments > > Have you re-based recently because I was having a look but ran into > merge conflicts. I'd like to get the merged at some point because I ran > into similar issues with the Xen only build without TCG. I addressed most of this review comments locally. Since Claudio's accelerator series was getting more attention (and is bigger) I was waiting it gets merged first. He just respun v14: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07171.html From MAILER-DAEMON Thu Jan 28 06:41:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gT-00018I-64 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:41:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gR-000186-E9 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:55 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:53977) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gM-00064q-KY for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:54 -0500 Received: by mail-wm1-x334.google.com with SMTP id j18so4039509wmi.3 for ; Thu, 28 Jan 2021 03:41:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tTX7d0wTHyfDb3yHSiQLS5kIC816/PRSPI9pggN9uSQ=; b=U6h9mXlvHEa6Quw7+J/PAGFrFcbNXNCd6Pe+D1pOJAZ2r741RuJRmCRGM4I/tO15ve /1g1cN0l13+owNXOB+K/+dLAgTw/jljxnGQOOhCw/Ntuf/6bFQ3ATnDqNhrFqE5zkQLi 63bcxtEZ5bC4uqv6WkHD29Z5MFb0WGdylyodKzj/MXynOVoMrQ2pR0g9sU/cV3AZtWwB buTPfsG4h37RxLqNP9JUR0EVHY/RNG4BI6zgvmTl/+qbbT0JwHOQ/nMVsZDGyLoO6LcL 0KFG3e4j6qYV9/M6pGZQh3ZVkMtbBm4JxmIRY3ugi9Xboxl5lqVXnVfUAgUGW3h9KYJx ORxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tTX7d0wTHyfDb3yHSiQLS5kIC816/PRSPI9pggN9uSQ=; b=R2d8pMJl/4VDPyvyAM9ogStfI0GKX91OaUIb/yYsBDmkyBNjPY0Kzg0UuKfWrXp5K8 pJ4yUT05ZOG3NXdyA2+R16Yq2i7p4FDjCykSp276o49Ik/XYUm1hv4pg9R3NyA2M3iyO JlsNMbPeQn34MXn31l6oXjvFmBFqMHadO4YMidd+5wDfXNkYIqLB8jlQSlQBgQKmt17h E2+RCT7f6RReRtgs9bW0jc1MtDVsAQQ8gEUAm2QkBFiVe7LljIsMDZ4koD54g3PXx+hR VXjnGNTkSbqVDdYobl4+6LKQcH51s1V3jER+heVq4MYc8HwtQ6v43EOUMF0fbZZr4/ZJ 1bPg== X-Gm-Message-State: AOAM530lFnLe4CHHHbtrGxaBuj+sIWqsjFtvtyT5OrtUAqvfwxppdnuY 1jLoDFRGsuhSO/V9THuRd73FBE0W5E4b8Q== X-Google-Smtp-Source: ABdhPJxKnlhVFTYMv5mB5XVHF0XNJtOF/6VHoiYCv/+3pbD/LJwOLpXnK6OkvsX55EqVt2tfM6dHHQ== X-Received: by 2002:a7b:c7c8:: with SMTP id z8mr8237331wmk.72.1611834108522; Thu, 28 Jan 2021 03:41:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Date: Thu, 28 Jan 2021 11:41:20 +0000 Message-Id: <20210128114145.20536-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:41:55 -0000 This patchset converts the CMSDK timer, watchdog and dualtimer devices to use the Clock framework instead of an integer property specifying a frequency in Hz. The series is quito a lot of patches but they should be mostly small and I hope easy to review. The motivation here is the upcoming Arm SSE-300 model: this has a new kind of timer device, which I wanted to write in the modern style with a Clock input. That meant the ARMSSE container object needed to know about Clocks, so converting the existing devices it used to Clocks seemed like a good first step. The series as a whole is a migration compat break for the machines involved: mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. v1->v2 changes (all very minor so I have left r-by tags in place): * in test cases, remove set-but-never-used QTestState* variables; gcc warns about these (I did my development with clang, which does not...) (patches 3, 4, 5) * in test cases, consistently phrase clock_step() arguments as calculations based on tick counts and the ns-per-tick value rather than just the final numbers (eg '500 * 40 + 1' instead of '20001') (patches 3, 5) * correct the forward-step amount when looking for periodic timer reload of the dualtimer (patch 5) * actually wire up the ARMSSE MAINCLK callback function (patch 22) The only patch still unreviewed is 5 ("tests: Add a simple test of the CMSDK APB dual timer"). thanks -- PMM Peter Maydell (25): ptimer: Add new ptimer_set_period_from_clock() function clock: Add new clock_has_source() function tests: Add a simple test of the CMSDK APB timer tests: Add a simple test of the CMSDK APB watchdog tests: Add a simple test of the CMSDK APB dual timer hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer hw/timer/cmsdk-apb-timer: Add Clock input hw/timer/cmsdk-apb-dualtimer: Add Clock input hw/watchdog/cmsdk-apb-watchdog: Add Clock input hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" hw/arm/armsse: Wire up clocks hw/arm/mps2: Inline CMSDK_APB_TIMER creation hw/arm/mps2: Create and connect SYSCLK Clock hw/arm/mps2-tz: Create and connect ARMSSE Clocks hw/arm/musca: Create and connect ARMSSE Clocks hw/arm/stellaris: Convert SSYS to QOM device hw/arm/stellaris: Create Clock input for watchdog hw/timer/cmsdk-apb-timer: Convert to use Clock input hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input tests/qtest/cmsdk-apb-watchdog-test: Test clock changes hw/arm/armsse: Use Clock to set system_clock_scale arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS docs/devel/clocks.rst | 16 +++ include/hw/arm/armsse.h | 14 +- include/hw/clock.h | 15 ++ include/hw/ptimer.h | 22 +++ include/hw/timer/cmsdk-apb-dualtimer.h | 5 +- include/hw/timer/cmsdk-apb-timer.h | 34 ++--- include/hw/watchdog/cmsdk-apb-watchdog.h | 5 +- include/qemu/typedefs.h | 1 + hw/arm/armsse.c | 48 +++++-- hw/arm/mps2-tz.c | 14 +- hw/arm/mps2.c | 28 +++- hw/arm/musca.c | 13 +- hw/arm/stellaris.c | 170 +++++++++++++++++------ hw/core/ptimer.c | 34 +++++ hw/timer/cmsdk-apb-dualtimer.c | 53 +++++-- hw/timer/cmsdk-apb-timer.c | 55 ++++---- hw/watchdog/cmsdk-apb-watchdog.c | 29 ++-- tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++ tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++ tests/qtest/cmsdk-apb-watchdog-test.c | 131 +++++++++++++++++ MAINTAINERS | 3 + tests/qtest/meson.build | 3 + 22 files changed, 756 insertions(+), 142 deletions(-) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c create mode 100644 tests/qtest/cmsdk-apb-timer-test.c create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gW-0001AY-Cp for mharc-qemu-arm@gnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/25] clock: Add new clock_has_source() function Date: Thu, 28 Jan 2021 11:41:22 +0000 Message-Id: <20210128114145.20536-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:41:57 -0000 Add a function for checking whether a clock has a source. This is useful for devices which have input clocks that must be wired up by the board as it allows them to fail in realize rather than ploughing on with a zero-period clock. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210121190622.22000-3-peter.maydell@linaro.org --- docs/devel/clocks.rst | 16 ++++++++++++++++ include/hw/clock.h | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 2548d842322..c54bbb82409 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -235,6 +235,22 @@ object during device instance init. For example: /* set initial value to 10ns / 100MHz */ clock_set_ns(clk, 10); +To enforce that the clock is wired up by the board code, you can +call ``clock_has_source()`` in your device's realize method: + +.. code-block:: c + + if (!clock_has_source(s->clk)) { + error_setg(errp, "MyDevice: clk input must be connected"); + return; + } + +Note that this only checks that the clock has been wired up; it is +still possible that the output clock connected to it is disabled +or has not yet been configured, in which case the period will be +zero. You should use the clock callback to find out when the clock +period changes. + Fetching clock frequency/period ------------------------------- diff --git a/include/hw/clock.h b/include/hw/clock.h index 6382f346569..e5f45e2626d 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk); */ void clock_set_source(Clock *clk, Clock *src); +/** + * clock_has_source: + * @clk: the clock + * + * Returns true if the clock has a source clock connected to it. + * This is useful for devices which have input clocks which must + * be connected by the board/SoC code which creates them. The + * device code can use this to check in its realize method that + * the clock has been connected. + */ +static inline bool clock_has_source(const Clock *clk) +{ + return clk->source != NULL; +} + /** * clock_set: * @clk: the clock to initialize. -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gY-0001Fl-H2 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gV-00019S-Ku for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:59 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46072) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gO-000664-Ki for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:59 -0500 Received: by mail-wr1-x432.google.com with SMTP id m13so5043205wro.12 for ; Thu, 28 Jan 2021 03:41:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Rp4YOjE1gcv04Ecoqqv1uDwHaV4/xeO6+AU9Z5cIK8=; b=qgGwCvDyOBuBYSwXrb0TpopTCYOR8WonUDAj5iLrHy49Tk9m6yB+rbYPrmCsemxJWR eITAFuxGsGn1/IYlcWGhUBMBLEBqz0Hak0ser/l/hpeiTZZcCy6e+NIOfTUqABp7VUBV MzQeuVokkm5zkGSV7KuV47WpvGaKo/LT+7y44gCzAE2ICZKYpx4LSjuUCBg3hRtV/rhL fwBkbehmty+RTOH41eVyjOi9BMOcdOizedaLbqfSDuE2rfmVbReVPqUmMu8W8WQTHEcI RRES/f2HeIjZv8plY0rtrjG6ChI1Exz/xdSRRTarHrSiZ+4hZXDux46iOvUfDjl7/ca9 UhEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Rp4YOjE1gcv04Ecoqqv1uDwHaV4/xeO6+AU9Z5cIK8=; b=QYUI0H1hKF72bNMUPWd896by0xrcXZY6gOL5aLtFBEyueWNTONweAfRvj5kcnjytmm Eiuey/CKYIVjVc8RuG04qnuitdsFs12cEqtNP+AZ/CSP3QXQ7vcTqfyBTeXaeUNCZAE8 CLOLZ7xnJjACP07UHHddc2DXylINWcJaQVi3+U93pKgUiuut73eDA2ctS5xEGdCkVGpo Quh0jqT9WSv3u3Ti4yJpGN7sb39KK5+t7E2HmdGFE8X/FoixMbaUnRY+FdOgdw/a77Ku 7CYpjmQ8Sn47NH+Wct01RmqAwXnmEDmLyvUvSCZ1vKHFIedXJQFEzX0l205gdBq22iKp GcUg== X-Gm-Message-State: AOAM533Drjw2nsH1ch8Cy6bTY27n0PlSSemsv8ButvX7PrFcOZQU1SNA zpF/7By9deDwfFJbxBlfkJtpWlYIIkqxDQ== X-Google-Smtp-Source: ABdhPJzC6LiKFB8iB2FcNoeKkiWZV2Q15E3h/Jnh3gPGRYVnSZbX65+ttSRSdyot2JDOwjaUlAfBRQ== X-Received: by 2002:adf:f452:: with SMTP id f18mr15394336wrp.11.1611834111278; Thu, 28 Jan 2021 03:41:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:50 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/25] tests: Add a simple test of the CMSDK APB timer Date: Thu, 28 Jan 2021 11:41:23 +0000 Message-Id: <20210128114145.20536-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:41:59 -0000 Add a simple test of the CMSDK APB timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-4-peter.maydell@linaro.org --- v1->v2 changes: - phrase various clock_step() arguments as calculations based on tick counts and the ns-per-tick value rather than just the final numbers - remove set-but-not-used QTestState *s variable that gcc warns about but clang does not --- tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 77 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-timer-test.c diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c new file mode 100644 index 00000000000..e85e1f7448e --- /dev/null +++ b/tests/qtest/cmsdk-apb-timer-test.c @@ -0,0 +1,75 @@ +/* + * QTest testcase for the CMSDK APB timer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40000000 + +#define CTRL 0 +#define VALUE 4 +#define RELOAD 8 +#define INTSTATUS 0xc + +static void test_timer(void) +{ + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0); + + /* Start timer: will fire after 40 * 1000 == 40000 ns */ + writel(TIMER_BASE + RELOAD, 1000); + writel(TIMER_BASE + CTRL, 9); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 500 + 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0); + + /* VALUE reloads at the following tick */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); + + /* Check write-1-to-clear behaviour of INTSTATUS */ + writel(TIMER_BASE + INTSTATUS, 0); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + writel(TIMER_BASE + INTSTATUS, 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + CTRL, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-timer/timer", test_timer); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 34359a99b8e..6c15f7db317 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h F: include/hw/arm/primecell.h F: hw/timer/cmsdk-apb-timer.c F: include/hw/timer/cmsdk-apb-timer.h +F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h F: hw/char/cmsdk-apb-uart.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8b..74addd74868 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gY-0001GV-PI for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gW-0001B6-KC for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:00 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:37089) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gQ-00066d-V7 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:00 -0500 Received: by mail-wr1-x436.google.com with SMTP id v15so5075698wrx.4 for ; Thu, 28 Jan 2021 03:41:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mIaFFwYWu88wzMmbyHFa8Xtc/F0W8Il5bCeA2Q8j4zA=; b=wXW+7aeri3aliDQPdm1oH5+nD5oSuJ8Jko6uCIgTwcWOBNbtTlFoqvhqqTWsmNqC54 VU5ev76NieFgExEH0RlANm1GB4vFWbXq15FDlTTIuR8q7KY0iRCP4ip4KkyN0Ydp52lz a4jtxJDaNN0brS7Hd6peamz+hMwSEOxLO/iPSOBLGA+R1M7xL3l62vovC42NGH13h7Hj 7DBSoz8JFPIz6uPEHtrKOSRr+aybabPNLP3M68++L9aUGs1ZkLTxLojXLpSRTD/M9mPg JxkYusianzvW30mHX6vIxfUzA9kuuVwa9+RsxMlOy1X1lqw0rYu3Hm1cngPY/gwxPQEo p3Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mIaFFwYWu88wzMmbyHFa8Xtc/F0W8Il5bCeA2Q8j4zA=; b=AYFu+mX+bkpBxvIC7p3yWBBCPlJEbEwToAU50+q/9B1CpdkivqJhTiZ0ocVd0pXPsT ejJBwd4u8V2LZd/093Ao5AOycofb0PDVHmDKQdSjbh5rgGF6zb1DIsFr3kPtthsiD5Kc +o4wm11kgYPhQbI10F9lMnnn4Rxzt3IlxODGt8ZMefPQso9iyuo62BnI6iFKveSbE+0j s5DE1BS1rE3biUFOFtiTCh3P9YxznCsv6i55Pc7BNLqyr37KdN0z+Wh4ELEkM/4zlws9 YL7dDuGTmhz/z7wGxKe1L3qn/UXoO1t/9N7HbuBK16wndPCOZSzDNtyx0prPb3PJbpfC T6yg== X-Gm-Message-State: AOAM533n146I4mrLwowRXs4aYZcz+byH/qP0dLCFjHS+LTV92/1AegkG c5ZXGWpzVIS6HMfA6zywsXU0Y4vURLzffg== X-Google-Smtp-Source: ABdhPJxuoc9onqxPezWfcEbtBJKnZgAjZSEalc1a2X3Y+FQ+0ncj16uIfGIeQVEX1bvvtwBBZpqfXA== X-Received: by 2002:a5d:4391:: with SMTP id i17mr15810545wrq.57.1611834113288; Thu, 28 Jan 2021 03:41:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:52 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/25] tests: Add a simple test of the CMSDK APB dual timer Date: Thu, 28 Jan 2021 11:41:25 +0000 Message-Id: <20210128114145.20536-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:01 -0000 Add a simple test of the CMSDK dual timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Message-id: 20210121190622.22000-6-peter.maydell@linaro.org --- v1->v2 changes: - phrase various clock_step() arguments as calculations based on tick counts and the ns-per-tick value rather than just the final numbers - remove set-but-not-used QTestState *s variable that gcc warns about but clang does not - use 40 * 256 in test_prescale() as suggested by Luc --- tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 132 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c new file mode 100644 index 00000000000..ad6a758289c --- /dev/null +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c @@ -0,0 +1,130 @@ +/* + * QTest testcase for the CMSDK APB dualtimer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40002000 + +#define TIMER1LOAD 0 +#define TIMER1VALUE 4 +#define TIMER1CONTROL 8 +#define TIMER1INTCLR 0xc +#define TIMER1RIS 0x10 +#define TIMER1MIS 0x14 +#define TIMER1BGLOAD 0x18 + +#define TIMER2LOAD 0x20 +#define TIMER2VALUE 0x24 +#define TIMER2CONTROL 0x28 +#define TIMER2INTCLR 0x2c +#define TIMER2RIS 0x30 +#define TIMER2MIS 0x34 +#define TIMER2BGLOAD 0x38 + +#define CTRL_ENABLE (1 << 7) +#define CTRL_PERIODIC (1 << 6) +#define CTRL_INTEN (1 << 5) +#define CTRL_PRESCALE_1 (0 << 2) +#define CTRL_PRESCALE_16 (1 << 2) +#define CTRL_PRESCALE_256 (2 << 2) +#define CTRL_32BIT (1 << 1) +#define CTRL_ONESHOT (1 << 0) + +static void test_dualtimer(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + TIMER1LOAD, 1000); + /* enable in free-running, wrapping, interrupt mode */ + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(500 * 40 + 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); + + /* + * We are in free-running wrapping 16-bit mode, so on the following + * tick VALUE should have wrapped round to 0xffff. + */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER1INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER1CONTROL, 0); +} + +static void test_prescale(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); + + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ + writel(TIMER_BASE + TIMER2LOAD, 1000); + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ + writel(TIMER_BASE + TIMER2CONTROL, + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 256 * 501); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 256 * 500); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); + + /* In periodic mode the tick VALUE now reloads */ + clock_step(40 * 256); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER2INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER2CONTROL, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 3729b89f359..154a91d12e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h +F: tests/qtest/cmsdk-apb-dualtimer-test.c F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 9e2ebc47041..69dd4a8547c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gZ-0001IE-C5 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gT-00018k-GN for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:59 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:36647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gM-00064w-Tm for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:41:57 -0500 Received: by mail-wm1-x333.google.com with SMTP id i9so4316327wmq.1 for ; Thu, 28 Jan 2021 03:41:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XY5Jo/ZT5buRijDwijPJpiWYvfGhsBqb0McwKxae44A=; b=VB7ChyjHAXtZLxKz9QXM8zrfwXDt3JjBoVecDU1V96TuMJBKUZHFDp/L7Qq+v0cwCJ JDlWUl8iWpGr3oNEAvIftDpLi4X+Ulc1l8s/vtPU+IIPyXAUxoq6N/xbQ49CtAzLDjr4 etR0kjNZJFQMR2q/FsXtJER1YnQOOQFjhZ9WIOn9slsGAfv4ULVIgXGJfP201KMpa2Df aBXgqZDPlQxC3xh+HgzYoXUm8u54F8n+5bRfu0oi6hR4qISk8bE6c+aChJAvKc+58dYj sBXNfqEqlrDbzvEUEo1Ktem6zRixqqCty/8+O/m54hGBqpJRXoEZ90+cFDRk2DTD2XSK 9c1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XY5Jo/ZT5buRijDwijPJpiWYvfGhsBqb0McwKxae44A=; b=nBBceBU+ySro51/1vo87XWg8qRgbfI4aONQHbIZ8Wp9TpDtaLsVU4iQOSfoGs5rnl6 +fNG+vlvR4vvV6lkVMalQxZcx/+m/EnFqpwg5jG7IelLjKwquSPjRtbnFf6v6d1YwVsL tn6XvIWt9943RNAuZjlfOaPhzzlGgJlHyS7hzolxkL9CKNhnQec49ir8tUkCyrbKvQ/H E+T7bECWhpR/8JkCOUIKUoym/MhccFQUNfXhxCZ+/lVFOub0Mwfeu+Wwrd6CbSJ7u3Cd Lm6KlcQ/NqBHPghwMOXEibFXVapGAQ/hG8rRp83tFIrviC+vPb/PZwVJszE5FzVBlqse GQtg== X-Gm-Message-State: AOAM530fdm+S6koa7XrZrFhJwKBSm+TjkPoLa5gg3EohAqzg/0MBg48r GvHnhxL7pLuQCvf9BzlZlfjXEuNiMi01Hw== X-Google-Smtp-Source: ABdhPJzRWcHy3OFTZMlNSOx+La/Bdq3k6RUWCVXEer/Vm6gh3RpOfv97vX0ImwLKUeh2luBMqjStRw== X-Received: by 2002:a05:600c:28b:: with SMTP id 11mr3103117wmk.69.1611834109439; Thu, 28 Jan 2021 03:41:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/25] ptimer: Add new ptimer_set_period_from_clock() function Date: Thu, 28 Jan 2021 11:41:21 +0000 Message-Id: <20210128114145.20536-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:41:59 -0000 The ptimer API currently provides two methods for setting the period: ptimer_set_period(), which takes a period in nanoseconds, and ptimer_set_freq(), which takes a frequency in Hz. Neither of these lines up nicely with the Clock API, because although both the Clock and the ptimer track the frequency using a representation of whole and fractional nanoseconds, conversion via either period-in-ns or frequency-in-Hz will introduce a rounding error. Add a new function ptimer_set_period_from_clock() which takes the Clock object directly to avoid the rounding issues. This includes a facility for the user to specify that there is a frequency divider between the Clock proper and the timer, as some timer devices like the CMSDK APB dualtimer need this. To avoid having to drag in clock.h from ptimer.h we add the Clock type to typedefs.h. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-2-peter.maydell@linaro.org --- include/hw/ptimer.h | 22 ++++++++++++++++++++++ include/qemu/typedefs.h | 1 + hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 412763fffb2..c443218475b 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s); */ void ptimer_set_period(ptimer_state *s, int64_t period); +/** + * ptimer_set_period_from_clock - Set counter increment from a Clock + * @s: ptimer to configure + * @clk: pointer to Clock object to take period from + * @divisor: value to scale the clock frequency down by + * + * If the ptimer is being driven from a Clock, this is the preferred + * way to tell the ptimer about the period, because it avoids any + * possible rounding errors that might happen if the internal + * representation of the Clock period was converted to either a period + * in ns or a frequency in Hz. + * + * If the ptimer should run at the same frequency as the clock, + * pass 1 as the @divisor; if the ptimer should run at half the + * frequency, pass 2, and so on. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block. + */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock, + unsigned int divisor); + /** * ptimer_set_freq - Set counter frequency in Hz * @s: ptimer to configure diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 976b529dfb5..68deb74ef6f 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState; typedef struct BusClass BusClass; typedef struct BusState BusState; typedef struct Chardev Chardev; +typedef struct Clock Clock; typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct CPUAddressSpace CPUAddressSpace; diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 2aa97cb665c..6ba19fd9658 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -15,6 +15,7 @@ #include "sysemu/qtest.h" #include "block/aio.h" #include "sysemu/cpus.h" +#include "hw/clock.h" #define DELTA_ADJUST 1 #define DELTA_NO_ADJUST -1 @@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period) } } +/* Set counter increment interval from a Clock */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk, + unsigned int divisor) +{ + /* + * The raw clock period is a 64-bit value in units of 2^-32 ns; + * put another way it's a 32.32 fixed-point ns value. Our internal + * representation of the period is 64.32 fixed point ns, so + * the conversion is simple. + */ + uint64_t raw_period = clock_get(clk); + uint64_t period_frac; + + assert(s->in_transaction); + s->delta = ptimer_get_count(s); + s->period = extract64(raw_period, 32, 32); + period_frac = extract64(raw_period, 0, 32); + /* + * divisor specifies a possible frequency divisor between the + * clock and the timer, so it is a multiplier on the period. + * We do the multiply after splitting the raw period out into + * period and frac to avoid having to do a 32*64->96 multiply. + */ + s->period *= divisor; + period_frac *= divisor; + s->period += extract64(period_frac, 32, 32); + s->period_frac = (uint32_t)period_frac; + + if (s->enabled) { + s->need_reload = true; + } +} + /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gZ-0001Iu-KE for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gY-0001FS-CK for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:02 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:44278) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gS-000671-Ob for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:02 -0500 Received: by mail-wr1-x430.google.com with SMTP id d16so5019448wro.11 for ; Thu, 28 Jan 2021 03:41:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PcyyQtxEfK2y+OFK30UnD/QXT/ftSlQorAj3S+Fk7FE=; b=qfN5rLMp4qA3iy1d2aPpnmztm8v/X2d7qe0H9nmWjWPmXeY6rZ5J6m7V0wdSbr69ZK w3pRDzS4IEulRYFOV5aaHoV6e8n4SfzlH4Kvjl+qLoUO4ED80DQjGWc5dD6O3UMSEMta zYXYTuZxkNEayxxyHDdk+hGrB6QWXV4FM777Z2C6h/Of3wAIt0KZmuBlZSQNPrXehXgv kPqL3h9HaSU+qX5O6Jd0+hMzUD+S/ka66XS/qtJk/rap2Z21uNUF+3ObpBcp0O5SuzV/ QYIV5jr6quUqfqQZh93bnpNT4T8Bjsdt2i1s26j81bklMvb1VkfOezBNdKb7QNwXD0MW Gy1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PcyyQtxEfK2y+OFK30UnD/QXT/ftSlQorAj3S+Fk7FE=; b=hecHu5qeCGDoswN+89HfubkaLgsulAJB8eyL3CVEnHPCPVRb++xJLMs67ijrtVvTSa QKkdghRti8TZl+xBR1USqyoU23e6t3sP9g/rkNGYyMZk6El1stgvRaBCs51z0GeAvoSP Zdg/vrGUwx3MLB7Zh9lFw+zT0AI2v5JuFKZfyr7Bvwbkp74g5+ZsALeEfGp7Dvg/Wgry QhBrIGragFyV8Arlw8VILCz5yIi3X10z/NGaOAgWKoxQogg/0+EXzucFl1FAZCMsnDWn 0KxbMoZddpPfOP0SbKvoezDobuORCF0ymkeMF6jLdG4QtX0jLHsq7H06zvUgzUndS7u9 tdaQ== X-Gm-Message-State: AOAM531TSmoz1seS5aewI01oWeKwMwjEzkMfY2aeZorzsonfpu9BrZTP qqdDOS7NEIQpXEd3XKu/SP4ncqZyixXJUg== X-Google-Smtp-Source: ABdhPJyzWrhXtESTCx/GsjTzMbiCF3IxgSKg4RnIh5De6ekw4KRLvk+jsOqlVEWYx6+VPbWqflOU/w== X-Received: by 2002:a5d:4402:: with SMTP id z2mr15796220wrq.265.1611834115157; Thu, 28 Jan 2021 03:41:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:54 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Date: Thu, 28 Jan 2021 11:41:27 +0000 Message-Id: <20210128114145.20536-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:02 -0000 As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. Since the device doesn't already have a doc comment for its "QEMU interface", we add one including the new Clock. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-8-peter.maydell@linaro.org --- include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++ hw/timer/cmsdk-apb-timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index baa009bb2da..fc2aa97acac 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -15,11 +15,19 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) +/* + * QEMU interface: + * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "pclk": clock for the timer + * + sysbus MMIO region 0: the register bank + * + sysbus IRQ 0: timer interrupt TIMERINT + */ struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; @@ -29,6 +37,7 @@ struct CMSDKAPBTimer { qemu_irq timerint; uint32_t pclk_frq; struct ptimer_state *timer; + Clock *pclk; uint32_t ctrl; uint32_t value; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index ae9c5422540..c63145ff553 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -35,6 +35,7 @@ #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-timer.h" #include "migration/vmstate.h" @@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) @@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_timer_vmstate = { .name = "cmsdk-apb-timer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_CLOCK(pclk, CMSDKAPBTimer), VMSTATE_UINT32(ctrl, CMSDKAPBTimer), VMSTATE_UINT32(value, CMSDKAPBTimer), VMSTATE_UINT32(reload, CMSDKAPBTimer), -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gb-0001MS-1a for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gW-0001AU-AT for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:00 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:40919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gQ-00066M-VN for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:00 -0500 Received: by mail-wm1-x32f.google.com with SMTP id c127so4295934wmf.5 for ; Thu, 28 Jan 2021 03:41:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xHWq9yH9LoFSUmKAgq76pgTL0JY1lWeKpFcupzRjAI4=; b=wW3X6RlvpbSjFvjthZf79H4Yh4JODHixoCCBdBDNa00vko+4W9xDc/ct9G3eV4ffwE 293ioufXEOSj8uC1k/kWkK8xPW/OoCto7IoiT/tACM8/24NQDP636WajW5FSe2cWl82A 1He1iPeqOFCirC0C2fn8x/Iy39BWTbfsymdZoCtz9reoEivCryCX/BqJN57EH2qhIZZT Z2GkS5yCRIqAJREUrPsEPmVoMhq23ztYURerHBK6eGOFYs5UeqsH2C44dNFZRfZ0QQwC uqQoV5GqoE7tjp19Tunj2PYLSq4eA9qCT4A6Ty7vXwdACUJjDcFaPPP5DSlaNe0hgx6c OguA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xHWq9yH9LoFSUmKAgq76pgTL0JY1lWeKpFcupzRjAI4=; b=TfTvDX3Oyl0vSSdHRdV3VHqzh1+D7TTFKhqYIAhjpeNjVYCYVa/dtm03rRfxo/CoYg 0FD+JkCrEUlaeLs89hfo9yVLiHKa1h4F2T8bwPJ8cJwaDXGHOpyPSTPrJjRFYtsRKg9E neyThzZV59jW/0UgLootAymXxMNk6A4cIztJf10uAlA2sqzVB8shF4S0pEkIMnTc+GNf SXkkecYAtaPF0STJxRRlMQNLV1WumUx+Kz/+0ErYj50PaohXSwZBdhlBmS727SXCpU4w cIOeP/+kQ3fJmIeXhIDu3M/3TKiehdRnmV55RjFXQDq71JYEH48RonnyX5xWN1i+BsTo N3bA== X-Gm-Message-State: AOAM5314euLVoPREGJe9ys2ipXvOZKDY2zc0UBQSMHFKLbuDdR6oOwWa WMuKVij4TcNUeaFGN17p30xN0VWRZX6HPQ== X-Google-Smtp-Source: ABdhPJwmQNQF/xojWT0/j+yN41UZ7sTYg7Rz0Y+yiOxSpWx2nTc6m7B1QtwHOM8AScfCe+IxMJCq9w== X-Received: by 2002:a1c:e1d4:: with SMTP id y203mr8375856wmg.50.1611834112248; Thu, 28 Jan 2021 03:41:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/25] tests: Add a simple test of the CMSDK APB watchdog Date: Thu, 28 Jan 2021 11:41:24 +0000 Message-Id: <20210128114145.20536-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:00 -0000 Add a simple test of the CMSDK watchdog, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-5-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- v1->v2 changes: - remove set-but-not-used QTestState *s variable --- tests/qtest/cmsdk-apb-watchdog-test.c | 79 +++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 81 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c new file mode 100644 index 00000000000..950f64c527b --- /dev/null +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -0,0 +1,79 @@ +/* + * QTest testcase for the CMSDK APB watchdog device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz, + * which is 80ns per tick. + */ +#define WDOG_BASE 0x40000000 + +#define WDOGLOAD 0 +#define WDOGVALUE 4 +#define WDOGCONTROL 8 +#define WDOGINTCLR 0xc +#define WDOGRIS 0x10 +#define WDOGMIS 0x14 +#define WDOGLOCK 0xc00 + +static void test_watchdog(void) +{ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(500 * 80 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine lm3s811evb"); + + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 6c15f7db317..3729b89f359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c F: include/hw/watchdog/cmsdk-apb-watchdog.h +F: tests/qtest/cmsdk-apb-watchdog-test.c F: hw/misc/tz-ppc.c F: include/hw/misc/tz-ppc.h F: hw/misc/tz-mpc.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 74addd74868..9e2ebc47041 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx = \ 'npcm7xx_watchdog_timer-test'] qtests_arm = \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gb-0001NG-9d for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gX-0001D6-93 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:01 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:35996) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gS-00066o-2Z for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:00 -0500 Received: by mail-wr1-x42c.google.com with SMTP id 6so5062253wri.3 for ; Thu, 28 Jan 2021 03:41:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4+oOsbOZCzGymS/pjG8axPSCcjrYv7uWaDnLd5easic=; b=RoogCL2v/x29BC0v2NyOztnq84tKwXC7eP9CHyXsYMvelN/RrXCxWNy2sSgtugzp0G 19BSqFE/oKy4CQFlobbXJ2LwoYY/But93FnVH+gEA5Ii7DvzzgBq4m7sblzcVnowNEul X5L638WTTA9FnPTAd4daRLsVUbnVLcVuB4HSDyF4ZO7PnYgU3AuxNqCGrlgJEqqqzmgS 8iybR9dxaFVFHqITjEWOLPoYkfV0cO7UNi8aAl8Uqf/ceXlGJoBk7tySn3SRPrsA/44H 072rB5pcx9bY8c6MpQ2sw2vVlZ2Or4/AwOmg8/SJNaXZ2bqI+1umTELfMiyM+8fee7xB x//g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4+oOsbOZCzGymS/pjG8axPSCcjrYv7uWaDnLd5easic=; b=kro+flJySsrTMnYS8z2vXNoQgXaImJm1Q69K/MVEyRCzLFcJ/t+HKykWVcTPBFZvR9 o7rwzLj+0uhX605YtGT9R/FyYwqgUToCh01YxLvqKX8Fdqab8bFmvW57d0Uy5pjWkWkF 9qjqrFEGih0mwarGFyWNFUS/We2G2pUt15ReTUwKHBfmXprOyLBx32QIp4gV+euimupB Zcjh7UhwXlEQkZICjU7whLpW8MNKHjrJhMlWINHLJFLtGI0Iy9Loi577XOsNuQwCiP2G cPR6V51pgl40j97s2zbziQmamldl/z3ODKAIsmZ/K7RamHaJ/3tnOHZ8offcUnM+F2gq xyUQ== X-Gm-Message-State: AOAM532OpuP9MHhcWggfGRAqfbcQ8ZZlhE2B4bTE7Bvm/MuZV3jIzg9q CN+kecFvXxx38IoTud5wbqNmoOcoMywXuQ== X-Google-Smtp-Source: ABdhPJw4KEIOPxPTCS+L4XGMS5eWFfa34rymJHTNHqLlbJTrSvZhhFeTZ2HGBeZ+xy66RTRx32Ubgg== X-Received: by 2002:a05:6000:1803:: with SMTP id m3mr15567503wrh.34.1611834114303; Thu, 28 Jan 2021 03:41:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:53 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Date: Thu, 28 Jan 2021 11:41:26 +0000 Message-Id: <20210128114145.20536-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:01 -0000 The state struct for the CMSDK APB timer device doesn't follow our usual naming convention of camelcase -- "CMSDK" and "APB" are both acronyms, but "TIMER" is not so should not be all-uppercase. Globally rename the struct to "CMSDKAPBTimer" (bringing it into line with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains as-is because "UART" is an acronym). Commit created with: perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-7-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 6 +++--- include/hw/timer/cmsdk-apb-timer.h | 4 ++-- hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++-------------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 77f86771c30..83f5e28c16e 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -153,9 +153,9 @@ struct ARMSSE { TZPPC apb_ppc0; TZPPC apb_ppc1; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTIMER timer0; - CMSDKAPBTIMER timer1; - CMSDKAPBTIMER s32ktimer; + CMSDKAPBTimer timer0; + CMSDKAPBTimer timer1; + CMSDKAPBTimer s32ktimer; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 0d80b2a48cd..baa009bb2da 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -18,9 +18,9 @@ #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" -OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER) +OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) -struct CMSDKAPBTIMER { +struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f85f1309f37..ae9c5422540 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -67,14 +67,14 @@ static const int timer_id[] = { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; -static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) +static void cmsdk_apb_timer_update(CMSDKAPBTimer *s) { qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); } static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); uint64_t r; switch (offset) { @@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); trace_cmsdk_apb_timer_write(offset, value, size); @@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = { static void cmsdk_apb_timer_tick(void *opaque) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); if (s->ctrl & R_CTRL_IRQEN_MASK) { s->intstatus |= R_INTSTATUS_IRQ_MASK; @@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque) static void cmsdk_apb_timer_reset(DeviceState *dev) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); trace_cmsdk_apb_timer_reset(); s->ctrl = 0; @@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj); memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, s, "cmsdk-apb-timer", 0x1000); @@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj) static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); if (s->pclk_frq == 0) { error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); @@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_PTIMER(timer, CMSDKAPBTIMER), - VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), - VMSTATE_UINT32(value, CMSDKAPBTIMER), - VMSTATE_UINT32(reload, CMSDKAPBTIMER), - VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), + VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_UINT32(ctrl, CMSDKAPBTimer), + VMSTATE_UINT32(value, CMSDKAPBTimer), + VMSTATE_UINT32(reload, CMSDKAPBTimer), + VMSTATE_UINT32(intstatus, CMSDKAPBTimer), VMSTATE_END_OF_LIST() } }; static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), + DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo cmsdk_apb_timer_info = { .name = TYPE_CMSDK_APB_TIMER, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(CMSDKAPBTIMER), + .instance_size = sizeof(CMSDKAPBTimer), .instance_init = cmsdk_apb_timer_init, .class_init = cmsdk_apb_timer_class_init, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:55 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input Date: Thu, 28 Jan 2021 11:41:28 +0000 Message-Id: <20210128114145.20536-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:04 -0000 As the first step in converting the CMSDK_APB_DUALTIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. We take the opportunity to correct the name of the clock input to match the hardware -- the dual timer names the clock which drives the timers TIMCLK. (It does also have a 'pclk' input, which is used only for the register and APB bus logic; on the SSE-200 these clocks are both connected together.) This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-9-peter.maydell@linaro.org --- include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++ hw/timer/cmsdk-apb-dualtimer.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 08d9e6fa3d5..3adbb01dd34 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC * + sysbus IRO 1: timer block 1 interrupt TIMINT1 @@ -28,6 +29,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer" @@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer { MemoryRegion iomem; qemu_irq timerintc; uint32_t pclk_frq; + Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; uint32_t timeritcr; diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index f6534241b94..781b496037b 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "migration/vmstate.h" @@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = { static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { .name = "cmsdk-apb-dualtimer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer), VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER_NUM_MODULES, 1, cmsdk_dualtimermod_vmstate, -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55ge-0001VX-WB for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gb-0001Oa-O4 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:05 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:54488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gV-00068Z-9k for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:05 -0500 Received: by mail-wm1-x32f.google.com with SMTP id u14so4042702wml.4 for ; Thu, 28 Jan 2021 03:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2e1YXz+Q0p/Ws1MZPKR+jaAmbZcN+lIEvqjMORMBP0Q=; b=ojOc5ay+OjcuVNl6T/PWhX8DlCZ+Wmhn5VBAljuFbzDp+5+Us57W+8foaSlIlLqu/w XxOL5KBoT1bAbv5oisrpIRVeYCPpOh+7Rryo4dK41jQT7kAJlAXg4hW0VfcE/gIzJcnB sf7RwHkfCxvpt2ZBJ0hnbYjMhGnC4RAMb6oqrN97zfffhjqcYLe/298/T9rqnFbWuLdc hiSyeRMJeJ6gxFh6YQlZuaNqA1QviPxkEPQgFGy0ddGF2PWv0KRfgZ9N707KilS6gLQY tYiaCkFt5MNUJzMUKZPawlmH/HfoTJhehYuaBHHrhVWut7Bco0iMAiqbfE6QaILwsFZa VopQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2e1YXz+Q0p/Ws1MZPKR+jaAmbZcN+lIEvqjMORMBP0Q=; b=YrEH1v3M+NSZKaYMabGmwJ5+l0Jzub3M7d1SAotd9crQnyN7Yzjbrrn5i5bKM4ahGF 2H5+Dc39CizU8lztIQW2GldHoBRTZlOAW3+x5ShB1yaaKC4QNrNDk3kcKvs8CGz7J6pI S5jRre66OCmSq2DMP2ev9I8qrYWGdtAncuhMFeKlSp49hjGuMugtnLS/oCYNFWBQTA+a 9agp2PI/tV82s8jAOgfIVeDTra1BraoIvQ/kH3G/nYFnbkZ4N9v0cReBvEZD5mgcaPmw tofkmUWKRVCfUxTZdtG78xaLd5ILU8srGj8ltRAMY5f0mapw1rvRW3a3sp+dcZcWiilI HMZg== X-Gm-Message-State: AOAM530gy0E1l3l0WHgBf7gsgHh1k79m8Te2HnmiN4BbS0KvIrbprXDY sEhwfyr/vm3M51OlfZzlzCpFGtgiJftQcg== X-Google-Smtp-Source: ABdhPJxNNN6otN77Uiv6pFE7T8KLXuosHZ3iTvBufhnCyUe7dELCbg1dntmxBEbV+3SNuI85fXzLMA== X-Received: by 2002:a05:600c:22cf:: with SMTP id 15mr8170546wmg.19.1611834117966; Thu, 28 Jan 2021 03:41:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:57 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Date: Thu, 28 Jan 2021 11:41:30 +0000 Message-Id: <20210128114145.20536-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:06 -0000 While we transition the ARMSSE code from integer properties specifying clock frequencies to Clock objects, we want to have the device provide both at once. We want the final name of the main input Clock to be "MAINCLK", following the hardware name. Unfortunately creating an input Clock with a name X creates an under-the-hood QOM property X; for "MAINCLK" this clashes with the existing UINT32 property of that name. Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be deleted. Commit created with: perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-11-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 2 +- hw/arm/armsse.c | 6 +++--- hw/arm/mps2-tz.c | 2 +- hw/arm/musca.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 83f5e28c16e..4860a793f4b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -39,7 +39,7 @@ * QEMU interface: * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK" is the frequency of the main system clock + * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index baac027659d..d2ba0459c44 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -47,7 +47,7 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -59,7 +59,7 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), @@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) } if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK property was not set"); + error_setg(errp, "MAINCLK_FRQ property was not set"); return; } diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3707876d6d4..6a9eed9022a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* diff --git a/hw/arm/musca.c b/hw/arm/musca.c index b50157f63a6..d82bef11cf2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -375,7 +375,7 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gk-0001Y9-BL for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gb-0001MF-0B for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:05 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46073) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gV-00068D-5c for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:04 -0500 Received: by mail-wr1-x432.google.com with SMTP id m13so5043509wro.12 for ; Thu, 28 Jan 2021 03:41:57 -0800 (PST) DKIM-Signature: v=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:56 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input Date: Thu, 28 Jan 2021 11:41:29 +0000 Message-Id: <20210128114145.20536-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:05 -0000 As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the wdogclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-10-peter.maydell@linaro.org --- include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++ hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 3da0d43e355..34069ca6969 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked + * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt * @@ -33,6 +34,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" @@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog { uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; + Clock *wdogclk; uint32_t control; uint32_t intstatus; diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 5bbadadfa68..b03bcb73628 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" @@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_watchdog_vmstate = { .name = "cmsdk-apb-watchdog", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog), VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), VMSTATE_UINT32(control, CMSDKAPBWatchdog), VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gm-0001bC-IT for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gd-0001TH-UL for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:07 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:36641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gW-00068v-H3 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:07 -0500 Received: by mail-wm1-x32b.google.com with SMTP id i9so4316746wmq.1 for ; Thu, 28 Jan 2021 03:41:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2K1kNTbNOMvi2EpXTLd2ToPKEqAh/Wj79aMwJhopKA=; b=JIRT16NxMAt4jGsxudcY7nyUYMc7HdDT7Q62QSd21ojMk9pOd3VdjogA0Bfwddkrxt HOajJg++U+vgKEJejBe1Nub9Xf891Dx5c7HPfNPSpARM7nw2KrrTvnaOwI2Ck5sJz3uf 2MfB56EEp7a5RrepckUYmZcupE0EkyuD9PNvqOAL5BTqsjxy3zs5hFM2pIM2px3YQGjv 3x3EAPGV5aBS4Z5NxZm84WwmsNfMOA4U/ZdrUI/TpY1tqQ4dBRaRi28SUttMaPfYYTug DtRCtSABPS86wjglSopxQA9A+ygw1+buOOXQzKfHChTRJc6t0XIvaFf7iAaIpeU89ea7 lHIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2K1kNTbNOMvi2EpXTLd2ToPKEqAh/Wj79aMwJhopKA=; b=DUAMqTc/9fV5zBwPwoNR6pfWP0v8B9MUmAEl1nRvlQ8NGrMASrRpaCrUsxYs2WBux3 APnZFitosxtOeew0M8+8wB7EtDNGywSI8rTCfdF3vvM6OpDYgfVYPOqv7PDzHNblU+97 Z5PEj2bQW9zLN/Af0kMcj/QWRHw2jqyX1fCbVuT5cqsz/H2do102tIgOka6xsHLoQqpp rL7GwkZKI2Z5Yo1XgmQAa/dHL/OMaii9s5ZIE0mM3+1NxVgZ8Ryn5fZZkDtxTyvvoSVu 001nscv3DQRcfuIIWwO/CFe62MdxkLBVsdXABBf9+daSxoimP1tDInzw6Yde9mBRVeFF 3dTQ== X-Gm-Message-State: AOAM531n4Oc1esi5v/MVWi99XUWffW23tz/U17PZsjpgZgjf8mafQpJC MOp8ADq2lIgt+xdRGTysAY4WbEToAB5nUg== X-Google-Smtp-Source: ABdhPJwZnFECUz1kYZpnn0kXBg33+nbhBxPQKXwu/gMKWDAkeLm35/td7OQ9snPlZo5OzIzPvr/6zw== X-Received: by 2002:a1c:df04:: with SMTP id w4mr8085586wmg.66.1611834118959; Thu, 28 Jan 2021 03:41:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:58 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/25] hw/arm/armsse: Wire up clocks Date: Thu, 28 Jan 2021 11:41:31 +0000 Message-Id: <20210128114145.20536-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:08 -0000 Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-12-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 6 ++++++ hw/arm/armsse.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 4860a793f4b..bfa1e79c4fe 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -37,6 +37,8 @@ * per-CPU identity and control register blocks * * QEMU interface: + * + Clock input "MAINCLK": clock for CPUs and most peripherals + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock @@ -103,6 +105,7 @@ #include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" +#include "hw/clock.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" #include "qom/object.h" @@ -209,6 +212,9 @@ struct ARMSSE { uint32_t nsccfg; + Clock *mainclk; + Clock *s32kclk; + /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d2ba0459c44..4349ce9bfdb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,6 +21,7 @@ #include "hw/arm/armsse.h" #include "hw/arm/boot.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) assert(info->sram_banks <= MAX_SRAM_BANKS); assert(info->num_cpus <= SSE_MAX_CPUS); + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); for (i = 0; i < info->num_cpus; i++) { @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * map its upstream ends to the right place in the container. */ qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; } @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; } @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; } @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * 0x4002f000: S32K timer */ qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; } @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; } @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; } @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; } @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, static const VMStateDescription armsse_vmstate = { .name = "iotkit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(mainclk, ARMSSE), + VMSTATE_CLOCK(s32kclk, ARMSSE), VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() } -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gn-0001bM-QO for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55ge-0001Uj-F4 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:08 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:33203) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gY-00069R-3l for qemu-arm@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:00 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Date: Thu, 28 Jan 2021 11:41:33 +0000 Message-Id: <20210128114145.20536-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:08 -0000 Create a fixed-frequency Clock object to be the SYSCLK, and wire it up to the devices that require it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-14-peter.maydell@linaro.org --- hw/arm/mps2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index f762d1b46af..cd1c215f941 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -46,6 +46,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" +#include "hw/qdev-clock.h" #include "qom/object.h" typedef enum MPS2FPGAType { @@ -84,6 +85,7 @@ struct MPS2MachineState { CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; + Clock *sysclk; }; #define TYPE_MPS2_MACHINE "mps2" @@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* This clock doesn't need migration because it is fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine) TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); @@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, qdev_get_gpio_in(armv7m, 10)); @@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, qdev_get_gpio_in_named(armv7m, "NMI", 0)); -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gr-0001hr-RK for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55ge-0001V5-PV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:10 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:40926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gX-00069B-CL for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:08 -0500 Received: by mail-wm1-x335.google.com with SMTP id c127so4296297wmf.5 for ; Thu, 28 Jan 2021 03:42:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zzVeUuHknztplC3v0ZMbhPlrZqaBQlkBJqvUyi+S9Nc=; b=e4+1aXrcpgs/7tq11fvtF0qHPKXtxuWZqIG+XTkZBwQEIFsWlFr2TNW6QgO9xCDXai xCRHG5M2g+4rKkk7R5aC4CMrNdmGpakSWBxGmZkJtUiYb+ulH9fTDh+90dCuHOepgYJQ WU17zPb9650ehmZeiHDVqWKM8BWiNQgQAZ9aGWTx20XXYkwEOC+emOTdVkpwEkeyHn63 K9Nz2FYlWSDvdGYkBA00rps6VyLnSqizoOtmVIgkMUFT1/9b5jCRdGfEisy1UWDIBPLo JZW1VWql7f2lTN7XSxDhJ047oNyYguH//2svox3C14eGfIZstrD+I5BZj0sNnNHI3bHn svEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zzVeUuHknztplC3v0ZMbhPlrZqaBQlkBJqvUyi+S9Nc=; b=O7h4W4CPhPUOUENWJe5H/jlBs4PTFKNXIleXUXfLMWNgrva8JtOnzuagTqTNy2kSMR dV1q7ESUFAIYogVRuJtXAOGFDgbnoItL0HrVYNEqXIerqAiNuC/atBSiwvxa/MqzQ5uK vUotjjHbZt+BtbVj/Zy1lN0WiBTdQcLjI6j1jOdkIVC9AXYwNvMZkNKPGt/SHYAfNn9v WXSmQ8enzyFikAW3u54f9BIWuFR/RQu3lu14FY36PkuKgHagG0a93Hsj6DU8sofwsjCQ NgBsEE8u9hbC/ti+A9wc16cv/2y5vZkhNNxLIxwYGoSP6pXWY9yZ2Q0wLUzeOAfXuCk0 6Qew== X-Gm-Message-State: AOAM531309tpN39qSmp46BT5hLWMguOtGpmdnzirSJALzERhQABNqnxQ F/O4PDAE3c66N/u04KdDIA0l+BS4SnT8Sw== X-Google-Smtp-Source: ABdhPJwNOtY47otdbGuJq5mXVe795Cc60m244Cs0xEyNnXlrFCwm+dDRMzA/UNLTe9Gzj2CIerz3Jw== X-Received: by 2002:a1c:408b:: with SMTP id n133mr8349999wma.103.1611834119976; Thu, 28 Jan 2021 03:41:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:41:59 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Date: Thu, 28 Jan 2021 11:41:32 +0000 Message-Id: <20210128114145.20536-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:10 -0000 The old-style convenience function cmsdk_apb_timer_create() for creating CMSDK_APB_TIMER objects is used in only two places in mps2.c. Most of the rest of the code in that file uses the new "initialize in place" coding style. We want to connect up a Clock object which should be done between the object creation and realization; rather than adding a Clock* argument to the convenience function, convert the timer creation code in mps2.c to the same style as is used already for the watchdog, dualtimer and other devices, and delete the now-unused convenience function. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-13-peter.maydell@linaro.org --- include/hw/timer/cmsdk-apb-timer.h | 21 --------------------- hw/arm/mps2.c | 18 ++++++++++++++++-- 2 files changed, 16 insertions(+), 23 deletions(-) diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index fc2aa97acac..54f7ec8c502 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -45,25 +45,4 @@ struct CMSDKAPBTimer { uint32_t intstatus; }; -/** - * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER - * @addr: location in system memory to map registers - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate) - */ -static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr, - qemu_irq timerint, - uint32_t pclk_frq) -{ - DeviceState *dev; - SysBusDevice *s; - - dev = qdev_new(TYPE_CMSDK_APB_TIMER); - s = SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, timerint); - return dev; -} - #endif diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 9a8b23c64ce..f762d1b46af 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -83,6 +83,7 @@ struct MPS2MachineState { /* CMSDK APB subsystem */ CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; + CMSDKAPBTimer timer[2]; }; #define TYPE_MPS2_MACHINE "mps2" @@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine) } /* CMSDK APB subsystem */ - cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); - cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); + for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { + g_autofree char *name = g_strdup_printf("timer%d", i); + hwaddr base = 0x40000000 + i * 0x1000; + int irqno = 8 + i; + SysBusDevice *sbd; + + object_initialize_child(OBJECT(mms), name, &mms->timer[i], + TYPE_CMSDK_APB_TIMER); + sbd = SYS_BUS_DEVICE(&mms->timer[i]); + qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); + } + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gu-0001k1-0w for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gk-0001Xy-90 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:15 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:55553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gb-0006BG-9M for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:13 -0500 Received: by mail-wm1-x332.google.com with SMTP id f16so4032163wmq.5 for ; Thu, 28 Jan 2021 03:42:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LwvLOtKV5yAzTDJrixEESRLdwfXbvmLiIYp4SPJcLMI=; b=LXJ3IwdsJPIOEp9hHMKnbhdlN0NedUIcvxzJ8yY5kfq6y5XBoV8baEvJfpILtYawF6 gGcKYoTSj9Rw+sKpJGhcgT6Hf+/p6lGaZGfrB33oEiRpXFicIWcUR5bZble/0/aEdlTv RDGgAVunx9p1bavoe5rvthaKtwto3goQFg28n7z+4y0QnKeMXmhIEDujP0tncw0T6M36 RbZwt8YTUNO46usdG2kGarkg6kFchBAbzBV+Kgk3fmfQ1ZTf3lLCFd/sRkD63r7mTutv 8bO20Ywrg/zZb3jGvFuIKeBoV0BQsiVQ9Dm8hgZUSRdrs4jL3yAf4jtoRHwJsR+TF7vY MlwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LwvLOtKV5yAzTDJrixEESRLdwfXbvmLiIYp4SPJcLMI=; b=P4cD3GMaWJlNGSsdUgFjQhDGoHdktRQCMoFtQLq/F4uUfsKmcZWRLjK+eILGGVKXr0 CaXHu3f7pNGk4NK5Vpl2cfTy5oeTv/QoEFcWpabIOQtyHj2Iqu9giyUmDoWBvxf6Ud2w qF9YTARgrFpaIgZWwyEDFYFTVbaogK1J/ETwkQ1xDy+whlzBBpsBhlBZ7OcY0ov8M1Wx nbQMWX7477fQB1leJFl7o8YF87yUDbUgdutq7AH7PNNT12CtKHKeoqEcBcbmaUiyX3em NhwmGFg4p5Yg8mhsiLjWcGaWZ91u1Nkdz7wTF3jFrkYdYBurrvU3RoCHxOOQ3wyCHF+I Hxxw== X-Gm-Message-State: AOAM530pPS5+6yQTER8KXMekMjwV5x+YtfqHZMonohgFHTmAqWTbED9O UJ08ErX37VEvPYKICG3V0DdEUmyO8vgMOg== X-Google-Smtp-Source: ABdhPJxAWi/QP3//I7OM8fL8etoUZQkeIo02R46PYL3wl2RZw4Pm/jNqP2/qcGN2dftDqj2IBrozDQ== X-Received: by 2002:a05:600c:28b:: with SMTP id 11mr3103900wmk.69.1611834123589; Thu, 28 Jan 2021 03:42:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:03 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/25] hw/arm/stellaris: Convert SSYS to QOM device Date: Thu, 28 Jan 2021 11:41:36 +0000 Message-Id: <20210128114145.20536-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:15 -0000 Convert the SSYS code in the Stellaris boards (which encapsulates the system registers) to a proper QOM device. This will provide us with somewhere to put the output Clock whose frequency depends on the setting of the PLL configuration registers. This is a migration compatibility break for lm3s811evb, lm3s6965evb. We use 3-phase reset here because the Clock will need to propagate its value in the hold phase. For the moment we reset the device during the board creation so that the system_clock_scale global gets set; this will be removed in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-17-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 107 insertions(+), 25 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 652823195b1..0194ede2fe0 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp) /* System controller. */ -typedef struct { +#define TYPE_STELLARIS_SYS "stellaris-sys" +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) + +struct ssys_state { + SysBusDevice parent_obj; + MemoryRegion iomem; uint32_t pborctl; uint32_t ldopctl; @@ -371,11 +376,18 @@ typedef struct { uint32_t dcgc[3]; uint32_t clkvclr; uint32_t ldoarst; + qemu_irq irq; + /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; - qemu_irq irq; - stellaris_board_info *board; -} ssys_state; + uint32_t did0; + uint32_t did1; + uint32_t dc0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; +}; static void ssys_update(ssys_state *s) { @@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = { static int ssys_board_class(const ssys_state *s) { - uint32_t did0 = s->board->did0; + uint32_t did0 = s->did0; switch (did0 & DID0_VER_MASK) { case DID0_VER_0: return DID0_CLASS_SANDSTORM; @@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset, switch (offset) { case 0x000: /* DID0 */ - return s->board->did0; + return s->did0; case 0x004: /* DID1 */ - return s->board->did1; + return s->did1; case 0x008: /* DC0 */ - return s->board->dc0; + return s->dc0; case 0x010: /* DC1 */ - return s->board->dc1; + return s->dc1; case 0x014: /* DC2 */ - return s->board->dc2; + return s->dc2; case 0x018: /* DC3 */ - return s->board->dc3; + return s->dc3; case 0x01c: /* DC4 */ - return s->board->dc4; + return s->dc4; case 0x030: /* PBORCTL */ return s->pborctl; case 0x034: /* LDOPCTL */ @@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void ssys_reset(void *opaque) +static void stellaris_sys_reset_enter(Object *obj, ResetType type) { - ssys_state *s = (ssys_state *)opaque; + ssys_state *s = STELLARIS_SYS(obj); s->pborctl = 0x7ffd; s->rcc = 0x078e3ac0; @@ -661,9 +673,19 @@ static void ssys_reset(void *opaque) s->rcgc[0] = 1; s->scgc[0] = 1; s->dcgc[0] = 1; +} + +static void stellaris_sys_reset_hold(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + ssys_calculate_system_clock(s); } +static void stellaris_sys_reset_exit(Object *obj) +{ +} + static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; @@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = { } }; +static Property stellaris_sys_properties[] = { + DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), + DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), + DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), + DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), + DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), + DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), + DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), + DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), + DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void stellaris_sys_instance_init(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(s); + + memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + static int stellaris_sys_init(uint32_t base, qemu_irq irq, stellaris_board_info * board, uint8_t *macaddr) { - ssys_state *s; + DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - s = g_new0(ssys_state, 1); - s->irq = irq; - s->board = board; /* Most devices come preprogrammed with a MAC address in the user data. */ - s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); - s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); + qdev_prop_set_uint32(dev, "user0", + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); + qdev_prop_set_uint32(dev, "user1", + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); + qdev_prop_set_uint32(dev, "did0", board->did0); + qdev_prop_set_uint32(dev, "did1", board->did1); + qdev_prop_set_uint32(dev, "dc0", board->dc0); + qdev_prop_set_uint32(dev, "dc1", board->dc1); + qdev_prop_set_uint32(dev, "dc2", board->dc2); + qdev_prop_set_uint32(dev, "dc3", board->dc3); + qdev_prop_set_uint32(dev, "dc4", board->dc4); + + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, irq); + + /* + * Normally we should not be resetting devices like this during + * board creation. For the moment we need to do so, because + * system_clock_scale will only get set when the STELLARIS_SYS + * device is reset, and we need its initial value to pass to + * the watchdog device. This hack can be removed once the + * watchdog has been converted to use a Clock input instead. + */ + device_cold_reset(dev); - memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); - memory_region_add_subregion(get_system_memory(), base, &s->iomem); - ssys_reset(s); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s); return 0; } - /* I2C controller. */ #define TYPE_STELLARIS_I2C "stellaris-i2c" @@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = { .class_init = stellaris_adc_class_init, }; +static void stellaris_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->vmsd = &vmstate_stellaris_sys; + rc->phases.enter = stellaris_sys_reset_enter; + rc->phases.hold = stellaris_sys_reset_hold; + rc->phases.exit = stellaris_sys_reset_exit; + device_class_set_props(dc, stellaris_sys_properties); +} + +static const TypeInfo stellaris_sys_info = { + .name = TYPE_STELLARIS_SYS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ssys_state), + .instance_init = stellaris_sys_instance_init, + .class_init = stellaris_sys_class_init, +}; + static void stellaris_register_types(void) { type_register_static(&stellaris_i2c_info); type_register_static(&stellaris_gptm_info); type_register_static(&stellaris_adc_info); + type_register_static(&stellaris_sys_info); } type_init(stellaris_register_types) -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gv-0001kl-U5 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gn-0001bm-Sn for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:18 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:40920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gd-0006Bw-3i for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:16 -0500 Received: by mail-wm1-x32e.google.com with SMTP id c127so4296527wmf.5 for ; Thu, 28 Jan 2021 03:42:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yZ8xu0Lo6T+SwLC4D2n+MG9CZOTMUcUo5Src/38TuZs=; b=g40UFwzgOTp7m7ioPZrkGlaY3gtXHEjV3giEP6Wq40EvOKxWkRsJpy81y164YY8mvF NgeCt/QzrnHr5Py+P8rdaSWwY1LOy6VEzLgzriUOeiBbkF1xQY89QX8TCZzIIkaxdvEI BGZpE9dSabTgaBrDMQ5MjDDOQFY9yng6uJdmUsSFg7y17CXFIeddxEN7djZBJtWnEQ2/ x60YRnj/7Wj+5w6+rYGHG36G2gz2dkLVBr794ekiRiy3oeDNti8Cdx7VAlGoxGNVGlf5 Jd6NKaNbz1MIQx8ec8EHFd4D9StJblj8re7I5ila3zAkXVIu/Wysvfi1Cyj9c54Z4fgH H2vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yZ8xu0Lo6T+SwLC4D2n+MG9CZOTMUcUo5Src/38TuZs=; b=oo19bWvNTVJ8AHDh3aEFkFNvBhiPAyqSLmSRJLZ3TCeY5MOKmyDCKN2vBVPMsmVWQf 43wQ0u9pbfoL5EdMA8sd3q+YmfknaF3MJ3kSBNO8K1ethBPlMq7AOvQ+Kp08wkI1uoBc H03NvS15CxhSratBjeYVHEAvKvmTFQ7kFJfaIKbVrg4twwTa4a+LPdAIKsxIp6oV3vSR Hf2L6d55PSYByWKDfRZ3HNEZBpF0ay1nEIO+Br741G+c/xf2GkhN/QL9G+wsg5AK4nnZ TniiojpS27VWyigb8Ut85McOjqX8ha2Guak4bHvum0oJywR09pJdV2JomqlCYk20Fi5M feeg== X-Gm-Message-State: AOAM5339Q5t5Wc18Ga1skG7yQsAFyXYwJDK6dc24XQXfSogVRQQ5uZXW L2UVWh2ZnspyaajdEBL2S/L+/Tr/iIdjaw== X-Google-Smtp-Source: ABdhPJz3Ju3ClAVHoeEHEAj63UJfFdyGb3g3+9ZFwP4kkh86QQzUk4Ooikt5wxpwqE/mQyVxto6Tug== X-Received: by 2002:a05:600c:2295:: with SMTP id 21mr8506158wmf.133.1611834125570; Thu, 28 Jan 2021 03:42:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:05 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Date: Thu, 28 Jan 2021 11:41:38 +0000 Message-Id: <20210128114145.20536-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:19 -0000 Switch the CMSDK APB timer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-19-peter.maydell@linaro.org --- hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c63145ff553..f053146d88f 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_timer_clk_update(void *opaque) +{ + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", + cmsdk_apb_timer_clk_update, s); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->pclk)) { + error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); return; } @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->pclk_frq); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); ptimer_transaction_commit(s->timer); } -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gw-0001mK-CZ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gp-0001cz-Ul for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:19 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:51594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gd-0006Cg-Uc for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:18 -0500 Received: by mail-wm1-x32b.google.com with SMTP id m2so4050681wmm.1 for ; Thu, 28 Jan 2021 03:42:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lnxZhqtkhnY8r8cAKmASAC+5gwFe5OR+EW9jsx4r30I=; b=joboC/LwkMaPmMA0p5XXNdEhlITVvPRWh/mbxR1x6DbOcuGK0b0EF75nvBhcNs/pTp /vcX3EK8lzL3UDINlkye3e4iO0n490rShzQMstZFXbjGR+iwrfECO9nYTB8mWMWUMZiZ AmVVM6PNPqFEwOAWr2m7Z7hx4LWzU4JhAbKHe0w9wF8136t92n9tQR4IsjU5RNfplWH5 Y/ikC04jsktA72Z2gy/kJ7IWwTk9fe5dannrx0iQK+OAqbz/p67/XO8aRa09TJRUiVkI UsbF4jJl4SSwiXGMQsxHC/uBsjC+aOEyfiV0Cq6s4dZRkFTFqhJgyk5YJ/heNeINqEu7 P92Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lnxZhqtkhnY8r8cAKmASAC+5gwFe5OR+EW9jsx4r30I=; b=GtvZXzPJ5Kfhn44sFE6SwkzVxVFC4uLmYjjBmqizXPaaxeoPhYwtkNowgUe1S4WYfo Dx03VMqYgZhfVMvd/k1F8VOAInZRDXOA0YjtxA4N59Ejs4+eIdXYv5+Dzbkf7X2wCzqZ eZWwUslLJKheOvJF1589boQZxsZY/1zYiwHltMY43qXnGV/+rHxFkcTHotu5VjoQe0Se /2AMdxMFEWTS8H9WHR5rzB4dH0Q84g2uUNTbOpR+URF7Iv7FplOQ7JB5dJZRAzCPMOSP yVSNGpai6gHrofn/xEeJeIBgjpF4aQnxShEpgvhKKyRg0E0h0tFlgqMTmYtoCTN236Ft yUug== X-Gm-Message-State: AOAM531whVfWY/6oh4GAtUmNzQgUq9ZUuHN5f7iyBiZGfWV3u5guYQza OXfir+NyoExcN8Bb/e6qc2uKorHIl40W7Q== X-Google-Smtp-Source: ABdhPJxNY3aGkHTh3kNqtkX4j5acTRG6ZsJ/X74A7CR0MUqL+PKUSt7pS25fzb19DKN/zop/fCfm8Q== X-Received: by 2002:a1c:e043:: with SMTP id x64mr8465245wmg.48.1611834126547; Thu, 28 Jan 2021 03:42:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:05 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input Date: Thu, 28 Jan 2021 11:41:39 +0000 Message-Id: <20210128114145.20536-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:20 -0000 Switch the CMSDK APB dualtimer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-20-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 781b496037b..828127b366f 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) qemu_set_irq(s->timerintc, timintc); } +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) +{ + /* Return the divisor set by the current CONTROL.PRESCALE value */ + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { + case 0: + return 1; + case 1: + return 16; + case 2: + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ + return 256; + default: + g_assert_not_reached(); + } +} + static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, uint32_t newctrl) { @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, default: g_assert_not_reached(); } - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); } if (changed & R_CONTROL_MODE_MASK) { @@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) * limit must both be set to 0xffff, so we wrap at 16 bits. */ ptimer_set_limit(m->timer, 0xffff, 1); - ptimer_set_freq(m->timer, m->parent->pclk_frq); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); ptimer_transaction_commit(m->timer); } @@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) s->timeritop = 0; } +static void cmsdk_apb_dualtimer_clk_update(void *opaque) +{ + CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque); + int i; + + for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { + CMSDKAPBDualTimerModule *m = &s->timermod[i]; + ptimer_transaction_begin(m->timer); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); + ptimer_transaction_commit(m->timer); + } +} + static void cmsdk_apb_dualtimer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } - s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", + cmsdk_apb_dualtimer_clk_update, s); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev); int i; - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->timclk)) { + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected"); return; } -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gw-0001nk-QH for mharc-qemu-arm@gnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:02 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 15/25] hw/arm/musca: Create and connect ARMSSE Clocks Date: Thu, 28 Jan 2021 11:41:35 +0000 Message-Id: <20210128114145.20536-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:13 -0000 Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-16-peter.maydell@linaro.org --- hw/arm/musca.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index d82bef11cf2..a9292482a06 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -33,6 +33,7 @@ #include "hw/misc/tz-ppc.h" #include "hw/misc/unimp.h" #include "hw/rtc/pl031.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MUSCA_NUMIRQ_MAX 96 @@ -82,6 +83,8 @@ struct MuscaMachineState { UnimplementedDeviceState sdio; UnimplementedDeviceState gpio; UnimplementedDeviceState cryptoisland; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MUSCA_MACHINE "musca" @@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) * don't model that in our SSE-200 model yet. */ #define SYSCLK_FRQ 40000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) { @@ -367,6 +372,11 @@ static void musca_init(MachineState *machine) exit(1); } + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, TYPE_SSE200); ssedev = DEVICE(&mms->sse); @@ -376,6 +386,8 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gy-0001rS-3c for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gk-0001ZI-KZ for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:15 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38214) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gZ-00069l-2H for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:14 -0500 Received: by mail-wr1-x429.google.com with SMTP id s7so2069414wru.5 for ; Thu, 28 Jan 2021 03:42:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O5f8WBqu2YhqzoSGVMquOcbgjjk1Qu9h4qYOyq13Wm8=; b=b7J5LXFKzrSQ8q0SFLTNwnCpT61vqHegyEGXdmPMzFYFIaAHWnFMikf8pd8GrRvDY/ 4txoeAtk/Gc8WD3QQV1mZstHhd4tcZZVhsVldeGFhr76I7yb/sfK+1nbCHGEZozoyPFm IGhCt9QgEgfRnULivLaW/QOtOf9bfUxgCtXFppc19CIVeE/S7i7whnvFoAUagKsGZhXR 4mY/ypZq857oxXi6CJ5Asn79aD4H6qncMe4P1XrA8L7Pn6wLXD15dqHVF/x9nd0vBTg2 kOIWz17ku8QRgTlAc0vdYvEs8YoHTgH8ztu9S/ZHc0rwZksh88lkA2ALmE6DmjmRGO/G G/0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O5f8WBqu2YhqzoSGVMquOcbgjjk1Qu9h4qYOyq13Wm8=; b=hAsubf9iOjWVAEM1fSgHhSFfufmXRM/Rjy77qACVOJUDC5B8CEMbQitfOZTic+XC6x /KnZFNi/T3kXNzbtjt8x5EIWIwQ5JS66vb/fxLxgUVUJC+Ws42vEXYCTHBfA0NS2VAi3 ejUzJZAUlrbVjPZGtkCZrwHuL/hePvQD94G9yiOBDwXbbhiPUiMnHsonj43SfmUB/MOK i6or1kjMJpWm1tyDC3tvAw44vHN4hrR9dVMLpRfw5K+05FT+XUAMXTH5Xkl35mNhvbw0 xdDcawjwDyujiTpqdbl6oTcnKnQ4QbQrWZfrUr+caxovp+ynSiXe7T5EvRdeOtmh0olt N+YQ== X-Gm-Message-State: AOAM533cwIGxxtmhaFuvuOMufN5Uwga/sqYtvy54GrN/GUIICJz1MOyi 6Y8ZsdShYo7hYeLUBiVBdNMVfKDgjThrig== X-Google-Smtp-Source: ABdhPJxuQYsXHTew1A+WhgrvfoSifSQ+yd/uvsMPSaEvxDk63vV6O6p+pplkBThTdav7f0pHn0Xg5A== X-Received: by 2002:adf:f452:: with SMTP id f18mr15394981wrp.11.1611834121687; Thu, 28 Jan 2021 03:42:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:01 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Date: Thu, 28 Jan 2021 11:41:34 +0000 Message-Id: <20210128114145.20536-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:15 -0000 Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-15-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6a9eed9022a..7acdf490f28 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -62,6 +62,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/core/split-irq.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MPS2TZ_NUMIRQ 92 @@ -100,6 +101,8 @@ struct MPS2TZMachineState { qemu_or_irq uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 20000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. @@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* These clocks don't need migration because they are fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, mmc->armsse_type); iotkitdev = DEVICE(&mms->iotkit); @@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine) OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gy-0001sj-I0 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gp-0001cl-Qt for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:19 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46272) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gb-0006Bh-SF for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:18 -0500 Received: by mail-wr1-x432.google.com with SMTP id q7so5024106wre.13 for ; Thu, 28 Jan 2021 03:42:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nifpo3xw4kmKoRcteNDK5FWNa7gwn40E7uhxQ3t57k8=; b=DEigW+LNQIRdeoxucN046sw1VoXfBRM18pNoo8A6+BHBR9TUK5qeF4dlxRWWzjEr7H 80y6KtnhiYPa0VXTBE3brhlyA6Mz41OerMSKnbP4viPb8ag18pJprkYqaTFtzhUA50tT 4yHB4CnwTurld1flzO8A+KASgq1gbsAn/hD46StFPyhcd3eHsnPrWSIqq4HCzMQ8dnS/ SczOZfcvG5EdUfVv7PSYi7NK1JRSEHxD313FvBh3yxfEbv7gFUeeb0khhseuYCrAvyd8 9QotK1BHOwTp7hUluDw2BVgledfJHFZe8FuYWCLw8BhHn1FvGpprJhG2/PGMWU4CyOE0 ws9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nifpo3xw4kmKoRcteNDK5FWNa7gwn40E7uhxQ3t57k8=; b=VH6ugMq8Z5aURgblPGUcL3pyhTgT9xZ02e/2YSdh/bYDNwgDPY7IpJzdwIhDVLFBZz NCj65uZoOSShmFrwkgzVJRfCBqMUXsJmVdCUs8xOXGlXDaieK0G/wHg5XSp15Myaer3Q eIbSRFMqBLJjgNt2Y7AddG3TJryQHmrBxHu336QNV46OMah9Gu8zPyvEksySgj3qYobP 4vwmpt/b9goZAo45tYLDTRc0dCEAy2lsZ7H4FGOhqv1K60sp0HfWIYWRGKCqBH3JoOnx fjvU/8keSE+GRbc8cZhJ0GcTlpSJP3YrGiObA3fpY2d/dYsblZQSSQguapRAggoLOkMx ZKjw== X-Gm-Message-State: AOAM530rNGSBlymtS8YW7LgGKJCKOEIRK00LyMeiMyf+D7/eClXFupuj DiHRUf6RpZQr32qz8S7BNE7qBTQphZHFtQ== X-Google-Smtp-Source: ABdhPJzkyTfPAsYlxliSe0yoD7OwC7tGzsvgQaRhbOudnvr9zFibTPWHPqPfdK6lD8w/NHDnSc/4gA== X-Received: by 2002:adf:c6c1:: with SMTP id c1mr6580310wrh.326.1611834124537; Thu, 28 Jan 2021 03:42:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:04 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 17/25] hw/arm/stellaris: Create Clock input for watchdog Date: Thu, 28 Jan 2021 11:41:37 +0000 Message-Id: <20210128114145.20536-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:20 -0000 Create and connect the Clock input for the watchdog device on the Stellaris boards. Because the Stellaris boards model the ability to change the clock rate by programming PLL registers, we have to create an output Clock on the ssys_state device and wire it up to the watchdog. Note that the old comment on ssys_calculate_system_clock() got the units wrong -- system_clock_scale is in nanoseconds, not milliseconds. Improve the commentary to clarify how we are calculating the period. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-18-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 0194ede2fe0..9b67c739ef2 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -26,6 +26,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "cpu.h" #include "qom/object.h" @@ -377,6 +378,7 @@ struct ssys_state { uint32_t clkvclr; uint32_t ldoarst; qemu_irq irq; + Clock *sysclk; /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; @@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s) } /* - * Caculate the sys. clock period in ms. + * Calculate the system clock period. We only want to propagate + * this change to the rest of the system if we're not being called + * from migration post-load. */ -static void ssys_calculate_system_clock(ssys_state *s) +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) { + /* + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input + * clock is 200MHz, which is a period of 5 ns. Dividing the clock + * frequency by X is the same as multiplying the period by X. + */ if (ssys_use_rcc2(s)) { system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); } else { system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); } + clock_set_ns(s->sysclk, system_clock_scale); + if (propagate_clock) { + clock_propagate(s->sysclk); + } } static void ssys_write(void *opaque, hwaddr offset, @@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x070: /* RCC2 */ if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { @@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc2 = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x100: /* RCGC0 */ s->rcgc[0] = value; @@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj) { ssys_state *s = STELLARIS_SYS(obj); - ssys_calculate_system_clock(s); + /* OK to propagate clocks from the hold phase */ + ssys_calculate_system_clock(s, true); } static void stellaris_sys_reset_exit(Object *obj) @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, false); return 0; } @@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = { VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), VMSTATE_UINT32(clkvclr, ssys_state), VMSTATE_UINT32(ldoarst, ssys_state), + /* No field for sysclk -- handled in post-load instead */ VMSTATE_END_OF_LIST() } }; @@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj) memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); } -static int stellaris_sys_init(uint32_t base, qemu_irq irq, - stellaris_board_info * board, - uint8_t *macaddr) +static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, + stellaris_board_info *board, + uint8_t *macaddr) { DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, */ device_cold_reset(dev); - return 0; + return dev; } /* I2C controller. */ @@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) int flash_size; I2CBus *i2c; DeviceState *dev; + DeviceState *ssys_dev; int i; int j; @@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), - board, nd_table[0].macaddr.a); + ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), + board, nd_table[0].macaddr.a); if (board->dc1 & (1 << 3)) { /* watchdog present */ @@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* system_clock_scale is valid now */ uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); + qdev_connect_clock_in(dev, "WDOGCLK", + qdev_get_clock_out(ssys_dev, "SYSCLK")); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55gy-0001tJ-OQ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gq-0001ed-JH for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:20 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gf-0006DI-0e for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:20 -0500 Received: by mail-wr1-x435.google.com with SMTP id s7so2069707wru.5 for ; Thu, 28 Jan 2021 03:42:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:07 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input Date: Thu, 28 Jan 2021 11:41:40 +0000 Message-Id: <20210128114145.20536-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:21 -0000 Switch the CMSDK APB watchdog device over to using its Clock input; the wdogclk_frq property is now ignored. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-21-peter.maydell@linaro.org --- hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index b03bcb73628..9cad0c67da4 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_watchdog_clk_update(void *opaque) +{ + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_watchdog_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); - s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", + cmsdk_apb_watchdog_clk_update, s); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) { CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); - if (s->wdogclk_frq == 0) { + if (!clock_has_source(s->wdogclk)) { error_setg(errp, - "CMSDK APB watchdog: wdogclk-frq property must be set"); + "CMSDK APB watchdog: WDOGCLK clock must be connected"); return; } @@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->wdogclk_frq); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); ptimer_transaction_commit(s->timer); } -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55h0-0001x0-3D for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gs-0001is-7l for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:22 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:36649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gh-0006E7-Sn for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:21 -0500 Received: by mail-wm1-x332.google.com with SMTP id i9so4317269wmq.1 for ; Thu, 28 Jan 2021 03:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dejnN+1TE+bIdVsXEIIkkiDTxwZNugqOzXyFunr0NOY=; b=dpZlRgzdCo/g1pxVEUJCNQOzV46NEadFGZUmVYhIW9hAFmvKTKQcU94WQwsKytPdbh qUxi0VyHrjNdnEUJPrQ4m/oDQtNJmMFwKZsqMU/vnyCbEwBCfcAh9uqA7/kkgaHxItws +WVIge7vcM1La+a4gAzsoiVsDXhodDikSZXOsza+JvOU4+RHfbC1ZvyPh5aCZwMhXLMD 83NMYS1hers4buC3QL1l9qZ78zGIdecZu165rl2AklfMF/Nneaabt3wEzNKXXdfGJz8v KEqUYr/VMwpuRPzIXkIS0VrtSEky6Bpl5RyMgwxAFpTNdCsC2PqVwFkktSZjqMNR1o/Y Vlrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dejnN+1TE+bIdVsXEIIkkiDTxwZNugqOzXyFunr0NOY=; b=fRqLtoJ7R++Cw79H/N5qlHB8WLyWVffMEPvTNbELZGtpo1G4oKG276hiws18BAZGnh b2ZEzh+FSgAfQfTcx41SkmT6J43H7J3kNtJZlufoidKAUdgHgi/yUs7jsDjrYdx2vyyQ A3s7aqjbSxKfSkDrGgnW9+Xe54GKv5/QzBIi8P5PEBMxLs0Wr2I2cjNl9TDxwFE/4IQe PG/ueHR9NV02Maq6Lvy3W3MFnsyaHvEa6z6FCtH+3EkZUvx6seQ3iJR0tFmzzmcuCXPB Mr9I3RMZseRObJyFlIEVbWRHc/R5qF8pSPlbzXggFYmFw7U0Mb2e8Ry+oe3wW/96JXG9 gj2A== X-Gm-Message-State: AOAM531whldhx+oWx94By/6tIUq31HUruD+nKgRpZAUZg019jALRqK3y 3Bp8xLH7iSn0MwUPIvVf+MDLXv2+mOdjUQ== X-Google-Smtp-Source: ABdhPJwL7Q1cQ3eIM2UFET0tMGHQQaq5XHmUf8oxI0T/f47dFyDLfPlCjo/P4qqLyBBdNgJvJOXnEg== X-Received: by 2002:a7b:c08f:: with SMTP id r15mr8407531wmh.22.1611834129473; Thu, 28 Jan 2021 03:42:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:08 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Date: Thu, 28 Jan 2021 11:41:42 +0000 Message-Id: <20210128114145.20536-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:23 -0000 Use the MAINCLK Clock input to set the system_clock_scale variable rather than using the mainclk_frq property. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210121190622.22000-23-peter.maydell@linaro.org --- v1->v2: wire armsse_mainclk_update() up as the Clock callback --- hw/arm/armsse.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4349ce9bfdb..9a6b24c79aa 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } +static void armsse_mainclk_update(void *opaque) +{ + ARMSSE *s = ARM_SSE(opaque); + /* + * Set system_clock_scale from our Clock input; this is what + * controls the tick rate of the CPU SysTick timer. + */ + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); +} + static void armsse_init(Object *obj) { ARMSSE *s = ARM_SSE(obj); @@ -242,7 +252,8 @@ static void armsse_init(Object *obj) assert(info->sram_banks <= MAX_SRAM_BANKS); assert(info->num_cpus <= SSE_MAX_CPUS); - s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", + armsse_mainclk_update, s); s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); @@ -451,9 +462,11 @@ static void armsse_realize(DeviceState *dev, Error **errp) return; } - if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK_FRQ property was not set"); - return; + if (!clock_has_source(s->mainclk)) { + error_setg(errp, "MAINCLK clock was not connected"); + } + if (!clock_has_source(s->s32kclk)) { + error_setg(errp, "S32KCLK clock was not connected"); } assert(info->num_cpus <= SSE_MAX_CPUS); @@ -1115,7 +1128,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; + /* Set initial system_clock_scale from MAINCLK */ + armsse_mainclk_update(s); } static void armsse_idau_check(IDAUInterface *ii, uint32_t address, -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55h1-0001yl-0Q for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gv-0001ka-5U for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:25 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:37093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gk-0006EU-EL for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:24 -0500 Received: by mail-wr1-x436.google.com with SMTP id v15so5076775wrx.4 for ; Thu, 28 Jan 2021 03:42:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jz9NDWJlL3r2GqLKIuRpg/kHH68d8J+FWgxl1TndnRQ=; b=yPyxG9nIm6gNg6JeGYh5/msRrjFyOZV8lfyeQ0rXzuxHON+vvP8rdmJKye8Xzrj4S8 tU5WqH4eY1H6c4smb61/oua1sW49rI7XJhJFKE7kzgMA1CVcKRNKBK1YSkRydvpeR7ZD WM8SL9/V2t5+AWMTJALnW9UNYX33MXSpHmTRmbdBT8BJtJBUbnRh4tLAAJJmSNHIUwJ6 XWJ34n1UaDLLuF+F/Vk3gnIaTj4cN5f+rv6MqXrJ+2K+AtXUVJXpqRKOmJFONQ/Vgn21 OB74Ja73gabYpFgFgoqLMFnuhawT4KA87a6RiM8oP4UJU1HNZ0NikLXrsriv38IfuTVX LpyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jz9NDWJlL3r2GqLKIuRpg/kHH68d8J+FWgxl1TndnRQ=; b=OmC81lI7gWb3rmMTjoYeuS/ZAeD3NOwWlVTeVvLiqAFvDUVo525v7jIBDn12AKhgBz Zc/CLHC6QL399cDM5qtEx0a3NucbdUebAlRtz0pTNuctZv342vHObZ5j3vwtZpHQrRT2 0+24BttWdxFn57MjTF6y6sfwvJqgcYP6+myL5RLI+aApHRy1iVCESaCjDVpdUbffsWiC Yfw9WxVBbluxXvo1FN4aEkM4vmCe/hGH1ZbQJn6wEzA3tvDnv3bJsV9XRMvhCv1lP6pC Qh20ylWV63Hy3HhCe2fGhMEwdXO+Uyjgmj4r3LUuYC9lU/409sgIlvMygftdHoo18aQr 9XaQ== X-Gm-Message-State: AOAM533THyJ3xGgNbUgkfL72yHjFteDV4qAfGJuMEr/WK0RDxwMzmZL8 VPwGbvHPH8RucjZ3PIb0jYnNGz5kaAUETg== X-Google-Smtp-Source: ABdhPJx4cRAZgxDRGWck1+kppNFBsbxdr/TdLyZLk5HkNXsFQMKD+rkhxUsQ6DjFiAPuvy8gjIlBMg== X-Received: by 2002:a5d:6686:: with SMTP id l6mr15715840wru.236.1611834132929; Thu, 28 Jan 2021 03:42:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:10 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 28 Jan 2021 11:41:43 +0000 Message-Id: <20210128114145.20536-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:26 -0000 Remove all the code that sets frequency properties on the CMSDK timer, dualtimer and watchdog devices and on the ARMSSE SoC device: these properties are unused now that the devices rely on their Clock inputs instead. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-24-peter.maydell@linaro.org --- hw/arm/armsse.c | 7 ------- hw/arm/mps2-tz.c | 1 - hw/arm/mps2.c | 3 --- hw/arm/musca.c | 1 - hw/arm/stellaris.c | 3 --- 5 files changed, 15 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9a6b24c79aa..34855e667de 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -727,7 +727,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. */ - qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; @@ -738,7 +737,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; @@ -749,7 +747,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; @@ -908,7 +905,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Devices behind APB PPC1: * 0x4002f000: S32K timer */ - qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; @@ -1002,7 +998,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); - qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; @@ -1013,7 +1008,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ - qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; @@ -1022,7 +1016,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) armsse_get_common_irq_in(s, 1)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); - qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7acdf490f28..90caa914934 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index cd1c215f941..39add416db5 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), name, &mms->timer[i], TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); - qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); @@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); - qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, @@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); - qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a9292482a06..945643c3cd7 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,7 +385,6 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 9b67c739ef2..5acb043a07e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) if (board->dc1 & (1 << 3)) { /* watchdog present */ dev = qdev_new(TYPE_LUMINARY_WATCHDOG); - /* system_clock_scale is valid now */ - uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; - qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); qdev_connect_clock_in(dev, "WDOGCLK", qdev_get_clock_out(ssys_dev, "SYSCLK")); -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55h3-00021J-5e for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gw-0001nG-ME for qemu-arm@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 28 Jan 2021 11:41:44 +0000 Message-Id: <20210128114145.20536-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:27 -0000 Now no users are setting the frq properties on the CMSDK timer, dualtimer, watchdog or ARMSSE SoC devices, we can remove the properties and the struct fields that back them. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-25-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 2 -- include/hw/timer/cmsdk-apb-dualtimer.h | 2 -- include/hw/timer/cmsdk-apb-timer.h | 2 -- include/hw/watchdog/cmsdk-apb-watchdog.h | 2 -- hw/arm/armsse.c | 2 -- hw/timer/cmsdk-apb-dualtimer.c | 6 ------ hw/timer/cmsdk-apb-timer.c | 6 ------ hw/watchdog/cmsdk-apb-watchdog.c | 6 ------ 8 files changed, 28 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index bfa1e79c4fe..676cd4f36b0 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -41,7 +41,6 @@ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to @@ -218,7 +217,6 @@ struct ARMSSE { /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; - uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; bool cpu_fpu[SSE_MAX_CPUS]; diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 3adbb01dd34..f3ec86c00b5 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerintc; - uint32_t pclk_frq; Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 54f7ec8c502..c4c7eae8499 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) /* * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "pclk": clock for the timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: timer interrupt TIMERINT @@ -35,7 +34,6 @@ struct CMSDKAPBTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerint; - uint32_t pclk_frq; struct ptimer_state *timer; Clock *pclk; diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 34069ca6969..c6b3e78731e 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog { /*< public >*/ MemoryRegion iomem; qemu_irq wdogint; - uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; Clock *wdogclk; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 34855e667de..26e1a8c95b6 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -48,7 +48,6 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -60,7 +59,6 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 828127b366f..ef49f5852d3 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { } }; -static Property cmsdk_apb_dualtimer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_dualtimer_realize; dc->vmsd = &cmsdk_apb_dualtimer_vmstate; dc->reset = cmsdk_apb_dualtimer_reset; - device_class_set_props(dc, cmsdk_apb_dualtimer_properties); } static const TypeInfo cmsdk_apb_dualtimer_info = { diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f053146d88f..ee51ce3369c 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { } }; -static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_timer_realize; dc->vmsd = &cmsdk_apb_timer_vmstate; dc->reset = cmsdk_apb_timer_reset; - device_class_set_props(dc, cmsdk_apb_timer_properties); } static const TypeInfo cmsdk_apb_timer_info = { diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 9cad0c67da4..302f1711738 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = { } }; -static Property cmsdk_apb_watchdog_properties[] = { - DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_watchdog_realize; dc->vmsd = &cmsdk_apb_watchdog_vmstate; dc->reset = cmsdk_apb_watchdog_reset; - device_class_set_props(dc, cmsdk_apb_watchdog_properties); } static const TypeInfo cmsdk_apb_watchdog_info = { -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55h4-00021k-Ss for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gv-0001lE-WD for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:26 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:55547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gm-0006G1-KX for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:25 -0500 Received: by mail-wm1-x32a.google.com with SMTP id f16so4032603wmq.5 for ; Thu, 28 Jan 2021 03:42:15 -0800 (PST) DKIM-Signature: v=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Date: Thu, 28 Jan 2021 11:41:45 +0000 Message-Id: <20210128114145.20536-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:26 -0000 Now that the watchdog device uses its Clock input rather than being passed the value of system_clock_scale at creation time, we can remove the hack where we reset the STELLARIS_SYS at board creation time to force it to set system_clock_scale. Instead it will be reset at the usual point in startup and will inform the watchdog of the clock frequency at that point. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-26-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 5acb043a07e..ad72c0959f1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); - /* - * Normally we should not be resetting devices like this during - * board creation. For the moment we need to do so, because - * system_clock_scale will only get set when the STELLARIS_SYS - * device is reset, and we need its initial value to pass to - * the watchdog device. This hack can be removed once the - * watchdog has been converted to use a Clock input instead. - */ - device_cold_reset(dev); - return dev; } -- 2.20.1 From MAILER-DAEMON Thu Jan 28 06:42:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l55h0-0001xd-9W for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 06:42:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l55gs-0001iD-1C for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:22 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44285) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l55gg-0006Dn-E7 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 06:42:21 -0500 Received: by mail-wr1-x435.google.com with SMTP id d16so5020174wro.11 for ; Thu, 28 Jan 2021 03:42:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iLfQwzRXcvknxpkyMmoH4p1ex2pddLgB3eHdSm55wjg=; b=bwwv7KEmATInReiDbCBFcHGyBcUZ53s8dsPWBufV3bWMQiRK96Rof6CB4H9cZZE3Ic M1/mdkrDVgiXxuOZSzAYebUOmo+vsEXWZI3q/GP1sLzeE2YdCiyRqhsWRfM3odUmuGRA YmIFZ2uBbyVgcQxfNacgALYcIhq9UK8pFCD1XucWBBHtbtmoE3cQ7t0PxKMYrU1GofBG AIzAXVkkiSLQanRSAfkgFPWzIXi7hIqXgIYon/TWPDHqE4h3mRvDmWB++otkEHoaeXEu 5t/DE9LCWlDftlTNSf7cBRjNg0TqmxZenqnyW4X1AoNngG625hfUPYTaccT9ItsRK2tG khUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iLfQwzRXcvknxpkyMmoH4p1ex2pddLgB3eHdSm55wjg=; b=m+InaSz6fL2CUKaX1tEDC+JGj+E8sUXIL49AcWmoXd0Dq2CIOMF8X8tva6wM0w9pEA klMuY6R7rVKbCNO/FWsLwQtpDdPBQE1sjrKERRwFs+UBJjFG+GpOVH94eO9ic6UM0mBg XgvM4X17LqQO6QMZRxaSCTL0YHRjIanN3OHNKcUhR5ZLW+oQkmd3FFXDiJmrNMdmZr7A /b9ZEFW58NzR7UrdXo91jFHSOIz74CmygNLEfWMQNAD41KYNo1RhOwF4C3nQbcmGf64w aLxS20q83A86TXegrySagi8ClLPYPCMVC/YhmEvPm7i5qbx+Xqwe2DrveXzXBcMK1LK/ shBQ== X-Gm-Message-State: AOAM5338NUyb9p52QuVFoILeM57EKJ0ur3gfeQ8Ew2+dHT8f7rJCnz+3 nIDMUtYPTx9YIElXv0puzbTr42VclXl7Nw== X-Google-Smtp-Source: ABdhPJyT3RhlRzzrd538Maf2qicyvsTCcWi1bt8LcnmvDCoyl6s0EDNFtTaC1TPzSpS5CsCkjUVfwg== X-Received: by 2002:a5d:4402:: with SMTP id z2mr15797119wrq.265.1611834128404; Thu, 28 Jan 2021 03:42:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q9sm6431033wme.18.2021.01.28.03.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 03:42:07 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Date: Thu, 28 Jan 2021 11:41:41 +0000 Message-Id: <20210128114145.20536-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> References: <20210128114145.20536-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 11:42:23 -0000 Now that the CMSDK APB watchdog uses its Clock input, it will correctly respond when the system clock frequency is changed using the RCC register on in the Stellaris board system registers. Test that when the RCC register is written it causes the watchdog timer to change speed. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-22-peter.maydell@linaro.org --- tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c index 950f64c527b..2710cb17b86 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -15,6 +15,7 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "libqtest-single.h" /* @@ -31,6 +32,11 @@ #define WDOGMIS 0x14 #define WDOGLOCK 0xc00 +#define SSYS_BASE 0x400fe000 +#define RCC 0x60 +#define SYSDIV_SHIFT 23 +#define SYSDIV_LENGTH 4 + static void test_watchdog(void) { g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); @@ -61,6 +67,50 @@ static void test_watchdog(void) g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); } +static void test_clock_change(void) +{ + uint32_t rcc; + + /* + * Test that writing to the stellaris board's RCC register to + * change the system clock frequency causes the watchdog + * to change the speed it counts at. + */ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(80 * 500 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */ + rcc = readl(SSYS_BASE + RCC); + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); + writel(SSYS_BASE + RCC, rcc); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(41); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + int main(int argc, char **argv) { int r; @@ -70,6 +120,8 @@ int main(int argc, char **argv) qtest_start("-machine lm3s811evb"); qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", + test_clock_change); r = g_test_run(); -- 2.20.1 From MAILER-DAEMON Thu Jan 28 07:08:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l566a-0006IR-Iu for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 07:08:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l566W-0006Gt-FE for qemu-arm@nongnu.org; Thu, 28 Jan 2021 07:08:52 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:45769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l566T-0006K5-Jx for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 04:08:47 -0800 (PST) MIME-Version: 1.0 References: <20210125210817.2564212-1-muellerd@fb.com> In-Reply-To: <20210125210817.2564212-1-muellerd@fb.com> From: Peter Maydell Date: Thu, 28 Jan 2021 12:08:36 +0000 Message-ID: Subject: Re: [PATCH] target/arm: Correctly initialize MDCR_EL2.HPMN To: =?UTF-8?Q?Daniel_M=C3=BCller?= Cc: QEMU Developers , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 12:08:52 -0000 On Mon, 25 Jan 2021 at 21:48, muellerd--- via wrote: > > When working with performance monitoring counters, we look at > MDCR_EL2.HPMN as part of the check whether a counter is enabled. This > check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no > counters are "enabled" for < EL2. > That's in violation of the Arm specification, which states that > > > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > > PMCR_EL0.N > > That's also what a comment in the code acknowledges, but the necessary > adjustment seems to have been forgotten when support for more counters > was added. > This change fixes the issue by setting the reset value to PMCR.N, which > is four. > > Signed-off-by: Daniel M=C3=BCller > --- > target/arm/helper.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d2ead3fcbd..195db4d378 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5705,13 +5705,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { > .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, > #endif > /* The only field of MDCR_EL2 that has a defined architectural reset= value > - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; b= ut we > - * don't implement any PMU event counters, so using zero as a reset > - * value for MDCR_EL2 is okay > + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. > */ > { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, > .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, > - .access =3D PL2_RW, .resetvalue =3D 0, > + .access =3D PL2_RW, .resetvalue =3D 4, > .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, > { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, > .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, Rather than having a hardcoded 4 here, could you add a #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ and then use the constant name both in the resetvalue here and also where we currently have 'pmcrn =3D 4' in define_pmu_regs()? thanks -- PMM From MAILER-DAEMON Thu Jan 28 07:11:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l569U-0001Yv-Kb for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 07:11:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l569S-0001Vm-Dd for qemu-arm@nongnu.org; Thu, 28 Jan 2021 07:11:54 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]:44824) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l569P-0007H7-Mr for qemu-arm@nongnu.org; Thu, 28 Jan 2021 07:11:54 -0500 Received: by mail-ed1-x52d.google.com with SMTP id c2so6292589edr.11 for ; Thu, 28 Jan 2021 04:11:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0lWTQBcnDCad8XpdN62W1XLqjcZb1faD1VJFzo+wx5c=; b=jOsWkj1VBqgvLEJNsfW/aIG2I2AEZM94wUeGAvUAKWuQVDW+d0o5T3z3Zc5bwYV+0/ Iv1sCgbVG6hBoJqZJB82GLQv3DYx+b4aflbL1cQFgzY3za6Sky7eRkNODOqNQiqpR6PB VL3IuliHsG90QP7BHUGYb0GAkhAUJ6eG0YuKw3WXU9fBtZkApxF1iyzocSDx2kpgydkg lzHIFLnoHb3QZ330bgr9dPlTwb+b8EZ5mvHK3tcdWnvGuGKmqJlQgvL9kn1dI/bBFOKP R9iPc1Zg/CxOYrA/gUqACCryVq6iTlw1gz8SxaMyECSZ2CibaPmTJ0s5V5GK8oIHU+cb /fIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0lWTQBcnDCad8XpdN62W1XLqjcZb1faD1VJFzo+wx5c=; b=gZbRddb6Q1C8BpJoqA71E1gN+TrIhI67sH0a0+EfatW8FsF7JFqe0USZegyAESuCG3 yqmxwLWMmr6lJmyymHCDlMliyLFvaYSSTXITGD/FJhm8hPYyyX3cKP0yyAQIGH0nPqDe bJ8OR0lUeswOVICKU3fmii/8MmiRrLu96funXEhpYK0tAC/mlB1dhLUHUiwydrgn8gJg wzkm5BFcKHP1jdO+t5pVLBT9HUypNP+D9PRoSAL7Vu6VBmKTrs7dosOdjH8r7OcV2TmW w+/62zq3T6apFJQxdGYHXLBK0toHOhSaGy1OpnQZYWvMeQ2/d21gB+tvnOv4gnzssSJb yDQQ== X-Gm-Message-State: AOAM531aCJdsxNvrJYKj/uqpWNFRDZyLppdQohoRwOaekyNhH1MfGIwb b/6P5dhYPChh1Vk5NI2ZAxN0Ks+7RbBVX0/Kr4eMkQ== X-Google-Smtp-Source: ABdhPJwSUoyImPlO/hkwouKtduzASZ6+PiOhDTWs2l6snrmmf/CYUnaY/yW2CcrI38hekbTDKAM/8VWQcT4saQ7KOm8= X-Received: by 2002:a05:6402:5107:: with SMTP id m7mr13543617edd.52.1611835910179; Thu, 28 Jan 2021 04:11:50 -0800 (PST) MIME-Version: 1.0 References: <20210127011142.2122790-1-wuhaotsh@google.com> In-Reply-To: <20210127011142.2122790-1-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 28 Jan 2021 12:11:38 +0000 Message-ID: Subject: Re: [PATCH v2] hw/misc: Fix arith overflow in NPCM7XX PWM module To: Hao Wu Cc: qemu-arm , QEMU Developers , QEMU Trivial , Havard Skinnemoen , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Doug Evans Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 12:11:54 -0000 On Wed, 27 Jan 2021 at 01:11, Hao Wu wrote: > > Fix potential overflow problem when calculating pwm_duty. > 1. Ensure p->cmr and p->cnr to be from [0,65535], according to the > hardware specification. > 2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1) > can excceed UINT32_MAX, we convert them to uint64_t in computation > and converted them back to uint32_t. > (duty is guaranteed to be <= MAX_DUTY so it won't overflow.) > > Fixes: CID 1442342 > Suggested-by: Peter Maydell > Reviewed-by: Doug Evans > Signed-off-by: Hao Wu > --- Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Thu Jan 28 07:13:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l56Az-0002eP-H6 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 07:13:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l56Av-0002c7-UP for qemu-arm@nongnu.org; Thu, 28 Jan 2021 07:13:27 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:34249) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l56At-0007mP-AP for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 04:13:21 -0800 (PST) MIME-Version: 1.0 References: <20210127232822.3530782-1-f4bug@amsat.org> In-Reply-To: <20210127232822.3530782-1-f4bug@amsat.org> From: Peter Maydell Date: Thu, 28 Jan 2021 12:13:10 +0000 Message-ID: Subject: Re: [PATCH] target/arm: Replace magic value by MMU_DATA_LOAD definition To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Richard Henderson , Joe Komlodi , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 12:13:27 -0000 On Wed, 27 Jan 2021 at 23:28, Philippe Mathieu-Daud=C3=A9 = wrote: > > cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to target-arm.next, thanks. -- PMM From MAILER-DAEMON Thu Jan 28 08:32:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57PP-0008US-OZ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:32:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57PK-0008TT-7h for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:32:26 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]:43357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57PH-000139-Cn for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:32:22 -0500 Received: by mail-ed1-x52d.google.com with SMTP id n6so6592661edt.10 for ; Thu, 28 Jan 2021 05:32:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VCbuhUgseEdIad8g+kRBzhDOBtgRomK/CWVMXG9z46I=; b=ZHCuhA1pfHPUhmCrOZ8pZbPZJA4a31dvwGvdo+Vp3bXo04SyWV0SW1fIhzkqoICYNN Tk0C7E0nt+dTnzkLLhWUSV0k8yQsIVkDjCc6VgAPT4jBeRyJQVoH+Dppih+s+tN2D+XI FHTifIVbtS6HzEfQZ/iqV7gjfCkDQMvY7ep4TZOzsmOudq6oH3wwpVljRIL7ZKimdLE5 2XsbW9Sr0RVBQL98sVsy0HPHR0iM6Z0Gp6S6e7/n7fxRT1sLaAruBW2RCOmvPbbeo6RI VrJCFjtvPD6GQIsvh7JGoqPV1QRJfrv0aZu3elqFOKLredqLsgmgmfKq6NrlWe6mRjPa w96Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VCbuhUgseEdIad8g+kRBzhDOBtgRomK/CWVMXG9z46I=; b=Zb35uxKsZDiSq9P5PDUqkmQEC6aR6haXEtcltLbuJwK/9n0LUgbopH4Pem/UY8KoMm WzvNTj9PJ1hLYtLnb44Ms5zy5+skjKI5tV6+33rKIDDHODrNrTE8avkGSBC/wpVAgGTf eWWE0SplkGMkSLhCDFBBBZ1Gm/QQReWMmWg2VIeyXKJXJFeH3j2ZKeJsNIDwuwtKxTHa Fnq/ELyNF2pR0xF6ME9337XaroMH+bM7CLsPfxHXQOMPnDjBPS81UcKzLUb6cRQ1Oac5 gTQBlhbvO1eRdHlS2eH8J3gPSXMhbAwkLtgLUYvIgy22XUiRbZguboeFVz8rfKsz5sfO tc8g== X-Gm-Message-State: AOAM530k6q5JonD2JwvmBXg7uM6VJzYEhX8hixyokO0EWOHzDOsBihAO BoXZxl3PLpN7Y6hjlxy57lUgrRcrhDCDD7DBbV48Jw== X-Google-Smtp-Source: ABdhPJwRFN8Vvj4rBzEwdtQ9QhJ8BrqAOfexyhaE68IkIGKlwyQRJ2fgY9UyJaz5ILCHbTfqGcfwFLneN5kW4drO7lo= X-Received: by 2002:a05:6402:3514:: with SMTP id b20mr13117066edd.100.1611840737400; Thu, 28 Jan 2021 05:32:17 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-11-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-11-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Thu, 28 Jan 2021 13:32:06 +0000 Message-ID: Subject: Re: [PATCH v8 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:32:26 -0000 On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > From: Bin Meng > > The endianness of data exchange between tx and rx fifo is incorrect. > Earlier bytes are supposed to show up on MSB and later bytes on LSB, > ie: in big endian. The manual does not explicitly say this, but the > U-Boot and Linux driver codes have a swap on the data transferred > to tx fifo and from rx fifo. > > With this change, U-Boot read from / write to SPI flash tests pass. > > => sf test 1ff000 1000 > SPI flash test: > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > Test passed > 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps > 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps > 2 write: 235 ticks, 17 KiB/s 0.136 Mbps > 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Bin Meng Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:34:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57RO-0001RN-4D for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:34:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57RM-0001PA-Mh for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:34:28 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:42065) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57RG-0001g8-OV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:34:24 -0500 Received: by mail-ed1-x529.google.com with SMTP id z22so6615879edb.9 for ; Thu, 28 Jan 2021 05:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=FDbVfjV0OH07Xlau7gYTFjUmJwQAphIIVLwJHzEZa2Y=; b=qUmcW5Jbih0a9zAcxiOt3QM9cabsUqNeXqt2kyevHcZ0KC6ljbTWh9wYgeZgKhixtK ONr6zMMQIoqaar+AidC3HQX6hBmTdkKFgsKaXQNUzydEvBL5C+y2JsJlHyZqBd6ovHDN ASZTdTyAoy5YlFZFRlAKNFDHqFypvP8pJceyP3BaqRKjMEGd4U67slBAdpJyACfND7LS RQqnUPx7LxlQ+Rn/Qfy891eSgg7NXCT75p4UJyfq+Lg+8YOs7SAqoV+rDYpxS7tGOej1 alOVKpnFf05kC7RlC0/lfRJ8UP9EoUgHN2bi3s28fbmP+BOEm6PG76pab/IrP6hyBzvw Lijg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=FDbVfjV0OH07Xlau7gYTFjUmJwQAphIIVLwJHzEZa2Y=; b=Z7FU9LYGU6nH6RTWWM1/DTrH/qKYFgYXJt8vhAe28lVgwDcFXrbBop30u3W+WHqvzE bvn2HQtThsbfrAcUrAzrKIBdHE8aucAIxfnfK84AnFf5MMFz2zrayaslabGjvh1ZSTxb 4SehTz/cAqE/1yayN1gqJOA3FP3sdsmoT3KNNO5kdkPsIrIUNHqvV3DpuD626i0Ltb2Q 9pZFDwCydTBg3jJvTqYNZrBKqWvw1p0sc39oTKfiZXL8W98s6BW0OiXe2MUX/ZnBGi5i 5HxikCgRBBosbzyCQxozpAK1mnJtNZA3tOdtJ9qtghhCGNZl6virZBLH0wGUWhTJ4Gjp 2FPA== X-Gm-Message-State: AOAM533eo7DTgqA2FL8tOAizK5XDOnnPqYXy79DNs//FtmwLFtclecTu QI2eQoGMpvCAI6WEiEF7EoQUM02UcR/h5N9GV5BoHg== X-Google-Smtp-Source: ABdhPJztztM2F9WUrSF8YR9QC8W0qoAWl5dgpEQDXq+q00x7eiCeo8PgmwHPS87uhjDJscImVqiCWT534Mw7OOGH+sw= X-Received: by 2002:aa7:c88a:: with SMTP id p10mr14092231eds.204.1611840859716; Thu, 28 Jan 2021 05:34:19 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-7-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-7-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Thu, 28 Jan 2021 13:34:08 +0000 Message-ID: Subject: Re: [PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:34:28 -0000 On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > From: Philippe Mathieu-Daud=C3=A9 > > When the block is disabled, only the ECSPI_CONREG register can > be modified. Setting the EN bit enabled the device, clearing it > "disables the block and resets the internal logic with the > exception of the ECSPI_CONREG" register. > > Ignore all other registers write except ECSPI_CONREG when the > block is disabled. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> > Signed-off-by: Bin Meng Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:35:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57S9-0001xA-H7 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:35:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57S7-0001ud-SL for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:35:15 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:45039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57S4-0001yC-GS for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 05:35:10 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-3-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-3-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Thu, 28 Jan 2021 13:34:59 +0000 Message-ID: Subject: Re: [PATCH v8 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:35:16 -0000 On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > From: Bin Meng > > Usually the approach is that the device on the other end of the line > is going to reset its state anyway, so there's no need to actively > signal an irq line change during the reset hook. > > Move imx_spi_update_irq() out of imx_spi_reset(), to a new function > imx_spi_soft_reset() that is called when the controller is disabled. > > Signed-off-by: Bin Meng > > --- Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:38:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57VJ-0004Nu-V7 for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id hr31sm2251528ejc.125.2021.01.28.05.38.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 05:38:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 05/25] tests: Add a simple test of the CMSDK APB dual timer To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel References: <20210128114145.20536-1-peter.maydell@linaro.org> <20210128114145.20536-6-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 28 Jan 2021 14:38:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210128114145.20536-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:38:31 -0000 On 1/28/21 12:41 PM, Peter Maydell wrote: > Add a simple test of the CMSDK dual timer, since we're about to do > some refactoring of how it is clocked. > > Signed-off-by: Peter Maydell > Message-id: 20210121190622.22000-6-peter.maydell@linaro.org > --- > v1->v2 changes: > - phrase various clock_step() arguments as calculations > based on tick counts and the ns-per-tick value rather > than just the final numbers > - remove set-but-not-used QTestState *s variable > that gcc warns about but clang does not > - use 40 * 256 in test_prescale() as suggested by Luc > --- > tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 132 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 28 08:39:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57Vx-0005UH-O2 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:39:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57Vw-0005SF-1l; Thu, 28 Jan 2021 08:39:12 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:34251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57Vu-0003Wx-Hw; Thu, 28 Jan 2021 08:39:11 -0500 Received: by mail-ed1-x536.google.com with SMTP id d22so6651852edy.1; Thu, 28 Jan 2021 05:39:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=GalHh1nXX/ke6QiaqUZyT8gQDYgzmnIJasDVOmD5Myw=; b=CBN3fsIWN0plqp10muuts+B0I9D5H24ZmGpHrlVAifI6ORGEoOEqhYFoxB9Bf5sbZN PfqRdH19hTU9J8rl/O9ZS6yx4D+J7Ku/6qheE2Ogq8wVFedioWIBYZMN6AZvd9L52+Lh PhRu+em4rKYvpS/e8q6KJjxGgv+FLBtr6r1IPBQyrF14eQx3e5LguenU0XrC6cKjVttV xkG8DnF4gBzqPEJCTYexG1d8FVt9Mwca9+9t4dPrak/FeniitEcO+UDkfiFGwDm44kNM Eunmf9i77aHW6ihjzw39L3X01Ra0PZzbTe3bE10YEaYNYMie67WLf4AiEPaPc7yg50nq Z3Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=GalHh1nXX/ke6QiaqUZyT8gQDYgzmnIJasDVOmD5Myw=; b=nubDYVwVnvlFBGXMdpwsW4/cwmVo2SvEbAIt+M8qQ8rR4MWjmfv5+Qs7Kqb6vHXbvk J8cHUvuCO+kizD+ukZ5Cl+N5XtLtL1t1mCOHCmb2QJ2YXbNIRRz4r1FrUnWlWmhF5k5F bOPvaLhxLCKzpklUNxxO2pmqXZ8eYHo/t7ll8hWpnbUDwF0oZXPMrEjGTEL5Vie8ZRzX lEAkPLEmk3zXtaOoCxmkyvh3GAAo/SGbI2/ilI5RkPxTlPUoFFHZMBbJVraJRzj70nwg rKCImXxzGD+s7R3yA3Chd46qyAz0VFM0QjsRSPu1p3GkZaPy84UQVWvr+VHXeLRLgwuz xrLw== X-Gm-Message-State: AOAM531uvPhcDFRidzUcpbrNXZllrrn7ZxZ8lRfG6mi2ZILBTOIkmWZt L7VTbMQKec4rWYlIO/iPcKc= X-Google-Smtp-Source: ABdhPJz1WmlVkzQcctkaPcPqjqo4NepMuckJvWOnDmjmQZzK/dzM8yU3ilS3CmEJJRalSnRqMbPtWg== X-Received: by 2002:a50:998f:: with SMTP id m15mr14286953edb.342.1611841148872; Thu, 28 Jan 2021 05:39:08 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u9sm3044084edv.32.2021.01.28.05.39.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 05:39:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel References: <20210128114145.20536-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <1394f5e0-d80a-a61f-9e59-325de416402b@amsat.org> Date: Thu, 28 Jan 2021 14:39:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210128114145.20536-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:39:12 -0000 On 1/28/21 12:41 PM, Peter Maydell wrote: > This patchset converts the CMSDK timer, watchdog and dualtimer devices > to use the Clock framework instead of an integer property specifying > a frequency in Hz. The series is quito a lot of patches but they > should be mostly small and I hope easy to review. > > The motivation here is the upcoming Arm SSE-300 model: this has a > new kind of timer device, which I wanted to write in the modern style > with a Clock input. That meant the ARMSSE container object needed > to know about Clocks, so converting the existing devices it used > to Clocks seemed like a good first step. > > The series as a whole is a migration compat break for the machines > involved: mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, > mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. > > v1->v2 changes (all very minor so I have left r-by tags in place): > * in test cases, remove set-but-never-used QTestState* variables; gcc > warns about these (I did my development with clang, which does not...) > (patches 3, 4, 5) > * in test cases, consistently phrase clock_step() arguments as calculations > based on tick counts and the ns-per-tick value rather than just the final > numbers (eg '500 * 40 + 1' instead of '20001') (patches 3, 5) > * correct the forward-step amount when looking for periodic timer reload > of the dualtimer (patch 5) > * actually wire up the ARMSSE MAINCLK callback function (patch 22) > > The only patch still unreviewed is 5 ("tests: Add a simple test of the > CMSDK APB dual timer"). > > thanks > -- PMM > > Peter Maydell (25): > ptimer: Add new ptimer_set_period_from_clock() function > clock: Add new clock_has_source() function > tests: Add a simple test of the CMSDK APB timer > tests: Add a simple test of the CMSDK APB watchdog > tests: Add a simple test of the CMSDK APB dual timer > hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer > hw/timer/cmsdk-apb-timer: Add Clock input > hw/timer/cmsdk-apb-dualtimer: Add Clock input > hw/watchdog/cmsdk-apb-watchdog: Add Clock input > hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" > hw/arm/armsse: Wire up clocks > hw/arm/mps2: Inline CMSDK_APB_TIMER creation > hw/arm/mps2: Create and connect SYSCLK Clock > hw/arm/mps2-tz: Create and connect ARMSSE Clocks > hw/arm/musca: Create and connect ARMSSE Clocks > hw/arm/stellaris: Convert SSYS to QOM device > hw/arm/stellaris: Create Clock input for watchdog > hw/timer/cmsdk-apb-timer: Convert to use Clock input > hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input > hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input > tests/qtest/cmsdk-apb-watchdog-test: Test clock changes > hw/arm/armsse: Use Clock to set system_clock_scale > arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, > ARMSSE > arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE > hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Tested-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 28 08:43:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57aN-0008Nz-JA for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:43:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57aM-0008N6-3Y for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:43:46 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:40775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57aG-00058M-W3 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:43:44 -0500 Received: by mail-ed1-x535.google.com with SMTP id a14so6655908edu.7 for ; Thu, 28 Jan 2021 05:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=r7rNPgL1Ipu5c9ziAcfsbd0SJejsrIOuX3XIPzLBs+k=; b=CN/2gl0vnv1W/ulWUI46Z+5w1rK8RznnK3v9SnHybhaC93viD/bSFaJKmyuuB5TIHx xZe5BnbRL616Pj0vwhksosiJ1P+d+n4P6GK+aHWHWTfx9Evt+/rLkiwZ7mrizUzKDwhn +hPFQGbFWNrFxtHKrCPx2aadYeCKe6UBNu95XkMn8ATTtHDKVOUO0T921oq5l0pKZrdK boNLdOiCYZRKW5e7Jq+SMkRxYFhC7Y4VL8lGrQ5PKQ+zpmUj42N/oov03VdyuCKeg86N pKFhxzStnRI7NbeqEDOnTfKT7maHi6Y11p13oKmVW1k/ApNT+URjwO3LB7H4AMTCGL6V yoQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=r7rNPgL1Ipu5c9ziAcfsbd0SJejsrIOuX3XIPzLBs+k=; b=Bh3nydepfNQxh0Qg2zpMggQCBmibpshaGejMKy78eUV8VY50o0prKHw7W92wEn8i9S OyPmj4J3EQ2NmbTvCrPlfNPHPPeQ70/x6YYo3LOMNVhbv2d9Rw9ZScCJNnzKjJzWjZRX SLjoiQ+ogQ+r6Nwst7WJJfbRxBbT8350EosB4nmblTBaZgOSM52vP3wdGU9jaXzmnEMW sHzi57uWGzftBQkltG+B9XpEkbhZkNoBiHTHIQbhQhh6I0NY/VGSlzhBjY/AcnkEdHuW s+CFYMxjfxqCaCOK6EOJih6ZXQdEA5PnW1N/DlThUqe8SeE66lKNCPeCI0rX6fh1FWm9 e/KQ== X-Gm-Message-State: AOAM530VIyhGJfZsY49t2ijiDiWi44i5CUTBlQlnbUcrys7vQcBOE95G CGDnzawb/KpP5DV/Dw8evoDp8UpXWtiWMVXa2BaJ9g== X-Google-Smtp-Source: ABdhPJwa9bdHeDo6Bz+8ClMqkSCkwuTDug3WX70J3d+XC96EZLmLSbh3gVV6XOXipTiVzSRQZwiQc6JguOPASdgx3uc= X-Received: by 2002:a05:6402:b2f:: with SMTP id bo15mr14552012edb.146.1611841417952; Thu, 28 Jan 2021 05:43:37 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Thu, 28 Jan 2021 13:43:26 +0000 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:43:46 -0000 On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > From: Philippe Mathieu-Daud=C3=A9 > > When the block is disabled, all registers are reset with the > exception of the ECSPI_CONREG. It is initialized to zero > when the instance is created. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 8fb3c9b..c952a3d 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > static void imx_spi_reset(DeviceState *dev) > { > IMXSPIState *s =3D IMX_SPI(dev); > + int i; > > DPRINTF("\n"); > > - memset(s->regs, 0, sizeof(s->regs)); > - > - s->regs[ECSPI_STATREG] =3D 0x00000003; > + for (i =3D 0; i < ARRAY_SIZE(s->regs); i++) { > + switch (i) { > + case ECSPI_CONREG: > + /* CONREG is not updated on reset */ > + break; > + case ECSPI_STATREG: > + s->regs[i] =3D 0x00000003; > + break; > + default: > + s->regs[i] =3D 0; > + break; > + } > + } This retains the CONREG register value for both: * 'soft' reset caused by write to device register to disable the block -- this is corrcet as per the datasheet quote * 'power on' reset via TYPE_DEVICE's reset method -- but in this case we should reset CONREG, because the Device reset method is like a complete device powercycle and should return the device state to what it was when QEMU was first started. thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:47:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57dc-0001oA-R5 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:47:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57db-0001o0-BV; Thu, 28 Jan 2021 08:47:07 -0500 Received: from mail-yb1-xb35.google.com ([2607:f8b0:4864:20::b35]:34268) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57dZ-0006LC-M7; Thu, 28 Jan 2021 08:47:07 -0500 Received: by mail-yb1-xb35.google.com with SMTP id v200so5515638ybe.1; Thu, 28 Jan 2021 05:47:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=PHspNHzClM8kdz38xYtmQHS4+REVO2x57FezXCH/BDY=; b=f2zk0rJ3y1T9Q5ofdFORrWHD2Eg1flxm9ae2fdqc3kTTx2hdAbtheSeHZ/EElg6Be5 PrraepRJgssyG0krnl7gtpdIGEOQcQJ7HzGcN65lFi+e/sp840P4yMVVMDt3/TbPVqcg F7IUqcUFxkOAZ6jQ294iLxbrXPTzq8ibf2GQMW5euAu+AKvWS64izUgPosFOw5ng2EHj NSrnfw17tWQO4OuaD3/bRTrgpT4WstEn4jwYbU26YUMmTUhquDDH+/0qPQC9YmDmfatj IfmgDz+Pvr+WJ4wXe5K9hYk3Fi6LK7XEyvVId663HU0lUwSagqMtQzP9ORSpwsSYkby3 OvHQ== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:47:07 -0000 On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell wr= ote: > > On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > > > From: Philippe Mathieu-Daud=C3=A9 > > > > When the block is disabled, all registers are reset with the > > exception of the ECSPI_CONREG. It is initialized to zero > > when the instance is created. > > > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > index 8fb3c9b..c952a3d 100644 > > --- a/hw/ssi/imx_spi.c > > +++ b/hw/ssi/imx_spi.c > > @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > static void imx_spi_reset(DeviceState *dev) > > { > > IMXSPIState *s =3D IMX_SPI(dev); > > + int i; > > > > DPRINTF("\n"); > > > > - memset(s->regs, 0, sizeof(s->regs)); > > - > > - s->regs[ECSPI_STATREG] =3D 0x00000003; > > + for (i =3D 0; i < ARRAY_SIZE(s->regs); i++) { > > + switch (i) { > > + case ECSPI_CONREG: > > + /* CONREG is not updated on reset */ > > + break; > > + case ECSPI_STATREG: > > + s->regs[i] =3D 0x00000003; > > + break; > > + default: > > + s->regs[i] =3D 0; > > + break; > > + } > > + } > > This retains the CONREG register value for both: > * 'soft' reset caused by write to device register to disable > the block > -- this is corrcet as per the datasheet quote > * 'power on' reset via TYPE_DEVICE's reset method > -- but in this case we should reset CONREG, because the Device > reset method is like a complete device powercycle and should > return the device state to what it was when QEMU was first > started. The POR value of CONREG is zero, which should be the default value, no? Regards, Bin From MAILER-DAEMON Thu Jan 28 08:51:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57hX-0003lo-BK for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:51:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57hW-0003kX-BV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:51:10 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:34401) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57hT-0007Qa-Bz for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:51:09 -0500 Received: by mail-ed1-x535.google.com with SMTP id d22so6697214edy.1 for ; Thu, 28 Jan 2021 05:51:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=GkzRAklb6idVbi4Nlegxw7IMnF2hkEvmjlxBgJ+vS9I=; b=zOpHgG6b9hGoscoCcOgh+sv2L2h5StT8MpGQ3HKnRZWSjVgVGfafsctn2g49oBKlfE le9G3l2iEuJUk7eOvwiHSKY+E0Bd15Vehux92Q+aFzZVXBra1yLiaoqqGP07MPwX2bPx iCNn2HqCtsuh+Ye6/XpzYQv7kXm2A62dyiGByukXpW50u0E66vXxla3GMKg9XWBPHK2O 8ju7hr2Ik2bjDwrJsWNeVSCPdsADCcimHDGW305CBOxdcpwlKkCt0o9bdlf08QKZjWMc wqr9XJeKB0vM3nOeLE/N+1RgmA23sC9MBHWtaOlk2OP386ecP8Us3KL/8YLiEpRtx40i UyVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=GkzRAklb6idVbi4Nlegxw7IMnF2hkEvmjlxBgJ+vS9I=; b=b0qhyGzzqT3BDNTgi/qyTL5Ioky7r0x8yI7MkLK3HMhVE3vFHB6AJN4hAAYmeYU99K ZlA7ea81YlLRD5Vc3Auyp5x574//0uPU3+1Su2ZyfgkHfFMf+s3+w4gR5DSTJAEvw4/n 1p38wmQyMhLEfnO5vkOeTea5PgTyh38qNQKSMl8Mvb98mLGn27+biGnrFrydHil6gm/l NyIDgReGt7TQXOSoJmAMJ+T/ovcw50a4Oq895lqfXA3dSBLghr2i57Yt29Ea5Eb5Hthg M+tAtriDwN92VwIKlhXO9gDIMWZx8gO1ilf5QkJchgeRgEOs+I2IHI9aMUtFri7Yg2Qa KoAw== X-Gm-Message-State: AOAM531S4d2u98tynQ9wqETaDZwkPPp3nugZEa6ToZX9vJ3i+sUqfUlp 421JW4IxMw1noJk0cBvqvCtyJUNR6xDkaGQoJm4EzA== X-Google-Smtp-Source: ABdhPJzRnKj4ag9vupbO6FcqHAfLAUfybK1GcRHprF1uv0p5hkz1uXkubvM9+eDU9eMF4+EKRvtCnqUyhoVbIqDq/b4= X-Received: by 2002:a05:6402:31ac:: with SMTP id dj12mr13929369edb.44.1611841864194; Thu, 28 Jan 2021 05:51:04 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-9-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1611063546-20278-9-git-send-email-bmeng.cn@gmail.com> From: Peter Maydell Date: Thu, 28 Jan 2021 13:50:52 +0000 Message-ID: Subject: Re: [PATCH v8 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:51:10 -0000 On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > From: Bin Meng > > Current implementation of the imx spi controller expects the burst > length to be multiple of 8, which is the most common use case. > > In case the burst length is not what we expect, log it to give user > a chance to notice it, and round it up to be multiple of 8. > > Signed-off-by: Bin Meng > @@ -128,7 +128,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) > > static uint32_t imx_spi_burst_length(IMXSPIState *s) > { > - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; > + uint32_t burst; > + > + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; > + if (burst % 8) { > + qemu_log_mask(LOG_UNIMP, > + "[%s]%s: burst length (%d) not multiple of 8!\n", > + TYPE_IMX_SPI, __func__, burst); > + burst = ROUND_UP(burst, 8); > + qemu_log_mask(LOG_UNIMP, > + "[%s]%s: burst length rounded up to %d; this may not work.\n", > + TYPE_IMX_SPI, __func__, burst); It's friendlier to the user to do the LOG_UNIMP when the unsupported CONREG value is written, rather than here where it is used. That way the warning happens once, rather than every time the device transmits data. Also, you could squash the warning down into one line, something like: "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n" rather than logging twice. thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:51:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57iJ-0004NI-AJ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:51:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57iI-0004Lp-E6 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:51:58 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:46337) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57iC-0007dT-BE for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:51:58 -0500 Received: by mail-ed1-x52a.google.com with SMTP id dj23so6645121edb.13 for ; Thu, 28 Jan 2021 05:51:50 -0800 (PST) DKIM-Signature: v=1; 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Thu, 28 Jan 2021 05:51:49 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> In-Reply-To: From: Peter Maydell Date: Thu, 28 Jan 2021 13:51:38 +0000 Message-ID: Subject: Re: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , "qemu-devel@nongnu.org Developers" , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:51:58 -0000 On Thu, 28 Jan 2021 at 07:15, Bin Meng wrote: > > On Fri, Jan 22, 2021 at 9:36 PM Bin Meng wrote: > > > > On Tue, Jan 19, 2021 at 9:40 PM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > This v8 series is based on the following 2 versions: > > > > > > - v5 series sent from Bin > > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 > > > - v7 series sent from Philippe > > > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 > > > > > > This series fixes a bunch of bugs in current implementation of the imx > > > spi controller, including the following issues: > > > > > > - remove imx_spi_update_irq() in imx_spi_reset() > > > - chip select signal was not lower down when spi controller is disabled > > > - round up the tx burst length to be multiple of 8 > > > - transfer incorrect data when the burst length is larger than 32 bit > > > - spi controller tx and rx fifo endianness is incorrect > > > - remove pointless variable (s->burst_length) initialization (Philippe) > > > - rework imx_spi_reset() to keep CONREG register value (Philippe) > > > - rework imx_spi_read() to handle block disabled (Philippe) > > > - rework imx_spi_write() to handle block disabled (Philippe) > > > > > > Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 > > > (interrupt mode). > > > > > > Changes in v8: > > > - keep the controller disable logic in the ECSPI_CONREG case > > > in imx_spi_write() > > > > Ping? > > Could we get this applied soon if no more comments? Sorry, I think I missed this re-send. I've reviewed or left comments on the patches that were still unreviewed. thanks -- PMM From MAILER-DAEMON Thu Jan 28 08:54:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l57ki-0006BP-6x for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 08:54:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l57kg-00069Z-Gn for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:54:26 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:46366) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l57kZ-00087J-NV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 08:54:25 -0500 Received: by mail-ed1-x529.google.com with SMTP id dj23so6654608edb.13 for ; Thu, 28 Jan 2021 05:54:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=J9bT+1htkfWngb5GTCiyd2mns4sFH1yUFJ/HiJJTGYE=; b=BpvcHLSiMfCOzRe1m7j3Ji4YBY8bpsUxLDiKAoVl9KGC3JurCIAxMdDmG4D9PGP3vr RF5/PMzOJmg+QhjGA53cZtysB5wMdqDXx/U9CUJ4qPOpDT1Ps/X9sLpQJO+5AxeS/Q7V dY1rj0XPzua/NYvnHtwXvjFjOqFQANpjXXCbhH6Nalbsu9tupg9MSkMFzjMcVtqCNAD9 WcjCc2xgDbmlj5H9B7UdEb120Yr++9M1g16fymzMA/iTrQ75pVkDbSBeAN72/3r6DHNc LNV1zWMhg/bVOiFc4tjQ1BORNmb5fsj0O9OnyX5zxLRCvwSRqWFmrUxPlpkNRj4NlRla agNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=J9bT+1htkfWngb5GTCiyd2mns4sFH1yUFJ/HiJJTGYE=; b=Ka0fGjQBRrAlrLHlDC1k4MBC03/KofgRGOHA2Z5L96gCB8UxgTIdPGtAEP9TFXLlhj GCO5s7opGo95sEUl5ZhqQ0E59cBc8QMNkFg9nF30MTTGWf7fo8bKo3xZTVTy0Q7iRfAl q1t/nJJ7gEYJH4uBo/DFlenu4z4x6+jjsck5j5S3FU0ZAFt3bI7xrwauLFkiKLoUo5La VTnBFUMGDl+bE7LPAF43T4A7OCVRktPHDKp2BdDarZbrFP/2qGIMpZtqITFhNp9qrs1p QGngk45BEXQa6B+3yRzkZe+HEBFs57s6yX4POinV3RrWHDgmsKsExg4EIbMB14wyZwnQ izYg== X-Gm-Message-State: AOAM53042Q7letK6bLFzqMhlSrCGS25culv6Jl55MaxOPFUFqw7uSS1b iv0Y3+r3/3H0PWRMGVl8BEJsdaA/I/BPH2X1guzKHw== X-Google-Smtp-Source: ABdhPJwDt24ZrL5tVRNaJ84cXbgBN0kteCzLi3wd1cyVfzGrhdVT+6MAxajpxhx5xqLSci8c3iNqKzBM19+ZdbgRhbM= X-Received: by 2002:a05:6402:5107:: with SMTP id m7mr14017698edd.52.1611842056944; Thu, 28 Jan 2021 05:54:16 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> In-Reply-To: From: Peter Maydell Date: Thu, 28 Jan 2021 13:54:05 +0000 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 13:54:26 -0000 On Thu, 28 Jan 2021 at 13:47, Bin Meng wrote: > > On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell = wrote: > > > > On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > > > > > From: Philippe Mathieu-Daud=C3=A9 > > > > > > When the block is disabled, all registers are reset with the > > > exception of the ECSPI_CONREG. It is initialized to zero > > > when the instance is created. > > > > > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > > > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > > index 8fb3c9b..c952a3d 100644 > > > --- a/hw/ssi/imx_spi.c > > > +++ b/hw/ssi/imx_spi.c > > > @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s= ) > > > static void imx_spi_reset(DeviceState *dev) > > > { > > > IMXSPIState *s =3D IMX_SPI(dev); > > > + int i; > > > > > > DPRINTF("\n"); > > > > > > - memset(s->regs, 0, sizeof(s->regs)); > > > - > > > - s->regs[ECSPI_STATREG] =3D 0x00000003; > > > + for (i =3D 0; i < ARRAY_SIZE(s->regs); i++) { > > > + switch (i) { > > > + case ECSPI_CONREG: > > > + /* CONREG is not updated on reset */ > > > + break; > > > + case ECSPI_STATREG: > > > + s->regs[i] =3D 0x00000003; > > > + break; > > > + default: > > > + s->regs[i] =3D 0; > > > + break; > > > + } > > > + } > > > > This retains the CONREG register value for both: > > * 'soft' reset caused by write to device register to disable > > the block > > -- this is corrcet as per the datasheet quote > > * 'power on' reset via TYPE_DEVICE's reset method > > -- but in this case we should reset CONREG, because the Device > > reset method is like a complete device powercycle and should > > return the device state to what it was when QEMU was first > > started. > > The POR value of CONREG is zero, which should be the default value, no? But you're not setting it to zero here, you're leaving it with whatever value it had before. (That's correct for soft reset, but wrong for power-on.) thanks -- PMM From MAILER-DAEMON Thu Jan 28 09:15:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l585D-0002yk-3B for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l585A-0002r9-8K; Thu, 28 Jan 2021 09:15:36 -0500 Received: from mail-yb1-xb30.google.com ([2607:f8b0:4864:20::b30]:40691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5858-0006M9-FT; Thu, 28 Jan 2021 09:15:35 -0500 Received: by mail-yb1-xb30.google.com with SMTP id w24so5575176ybi.7; Thu, 28 Jan 2021 06:15:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=88zMDvynYl+VCILBwZxGIJSVNOkBVvT44NtQ/W11vZg=; b=BpmpiMxCbvnplmXE1xZQBfb6/3INnLepE8WAvNyim44FTm5OStMuFQmHhfrbLXBELh wRZ5m3XUvHMq0/5Xq8XnI7WEsUCk57zynu3SP2mk3Y3rfjf1Ui4dg/7kP+d4CELUjy0d J76DI1aWbnINOHV8upP2mRtJe6hLRSYkQx104AHNdT/9LeUHv9W5RO6/umwpXJf3FUrZ CqfZuMv2QMqxww9q/biKAvplEm9q6yBFHD+NbUREf1hYSlvgcRAHCDP9W1hx1jm7b9NM FutT13wls0ZCdQlS7mJmMp70ONRTldrbPPYWy4c/iYad084+Mk2/YapVa3r67+w+QaJ2 112w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=88zMDvynYl+VCILBwZxGIJSVNOkBVvT44NtQ/W11vZg=; b=JScarw8qQgMdEmFTGWkglPajaEFBOGax3+mJ5rFEqxxVImH58bBZ+zOGcS3CJ3wITr wiPFLGwXNRQUK2b8X4/u+Q8uIMVyvLFJr0DVmDqegx4oTHhav5zJH77nu30auySEsKE7 JER2L2Jq8cawRICon9dduCXeFaRGaW+LcR06y61QRYBSW5blF1VX8UU7vf0GyP7u9oZU JYpIxTeHY2wSsHIcdo/dM2F21jPRxVXxnGeJaB82m3/78nwoEYt/zOtrl0/hlcSCvhY2 9Ya8VgLniOG5vcUTfFuMb/cq8bY3RJcVM3MMRYNvxH74QYa3jKXGYSSYWdbMofdhdGgj RUBQ== X-Gm-Message-State: AOAM5311y587CJgFrTb0ZxPyGNyA/1ruApEX+Egk1JpYGwnhoxfXJDhk xo0FQXGnpJK8AlxxPt3LdODtS1mr8rQgZNE4G7M= X-Google-Smtp-Source: ABdhPJxqEueHgXs4OcTVtGw5h24FLCen/56aTpkkF8SU1gC+bIbiR19Yu60k49WyXJrKwF7NsdHiknKoO+mtt4Y263M= X-Received: by 2002:a25:3bc5:: with SMTP id i188mr23867635yba.332.1611843332852; Thu, 28 Jan 2021 06:15:32 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> In-Reply-To: From: Bin Meng Date: Thu, 28 Jan 2021 22:15:18 +0800 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Peter Maydell Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis , QEMU Developers , qemu-arm , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b30; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:15:36 -0000 On Thu, Jan 28, 2021 at 9:54 PM Peter Maydell wr= ote: > > On Thu, 28 Jan 2021 at 13:47, Bin Meng wrote: > > > > On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell wrote: > > > > > > On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: > > > > > > > > From: Philippe Mathieu-Daud=C3=A9 > > > > > > > > When the block is disabled, all registers are reset with the > > > > exception of the ECSPI_CONREG. It is initialized to zero > > > > when the instance is created. > > > > > > > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > > > > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > > > > > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > > > > index 8fb3c9b..c952a3d 100644 > > > > --- a/hw/ssi/imx_spi.c > > > > +++ b/hw/ssi/imx_spi.c > > > > @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState = *s) > > > > static void imx_spi_reset(DeviceState *dev) > > > > { > > > > IMXSPIState *s =3D IMX_SPI(dev); > > > > + int i; > > > > > > > > DPRINTF("\n"); > > > > > > > > - memset(s->regs, 0, sizeof(s->regs)); > > > > - > > > > - s->regs[ECSPI_STATREG] =3D 0x00000003; > > > > + for (i =3D 0; i < ARRAY_SIZE(s->regs); i++) { > > > > + switch (i) { > > > > + case ECSPI_CONREG: > > > > + /* CONREG is not updated on reset */ > > > > + break; > > > > + case ECSPI_STATREG: > > > > + s->regs[i] =3D 0x00000003; > > > > + break; > > > > + default: > > > > + s->regs[i] =3D 0; > > > > + break; > > > > + } > > > > + } > > > > > > This retains the CONREG register value for both: > > > * 'soft' reset caused by write to device register to disable > > > the block > > > -- this is corrcet as per the datasheet quote > > > * 'power on' reset via TYPE_DEVICE's reset method > > > -- but in this case we should reset CONREG, because the Device > > > reset method is like a complete device powercycle and should > > > return the device state to what it was when QEMU was first > > > started. > > > > The POR value of CONREG is zero, which should be the default value, no? > > But you're not setting it to zero here, you're leaving it with > whatever value it had before. (That's correct for soft reset, > but wrong for power-on.) I think that's ensured by object_initialize_with_type(). Regards, Bin From MAILER-DAEMON Thu Jan 28 09:18:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l587c-0006t8-4j for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:18:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l587Z-0006qn-6N; Thu, 28 Jan 2021 09:18:05 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:38880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l587X-0007C0-JG; Thu, 28 Jan 2021 09:18:04 -0500 Received: by mail-ej1-x62e.google.com with SMTP id bl23so8004981ejb.5; Thu, 28 Jan 2021 06:18:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=RjERuanCbSHtMiaBdfhlXB6ezh/LXStNyUZKsPthKw0=; b=MHPHAw97C/wXQLERQbwwGr2ffxk/1PCbjDSw38tPW5NLsa1mhgCw0koI+UlBqvXqFH 1mvubmeddoDFsYd91IlDxktu05n8SJIA/w2UP4Nfghj+AO6X60b7ZhqGaQhtgjaQzMA2 YcwKZHtYCzIbGag2hXAl79T4wTKvxTOqqbX32oEZ1V6BvrPD8p7vkWLvOSiCWWcbGApo mq9tvp0UfanepVk99i/nvBZphxCRxSGwAW2gwsK86TiyA+dn2tta97heWjiNIj/y8JPe pj3D2p/LltfUQ+2LM++9gUA8Zqqu35qzlQuf1TFXzyQkR8D4gvX1ix1MEbiDMp8pS6mF h9yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=RjERuanCbSHtMiaBdfhlXB6ezh/LXStNyUZKsPthKw0=; b=OXQaCity2Dl7clz0Bm4/KTrJDA4Jsg+jpP/rhhuDBmQbk0GO30K82MqEOzS2iBpK5B 0YrnejRkMayQKoYVUnH2DrFPhhyCgCcICUwv/bMY6miz6Cel69QhRGpNOEL0iYp1G2W/ i+7hPKzrboql0lm/5mkdyUqfCW0zD2aS8/xemM4PuEXFQBTBIer7seIUdcYOdkZ+ibWg sgY+A6v39W1csSLSYV/gngEI/jqn9pdBc8SrxyQKI9RAoSfwC5RUKbEl8Ecw/BxuAWH5 tt2ihTRZ2Tq40GJBW/3a+Pl9XiU1bBR48GxG7I6uR+9+2aaFEgx8J/YErMdY2iV7+7o/ dlIQ== X-Gm-Message-State: AOAM533iY1iY3sC0x7OzV697SbiH8S9aRRL0q/nux1G2xSkx2QoIxkBs vHpfyLFeKxX8zze/m2BkE78= X-Google-Smtp-Source: ABdhPJzhGqEClocasHd1673LqnCpTy7hQl95kXBHEaqn/uofz9vIlpDKu8/LtCHKvxOFOjfq6yZCEQ== X-Received: by 2002:a17:906:f1d6:: with SMTP id gx22mr11387945ejb.348.1611843481800; Thu, 28 Jan 2021 06:18:01 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id n20sm3083755edr.89.2021.01.28.06.18.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 06:18:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Peter Maydell , Bin Meng Cc: Bin Meng , QEMU Developers , qemu-arm , Alistair Francis , Jean-Christophe Dubois References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> Date: Thu, 28 Jan 2021 15:17:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:18:05 -0000 On 1/28/21 2:54 PM, Peter Maydell wrote: > On Thu, 28 Jan 2021 at 13:47, Bin Meng wrote: >> >> On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell wrote: >>> >>> On Tue, 19 Jan 2021 at 13:40, Bin Meng wrote: >>>> >>>> From: Philippe Mathieu-Daudé >>>> >>>> When the block is disabled, all registers are reset with the >>>> exception of the ECSPI_CONREG. It is initialized to zero >>>> when the instance is created. >>>> >>>> Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), >>>> chapter 21.7.3: Control Register (ECSPIx_CONREG) >>> >>>> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c >>>> index 8fb3c9b..c952a3d 100644 >>>> --- a/hw/ssi/imx_spi.c >>>> +++ b/hw/ssi/imx_spi.c >>>> @@ -231,12 +231,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) >>>> static void imx_spi_reset(DeviceState *dev) >>>> { >>>> IMXSPIState *s = IMX_SPI(dev); >>>> + int i; >>>> >>>> DPRINTF("\n"); >>>> >>>> - memset(s->regs, 0, sizeof(s->regs)); >>>> - >>>> - s->regs[ECSPI_STATREG] = 0x00000003; >>>> + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { >>>> + switch (i) { >>>> + case ECSPI_CONREG: >>>> + /* CONREG is not updated on reset */ >>>> + break; >>>> + case ECSPI_STATREG: >>>> + s->regs[i] = 0x00000003; >>>> + break; >>>> + default: >>>> + s->regs[i] = 0; >>>> + break; >>>> + } >>>> + } >>> >>> This retains the CONREG register value for both: >>> * 'soft' reset caused by write to device register to disable >>> the block >>> -- this is corrcet as per the datasheet quote >>> * 'power on' reset via TYPE_DEVICE's reset method >>> -- but in this case we should reset CONREG, because the Device >>> reset method is like a complete device powercycle and should >>> return the device state to what it was when QEMU was first >>> started. >> >> The POR value of CONREG is zero, which should be the default value, no? > > But you're not setting it to zero here, you're leaving it with > whatever value it had before. (That's correct for soft reset, > but wrong for power-on.) zero value on power-on is what I tried to describe as "It is initialized to zero when the instance is created." Most of the codebase assumes QOM provides a zero-initialized instance state. Do you think it should be explicit? Regards, Phil. From MAILER-DAEMON Thu Jan 28 09:22:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58C5-0002xB-7m for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:22:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58C3-0002uB-K6 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:22:43 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]:44389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58C0-0000S8-W9 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:22:43 -0500 Received: by mail-ed1-x52f.google.com with SMTP id c2so6778013edr.11 for ; Thu, 28 Jan 2021 06:22:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=8Tcbr9SedKFrNWTq4e/LLHNQILimboW0eGVvS+bEniw=; b=qyY/HXQXptNOa5T8hs1kvW4IKbJPZ6FpYo9Xe9CXzR7s8bHNQD+qiV2K52d+0NrCh6 wuU1Cz/1JUwjnpVQUanfnaq05fFCQRMaoqYl9B/UAbhXLh0r/BTT8mvGSWib/vjzvD7w zo0YgkdEraZhEOeK3Zr7ro4EVYDaBU4ScCUIPb15gvwujbc9fV0nJK6ODLgZUwcByF2V 6b+g1UUGa8dMUHYvIne5szc27uNN3azg6XNONst8igOnVQNZ4uauSlOtRjAJeMKw6OoO YK7xZytfkuJn5CWTnT+WSNBAeqeCDzZoSvoMqzdbq2sKgYlHD/EYwjfuDqwrAYsH2lvJ FNUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=8Tcbr9SedKFrNWTq4e/LLHNQILimboW0eGVvS+bEniw=; b=L2dp685qgXgjEbvCbhrfnouUkSvirtudws2tLz3Np4t/o0lnYPYQ6p58lCcyrbxpBU pu0qQTohpd4VhF6u0VeEnU5+XArONq6wFNQCJU/pG3D0JQQWyY21vXGFOB28nPBUpOoO Q3F4Nxsk2BY0u9cG0xj6uY0afgouX9adUfTkDQ1kcbSE6X7oNgNllHJrk/V3w3iHIvfv To+hxvNXI7B/GXFl+DWuPOlGpo0Nj92J34ydAnhyCWR2X7cTG2/GcwGaZiiFeIA7URSq piidUDx0gD+9AiVWfQeFPM59yezRmc9HhBn1u8iVxZTfMSlcfPkygnZIZK+MHbj+z1Sw mndQ== X-Gm-Message-State: AOAM531bVMjyEKptfkZ3SrnTpKuyVZoE8UyFbhEhUy5i2NnzBkwAqJlM 5n70n/reRaPQ4eNDOLlVPnuwihIYI90RXpO9COqiQA== X-Google-Smtp-Source: ABdhPJxeRYZ/DjXbTOu59+Zl39D6ljotFEFwNZnw+UDMAEV9t3tLO9oiDYiZI8QlzsIeT86xqZZ4ZonY021UA2Im0pg= X-Received: by 2002:aa7:c88a:: with SMTP id p10mr14328349eds.204.1611843759171; Thu, 28 Jan 2021 06:22:39 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> In-Reply-To: <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> From: Peter Maydell Date: Thu, 28 Jan 2021 14:22:27 +0000 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Bin Meng , Bin Meng , QEMU Developers , qemu-arm , Alistair Francis , Jean-Christophe Dubois Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:22:43 -0000 On Thu, 28 Jan 2021 at 14:18, Philippe Mathieu-Daud=C3=A9 = wrote: > > On 1/28/21 2:54 PM, Peter Maydell wrote: > > On Thu, 28 Jan 2021 at 13:47, Bin Meng wrote: > >> > >> On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell wrote: > >>> This retains the CONREG register value for both: > >>> * 'soft' reset caused by write to device register to disable > >>> the block > >>> -- this is corrcet as per the datasheet quote > >>> * 'power on' reset via TYPE_DEVICE's reset method > >>> -- but in this case we should reset CONREG, because the Device > >>> reset method is like a complete device powercycle and should > >>> return the device state to what it was when QEMU was first > >>> started. > >> > >> The POR value of CONREG is zero, which should be the default value, no= ? > > > > But you're not setting it to zero here, you're leaving it with > > whatever value it had before. (That's correct for soft reset, > > but wrong for power-on.) > > zero value on power-on is what I tried to describe as > "It is initialized to zero when the instance is created." Yes, but QOM device reset does not happen just once at startup and not thereafter. Consider: * user starts QEMU * QOM devices are created and realized * QOM device reset happens -- CONREG is zero here because QOM structs are zero-initialized * guest runs * guest modifies CONREG from its initial value * system reset is requested (perhaps by user, perhaps by guest writing some register or another) * QOM device reset happens -- CONREG is not zero here, so reset must clear it thanks -- PMM From MAILER-DAEMON Thu Jan 28 09:32:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58La-0001U5-44 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:32:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58LU-0001TF-FH; Thu, 28 Jan 2021 09:32:30 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:40280) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58LL-00048W-Ij; Thu, 28 Jan 2021 09:32:22 -0500 Received: by mail-ej1-x62a.google.com with SMTP id gx5so8056518ejb.7; Thu, 28 Jan 2021 06:32:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=6DRo2VevtgZRCIOMvLkYVjMIfduDRPEFsCZj4TkdEHQ=; b=u1AO+jXQpl88AAm8tIxnUUhNsmJin8hGfSeH8pDp7C+Bi78tQuXdo8mIJq6FsjLLIm UauQNV0D3P8BXgR3sbIfdMWMZag0tdBTv/i6KWfcegcSLCPx3RT0cgsVY/fPGJ8My057 jsFpyJ/eC4vQLdbbC3UsJmZy/L0jBgF365rM67X9g1Z/XHo+Xi+0mN+cTEGIH7be1wIA B+kVB3hsbkmOFh5iA6CbIbD2Y/K/qzx8G4VSsLzx+M3K9UTOcdESKg6QHSIyug9xJMaK c6onmf0yPmZHvG8gKzIxIAXi+cv6RwKTsZN9z0jk83A9l+sCekXoKMl+qicCm7cinipj +JMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=6DRo2VevtgZRCIOMvLkYVjMIfduDRPEFsCZj4TkdEHQ=; b=j67FASvI6ziLqCQhzqEh48B+zD5AwPAEPmqSrxfXvKdzc0JHSh21dyQ3XV/kYrqpPu p0CSHURiFAvR1TKN6nojBoqW8W+go4aRQ72P6eH7lnickGeJQZ5AWh+PQ85qnoBc9l3Y oBgcFZ1QMGrPrgcTxIJ8CYQU4Gf/vcO4IHPvt3i1C4PTJuL1NRWmT7QGWbhfpJYZ30oO 0GosC6OSEbeviDcUyw0dyZRqF/jQ0jYTiMpEF9aXpkibUu52VoUcBKTfm5bpcOqgMV3/ o3MX7W2d4UJeT8k/vnLYtEwPzNy9+GlAp4oxtvTXXMPR2sfLxJGC4bxco381LY8EnLOQ M04g== X-Gm-Message-State: AOAM532dhS6lMuZ05azB21cdbEBADNkrXsOCakERSRZIojF3j2GLUF7i XJfUkkwVenjwwfbBAW/PsQc= X-Google-Smtp-Source: ABdhPJwRevZdeH84vTH50ZU8UAuiznFXZQAPSuidsG3QUX/j/c1RUtzyqJP8cNJfAnL3PIhIVSKN2Q== X-Received: by 2002:a17:906:49c2:: with SMTP id w2mr10883323ejv.12.1611844337423; Thu, 28 Jan 2021 06:32:17 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id g25sm2337439ejf.15.2021.01.28.06.32.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 06:32:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Peter Maydell , Bin Meng Cc: QEMU Developers , Jean-Christophe Dubois , qemu-arm , Alistair Francis , Bin Meng References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9a8312d7-d3b3-b896-a669-8ce8efc66bf0@amsat.org> Date: Thu, 28 Jan 2021 15:32:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:32:30 -0000 On 1/28/21 3:22 PM, Peter Maydell wrote: > On Thu, 28 Jan 2021 at 14:18, Philippe Mathieu-Daudé wrote: >> >> On 1/28/21 2:54 PM, Peter Maydell wrote: >>> On Thu, 28 Jan 2021 at 13:47, Bin Meng wrote: >>>> >>>> On Thu, Jan 28, 2021 at 9:43 PM Peter Maydell wrote: >>>>> This retains the CONREG register value for both: >>>>> * 'soft' reset caused by write to device register to disable >>>>> the block >>>>> -- this is corrcet as per the datasheet quote >>>>> * 'power on' reset via TYPE_DEVICE's reset method >>>>> -- but in this case we should reset CONREG, because the Device >>>>> reset method is like a complete device powercycle and should >>>>> return the device state to what it was when QEMU was first >>>>> started. >>>> >>>> The POR value of CONREG is zero, which should be the default value, no? >>> >>> But you're not setting it to zero here, you're leaving it with >>> whatever value it had before. (That's correct for soft reset, >>> but wrong for power-on.) >> >> zero value on power-on is what I tried to describe as >> "It is initialized to zero when the instance is created." > > Yes, but QOM device reset does not happen just once at startup and > not thereafter. Consider: > > * user starts QEMU > * QOM devices are created and realized > * QOM device reset happens > -- CONREG is zero here because QOM structs are zero-initialized > * guest runs > * guest modifies CONREG from its initial value > * system reset is requested (perhaps by user, perhaps by > guest writing some register or another) > * QOM device reset happens > -- CONREG is not zero here, so reset must clear it Oh I totally missed that :S Bin, I'd correct this as: - extract imx_spi_soft_reset(IMXSPIState *s) from imx_spi_reset() - zero-initialize CONREG in imx_spi_reset(). static void imx_spi_soft_reset(IMXSPIState *s) { ... } static void imx_spi_reset(DeviceState *dev) { IMXSPIState *s = IMX_SPI(dev); s->regs[ECSPI_CONREG] = 0; imx_spi_soft_reset(s); } What do you think? Phil. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id x17sm3027984edd.76.2021.01.28.06.38.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 06:38:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 01/25] ptimer: Add new ptimer_set_period_from_clock() function To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Luc Michel References: <20210128114145.20536-1-peter.maydell@linaro.org> <20210128114145.20536-2-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <8d5fbbc7-56fe-9a08-c891-3021f17e32f9@amsat.org> Date: Thu, 28 Jan 2021 15:38:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210128114145.20536-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:38:06 -0000 On 1/28/21 12:41 PM, Peter Maydell wrote: > The ptimer API currently provides two methods for setting the period: > ptimer_set_period(), which takes a period in nanoseconds, and > ptimer_set_freq(), which takes a frequency in Hz. Neither of these > lines up nicely with the Clock API, because although both the Clock > and the ptimer track the frequency using a representation of whole > and fractional nanoseconds, conversion via either period-in-ns or > frequency-in-Hz will introduce a rounding error. > > Add a new function ptimer_set_period_from_clock() which takes the > Clock object directly to avoid the rounding issues. This includes a > facility for the user to specify that there is a frequency divider > between the Clock proper and the timer, as some timer devices like > the CMSDK APB dualtimer need this. > > To avoid having to drag in clock.h from ptimer.h we add the Clock > type to typedefs.h. > > Signed-off-by: Peter Maydell > Reviewed-by: Luc Michel > Message-id: 20210121190622.22000-2-peter.maydell@linaro.org > --- > include/hw/ptimer.h | 22 ++++++++++++++++++++++ > include/qemu/typedefs.h | 1 + > hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++ > 3 files changed, 57 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 28 09:38:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58RL-0005io-Jn for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:38:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58RF-0005gZ-IM for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:38:26 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:46459) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58RB-0006Cg-6T for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:38:25 -0500 Received: by mail-ej1-x62e.google.com with SMTP id rv9so8054940ejb.13 for ; Thu, 28 Jan 2021 06:38:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BOUtrUQbu4v4DcBOyp3QHTI9z/QDDXd95PtlE1x7RnU=; b=esnld8CMrPBUhXNe/av8piYuONGbvNGhHTxp571wsxa00L0pCrdGBsLTOo/PYzz/5D xEVul5br5U2/dA+q23ucGHf1rlBDCG1LdLHRngyO8no5Ow/2mAIg2CP/SEYx/zFRL1jd dwCUYLUIUTTHm99DV/VexRIbzWY3nPOkPoYJaKME7+3GxVa0HvCV6loB3if/dDrEsStS p1KCq0LCXJcmOz4OtFSlkVwEwf3z6xZRSrCaqcI4VsqK1FkyHGFNeXhNsdx11dnIXuvl 1u+VGG57g0KLEukT4cCeAxM9sKsae2ySokq0RiV8nHtxDK4sMfihWLbDPoVd0PJx8Fqr PSMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BOUtrUQbu4v4DcBOyp3QHTI9z/QDDXd95PtlE1x7RnU=; b=GefV3QDZebvt7O9ZeD8xtZHwE+h/Otg0OlpTYu6Mxk2kVRkvrrzmR1KXmCIsJSqDEv K/S8+m6pq+XHlvs7TMxPQ5pMiRI/LoQLKld4Jyd9co+zBBPRdPXJfagj6+7WrFNwU6C4 LNIui7+wVwTQ7N/BWrpaL6y0MV3DSIMGKGKuWa5SA56vmveLaLYwTeyfdIUwZaUFlPuu IHKEJ1xAlXe5MwzhQfu9nqtRRqggIqYaYj9F+ThaYcsX4JGALngdIGs7aa8TjQy7yUiU kuNmuYyWW4LSK5aTtsKD7buiYuHweapL3YxbKrNubNmnDVTnDBe0TDm4fGmjDXU1oAy3 MOJw== X-Gm-Message-State: AOAM531A2imlj/qWfEE6Y372hn3ikg/IAWkcGO07EFWUpmsNsy+Jz8dq g+X4m11yGT42peUlnId/zA7y+kaEUSIVjB1EY68ETw== X-Google-Smtp-Source: ABdhPJyI9TP7ov/1P3UAanPd7JEGWctGR4ePuKKd78/7NTmQGUnfYq4SNeZPdcUlbeR/w8K5PKpmVOG/W4c10dXiMqg= X-Received: by 2002:a17:906:2747:: with SMTP id a7mr11928329ejd.250.1611844699361; Thu, 28 Jan 2021 06:38:19 -0800 (PST) MIME-Version: 1.0 References: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu> In-Reply-To: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu> From: Peter Maydell Date: Thu, 28 Jan 2021 14:38:08 +0000 Message-ID: Subject: Re: [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue To: Mike Nawrocki Cc: qemu-arm , QEMU Developers , QEMU Trivial Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:38:26 -0000 On Thu, 28 Jan 2021 at 14:31, Mike Nawrocki wrote: > > The SCR_EL3 register reset value (0) and the value produced when > writing 0 via the scr_write function (set as writefn in the register > struct) differ. This causes migration to fail. > > I believe the solution is to specify a raw_writefn for that register. > > Failing invocation: > $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic > QEMU 5.2.0 monitor - type 'help' for more information > (qemu) migrate "exec:cat > img" > (qemu) q > $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic -incoming "exec:cat img" > qemu-system-arm: error while loading state for instance 0x0 of device 'cpu' > qemu-system-arm: load of migration failed: Operation not permitted I'll review the patch later, but for the moment just a note that I'm pretty sure this is not the only issue you'll run into with trying to migrate an AArch32 TrustZone-enabled CPU. https://bugs.launchpad.net/qemu/+bug/1839807 has the details but in summary we aren't migrating the Secure banked contents of cp15 registers which are banked Secure/Non-Secure. The symptom will be that migration succeeds but the guest doesn't behave correctly on the destination/after state restore. thanks -- PMM From MAILER-DAEMON Thu Jan 28 09:41:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58Ub-0000aw-7U for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:41:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58UZ-0000Wb-5F for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:41:51 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:33715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58UV-0007HT-EM for qemu-arm@nongnu.org; Thu, 28 Jan 2021 09:41:50 -0500 Received: by mail-ej1-x635.google.com with SMTP id by1so8168377ejc.0 for ; Thu, 28 Jan 2021 06:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=6HIVzNVqs8si5zhdqS4qhDfVW8FvAwhegS35T9JqgpE=; b=vn0COtHbqCX//3Jyne5pmBN7AbiywrY2BdjPoYDOnuHLWGPsP6i8yV7EJ840G8Q3Wd E9gs1bTIjhGb8oRTuXCHTBxZbTdvlN+9ZtZNtcDifir7OLUmF/hnnocPTZrw82rfLc63 s5J0qlq1utLixiY3CrFhkF6l8BcdaqAs0HHHS3WZBo1n0QLnLttPabmHVvjRMDbP8PVn ZHrON4NThmpLQAHOv74qu5Xa0S1nqcXjZv3plOn+krp6eQrtb7igxV0MivBT6Pl0tnxF x+whjAisN+5KQT7nb+HZxG4wuDzpIlfkxo40ObnmFoNi+PwcJ6fVtAw8X35s9t81FWh7 aF1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=6HIVzNVqs8si5zhdqS4qhDfVW8FvAwhegS35T9JqgpE=; b=mFpUkE0a/roA6bYz2grTSYVl8jJEY1d5PRnP+VJwi+sMnf1BSrBCYPrJmxDBTjMiNZ zlg3lX+9rM7DJFoJOA9F9UndyllhJ49DRuM+Id96ZNyT6392xnF5wWP4QaSssEKPZpsR hkO9sBev8eHQP2Ji/2VP/c6zDvivwkBCqu12kdhpdD8d2We3WnS6pvnh+QsuoASPxp5G YOlyIhRUhshXdNynF3Q+WTV8/3W63xmM6gbisK4OlzOLLasWjFvq9QDW4s3hI+Q/FuiA ft5NiQ03uReq8jVvfu0oKlLBG8XpYx/5NOixDAg5/3ptE+NXEdI5Q6YbhG/1e/DF4S1b //lA== X-Gm-Message-State: AOAM532LZAYsB2jhXAFBTafg/VL9Uww+0SzkQVz1i7vUh4Aj8XsfGFQL MQo2htGb2lz/TgsYZMN2cp9B3vIhiPbC30/mPph6kA== X-Google-Smtp-Source: ABdhPJxn7B6ZLk8bLMCl2pQbuB6DZnwArAZyq/GNWalr7J94Xf3k+7ZxEBW8F+T5DAUUYxXrsH5l68shEJPgpSDonso= X-Received: by 2002:a17:906:494c:: with SMTP id f12mr11681040ejt.56.1611844902345; Thu, 28 Jan 2021 06:41:42 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> <9a8312d7-d3b3-b896-a669-8ce8efc66bf0@amsat.org> In-Reply-To: <9a8312d7-d3b3-b896-a669-8ce8efc66bf0@amsat.org> From: Peter Maydell Date: Thu, 28 Jan 2021 14:41:31 +0000 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Bin Meng , QEMU Developers , Jean-Christophe Dubois , qemu-arm , Alistair Francis , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:41:51 -0000 On Thu, 28 Jan 2021 at 14:32, Philippe Mathieu-Daud=C3=A9 = wrote: > Oh I totally missed that :S > > Bin, I'd correct this as: > > - extract imx_spi_soft_reset(IMXSPIState *s) from imx_spi_reset() > - zero-initialize CONREG in imx_spi_reset(). > > static void imx_spi_soft_reset(IMXSPIState *s) > { > ... > } > > static void imx_spi_reset(DeviceState *dev) > { > IMXSPIState *s =3D IMX_SPI(dev); > > s->regs[ECSPI_CONREG] =3D 0; > imx_spi_soft_reset(s); > } > > What do you think? That doesn't give you anywhere to put the imx_spi_update_irq() call, which must happen only on soft reset and not on DeviceState reset. You could do one of: * have a 'common reset' function that does most of this, plus an imx_spi_reset which clears CONREG and calls common reset and an imx_spi_soft_reset which calls common reset and imx_spi_update_irq() * have imx_spi_soft_reset save the old CONREG in a local variable before calling imx_spi_reset and then restore it to s->regs thanks -- PMM From MAILER-DAEMON Thu Jan 28 09:46:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58ZQ-0007bS-CC for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:46:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58ZO-0007Xz-IR; Thu, 28 Jan 2021 09:46:50 -0500 Received: from unifiededge.gtri.gatech.edu ([130.207.205.170]:28786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58ZM-0000c2-0Z; Thu, 28 Jan 2021 09:46:50 -0500 Content-Transfer-Encoding: 8bit Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; d=gtri.gatech.edu; s=unifiededge; c=simple/simple; t=1611844301; h=from:subject:to:date:message-id; bh=w/EyQalOWuVWocDQhP95aCvyNFJVs0DYo9EJN601YUQ=; b=flLeISIFqKBUHRaHsrxqNnIlUwKDKvZcdrH/m5LurAIsOJyMAPFB6t82xabk7DSBCIq8cagn7rR TGYUXztfF8VaSrjpiKVZXMKqVBkDTCLJI0cIzIq4oRhbIWm9rhBdWlg+6PfnDJtTMA1Q+3A5Ck5Ef 0/MiCkp3N3lTy18+MqaIEudGNqZxtNvU6R3PNyR4jneXl/Eg5zy7ME/hISPCxj8vQ2iRa3TpIZr4N gCr2XBENOSGCiTSuvqnddKuUNZz/JfXRwbHFa2NCZKbNUUMFHDpIxSJ9zK+THWOZWSN+RcwWideU3 zxufOLKIrxAnXgm4IT12qsCdArRueIALxptw== Received: from tybee.core.gtri.org (10.41.1.49) by exedge06.gtri.dmz (10.41.104.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.2.721.2; Thu, 28 Jan 2021 09:31:41 -0500 Received: from localhost.localdomain (10.41.0.30) by tybee.core.gtri.org (10.41.1.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Thu, 28 Jan 2021 09:31:41 -0500 From: Mike Nawrocki To: CC: , , , Mike Nawrocki Subject: [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register Date: Thu, 28 Jan 2021 09:31:02 -0500 Message-ID: <20210128143102.7834-2-michael.nawrocki@gtri.gatech.edu> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu> References: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu> MIME-Version: 1.0 X-ClientProxiedBy: hatteras.core.gtri.org (10.41.22.72) To tybee.core.gtri.org (10.41.1.49) Received-SPF: pass client-ip=130.207.205.170; envelope-from=Michael.Nawrocki@gtri.gatech.edu; helo=unifiededge.gtri.gatech.edu X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:46:50 -0000 Fixes an issue in migration where the reset value of SCR and the value produced by scr_write via the writefn for SCR_EL3 mismatch. Signed-off-by: Mike Nawrocki --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ead3fcbd..e3c4fe76cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5785,7 +5785,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .resetvalue = 0, .writefn = scr_write }, + .resetvalue = 0, .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, -- 2.20.1 From MAILER-DAEMON Thu Jan 28 09:46:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58ZT-0007do-MN for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:46:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58ZQ-0007bU-KC; Thu, 28 Jan 2021 09:46:52 -0500 Received: from unifiededge.gtri.gatech.edu ([130.207.205.170]:20950) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58ZM-0000c3-5H; Thu, 28 Jan 2021 09:46:52 -0500 Content-Transfer-Encoding: 8bit Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; d=gtri.gatech.edu; s=unifiededge; c=simple/simple; t=1611844300; h=from:subject:to:date:message-id; bh=rgvmgdcyzggiCgfSXThLfGZq+ttZqivy+Z4oyt+0EFk=; b=rExLeuKUMJ1LJnvCombSZ1oNHXChZaV4MDSTkuxdCwRGHD9HXDqflhtg3Lo/I1Pog0P/te3FqA4 KkUn7/2v4WzRKliLsNn68Ds1eKT+GRPBNh0zZjxqNMjgav7fXUaPwm4IutoaqrdASsu3opnr8mE3n Y21UeOyI90BTydWdivqleaHUWPjR45p/lm7P2LNJzE2qvXbIx4SPaj1AKmWwuQvFJpXdfPmIRUm/Y aHOdxyZtWVkwkp3loFZFAjfN+2qDpqOPqkknu2ZExEqz5O7GJdCWLvbcRmd73cZS9a79IHckAz48j rOBK6WNG27InYa7b5ZUQDXgLSzAU9iehNq8A== Received: from tybee.core.gtri.org (10.41.1.49) by exedge07.gtri.dmz (10.41.104.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.2.721.2; Thu, 28 Jan 2021 09:31:40 -0500 Received: from localhost.localdomain (10.41.0.30) by tybee.core.gtri.org (10.41.1.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Thu, 28 Jan 2021 09:31:40 -0500 From: Mike Nawrocki To: CC: , , , Mike Nawrocki Subject: [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue Date: Thu, 28 Jan 2021 09:31:01 -0500 Message-ID: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-ClientProxiedBy: hatteras.core.gtri.org (10.41.22.72) To tybee.core.gtri.org (10.41.1.49) Received-SPF: pass client-ip=130.207.205.170; envelope-from=Michael.Nawrocki@gtri.gatech.edu; helo=unifiededge.gtri.gatech.edu X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:46:53 -0000 The SCR_EL3 register reset value (0) and the value produced when writing 0 via the scr_write function (set as writefn in the register struct) differ. This causes migration to fail. I believe the solution is to specify a raw_writefn for that register. Failing invocation: $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic QEMU 5.2.0 monitor - type 'help' for more information (qemu) migrate "exec:cat > img" (qemu) q $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic -incoming "exec:cat img" qemu-system-arm: error while loading state for instance 0x0 of device 'cpu' qemu-system-arm: load of migration failed: Operation not permitted Mike Nawrocki (1): target/arm: Add raw_writefn to SCR_EL3 register target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 From MAILER-DAEMON Thu Jan 28 09:49:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58bo-00038F-Nn for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 09:49:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58bm-00034A-V8; Thu, 28 Jan 2021 09:49:18 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:46651) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58bl-0001SK-Dv; Thu, 28 Jan 2021 09:49:18 -0500 Received: by mail-ej1-x634.google.com with SMTP id rv9so8111155ejb.13; Thu, 28 Jan 2021 06:49:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=SrxEts2129qGoww/QhPzpYQOwcyVGTBmHuwr9Mjv48Q=; b=gZ+YvYAAQXX9d3o8EkpbLirUtyXs5CK1a+cqnOS1aJblByH+EalpxECPCi0COi6fpz ByHMMrfEpQKHIE3+bLfYO1zyTg9z3yg/TRdsQniH9op1+93bY1KwRiG7P2cmfBT0eRpe kLcMP7aXb6pGcu/hr7A8UNXkRC6Ijss5ievJurOID/8i+PT/hxWX/qHsH9d2c6lDqwgd 8cMhwDvXfoQ2Qp3bMbhYUrhZiReuGHBdVon0+RQciNxZX311WqmjXdOGVVVGQS6hJ4yU zwg6c0b/uCt7TVmLnPSUoOrIANkO/h23FG++IiTidEKX3GQYlN+J/hVDN+fHD5Jc78hk ou7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=SrxEts2129qGoww/QhPzpYQOwcyVGTBmHuwr9Mjv48Q=; b=kx/IL8cubM9EBZV5MOfbseVK9nha5XYrmgM7d5kz3v+i0eucDoeaFj53RTFgCFun/m s8f50QukMvPEKxbtE0FKRMG7WksAEN76Lze1WCac9Y1oUyR5MltW4b+nj2UGv3Ie+WOB X+SpDV9mhNqt8UhX886wbIckbn1NZDrcqgu9QsOQnGpVYp2bjTTtIjF7CPlV3LOpsPr1 FIc+uR4GLMe+uFaBRdHecOLmAnkUgCUwMJZH8F5DfJ0HtJD+MN9Geqd23eav3GEOR+ZR 0YR75a3X0XJbQqpP8kGtaAzCWt0BGXuHRwZ3Hlz1V2tTkUG3XnW7U9/dFgC7vPzFm/h/ UljQ== X-Gm-Message-State: AOAM532ZqSLDvhzrrWezDHaET2F+t4zqqX0d4Xhj+WsLdfl9/tm9ioLi tk3hPuk5BEmcOE3M5QdoeB8= X-Google-Smtp-Source: ABdhPJx+jNqv36fcneXCzyM18W8iEt9Pld6oncP6nc8iLr9IE8dTjtOqB9h2RprWQMFapm0YGbn+eg== X-Received: by 2002:a17:906:f755:: with SMTP id jp21mr11374119ejb.22.1611845355327; Thu, 28 Jan 2021 06:49:15 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id n2sm2522628ejl.1.2021.01.28.06.49.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 06:49:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Peter Maydell Cc: Bin Meng , QEMU Developers , Jean-Christophe Dubois , qemu-arm , Alistair Francis , Bin Meng References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> <9a8312d7-d3b3-b896-a669-8ce8efc66bf0@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <26b80ae5-f1e0-f438-a1e5-9922686be128@amsat.org> Date: Thu, 28 Jan 2021 15:49:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 14:49:19 -0000 On 1/28/21 3:41 PM, Peter Maydell wrote: > On Thu, 28 Jan 2021 at 14:32, Philippe Mathieu-Daudé wrote: >> Oh I totally missed that :S >> >> Bin, I'd correct this as: >> >> - extract imx_spi_soft_reset(IMXSPIState *s) from imx_spi_reset() >> - zero-initialize CONREG in imx_spi_reset(). >> >> static void imx_spi_soft_reset(IMXSPIState *s) >> { >> ... >> } >> >> static void imx_spi_reset(DeviceState *dev) >> { >> IMXSPIState *s = IMX_SPI(dev); >> >> s->regs[ECSPI_CONREG] = 0; >> imx_spi_soft_reset(s); >> } >> >> What do you think? > > That doesn't give you anywhere to put the imx_spi_update_irq() > call, which must happen only on soft reset and not on DeviceState > reset. You could do one of: > * have a 'common reset' function that does most of this, > plus an imx_spi_reset which clears CONREG and calls > common reset and an imx_spi_soft_reset which calls > common reset and imx_spi_update_irq() > * have imx_spi_soft_reset save the old CONREG in a local > variable before calling imx_spi_reset and then restore it > to s->regs Long term maintenance I'd prefer the 'common reset' approach (but this is probably subjective to my view on the hardware, since this is software, the 2nd approach is also valid but harder to represent thinking of hardware). Bin, can you send a v9? (using the approach you prefer) Thanks, Phil. From MAILER-DAEMON Thu Jan 28 10:00:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l58mu-0006Va-JF for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:00:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l58mq-0006U0-JD; Thu, 28 Jan 2021 10:00:44 -0500 Received: from mail-yb1-xb2f.google.com ([2607:f8b0:4864:20::b2f]:43504) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l58mj-0005v2-K7; Thu, 28 Jan 2021 10:00:44 -0500 Received: by mail-yb1-xb2f.google.com with SMTP id y128so5691794ybf.10; Thu, 28 Jan 2021 07:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=2BQSxln3svi2n+JcH2fO7IYmtxAF9oG3oZ57LVMvl9I=; b=plWmR/5dKChfrjWAEz/Ubkrb1RRyEgkkqfgcKVas4zgsMh6CMz6oVssSv1L9EAYU5A 0Eb28qWHJt0eGW2+mfiVURugLq823X58V/30ERltrXwfKrgcXPoWr+g+Ed8iQsyNCrTV wowz1qBUU5P8EdDua768qiODiM8D8AsmCGmapp1vj9tPRj77rAJmOKIfuHe+OU9PuMai RZSgnp2PvtX0yaKp0q0E1goC5O7lc9RCyST+v0CwZWkY8VPrg+7CxRoCgaxk4aCH2bXs ka/OtRN3w5QnBprFE8q558uOWz31Esex3iVXIiUWGLRXztaoOKmmmyVezQpDK45qqg6y P4dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=2BQSxln3svi2n+JcH2fO7IYmtxAF9oG3oZ57LVMvl9I=; b=jHlMCfY6pk6Xbx3nVPjjKd/gnoYTnjbcbU+vRJq59/AJ1CaQjcCUOtA3gaHVxpuj6L vYcSMs/U5iLIRAGA3m1+EeyQ3RdEfXUwz4gGtmhxoP8Zlw+et1zj7HLkyb495AIvNRfU LAn5/dnqEaW333oMUh0jmMBMbT04kmUpZwYQeookYvJQyB6VlEk//4RuwA5p2Otb0YnL RG48bJV7K7i+C8UHQXKvGdTaAKMU/CgU9sOcmXD/2f7d0yfeTru8qMINgUeiMA0/IqLr avtu9BAoi8YJCv5cmhmaIeGH3OWeVKYGyfBUCN90peqS5+IEWrVrIskRfmvHPWkdOkcl J6rw== X-Gm-Message-State: AOAM531125g7rzVo7BNQqh3kuMc4wg8j1LNet2wowjlDlK7P9igvcYfh biZHsxPFRu6jAjEx/NAS3Cj6BO8kKICNEpCD0bk= X-Google-Smtp-Source: ABdhPJxjq2Kr5erAERLQfeQapKXK+/aN70E6+ma1cDpFCk3GnD/t4qOqF8GwRWZnqTg9cLyUjxeM1zp2ZQ3QXgxIWW8= X-Received: by 2002:a25:cc3:: with SMTP id 186mr4089880ybm.306.1611846028388; Thu, 28 Jan 2021 07:00:28 -0800 (PST) MIME-Version: 1.0 References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> <1611063546-20278-5-git-send-email-bmeng.cn@gmail.com> <34c45d74-adec-2734-830b-612b5e2f6083@amsat.org> <9a8312d7-d3b3-b896-a669-8ce8efc66bf0@amsat.org> <26b80ae5-f1e0-f438-a1e5-9922686be128@amsat.org> In-Reply-To: <26b80ae5-f1e0-f438-a1e5-9922686be128@amsat.org> From: Bin Meng Date: Thu, 28 Jan 2021 23:00:16 +0800 Message-ID: Subject: Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , Bin Meng , QEMU Developers , Jean-Christophe Dubois , qemu-arm , Alistair Francis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2f; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:00:45 -0000 On Thu, Jan 28, 2021 at 10:49 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/28/21 3:41 PM, Peter Maydell wrote: > > On Thu, 28 Jan 2021 at 14:32, Philippe Mathieu-Daud=C3=A9 wrote: > >> Oh I totally missed that :S > >> > >> Bin, I'd correct this as: > >> > >> - extract imx_spi_soft_reset(IMXSPIState *s) from imx_spi_reset() > >> - zero-initialize CONREG in imx_spi_reset(). > >> > >> static void imx_spi_soft_reset(IMXSPIState *s) > >> { > >> ... > >> } > >> > >> static void imx_spi_reset(DeviceState *dev) > >> { > >> IMXSPIState *s =3D IMX_SPI(dev); > >> > >> s->regs[ECSPI_CONREG] =3D 0; > >> imx_spi_soft_reset(s); > >> } > >> > >> What do you think? > > > > That doesn't give you anywhere to put the imx_spi_update_irq() > > call, which must happen only on soft reset and not on DeviceState > > reset. You could do one of: > > * have a 'common reset' function that does most of this, > > plus an imx_spi_reset which clears CONREG and calls > > common reset and an imx_spi_soft_reset which calls > > common reset and imx_spi_update_irq() > > * have imx_spi_soft_reset save the old CONREG in a local > > variable before calling imx_spi_reset and then restore it > > to s->regs > > Long term maintenance I'd prefer the 'common reset' approach > (but this is probably subjective to my view on the hardware, > since this is software, the 2nd approach is also valid but > harder to represent thinking of hardware). > > Bin, can you send a v9? (using the approach you prefer) > Yes, I will send a v9. Thanks Peter for the explanation on the QOM device reset scenarios. Regards, Bin From MAILER-DAEMON Thu Jan 28 10:24:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l599Z-0008HK-5b for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:24:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l599W-0008F6-VG for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:24:10 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:45857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l599V-0005qA-Ds for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:24:10 -0500 Received: by mail-ej1-x631.google.com with SMTP id ke15so8295392ejc.12 for ; Thu, 28 Jan 2021 07:24:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5C784LBgBqv2S0P5V2jlWW5dGwtZ4K4baKv/vb7rCMA=; b=Uubg8lZ+2DEEJ/wRzLMUq02jgTGZuFuNf9+YueUZlaGqYys1pHiUe5h9VDsVh/0gB/ vli/yla7zaouh8KXYyKBgL/nxTjT4lr1RqMtvJQukXzeRfcFdnP2PYW5nE6O87UM5i2f NL8opuZddYwumAEtFGRvJOgRwKgKikCPG2cfWhxJI5sRlEBfBTM8h7VTvd5dnsP9s+3F oeZ5wkVIcW64p3Txw2etYzd83miC4qZFBVInr9z8hJN73/QUfM7w+rdi8NX+us+wLHhA KqpoaEvPQqvjpkCsmu57hczOVeLZ48tiqS3RxP/68Vh02GZGgxuZaO414k1VYp2s62IN YKkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5C784LBgBqv2S0P5V2jlWW5dGwtZ4K4baKv/vb7rCMA=; b=X5EjHRHvRqFQL8BXc+f6rp8HDW1sVrzMd8GYi4D+AFyzrRcoLGTNAZubFTvN7OjzmA Fj8sHTE72ol5z7U/EleoVgQFSEqFPKl9h7aszmzJTLrQUum2BdLuQk837QsQ8bQRNcnt 2b7gVfSRZEyQJhCVqbmIn3CvZkVEcc0LAfG3YBfC6Rnr7XI2JcYxOhrngdzHRRbI011A qvj4m1dHiHxgxXjyLuDBfet8j+fdnUK6RPiJK7gwzCWwNJOUdycLb6Q/G+zgpLE8m9rY KoRizIJFVr3umBwrHN967LTg3lDVMMvBJybZcc/gcJFzH9t4XUUGrYuX1EZeuKbAh+ny zUSQ== X-Gm-Message-State: AOAM531qqrABscr2xwf3vIR0QCdKzPAoymu0KxHaKcnqV1h+wSyMglpT IaSFKdqgALITZzf0tUmLvTTBNbyykGcB8Mi+4Wtvxg== X-Google-Smtp-Source: ABdhPJwiSriSd/9oPr4oXDETr1Z+5jOdo+XtlERoCXxoSkyG1WNpq/I1eBhuK0r9xwTyxmrLYv8T0XpXCKFQ3XN6RD4= X-Received: by 2002:a17:906:3603:: with SMTP id q3mr11247368ejb.382.1611847447230; Thu, 28 Jan 2021 07:24:07 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-4-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-4-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 15:23:56 +0000 Message-ID: Subject: Re: [PATCH v6 03/11] hvf: Move common code out To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:24:11 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > Until now, Hypervisor.framework has only been available on x86_64 systems. > With Apple Silicon shipping now, it extends its reach to aarch64. To > prepare for support for multiple architectures, let's move common code out > into its own accel directory. > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Tested-by: Roman Bolshakov I was expecting this all to be pretty much pure code-motion, but it isn't. Examples: > +static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) > +{ > + struct mac_slot *macslot; > + hv_return_t ret; > + > + macslot = &mac_slots[slot->slot_id]; > + > + if (macslot->present) { > + if (macslot->size != slot->size) { > + macslot->present = 0; > + ret = hv_vm_unmap(macslot->gpa_start, macslot->size); > + assert_hvf_ok(ret); > + } > + } > + > + if (!slot->size) { > + return 0; > + } > + > + macslot->present = 1; > + macslot->gpa_start = slot->start; > + macslot->size = slot->size; > + ret = hv_vm_map(slot->mem, slot->start, slot->size, flags); In the old code this line is - ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags); > + assert_hvf_ok(ret); > + return 0; > +} > +static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on) > +{ > + hvf_slot *slot; > + > + slot = hvf_find_overlap_slot( > + section->offset_within_address_space, > + int128_get64(section->size)); > + > + /* protect region against writes; begin tracking it */ > + if (on) { > + slot->flags |= HVF_SLOT_LOG; > + hv_vm_protect((uintptr_t)slot->start, (size_t)slot->size, > + HV_MEMORY_READ); The casts here were different in the old code: - hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size, - HV_MEMORY_READ); And these changes look like they ought to be in a different patch: > void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, > SegmentCache *qseg, bool is_tr) > { > @@ -437,7 +438,7 @@ int hvf_process_events(CPUState *cpu_state) > env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS); > > if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { > - hvf_cpu_synchronize_state(cpu_state); > + cpu_synchronize_state(cpu_state); > do_cpu_init(cpu); > } > > @@ -451,12 +452,12 @@ int hvf_process_events(CPUState *cpu_state) > cpu_state->halted = 0; > } > if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { > - hvf_cpu_synchronize_state(cpu_state); > + cpu_synchronize_state(cpu_state); > do_cpu_sipi(cpu); > } > if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { > cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR; > - hvf_cpu_synchronize_state(cpu_state); > + cpu_synchronize_state(cpu_state); > apic_handle_tpr_access_report(cpu->apic_state, env->eip, > env->tpr_access_type); > } Could you go through and make sure that as much of possible of this patch is pure "cut from file A and paste into file B", please? The git diff --color-moved option is really helpful for this: the aim should be for the patch as much as possible to be the blues, yellows and purples of "this code just moved" and as few as possible lines of green/red "this code is deleted or added". (In some places it might be helpful to split parts of this change into separate patches, eg if you want to make a function 'static' when it was unnecessarily global before.) thanks -- PMM From MAILER-DAEMON Thu Jan 28 10:24:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59AH-0000UO-G6 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:24:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59AD-0000Ss-Vw; Thu, 28 Jan 2021 10:24:53 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59A9-0005xH-Qt; Thu, 28 Jan 2021 10:24:53 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DRPPQ4MfQzjDTL; Thu, 28 Jan 2021 23:23:22 +0800 (CST) Received: from [10.174.184.42] (10.174.184.42) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.498.0; Thu, 28 Jan 2021 23:24:13 +0800 Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: Kirti Wankhede , Paolo Bonzini References: <20210111073439.20236-1-zhukeqian1@huawei.com> <590a2752-9bba-6971-51b0-a8accee6e814@nvidia.com> CC: Alex Williamson , , , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , "Eduardo Habkost" , Peter Xu , "Dr . David Alan Gilbert" , Igor Mammedov , , Zenghui Yu , From: Keqian Zhu Message-ID: Date: Thu, 28 Jan 2021 23:24:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <590a2752-9bba-6971-51b0-a8accee6e814@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhukeqian1@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:24:54 -0000 Hi Paolo and Kirti, Many thanks for reply. I am busy today and will reply you tomorrow, Thanks. Keqian. On 2021/1/28 5:03, Kirti Wankhede wrote: > > > On 1/11/2021 1:04 PM, Keqian Zhu wrote: >> For now the switch of vfio dirty page tracking is integrated into >> the vfio_save_handler, it causes some problems [1]. >> > > Sorry, I missed [1] mail, somehow it didn't landed in my inbox. > >> The object of dirty tracking is guest memory, but the object of >> the vfio_save_handler is device state. This mixed logic produces >> unnecessary coupling and conflicts: >> >> 1. Coupling: Their saving granule is different (perVM vs perDevice). >> vfio will enable dirty_page_tracking for each devices, actually >> once is enough. > > That's correct, enabling dirty page tracking once is enough. But log_start and log_stop gets called on address space update transaction, region_add() or region_del(), at this point migration may not be active. We don't want to allocate bitmap memory in kernel for lifetime of VM, without knowing migration will be happen or not. vfio_iommu_type1 module should allocate bitmap memory only while migration is active. > > Paolo's suggestion here to use log_global_start and log_global_stop callbacks seems correct here. But at this point vfio device state is not yet changed to |_SAVING as you had identified it in [1]. May be we can start tracking bitmap in iommu_type1 module while device is not yet _SAVING, but getting dirty bitmap while device is yet not in _SAVING|_RUNNING state doesn't seem optimal solution. > > Pasting here your question from [1] > >> Before start dirty tracking, we will check and ensure that the device >> is at _SAVING state and return error otherwise. But the question is >> that what is the rationale? Why does the VFIO_IOMMU_DIRTY_PAGES >> ioctl have something to do with the device state? > > Lets walk through the types of devices we are supporting: > 1. mdev devices without IOMMU backed device > Vendor driver pins pages as and when required during runtime. We can say that vendor driver is smart which identifies the pages to pin. We are good here. > > 2. mdev device with IOMMU backed device > This is similar to vfio-pci, direct assigned device, where all pages are pinned at VM bootup. Vendor driver is not smart, so bitmap query will report all pages dirty always. If --auto-converge is not set, VM stucks infinitely in pre-copy phase. This is known to us. > > 3. mdev device with IOMMU backed device with smart vendor driver > In this case as well all pages are pinned at VM bootup, but vendor driver is smart to identify the pages and pin them explicitly. > Pages can be pinned anytime, i.e. during normal VM runtime or on setting _SAVING flag (entering pre-copy phase) or while in iterative pre-copy phase. There is no restriction based on these phases for calling vfio_pin_pages(). Vendor driver can start pinning pages based on its device state when _SAVING flag is set. In that case, if dirty bitmap is queried before that then it will report all sysmem as dirty with an unnecessary copy of sysmem. > As an optimal solution, I think its better to query bitmap only after all vfio devices are in pre-copy phase, i.e. after _SAVING flag is set. > >> 2. Conflicts: The ram_save_setup() traverses all memory_listeners >> to execute their log_start() and log_sync() hooks to get the >> first round dirty bitmap, which is used by the bulk stage of >> ram saving. However, it can't get dirty bitmap from vfio, as >> @savevm_ram_handlers is registered before @vfio_save_handler. >> > Right, but it can get dirty bitmap from vfio device in it's iterative callback > ram_save_pending -> > migration_bitmap_sync_precopy() .. -> > vfio_listerner_log_sync > > Thanks, > Kirti > >> Move the switch of vfio dirty_page_tracking into vfio_memory_listener >> can solve above problems. Besides, Do not require devices in SAVING >> state for vfio_sync_dirty_bitmap(). >> >> [1] https://www.spinics.net/lists/kvm/msg229967.html >> >> Reported-by: Zenghui Yu >> Signed-off-by: Keqian Zhu >> --- >> hw/vfio/common.c | 53 +++++++++++++++++++++++++++++++++++++-------- >> hw/vfio/migration.c | 35 ------------------------------ >> 2 files changed, 44 insertions(+), 44 deletions(-) >> >> diff --git a/hw/vfio/common.c b/hw/vfio/common.c >> index 6ff1daa763..9128cd7ee1 100644 >> --- a/hw/vfio/common.c >> +++ b/hw/vfio/common.c >> @@ -311,7 +311,7 @@ bool vfio_mig_active(void) >> return true; >> } >> -static bool vfio_devices_all_saving(VFIOContainer *container) >> +static bool vfio_devices_all_dirty_tracking(VFIOContainer *container) >> { >> VFIOGroup *group; >> VFIODevice *vbasedev; >> @@ -329,13 +329,8 @@ static bool vfio_devices_all_saving(VFIOContainer *container) >> return false; >> } >> - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { >> - if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) >> - && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { >> - return false; >> - } >> - continue; >> - } else { >> + if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) >> + && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { >> return false; >> } >> } >> @@ -987,6 +982,44 @@ static void vfio_listener_region_del(MemoryListener *listener, >> } >> } >> +static void vfio_set_dirty_page_tracking(VFIOContainer *container, bool start) >> +{ >> + int ret; >> + struct vfio_iommu_type1_dirty_bitmap dirty = { >> + .argsz = sizeof(dirty), >> + }; >> + >> + if (start) { >> + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; >> + } else { >> + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; >> + } >> + >> + ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); >> + if (ret) { >> + error_report("Failed to set dirty tracking flag 0x%x errno: %d", >> + dirty.flags, errno); >> + } >> +} >> + >> +static void vfio_listener_log_start(MemoryListener *listener, >> + MemoryRegionSection *section, >> + int old, int new) >> +{ >> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >> + >> + vfio_set_dirty_page_tracking(container, true); >> +} >> + >> +static void vfio_listener_log_stop(MemoryListener *listener, >> + MemoryRegionSection *section, >> + int old, int new) >> +{ >> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >> + >> + vfio_set_dirty_page_tracking(container, false); >> +} >> + >> static int vfio_get_dirty_bitmap(VFIOContainer *container, uint64_t iova, >> uint64_t size, ram_addr_t ram_addr) >> { >> @@ -1128,7 +1161,7 @@ static void vfio_listerner_log_sync(MemoryListener *listener, >> return; >> } >> - if (vfio_devices_all_saving(container)) { >> + if (vfio_devices_all_dirty_tracking(container)) { >> vfio_sync_dirty_bitmap(container, section); >> } >> } >> @@ -1136,6 +1169,8 @@ static void vfio_listerner_log_sync(MemoryListener *listener, >> static const MemoryListener vfio_memory_listener = { >> .region_add = vfio_listener_region_add, >> .region_del = vfio_listener_region_del, >> + .log_start = vfio_listener_log_start, >> + .log_stop = vfio_listener_log_stop, >> .log_sync = vfio_listerner_log_sync, >> }; >> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c >> index 00daa50ed8..c0f646823a 100644 >> --- a/hw/vfio/migration.c >> +++ b/hw/vfio/migration.c >> @@ -395,40 +395,10 @@ static int vfio_load_device_config_state(QEMUFile *f, void *opaque) >> return qemu_file_get_error(f); >> } >> -static int vfio_set_dirty_page_tracking(VFIODevice *vbasedev, bool start) >> -{ >> - int ret; >> - VFIOMigration *migration = vbasedev->migration; >> - VFIOContainer *container = vbasedev->group->container; >> - struct vfio_iommu_type1_dirty_bitmap dirty = { >> - .argsz = sizeof(dirty), >> - }; >> - >> - if (start) { >> - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { >> - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; >> - } else { >> - return -EINVAL; >> - } >> - } else { >> - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; >> - } >> - >> - ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); >> - if (ret) { >> - error_report("Failed to set dirty tracking flag 0x%x errno: %d", >> - dirty.flags, errno); >> - return -errno; >> - } >> - return ret; >> -} >> - >> static void vfio_migration_cleanup(VFIODevice *vbasedev) >> { >> VFIOMigration *migration = vbasedev->migration; >> - vfio_set_dirty_page_tracking(vbasedev, false); >> - >> if (migration->region.mmaps) { >> vfio_region_unmap(&migration->region); >> } >> @@ -469,11 +439,6 @@ static int vfio_save_setup(QEMUFile *f, void *opaque) >> return ret; >> } >> - ret = vfio_set_dirty_page_tracking(vbasedev, true); >> - if (ret) { >> - return ret; >> - } >> - >> qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE); >> ret = qemu_file_get_error(f); >> > . > From MAILER-DAEMON Thu Jan 28 10:25:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59BB-0000vS-Fl for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:25:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59B9-0000rV-Q8 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:25:51 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:43043) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l59B6-0006Ne-E2 for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 07:25:46 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-6-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-6-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 15:25:34 +0000 Message-ID: Subject: Re: [PATCH v6 05/11] arm: Set PSCI to 0.2 for HVF To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:25:52 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > In Hypervisor.framework, we just pass PSCI calls straight on to the QEMU emulation > of it. That means, if TCG is compatible with PSCI 0.2, so are we. Let's transpose > that fact in code too. > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Reviewed-by: Peter Maydell thanks -- PMM From MAILER-DAEMON Thu Jan 28 10:28:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59Di-0003eY-DM for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:28:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59Dg-0003eH-I9 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:28:28 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:42466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l59Df-0007Q8-3e for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:28:28 -0500 Received: by mail-ed1-x52a.google.com with SMTP id z22so7060191edb.9 for ; Thu, 28 Jan 2021 07:28:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FW8IrmaDYnWKdgHUXE+sN4Ii+nBJ56wUbQ4Ky9VXiQ0=; b=lDPS3YDbrJYkyQx+5k2w6iVRdRqsFjM+OSB0/fsWeIHwtmEwEnAPohHDlauqMf6n57 9diZ/RRoIspYJg4cXbd88cwJHltkqZ84k4aIkb7hDfxa/tBAo4KMZ/iXpeXhntzH8Ib7 f+tIyW2vwZVHk0Kb4Vvvl9tbclrxISZRhlsNw9AtAFyamH4fhc/d1ykEvA6f9MklszyH gNlnWsrBVa7iWg4AGsXzZpM4awpBUnWcqRgr7GC5GN/oH95KUsYaIJ7KW6AVIK93YuEu n7KgOSMZJQ+SfE3kZWg/3sOfUAjq5vcSAzk6OaezcQuCPMGVEq0VxSM3iPafzQ8QQdqc RT1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FW8IrmaDYnWKdgHUXE+sN4Ii+nBJ56wUbQ4Ky9VXiQ0=; b=Q/3MH3zZWIGZAMkB0s5SZe1doPnsrhmfs7DRJyPNs0lSrJroE6X44IFyBh0EQ3JrJ8 YMn8Zqyg96ExP5bTEV0KAO5unWPnX68n/dNdrNrb/99K0kbfDcjc3uoLEXaaD9q3XwKv Z0yVQKyaC+S0DTyQKvkICGEZAirCGh1ylWe6mgCZsgCD7YBcfgB5Y2qLhTSOAlU51G52 +cREz/T1SMl7dngrHaiVSYR1F3F00MQxbBvNMx+LGkhkFHZcCMotE714OYmt2QwO/maH H6DRiKq4J8pRq+UOFL4Di3cD6r9dR9GLh0K2JBPF2js8WeIV0ygG+fSlRtxrzVVUN02W k8ww== X-Gm-Message-State: AOAM533CuVFcpL7htc3GcRqaWkBnKyAf0lDM0jKOywjW1BINMk44g7fi raLoAcxxCeeojCNGg8Pvh7+GhWLKpqotkixT0YHsww== X-Google-Smtp-Source: ABdhPJyb1X0gN+TZgnJ//UXOa7yuRQpUKvSBi/YBBeSwoRX/2wRfzzyWe7Y/bY6U/axogZzvsq/PdWMSIknxS25ZHPo= X-Received: by 2002:aa7:c88a:: with SMTP id p10mr54516eds.204.1611847705567; Thu, 28 Jan 2021 07:28:25 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-7-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-7-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 15:28:13 +0000 Message-ID: Subject: Re: [PATCH v6 06/11] hvf: Simplify post reset/init/loadvm hooks To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:28:28 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > The hooks we have that call us after reset, init and loadvm really all > just want to say "The reference of all register state is in the QEMU > vcpu struct, please push it". > > We already have a working pushing mechanism though called cpu->vcpu_dirty, > so we can just reuse that for all of the above, syncing state properly the > next time we actually execute a vCPU. > > This fixes PSCI resets on ARM, as they modify CPU state even after the > post init call has completed, but before we execute the vCPU again. > > To also make the scheme work for x86, we have to make sure we don't > move stale eflags into our env when the vcpu state is dirty. > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Tested-by: Roman Bolshakov What's the difference between HVF and KVM that means this code doesn't have the same structure the KVM code does here? thanks -- PMM From MAILER-DAEMON Thu Jan 28 10:43:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59Rv-00020R-S2 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59Rl-0001x1-6G for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:43:06 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:55351) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l59Rj-0004J8-3S for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:43:00 -0500 Received: by mail-wm1-x335.google.com with SMTP id f16so4670667wmq.5 for ; Thu, 28 Jan 2021 07:42:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:user-agent:from:to:cc:subject:date:in-reply-to :message-id:mime-version:content-transfer-encoding; bh=12mnrR8ms+5WwSs+PQVzHOmb66VScSLabLuV3gix8ak=; b=kuTguAq0PIxh75dPU2EoEK+kClZITPzeJAUWVxlLI4qXRRy0EHl5JbOERJ2BxGOyRM yT9Tn2JPqLmUg1A3k8U6kD+EsS/KfoJGq9MFVYh1n8kwm6jXSeAX2yYYRA7aC9a1Tz6n 0GCdFo8Jl+PO5frszxrgjaOu4QaG1xRcSPJ8EJY2gfZN8GPFN+cNDPBLf9r43uEjFP1y cNa99zIFL8b2J2DfkG7gudABYoDzAsb7EoAiXxTgM9xjF4L79iif28PCWFM98gV85lYI mF4/w+be+bo5oU8WNNF4yL9GPmFxOZgI2MR7EO0+zvwHSE+o8VkEvGppO+YJPgKIMJB2 deLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:references:user-agent:from:to:cc:subject:date :in-reply-to:message-id:mime-version:content-transfer-encoding; bh=12mnrR8ms+5WwSs+PQVzHOmb66VScSLabLuV3gix8ak=; b=XoiKVNoioe9UsLwzEXRT78EHUgY6Km5YSy1i1ITx4vsdpRi3wnWei4O3V8y8W9Rh+P j+BRrDekgnzP4mAJXLX/xa2ZRcEpvZLIny0x3cWo87W0zRkeoFLOclbn0IZxoNg8sGBu yQa0vxnQcu0BH3UbZpgZZtXgBMkntaLIys9KmfDsWHThn5u/YrD4R75sLuvA9S1zlZo+ o2pwxBjmbnwkYa2hxSJvOykhpk89ZZ0MP0ZQQwYTmyblLawG4TE0mQD3J8QjurF6F9Qh BtqDQq4U3pFLggMTZ+YHyKvZcO1fkJFEt0uGdcZVEWkfGEC1ilvQrwiQJnjJkdLBZDj8 hE2Q== X-Gm-Message-State: AOAM531UzZh9XrAqwnwj5IuxNHjv0E5x5blfUKNWWl4gtqy11AdY09zb YF6TEO2vQkShc2SRJiyiD9zm6A== X-Google-Smtp-Source: ABdhPJyuRinAeKRNz0U8QY7HX488Da2kP0mO3x8wMmScPfiPSOxC3b+qIw/y4ga4d/V9tTSnOTvOrQ== X-Received: by 2002:a1c:ed0b:: with SMTP id l11mr9248340wmh.47.1611848576851; Thu, 28 Jan 2021 07:42:56 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y14sm7258669wro.58.2021.01.28.07.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 07:42:55 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A63981FF7E; Thu, 28 Jan 2021 15:42:54 +0000 (GMT) References: <20200929224355.1224017-1-philmd@redhat.com> <87r1m5x56h.fsf@linaro.org> <98f06a0a-efe6-c630-8e68-0e4559f04d58@redhat.com> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Claudio Fontana , qemu-devel@nongnu.org, Thomas Huth , Paolo Bonzini , Richard Henderson , Fam Zheng , Peter Maydell , kvm@vger.kernel.org, qemu-arm@nongnu.org, Richard Henderson Subject: Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Date: Thu, 28 Jan 2021 15:42:38 +0000 In-reply-to: <98f06a0a-efe6-c630-8e68-0e4559f04d58@redhat.com> Message-ID: <87bld9ukxt.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:43:08 -0000 Philippe Mathieu-Daud=C3=A9 writes: > Hi Alex, > > On 1/28/21 1:41 AM, Alex Benn=C3=A9e wrote: >> Philippe Mathieu-Daud=C3=A9 writes: >>=20 >>> Cover from Samuel Ortiz from (part 1) [1]: >>> >>> This patchset allows for building and running ARM targets with TCG >>> disabled. [...] >>> >>> The rationale behind this work comes from the NEMU project where we're >>> trying to only support x86 and ARM 64-bit architectures, without >>> including the TCG code base. We can only do so if we can build and run >>> ARM binaries with TCG disabled. >>> >>> v4 almost 2 years later... [2]: >>> - Rebased on Meson >>> - Addressed Richard review comments >>> - Addressed Claudio review comments >>=20 >> Have you re-based recently because I was having a look but ran into >> merge conflicts. I'd like to get the merged at some point because I ran >> into similar issues with the Xen only build without TCG. > > I addressed most of this review comments locally. Since Claudio's > accelerator series was getting more attention (and is bigger) I was > waiting it gets merged first. He just respun v14: > https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07171.html OK I'll have a look at Claudio's first ;-) --=20 Alex Benn=C3=A9e From MAILER-DAEMON Thu Jan 28 10:52:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59b7-00029C-SY for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 10:52:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59b5-00026n-St for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:52:39 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]:36845) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l59b3-00081z-G7 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 10:52:39 -0500 Received: by mail-ej1-x634.google.com with SMTP id l9so8516013ejx.3 for ; Thu, 28 Jan 2021 07:52:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zF8xeAznwgn4L/OdyBHBQ5UOpYDEsDc3ed21kkQniYI=; b=e7dlQYzZ0toMRVoIdrmp0UvbfXFQfD5JzJMR9IanrWoH5id1wVGBdurAHnh9dJsBn9 2Wzm4wREsis68L7pYX/W4ICKh2XngiTAL3HgnuthK41J92Uy5efHo2kFUNDppBNp/3uo 9dJVMY7tzgIPA6/eJ0D8MfxDocR1wLkp0zjKCzvPEjNAF2jcIXgIrtJiZSmdC1oTl0Vu aTGPG+sVHlIZpNgk0wPh8DHz7LE8cubobVUV7BA6WiA+i2Wq6Q9fNvdLlDRVD59vsSdq g1XYBp2oHfUdI/h6KBwx5Cm3/iarPHoVujhMYKrlqdsDxl3s2mQNHHm7wbZv6o6h8V7q sRzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zF8xeAznwgn4L/OdyBHBQ5UOpYDEsDc3ed21kkQniYI=; b=SkDRkyncSrBYykYA0v23na/N9dLPtZz9dJP8t3EXOkS/VgC1mWZAh4BFAfBep5scHO y0dbfDIJ7TAFNeqUPEIDbxAPDaFxYNcUMlVAfcAEFpBpUtKDf6EKmkPanIGb7s2tE48V g5ySyrFyCf2ahpIGLWuP117oyU8AYGJjaEw0iA/0YrdnA2ollyrDEEPXBuF446P1Zugp l/mnKhH0wF/BwyB9apSKZeHsrs268hOh0E2BASbICLhx4VOupZEI9k/ftlDEJ2rXvdqf 896rf0z15BwBvSBvJu6JZFhy9g6pt/ZJOab0oCvfkQ6qu9A29kPiYshEZEOxguy98zhD 5XiQ== X-Gm-Message-State: AOAM532Z8x1URRso53CJuy1st7jRckdM/hM81NoY5At+Du1s4YcCQ9nk /0XmRFxa+hLNGvgw9I7aZ6OFxazvanXHOws5zqBTWg== X-Google-Smtp-Source: ABdhPJwK/ZZcjNrKUbn+ipl10ut5by/3e2gObX+MQuvFJznvx34fVkLv+HL0ZXv2Z9zRdHV26+ntP643rd5ec1ee1II= X-Received: by 2002:a17:906:b215:: with SMTP id p21mr11571615ejz.407.1611849153114; Thu, 28 Jan 2021 07:52:33 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-8-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-8-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 15:52:21 +0000 Message-ID: Subject: Re: [PATCH v6 07/11] hvf: Add Apple Silicon support To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 15:52:40 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > With Apple Silicon available to the masses, it's a good time to add support > for driving its virtualization extensions from QEMU. > > This patch adds all necessary architecture specific code to get basic VMs > working. It's still pretty raw, but definitely functional. > > Known limitations: > > - Vtimer acknowledgement is hacky > - Should implement more sysregs and fault on invalid ones then > - WFI handling is missing, need to marry it with vtimer > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > --- a/accel/hvf/hvf-cpus.c > +++ b/accel/hvf/hvf-cpus.c > @@ -58,6 +58,10 @@ > #include "sysemu/runstate.h" > #include "qemu/guest-random.h" > > +#ifdef __aarch64__ > +#define HV_VM_DEFAULT NULL > +#endif > /* Memory slots */ > > struct mac_slot { > @@ -328,7 +332,11 @@ static int hvf_init_vcpu(CPUState *cpu) > pthread_sigmask(SIG_BLOCK, NULL, &set); > sigdelset(&set, SIG_IPI); > > +#ifdef __aarch64__ > + r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); > +#else > r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); > +#endif > cpu->vcpu_dirty = 1; > assert_hvf_ok(r); > > @@ -399,8 +407,14 @@ static void hvf_start_vcpu_thread(CPUState *cpu) > cpu, QEMU_THREAD_JOINABLE); > } > > +__attribute__((weak)) void hvf_kick_vcpu_thread(CPUState *cpu) > +{ > + cpus_kick_thread(cpu); > +} > + > static const CpusAccel hvf_cpus = { > .create_vcpu_thread = hvf_start_vcpu_thread, > + .kick_vcpu_thread = hvf_kick_vcpu_thread, > > .synchronize_post_reset = hvf_cpu_synchronize_post_reset, > .synchronize_post_init = hvf_cpu_synchronize_post_init, > diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h > index 9d3cb53e47..c2ac6c8f97 100644 > --- a/include/sysemu/hvf_int.h > +++ b/include/sysemu/hvf_int.h > @@ -11,7 +11,12 @@ > #ifndef HVF_INT_H > #define HVF_INT_H > > +#include "qemu/osdep.h" .h files must never include osdep.h (all .c files do as their first include line). > +#ifdef __aarch64__ > +#include > +#else > #include > +#endif > > /* hvf_slot flags */ > #define HVF_SLOT_LOG (1 << 0) > @@ -44,7 +49,8 @@ struct HVFState { > extern HVFState *hvf_state; > > struct hvf_vcpu_state { > - int fd; > + uint64_t fd; Why the change in the type for 'fd' ? > + void *exit; Can we define this as a "hv_vcpu_exit_t *" so we don't have to cast it in the call to hv_vcpu_create() ? > }; > > void assert_hvf_ok(hv_return_t ret); > @@ -54,5 +60,6 @@ int hvf_arch_init_vcpu(CPUState *cpu); > void hvf_arch_vcpu_destroy(CPUState *cpu); > int hvf_vcpu_exec(CPUState *cpu); > hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); > +void hvf_kick_vcpu_thread(CPUState *cpu); > > #endif > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > new file mode 100644 > index 0000000000..8f18efe856 > --- /dev/null > +++ b/target/arm/hvf/hvf.c > @@ -0,0 +1,618 @@ > +/* > + * QEMU Hypervisor.framework support for Apple Silicon > + > + * Copyright 2020 Alexander Graf > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "qemu/error-report.h" > + > +#include "sysemu/runstate.h" > +#include "sysemu/hvf.h" > +#include "sysemu/hvf_int.h" > +#include "sysemu/hw_accel.h" > + > +#include "exec/address-spaces.h" > +#include "hw/irq.h" > +#include "qemu/main-loop.h" > +#include "sysemu/accel.h" > +#include "sysemu/cpus.h" > +#include "target/arm/cpu.h" > +#include "target/arm/internals.h" > + > +#define HVF_DEBUG 0 > +#define DPRINTF(...) \ > + if (HVF_DEBUG) { \ > + fprintf(stderr, "HVF %s:%d ", __func__, __LINE__); \ > + fprintf(stderr, __VA_ARGS__); \ > + fprintf(stderr, "\n"); \ > + } No new DPRINTF macros, please. Use tracepoints. > + > +#define HVF_SYSREG(crn, crm, op0, op1, op2) \ > + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) > +#define PL1_WRITE_MASK 0x4 > + > +#define SYSREG(op0, op1, crn, crm, op2) \ > + ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1)) > +#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7) > +#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) > +#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) > + > +#define WFX_IS_WFE (1 << 0) > +static const struct hvf_sreg_match hvf_sreg_match[] = { > + { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, > + { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, > + { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, > + { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, I'm not a huge fan of this big long hardcoded list of registers. Is there some way to work from either the QEMU cpregs hashtable or asking the hypervisor framework about what sysregs it has? (Compare the KVM approach, though I admit it has its own issues, so if there's a genuinely better way to do something I'm not ruling it out on principle.) > +#ifdef SYNC_NO_RAW_REGS What's this ifdef for? > +int hvf_get_registers(CPUState *cpu) > +{ > + ARMCPU *arm_cpu = ARM_CPU(cpu); > + CPUARMState *env = &arm_cpu->env; > + hv_return_t ret; > + uint64_t val; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { > + ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); > + *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; > + assert_hvf_ok(ret); > + } > + > + val = 0; > + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); > + assert_hvf_ok(ret); > + vfp_set_fpcr(env, val); > + > + val = 0; > + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); > + assert_hvf_ok(ret); > + vfp_set_fpsr(env, val); > + > + ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); > + assert_hvf_ok(ret); > + pstate_write(env, val); > + > + for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { > + ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val); > + assert_hvf_ok(ret); > + > + arm_cpu->cpreg_values[i] = val; > + } > + write_list_to_cpustate(arm_cpu); Have I missed it, or are we not syncing the FPU/vector registers? > + return 0; > +} > + if (iswrite) { > + val = hvf_get_reg(cpu, srt); > + address_space_write(&address_space_memory, > + hvf_exit->exception.physical_address, > + MEMTXATTRS_UNSPECIFIED, &val, len); Does the hvf framework provide a way to report the external-abort if address_space_write() returns something other than MEMTX_OK ? > + break; > + case EC_AA64_SMC: > + cpu_synchronize_state(cpu); > + if (arm_is_psci_call(arm_cpu, EXCP_SMC)) { > + arm_handle_psci_call(arm_cpu); Have you checked that all the PSCI code really can cope with being called from a non-TCG accelerator? (As an example the CPU_SUSPEND implementation calls the TCG wfi helper...) > + } else { > + DPRINTF("unknown SMC! %016llx", env->xregs[0]); > + env->xregs[0] = -1; This should inject an UNDEF exception into the guest. (Compare the pre_smc helper in target/arm/op_helper.c for TCG.) > + } > + env->pc += 4; > + break; > + default: > + cpu_synchronize_state(cpu); > + DPRINTF("exit: %llx [ec=0x%x pc=0x%llx]", syndrome, ec, env->pc); > + error_report("%llx: unhandled exit %llx", env->pc, exit_reason); Hex values should have leading '0x'. > + } > + > + if (advance_pc) { > + uint64_t pc; > + > + flush_cpu_state(cpu); > + > + r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); > + assert_hvf_ok(r); > + pc += 4; > + r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); > + assert_hvf_ok(r); > + } > + } > +} thanks -- PMM From MAILER-DAEMON Thu Jan 28 11:00:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59j5-0005zi-0M for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 11:00:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49424) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59j3-0005yh-K0 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:00:53 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:42380) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l59j0-00034c-1o for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 08:00:47 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-9-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-9-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 16:00:35 +0000 Message-ID: Subject: Re: [PATCH v6 08/11] arm: Add Hypervisor.framework build target To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:00:53 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > Now that we have all logic in place that we need to handle Hypervisor.framework > on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we > can build it. > > Signed-off-by: Alexander Graf > Reviewed-by: Roman Bolshakov > Tested-by: Roman Bolshakov (x86 only) > > --- > > v1 -> v2: > > - Fix build on 32bit arm > > v3 -> v4: > > - Remove i386-softmmu target > --- > meson.build | 11 ++++++++++- > target/arm/hvf/meson.build | 3 +++ > target/arm/meson.build | 2 ++ > 3 files changed, 15 insertions(+), 1 deletion(-) > create mode 100644 target/arm/hvf/meson.build > > diff --git a/meson.build b/meson.build > index c667d64498..8302fcbd90 100644 > --- a/meson.build > +++ b/meson.build > @@ -74,16 +74,25 @@ else > endif > > accelerator_targets = { 'CONFIG_KVM': kvm_targets } > + > +if cpu in ['x86', 'x86_64'] We don't support 32-bit x86 hosts so I don't think you need the 'x86' here. > + hvf_targets = ['x86_64-softmmu'] > +elif cpu in ['aarch64'] > + hvf_targets = ['aarch64-softmmu'] > +else > + hvf_targets = [] > +endif > + > if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] > # i368 emulator provides xenpv machine type for multiple architectures > accelerator_targets += { > 'CONFIG_XEN': ['i386-softmmu', 'x86_64-softmmu'], > + 'CONFIG_HVF': hvf_targets, This 'if' is specific to the weird Xen thing where for arm hosts we build the Xen code into a qemu-system-i386/qemu-system-x86_64, so it's the wrong place to add HVF stuff. I think what you want is to follow the same pattern as the KVM stuff, so just accelerator_targets += { 'CONFIG_HVF': hvf_targets } after the if-ladder where you're setting hvf_targets. thanks -- PMM From MAILER-DAEMON Thu Jan 28 11:14:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l59wK-0007Po-KN for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 11:14:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l59wE-0007Op-Vd for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:14:32 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:40542) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l59wA-00017c-3j for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:14:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611850464; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Vohs2+KlSVFNeHtYycpizObEwEjoJ1/fOO/41o5aITY=; b=SYZGCtq2zkw8U8w7vL/i/Zs51M2bEdN8PvVfyUsE6wTCeIqd5DV2bz7YW9w9/eUX7sNB9Z wKAHw2lITEPLCRjy5K8klPMR70HQuoIO+/jk+Dl7qoDygloPkY6V8UyJ9XZy4DdEnfASAF woonTEbVuLjUTKWW2XXcRot+Xa8Y3T4= Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-413-C1s-QkaCOqKrmrVeHYgqzg-1; Thu, 28 Jan 2021 11:14:23 -0500 X-MC-Unique: C1s-QkaCOqKrmrVeHYgqzg-1 Received: by mail-ej1-f71.google.com with SMTP id k3so2393927ejr.16 for ; Thu, 28 Jan 2021 08:14:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Vohs2+KlSVFNeHtYycpizObEwEjoJ1/fOO/41o5aITY=; b=LEPZ76xOB6jbsn0KaGl1IBm+ktMQ/RCObyQiG5Msncxi88qJd7XMfbG3j+jA/0P/nf g0Fx2QTP3NWTuRjHPRRwkBbG2FjUgyA35/IhnN7CwqQ5+DU9XX5w5M4A8WaTLWH2r1NK SK3kfYQmjtjsK33KGUH6M+oZjWNaIGrZMLzCJIQjE/YkB+vNISo+N7Wb3HSMzpiDBTcg d1KUfFYDQHfsdzx4yVCBt9sw4YYWXH8dJR1L9LhBa/HHOO19WcbOckZSzX2ScjneOvzc ykmL0Z96UjZ8Y8tp98CNHw7hhtgPfsPz1CaPUquaiRtFannemZHjg1wcD4uEdDfckQd/ xo9g== X-Gm-Message-State: AOAM5312qAhhWfDTHNSyy46xP6IatM+ySjzF5Cn2DTasBcKwXuhRpiG1 aQgfivaql0lVj0Vy0XlcJcAJn1ezvjMg1Xpn46A3sYIg3Efab2knSZ7b3GjOuHEAEm33YQSzyU3 hhLBm49fbLqjx X-Received: by 2002:a17:907:9801:: with SMTP id ji1mr105096ejc.420.1611850460860; Thu, 28 Jan 2021 08:14:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJwETFK6s9x6Et2enzglxqyxoYvDTpxdk3h5aBGxXxI3joXyTiC9FW6ySz2kRhkvp13xaXtuqg== X-Received: by 2002:a17:907:9801:: with SMTP id ji1mr105069ejc.420.1611850460550; Thu, 28 Jan 2021 08:14:20 -0800 (PST) Received: from x1w.redhat.com (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id lz27sm2464220ejb.50.2021.01.28.08.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 08:14:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Peter Maydell , Thomas Huth , qemu-arm@nongnu.org, Darren Kenny , Eric Auger , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Bulekov Subject: [PATCH] hw/intc/arm_gic: Allow to use QTest without crashing Date: Thu, 28 Jan 2021 17:14:17 +0100 Message-Id: <20210128161417.3726358-1-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:14:32 -0000 Alexander reported an issue in gic_get_current_cpu() using the fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible doing: $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio [I 1611849440.651452] OPENED [R +0.242498] readb 0xf03ff000 hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState') SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in AddressSanitizer:DEADLYSIGNAL ================================================================= ==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) ==3719691==The signal is caused by a READ memory access. #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 #3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9 #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18 #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16 #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9 #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23 #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18 #10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18 #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13 #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 current_cpu is NULL because QTest accelerator does not use CPU. Fix by skipping the check and returning the first CPU index when QTest accelerator is used, similarly to commit c781a2cc423 ("hw/i386/vmport: Allow QTest use without crashing"). Reported-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/arm_gic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index af41e2fb448..c33b1c8c4bc 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -28,6 +28,7 @@ #include "qemu/module.h" #include "trace.h" #include "sysemu/kvm.h" +#include "sysemu/qtest.h" /* #define DEBUG_GIC */ @@ -57,7 +58,7 @@ static const uint8_t gic_id_gicv2[] = { static inline int gic_get_current_cpu(GICState *s) { - if (s->num_cpu > 1) { + if (!qtest_enabled() && s->num_cpu > 1) { return current_cpu->cpu_index; } return 0; -- 2.26.2 From MAILER-DAEMON Thu Jan 28 11:25:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5A7I-0000mm-Bo for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 11:25:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5A7H-0000jx-3Q for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:25:55 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:43374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5A7E-0005GM-BQ for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:25:54 -0500 Received: by mail-ed1-x531.google.com with SMTP id n6so7280397edt.10 for ; Thu, 28 Jan 2021 08:25:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tJuGslgeW7w4cAv44iEm6ui16UJgZucXEB/uRmVEIrs=; b=UcmAC4E9+LvX0HJlehbjSZR5vVMgK7rVTCQV1n5kBA8OgFxe0hWCYvN9jKbUDGDWHh 461Iu6A5GArzS3XPJSyLcxSxBcXAuKFHdh3BQcs4UqQY+ShgCGdLecXxbm9abSSbB1c7 yjl3RrxT5+GB8Cr8FH3V7LuOhNFDIiVxug8lyW0s0oPIoXCgTna5j9xVnV0UAEQh29Nq WWcWRgzX0uAZVhLifrmsQSVu4d0yzM+J2WPou/kTFHH8HsFWpLl+ewjH/Cnoi6apKH39 +5JbJ9J46IUL4ciNuYeYAKLPj/2FOmVguQsX6/evgE2/QOkC3IUmD9rn6ltQnvgUOlOD V1yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tJuGslgeW7w4cAv44iEm6ui16UJgZucXEB/uRmVEIrs=; b=XqwCQHBQ3YSaWJvlMLJvDytQG9We6PqHe7WhwpiZBzuUtEIDpJlEJss1xbqvjQfsIf 3wxawyTN1oinO/dOIIPotJkUNANskRDeLVP0ygUc1M2BLUTgrE1gwqlbOqmGNxqPMlvt 9FXLqMF8abeNBMbt6Rgrvg7bwnJ8LCB77EmW+VvzuDWa7DAiUKPK+pFvrBGyZrg7tFdq NPy+li8YKmFaw64FxloBm40fuNrD3VK20cLKWIUufja+V839oMmKQIFZ1OI2C3Qj/DpK B7db5nLUkUO008uYrwI/RXa6HuqTvHSNg6zHrLLJge7b/QnJYcFVscHRq9af9TexHvN7 de8w== X-Gm-Message-State: AOAM533Kerv/N+agjo2oEBKveMITcxhC5P1/SS6728+XnMXfV6+8Qqhn B8yTifiXhWxrcCPJqRkscWFn5Y7SAIX7d3Bfw1eXWQ== X-Google-Smtp-Source: ABdhPJxei/RWxTdcY9JIW0jILLK8i1rQZwjJQ69EqJCkNzPSWssmwKpw+lAIye6GsVahdOofzKl8tsoyUIiC6nNmjA0= X-Received: by 2002:a05:6402:5107:: with SMTP id m7mr381301edd.52.1611851150324; Thu, 28 Jan 2021 08:25:50 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-10-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-10-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 16:25:39 +0000 Message-ID: Subject: Re: [PATCH v6 09/11] arm/hvf: Add a WFI handler To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:25:55 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > From: Peter Collingbourne > > Sleep on WFI until the VTIMER is due but allow ourselves to be woken > up on IPI. > > In this implementation IPI is blocked on the CPU thread at startup and > pselect() is used to atomically unblock the signal and begin sleeping. > The signal is sent unconditionally so there's no need to worry about > races between actually sleeping and the "we think we're sleeping" > state. It may lead to an extra wakeup but that's better than missing > it entirely. > > Signed-off-by: Peter Collingbourne > [agraf: Remove unused 'set' variable, always advance PC on WFX trap] > Signed-off-by: Alexander Graf > Acked-by: Roman Bolshakov > --- > accel/hvf/hvf-cpus.c | 5 ++-- > include/sysemu/hvf_int.h | 1 + > target/arm/hvf/hvf.c | 56 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 59 insertions(+), 3 deletions(-) > > diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c > index 6d70ee742e..abef6a58f7 100644 > --- a/accel/hvf/hvf-cpus.c > +++ b/accel/hvf/hvf-cpus.c > @@ -322,15 +322,14 @@ static int hvf_init_vcpu(CPUState *cpu) > cpu->hvf = g_malloc0(sizeof(*cpu->hvf)); > > /* init cpu signals */ > - sigset_t set; > struct sigaction sigact; > > memset(&sigact, 0, sizeof(sigact)); > sigact.sa_handler = dummy_signal; > sigaction(SIG_IPI, &sigact, NULL); > > - pthread_sigmask(SIG_BLOCK, NULL, &set); > - sigdelset(&set, SIG_IPI); > + pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); > + sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); > > #ifdef __aarch64__ > r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL); > diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h > index c2ac6c8f97..7a397fe85a 100644 > --- a/include/sysemu/hvf_int.h > +++ b/include/sysemu/hvf_int.h > @@ -51,6 +51,7 @@ extern HVFState *hvf_state; > struct hvf_vcpu_state { > uint64_t fd; > void *exit; > + sigset_t unblock_ipi_mask; > }; > > void assert_hvf_ok(hv_return_t ret); > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > index 8f18efe856..f0850ab14a 100644 > --- a/target/arm/hvf/hvf.c > +++ b/target/arm/hvf/hvf.c > @@ -2,6 +2,7 @@ > * QEMU Hypervisor.framework support for Apple Silicon > > * Copyright 2020 Alexander Graf > + * Copyright 2020 Google LLC > * > * This work is licensed under the terms of the GNU GPL, version 2 or later. > * See the COPYING file in the top-level directory. > @@ -17,6 +18,8 @@ > #include "sysemu/hvf_int.h" > #include "sysemu/hw_accel.h" > > +#include > + > #include "exec/address-spaces.h" > #include "hw/irq.h" > #include "qemu/main-loop.h" > @@ -411,6 +414,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) > > void hvf_kick_vcpu_thread(CPUState *cpu) > { > + cpus_kick_thread(cpu); > hv_vcpus_exit(&cpu->hvf->fd, 1); > } > > @@ -466,6 +470,18 @@ static int hvf_inject_interrupts(CPUState *cpu) > return 0; > } > > +static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) > +{ > + /* > + * Use pselect to sleep so that other threads can IPI us while we're > + * sleeping. > + */ > + qatomic_mb_set(&cpu->thread_kicked, false); > + qemu_mutex_unlock_iothread(); > + pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); > + qemu_mutex_lock_iothread(); > +} It seems a bit odd that this is specific to Arm hvf. Doesn't x86 hvf need "pause until interrupt" functionality ? > + > int hvf_vcpu_exec(CPUState *cpu) > { > ARMCPU *arm_cpu = ARM_CPU(cpu); > @@ -577,6 +593,46 @@ int hvf_vcpu_exec(CPUState *cpu) > } > case EC_WFX_TRAP: > advance_pc = true; > + if (!(syndrome & WFX_IS_WFE) && !(cpu->interrupt_request & > + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ))) { > + > + uint64_t ctl; > + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, > + &ctl); > + assert_hvf_ok(r); > + > + if (!(ctl & 1) || (ctl & 2)) { > + /* Timer disabled or masked, just wait for an IPI. */ > + hvf_wait_for_ipi(cpu, NULL); > + break; > + } > + > + uint64_t cval; > + r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, > + &cval); > + assert_hvf_ok(r); > + > + int64_t ticks_to_sleep = cval - mach_absolute_time(); > + if (ticks_to_sleep < 0) { > + break; > + } > + > + uint64_t seconds = ticks_to_sleep / arm_cpu->gt_cntfrq_hz; > + uint64_t nanos = > + (ticks_to_sleep - arm_cpu->gt_cntfrq_hz * seconds) * > + 1000000000 / arm_cpu->gt_cntfrq_hz; > + > + /* > + * Don't sleep for less than 2ms. This is believed to improve > + * latency of message passing workloads. > + */ Believed by who ? > + if (!seconds && nanos < 2000000) { > + break; > + } > + > + struct timespec ts = { seconds, nanos }; > + hvf_wait_for_ipi(cpu, &ts); > + } Why doesn't the timer timeout manifest as an IPI ? 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Thu, 28 Jan 2021 16:27:49 +0000 From: Darren Kenny To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Peter Maydell , Thomas Huth , Alexander Bulekov , Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH] hw/intc/arm_gic: Allow to use QTest without crashing In-Reply-To: <20210128161417.3726358-1-philmd@redhat.com> References: <20210128161417.3726358-1-philmd@redhat.com> Date: Thu, 28 Jan 2021 16:27:42 +0000 Message-ID: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [79.97.215.145] X-ClientProxiedBy: DB8P191CA0017.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:130::27) To DM6PR10MB2857.namprd10.prod.outlook.com (2603:10b6:5:64::25) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from oracle.com (79.97.215.145) by DB8P191CA0017.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:130::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3805.16 via Frontend Transport; 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envelope-from=darren.kenny@oracle.com; helo=aserp2120.oracle.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:30:09 -0000 On Thursday, 2021-01-28 at 17:14:17 +01, Philippe Mathieu-Daud=C3=A9 wrote: > Alexander reported an issue in gic_get_current_cpu() using the > fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible > doing: > > $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=3Dqtest = -qtest stdio > [I 1611849440.651452] OPENED > [R +0.242498] readb 0xf03ff000 > hw/intc/arm_gic.c:63:29: runtime error: member access within null point= er of type 'CPUState' (aka 'struct CPUState') > SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic= .c:63:29 in > AddressSanitizer:DEADLYSIGNAL > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D3719691=3D=3DERROR: AddressSanitizer: SEGV on unknown address 0x0= 000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) > =3D=3D3719691=3D=3DThe signal is caused by a READ memory access. > #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 > #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 > #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 > #3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu= /memory.c:464:9 > #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552= :18 > #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:= 1426:16 > #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1= 449:9 > #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:= 23 > #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 > #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875= :18 > #10 0x56187aa88633 in address_space_read include/exec/memory.h:2489= :18 > #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13 > #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 > #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 > > current_cpu is NULL because QTest accelerator does not use CPU. > > Fix by skipping the check and returning the first CPU index when > QTest accelerator is used, similarly to commit c781a2cc423 > ("hw/i386/vmport: Allow QTest use without crashing"). > > Reported-by: Alexander Bulekov > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Darren Kenny > --- > hw/intc/arm_gic.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index af41e2fb448..c33b1c8c4bc 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -28,6 +28,7 @@ > #include "qemu/module.h" > #include "trace.h" > #include "sysemu/kvm.h" > +#include "sysemu/qtest.h" > =20 > /* #define DEBUG_GIC */ > =20 > @@ -57,7 +58,7 @@ static const uint8_t gic_id_gicv2[] =3D { > =20 > static inline int gic_get_current_cpu(GICState *s) > { > - if (s->num_cpu > 1) { > + if (!qtest_enabled() && s->num_cpu > 1) { > return current_cpu->cpu_index; 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Thu, 28 Jan 2021 08:40:57 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-11-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-11-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 16:40:45 +0000 Message-ID: Subject: Re: [PATCH v6 10/11] hvf: arm: Add support for GICv3 To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:41:03 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > We currently only support GICv2 emulation. To also support GICv3, we will > need to pass a few system registers into their respective handler functions. > > This patch adds handling for all of the required system registers, so that > we can run with more than 8 vCPUs. > > Signed-off-by: Alexander Graf > Acked-by: Roman Bolshakov So, how much of the GICv3 does Hypervisor.framework expect userspace to implement ? Currently we have two GICv3 implementations: * hw/intc/arm_gicv3_kvm.c -- which is the stub device that handles the KVM in-kernel GICv3 * hw/intc/arm_gicv3.c -- which is the full-emulation device that assumes that it is working with a TCG CPU Support for HVF GICv3 needs either another one of these or some serious refactoring of the full-emulation device so that it doesn't assume that the CPU it's dealing with is a TCG one. (I suspect the right design is to bite the bullet and make the implementation follow the hardware in having "the GIC device proper" and "the GIC CPU interface" separate from each other and communicating via an API approximately equivalent to the GIC Stream Protocol as described in the GICv3 architecture specification; but that's a painful refactor and there might be some other approach less invasive but still reasonably clean.) > static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) > { > ARMCPU *arm_cpu = ARM_CPU(cpu); > @@ -431,6 +491,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) > case SYSREG_PMCCNTR_EL0: > val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > break; > + case SYSREG_ICC_AP0R0_EL1: > + case SYSREG_ICC_AP0R1_EL1: > + case SYSREG_ICC_AP0R2_EL1: > + case SYSREG_ICC_AP0R3_EL1: > + case SYSREG_ICC_AP1R0_EL1: > + case SYSREG_ICC_AP1R1_EL1: > + case SYSREG_ICC_AP1R2_EL1: > + case SYSREG_ICC_AP1R3_EL1: > + case SYSREG_ICC_ASGI1R_EL1: > + case SYSREG_ICC_BPR0_EL1: > + case SYSREG_ICC_BPR1_EL1: > + case SYSREG_ICC_DIR_EL1: > + case SYSREG_ICC_EOIR0_EL1: > + case SYSREG_ICC_EOIR1_EL1: > + case SYSREG_ICC_HPPIR0_EL1: > + case SYSREG_ICC_HPPIR1_EL1: > + case SYSREG_ICC_IAR0_EL1: > + case SYSREG_ICC_IAR1_EL1: > + case SYSREG_ICC_IGRPEN0_EL1: > + case SYSREG_ICC_IGRPEN1_EL1: > + case SYSREG_ICC_PMR_EL1: > + case SYSREG_ICC_SGI0R_EL1: > + case SYSREG_ICC_SGI1R_EL1: > + case SYSREG_ICC_SRE_EL1: > + val = hvf_sysreg_read_cp(cpu, reg); > + break; > + case SYSREG_ICC_CTLR_EL1: > + val = hvf_sysreg_read_cp(cpu, reg); > + > + /* AP0R registers above 0 don't trap, expose less PRIs to fit */ > + val &= ~ICC_CTLR_EL1_PRIBITS_MASK; > + val |= 4 << ICC_CTLR_EL1_PRIBITS_SHIFT; > + break; Pretty sure you don't want to be trying to squeeze even the GICv3 cpuif implementation into this source file... > default: > DPRINTF("unhandled sysreg read %08x (op0=%d op1=%d op2=%d " > "crn=%d crm=%d)", reg, (reg >> 20) & 0x3, > @@ -442,6 +535,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) > return val; > } > > +static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) > +{ > + ARMCPU *arm_cpu = ARM_CPU(cpu); > + CPUARMState *env = &arm_cpu->env; > + const ARMCPRegInfo *ri; > + > + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); > + > + if (ri) { > + if (ri->writefn) { > + ri->writefn(env, ri, val); > + } else { > + CPREG_FIELD64(env, ri) = val; > + } > + DPRINTF("vgic write to %s [val=%016llx]", ri->name, val); > + } > +} > + > static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) > { > ARMCPU *arm_cpu = ARM_CPU(cpu); > @@ -449,6 +560,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) > switch (reg) { > case SYSREG_CNTPCT_EL0: > break; > + case SYSREG_ICC_AP0R0_EL1: > + case SYSREG_ICC_AP0R1_EL1: > + case SYSREG_ICC_AP0R2_EL1: > + case SYSREG_ICC_AP0R3_EL1: > + case SYSREG_ICC_AP1R0_EL1: > + case SYSREG_ICC_AP1R1_EL1: > + case SYSREG_ICC_AP1R2_EL1: > + case SYSREG_ICC_AP1R3_EL1: > + case SYSREG_ICC_ASGI1R_EL1: > + case SYSREG_ICC_BPR0_EL1: > + case SYSREG_ICC_BPR1_EL1: > + case SYSREG_ICC_CTLR_EL1: > + case SYSREG_ICC_DIR_EL1: > + case SYSREG_ICC_HPPIR0_EL1: > + case SYSREG_ICC_HPPIR1_EL1: > + case SYSREG_ICC_IAR0_EL1: > + case SYSREG_ICC_IAR1_EL1: > + case SYSREG_ICC_IGRPEN0_EL1: > + case SYSREG_ICC_IGRPEN1_EL1: > + case SYSREG_ICC_PMR_EL1: > + case SYSREG_ICC_SGI0R_EL1: > + case SYSREG_ICC_SGI1R_EL1: > + case SYSREG_ICC_SRE_EL1: > + hvf_sysreg_write_cp(cpu, reg, val); > + break; > + case SYSREG_ICC_EOIR0_EL1: > + case SYSREG_ICC_EOIR1_EL1: > + hvf_sysreg_write_cp(cpu, reg, val); > + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0); > + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); This definitely looks wrong. Not every interrupt is a timer interrupt, and writing to EOIR in the GIC doesn't squelch the underlying timer irq, that should happen somewhere else. thanks -- PMM From MAILER-DAEMON Thu Jan 28 11:55:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5AZf-0001dW-Fk for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 11:55:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AZb-0001cs-Re; Thu, 28 Jan 2021 11:55:12 -0500 Received: from mail.weilnetz.de ([37.120.169.71]:60564 helo=mail.v2201612906741603.powersrv.de) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AZZ-0007w8-EO; Thu, 28 Jan 2021 11:55:11 -0500 Received: from macbook01.bib.uni-mannheim.de (macbook01.bib.uni-mannheim.de [134.155.36.117]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.v2201612906741603.powersrv.de (Postfix) with ESMTPSA id C397EDA07F0; Thu, 28 Jan 2021 17:55:06 +0100 (CET) Subject: Re: [PATCH v6 00/11] hvf: Implement Apple Silicon Support To: Alexander Graf , qemu-devel@nongnu.org Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm@nongnu.org, Frank Yang , Paolo Bonzini , Peter Collingbourne References: <20210120224444.71840-1-agraf@csgraf.de> From: Stefan Weil Message-ID: Date: Thu, 28 Jan 2021 17:55:07 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.16; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=37.120.169.71; envelope-from=sw@weilnetz.de; helo=mail.v2201612906741603.powersrv.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:55:12 -0000 Am 20.01.21 um 23:44 schrieb Alexander Graf: > Now that Apple Silicon is widely available, people are obviously excited > to try and run virtualized workloads on them, such as Linux and Windows. > > This patch set implements a fully functional version to get the ball > going on that. With this applied, I can successfully run both Linux and > Windows as guests. I am not aware of any limitations specific to > Hypervisor.framework apart from: > > - Live migration / savevm > - gdbstub debugging (SP register) > > > Enjoy! > > Alex Alex, did you already try running `make check-tcg` on a new Mac? I currently struggle with tests/tcg/aarch64/system/boot.S which is not accepted by the Apple clang compiler. It first complains about ".section .rodata". That can be replaced by ".cstring", but then other errors are reported (unknown AArch64 fixup kind, ADR/ADRP relocations must be GOT relative, fixup value out of range). Regards, Stefan From MAILER-DAEMON Thu Jan 28 11:56:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Aaa-0001zK-Or for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 11:56:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AaX-0001wg-TX for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:56:09 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]:34519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5AaS-0008F7-Qo for qemu-arm@nongnu.org; Thu, 28 Jan 2021 11:56:09 -0500 Received: by mail-ed1-x52b.google.com with SMTP id d22so7430849edy.1 for ; Thu, 28 Jan 2021 08:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LZOpokNEvr8TY21lt4Tg0K+O4N2vmlcKhBZUpPguMbw=; b=dBfKOD+XZGg5AvPsyHtTwfUkOEOY5+o4jlpV9MIHgVOZT2JgLCVCmqNUdOf122OEfh dta/uYeZL09KH7tuK75B0kicyZvfMUOX5nQ07w2Ep/qIK7WMJGJAJuVMOfLWBfwKlFMi px0lQzgJYdH1tBJQDvQHGX2VKNnBzrHJYs5LHSqBFXm3gkO2dsBb7kQGzB244o1ajytV B6dnCzGp22whgIvtcCPRzB4/qm3i/CtjMmLy/xI4TguXUnIyUxiZlZUms2XdkSbqWJ00 Cvggeg3EiT+71+2O2DnB6bpPCGhFwpi/RzqxroJbTP8ZGDRsxrm/DdRyZcYbcmsXmCeu MuSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LZOpokNEvr8TY21lt4Tg0K+O4N2vmlcKhBZUpPguMbw=; b=QGT0Z0ZblnuEatkBH4Xzka3JdHeBpH9W2kmCujVbF8bIkBeGY94HZsjBmoQt6QAhfv 4qtFUs5Wphb3QkDSFtVhM2NB2RHHwIy5x6oNNH3QH55Ryn619/kLwVORVO8tCmRmgUzw bEMCGZ1J3Er8CL8ZmdUby3A4yjYealyNwBhePuRpuf0ztqaDVegxmfnQ+W1KxIai3bOm T3cMnR2ImMOlANVQni1/ckgshxupFUkrR+r4MSN8hgjvZ7/Hbxzpc5mDzwrB9HwU5ojZ Y+YfPeM7tXJe+OA9ES720ysZhYM6OwdY/SD7pjtoqkX6tuX3ieDfbmYJRAsmSF9W75K8 sAoQ== X-Gm-Message-State: AOAM532Jlt4tDLy0vguZG/KNJI6Q4vChDlJcD+g7pT6Xgv52vMvESaR+ uWnc0TVY057TNNc3oxzJ1LdchcI5DE+g9Df2zxHBQw== X-Google-Smtp-Source: ABdhPJzu5bepJcq+klI6VrmGzClxsuzNpm7e3Sq/an35VSml7oj85c+pNcEHTCtANAepCpqnuIQu9ushCekQLK6GjeA= X-Received: by 2002:a05:6402:3514:: with SMTP id b20mr519235edd.100.1611852963101; Thu, 28 Jan 2021 08:56:03 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> <20210120224444.71840-12-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-12-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 16:55:51 +0000 Message-ID: Subject: Re: [PATCH v6 11/11] hvf: arm: Implement -cpu host To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 16:56:10 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > Now that we have working system register sync, we push more target CPU > properties into the virtual machine. That might be useful in some > situations, but is not the typical case that users want. > > So let's add a -cpu host option that allows them to explicitly pass all > CPU capabilities of their host CPU into the guest. > > Signed-off-by: Alexander Graf > Acked-by: Roman Bolshakov > --- > include/sysemu/hvf.h | 2 ++ > target/arm/cpu.c | 9 ++++++--- > target/arm/cpu.h | 2 ++ > target/arm/hvf/hvf.c | 41 +++++++++++++++++++++++++++++++++++++++++ > target/arm/kvm_arm.h | 2 -- > 5 files changed, 51 insertions(+), 5 deletions(-) > > diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h > index f893768df9..7eb61cf094 100644 > --- a/include/sysemu/hvf.h > +++ b/include/sysemu/hvf.h > @@ -19,6 +19,8 @@ > #ifdef CONFIG_HVF > uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, > int reg); > +struct ARMCPU; Yuck. > +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); This is arm-specific, it doesn't belong in the generic hvf.h. Put it somewhere else, and somewhere that we can get the typedef from cpu.h, same as with the kvm equivalent. > extern bool hvf_allowed; > #define hvf_enabled() (hvf_allowed) > #else /* !CONFIG_HVF */ > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index f1929b5eba..abd129d23f 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -2288,12 +2288,16 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > #endif > } > > -#ifdef CONFIG_KVM > +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) > static void arm_host_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > > +#ifdef CONFIG_KVM > kvm_arm_set_cpu_features_from_host(cpu); > +#else > + hvf_arm_set_cpu_features_from_host(cpu); > +#endif > if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { > aarch64_add_sve_properties(obj); > } This adds all the SVE related properties, so you probably need to have an equivalent of the kvm_arm_sve_supported() checks in cpu64.c that make those properties return an error on HVF. > @@ -2305,7 +2309,6 @@ static const TypeInfo host_arm_cpu_type_info = { > .parent = TYPE_AARCH64_CPU, > .instance_init = arm_host_initfn, > }; > - > #endif Stray whitespace change. > > static void arm_cpu_instance_init(Object *obj) > @@ -2364,7 +2367,7 @@ static void arm_cpu_register_types(void) > > type_register_static(&arm_cpu_type_info); > > -#ifdef CONFIG_KVM > +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) > type_register_static(&host_arm_cpu_type_info); > #endif > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index df0d677833..5cc59df451 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2961,6 +2961,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); > #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_ARM_CPU > > +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU > + > #define cpu_signal_handler cpu_arm_signal_handler > #define cpu_list arm_cpu_list > > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > index 98bd6712c0..42dcc23ba0 100644 > --- a/target/arm/hvf/hvf.c > +++ b/target/arm/hvf/hvf.c > @@ -372,6 +372,47 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) > return val; > } > > +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) > +{ > + ARMISARegisters host_isar; > + const struct isar_regs { > + int reg; > + uint64_t *val; > + } regs[] = { > + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, > + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, > + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, > + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, > + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, > + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, > + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, > + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, > + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, > + }; Since there's no AArch32 support in this register list, we should check and error-out if the ID_AA64PFR0_EL1 value we read has 2 in either the .EL0 or .EL1 fields. (This is a never-happen case on current hardware AIUI, but we might as well be explicit about it.) > + hv_vcpu_t fd; > + hv_vcpu_exit_t *exit; > + int i; > + > + cpu->dtb_compatible = "arm,arm-v8"; > + cpu->env.features = (1ULL << ARM_FEATURE_V8) | > + (1ULL << ARM_FEATURE_NEON) | > + (1ULL << ARM_FEATURE_AARCH64) | > + (1ULL << ARM_FEATURE_PMU) | > + (1ULL << ARM_FEATURE_GENERIC_TIMER); > + > + /* We set up a small vcpu to extract host registers */ > + > + assert_hvf_ok(hv_vcpu_create(&fd, &exit, NULL)); > + for (i = 0; i < ARRAY_SIZE(regs); i++) { > + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val)); > + } > + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &cpu->midr)); > + assert_hvf_ok(hv_vcpu_destroy(fd)); Nicer to follow the KVM approach of only doing this once and caching the results in arm_host_cpu_features, so that for a many-cores VM you don't do it once per core. > + > + cpu->isar = host_isar; > + cpu->reset_sctlr = 0x00c50078; > +} > + > void hvf_arch_vcpu_destroy(CPUState *cpu) > { > } > diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h > index eb81b7059e..081727a37e 100644 > --- a/target/arm/kvm_arm.h > +++ b/target/arm/kvm_arm.h > @@ -214,8 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, > */ > void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); > > -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU > - > /** > * ARMHostCPUFeatures: information about the host CPU (identified > * by asking the host kernel) > -- > 2.24.3 (Apple Git-128) thanks -- PMM From MAILER-DAEMON Thu Jan 28 12:00:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5AeM-0005D3-JP for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:00:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AeK-0005BB-Kb for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:00:04 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:36139) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5AeG-0001PZ-TP for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:00:04 -0500 Received: by mail-ed1-x532.google.com with SMTP id d2so7457558edz.3 for ; Thu, 28 Jan 2021 09:00:00 -0800 (PST) DKIM-Signature: v=1; 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Thu, 28 Jan 2021 08:59:59 -0800 (PST) MIME-Version: 1.0 References: <20210120224444.71840-1-agraf@csgraf.de> In-Reply-To: <20210120224444.71840-1-agraf@csgraf.de> From: Peter Maydell Date: Thu, 28 Jan 2021 16:59:47 +0000 Message-ID: Subject: Re: [PATCH v6 00/11] hvf: Implement Apple Silicon Support To: Alexander Graf Cc: QEMU Developers , qemu-arm , Cameron Esfahani , Roman Bolshakov , Eduardo Habkost , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Frank Yang , Peter Collingbourne Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:00:05 -0000 On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > Now that Apple Silicon is widely available, people are obviously excited > to try and run virtualized workloads on them, such as Linux and Windows. > > This patch set implements a fully functional version to get the ball > going on that. With this applied, I can successfully run both Linux and > Windows as guests. I am not aware of any limitations specific to > Hypervisor.framework apart from: > > - Live migration / savevm > - gdbstub debugging (SP register) > I've gone through making code review comments. Since patch 1 is also required for Big Sur support on x86 Macs, I'll take that via target-arm.next now (unless anybody would rather it went in via a different route). thanks -- PMM From MAILER-DAEMON Thu Jan 28 12:12:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5AqK-0007JA-Oq for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:12:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AqH-0007Gy-Bx; Thu, 28 Jan 2021 12:12:26 -0500 Received: from mta-02.yadro.com ([89.207.88.252]:38076 helo=mta-01.yadro.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5AqC-0005VX-13; Thu, 28 Jan 2021 12:12:25 -0500 Received: from localhost (unknown [127.0.0.1]) by mta-01.yadro.com (Postfix) with ESMTP id 5F84641279; Thu, 28 Jan 2021 17:12:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=yadro.com; h= in-reply-to:content-disposition:content-type:content-type :mime-version:references:message-id:subject:subject:from:from :date:date:received:received:received; s=mta-01; t=1611853935; x=1613668336; bh=vqstYAQyEx9Op7OzbbJqBv83k1ndlIG2eEZM76UKHL8=; b= SADyM2cPiRJwf9HkD2hjcX1bDBjw0AOBkuMNUTLa7Emg+BEUGhy8DnKebKVbmnLk AVk20ln3DEb17EB/UpBk6Kx6M3k2ARIXQue6VPWgCEeiAFFn8bVeMgKg6IhB+8WF uqrGr4kXwC/plAr79do8UVPJSazIK9rFtKUxw/GdWIc= X-Virus-Scanned: amavisd-new at yadro.com Received: from mta-01.yadro.com ([127.0.0.1]) by localhost (mta-01.yadro.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CUx1SYK8zSeC; Thu, 28 Jan 2021 20:12:15 +0300 (MSK) Received: from T-EXCH-03.corp.yadro.com (t-exch-03.corp.yadro.com [172.17.100.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mta-01.yadro.com (Postfix) with ESMTPS id 2159C4126E; Thu, 28 Jan 2021 20:12:15 +0300 (MSK) Received: from localhost (172.17.204.212) by T-EXCH-03.corp.yadro.com (172.17.100.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.32; Thu, 28 Jan 2021 20:12:15 +0300 Date: Thu, 28 Jan 2021 20:12:14 +0300 From: Roman Bolshakov To: Peter Maydell , Paolo Bonzini CC: Alexander Graf , QEMU Developers , qemu-arm , Cameron Esfahani , Eduardo Habkost , Marcel Apfelbaum , Richard Henderson , Frank Yang , Peter Collingbourne Subject: Re: [PATCH v6 00/11] hvf: Implement Apple Silicon Support Message-ID: References: <20210120224444.71840-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-Originating-IP: [172.17.204.212] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-03.corp.yadro.com (172.17.100.103) Received-SPF: pass client-ip=89.207.88.252; envelope-from=r.bolshakov@yadro.com; helo=mta-01.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:12:26 -0000 On Thu, Jan 28, 2021 at 04:59:47PM +0000, Peter Maydell wrote: > On Wed, 20 Jan 2021 at 22:44, Alexander Graf wrote: > > > > Now that Apple Silicon is widely available, people are obviously excited > > to try and run virtualized workloads on them, such as Linux and Windows. > > > > This patch set implements a fully functional version to get the ball > > going on that. With this applied, I can successfully run both Linux and > > Windows as guests. I am not aware of any limitations specific to > > Hypervisor.framework apart from: > > > > - Live migration / savevm > > - gdbstub debugging (SP register) > > > > I've gone through making code review comments. > > Since patch 1 is also required for Big Sur support on x86 Macs, > I'll take that via target-arm.next now (unless anybody would rather > it went in via a different route). > Hi Peter, I wonder if patch 1 and patch 2 should go via Paolo's i386 or misc tree? (IMO whatever the fastest way to master works). Both are reviewed and nobody raised objections to them. Thanks, Roman From MAILER-DAEMON Thu Jan 28 12:19:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Awy-00046O-0w for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:19:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Aws-00041Z-9H; Thu, 28 Jan 2021 12:19:15 -0500 Received: from relay68.bu.edu ([128.197.228.73]:52652) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Awq-00084y-7K; Thu, 28 Jan 2021 12:19:13 -0500 X-Envelope-From: alxndr@bu.edu X-BU-AUTH: mozz.bu.edu [128.197.127.33] Received: from BU-AUTH (localhost.localdomain [127.0.0.1]) (authenticated bits=0) by relay68.bu.edu (8.14.3/8.14.3) with ESMTP id 10SHIBY0030640 (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256 verify=NO); Thu, 28 Jan 2021 12:18:14 -0500 Date: Thu, 28 Jan 2021 12:18:11 -0500 From: Alexander Bulekov To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , Darren Kenny , Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini Subject: Re: [PATCH] hw/intc/arm_gic: Allow to use QTest without crashing Message-ID: <20210128171811.jlnevikw4wgywjks@mozz.bu.edu> References: <20210128161417.3726358-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210128161417.3726358-1-philmd@redhat.com> Received-SPF: pass client-ip=128.197.228.73; envelope-from=alxndr@bu.edu; helo=relay68.bu.edu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:19:15 -0000 On 210128 1714, Philippe Mathieu-Daudé wrote: > Alexander reported an issue in gic_get_current_cpu() using the > fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible > doing: > > $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio > [I 1611849440.651452] OPENED > [R +0.242498] readb 0xf03ff000 > hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState') > SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in > AddressSanitizer:DEADLYSIGNAL > ================================================================= > ==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) > ==3719691==The signal is caused by a READ memory access. > #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 > #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 > #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 > #3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9 > #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18 > #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16 > #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9 > #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23 > #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 > #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18 > #10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18 > #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13 > #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 > #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 > > current_cpu is NULL because QTest accelerator does not use CPU. > > Fix by skipping the check and returning the first CPU index when > QTest accelerator is used, similarly to commit c781a2cc423 > ("hw/i386/vmport: Allow QTest use without crashing"). > > Reported-by: Alexander Bulekov Reviewed-by: Alexander Bulekov For reference, some older threads about similar issues in the GDB stub and monitor: https://bugs.launchpad.net/qemu/+bug/1602247 https://patchew.org/QEMU/20200701182100.26930-1-philmd@redhat.com/ https://bugs.launchpad.net/qemu/+bug/1878645 > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/intc/arm_gic.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index af41e2fb448..c33b1c8c4bc 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -28,6 +28,7 @@ > #include "qemu/module.h" > #include "trace.h" > #include "sysemu/kvm.h" > +#include "sysemu/qtest.h" > > /* #define DEBUG_GIC */ > > @@ -57,7 +58,7 @@ static const uint8_t gic_id_gicv2[] = { > > static inline int gic_get_current_cpu(GICState *s) > { > - if (s->num_cpu > 1) { > + if (!qtest_enabled() && s->num_cpu > 1) { > return current_cpu->cpu_index; > } > return 0; > -- > 2.26.2 > > From MAILER-DAEMON Thu Jan 28 12:29:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5B6L-00059v-Cp for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:29:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5B6J-00055p-Ut for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:28:59 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]:36446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5B6H-0003A8-Dy for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:28:59 -0500 Received: by mail-ed1-x531.google.com with SMTP id d2so7570978edz.3 for ; Thu, 28 Jan 2021 09:28:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=GR92uWHbhhdDZc0WH5I5nCMOgJmbOUxJ102ykzoRMaM=; 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Thu, 28 Jan 2021 09:28:55 -0800 (PST) MIME-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-3-wuhaotsh@google.com> In-Reply-To: <20210126193237.1534208-3-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 28 Jan 2021 17:28:44 +0000 Message-ID: Subject: Re: [PATCH 2/6] hw/i2c: Implement NPCM7XX SMBus Module Single Mode To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Havard Skinnemoen , Patrick Venture , Doug Evans Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:29:00 -0000 On Tue, 26 Jan 2021 at 19:32, Hao Wu wrote: > > This commit implements the single-byte mode of the SMBus. > > Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses > compliant with SMBus and I2C protocol. > > This patch implements the single-byte mode of the SMBus. In this mode, > the user sends or receives a byte each time. The SMBus device transmits > it to the underlying i2c device and sends an interrupt back to the QEMU > guest. > > Reviewed-by: Doug Evans > Reviewed-by: Tyrong Ting > Signed-off-by: Hao Wu > --- > docs/system/arm/nuvoton.rst | 2 +- > hw/arm/npcm7xx.c | 68 ++- > hw/i2c/meson.build | 1 + > hw/i2c/npcm7xx_smbus.c | 766 +++++++++++++++++++++++++++++++++ > hw/i2c/trace-events | 11 + > include/hw/arm/npcm7xx.h | 2 + > include/hw/i2c/npcm7xx_smbus.h | 88 ++++ > 7 files changed, 921 insertions(+), 17 deletions(-) > create mode 100644 hw/i2c/npcm7xx_smbus.c > create mode 100644 include/hw/i2c/npcm7xx_smbus.h > > diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst > index a1786342e2..34fc799b2d 100644 > --- a/docs/system/arm/nuvoton.rst > +++ b/docs/system/arm/nuvoton.rst > @@ -43,6 +43,7 @@ Supported devices > * GPIO controller > * Analog to Digital Converter (ADC) > * Pulse Width Modulation (PWM) > + * SMBus controller (SMBF) > > Missing devices > --------------- > @@ -58,7 +59,6 @@ Missing devices > > * Ethernet controllers (GMAC and EMC) > * USB device (USBD) > - * SMBus controller (SMBF) > * Peripheral SPI controller (PSPI) > * SD/MMC host > * PECI interface > diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c > index d1fe9bd1df..8f596ffd69 100644 > --- a/hw/arm/npcm7xx.c > +++ b/hw/arm/npcm7xx.c > @@ -104,6 +104,22 @@ enum NPCM7xxInterrupt { > NPCM7XX_OHCI_IRQ = 62, > NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ > NPCM7XX_PWM1_IRQ, /* PWM module 1 */ > + NPCM7XX_SMBUS0_IRQ = 64, > + NPCM7XX_SMBUS1_IRQ, > + NPCM7XX_SMBUS2_IRQ, > + NPCM7XX_SMBUS3_IRQ, > + NPCM7XX_SMBUS4_IRQ, > + NPCM7XX_SMBUS5_IRQ, > + NPCM7XX_SMBUS6_IRQ, > + NPCM7XX_SMBUS7_IRQ, > + NPCM7XX_SMBUS8_IRQ, > + NPCM7XX_SMBUS9_IRQ, > + NPCM7XX_SMBUS10_IRQ, > + NPCM7XX_SMBUS11_IRQ, > + NPCM7XX_SMBUS12_IRQ, > + NPCM7XX_SMBUS13_IRQ, > + NPCM7XX_SMBUS14_IRQ, > + NPCM7XX_SMBUS15_IRQ, Would be nicer to put these in their correct place in numerical order, ie above the PWM IRQs rather than below them. (The list is otherwise already in numerical order.) > NPCM7XX_GPIO0_IRQ = 116, > NPCM7XX_GPIO1_IRQ, > NPCM7XX_GPIO2_IRQ, > @@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] = { > 0xf0104000, > +static const VMStateDescription vmstate_npcm7xx_smbus = { > + .name = "npcm7xx-smbus", > + .version_id = 0, > + .minimum_version_id = 0, > + .fields = (VMStateField[]) { > + VMSTATE_END_OF_LIST(), > + }, Looks like you forgot to fill in the fields in the vmstate :-) > +}; > + thanks -- PMM From MAILER-DAEMON Thu Jan 28 12:32:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5BA9-0008J9-Ts for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:32:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5BA7-0008Ia-VL for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:32:56 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:36193) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5B9z-0004sg-3N for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:32:55 -0500 Received: by mail-ej1-x629.google.com with SMTP id l9so9016945ejx.3 for ; Thu, 28 Jan 2021 09:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KqTBMNBBEJ1sOhIslJwSqd9Q2bYRZH5ZzE5JPKV85NI=; b=Dx39f+XjCmmk79lsbVMqT4bJidCbg6iX/8HgTLxrgZy6SGaMuAH0s299HA7kGyKKFO Vad/vENRA2x1R45bM3OOspd62NXlLt3I2Wau3nVBQM/0RR5T8JWWHD584tEZ6vHtiTBd w+76Wn1AWP7nX0zome3BxZSUUA7H6avUkalQaWnUX1pKGLaR7TXT1D9JxM5bqwvmyKs5 ibi5lsKIjwXdzRYkjQXEfwxtjH/vGWU+vY4hu2AERbrQzetFSOCRHQCNNh6gVHfFlugA Nlnf4g+NEUOptlLpCIYcoIYgN4cS0BY8HhFXSdJ9qG2oD9sgfNqKWYrxpXLsQuxjK8Iv b/7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KqTBMNBBEJ1sOhIslJwSqd9Q2bYRZH5ZzE5JPKV85NI=; b=a5mmx1yUOoeA7KeTE882xj9OkHDJ4PEGJl5xGsKnbfWVftnurmZXhOCXj8Sg+WJxsL SoSvCedntTe/9hwxvit/6naipZcy985Hrbaj5MLS+naFuadauh0pp1/6EVv5UsqWqMo7 1C+a6Vmz3eQaw3VsI+EQUHcXpETNdZGLpRCsOoi6OZxB5FtLDTU2Jr44vTosxLeEUq01 XFGSRDSG9q+OXvyzRdKpXT9uqVgfC34HnyROuHPg7FR9KT3b93qxh1B7sO3IpZcctwcC uTMj6JrngYm26mLJu/cECHPLnWhTBxUAoUFO/i86hNkjj50L9jmMmHIfYzZHzVDl115t XwTQ== X-Gm-Message-State: AOAM531FgWX20eyl8crJBwgEbLv65u5ZaBb7PbDxPJToMqAsNapA+57a gKy/ffbmPOEGv/BA15i5125hkRVIsHRDobupzwVLXA== X-Google-Smtp-Source: ABdhPJzdNotn3nWcAO9ijxsBL/0dE+zhxY3PT6heTGmrGqX4TiFoGFTu6MLOf9djFpZ9aSAVdDM/0ayANqrbsymTvPk= X-Received: by 2002:a17:906:494c:: with SMTP id f12mr522098ejt.56.1611855163813; Thu, 28 Jan 2021 09:32:43 -0800 (PST) MIME-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-4-wuhaotsh@google.com> In-Reply-To: <20210126193237.1534208-4-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 28 Jan 2021 17:32:32 +0000 Message-ID: Subject: Re: [PATCH 3/6] hw/arm: Add I2C device tree for NPCM750 eval board To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Havard Skinnemoen , Patrick Venture , Doug Evans Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:32:56 -0000 On Tue, 26 Jan 2021 at 19:32, Hao Wu wrote: > > Add an I2C device tree for NPCM750 evaluation board. > > Reviewed-by: Doug Evans > Reviewed-by: Tyrong Ting > Signed-off-by: Hao Wu Slightly confusing commit message, because "device tree" usually means the data structure describing hardware for Linux (https://www.kernel.org/doc/html/latest/devicetree/usage-model.html). Something like "Create the I2C tmp105 temperature sensor devices" would be clearer, I think. > --- > hw/arm/npcm7xx_boards.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c > index 3fdd5cab01..2d82f48848 100644 > --- a/hw/arm/npcm7xx_boards.c > +++ b/hw/arm/npcm7xx_boards.c > @@ -98,6 +98,20 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, > return NPCM7XX(obj); > } > > +static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) > +{ > + g_assert(num < ARRAY_SIZE(soc->smbus)); > + return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); > +} > + > +static void npcm750_evb_i2c_init(NPCM7xxState *soc) > +{ > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); > + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); I assume these correspond to temperature sensors on the real board. Might be worth having a comment saying what their function is (I'm guessing they're measuring temperature of different bits of the board somehow?) > +} > + > static void npcm750_evb_init(MachineState *machine) > { > NPCM7xxState *soc; > @@ -108,6 +122,7 @@ static void npcm750_evb_init(MachineState *machine) > > npcm7xx_load_bootrom(machine, soc); > npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); > + npcm750_evb_i2c_init(soc); > npcm7xx_load_kernel(machine, soc); > } > > -- > 2.30.0.365.g02bc693789-goog thanks -- PMM From MAILER-DAEMON Thu Jan 28 12:33:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5BAn-0000d3-VX for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:33:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5BAm-0000ZH-7k for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:33:36 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:43808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5BAk-00059D-OH for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:33:35 -0500 Received: by mail-ej1-x62c.google.com with SMTP id a10so8967619ejg.10 for ; Thu, 28 Jan 2021 09:33:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=peCI9eHyva00w0o1LMwcOBAo1uSTfHW3Ms1naaOzJLY=; b=AMYszEzN04+I/ZpilnWiA0FYENYDEoOOsCwb0UVyEr3LvgW9U2cHyYKdsPv0X9f50N UASkhsBlTmx4Tkgtviyif9eSSgYK8phppoiSuXsV7C75D/Xn4Uss1DdTKg+0mnGcCUMz HqPp9hwySZfHW/eEUjtdgjVjyyG4IxGAf20jCE0pldMzQItOQIUGfD/cWDBcgaOgrZXC Op8Of18z6QhCAaXHp4uxOGC8JTTyzsgJWD2GbXzrnOs6F7A0qpWEJJtCdxod9DTWLOzh CksK92RqesoE9NzJngjfq8vAScoDKhGWNgbSas1+22vIP1e0mUY/p0yk5I8qJyJ25zav KWnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=peCI9eHyva00w0o1LMwcOBAo1uSTfHW3Ms1naaOzJLY=; b=fVi2bHB2vs75Dh7jqg0GvAsXl597WI/B3sZKbEwgDZmnFZWXFicIMIMA7zUWym4HnW S8PfhDX//lPrnuPX8B2oZgQEar7bYt7il+dSEYnUmZoQhHodzxc/ukHYoYP2+SDZy09p 8VrNEaYCKrHKFtYsVCWL0j1p8ztg2ifTYbMB+p1I9ZpA9qACNoSv8MxFdGGdTPiXaZbi cRrMvm3e7EWvFTrNyuL5YdYroSrtyN2u7TvbHekcpJLH21grxSipiU4ue7EzkFJ5mCfP vWDS7ocPvKQOJRQdkMxeqUp1SrzMJkFDNC9MGRO5bLDGZlcB3n6qcNwHAHe0bWnYkuf+ z+gw== X-Gm-Message-State: AOAM531P/f2eDKzULmhOj3ZzKRunRFwdOwx9Wfzwfjh17m2xOJR2gho5 KGokCJPrpvGrmfGCA/6fo9N2LlPsqof8KboiMhODrg== X-Google-Smtp-Source: ABdhPJyHF/rlsYqyDwdIxuD6PJPSupccYZg9r6evuUrI8X/QZPauu1LWDUMuBbVKWOjT5zptCo1XvyV4sdUBMQJjG4w= X-Received: by 2002:a17:906:4002:: with SMTP id v2mr473813ejj.85.1611855213351; Thu, 28 Jan 2021 09:33:33 -0800 (PST) MIME-Version: 1.0 References: <20210126193237.1534208-1-wuhaotsh@google.com> <20210126193237.1534208-5-wuhaotsh@google.com> In-Reply-To: <20210126193237.1534208-5-wuhaotsh@google.com> From: Peter Maydell Date: Thu, 28 Jan 2021 17:33:22 +0000 Message-ID: Subject: Re: [PATCH 4/6] hw/arm: Add I2C device tree for Quanta GSJ To: Hao Wu Cc: qemu-arm , QEMU Developers , IS20 Avi Fishman , CS20 KFTing , Havard Skinnemoen , Patrick Venture , Doug Evans Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:33:36 -0000 On Tue, 26 Jan 2021 at 19:32, Hao Wu wrote: > > Add an I2C device tree for Quanta GSJ. We only included devices with > existing QEMU implementation, including AT24 EEPROM and temperature > sensors. > > Reviewed-by: Doug Evans > Reviewed-by: Tyrong Ting > Signed-off-by: Hao Wu Same remarks as for patch 3 apply here too. thanks -- PMM From MAILER-DAEMON Thu Jan 28 12:47:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5BNq-0003Tz-F5 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 12:47:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5BNk-0003QF-Kb for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:47:02 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:47414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5BNe-0001EJ-VX for qemu-arm@nongnu.org; Thu, 28 Jan 2021 12:47:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611856013; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=isSAFS+v7sExV3N+0nlUCmMIaibmFR/wXYLd+oxw3CQ=; b=AEtM8F5RAMiPgcPsn+ugfV9HoIjj5rUHufeGO16J6pqdjzV8C/OATQK9Ln0W/8Oj/rsrav 0a0Lg0Tr+mJnVYWNU5MiDjh37dzuZmce5tDwFKv1XKBq/6Nh5XvLz/UaU4m77dGA1XqKMM gbU9R56wXF4N4d7vInaFws1kPG/AXDQ= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-43-s8APbRhaOw-ZjbepKyi3Aw-1; Thu, 28 Jan 2021 12:46:37 -0500 X-MC-Unique: s8APbRhaOw-ZjbepKyi3Aw-1 Received: by mail-wr1-f72.google.com with SMTP id j8so3479708wrx.17 for ; Thu, 28 Jan 2021 09:46:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=isSAFS+v7sExV3N+0nlUCmMIaibmFR/wXYLd+oxw3CQ=; b=iR6PqY6ru1fMWoQBU5cxgmB+J34kEtnmlExmBiIjjZHO4MqbqOmqocy9OpL0JoDCe1 2xMBvasnT/VSXJQH5vu5/E0RFATyILhUrIVOp0X7/0FvuswNQPeMWs93X1lshpwbkkrW p1uDiFZ0ETcAnaGMd4mMrP9zHSkMhnGN+Td7xfs4uS4WPRz7+QojzXxMk1n64nBsiLo1 YA5H1ufURXfdaRa1S2yBnDQSaKJnGG4324wCKGRb++f1YKTCCo9c3SUqICYB3WMWxPVv t2J0M9MVUPsYwSsN2JV65mmsrEkNwFePh/HRRjF2BTZMOerinNM/lzGOZlwwImdwXfdq K7PQ== X-Gm-Message-State: AOAM532HSz4u13u89Gv2or6QsU0fYzEazzsVdZcA5UTsKS/YR5sfjlNM kwGNwheAHrgXQE8zi8HpF2HeUtFIgOwqdzDLYrL1mNNWkDsXUWhtG4IJG97xbK97M73XobD349n 45/+TwDUU9aa7 X-Received: by 2002:a5d:4e4c:: with SMTP id r12mr239852wrt.354.1611855996465; Thu, 28 Jan 2021 09:46:36 -0800 (PST) X-Google-Smtp-Source: ABdhPJzcSjQdgGuIt2rsmY0cSd0HQ9GheYfgGwTznWn+dXd0giHG9QKATSygsV9gGH6WmdW+Wi+QAQ== X-Received: by 2002:a5d:4e4c:: with SMTP id r12mr239826wrt.354.1611855996278; Thu, 28 Jan 2021 09:46:36 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id b11sm7838650wrp.60.2021.01.28.09.46.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 09:46:35 -0800 (PST) Subject: Re: [PATCH] hw/intc/arm_gic: Allow to use QTest without crashing To: Alexander Bulekov , Luc Michel , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , Darren Kenny , Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini References: <20210128161417.3726358-1-philmd@redhat.com> <20210128171811.jlnevikw4wgywjks@mozz.bu.edu> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <82de6c97-d13b-01b9-e9ad-3b20f00adc5e@redhat.com> Date: Thu, 28 Jan 2021 18:46:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210128171811.jlnevikw4wgywjks@mozz.bu.edu> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 17:47:03 -0000 On 1/28/21 6:18 PM, Alexander Bulekov wrote: > On 210128 1714, Philippe Mathieu-Daudé wrote: >> Alexander reported an issue in gic_get_current_cpu() using the >> fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible >> doing: >> >> $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio >> [I 1611849440.651452] OPENED >> [R +0.242498] readb 0xf03ff000 >> hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState') >> SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in >> AddressSanitizer:DEADLYSIGNAL >> ================================================================= >> ==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) >> ==3719691==The signal is caused by a READ memory access. >> #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 >> #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 >> #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 >> #3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9 >> #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18 >> #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16 >> #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9 >> #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23 >> #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 >> #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18 >> #10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18 >> #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13 >> #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 >> #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 >> >> current_cpu is NULL because QTest accelerator does not use CPU. >> >> Fix by skipping the check and returning the first CPU index when >> QTest accelerator is used, similarly to commit c781a2cc423 >> ("hw/i386/vmport: Allow QTest use without crashing"). >> >> Reported-by: Alexander Bulekov > > Reviewed-by: Alexander Bulekov > > For reference, some older threads about similar issues in the GDB stub > and monitor: > https://bugs.launchpad.net/qemu/+bug/1602247 This one is different. I thought this issue was fixed by the series around commit 7cf48f6752e ("gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo"). When using physical addresses with gdbstub, we should be able to select a particular address space. Maybe this fixes pmemsave accessing MMIO here: https://bugs.launchpad.net/qemu/+bug/1751674 > https://bugs.launchpad.net/qemu/+bug/1878645 > https://patchew.org/QEMU/20200701182100.26930-1-philmd@redhat.com/ I'm still procrastinating this thread :> > >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/intc/arm_gic.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >> index af41e2fb448..c33b1c8c4bc 100644 >> --- a/hw/intc/arm_gic.c >> +++ b/hw/intc/arm_gic.c >> @@ -28,6 +28,7 @@ >> #include "qemu/module.h" >> #include "trace.h" >> #include "sysemu/kvm.h" >> +#include "sysemu/qtest.h" >> >> /* #define DEBUG_GIC */ >> >> @@ -57,7 +58,7 @@ static const uint8_t gic_id_gicv2[] = { >> >> static inline int gic_get_current_cpu(GICState *s) >> { >> - if (s->num_cpu > 1) { >> + if (!qtest_enabled() && s->num_cpu > 1) { >> return current_cpu->cpu_index; >> } >> return 0; >> -- >> 2.26.2 >> >> > From MAILER-DAEMON Thu Jan 28 13:06:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5BgB-0001zF-HX for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 13:06:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Bg7-0001w5-P5 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 13:05:59 -0500 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]:41526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Bg5-0008Tf-Hx for qemu-arm@nongnu.org; Thu, 28 Jan 2021 13:05:59 -0500 Received: by mail-ed1-x52e.google.com with SMTP id bx12so7668438edb.8 for ; Thu, 28 Jan 2021 10:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Re1RwwGUNB5sg+yEG415P4GxdiDQT4tR/tMFlPyz+vE=; b=Y1mvluxVx6smKiNIA8DguWYEPvuHNmTuQ/61ZyeJH2wuucsfccF+9JI4aKKzzXQLki Im+/JgUYGrgapTljYUmpC1zXbDFW6tRfXFbzTZyHgB70AD1/CrEmCHiaQTPZBVa8pod9 b96oc1YtU9YCcZeoTioSTKQ2VSPweuU9frytlZa70FcYEhXw/yxu9gQoHSwDXqs3vU8p /W+gOePp5YTx0d0EP6655RRNCOB2tvjUuOt7e/qp3qc5xX7DtQ9J+IuNEgC5kNTD8kT0 RlYWZv6abf/H91G+9RzT7QhqWfJfLgb4thahG6/pCj3dT0/Q2Ox6bG1SVxq20byMwaSz vmkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Re1RwwGUNB5sg+yEG415P4GxdiDQT4tR/tMFlPyz+vE=; b=X2fn0okA4iVc4YTEsPp1txVFk5f+fds4WH+5QoYEs1oQgQefmxMvDiJbSsk7ry6i/p MvcigjHWqUpo4+7AtWAYETk0tOKkolxO3S603o7Eu+0AcWr35d2TxrKXP0X469zJ7due Dr3zerRoHvLSlxR6/YkHftd3R1cNU6TdiJF2JyS1JP/+XOsaKFYKkfn0J+A7M5yKcVE0 O4jlB6sd+pfo/9MoD9RD5heYknA8zXJoRYjbrW9gjQnMRBAiBm8+fBrhUA285DqPgRWf 71T8ydq3mis667jL9YeqtToRvvsqK9kNJXP+qvqeYyfZAl3i3zWhVVl37TrMKaelCHFK uZ+Q== X-Gm-Message-State: AOAM530qJRd40WdAaRqqXhdGSgtMBGAcz369ze/G7lp7zD2oy5cTcEK5 NP/6xxxW1j2Nreh2FecsynpPp8PFfmhSyQKDNXOX4Q== X-Google-Smtp-Source: ABdhPJxgf0UpLoEfNPFcp6Uw5+EkWJ03Q6G3dfgQjyiuSmjORfaABwmFZCWKsKXWBI7vMyNzQ0RmzmCJCCGV5v9FSGw= X-Received: by 2002:a05:6402:5107:: with SMTP id m7mr908986edd.52.1611857152771; Thu, 28 Jan 2021 10:05:52 -0800 (PST) MIME-Version: 1.0 References: <20210128161417.3726358-1-philmd@redhat.com> <20210128171811.jlnevikw4wgywjks@mozz.bu.edu> <82de6c97-d13b-01b9-e9ad-3b20f00adc5e@redhat.com> In-Reply-To: <82de6c97-d13b-01b9-e9ad-3b20f00adc5e@redhat.com> From: Peter Maydell Date: Thu, 28 Jan 2021 18:05:41 +0000 Message-ID: Subject: Re: [PATCH] hw/intc/arm_gic: Allow to use QTest without crashing To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Alexander Bulekov , Luc Michel , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Thomas Huth , Darren Kenny , Eric Auger , qemu-arm , Paolo Bonzini Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 18:06:00 -0000 On Thu, 28 Jan 2021 at 17:46, Philippe Mathieu-Daud=C3=A9 wrote: > > On 1/28/21 6:18 PM, Alexander Bulekov wrote: > > On 210128 1714, Philippe Mathieu-Daud=C3=A9 wrote: > >> Alexander reported an issue in gic_get_current_cpu() using the > >> fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible > >> doing: > >> > >> $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=3Dqte= st -qtest stdio > >> [I 1611849440.651452] OPENED > >> [R +0.242498] readb 0xf03ff000 > >> hw/intc/arm_gic.c:63:29: runtime error: member access within null po= inter of type 'CPUState' (aka 'struct CPUState') > >> SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_= gic.c:63:29 in > >> AddressSanitizer:DEADLYSIGNAL > >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > >> =3D=3D3719691=3D=3DERROR: AddressSanitizer: SEGV on unknown address = 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) > >> =3D=3D3719691=3D=3DThe signal is caused by a READ memory access. > >> #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 > >> #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 > >> #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 > >> #3 0x56187adc573b in memory_region_read_with_attrs_accessor soft= mmu/memory.c:464:9 > >> #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:= 552:18 > >> #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory= .c:1426:16 > >> #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.= c:1449:9 > >> #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:28= 22:23 > >> #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 > >> #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2= 875:18 > >> #10 0x56187aa88633 in address_space_read include/exec/memory.h:2= 489:18 > >> #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:= 13 > >> #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 > >> #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 > >> > >> current_cpu is NULL because QTest accelerator does not use CPU. > >> > >> Fix by skipping the check and returning the first CPU index when > >> QTest accelerator is used, similarly to commit c781a2cc423 > >> ("hw/i386/vmport: Allow QTest use without crashing"). > >> > >> Reported-by: Alexander Bulekov > > > > Reviewed-by: Alexander Bulekov > > > > For reference, some older threads about similar issues in the GDB stub > > and monitor: > > https://bugs.launchpad.net/qemu/+bug/1602247 > > This one is different. I thought this issue was fixed by > the series around commit 7cf48f6752e ("gdbstub: add multiprocess > support to (f|s)ThreadInfo and ThreadExtraInfo"). > > When using physical addresses with gdbstub, we should be able to > select a particular address space. Yes, but the problem with the GIC device is that it does not use AddressSpaces to identify which CPU is accessing it. We would either need to make it do that, or else add support for using the MemTxAttrs requester_id to identify which CPU is making a memory access and get the GIC to use that instead. (This is more or less how the h/w does it.) > Maybe this fixes pmemsave accessing MMIO here: > https://bugs.launchpad.net/qemu/+bug/1751674 Nope, because the monitor pmemsave command goes via cpu_physical_memory_rw(), which does an access to address_space_memory. So unlike the gdbstub it's not even trying to say which CPU it cares about. (The monitor does have a "current CPU" concept, via mon_get_cpu(). But it's not used in the pmemsave codepath.) gdbstub direct-physical-memory-access is also via cpu_physical_memory_rw(), incidentally. thanks -- PMM From MAILER-DAEMON Thu Jan 28 13:53:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5CPp-0000G6-P3 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 13:53:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5CPo-0000FU-Ii for qemu-arm@nongnu.org; Thu, 28 Jan 2021 13:53:12 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:46560) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5CPm-0000PJ-CX for qemu-arm@nongnu.org; Thu, 28 Jan 2021 13:53:12 -0500 Received: by mail-wr1-x42c.google.com with SMTP id q7so6443764wre.13 for ; Thu, 28 Jan 2021 10:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Xtj/YspweNDXNSalS9uwvsWmvlz2awO1cN3TGJ6zgII=; b=C1qfoXcqK+zisS1rqAJiqCI6nBw9ZFxubXhLHX/0TU0e8ki77GADE4u8tfar9HjzrU 4e676oxmC4Na1HvehEKg22TjgnG12ftDpoxQZ7XUAjAxHF+POPRd7Dm1s34JYVziHjXq GHWBVaN7PHsrwDAzWTSi7ipEYwzKoTtR6qZBqdVHTR9D382UDevEJvzv/aBISbyEjbsW Im5nXCTsB8LPQCR0PFU39EI+evAe301ddJUXxafQo+XGzVUKAQ2Hx5nhZ6L4XAoHp3bq u9vjNvVB3zWj56ckdPczRBcntF2O+q5deh3YB+0CuM9PqhoN998W6PpewukhqUrk6LiA 9+hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Xtj/YspweNDXNSalS9uwvsWmvlz2awO1cN3TGJ6zgII=; b=a9OUhcHzMuttHzhr7tlWlm3a9iqC3BEu4mW88h2+zgFMC0iG65YTQeHMCWltcAF4jK BwkElCFEnGCAKBZ+8ajhvlY9iGVrmxfHM19/pg4184WxQdpTW4hMhh3EYu3ImZ3YqdH5 dimS9vROUUyFVQaolnGkLOg74+x+uK4pgrBhmyj0GXKo1s3W/WhI0XYOTuxOi2kERufQ Nt0ViLI4fxovULJJ9+4ktDP7wHm+w6aq/yt9iG1vZ2vWBkNg5wqE5jz6KrMlzl5bZWvn pjmhjNo3POAShah4ywJNF/MJnjPr8TbaSZ+g3p7NUowHPR79BbtSFmgl+OyBvpuciHS5 /f3A== X-Gm-Message-State: AOAM530rMDGAU8+D65sOwzkrfbsd6Fu66Au9semKbYSx0FOsTqYxNHcB QDx7j+SmlYUFXctFE7oq6T4bJQ== X-Google-Smtp-Source: ABdhPJwW/Wt91j0NvQ+g/Vzv5FBrIsaN4Iw9oZd7gioHCJtpuV5ctMGCtUr788VCxglRKPUGb+ksZA== X-Received: by 2002:a05:6000:1543:: with SMTP id 3mr559903wry.254.1611859988612; Thu, 28 Jan 2021 10:53:08 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id v6sm8019721wrx.32.2021.01.28.10.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 10:53:07 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id BE9FD1FF7E; Thu, 28 Jan 2021 18:53:06 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Anders Roxell , Peter Maydell Subject: [PATCH] docs/system: document an example vexpress-a15 invocation Date: Thu, 28 Jan 2021 18:53:00 +0000 Message-Id: <20210128185300.2875-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 18:53:12 -0000 The wiki and the web are curiously absent of the right runes to boot a vexpress model so I had to work from first principles to work it out. Use the more modern -drive notation so alternative backends can be used (unlike the hardwired -sd mode). Signed-off-by: Alex Bennée Cc: Anders Roxell --- docs/system/arm/vexpress.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst index 7f1bcbef07..30b1823b95 100644 --- a/docs/system/arm/vexpress.rst +++ b/docs/system/arm/vexpress.rst @@ -58,3 +58,29 @@ Other differences between the hardware and the QEMU model: ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is provided on the command line then QEMU will edit it to include suitable entries describing these transports for the guest. + +Booting a Linux kernel +---------------------- + +Building a current Linux kernel with ``multi_v7_defconfig`` should be +enough to get something running. + +.. code-block:: bash + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-linux-gnueabihf- + $ make multi_v7_defconfig + $ make + +By default you will want to boot your rootfs of the sdcard interface. +Your rootfs will need to be padded to the right size. With a suitable +DTB you could also add devices to the virtio-mmio bus. + +.. code-block:: bash + + $ qemu-system-arm -cpu cortex-a15 -smp 4 -m 4096 \ + -machine type=vexpress-a15 -serial mon:stdio \ + -drive if=sd,driver=file,filename=armel-rootfs.ext4 \ + -kernel zImage \ + -dtb vexpress-v2p-ca15-tc1.dtb \ + -append "console=ttyAMA0 root=/dev/mmcblk0 ro" -- 2.20.1 From MAILER-DAEMON Thu Jan 28 13:57:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5CTU-000238-Ni for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 13:57:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5CTS-000227-RO; Thu, 28 Jan 2021 13:56:58 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:57544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5CTQ-0001mM-42; Thu, 28 Jan 2021 13:56:58 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id EBDFCC602E6; Thu, 28 Jan 2021 19:56:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611860210; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=PhCu5VZ+N0y8BKMMUt9pRNZk4CFb1adHzYxlBpNDyZU=; b=fr4fb9nMiyjcwrupz1UYn9Hd97dwdD1/Je5cikqHJXmKg4qmiFH8feM/MU0Jy49KjJpQFC anAJQg0MVLnAC2VEOf5xYQKf6MzNqPEp6q0J/hwT+Wvc2gS/Aq3ScM7RDpkk7xJozAZ1kr Y1IR8+KtRZ2CRLlXXkJLN37aH2hAtiZVugZGSNlIryeTu7482mrnlWdpHt7yvvkJ4aYkpF 3TQV9e5/qXJ+fAsZgRcKQVhiPQE+TH3uke20eu4xdQdB9HrVCM9osVVolugZSlqOyClT/X NCyjPVCIVGdHWPYk/In27MnS/6Vj5lR5iszM+uMReOID0dEmMl2ieOfIY9JoNA== Date: Thu, 28 Jan 2021 19:57:13 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v2 05/25] tests: Add a simple test of the CMSDK APB dual timer Message-ID: <20210128185713.ecccnb5bx35l3bdn@sekoia-pc.home.lmichel.fr> References: <20210128114145.20536-1-peter.maydell@linaro.org> <20210128114145.20536-6-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210128114145.20536-6-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 18:56:59 -0000 On 11:41 Thu 28 Jan , Peter Maydell wrote: > Add a simple test of the CMSDK dual timer, since we're about to do > some refactoring of how it is clocked. > > Signed-off-by: Peter Maydell > Message-id: 20210121190622.22000-6-peter.maydell@linaro.org Reviewed-by: Luc Michel > --- > v1->v2 changes: > - phrase various clock_step() arguments as calculations > based on tick counts and the ns-per-tick value rather > than just the final numbers > - remove set-but-not-used QTestState *s variable > that gcc warns about but clang does not > - use 40 * 256 in test_prescale() as suggested by Luc > --- > tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++ > MAINTAINERS | 1 + > tests/qtest/meson.build | 1 + > 3 files changed, 132 insertions(+) > create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c > > diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c > new file mode 100644 > index 00000000000..ad6a758289c > --- /dev/null > +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c > @@ -0,0 +1,130 @@ > +/* > + * QTest testcase for the CMSDK APB dualtimer device > + * > + * Copyright (c) 2021 Linaro Limited > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest-single.h" > + > +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ > +#define TIMER_BASE 0x40002000 > + > +#define TIMER1LOAD 0 > +#define TIMER1VALUE 4 > +#define TIMER1CONTROL 8 > +#define TIMER1INTCLR 0xc > +#define TIMER1RIS 0x10 > +#define TIMER1MIS 0x14 > +#define TIMER1BGLOAD 0x18 > + > +#define TIMER2LOAD 0x20 > +#define TIMER2VALUE 0x24 > +#define TIMER2CONTROL 0x28 > +#define TIMER2INTCLR 0x2c > +#define TIMER2RIS 0x30 > +#define TIMER2MIS 0x34 > +#define TIMER2BGLOAD 0x38 > + > +#define CTRL_ENABLE (1 << 7) > +#define CTRL_PERIODIC (1 << 6) > +#define CTRL_INTEN (1 << 5) > +#define CTRL_PRESCALE_1 (0 << 2) > +#define CTRL_PRESCALE_16 (1 << 2) > +#define CTRL_PRESCALE_256 (2 << 2) > +#define CTRL_32BIT (1 << 1) > +#define CTRL_ONESHOT (1 << 0) > + > +static void test_dualtimer(void) > +{ > + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); > + > + /* Start timer: will fire after 40000 ns */ > + writel(TIMER_BASE + TIMER1LOAD, 1000); > + /* enable in free-running, wrapping, interrupt mode */ > + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); > + > + /* Step to just past the 500th tick and check VALUE */ > + clock_step(500 * 40 + 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(500 * 40); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); > + > + /* > + * We are in free-running wrapping 16-bit mode, so on the following > + * tick VALUE should have wrapped round to 0xffff. > + */ > + clock_step(40); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); > + > + /* Check that any write to INTCLR clears interrupt */ > + writel(TIMER_BASE + TIMER1INTCLR, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); > + > + /* Turn off the timer */ > + writel(TIMER_BASE + TIMER1CONTROL, 0); > +} > + > +static void test_prescale(void) > +{ > + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); > + > + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ > + writel(TIMER_BASE + TIMER2LOAD, 1000); > + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ > + writel(TIMER_BASE + TIMER2CONTROL, > + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); > + > + /* Step to just past the 500th tick and check VALUE */ > + clock_step(40 * 256 * 501); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); > + > + /* Just past the 1000th tick: timer should have fired */ > + clock_step(40 * 256 * 500); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); > + > + /* In periodic mode the tick VALUE now reloads */ > + clock_step(40 * 256); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); > + > + /* Check that any write to INTCLR clears interrupt */ > + writel(TIMER_BASE + TIMER2INTCLR, 1); > + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); > + > + /* Turn off the timer */ > + writel(TIMER_BASE + TIMER2CONTROL, 0); > +} > + > +int main(int argc, char **argv) > +{ > + int r; > + > + g_test_init(&argc, &argv, NULL); > + > + qtest_start("-machine mps2-an385"); > + > + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); > + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); > + > + r = g_test_run(); > + > + qtest_end(); > + > + return r; > +} > diff --git a/MAINTAINERS b/MAINTAINERS > index 3729b89f359..154a91d12e5 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h > F: tests/qtest/cmsdk-apb-timer-test.c > F: hw/timer/cmsdk-apb-dualtimer.c > F: include/hw/timer/cmsdk-apb-dualtimer.h > +F: tests/qtest/cmsdk-apb-dualtimer-test.c > F: hw/char/cmsdk-apb-uart.c > F: include/hw/char/cmsdk-apb-uart.h > F: hw/watchdog/cmsdk-apb-watchdog.c > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 9e2ebc47041..69dd4a8547c 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -141,6 +141,7 @@ qtests_npcm7xx = \ > 'npcm7xx_timer-test', > 'npcm7xx_watchdog_timer-test'] > qtests_arm = \ > + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ > (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ > (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ > -- > 2.20.1 > -- From MAILER-DAEMON Thu Jan 28 13:57:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5CU0-0002DT-7N for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 13:57:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5CTy-0002BN-E9; Thu, 28 Jan 2021 13:57:30 -0500 Received: from pharaoh.lmichel.fr ([149.202.28.74]:57586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5CTo-0001tg-1j; Thu, 28 Jan 2021 13:57:30 -0500 Received: from localhost (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPSA id 11C95C602E6; Thu, 28 Jan 2021 19:57:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1611860237; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dt2nXwWpRm8j9+M9HAiJNOIcfqEePQTlCmL6rYZK9gE=; b=bDc9S0lwV/7DygkIDhzueSCTEb9C4Q44tUHegIsERXZxkRx3qC1YU1TYsNomfSLT5RxYn+ RxmcCwanJls7cvH1ZysHFxkTNkOXK7GPfxxTYJZCZnNiSXd0nnCfc+m3RTMQsN4wmM8B4k buwqLNBKUmySNIoPBkYrW65seyHpBJYp7Y3dRLDRI/vttJO/Me36X3qUQNyV5nvvkjx3rJ T+pFgsKaXVnzXUHLodDbAJrtdEh/ouECsx7hqqJkU1RPHrPL8GdmPpTWJDUpEiY9v4GB7r EtblNA20YhWxTRyVV57SdRsxCYBr1eHFQiGCBlIp/NGxM2IFdIFOsm5xjOLl6Q== Date: Thu, 28 Jan 2021 19:57:41 +0100 From: Luc Michel To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v2 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Message-ID: <20210128185741.c6qm47dab47emdqh@sekoia-pc.home.lmichel.fr> References: <20210128114145.20536-1-peter.maydell@linaro.org> <20210128114145.20536-23-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210128114145.20536-23-peter.maydell@linaro.org> Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 18:57:30 -0000 On 11:41 Thu 28 Jan , Peter Maydell wrote: > Use the MAINCLK Clock input to set the system_clock_scale variable > rather than using the mainclk_frq property. > > Signed-off-by: Peter Maydell > Reviewed-by: Philippe Mathieu-Daudé > Message-id: 20210121190622.22000-23-peter.maydell@linaro.org Reviewed-by: Luc Michel > --- > v1->v2: wire armsse_mainclk_update() up as the Clock callback > --- > hw/arm/armsse.c | 24 +++++++++++++++++++----- > 1 file changed, 19 insertions(+), 5 deletions(-) > > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c > index 4349ce9bfdb..9a6b24c79aa 100644 > --- a/hw/arm/armsse.c > +++ b/hw/arm/armsse.c > @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) > qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); > } > > +static void armsse_mainclk_update(void *opaque) > +{ > + ARMSSE *s = ARM_SSE(opaque); > + /* > + * Set system_clock_scale from our Clock input; this is what > + * controls the tick rate of the CPU SysTick timer. > + */ > + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); > +} > + > static void armsse_init(Object *obj) > { > ARMSSE *s = ARM_SSE(obj); > @@ -242,7 +252,8 @@ static void armsse_init(Object *obj) > assert(info->sram_banks <= MAX_SRAM_BANKS); > assert(info->num_cpus <= SSE_MAX_CPUS); > > - s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); > + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", > + armsse_mainclk_update, s); > s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); > > memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); > @@ -451,9 +462,11 @@ static void armsse_realize(DeviceState *dev, Error **errp) > return; > } > > - if (!s->mainclk_frq) { > - error_setg(errp, "MAINCLK_FRQ property was not set"); > - return; > + if (!clock_has_source(s->mainclk)) { > + error_setg(errp, "MAINCLK clock was not connected"); > + } > + if (!clock_has_source(s->s32kclk)) { > + error_setg(errp, "S32KCLK clock was not connected"); > } > > assert(info->num_cpus <= SSE_MAX_CPUS); > @@ -1115,7 +1128,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) > */ > sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); > > - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; > + /* Set initial system_clock_scale from MAINCLK */ > + armsse_mainclk_update(s); > } > > static void armsse_idau_check(IDAUInterface *ii, uint32_t address, > -- > 2.20.1 > -- From MAILER-DAEMON Thu Jan 28 15:03:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5DVJ-0005a3-7N for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 15:03:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5DVB-0005Z7-8f for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 20:02:40 +0000 (UTC) Received: from work-vm (ovpn-115-60.ams2.redhat.com [10.36.115.60]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 79DEE5D9F4; Thu, 28 Jan 2021 20:02:25 +0000 (UTC) Date: Thu, 28 Jan 2021 20:02:23 +0000 From: "Dr. David Alan Gilbert" To: Paolo Bonzini Cc: Keqian Zhu , Kirti Wankhede , Alex Williamson , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , Igor Mammedov , wanghaibin.wang@huawei.com, Zenghui Yu , jiangkunkun@huawei.com Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener Message-ID: <20210128200223.GJ2951@work-vm> References: <20210111073439.20236-1-zhukeqian1@huawei.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 20:02:49 -0000 * Paolo Bonzini (pbonzini@redhat.com) wrote: > On 11/01/21 08:34, Keqian Zhu wrote: > > +static void vfio_listener_log_start(MemoryListener *listener, > > + MemoryRegionSection *section, > > + int old, int new) > > +{ > > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > > + > > + vfio_set_dirty_page_tracking(container, true); > > +} > > + > > +static void vfio_listener_log_stop(MemoryListener *listener, > > + MemoryRegionSection *section, > > + int old, int new) > > +{ > > + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > > + > > + vfio_set_dirty_page_tracking(container, false); > > +} > > + > > This would enable dirty page tracking also just for having a framebuffer > (DIRTY_MEMORY_VGA). Technically it would be correct, but it would also be > more heavyweight than expected. Wouldn't that only happen on emulated video devices? > In order to only cover live migration, you can use the log_global_start and > log_global_stop callbacks instead. > > If you want to use log_start and log_stop, you need to add respectively > > if (old != 0) { > return; > } > > and > > if (new != 0) { > return; > } Why 0, wouldn't you be checking for DIRTY_LOG_MIGRATION somewhere? Dave > before the calls to vfio_set_dirty_page_tracking. But I think it's more > appropriate for VFIO to use log_global_*. > > Thanks, > > Paolo > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Jan 28 16:31:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Et2-0003op-6o for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 16:31:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Et1-0003mW-84 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 16:31:31 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:23441) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5Esw-0002jR-Gq for qemu-arm@nongnu.org; Thu, 28 Jan 2021 16:31:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611869483; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bXce2jqyzXt5VCPVL5P4ZOOaG8p3M/O5OY6ApDO1CRE=; b=g0vZuwpdczGo2HPh9dzdj0SpLawv6HTFFNs9pSfqP0+EhO80emSuRHKZho8v7OYmc4u+qO LaXc10el+cUa1qTC/wXXLxjVj71D5naRLjQBg2YDNbV8gJv7224NmAiouKMShrzofmv6VQ pp9wBLE9WPc2NKXuNL+7HdsbksOQrxY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-202-sIznfFDjPfq_DBZgPFytpg-1; Thu, 28 Jan 2021 16:30:15 -0500 X-MC-Unique: sIznfFDjPfq_DBZgPFytpg-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A2BC48030A0; Thu, 28 Jan 2021 21:30:13 +0000 (UTC) Received: from [10.36.114.62] (ovpn-114-62.ams2.redhat.com [10.36.114.62]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5093F1F469; Thu, 28 Jan 2021 21:30:12 +0000 (UTC) Subject: Re: [PATCH] hw/arm/smmuv3: Fix addr_mask for range-based invalidation From: Auger Eric To: Zenghui Yu , qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: wanghaibin.wang@huawei.com References: <20201225095015.609-1-yuzenghui@huawei.com> <4e114709-e5c2-1860-c760-c05aa3ed5388@redhat.com> Message-ID: <45f3334d-f0b4-9a40-1bd1-78bd04735eaf@redhat.com> Date: Thu, 28 Jan 2021 22:30:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <4e114709-e5c2-1860-c760-c05aa3ed5388@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 21:31:31 -0000 Hi Zenghui, On 1/28/21 9:25 AM, Auger Eric wrote: > Hi Zenghui, > > On 12/25/20 10:50 AM, Zenghui Yu wrote: >> When performing range-based IOTLB invalidation, we should decode the TG >> field into the corresponding translation granule size so that we can pass >> the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to >> properly emulate the architecture. >> >> Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") >> Signed-off-by: Zenghui Yu > > Good catch! I tested with older guest kernels though. I wonder how I did > not face the bug? Please ignore this wrong comment as this corresponds to recent kernels instead. Still puzzled anyway ;-) Eric > > >> --- >> hw/arm/smmuv3.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >> index bbca0e9f20..65231c7d52 100644 >> --- a/hw/arm/smmuv3.c >> +++ b/hw/arm/smmuv3.c >> @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, >> { >> SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >> IOMMUTLBEvent event; >> - uint8_t granule = tg; >> + uint8_t granule; >> >> if (!tg) { >> SMMUEventInfo event = {.inval_ste_allowed = true}; >> @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, >> return; >> } >> granule = tt->granule_sz; >> + } else { >> + guanule = tg * 2 + 10; > maybe just init granule to this value above while fixing the typo. > > Thanks > > Eric >> } >> >> event.type = IOMMU_NOTIFIER_UNMAP; >> From MAILER-DAEMON Thu Jan 28 17:41:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fz7-0005OX-Kp for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:41:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fz5-0005OK-Ex for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:51 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:46559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fz1-00083c-So for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:51 -0500 Received: by mail-pg1-x532.google.com with SMTP id r38so5267512pgk.13 for ; Thu, 28 Jan 2021 14:41:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=58Y2BWHPpBtCNBlBSdo8EMqqUyTjMdnU8TZUneOpgds=; b=cCw7EZV0fbusih35UkR62uQ7pI2uPVEFJOODRDPyURe9Ze4WxA4o41+b/ShlSEODYO EWIbGuM9bZJGz4aQAz2K2e7OTj5iVtr+EgcJ79NFvjwj7cZhsQ7gsPJYMux2Rm1oqs/s Gwo3H1xQZpd3LcY8eD6yCWc0sRYAMj4fqWipwKvtTnrwuFZR6JJ0RSQEsvG7cCJcAwFj cVhPNFcl0udiymApH+cHl9aPRdUsHyTPO01E7SDcxw/9Ao+Z2EE98KjuwgHzeNDZb1Ae +ccnzqsmqVOODrVPw5YRcnE0w2hbGSgOEAztAy+9JeSnRU7lCi01bBeEYTtbP9xC+VIA picQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=58Y2BWHPpBtCNBlBSdo8EMqqUyTjMdnU8TZUneOpgds=; b=CypB3PYUZ42iMlbN2MJOWuUQw9cFBr6WZ1kA1eJjsoeAY4mqKGf65Lt77MGNgfkmpn /PM0qWSb2eHtYuJj/CzT886wkwgZdaSGOSu606Z+DgkrzG/EpREduGO0pG/0fjgX69k9 0vsW6VeDStmC8cPbkPiIJeEg0Fm0uUiT6ZMt5dPgA34tZo9IarQtalMBQYYSiOne4m2h kMyma2bsQ9y8hm2vCsotM5tp+eCSV8JIkSqCDs7KWLSt2dAqdN8a0HAywI59FHRV3S0n CcRDxAxuX0ufOC3u4/XBheRXycHOTFPqLfgy1cDZa39TCphM4k+lU1Gqhbh8MfODqij4 IHjQ== X-Gm-Message-State: AOAM5308d+LSjjEpeceBcmnyXOuOJHsMgyA3K5yWMpuJ9EysOH82gjTB boWe2Or0i+jaEiMCzAlKWE7M0g== X-Google-Smtp-Source: ABdhPJwjpqylOjCDnbgoUQKM6Oj7kiKk5YL1x+Ffls35XoHtV6Zg9x9IgXk+j/AQsJxVDR06tkTvIA== X-Received: by 2002:a63:5805:: with SMTP id m5mr1536885pgb.352.1611873704819; Thu, 28 Jan 2021 14:41:44 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 00/23] target-arm: Implement ARMv8.5-MemTag, user mode Date: Thu, 28 Jan 2021 12:41:18 -1000 Message-Id: <20210128224141.638790-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:41:51 -0000 The kernel abi was finally merged into 5.10. Changes for v4: * Revamp "Add support for TARGET_TAGGED_ADDRESSES". There are now two sets of functions in include/exec/, one for tagged and one for untagged addresses. The former takes a CPUState, and does not assume current_cpu is a thing. So much for the generic bits... However, use of current_cpu remains, pushed down to lock_user. Changing everything that touches that, or get/put_user, is daunting. * Fix tbi0 vs tbi1 for linux-user. This had a number of cascading effects. * Adjust when async errors are noticed. Changes for v3: * Split out type changes to separate patches. * Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. * Do not overlap PAGE_TARGET_2 with PAGE_RESERVED. * Use syndrome.h, arm_deliver_fault. r~ Richard Henderson (23): tcg: Introduce target-specific page data for user-only linux-user: Introduce PAGE_ANON exec: Use uintptr_t for guest_base exec: Use uintptr_t in cpu_ldst.h exec: Improve types for guest_addr_valid linux-user: Check for overflow in access_ok linux-user: Tidy VERIFY_READ/VERIFY_WRITE bsd-user: Tidy VERIFY_READ/VERIFY_WRITE linux-user: Do not use guest_addr_valid for h2g_valid linux-user: Fix guest_addr_valid vs reserved_va exec: Add support for TARGET_TAGGED_ADDRESSES linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE target/arm: Improve gen_top_byte_ignore target/arm: Use the proper TBI settings for linux-user linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG linux-user/aarch64: Implement PROT_MTE target/arm: Split out syndrome.h from internals.h linux-user/aarch64: Pass syndrome to EXC_*_ABORT linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error target/arm: Add allocation tag storage for user mode target/arm: Enable MTE for user-only tests/tcg/aarch64: Add mte smoke tests bsd-user/qemu.h | 9 +- include/exec/cpu-all.h | 47 ++++- include/exec/cpu_ldst.h | 42 +++-- linux-user/aarch64/target_signal.h | 3 + linux-user/aarch64/target_syscall.h | 13 ++ linux-user/qemu.h | 19 +- linux-user/syscall_defs.h | 1 + target/arm/cpu-param.h | 3 + target/arm/cpu.h | 32 ++++ target/arm/internals.h | 249 +------------------------ target/arm/syndrome.h | 273 ++++++++++++++++++++++++++++ tests/tcg/aarch64/mte.h | 60 ++++++ accel/tcg/translate-all.c | 28 +++ bsd-user/main.c | 4 +- linux-user/aarch64/cpu_loop.c | 38 +++- linux-user/elfload.c | 4 +- linux-user/main.c | 4 +- linux-user/mmap.c | 29 ++- linux-user/syscall.c | 71 +++++++- target/arm/cpu.c | 25 ++- target/arm/mte_helper.c | 39 +++- target/arm/tlb_helper.c | 15 +- target/arm/translate-a64.c | 25 +-- tests/tcg/aarch64/mte-1.c | 28 +++ tests/tcg/aarch64/mte-2.c | 45 +++++ tests/tcg/aarch64/mte-3.c | 51 ++++++ tests/tcg/aarch64/mte-4.c | 45 +++++ tests/tcg/aarch64/pauth-2.c | 1 - tests/tcg/aarch64/Makefile.target | 6 + tests/tcg/configure.sh | 4 + 30 files changed, 888 insertions(+), 325 deletions(-) create mode 100644 target/arm/syndrome.h create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:41:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzD-0005Q1-6i for mharc-qemu-arm@gnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 01/23] tcg: Introduce target-specific page data for user-only Date: Thu, 28 Jan 2021 12:41:19 -1000 Message-Id: <20210128224141.638790-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:41:58 -0000 This data can be allocated by page_alloc_target_data() and released by page_set_flags(start, end, prot | PAGE_RESET). This data will be used to hold tag memory for AArch64 MTE. Signed-off-by: Richard Henderson --- v3: Add doc comments; tweak alloc so that the !PAGE_VALID case is clear. --- include/exec/cpu-all.h | 42 +++++++++++++++++++++++++++++++++------ accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++ linux-user/mmap.c | 4 +++- linux-user/syscall.c | 4 ++-- 4 files changed, 69 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4b5408c341..99a09ee137 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -264,15 +264,21 @@ extern intptr_t qemu_host_page_mask; #define PAGE_EXEC 0x0004 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 -/* original state of the write flag (used when tracking self-modifying - code */ +/* + * Original state of the write flag (used when tracking self-modifying code) + */ #define PAGE_WRITE_ORG 0x0010 -/* Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 + #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 @@ -287,6 +293,30 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); + +/** + * page_alloc_target_data(address, size) + * @address: guest virtual address + * @size: size of data to allocate + * + * Allocate @size bytes of out-of-band data to associate with the + * guest page at @address. If the page is not mapped, NULL will + * be returned. If there is existing data associated with @address, + * no new memory will be allocated. + * + * The memory will be freed when the guest page is deallocated, + * e.g. with the munmap system call. + */ +void *page_alloc_target_data(target_ulong address, size_t size); + +/** + * page_get_target_data(address) + * @address: guest virtual address + * + * Return any out-of-bound memory assocated with the guest page + * at @address, as per page_alloc_target_data. + */ +void *page_get_target_data(target_ulong address); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 81d4c83f22..bba9c8e0b3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -114,6 +114,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2740,6 +2741,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2754,6 +2756,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2767,10 +2771,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p->flags & PAGE_VALID) { + ret = p->target_data; + if (!ret) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 810653c503..c693505b60 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: trace_target_mmap_complete(start); @@ -792,7 +793,8 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = h2g(host_addr); prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 34760779c8..6001022e96 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4632,8 +4632,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzF-0005Sc-Cu for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzD-0005Ql-Pa for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:59 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:38162) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fz5-00085D-32 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:59 -0500 Received: by mail-pf1-x42e.google.com with SMTP id y205so4966045pfc.5 for ; Thu, 28 Jan 2021 14:41:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ro1QlxJECFSg4T0qJhYTh9dJGKCuHRxnJ3IHfAQq/RM=; b=TYrpS9gATOUJYsbU8tfz+MqcCiG0GJFuTz18MJvgyG8WoM4iDZo6HeTH14sZr1Sp+O 53JEcBFkWMZ97eAL16azZ6GKpNxy+I61nm9m0XgiJU0vy8rc1SRn32zTmFIszQc0rUW6 3IqkDlCmeLcHH0YKRL5wF+JcQivJjv/tY3hDzkSE3l79LEr+FYRgLQi642xO5b4XYJRm 3h2tX0Vl4wKjw1kis1H3g3OobRZkzo0swpongq+lr06Sr5GXhIXvDgizER4hpXQlLBl8 9fIcEK31i/l9ZQ7uUPzHPr+2to6mvboPxP7IJwGg0AuRP3WJZZNLvVyGik0XsNno+oP/ 4q5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ro1QlxJECFSg4T0qJhYTh9dJGKCuHRxnJ3IHfAQq/RM=; b=N+pqIOWmyiCgs9G0MEw/F7CW7J0GbN1j4ore6BW/6j/WEecKPFPp2FaSvnZHmFyRZE WvsmUFg9GrlLmLwGE5sIpeBnNo8Dll+AqN7IyZvC1pUJYer/vP1RikMqssoM675cEF7l VAsMhatU34kSNVhp5QzLJzg0ogGAQlrazOm5VRFYWsM2CZEtA4QG8cgZeX/wcl7XQqI/ uW3SjHMOx5wa9poxbrygIV1g32IMV9fivFGx5psCaC8tSnxmhOJMWYaeUpwddpNPQ29p rwKJqbq47UfK4MFhTiwlN7MVOx9q7s9kvUv5jfSy00AHvm7WBJm4ujb2H1Ykomc6rAcQ us2g== X-Gm-Message-State: AOAM532dyA5rl5KCCJXJW4An6Bq4XU+6HQGwyR0zZCJpszympRgcCKmH D0bPzSQth3yPoKVSdPxZSx/L4FLtZlVaBuIM X-Google-Smtp-Source: ABdhPJw67VFfy4FqDwujFVHGW8z1zMUJE/kl1DSfu+Tsrmlk7VciKWsIxH4lAadNmQSi7FuOLKCxEA== X-Received: by 2002:a63:1f21:: with SMTP id f33mr1639027pgf.31.1611873709819; Thu, 28 Jan 2021 14:41:49 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 03/23] exec: Use uintptr_t for guest_base Date: Thu, 28 Jan 2021 12:41:21 -1000 Message-Id: <20210128224141.638790-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:00 -0000 This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- bsd-user/main.c | 4 ++-- linux-user/elfload.c | 4 ++-- linux-user/main.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c23c77589b..c52180e8e6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -158,7 +158,7 @@ static inline void tswap64s(uint64_t *s) /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient location. */ -extern unsigned long guest_base; +extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; diff --git a/bsd-user/main.c b/bsd-user/main.c index 65163e1396..c09d74d788 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -41,7 +41,7 @@ int singlestep; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; unsigned long reserved_va; @@ -965,7 +965,7 @@ int main(int argc, char **argv) g_free(target_environ); if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a64050713f..29f07bb234 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2135,9 +2135,9 @@ static void pgb_have_guest_base(const char *image_name, abi_ulong guest_loaddr, void *addr, *test; if (!QEMU_IS_ALIGNED(guest_base, align)) { - fprintf(stderr, "Requested guest base 0x%lx does not satisfy " + fprintf(stderr, "Requested guest base %p does not satisfy " "host minimum alignment (0x%lx)\n", - guest_base, align); + (void *)guest_base, align); exit(EXIT_FAILURE); } diff --git a/linux-user/main.c b/linux-user/main.c index bb4e55e8fc..55aac56d70 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -58,7 +58,7 @@ static const char *cpu_model; static const char *cpu_type; static const char *seed_optarg; unsigned long mmap_min_addr; -unsigned long guest_base; +uintptr_t guest_base; bool have_guest_base; /* @@ -819,7 +819,7 @@ int main(int argc, char **argv, char **envp) g_free(target_environ); if (qemu_loglevel_mask(CPU_LOG_PAGE)) { - qemu_log("guest_base 0x%lx\n", guest_base); + qemu_log("guest_base %p\n", (void *)guest_base); log_page_dump("binary load"); qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzH-0005UG-Kj for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzE-0005Rp-LX for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:00 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:43022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fz7-00085R-6D for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:00 -0500 Received: by mail-pg1-x536.google.com with SMTP id n10so5268701pgl.10 for ; Thu, 28 Jan 2021 14:41:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uDiO56BD9yBVu0nwAI/hhOcXCMAfaRu426dsljY4dMQ=; b=KNlwAW2OtJHHam3IQR/lsRk9Kkd/FHpeb5a/HSmXLS9KqdjNR5vGwB1AsZNyaQbEx4 HDXyNpvJTBMpL+DbLBomdUgTMjz3h5LZcDP0959pMNRP6UGQGWiqb0jKd5mzZG8HQciB CFhZEWcZ7u9anNLUUiCn8Uw5X3Hg/t4GwcWfW7wQmgiTWujJabCl2/p2TtNOMOrbyqlZ WqZ4nyyKgTgLVQfUZok5n1h1lp+QIhlg6W2sesBuflgJ5x+6+AnKdawZtdFtw6ZNlphg jFMfBZQc5g8GPcG/pcYhfKvXsUeJNO/1NcegO1td/u4W4r73BWFfRlJk1+YnD5l0tdgI P1BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uDiO56BD9yBVu0nwAI/hhOcXCMAfaRu426dsljY4dMQ=; b=cs+e1T/Tb3ua9c2mfZlBQUYoeMPsvH6Fdswi/H6LgOshXrb57aIcirP6hexbo4omUS B3mJUyRFoM/ZsERugFWgccl/vxz66ke5eaV+APTLdH9v3/jsbf1UfurGV7SsOfs8ypBX Jx5VZjEbcjKKPix1OnoZPaxMQYkc5b1cYLG923gzOvDsxU/FM5W9DstXdyssj93EIuXw KEqJ5KWE+JF0CfQwvin93XpD9SrS0E7OU1AeLPZnLKGK10Kv7g3jmAvVcHMG85oEPAWl twZ4pG4YKLTAuwyAJVe3gzqSMEyguGJEpFbdKkmWGXtyzxrXx7clohD/F8YT4pNVvtfj uM4Q== X-Gm-Message-State: AOAM531k7wqzYZqLWet0aNOHy6byYZ4KxdpuHqHpq3PW+lye//GwpJJK 0MNmLX3sKWyYbZwm5z91v04dyw== X-Google-Smtp-Source: ABdhPJz8RLw1G3hQXRoCQgl7Vd2e7FPt00q/y4DCoI5jZC6TLHhL2i/IY7wuDe9C00oRe5TFnl/33g== X-Received: by 2002:a62:5c43:0:b029:1bb:9418:b59b with SMTP id q64-20020a625c430000b02901bb9418b59bmr1372979pfb.35.1611873711385; Thu, 28 Jan 2021 14:41:51 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 04/23] exec: Use uintptr_t in cpu_ldst.h Date: Thu, 28 Jan 2021 12:41:22 -1000 Message-Id: <20210128224141.638790-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:01 -0000 This is more descriptive than 'unsigned long'. No functional change, since these match on all linux+bsd hosts. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ef54cb7e1f..3f9063aade 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -70,14 +70,14 @@ typedef uint64_t abi_ptr; #endif /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base)) +#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS #define guest_addr_valid(x) (1) #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base) +#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline int guest_range_valid(unsigned long start, unsigned long len) { @@ -85,7 +85,7 @@ static inline int guest_range_valid(unsigned long start, unsigned long len) } #define h2g_nocheck(x) ({ \ - unsigned long __ret = (unsigned long)(x) - guest_base; \ + uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ }) -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzK-0005Ww-RC for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzD-0005QU-J0 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:59 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:44515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fz5-00084u-2W for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:41:59 -0500 Received: by mail-pf1-x430.google.com with SMTP id t29so4961550pfg.11 for ; Thu, 28 Jan 2021 14:41:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kyzjq96nH0KWrOiii6echH6ofV70lplGMBMMhcVo2Uo=; b=KvS9dgiqbKO3ebcoIxR4Yrw78r+JAItDFG6rSKiz6tsiOXoFZYxWLyKCmfsRMnw2h9 Vv9VCBKa7d1ylMd/YcZ2I1pKzbZd6mjRSwdLKpikbSyO1xMEdLyksV8l2/EflSOjjI2v ZeMrhLfcpOrl0hDb7H1rhyHAkwUK2zIZ3tSwlrx2O23qtXUGmkWgOWK73Ck9iHg7rag6 cgJiqdJUewKFfhQlwYWlB93TdKhQdMPmg4tqCtGUTPMk/MZYXnssgitNGMRV+Me7Yn4O COm3fZkRWuH5eBkuezZzsfn1ncBY2K+ZE2Nn0MRhsR9Gq2sKabCdp3imG/EhlcPfkHyn o7cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kyzjq96nH0KWrOiii6echH6ofV70lplGMBMMhcVo2Uo=; b=GT/QywoSfDL358X0h9rIe8zETcOM6XN1Ga2GW53GFH3jcfJQohpQ8QHibKPZZnw066 nyqTNUaDO9y8BkThc6MJpd9mVLj2uJZYg9O4/8QTrLrY9zlDkm7Pb2HPzYusg2lYVp3B Ef16kWIrFH+z+fIBb6Jnfm/3LnoVi6r0qH4DWMBcFy5dKuxRQrQF+RGLZTeV8VzlJIUa 0vWhBs6fKtCcSDq92EeounrHBRtoT/cwDd+ooqyIpCcin2S/LxCK6e4WJeY6DPq0T4oc g2rCPA5GWFOXoxhVypIFVSw1NFrgnZEq7EMJKK1Nj9Z1rL4d+kTcWGd0Nc4ZM7vlGcXZ rtng== X-Gm-Message-State: AOAM530+8YEw1FrGXMC/5VL56s6Z/AlGRDLytFg0Hk0JaBIU3W1lFB+e CzPZsyNAcW2Al4pmIcMCkRzthg== X-Google-Smtp-Source: ABdhPJxZnm2XCviJEVTpglJ+1Ql0hniAiWMd0Fw0BeAkx1h739L2eosR3lAhaNqvEP2Kg+lPe32yoA== X-Received: by 2002:a63:bd4a:: with SMTP id d10mr1589649pgp.18.1611873708278; Thu, 28 Jan 2021 14:41:48 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 02/23] linux-user: Introduce PAGE_ANON Date: Thu, 28 Jan 2021 12:41:20 -1000 Message-Id: <20210128224141.638790-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:41:59 -0000 Record whether the backing page is anonymous, or if it has file backing. This will allow us to get close to the Linux AArch64 ABI for MTE, which allows tag memory only on ram-backed VMAs. The real ABI allows tag memory on files, when those files are on ram-backed filesystems, such as tmpfs. We will not be able to implement that in QEMU linux-user. Thankfully, anonymous memory for malloc arenas is the primary consumer of this feature, so this restricted version should still be of use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/mmap.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 99a09ee137..c23c77589b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -275,6 +275,8 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_INV 0x0020 /* For use with page_set_flags: page is being replaced; target_data cleared. */ #define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index c693505b60..7fb4c628e1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -599,6 +599,9 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, } } the_end1: + if (flags & MAP_ANONYMOUS) { + page_flags |= PAGE_ANON; + } page_flags |= PAGE_RESET; page_set_flags(start, start + len, page_flags); the_end: -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzS-0005ZL-Ac for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzI-0005Uk-9q for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:04 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:41586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzC-00085i-5w for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:03 -0500 Received: by mail-pg1-x531.google.com with SMTP id i7so5277166pgc.8 for ; Thu, 28 Jan 2021 14:41:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BPFkHBCfiYE2/tooUwU3w49LVJJCP7NOmKVnwS50G54=; b=CvUmxM9X2eaF8quUW5YzlNRp8TTpeu52G5JY/4/6pNfV39n6Fx0h98IRLTVfoKl99c FBxqV9h/RlS89jjByTZmoOZIfzfT1wwOml2tlNe3Fb1Bpxi7b5aX7+454BhUp0TcPAbE lpGktkMLskmmoEl/JhVcFUO2xmHgsVewQiCjjT/IgRtJ6jlox7bDg4Ruof4Qy6PAGPfB UbcM9laboiga5j85HzUcCLCIYxjOw+Vud4fakXJyJGU4nwdsUxSWI1SWJ4AsPjH+tSyN bt7iO9r7Q59s8UYiSEfORtFmg5d8OFoC5CZMkFq1GO7H7xznkpl5M+nt0gysPF0Ty7Wt VUAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BPFkHBCfiYE2/tooUwU3w49LVJJCP7NOmKVnwS50G54=; b=kGL8ApH56fOWrdBQQarAZxbW56Sgzya/ZYS/M8bwm0ro0wg7Qld27bdxNDMiZKoMLR 7udFo0V6X8fYHvFBIifRtwEbWksjQvOqkcbJRfmWVvISI5ymaXqr8m0NWtNqGQ4XKqM8 ctX2S6pecfZrSGDYbV4F3H0HEPi+aEoAQH0s8kvO278ppZjOWRzyDiKftaayjpKK6KfA HZcvS+U88iWJ3Bj0Ggc9rjPk0YOOyOVBtcvBXcsM3ptOHNC1Yr0zhLy0fONCSCfTlisw jG3bWKn2tYrGm7C1s/0BgIJv8My9IlWRAItBx7+uyIHG3r/ERApkM+eppjE0Kggv0Iyr tu/g== X-Gm-Message-State: AOAM530M1DSBfWR7+glCBRtFdyZCfElfXyZGQ1erV0aRcWpH58P9DrEc xOulIRjt1CXLDLTtFAIJToAt6JeY7LGxDCOD X-Google-Smtp-Source: ABdhPJzVOkal9PGdRk393v7XvHMYy+1C4ah/1MFZmlguOEILcDI/+kjN20+6qkCGonjbLnPzU0Tqjg== X-Received: by 2002:a62:25c5:0:b029:1bc:431b:6aa4 with SMTP id l188-20020a6225c50000b02901bc431b6aa4mr1414714pfl.58.1611873713096; Thu, 28 Jan 2021 14:41:53 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 05/23] exec: Improve types for guest_addr_valid Date: Thu, 28 Jan 2021 12:41:23 -1000 Message-Id: <20210128224141.638790-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:06 -0000 Return bool not int; pass abi_ulong not 'unsigned long'. All callers use abi_ulong already, so the change in type has no effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 3f9063aade..5e8878ee9b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -79,7 +79,7 @@ typedef uint64_t abi_ptr; #endif #define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) -static inline int guest_range_valid(unsigned long start, unsigned long len) +static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5FzQ-0005Xi-BA for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:32952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzF-0005Sj-T7 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:02 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:33934) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzC-00086q-5r for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:01 -0500 Received: by mail-pf1-x429.google.com with SMTP id m6so4977327pfk.1 for ; Thu, 28 Jan 2021 14:41:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VyGOgXRVYXE4KsV9afYsCBAI5eV0Qm7bovPtD8hErTQ=; b=y+nqzgfUpxP+MBupTlO6Fw47r3A/VRUS1Nz3V+loikx3SMBMSIQ5WtaxoIjvuLee3F Mc4qqSWpEegKlFbVWdE7hp7bw0f4QmUrvfWlMYYmR9VuJGt4iTREmBMNY4yGwExdp8UM JzDv1mBc/jMCW/oK7IEmd0h81kGOSTi3FhQpDSWgMNGoBbfnic/JvHOjZDnqb3XLgAIj /wg4QD61CZR5FgPb+7Ru48qaGUhtwLgz2qEqKRVNur8DMZHJ8wkWQ/tA6ggsNFZL2Oq5 ZO8EGFPjdL2luPkW8cv8Q70HyTsFu1KDOQnb0FSe+jwvkuOiGnXgtf1NuJqgojrkGs2m NiGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VyGOgXRVYXE4KsV9afYsCBAI5eV0Qm7bovPtD8hErTQ=; b=L3SaMMB9WDuVB5iAAQLcuNVzZ3/EIh4FP51pbIFyVyoVeZryc7nw+S4RazAA1lVZMM fZEkvrqBlwMpw0Pu6CUrk5Erx7jmunOO0cSbACscT615WmyWzq0RNVf3eGT8PkLNkLk9 XI8eZDq/Wl4XiRHnnnpL4EdHPsKe4dzA+7EdEzlwA7OF+9a0DMwFoxnGEStoOE732+Vm vlr5zNswkR96kv58eFi/mNKulyrk52ZmdaNVDLYLr9K0S3D7HhQYw400sBDfKxXR4cEA wPsbui/XSlWQJP16Dg4ipRh0xC7/fuccgWC21Gkc9bjxAJpquwLa8Jo67Ryh2ScmAVg4 PKfA== X-Gm-Message-State: AOAM530zIELaQ/c4a+UAffbEByWwRTjALg1khCj2qLi5IN3s7s9yB0mu 05EfiO/S+HLVs9iPBZuCnj2RRA== X-Google-Smtp-Source: ABdhPJzb7Oto9jfFEkwxXRarlbsg1pyQ/Dqr68V/bpDJZg4OQ7rZaPykW0/si/7klCAGw3+yYKWOug== X-Received: by 2002:a63:9811:: with SMTP id q17mr1640543pgd.238.1611873716255; Thu, 28 Jan 2021 14:41:56 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 07/23] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 28 Jan 2021 12:41:25 -1000 Message-Id: <20210128224141.638790-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:02 -0000 These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 441ba6a78b..9251337daf 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -488,8 +488,8 @@ extern unsigned long guest_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { @@ -501,9 +501,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) !guest_addr_valid(addr + size - 1))) { return false; } - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : - (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzc-0005de-Np for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzK-0005WA-J4 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:11 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:39348) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzC-00086Z-6E for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:06 -0500 Received: by mail-pg1-x52a.google.com with SMTP id o63so5269917pgo.6 for ; Thu, 28 Jan 2021 14:41:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yAOD8rB2c9GoNvNcKMZwjdplIAr1RvdqOJ4SbnIjxU0=; b=R/F3YyFCc8P4RFEKcagFfxMLOvG9vlxwyTklHlikzFx6WPnuKQWec2SILIg7td2fzU siH2mWYc7CCMnj+eJF0B1Vixgveut2jo7Gkp8pTi0j65BJQwNvY9Wk1i8kSpJCCRitxo YXfGFUeZ+PoJHlJLTCfHOP5unBeerJ+X9jd+1tl0ifjkhOGWY9XaQ8PAgK3H5c78Ij1a qDLjKceXJ0esgipHREPO4UGuRZ+VzXEpjn2xkifg7SLO2dLTtzV/ps1Z3s+Phn47H0pO OHGfGN7qBSirTQtcKvERMM2v2c77rPhuQ6cdWl4FTgjZQJi+QSCULyeZFwICdhAGjaLa JjCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yAOD8rB2c9GoNvNcKMZwjdplIAr1RvdqOJ4SbnIjxU0=; b=Ctse1rLzVBYe+qZkEzzeaWBPhLwP05UOvRPRiX1K7B0tQqOBHPYyTDUoR24gN6rL39 k780eODh7DIMmvEeZWPjiCbE/jrO9QTGTyRys97/RYEDShGis+HFcT1RQbswa7wQtwbr NC3D62Lf7dCRxTZCjHvcgvVGib1aqmNz1h4UuEB5mZ55P5i22c3Slbs/G6ZySDYoHcmE MSGAj1PLwXW8jEt2Q6w+3yYBMZIO++KPNgXerdNhpl7e9+lvK47TkmEzBsWGjZ2Ol4pE wOu+IANdEs2xus7ju2Qp2mJeOfBC8/xFa7LIZD90UgJnZamh5CcM5uuOQw9xerbNMkSp Gbeg== X-Gm-Message-State: AOAM5305ZXdQ65SMR82hPs8HOnwKRY7orARQYF6NUL+k05I3w/zaqYuW f/TtPZnA/FDrSSNADFBNRRVGKg== X-Google-Smtp-Source: ABdhPJyCoHhIpJobTui0FmknN/9uXGPI9TVSZnqw3kykCRB1K6dV+XhFOTMI17nfHpzknwMquxbmVg== X-Received: by 2002:a65:408c:: with SMTP id t12mr1532592pgp.157.1611873714714; Thu, 28 Jan 2021 14:41:54 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 06/23] linux-user: Check for overflow in access_ok Date: Thu, 28 Jan 2021 12:41:24 -1000 Message-Id: <20210128224141.638790-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:12 -0000 Verify that addr + size - 1 does not wrap around. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/qemu.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 17aa992165..441ba6a78b 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -491,12 +491,19 @@ extern unsigned long guest_stack_size; #define VERIFY_READ 0 #define VERIFY_WRITE 1 /* implies read access */ -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return guest_addr_valid(addr) && - (size == 0 || guest_addr_valid(addr + size - 1)) && - page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + if (!guest_addr_valid(addr)) { + return false; + } + if (size != 0 && + (addr + size - 1 < addr || + !guest_addr_valid(addr + size - 1))) { + return false; + } + return page_check_range((target_ulong)addr, size, + (type == VERIFY_READ) ? PAGE_READ : + (PAGE_READ | PAGE_WRITE)) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzc-0005eL-VQ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzK-0005Wg-MI for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:11 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:38164) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzF-00088Q-RR for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:06 -0500 Received: by mail-pj1-x1033.google.com with SMTP id l18so5250227pji.3 for ; Thu, 28 Jan 2021 14:42:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4REF6cfdA8MQv8viPXefMUo/38x0z3uSDZzFVOD3Xwc=; b=Aw9NDjqY6PN9drRr+/r4nElPi2eAAbZVnJ+fn1Z7s0D8FWNFXW47STthtTal25DXQh qHZyeD3xL78B8D3btXbY1ByLAWKpBUpr04H14BerHxArgo+E3gOlh5TVD80m3vulh3Fx rsfKisD58WD2thmQWv5xTsBApsH7uGru0HCwDm9blDgeRKHzVfriJ1jIYwQ/bKt10SEV LMH/eXAAu8xEyMfGbXov7Mjiy5geDpDSr+uATldXchscO8ofjtHoB3Q9kX4i0FhqyaDL u6+1u9IblN9g1WIEQYmwHzLuA46QdYBQUGjfm98yo6ryPP/AFG0iYa41XIDo3d6pxoA1 ez2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4REF6cfdA8MQv8viPXefMUo/38x0z3uSDZzFVOD3Xwc=; b=lkEBJwhXPtsKQ2mLpZNgBm+iI3K+pw2j2EcTc8YUcvPO7a3WY26zJ7RNkaUfix7nTO zoDUcgCregyQJUH/nHm/diQiQjpGLKZr4zJd2MW8N98fmszJxRZJg8+sFgkUC+szt2En 9BwH35NVjo4iecOrqm+2tToZtBUXYpg2uZuT2ByhRLpt5PyqXfHpMWyArWSdoopj3DPP JK2BDOaPZDxr/aK/UXYC2OTrO8LtfXrUt8DCxYRKg4ptxBqVEsw40eBqw6DtOpBd7ltL +TZ8dondRFD8lkXyO/hbcdj5urwkBLxHnkLqwabTE1mHxJtsvArWfpwYx1dBG/C0htN+ vr/g== X-Gm-Message-State: AOAM530DRCkS2rH3pTz6x36BFUvbyzx359L2Udy/AEZh4VO5fLLR1iOr IRDeHEUiOxlzZlmUBdYgOaVHUQ== X-Google-Smtp-Source: ABdhPJyvcZ/prO2NrGDacCA0aBlyyqqHIJdB/JiGfUpoFOQNLt6RqI/lTQAfVGAtT9JVsJ1a9HSFtw== X-Received: by 2002:a17:90b:949:: with SMTP id dw9mr1585322pjb.20.1611873719633; Thu, 28 Jan 2021 14:41:59 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 09/23] linux-user: Do not use guest_addr_valid for h2g_valid Date: Thu, 28 Jan 2021 12:41:27 -1000 Message-Id: <20210128224141.638790-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:12 -0000 This is the only use of guest_addr_valid that does not begin with a guest address, but a host address being transformed to a guest address. We will shortly adjust guest_addr_valid to handle guest memory tags, and the host address should not be subjected to that. Move h2g_valid adjacent to the other h2g macros. Signed-off-by: Richard Henderson --- v3: Ditch type changes; retain true for HLB <= GAM (pmm). --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5e8878ee9b..4e6ef3d542 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -77,13 +77,16 @@ typedef uint64_t abi_ptr; #else #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) #endif -#define h2g_valid(x) guest_addr_valid((uintptr_t)(x) - guest_base) static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; } +#define h2g_valid(x) \ + (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) + #define h2g_nocheck(x) ({ \ uintptr_t __ret = (uintptr_t)(x) - guest_base; \ (abi_ptr)__ret; \ -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzd-0005f5-6h for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzS-0005ZE-9R for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:14 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:44661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzD-00087N-DM for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:13 -0500 Received: by mail-pg1-x533.google.com with SMTP id s23so4008083pgh.11 for ; Thu, 28 Jan 2021 14:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cekQQRp0i5HZWYUW7TcRhFHir1r8zA6FY8NgWmITL0g=; b=P45dcWV36QBYWLPKsh85Wgp3WQ8mod5/LU6UhnVpxZXpLF7P+s96jP2oHihUmevjtd XDYoUccTDJNYUpp/YOO5UERIsz0Ef1HE0+o1LhZiDkrDkjawz2cv4VEPwgs/4zAr9R+G ZvJj3cU3PV039ApCXLD4lao1A2bUseGuCC6lPMBh7Qmi2GF2pq3ZZ2RJtHONPbv0u1Yk 0eRbDgL9KG1bVKeOaEUQcLCpR1Y/zk3bc9JotsKAahf42KqVZIEnwv+EVf8tDG6K47rq NmlLuKObcGatEP00RL1XYZY6qmzV9ddBy289Nkgh4ZTGcQplPlpaLbbTKI4oSRJb0tL6 CSsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cekQQRp0i5HZWYUW7TcRhFHir1r8zA6FY8NgWmITL0g=; b=HvrsgUa6jD8Dp3QdYZTXaBSWyhFPyM4FDmTLIbYA8HbXRZmS0eWJA4ZtOcl25M8A3o 8GciQnfCRwYgbOnq2uOX/tCyUnWfZfCyYuJXgZjLtOZDqrup9pfF9LonY7xZnYKVS3Ln OdRE1b9aFE36Nvz88S+/+pjcDMqGLnqqIxaePShzJsEDA6Egmic+f0O4YztMla76x68y JKxDFNTPkv0O5RHRitKwg5a7FawXNgXg7TrUoRkogXUryhVohOZDpotMvqjVT5O0Z9ye nN1pjMUV2ao+LG6qkDlZ57J/vlrwdNVEiPhx3yqdtsk8IJ8Erw4f4hRuDmslcC/SZ7r8 Pfiw== X-Gm-Message-State: AOAM531oTXtb4HdiEQu3mgf45HF76WDBVtROwb66WU4qNJdDljhj9Yd1 xTjrlbDQL5r3MDtZrOuCUrsmUYVeYQKjRz3W X-Google-Smtp-Source: ABdhPJymCNF5rFURwc8v4QZFuYWTygKAIYhQ9VJtA01WWrZnHOi6sO+NUULWnR68A7AS5a/gddESRQ== X-Received: by 2002:a63:fd10:: with SMTP id d16mr1500415pgh.333.1611873718039; Thu, 28 Jan 2021 14:41:58 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:41:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 08/23] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE Date: Thu, 28 Jan 2021 12:41:26 -1000 Message-Id: <20210128224141.638790-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:14 -0000 These constants are only ever used with access_ok, and friends. Rather than translating them to PAGE_* bits, let them equal the PAGE_* bits to begin. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index f8bb1e5459..4076adabd0 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -218,13 +218,12 @@ extern unsigned long x86_stack_size; /* user access */ -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 /* implies read access */ +#define VERIFY_READ PAGE_READ +#define VERIFY_WRITE (PAGE_READ | PAGE_WRITE) -static inline int access_ok(int type, abi_ulong addr, abi_ulong size) +static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) { - return page_check_range((target_ulong)addr, size, - (type == VERIFY_READ) ? PAGE_READ : (PAGE_READ | PAGE_WRITE)) == 0; + return page_check_range((target_ulong)addr, size, type) == 0; } /* NOTE __get_user and __put_user use host pointers and don't check access. */ -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzd-0005hF-Si for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzS-0005ZS-GV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:15 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:40646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzI-00089K-CV for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:14 -0500 Received: by mail-pj1-x102e.google.com with SMTP id jx18so5244457pjb.5 for ; Thu, 28 Jan 2021 14:42:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X+LaZKuwwsvEvbJ+r5ztAOZO016eLRKSU8aYWIJf1AQ=; b=FLojX3ixA2yr6qJk8jYuO88bLmrIyoPpSgF02ee9VcqomnUs/FTBOJA0xeHzhF1gSK GlhwJZQ5QwBbfCE4UH5m22DPj84x47SVcdZGQDfskbT8Y09V/ZIts/pGOEd/E3sTQjxk NHa8aFWn8obcD+G2ApgvQL8CImzytrk47EFVdtt4zvVJMK4B6z2CU60/SjhTF2ANHiOv 0bchzib+5SCXPv1jvkOdS9HIBM5XvntEcmrWdrzQxFiS3B+yL0B6hdRmBMItm7Okk/97 PktnWWqEe8wnn1T0kNOwG1rF5LrQgBtw3gqH2ETkCRDPUh7LE40ihOd6Glxs1D/MlDRI 0VGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X+LaZKuwwsvEvbJ+r5ztAOZO016eLRKSU8aYWIJf1AQ=; b=duusV2OawFrBQ3I99VRSBYGRGGB0j1x6oFf2hCV7K3Q52Sc4/SWXojK6tjeCSxk0eF z5NjaAtxoCl2mlCZlAa7QlUBR/ZttoN1IOEZFCWR7t9YlFe+FDAE4JaERz2eAC+NKVSg 1ow/6mLD6bzMzmriSIYWsUBfq8RSXcur4ZleAhy8rb0TjD15KzcGODhL67Rki6GU+Z8l 5VF31CUpfZBAhCMWBZZcob6eHnVt+IAFbhoG/TFUbqJ9JaSHBfRZ15KJO5IXXCSQ8Ipc 0liXPkjM+/lwzSOUQdh2FyDWdAVILtFwYgn/zXZ1PIh5FPnwHUQ4sQKjJJCuv5hY8M5h rtyg== X-Gm-Message-State: AOAM532cTmBuk5NnXsWou2QAB8fitQKTOXtjY4YGiDFlw/O7hDfJTf50 5GYG9d3TM0z6msIR+GfTporeOg== X-Google-Smtp-Source: ABdhPJxhALg9iAcIyXkRiiARgETy5dIjO9n6HCoywfZsqIr/DzbYqJOycLqhuGlQKvANacWgU7pu9g== X-Received: by 2002:a17:90a:17c8:: with SMTP id q66mr1515883pja.167.1611873722704; Thu, 28 Jan 2021 14:42:02 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 11/23] exec: Add support for TARGET_TAGGED_ADDRESSES Date: Thu, 28 Jan 2021 12:41:29 -1000 Message-Id: <20210128224141.638790-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:16 -0000 The AArch64 Linux ABI has always enabled TBI, but has historically required that pointer tags be removed before a syscall. This has changed in the lead-up to ARMv8.5-MTE, in a way that affects the ABI generically and not specifically to MTE. This patch allows the target to indicate that (1) there are tags and (2) whether or not they should be taken into account at the syscall level. Adjust g2h, guest_addr_valid, and guest_range_valid to ignore pointer tags, similar to how TIF_TAGGED_ADDR alters __range_ok in the arm64 kernel source. The prctl syscall is not not yet updated, so this change by itself has no visible effect. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e62f4fba00..1df9b93e59 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,17 +69,31 @@ typedef uint64_t abi_ptr; #define TARGET_ABI_FMT_ptr "%"PRIx64 #endif +static inline abi_ptr untagged_addr(abi_ptr x) +{ +#ifdef TARGET_TAGGED_ADDRESSES + if (current_cpu) { + return cpu_untagged_addr(current_cpu, x); + } +#endif + return x; +} + /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -#define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) +static inline void *g2h(abi_ulong x) +{ + return (void *)((uintptr_t)untagged_addr(x) + guest_base); +} static inline bool guest_addr_valid(abi_ulong x) { - return x <= GUEST_ADDR_MAX; + return untagged_addr(x) <= GUEST_ADDR_MAX; } static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { - return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; + return len - 1 <= GUEST_ADDR_MAX && + untagged_addr(start) <= GUEST_ADDR_MAX - len + 1; } #define h2g_valid(x) \ -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzf-0005lI-Bm for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzV-0005b8-Ka for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:18 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:37457) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzK-00089r-9Y for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:17 -0500 Received: by mail-pl1-x62c.google.com with SMTP id q2so4183201plk.4 for ; Thu, 28 Jan 2021 14:42:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ed3tfUDy0PesAaobPtQ3BXGUB495/TZW6laQkFKoabs=; b=yF/j6ZLfWtPUzR7p8XrSzBl2BK9YTHUQZCxe0KLo1/mQIrw3kv6MpzPbrk6Ad128Tf 4LygrIKCrYoBb+kyiAV7Z31dFLJwVfU1t2jdMG1V4RxcBI2xcRxob1dP6T1xauIEgO40 QwnX9T7arJgp7Pv9FHXOE+Yjf1rwWFOIz4NOOjITazEWJm+uHSwy9xm7X0PRnoRBAfz4 96buEfaXSlp2MTiG3xNTzBFw+fadhQgzrZr2CJG4Ug6bYxE/93KWCzwZs1HV7gTDO87V szTEE519iyqoajLMsiea2Rk2gwoFyE3jXMECk69zpBYuLJ1ooWojZO/c0Jac4RpscUBr 9iqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ed3tfUDy0PesAaobPtQ3BXGUB495/TZW6laQkFKoabs=; b=LA1S80GW+L/Bg+5MYoegwcoQs9s4wbrZV2L5FQB5f3HQLNTUQ7u28+HsvI8KQPWUZ4 5gGMZA/0SPvfFv/WCKbvm04/HPX0nxt6jlNZMa7797gmzufxhlLFSQOWm+1cj1f1/Oku PAynHMBF13f7UdyBMvcffOypr/3p+iS0IMWJIdbBGlYmjjmOB/nm8iIHPpOyADR3ESQe pN8h6aiORRhhg4NoeTXEUpuBxfR6C1DLz2Er4bMDuVIfq6ddvy7xo6Waqwphzyi18ZfJ UL2GfGZZuGbd1IPzXFGCqzX4ZLzY+xPfKUaA2WbgH2wUEmjbBA2HE0BiHioIoxaCF8JL V+LA== X-Gm-Message-State: AOAM530X5Gh0apRPVJnNAPeutX8CyNdB2e7xvSmdToXWrI1PkqCh9xRd Sf0r80I1T2y8hWYUSmtfP3HXwQ== X-Google-Smtp-Source: ABdhPJyde7yebterc+4Mi3C8TxjBmNz6nlVyOMhieN/q0ZnXNIN5EZsn6XCmzEM/ctcw9j4bV2vmog== X-Received: by 2002:a17:90a:f181:: with SMTP id bv1mr1468286pjb.57.1611873724671; Thu, 28 Jan 2021 14:42:04 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 12/23] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Date: Thu, 28 Jan 2021 12:41:30 -1000 Message-Id: <20210128224141.638790-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:18 -0000 This is the prctl bit that controls whether syscalls accept tagged addresses. See Documentation/arm64/tagged-address-abi.rst in the linux kernel. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 4 ++++ target/arm/cpu-param.h | 3 +++ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++ linux-user/syscall.c | 24 ++++++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 3194e6b009..820601dfcc 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -30,4 +30,8 @@ struct target_pt_regs { # define TARGET_PR_PAC_APDBKEY (1 << 3) # define TARGET_PR_PAC_APGAKEY (1 << 4) +#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 +#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 +# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 00e7d9e937..7f38d33b8e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -20,6 +20,9 @@ #ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +# ifdef TARGET_AARCH64 +# define TARGET_TAGGED_ADDRESSES +# endif #else /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df0d677833..0db6e65467 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,6 +721,11 @@ typedef struct CPUARMState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + +#ifdef TARGET_TAGGED_ADDRESSES + /* Linux syscall tagged address support */ + bool tagged_addr_enable; +#endif } CPUARMState; static inline void set_feature(CPUARMState *env, int feature) @@ -3601,6 +3606,32 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) */ #define PAGE_BTI PAGE_TARGET_1 +#ifdef TARGET_TAGGED_ADDRESSES +/** + * cpu_untagged_addr: + * @cs: CPU context + * @x: tagged address + * + * Remove any address tag from @x. This is explicitly related to the + * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. + * + * There should be a better place to put this, but we need this in + * include/exec/cpu_ldst.h, and not some place linux-user specific. + */ +static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) +{ + ARMCPU *cpu = ARM_CPU(cs); + if (cpu->env.tagged_addr_enable) { + /* + * TBI is enabled for userspace but not kernelspace addresses. + * Only clear the tag if bit 55 is clear. + */ + x &= sextract64(x, 0, 56); + } + return x; +} +#endif + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 6001022e96..46526f50b0 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10963,6 +10963,30 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, } } return -TARGET_EINVAL; + case TARGET_PR_SET_TAGGED_ADDR_CTRL: + { + abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; + CPUARMState *env = cpu_env; + + if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE; + return 0; + } + case TARGET_PR_GET_TAGGED_ADDR_CTRL: + { + abi_long ret = 0; + CPUARMState *env = cpu_env; + + if (arg2 || arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (env->tagged_addr_enable) { + ret |= TARGET_PR_TAGGED_ADDR_ENABLE; + } + return ret; + } #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzf-0005lx-KM for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzY-0005cc-CT for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:24 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:43019) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzM-0008A9-17 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:20 -0500 Received: by mail-pg1-x532.google.com with SMTP id n10so5269306pgl.10 for ; Thu, 28 Jan 2021 14:42:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3ZJGnXzF/NMDb1ycGSuuM5DTXpfVPEQ3f0lC4BF0AxI=; b=pbRkK3IaVOuCPYjmdn+qbJWZnZgI2Vlttcs3pu6ylmrf1y/64VpXi4t4gaEQM24GvZ UdMXOjgPcTYCt+LFPBIJ/4yrufITKEwp0RGkyumSrwa/YFiua2QBX/oEnd7c81LyvdWv W2Z8weYXAGOtMABscklC8UtbqUXw2EzANfMpKkcMtgwJS4CkstXyt0cThA9fEXnRVFWw BdMrz3EmnXIKlccxWr4/PxU+dcp5gYWfYzAI16D5WDpe5tRhhwNMZn/Tx3F9aBc0c0ls QEWFLldga2q4QtMkVVL29PB799q0io14N86sLuffUu20kvkN0yI4Cool7DzVvB0Pu9EL 7Krw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3ZJGnXzF/NMDb1ycGSuuM5DTXpfVPEQ3f0lC4BF0AxI=; b=guzI6fbXCt0v5C4fPTj11EsdCE1PIojwUu0+coW/aaU+pfXKksNm7SAqZ9ZioOBghd imudb6XC9b/Yfg6HB5Tr5x4z9pa+Q7mZosX7G287n6vHepdgenX85Oee9vfZ/W1quyx2 aQtKuZWyV9Xwpz9qsirzX3xHezaIRm5qIumPxgDbAFQCwc1cnJufWP9JcCGrcoBIYfqf GsmO3McMSZL5Fs9IKh/DPA0SrGqM97241C1l2m/gqdnfjfg6puNE134bHdxYCWmcglPf 815SBfN9PhMMFTspbzLJBlHUVJPBSCtZL+aQ4H8cr0iflWWuFfKNPaU6ab60aOEEwt9C oltg== X-Gm-Message-State: AOAM532fUOSsYZF2DSxLzMjTyqkTmMr11hLrjVd8duNTTGWghCLU/vKR mQV96n55cVO3rrC/Juc2G0WIlQ== X-Google-Smtp-Source: ABdhPJwWbvaAdkhaD+Z/Pg1aN8jbMqy8bUivAxx8cppd4NYOsAqKZ6VJAA8c9go2Civ1HOkpo9bJOQ== X-Received: by 2002:a63:1865:: with SMTP id 37mr1595347pgy.206.1611873726197; Thu, 28 Jan 2021 14:42:06 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 13/23] target/arm: Improve gen_top_byte_ignore Date: Thu, 28 Jan 2021 12:41:31 -1000 Message-Id: <20210128224141.638790-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:24 -0000 Use simple arithmetic instead of a conditional move when tbi0 != tbi1. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ffc060e5d7..3ec0dc17d8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -183,17 +183,20 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, /* Sign-extend from bit 55. */ tcg_gen_sextract_i64(dst, src, 0, 56); - if (tbi != 3) { - TCGv_i64 tcg_zero = tcg_const_i64(0); - - /* - * The two TBI bits differ. - * If tbi0, then !tbi1: only use the extension if positive. - * if !tbi0, then tbi1: only use the extension if negative. - */ - tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, - dst, dst, tcg_zero, dst, src); - tcg_temp_free_i64(tcg_zero); + switch (tbi) { + case 1: + /* tbi0 but !tbi1: only use the extension if positive */ + tcg_gen_and_i64(dst, dst, src); + break; + case 2: + /* !tbi0 but tbi1: only use the extension if negative */ + tcg_gen_or_i64(dst, dst, src); + break; + case 3: + /* tbi0 and tbi1: always use the extension */ + break; + default: + g_assert_not_reached(); } } } -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzg-0005nk-7y for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5FzV-0005bB-Q8 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:18 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:42115) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzH-000898-R7 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:17 -0500 Received: by mail-pl1-x631.google.com with SMTP id s15so4166735plr.9 for ; Thu, 28 Jan 2021 14:42:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XRNC7TN62/mhJ44h4TxsBn3p8qzX1+L1EKv8lKpxGuM=; b=vblZAsOEFd82DGYDOVgYbHn0mioP2LeWtRtyFGs/MRXk8Nth5Y3ZGqgUJ92pJkjLgS vER9jA1vigrP+IkeDmO7lndLQc5oVMQbOj7w2OSJkckTrK3PV6Rb7Dg+ARBzrgU3LMld de7FT484SRvm4vGGUCTFjAamPeHgsXoaf72TOE481v/kAJIRv8S7dXskl10kJmuafyeq Cqv+iPTHYb6WPE1W0UOBp+aLj3leOnJ4owhvpoiodhO5r6ruAzDgDsC8hU7rnHWNXQ1/ Q+57NHLDo1GIZjSMiErfJwGpxRuuMvwEvfoV4GgFRu87P0oXsAj6XRZpW5HVDYKzCwc/ Hthg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XRNC7TN62/mhJ44h4TxsBn3p8qzX1+L1EKv8lKpxGuM=; b=cK43PX2Njyz8QvSuz0cWu3EW+wtPd0RSG2SsYlaoBCnpOKxFSyFWd40tUv44KdGSth 2TpdprdUIIxRQZyIKEgZBPbE+TtZ1u4njZDtijrSNeMAI7jhkT945xgOgGdmldXDxN7S 9xnpsC7qsgORiPVQ2yt8YQgZ8CGXmDRxkadoWKLX6uhHuEcrgyiFii8vfykN9smyfWxz 1hLdfk922wB57P9khFiam0RzIfrHn8t3QdbuipuQANIwlt8y/SBtQldRtrKNCbMzYsdL bu/hoQjUUMVVZvBoqfS48bEyeYWxnWm5OTpJxdIKxuauHjgqi1D6JAJzwrmN6ZMlIx7n P8ig== X-Gm-Message-State: AOAM533YwdrCFoxItN+5LFa8Ib3oLdN6YpU4cDAmjNKmGGryUI25lhOp u/sptWCGhKxQdL9nDb/aj2FHlz8KMa4G946j X-Google-Smtp-Source: ABdhPJyxedohV9pkYYBJldole0kJTRHzkVUkCrydk1cK9jVB4La+8zw5cXIyPCv53IzsjVT+N9uADQ== X-Received: by 2002:a17:90a:7e2:: with SMTP id m89mr1522901pjm.2.1611873721204; Thu, 28 Jan 2021 14:42:01 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 10/23] linux-user: Fix guest_addr_valid vs reserved_va Date: Thu, 28 Jan 2021 12:41:28 -1000 Message-Id: <20210128224141.638790-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:18 -0000 We must always use GUEST_ADDR_MAX, because even 32-bit hosts can use -R to restrict the memory address of the guest. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 4e6ef3d542..e62f4fba00 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,11 +72,10 @@ typedef uint64_t abi_ptr; /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ #define g2h(x) ((void *)((uintptr_t)(abi_ptr)(x) + guest_base)) -#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS -#define guest_addr_valid(x) (1) -#else -#define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX) -#endif +static inline bool guest_addr_valid(abi_ulong x) +{ + return x <= GUEST_ADDR_MAX; +} static inline bool guest_range_valid(abi_ulong start, abi_ulong len) { -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzg-0005p1-P6 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzd-0005h3-QD for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:25 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:36618) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzP-0008AS-5g for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:25 -0500 Received: by mail-pg1-x52f.google.com with SMTP id c132so5287379pga.3 for ; Thu, 28 Jan 2021 14:42:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QgNyelKt2GngvKbsoMDpo4CJhyrMaW41bQD6ElDWNXc=; b=IySlJ/+gM72ylDP0saKIP+vk9AVwNxn1CW9eAahP6Co3EiWHHZwhDyHM6aJRuIkXL5 8hE7YwhvnJrPXn+dcqgf1uM4qKQE/H/qMQj0DSi7XXw78TLH4KYkQnTKIMgoRFy4xnTC CLBcfyEnhSq2KrltiI9YXpmW+tDWvDgAtyjlcHMsmt7lGnu5drfBb7tWE9SjQmsS28io GjnO17yTW51DAkBkVpxH8Y/UdPE0SYgwlcbJRnkUNCLwg0K2sLlGeztIaa+iYMvTxAu7 joPgdA1kAAfyXmvS31fURzoVK4moiWLpoUbWTkPMOojp35DVdlxSy//v6ijuHR/AJV4B vHcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QgNyelKt2GngvKbsoMDpo4CJhyrMaW41bQD6ElDWNXc=; b=ZHkyadh2cgVnacaxkua5jaxtSpiYcL5PTbIGR9aeFpkZA6vVCA+6Ji5V5Fz8eevGaf FbHXJS7I0DNBE2qR500DGYm8YLzOyJstkmF54gvto4hjIWt+wS3qG18ZvqzsoiZEO2me WwRlL8Ub+JBwfeEoGyIyPUcXUr1/YWliuRy9DSWtuZ1YssmsVthZOuKrrsG71W7mP/Wy HBnW+56qhB6JJz1lIaB/sC5vlcTtyeVf5CumlIjr8Va97bjmBW1f6SJtcPRTVPBTqUlG ilu7B0lvx9JSnfTelWNgjP9qxkQPhCoDHDEb2bFo3TX2GD5KnINgVRNcBmOCVDyyxtTL yT4g== X-Gm-Message-State: AOAM53102EUgO8rmbUivnesEglG/ROVODPvhTS5sdMwFK2qsZ0QqntMj IX0eJ2FPgMedWyi6MOL57RTciw== X-Google-Smtp-Source: ABdhPJzKLL+UPLQSAH9mmrq836tG8OrwZV+818yELjwKHYFc3r3B00e4GhfSJlwL/mK1UucYpCPYJQ== X-Received: by 2002:aa7:9d0c:0:b029:1bd:1e1f:8885 with SMTP id k12-20020aa79d0c0000b02901bd1e1f8885mr1469801pfp.48.1611873727910; Thu, 28 Jan 2021 14:42:07 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 14/23] target/arm: Use the proper TBI settings for linux-user Date: Thu, 28 Jan 2021 12:41:32 -1000 Message-Id: <20210128224141.638790-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:26 -0000 We were fudging TBI1 enabled to speed up the generated code. Now that we've improved the code generation, remove this. Also, tidy the comment to reflect the current code. The pauth test was testing a kernel address (-1) and making incorrect assumptions about TBI1; stick to userland addresses. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/cpu.c | 10 +++------- tests/tcg/aarch64/pauth-2.c | 1 - 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 853fa88fd6..6efe0c303e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1413,9 +1413,9 @@ static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) */ static inline uint64_t useronly_clean_ptr(uint64_t ptr) { - /* TBI is known to be enabled. */ #ifdef CONFIG_USER_ONLY - ptr = sextract64(ptr, 0, 56); + /* TBI0 is known to be enabled, while TBI1 is disabled. */ + ptr &= sextract64(ptr, 0, 56); #endif return ptr; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141..db81a12418 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -200,14 +200,10 @@ static void arm_cpu_reset(DeviceState *dev) env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); } /* - * Enable TBI0 and TBI1. While the real kernel only enables TBI0, - * turning on both here will produce smaller code and otherwise - * make no difference to the user-level emulation. - * - * In sve_probe_page, we assume that this is set. - * Do not modify this without other changes. + * Enable TBI0 but not TBI1. + * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index 9bba0beb63..978652ede3 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -53,7 +53,6 @@ void do_test(uint64_t value) int main() { do_test(0); - do_test(-1); do_test(0xda004acedeadbeefull); return 0; } -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzh-0005rV-K2 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzf-0005l4-73 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:27 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:36623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzS-0008Bb-0G for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:26 -0500 Received: by mail-pg1-x534.google.com with SMTP id c132so5287459pga.3 for ; Thu, 28 Jan 2021 14:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i1r8pB7pD9EIFwj0J5T7PSXbPTyHStDyxJkV5qjF0ns=; b=JSl5oohobKCmwXuxdrPAPGWF3e3/rAKBAqDiFTE+OK1KAjHYd0nsa/eijA6Gx26Wnc HM2fhxC5nvlKOFcG8L2mTdz63nZjZ7//llvTL4n0gDbchDyWL0YojKM8yUj/wub9oFss cbMmx/kkT+WJ1XSCJAVQAEzvFI7g/xQ+zJ44QNMszkqz2ii2a6UrVhR/2oFOdX0u+QmQ BQ63MywNnCZOzhgSMPA0UxU/uM9fxtPYQJXSz6nEmcB8BM02vJx5YK1RqtRQSyTby617 NHTSGfhD+7AW1mURJEbEauedJ0VsoN80zPeoejNa0l4PwylR/eorNEuTopD59sR3ExAN +pOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i1r8pB7pD9EIFwj0J5T7PSXbPTyHStDyxJkV5qjF0ns=; b=Gx5rUoauL9c5e4vA+YtAud/emKGIpyX+UODgGl43FHmFpetWiKuXZay4+7mHHsIGlP 2EPNJhm06FUfHcF7T0oEsGpl3cMZeWTXTGjOf5ZA2yFacvbEoCOkuP9GepLZSkMDiVVo AxBfB5wqdn3+d3KedrDxeX4K7f94QzQ/wRjlZd0qrUnSlDOH5ZAeZPc5f7lzqFBJotgX Y8gfeAGXc8wD3yLSCRkiG1jBI4HxxhoG5y1spo8ZWU2+qS+kzZzCKnEiNwzAQOlk3+4Q qiys0ZcxOmmKQ3mtHZ0vpzgvxw3MhSvz6pE5CbiqjQ0DHVDPZoCCLFhapqh4y2jTs9ZJ 0cfA== X-Gm-Message-State: AOAM532r7sJ0gmlaHsO2mURVvxw5rKS3mhJTeyWC8BfQiyB6Vn5GooN3 TKlBhwinDDWoxrCYPXb3gWDxvsYigAO2V6Mn X-Google-Smtp-Source: ABdhPJzVBymBvGRDJOydMuHtaUy3ACHZNDdMFaeAAkikvbF3wT2ECNThBagMm2ZUPHFHOesfTiyo7w== X-Received: by 2002:a62:7f12:0:b029:1bd:d6e7:e2ba with SMTP id a18-20020a627f120000b02901bdd6e7e2bamr1605393pfd.65.1611873731204; Thu, 28 Jan 2021 14:42:11 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 16/23] linux-user/aarch64: Implement PROT_MTE Date: Thu, 28 Jan 2021 12:41:34 -1000 Message-Id: <20210128224141.638790-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:27 -0000 Remember the PROT_MTE bit as PAGE_MTE/PAGE_TARGET_2. Otherwise this does not yet have effect. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Do not overlap PAGE_TARGET_2 with PAGE_RESERVED. --- include/exec/cpu-all.h | 1 + linux-user/syscall_defs.h | 1 + target/arm/cpu.h | 1 + linux-user/mmap.c | 22 ++++++++++++++-------- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c52180e8e6..b2a72f70ec 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -284,6 +284,7 @@ extern intptr_t qemu_host_page_mask; #endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0080 +#define PAGE_TARGET_2 0x0200 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index f98c1c1c8d..46a960fccb 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1311,6 +1311,7 @@ struct target_winsize { #ifdef TARGET_AARCH64 #define TARGET_PROT_BTI 0x10 +#define TARGET_PROT_MTE 0x20 #endif /* Common */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0db6e65467..7a79dde6f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3605,6 +3605,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) * AArch64 usage of the PAGE_TARGET_* bits for linux-user. */ #define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 7fb4c628e1..34bd114f97 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -84,18 +84,24 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) | (prot & PROT_EXEC ? PROT_READ : 0); #ifdef TARGET_AARCH64 - /* - * The PROT_BTI bit is only accepted if the cpu supports the feature. - * Since this is the unusual case, don't bother checking unless - * the bit has been requested. If set and valid, record the bit - * within QEMU's page_flags. - */ - if (prot & TARGET_PROT_BTI) { + { ARMCPU *cpu = ARM_CPU(thread_cpu); - if (cpu_isar_feature(aa64_bti, cpu)) { + + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if ((prot & TARGET_PROT_BTI) && cpu_isar_feature(aa64_bti, cpu)) { valid |= TARGET_PROT_BTI; page_flags |= PAGE_BTI; } + /* Similarly for the PROT_MTE bit. */ + if ((prot & TARGET_PROT_MTE) && cpu_isar_feature(aa64_mte, cpu)) { + valid |= TARGET_PROT_MTE; + page_flags |= PAGE_MTE; + } } #endif -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzk-00060A-PJ for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzi-0005tm-Hc for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:30 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:35858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzT-0008D2-VS for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:30 -0500 Received: by mail-pl1-x633.google.com with SMTP id e9so4181481plh.3 for ; Thu, 28 Jan 2021 14:42:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wwvKJTzKdnYj9oOM3633KBBYzXxSt9lSc02L89Z+ers=; b=khozQ29PPFCHefYejhG2vCblf0hXQozIw4y0A1NL0fVE7fYzuL0xEm6PguNlMV0Urf qP19wZ+GhbigbEOIe1t1u64MIzfIWEzJAIchwbmlUWJpHfzSLK7J92n9cI9tXiviN8KB /FmvQEhQRCAcETLrdPA8N2qz7VUGNI4JLzpdM+Pr7syLXfATZ/Gath0hg6lGszW5p7uY YOlqzVyCihl79kDJSxhziRuMlqLEBAjXwV7s3B54v2Pb6hv9Pfnh7RH0hwSp1b9mpptJ jU2pI0BPJyKeoF+wqsGrTRs9sfXCNQ1R1doq+NQ0SMv0AOtXHuGd72NYps2qAhJMBrsI xyIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wwvKJTzKdnYj9oOM3633KBBYzXxSt9lSc02L89Z+ers=; b=n3LsQJqsJy4nXWM2sLkn7YRpxNcLjKRiFsIyL586cvJi1EsietCPmPFJR2OFIwl+TA UDFymDNrTcR48JKX2RvkP2ODN9GEzbbLMwIwp7ne6Qt070ek56Q3WB2TtPjhgFNBgR+g E/MVtZuG0Onk+Oprd4FVGG+wJxN/cBnC5/FuHVZy3OXieY2BUyqcagOKr8ChQf36cOsQ V7V+SlbIuW5Sx0PQyWUtcfcWBMPNOkpFDxqpWqY5nEG2/8QHoS2EPJr5+Sdg1UXl5rY/ mcGTN6kGqaJdm3bHzAFRMBvw6VeWKsVFeqhsUQeztdvBSpt/WbYklsSSw+AyznIwQF28 TLMQ== X-Gm-Message-State: AOAM531iU1R6qQ7WLD+5aFzv1XvaLh0KBBYpvuvrvmbU2rpoWUIotX4t vTsJXDXDUzuX0NsilT9dioMZBA== X-Google-Smtp-Source: ABdhPJy9Hz4E1DU24UjAwg2qX5XLdYbnyfAVVTVqAe3dXbTCI3hHtHJECciAFdK7yBB4OPjU4y8Yug== X-Received: by 2002:a17:902:9007:b029:df:f347:3cc3 with SMTP id a7-20020a1709029007b02900dff3473cc3mr1500700plp.41.1611873734393; Thu, 28 Jan 2021 14:42:14 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 18/23] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Date: Thu, 28 Jan 2021 12:41:36 -1000 Message-Id: <20210128224141.638790-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:31 -0000 A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Signed-off-by: Richard Henderson --- v3: Use syndrome.h, arm_deliver_fault. --- linux-user/aarch64/cpu_loop.c | 24 +++++++++++++++++++++--- target/arm/tlb_helper.c | 15 +++++++++------ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 42b9c15f53..4e43906e66 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "qemu/guest-random.h" #include "hw/semihosting/common-semi.h" +#include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -76,7 +77,7 @@ void cpu_loop(CPUARMState *env) { CPUState *cs = env_cpu(env); - int trapnr; + int trapnr, ec, fsc; abi_long ret; target_siginfo_t info; @@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env) case EXCP_DATA_ABORT: info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; - /* XXX: check env->error_code */ - info.si_code = TARGET_SEGV_MAPERR; info._sifields._sigfault._addr = env->exception.vaddress; + + /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ + ec = syn_get_ec(env->exception.syndrome); + assert(ec == EC_DATAABORT || ec == EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + info.si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + info.si_code = TARGET_SEGV_ACCERR; + break; + default: + g_assert_not_reached(); + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index df85079d9f..9609333cbd 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; #ifdef CONFIG_USER_ONLY - cpu->env.exception.vaddress = address; - if (access_type == MMU_INST_FETCH) { - cs->exception_index = EXCP_PREFETCH_ABORT; + int flags = page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type = ARMFault_Permission; } else { - cs->exception_index = EXCP_DATA_ABORT; + fi.type = ARMFault_Translation; } - cpu_loop_exit_restore(cs, retaddr); + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); #else hwaddr phys_addr; target_ulong page_size; int prot, ret; MemTxAttrs attrs = {}; - ARMMMUFaultInfo fi = {}; ARMCacheAttrs cacheattrs = {}; /* -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzm-00065w-Tx for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzl-000613-4B for qemu-arm@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 21/23] target/arm: Add allocation tag storage for user mode Date: Thu, 28 Jan 2021 12:41:39 -1000 Message-Id: <20210128224141.638790-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:33 -0000 Use the now-saved PAGE_ANON and PAGE_MTE bits, and the per-page saved data. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d55f8d1e1e..1c569336ea 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, int tag_size, uintptr_t ra) { #ifdef CONFIG_USER_ONLY - /* Tag storage not implemented. */ - return NULL; + uint64_t clean_ptr = useronly_clean_ptr(ptr); + int flags = page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; #else uintptr_t index; CPUIOTLBEntry *iotlbentry; -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzo-00068j-2r for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fze-0005k8-RU for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:26 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:36622) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzP-0008BP-OQ for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:26 -0500 Received: by mail-pg1-x533.google.com with SMTP id c132so5287419pga.3 for ; Thu, 28 Jan 2021 14:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5bvrCnDcElA75br2YmmksQwg8lUlxPa22qY4Fj6h+lg=; b=M0SbjigOnaVcix0YSJ9WpeivyMKfPUPSwXYyLXDBI4l6ARdj1qYWsQgn23n8/xgCkl EhW/1W58NUhWiKOLTavHBp5kplKDyi6rN+mozKwK3teETJ/andTw5UMaJuQn424lcFBa Whyj98QH2XRPMoYRKOscRyvzXK8HZPG/HJTEhgFbZVLhXosP0QhuChjL1Ze2b83CUafa HgSNRZn85T9mPtHrFtnsm6zUWDD/00HJQp4Oy7ezq16zihRJkvVO1pjgBpiQKdsBO6S1 UzUgyaifN74wizJ83ZSX4OQ+SKYCqoaLNdg5J6TSkGyyeXhRWvEQRi38yNfDSjANJ/UT wdQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5bvrCnDcElA75br2YmmksQwg8lUlxPa22qY4Fj6h+lg=; b=nsVYuG7vbhqla7347f5jJBtbNHrKxExX3YO2HGqEubl2+bE07m7QEJCRhy62aL/7d8 wmqxa07/fI70o75DDmF5SOCw143sg3KlKk8vKxVf/uOrqREMuwBswjwyzHZ8EFhpgSl+ 6OLjoYOjXDEWJDzGpEIW978SFu5xAyUBZCWYe/piWhFRh57x9haac2bDTQU9BZy4HedL SVKbkJbmzFGuqHwIA15m5MTtAE6m9zIyGPahw5QEKKC2DtW8VY1Rpf8pJurL+xLfZBBp DKUtOHbDTRCbi4K3syOAkJP21UmdowAHqwcBiJDptLb4xrmQhxIuEG2iKzsQabNHmTxO 1c1w== X-Gm-Message-State: AOAM532ltBXLHnCzMkXQZFLn37pOPFbxH3o6pxKTmOT1qL2uwBrgZHtb 7N3lIKCbev3Bk1vwDfHmTz+4Pfr5mSfpIsGn X-Google-Smtp-Source: ABdhPJx4MFmz2+5p+HE7YmUw9COPUHRFMgyvXkUW3yXsxyggLdLhrkbC8SQOQdTElGPdLPwEfR0Gjw== X-Received: by 2002:a63:c441:: with SMTP id m1mr1512364pgg.353.1611873729575; Thu, 28 Jan 2021 14:42:09 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 15/23] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Date: Thu, 28 Jan 2021 12:41:33 -1000 Message-Id: <20210128224141.638790-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:27 -0000 These prctl fields are required for the function of MTE. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 9 ++++++ linux-user/syscall.c | 43 +++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 820601dfcc..76f6c3391d 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -33,5 +33,14 @@ struct target_pt_regs { #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) +/* MTE tag check fault modes */ +# define TARGET_PR_MTE_TCF_SHIFT 1 +# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) +# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) +/* MTE tag inclusion mask */ +# define TARGET_PR_MTE_TAG_SHIFT 3 +# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 46526f50b0..d645eb8f44 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10967,17 +10967,53 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); + + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= TARGET_PR_MTE_TCF_MASK; + valid_mask |= TARGET_PR_MTE_TAG_MASK; + } if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) { return -TARGET_EINVAL; } env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE; + + if (cpu_isar_feature(aa64_mte, cpu)) { + switch (arg2 & TARGET_PR_MTE_TCF_MASK) { + case TARGET_PR_MTE_TCF_NONE: + case TARGET_PR_MTE_TCF_SYNC: + case TARGET_PR_MTE_TCF_ASYNC: + break; + default: + return -EINVAL; + } + + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * Note that the syscall values are consistent with hw. + */ + env->cp15.sctlr_el[1] = + deposit64(env->cp15.sctlr_el[1], 38, 2, + arg2 >> TARGET_PR_MTE_TCF_SHIFT); + + /* + * Write PR_MTE_TAG to GCR_EL1[Exclude]. + * Note that the syscall uses an include mask, + * and hardware uses an exclude mask -- invert. + */ + env->cp15.gcr_el1 = + deposit64(env->cp15.gcr_el1, 0, 16, + ~arg2 >> TARGET_PR_MTE_TAG_SHIFT); + arm_rebuild_hflags(env); + } return 0; } case TARGET_PR_GET_TAGGED_ADDR_CTRL: { abi_long ret = 0; CPUARMState *env = cpu_env; + ARMCPU *cpu = env_archcpu(env); if (arg2 || arg3 || arg4 || arg5) { return -TARGET_EINVAL; @@ -10985,6 +11021,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, if (env->tagged_addr_enable) { ret |= TARGET_PR_TAGGED_ADDR_ENABLE; } + if (cpu_isar_feature(aa64_mte, cpu)) { + /* See above. */ + ret |= (extract64(env->cp15.sctlr_el[1], 38, 2) + << TARGET_PR_MTE_TCF_SHIFT); + ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16, + ~env->cp15.gcr_el1); + } return ret; } #endif /* AARCH64 */ -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzo-00069X-HB for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzh-0005sG-TV for qemu-arm@nongnu.org; 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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 19/23] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault Date: Thu, 28 Jan 2021 12:41:37 -1000 Message-Id: <20210128224141.638790-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:30 -0000 Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 2 ++ linux-user/aarch64/cpu_loop.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index ddd73169f0..777fb667fe 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,5 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ + #define TARGET_ARCH_HAS_SETUP_FRAME #endif /* AARCH64_TARGET_SIGNAL_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 4e43906e66..b6a2e65593 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -134,6 +134,9 @@ void cpu_loop(CPUARMState *env) case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ info.si_code = TARGET_SEGV_ACCERR; break; + case 0x11: /* Synchronous Tag Check Fault */ + info.si_code = TARGET_SEGV_MTESERR; + break; default: g_assert_not_reached(); } -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzo-0006An-W1 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzj-0005vQ-9m for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:31 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:39357) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzX-0008EO-La for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:30 -0500 Received: by mail-pg1-x532.google.com with SMTP id o63so5270628pgo.6 for ; Thu, 28 Jan 2021 14:42:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j34etXVQZzqqkkDQF4UCutDcHqFcrqbhKldr7JT3Nmk=; b=mKXxstFiDWv5XglClKNXc3avHws3W7vvEy0pq/qksBqkMgKnqQh4abpDjGT/Q4EnzI kedzqZB0H6eWrsv4OpgHMMwy+XLK2MtrOhoIXJhgI+CLNjIaognILbgDT4uuyKeKCiI2 0kxckyiOGwvuoQC4PNspD4VTFx2IX9cquudXu2+zwkDkJ79qXHDXha+p1dSrYW6WNWm8 Y+0kTLPW9UeULwKyaL4QYLXhnADhhKDoeEUTdL26Eg+p/1hZR3kaBcZ8kD8FvQRYnGv7 s6a+aPAuYQY/FvD7ddXBFIjb07S1uD5U73VJQJqhry0Z16RMahGHQ4zCBaaA2Q6KxOsJ X8vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j34etXVQZzqqkkDQF4UCutDcHqFcrqbhKldr7JT3Nmk=; b=thEwkpFt54CCSeYCr+obnJ+rn2Ui7nHgEuuKDUX1+1yj4qVF2c9CfpaneTS4LTBubF qkEij3OWGOW+6WXNpuTwfAHDNdSWcWGvLIseQvu6Q1yHIjauVfiQWmfMHS7c9VVyf8Zx tRdUnq0vd7a4ueOIJ3i8k2grD8WGURN+sHkmM+ymtv+bapiOYU9kTai4nuFVLGzi8Qhl YXXZX9NI1P9HMTbRx8v+Cu/z8P60E09WdqP3+KzCJs8dICgn9CjL4hIIp0RPNpRMRSoh a4rcYi533KprEIFVAOGvQW+RIG1cP1XXCerHMcqObvmuGKe9qK682VayfQ+kdQBsbXBM ItBQ== X-Gm-Message-State: AOAM533jpVXaYNCdPwLOtH1P95KG5UuEuWYOLfGjUvYlTBAMezqHPOsn g4NIiKho3xw0Ky0cIkHZACW3cA== X-Google-Smtp-Source: ABdhPJwd9nNYm3DYd2Byuks3HjREQg2YTgz8quYZtUj1OzWjdDyKYalZO2iksIomwRXuD1Ru4pNd6g== X-Received: by 2002:a65:56cb:: with SMTP id w11mr1696082pgs.88.1611873737546; Thu, 28 Jan 2021 14:42:17 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 20/23] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Date: Thu, 28 Jan 2021 12:41:38 -1000 Message-Id: <20210128224141.638790-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:31 -0000 The real kernel collects _TIF_MTE_ASYNC_FAULT into the current thread's state on any kernel entry (interrupt, exception etc), and then delivers the signal in advance of resuming the thread. This means that while the signal won't be delivered immediately, it will not be delayed forever -- at minimum it will be delivered after the next clock interrupt. We don't have a clock interrupt in linux-user, so we issue a cpu_kick to signal a return to the main loop at the end of the current TB. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 11 +++++++++++ target/arm/mte_helper.c | 10 ++++++++++ 3 files changed, 22 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h index 777fb667fe..18013e1b23 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -21,6 +21,7 @@ typedef struct target_sigaltstack { #include "../generic/signal.h" +#define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ #define TARGET_ARCH_HAS_SETUP_FRAME diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index b6a2e65593..7c42f65706 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -164,6 +164,17 @@ void cpu_loop(CPUARMState *env) EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); abort(); } + + /* Check for MTE asynchronous faults */ + if (unlikely(env->cp15.tfsr_el[0])) { + env->cp15.tfsr_el[0] = 0; + info.si_signo = TARGET_SIGSEGV; + info.si_errno = 0; + info._sifields._sigfault._addr = 0; + info.si_code = TARGET_SEGV_MTEAERR; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + process_pending_signals(env); /* Exception return on AArch64 always clears the exclusive monitor, * so any return to running guest code implies this. diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 153bd1e9df..d55f8d1e1e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -565,6 +565,16 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, select = 0; } env->cp15.tfsr_el[el] |= 1 << select; +#ifdef CONFIG_USER_ONLY + /* + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, + * which then sends a SIGSEGV when the thread is next scheduled. + * This cpu will return to the main loop at the end of the TB, + * which is rather sooner than "normal". But the alternative + * is waiting until the next syscall. + */ + qemu_cpu_kick(env_cpu(env)); +#endif break; default: -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzp-0006BN-6a for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzk-00060e-VD for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:33 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:40926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fzc-0008Ev-8a for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:32 -0500 Received: by mail-pg1-x529.google.com with SMTP id b21so5277516pgk.7 for ; Thu, 28 Jan 2021 14:42:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J1HR7ri25V0SiyAVmlpxEOPAwd8z1s6dfRj86QGjtrs=; b=Rn78l5i/mDHGv+CnxSdJk8JezkCDFkg5sMXfhABcygQ14Tz899ENlvpQByYmRtDi+s OeVHdX+d8rqrvLDrj7N1GWEZ0XUXO7YmCnFsoYTF6PTVcYbqW7txGCNlvhk3ND6av5Sv mXF/w/2Zbq0796fxlaXPYS7+bzjyqrfl4528rZuwRIECV1IkfGDLfpW72pqkC167l6Hp bbCHg+b6golFUkCM8zogzJ8oXIUASv9nDitKgXOBAx93nm+jANMscBczgdJXwfNAijra nRI8eLa0eFkN+TyiLChFCt/sAgit25dN7Tk10CYcWtSKyq8xHLbvedJEQiT3KrIMsSaO m+EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J1HR7ri25V0SiyAVmlpxEOPAwd8z1s6dfRj86QGjtrs=; b=mFteRE01ue1be5h5mEaPIz2tVcbNQ8xt1E46m+R4vYsFuNSaUGxXQK2WijM95PCIKC IsCJy6r+9tAmg1S3oWMTLwLsBFp0O2OuhXLcwoV2hOtrLdpNubWmNuuxCGnt8HH/WwYs cFBCNqWyMa1+59MSfTfF/ND/sKzQfZ6wISaoV0TZIm77oyZB+krbazvqtv1kAgke1s4R gOk94MUzTisdwLsQK0qGKvDCLf21eI5R0ryCkAaqHg/KEeA/32ONB7MCOZ+GIDhpVVJX SlhJl6BFWNXk3fq/7ZIPcISUpd91fE03kaFx1G6F9EuuGf+fwXHBuXCkLZpUa+2isSPj unVQ== X-Gm-Message-State: AOAM532zJftr49n+R3blTVtqObPli4ZprrZtfUESk0WX+y7QmNg7GD+j 69s5+jeZLXL2aQZgMka1LyGAwg== X-Google-Smtp-Source: ABdhPJx14wqhLg8pZBq/f86TFSQveYEFtblIKxLEMQCgt6pABwZqCNqK1T8fQRRzvtGy5Fu5nKi07w== X-Received: by 2002:a63:d917:: with SMTP id r23mr1621705pgg.126.1611873740877; Thu, 28 Jan 2021 14:42:20 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 22/23] target/arm: Enable MTE for user-only Date: Thu, 28 Jan 2021 12:41:40 -1000 Message-Id: <20210128224141.638790-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:33 -0000 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index db81a12418..43933550c3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -204,6 +204,21 @@ static void arm_cpu_reset(DeviceState *dev) * Note that this must match useronly_clean_ptr. */ env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); + + /* Enable MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + /* Enable tag access, but leave TCF0 as No Effect (0). */ + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* + * Exclude all tags, so that tag 0 is always used. + * This corresponds to Linux current->thread.gcr_incl = 0. + * + * Set RRND, so that helper_irg() will generate a seed later. + * Here in cpu_reset(), the crypto subsystem has not yet been + * initialized. + */ + env->cp15.gcr_el1 = 0x1ffff; + } #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzp-0006Bx-CO for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzk-00060Q-U2 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:32 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:32871) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5FzS-0008Cd-Cr for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:32 -0500 Received: by mail-pj1-x102f.google.com with SMTP id lw17so5462202pjb.0 for ; Thu, 28 Jan 2021 14:42:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AeXHcPCSuE2/vQCK82nwTpWyz+X0ZLD3MidtG+7siVA=; b=a717VB5Nfo+sCD7qw7pe1yaga+15dxyAuNvvPFSYNmfXahxvRtZbp/2QFNET0ylWXV QteFtdyF42rqzWW2JHvEnRVl8622cxYRTuiF2l4p1rkYuWsGrngAqfpo/vxI8vdJgn+h PsoKWJoC+nYb6/d1i8r40dKhE7IP/cT/Sl9Btc8zOmAJLAuCl1G6u6WfRvW1EjqMPjK/ L0R1Rf0Rtz4wKvQMMjtTqmXUeAMCufnE8SUHNxsA2ybATiWJEH3E/88W71fz/6lADdkv SmDZfa+vG9ivlHE3flJnWbezqE4Wvsy8Ng6GpFJfsMqW+xvLGDkdIv2Y4rBHpTXcjRFM YHEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AeXHcPCSuE2/vQCK82nwTpWyz+X0ZLD3MidtG+7siVA=; b=WAThxA3jOwe4ZvcA9VRkdTTu5QM2/JxGUSi34S4FNWiRrm8MOhpo7tub9VQez4vzoV T9BllKIO05Q1UihLzvynehA+Od4TVLka4fEer31FDLMxGDOXU3cP+JeImCBYkpjjZXuZ o81lOMFqkAoD+P4QhNy0iUg73CujNM4J06eBXz45sik7dVRH8M5+ddAJZVBHaW5CZN6c 5Tc794YkKCYLpJiHlS2Luu0kOyf/E6RGfN9/hJq/cbBxfjt5YqjVVACw7xvBW9LlREzL MQCIMX1OnJauaxnF1ddwzmZvHUsjHWmMHjhe4le1MutUtHuTvZb5RqOoBgqXA33InNgT Y1bQ== X-Gm-Message-State: AOAM530tTYAd6vehtsJnk4UTeeE4RHPjlFsy6nGdqPAhSfyv0UObiNjD yV1QLW7Sg5BDQURN8AKVNM255A== X-Google-Smtp-Source: ABdhPJwT9FHCwhVYqzqrWKvVpxPimH3uci2b2eKlimrUa6W/4784JIMgXVpa16vBhbZS7I2eCG1y4g== X-Received: by 2002:a17:902:ed83:b029:de:84d2:9ce6 with SMTP id e3-20020a170902ed83b02900de84d29ce6mr1573168plj.4.1611873732821; Thu, 28 Jan 2021 14:42:12 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 17/23] target/arm: Split out syndrome.h from internals.h Date: Thu, 28 Jan 2021 12:41:35 -1000 Message-Id: <20210128224141.638790-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:33 -0000 Move everything related to syndromes to a new file, which can be shared with linux-user. Signed-off-by: Richard Henderson --- target/arm/internals.h | 245 +----------------------------------- target/arm/syndrome.h | 273 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 244 deletions(-) create mode 100644 target/arm/syndrome.h diff --git a/target/arm/internals.h b/target/arm/internals.h index 6efe0c303e..5a4a742eba 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -26,6 +26,7 @@ #define TARGET_ARM_INTERNALS_H #include "hw/registerfields.h" +#include "syndrome.h" /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -256,250 +257,6 @@ static inline bool extended_addresses_enabled(CPUARMState *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); } -/* Valid Syndrome Register EC field values */ -enum arm_exception_class { - EC_UNCATEGORIZED = 0x00, - EC_WFX_TRAP = 0x01, - EC_CP15RTTRAP = 0x03, - EC_CP15RRTTRAP = 0x04, - EC_CP14RTTRAP = 0x05, - EC_CP14DTTRAP = 0x06, - EC_ADVSIMDFPACCESSTRAP = 0x07, - EC_FPIDTRAP = 0x08, - EC_PACTRAP = 0x09, - EC_CP14RRTTRAP = 0x0c, - EC_BTITRAP = 0x0d, - EC_ILLEGALSTATE = 0x0e, - EC_AA32_SVC = 0x11, - EC_AA32_HVC = 0x12, - EC_AA32_SMC = 0x13, - EC_AA64_SVC = 0x15, - EC_AA64_HVC = 0x16, - EC_AA64_SMC = 0x17, - EC_SYSTEMREGISTERTRAP = 0x18, - EC_SVEACCESSTRAP = 0x19, - EC_INSNABORT = 0x20, - EC_INSNABORT_SAME_EL = 0x21, - EC_PCALIGNMENT = 0x22, - EC_DATAABORT = 0x24, - EC_DATAABORT_SAME_EL = 0x25, - EC_SPALIGNMENT = 0x26, - EC_AA32_FPTRAP = 0x28, - EC_AA64_FPTRAP = 0x2c, - EC_SERROR = 0x2f, - EC_BREAKPOINT = 0x30, - EC_BREAKPOINT_SAME_EL = 0x31, - EC_SOFTWARESTEP = 0x32, - EC_SOFTWARESTEP_SAME_EL = 0x33, - EC_WATCHPOINT = 0x34, - EC_WATCHPOINT_SAME_EL = 0x35, - EC_AA32_BKPT = 0x38, - EC_VECTORCATCH = 0x3a, - EC_AA64_BKPT = 0x3c, -}; - -#define ARM_EL_EC_SHIFT 26 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -static inline uint32_t syn_get_ec(uint32_t syn) -{ - return syn >> ARM_EL_EC_SHIFT; -} - -/* Utility functions for constructing various kinds of syndrome value. - * Note that in general we follow the AArch64 syndrome values; in a - * few cases the value in HSR for exceptions taken to AArch32 Hyp - * mode differs slightly, and we fix this up when populating HSR in - * arm_cpu_do_interrupt_aarch32_hyp(). - * The exception is FP/SIMD access traps -- these report extra information - * when taking an exception to AArch32. For those we include the extra coproc - * and TA fields, and mask them out when taking the exception to AArch64. - */ -static inline uint32_t syn_uncategorized(void) -{ - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_svc(uint32_t imm16) -{ - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_hvc(uint32_t imm16) -{ - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa64_smc(uint32_t imm16) -{ - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa32_hvc(uint32_t imm16) -{ - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_smc(void) -{ - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; -} - -static inline uint32_t syn_aa64_bkpt(uint32_t imm16) -{ - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); -} - -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) -{ - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); -} - -static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, - int crn, int crm, int rt, - int isread) -{ - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, - int crn, int crm, int rt, int isread, - bool is_16bit) -{ - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, - int rt, int rt2, int isread, - bool is_16bit) -{ - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; -} - -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; -} - -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) -{ - /* AArch32 SIMD trap: TA == 1 coproc == 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); -} - -static inline uint32_t syn_sve_access_trap(void) -{ - return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_pactrap(void) -{ - return EC_PACTRAP << ARM_EL_EC_SHIFT; -} - -static inline uint32_t syn_btitrap(int btype) -{ - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; -} - -static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) -{ - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; -} - -static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, - int ea, int cm, int s1ptw, - int wnr, int fsc) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; -} - -static inline uint32_t syn_data_abort_with_iss(int same_el, - int sas, int sse, int srt, - int sf, int ar, - int ea, int cm, int s1ptw, - int wnr, int fsc, - bool is_16bit) -{ - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; -} - -static inline uint32_t syn_swstep(int same_el, int isv, int ex) -{ - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; -} - -static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) -{ - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; -} - -static inline uint32_t syn_breakpoint(int same_el) -{ - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | 0x22; -} - -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) -{ - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; -} - /* Update a QEMU watchpoint based on the information the guest has set in the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h new file mode 100644 index 0000000000..39a31260f2 --- /dev/null +++ b/target/arm/syndrome.h @@ -0,0 +1,273 @@ +/* + * QEMU ARM CPU -- syndrome functions and types + * + * Copyright (c) 2014 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + * + * This header defines functions, types, etc which need to be shared + * between different source files within target/arm/ but which are + * private to it and not required by the rest of QEMU. + */ + +#ifndef TARGET_ARM_SYNDROME_H +#define TARGET_ARM_SYNDROME_H + +/* Valid Syndrome Register EC field values */ +enum arm_exception_class { + EC_UNCATEGORIZED = 0x00, + EC_WFX_TRAP = 0x01, + EC_CP15RTTRAP = 0x03, + EC_CP15RRTTRAP = 0x04, + EC_CP14RTTRAP = 0x05, + EC_CP14DTTRAP = 0x06, + EC_ADVSIMDFPACCESSTRAP = 0x07, + EC_FPIDTRAP = 0x08, + EC_PACTRAP = 0x09, + EC_CP14RRTTRAP = 0x0c, + EC_BTITRAP = 0x0d, + EC_ILLEGALSTATE = 0x0e, + EC_AA32_SVC = 0x11, + EC_AA32_HVC = 0x12, + EC_AA32_SMC = 0x13, + EC_AA64_SVC = 0x15, + EC_AA64_HVC = 0x16, + EC_AA64_SMC = 0x17, + EC_SYSTEMREGISTERTRAP = 0x18, + EC_SVEACCESSTRAP = 0x19, + EC_INSNABORT = 0x20, + EC_INSNABORT_SAME_EL = 0x21, + EC_PCALIGNMENT = 0x22, + EC_DATAABORT = 0x24, + EC_DATAABORT_SAME_EL = 0x25, + EC_SPALIGNMENT = 0x26, + EC_AA32_FPTRAP = 0x28, + EC_AA64_FPTRAP = 0x2c, + EC_SERROR = 0x2f, + EC_BREAKPOINT = 0x30, + EC_BREAKPOINT_SAME_EL = 0x31, + EC_SOFTWARESTEP = 0x32, + EC_SOFTWARESTEP_SAME_EL = 0x33, + EC_WATCHPOINT = 0x34, + EC_WATCHPOINT_SAME_EL = 0x35, + EC_AA32_BKPT = 0x38, + EC_VECTORCATCH = 0x3a, + EC_AA64_BKPT = 0x3c, +}; + +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +static inline uint32_t syn_get_ec(uint32_t syn) +{ + return syn >> ARM_EL_EC_SHIFT; +} + +/* + * Utility functions for constructing various kinds of syndrome value. + * Note that in general we follow the AArch64 syndrome values; in a + * few cases the value in HSR for exceptions taken to AArch32 Hyp + * mode differs slightly, and we fix this up when populating HSR in + * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra coproc + * and TA fields, and mask them out when taking the exception to AArch64. + */ +static inline uint32_t syn_uncategorized(void) +{ + return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_svc(uint32_t imm16) +{ + return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_hvc(uint32_t imm16) +{ + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa32_hvc(uint32_t imm16) +{ + return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_smc(void) +{ + return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + +static inline uint32_t syn_aa64_bkpt(uint32_t imm16) +{ + return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) +{ + return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) + | (is_16bit ? 0 : ARM_EL_IL); +} + +static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, + int crn, int crm, int rt, + int isread) +{ + return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL + | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) + | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, + int crn, int crm, int rt, int isread, + bool is_16bit) +{ + return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) + | (crn << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, + int rt, int rt2, int isread, + bool is_16bit) +{ + return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (opc1 << 16) + | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; +} + +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) +{ + /* AArch32 SIMD trap: TA == 1 coproc == 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); +} + +static inline uint32_t syn_sve_access_trap(void) +{ + return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_pactrap(void) +{ + return EC_PACTRAP << ARM_EL_EC_SHIFT; +} + +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + +static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) +{ + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; +} + +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, + int ea, int cm, int s1ptw, + int wnr, int fsc) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + +static inline uint32_t syn_data_abort_with_iss(int same_el, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, + int wnr, int fsc, + bool is_16bit) +{ + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14) + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; +} + +static inline uint32_t syn_swstep(int same_el, int isv, int ex) +{ + return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; +} + +static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) +{ + return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; +} + +static inline uint32_t syn_breakpoint(int same_el) +{ + return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + | ARM_EL_IL | 0x22; +} + +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +{ + return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | + (cv << 24) | (cond << 20) | ti; +} + +#endif /* TARGET_ARM_SYNDROME_H */ -- 2.25.1 From MAILER-DAEMON Thu Jan 28 17:42:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Fzp-0006Cf-Jm for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 17:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Fzl-00062q-R2 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:33 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:35111) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Fzc-0008FA-9l for qemu-arm@nongnu.org; Thu, 28 Jan 2021 17:42:33 -0500 Received: by mail-pf1-x431.google.com with SMTP id w14so4979789pfi.2 for ; Thu, 28 Jan 2021 14:42:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HKtHUyeX46/E9EoVvwvRWE1/PXHFC9tVF6JjxX+JLd4=; b=YYg6OH7Z73IlMQyvPM01NdWvtipolaDlWRVbDrgk6X5tBSWv0iuqTuRzf/3FdrkEgJ gCluzxNeI5KRLfUgJiFYzvd6w2LWCFX/LqC3nbhZg5WXfz2ZVT1Vh1J4qovo+RUC6Kys NXhEywqrUW5AWYatQk/W9HLgE+WQw0jYB60HK5tBUHzqik2siBYmMDcHwgUNK1b5XcX2 uveoWvQK54EktXycrMDojnyGWWO6vmE1woE4/5HV87fvQDvJLnV+CBlo+QoiQuAHezNR jM538vbv5O8c7BGIWm4KdXctH+fYQVO28b1KOcaRoy0VK5IO2klGGCw37X+LIPlt90V0 G0fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HKtHUyeX46/E9EoVvwvRWE1/PXHFC9tVF6JjxX+JLd4=; b=rL4mR+hhvFc084dcRgXy8d/lUt4t+QXITBrrHwtjgEi9e0g/t0KtiT00PdTHjKD2gL yGYbdN93zOtgsSwQHNZ566IEbJbZwxKdMMmYvo4iKXx7LI2vdVx6zBOzqWx00dWlxOgr bxviJnITck+JYT83G1tW+doG3DPIv8+fxIlqXTKHHQ64jOLJFhUr9ivghxJiA2U6Xb5M ZzSY1rFLFlE1qe/Qu/h/xh7ktWIjTu4u6KNbWtCNY5LReTE0HiRfZnM3Cw1K6V31d2Sv cuxFQ/QW5L8YkHIjm6refbxbiZs+JzYWzrVXGHGyx1iV32ZEv/F91O1vsIFU1EZDKNUT bwmQ== X-Gm-Message-State: AOAM53310t4ZvoJGyZWhVK9FmU8QnJiQrAtuQ+mgKw+dxVGtyj9ZC9TE zgHYh+VhfRuwPV9gtxIeIMGz4rLJMWvJILQ3 X-Google-Smtp-Source: ABdhPJxDijDPc/+P7djzgykFzeG67JGObz2bAhqWRWXQrK8yooy0NKK4iBkJRrX4Kiyz8N/wuzYfKQ== X-Received: by 2002:a05:6a00:2d5:b029:1b9:67bd:b60f with SMTP id b21-20020a056a0002d5b02901b967bdb60fmr1482173pft.10.1611873742378; Thu, 28 Jan 2021 14:42:22 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id m10sm6042358pjs.25.2021.01.28.14.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 14:42:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 23/23] tests/tcg/aarch64: Add mte smoke tests Date: Thu, 28 Jan 2021 12:41:41 -1000 Message-Id: <20210128224141.638790-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210128224141.638790-1-richard.henderson@linaro.org> References: <20210128224141.638790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2021 22:42:34 -0000 Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte.h | 60 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/mte-1.c | 28 +++++++++++++++ tests/tcg/aarch64/mte-2.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/mte-3.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/mte-4.c | 45 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++++ tests/tcg/configure.sh | 4 +++ 7 files changed, 239 insertions(+) create mode 100644 tests/tcg/aarch64/mte.h create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c create mode 100644 tests/tcg/aarch64/mte-3.c create mode 100644 tests/tcg/aarch64/mte-4.c diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h new file mode 100644 index 0000000000..141cef522c --- /dev/null +++ b/tests/tcg/aarch64/mte.h @@ -0,0 +1,60 @@ +/* + * Linux kernel fallback API definitions for MTE and test helpers. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_SET_TAGGED_ADDR_CTRL +# define PR_SET_TAGGED_ADDR_CTRL 55 +#endif +#ifndef PR_TAGGED_ADDR_ENABLE +# define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#endif +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +#endif + +#ifndef PROT_MTE +# define PROT_MTE 0x20 +#endif + +#ifndef SEGV_MTEAERR +# define SEGV_MTEAERR 8 +# define SEGV_MTESERR 9 +#endif + +static void enable_mte(int tcf) +{ + int r = prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0); + if (r < 0) { + perror("PR_SET_TAGGED_ADDR_CTRL"); + exit(2); + } +} + +static void *alloc_mte_mem(size_t size) +{ + void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (p == MAP_FAILED) { + perror("mmap PROT_MTE"); + exit(2); + } + return p; +} diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..88dcd617ad --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,28 @@ +/* + * Memory tagging, basic pass cases. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + int *p0, *p1, *p2; + long c; + + enable_mte(PR_MTE_TCF_NONE); + p0 = alloc_mte_mem(sizeof(*p0)); + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..a62278276a --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, basic fail cases, synchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTESERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + *p2 = 0; + + abort(); +} diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c new file mode 100644 index 0000000000..424ea685c2 --- /dev/null +++ b/tests/tcg/aarch64/mte-3.c @@ -0,0 +1,51 @@ +/* + * Memory tagging, basic fail cases, asynchronous signals. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_code == SEGV_MTEAERR); + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + long *p0, *p1, *p2; + long excl = 1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* + * Signal for async error will happen eventually. + * For a real kernel this should be after the next IRQ (e.g. timer). + * For qemu linux-user, we kick the cpu and exit at the next TB. + * In either case, loop until this happens (or killed by timeout). + * For extra sauce, yield, producing EXCP_YIELD to cpu_loop(). + */ + asm("str %0, [%0]; yield" : : "r"(p2)); + while (1); +} diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c new file mode 100644 index 0000000000..a8cc9f5984 --- /dev/null +++ b/tests/tcg/aarch64/mte-4.c @@ -0,0 +1,45 @@ +/* + * Memory tagging, re-reading tag checks. + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void __attribute__((noinline)) tagset(void *p, size_t size) +{ + size_t i; + for (i = 0; i < size; i += 16) { + asm("stg %0, [%0]" : : "r"(p + i)); + } +} + +void __attribute__((noinline)) tagcheck(void *p, size_t size) +{ + size_t i; + void *c; + + for (i = 0; i < size; i += 16) { + asm("ldg %0, [%1]" : "=r"(c) : "r"(p + i), "0"(p)); + assert(c == p); + } +} + +int main(int ac, char **av) +{ + size_t size = getpagesize() * 4; + long excl = 1; + int *p0, *p1; + + enable_mte(PR_MTE_TCF_ASYNC); + p0 = alloc_mte_mem(size); + + /* Tag the pointer. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + + tagset(p1, size); + tagcheck(p1, size); + + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index d7d33e293c..bf53ad0087 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -35,6 +35,12 @@ endif # bti-2 tests PROT_BTI, so no special compiler support required. AARCH64_TESTS += bti-2 +# MTE Tests +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 +mte-%: CFLAGS += -march=armv8.5-a+memtag +endif + # Semihosting smoke test for linux-user AARCH64_TESTS += semihosting run-semihosting: semihosting diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f2..ba8ac9a93e 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -244,6 +244,10 @@ for target in $target_list; do -mbranch-protection=standard -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak fi + if do_compiler "$target_compiler" $target_compiler_cflags \ + -march=armv8.5-a+memtag -o $TMPE $TMPC; then + echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak + fi ;; esac -- 2.25.1 From MAILER-DAEMON Thu Jan 28 18:16:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5GWB-00040b-K7 for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 18:16:03 -0500 Received: from eggs.gnu.org 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PcqQ== X-Gm-Message-State: AOAM531luGTvMVrZ3iQMVNEABaSZratBfnLHrp2Ih7cKUKV9XosW9r/d sbZZY7eUQ3Qq97PFtLGQtb1ceKRxJcREdA== X-Google-Smtp-Source: ABdhPJz6WuPtLKuXCJIebecu3Wp0YgBSKUro3B1QrY6RC590e/BvsiQ8KWRmr8bvk9OpNqpoWi5s/OcdfvNujg== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:90a:4088:: with SMTP id l8mr2019690pjg.106.1611882248047; Thu, 28 Jan 2021 17:04:08 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:40 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-2-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 1/6] hw/arm: Remove GPIO from unimplemented NPCM7XX From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3CF8TYAgKCBsNL81FKJ87FF7C5.3FDH5DL-1IDEFE7EL.FI7@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:13 -0000 NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 72040d4079..d1fe9bd1df 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -576,14 +576,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB); - create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ICu-00034a-7E for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 20:04:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55550) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3Bl8TYAgKCBkLJ6zDIH65DD5A3.1DBF3BJ-zGBCDC5CJ.DG5@flex--wuhaotsh.bounces.google.com>) id 1l5ICr-00030e-94 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 20:04:13 -0500 Received: from mail-pg1-x54a.google.com ([2607:f8b0:4864:20::54a]:49134) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3Bl8TYAgKCBkLJ6zDIH65DD5A3.1DBF3BJ-zGBCDC5CJ.DG5@flex--wuhaotsh.bounces.google.com>) id 1l5ICm-0004Uf-Kt for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 17:04:06 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:39 -0800 Message-Id: <20210129005845.416272-1-wuhaotsh@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 0/6] hw/i2c: Add NPCM7XX SMBus Device From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3Bl8TYAgKCBkLJ6zDIH65DD5A3.1DBF3BJ-zGBCDC5CJ.DG5@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:13 -0000 This patch set implements the System manager bus (SMBus) module in NPCM7XX SoC. Basically, it emulates the data transactions of the module, not the SDA/SCL levels. We have also added a QTest which contains read and write operations for both single-byte and FIFO mode, and added basic I2C devices for npcm750-evb and quanta-gsj boards. We also cleaned up the unimplemented GPIO devices in npcm7xx.c since they are already implemented. Changes since v1: - Fix errors for i2c device addresses for temperature sensors in GSJ machine - Use at24c device to emulate GSJ EEPROM. It supports more than 256 bytes. - Fill in VMState in npcm7xx_smbus.c - Change commit message in patch 3 and 4 - Fix order in npcm7xx.c IRQ list - Add a few extra comments to make things clearer Hao Wu (6): hw/arm: Remove GPIO from unimplemented NPCM7XX hw/i2c: Implement NPCM7XX SMBus Module Single Mode hw/arm: Add I2C sensors for NPCM750 eval board hw/arm: Add I2C sensors and EEPROM for GSJ machine hw/i2c: Add a QTest for NPCM7XX SMBus Device hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode default-configs/devices/arm-softmmu.mak | 1 + docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 76 +- hw/arm/npcm7xx_boards.c | 46 + hw/i2c/meson.build | 1 + hw/i2c/npcm7xx_smbus.c | 1097 +++++++++++++++++++++++ hw/i2c/trace-events | 12 + include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 113 +++ tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_smbus-test.c | 495 ++++++++++ 11 files changed, 1821 insertions(+), 25 deletions(-) create mode 100644 hw/i2c/npcm7xx_smbus.c create mode 100644 include/hw/i2c/npcm7xx_smbus.h create mode 100644 tests/qtest/npcm7xx_smbus-test.c -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ICv-00038C-KG for mharc-qemu-arm@gnu.org; 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Thu, 28 Jan 2021 17:04:11 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:42 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-4-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 3/6] hw/arm: Add I2C sensors for NPCM750 eval board From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3C18TYAgKCB4QOB4INMBAIIAF8.6IGK8GO-4LGHIHAHO.ILA@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:15 -0000 Add I2C temperature sensors for NPCM750 eval board. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx_boards.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 3fdd5cab01..47a215bd01 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -98,6 +98,24 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, return NPCM7XX(obj); } +static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) +{ + g_assert(num < ARRAY_SIZE(soc->smbus)); + return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); +} + +static void npcm750_evb_i2c_init(NPCM7xxState *soc) +{ + /* lm75 temperature sensor on SVB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48); + /* lm75 temperature sensor on EB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48); + /* tmp100 temperature sensor on EB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48); + /* tmp100 temperature sensor on SVB, tmp105 is compatible */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -108,6 +126,7 @@ static void npcm750_evb_init(MachineState *machine) npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); + npcm750_evb_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ICv-00038q-Sk for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 20:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3CV8TYAgKCBwOM92GLK98GG8D6.4GEI6EM-2JEFGF8FM.GJ8@flex--wuhaotsh.bounces.google.com>) id 1l5ICu-00034S-47 for qemu-arm@nongnu.org; Thu, 28 Jan 2021 20:04:16 -0500 Received: from mail-pf1-x449.google.com ([2607:f8b0:4864:20::449]:55945) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3CV8TYAgKCBwOM92GLK98GG8D6.4GEI6EM-2JEFGF8FM.GJ8@flex--wuhaotsh.bounces.google.com>) id 1l5ICq-0004Vs-NQ for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 17:04:09 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:41 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-3-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 2/6] hw/i2c: Implement NPCM7XX SMBus Module Single Mode From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::449; envelope-from=3CV8TYAgKCBwOM92GLK98GG8D6.4GEI6EM-2JEFGF8FM.GJ8@flex--wuhaotsh.bounces.google.com; helo=mail-pf1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:16 -0000 This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Corey Minyard Ack-by: Corey Minyard --- docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 68 ++- hw/i2c/meson.build | 1 + hw/i2c/npcm7xx_smbus.c | 781 +++++++++++++++++++++++++++++++++ hw/i2c/trace-events | 11 + include/hw/arm/npcm7xx.h | 2 + include/hw/i2c/npcm7xx_smbus.h | 88 ++++ 7 files changed, 936 insertions(+), 17 deletions(-) create mode 100644 hw/i2c/npcm7xx_smbus.c create mode 100644 include/hw/i2c/npcm7xx_smbus.h diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index a1786342e2..34fc799b2d 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -43,6 +43,7 @@ Supported devices * GPIO controller * Analog to Digital Converter (ADC) * Pulse Width Modulation (PWM) + * SMBus controller (SMBF) Missing devices --------------- @@ -58,7 +59,6 @@ Missing devices * Ethernet controllers (GMAC and EMC) * USB device (USBD) - * SMBus controller (SMBF) * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d1fe9bd1df..f8950f9470 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -102,6 +102,22 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ NPCM7XX_EHCI_IRQ = 61, NPCM7XX_OHCI_IRQ = 62, + NPCM7XX_SMBUS0_IRQ = 64, + NPCM7XX_SMBUS1_IRQ, + NPCM7XX_SMBUS2_IRQ, + NPCM7XX_SMBUS3_IRQ, + NPCM7XX_SMBUS4_IRQ, + NPCM7XX_SMBUS5_IRQ, + NPCM7XX_SMBUS6_IRQ, + NPCM7XX_SMBUS7_IRQ, + NPCM7XX_SMBUS8_IRQ, + NPCM7XX_SMBUS9_IRQ, + NPCM7XX_SMBUS10_IRQ, + NPCM7XX_SMBUS11_IRQ, + NPCM7XX_SMBUS12_IRQ, + NPCM7XX_SMBUS13_IRQ, + NPCM7XX_SMBUS14_IRQ, + NPCM7XX_SMBUS15_IRQ, NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */ NPCM7XX_PWM1_IRQ, /* PWM module 1 */ NPCM7XX_GPIO0_IRQ = 116, @@ -152,6 +168,26 @@ static const hwaddr npcm7xx_pwm_addr[] = { 0xf0104000, }; +/* Direct memory-mapped access to each SMBus Module. */ +static const hwaddr npcm7xx_smbus_addr[] = { + 0xf0080000, + 0xf0081000, + 0xf0082000, + 0xf0083000, + 0xf0084000, + 0xf0085000, + 0xf0086000, + 0xf0087000, + 0xf0088000, + 0xf0089000, + 0xf008a000, + 0xf008b000, + 0xf008c000, + 0xf008d000, + 0xf008e000, + 0xf008f000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -353,6 +389,11 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); } + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { + object_initialize_child(obj, "smbus[*]", &s->smbus[i], + TYPE_NPCM7XX_SMBUS); + } + object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); @@ -509,6 +550,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); } + /* SMBus modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus)); + for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { + Object *obj = OBJECT(&s->smbus[i]); + + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i)); + } + /* USB Host */ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, &error_abort); @@ -576,22 +628,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB); - create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB); create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB); create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build index 3a511539ad..cdcd694a7f 100644 --- a/hw/i2c/meson.build +++ b/hw/i2c/meson.build @@ -9,6 +9,7 @@ i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c')) i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) +i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c')) i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c')) i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c')) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c new file mode 100644 index 0000000000..c72b6e446f --- /dev/null +++ b/hw/i2c/npcm7xx_smbus.c @@ -0,0 +1,781 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/i2c/npcm7xx_smbus.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/guest-random.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#include "trace.h" + +#define NPCM7XX_SMBUS_VERSION 1 +#define NPCM7XX_SMBUS_FIFO_EN 0 + +enum NPCM7xxSMBusCommonRegister { + NPCM7XX_SMB_SDA = 0x0, + NPCM7XX_SMB_ST = 0x2, + NPCM7XX_SMB_CST = 0x4, + NPCM7XX_SMB_CTL1 = 0x6, + NPCM7XX_SMB_ADDR1 = 0x8, + NPCM7XX_SMB_CTL2 = 0xa, + NPCM7XX_SMB_ADDR2 = 0xc, + NPCM7XX_SMB_CTL3 = 0xe, + NPCM7XX_SMB_CST2 = 0x18, + NPCM7XX_SMB_CST3 = 0x19, + NPCM7XX_SMB_VER = 0x1f, +}; + +enum NPCM7xxSMBusBank0Register { + NPCM7XX_SMB_ADDR3 = 0x10, + NPCM7XX_SMB_ADDR7 = 0x11, + NPCM7XX_SMB_ADDR4 = 0x12, + NPCM7XX_SMB_ADDR8 = 0x13, + NPCM7XX_SMB_ADDR5 = 0x14, + NPCM7XX_SMB_ADDR9 = 0x15, + NPCM7XX_SMB_ADDR6 = 0x16, + NPCM7XX_SMB_ADDR10 = 0x17, + NPCM7XX_SMB_CTL4 = 0x1a, + NPCM7XX_SMB_CTL5 = 0x1b, + NPCM7XX_SMB_SCLLT = 0x1c, + NPCM7XX_SMB_FIF_CTL = 0x1d, + NPCM7XX_SMB_SCLHT = 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + NPCM7XX_SMB_FIF_CTS = 0x10, + NPCM7XX_SMB_FAIR_PER = 0x11, + NPCM7XX_SMB_TXF_CTL = 0x12, + NPCM7XX_SMB_T_OUT = 0x14, + NPCM7XX_SMB_TXF_STS = 0x1a, + NPCM7XX_SMB_RXF_STS = 0x1c, + NPCM7XX_SMB_RXF_CTL = 0x1e, +}; + +/* ST fields */ +#define NPCM7XX_SMBST_STP BIT(7) +#define NPCM7XX_SMBST_SDAST BIT(6) +#define NPCM7XX_SMBST_BER BIT(5) +#define NPCM7XX_SMBST_NEGACK BIT(4) +#define NPCM7XX_SMBST_STASTR BIT(3) +#define NPCM7XX_SMBST_NMATCH BIT(2) +#define NPCM7XX_SMBST_MODE BIT(1) +#define NPCM7XX_SMBST_XMIT BIT(0) + +/* CST fields */ +#define NPCM7XX_SMBCST_ARPMATCH BIT(7) +#define NPCM7XX_SMBCST_MATCHAF BIT(6) +#define NPCM7XX_SMBCST_TGSCL BIT(5) +#define NPCM7XX_SMBCST_TSDA BIT(4) +#define NPCM7XX_SMBCST_GCMATCH BIT(3) +#define NPCM7XX_SMBCST_MATCH BIT(2) +#define NPCM7XX_SMBCST_BB BIT(1) +#define NPCM7XX_SMBCST_BUSY BIT(0) + +/* CST2 fields */ +#define NPCM7XX_SMBCST2_INTSTS BIT(7) +#define NPCM7XX_SMBCST2_MATCH7F BIT(6) +#define NPCM7XX_SMBCST2_MATCH6F BIT(5) +#define NPCM7XX_SMBCST2_MATCH5F BIT(4) +#define NPCM7XX_SMBCST2_MATCH4F BIT(3) +#define NPCM7XX_SMBCST2_MATCH3F BIT(2) +#define NPCM7XX_SMBCST2_MATCH2F BIT(1) +#define NPCM7XX_SMBCST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define NPCM7XX_SMBCST3_EO_BUSY BIT(7) +#define NPCM7XX_SMBCST3_MATCH10F BIT(2) +#define NPCM7XX_SMBCST3_MATCH9F BIT(1) +#define NPCM7XX_SMBCST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define NPCM7XX_SMBCTL1_STASTRE BIT(7) +#define NPCM7XX_SMBCTL1_NMINTE BIT(6) +#define NPCM7XX_SMBCTL1_GCMEN BIT(5) +#define NPCM7XX_SMBCTL1_ACK BIT(4) +#define NPCM7XX_SMBCTL1_EOBINTE BIT(3) +#define NPCM7XX_SMBCTL1_INTEN BIT(2) +#define NPCM7XX_SMBCTL1_STOP BIT(1) +#define NPCM7XX_SMBCTL1_START BIT(0) + +/* CTL2 fields */ +#define NPCM7XX_SMBCTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define NPCM7XX_SMBCTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define NPCM7XX_SMBCTL3_SCL_LVL BIT(7) +#define NPCM7XX_SMBCTL3_SDA_LVL BIT(6) +#define NPCM7XX_SMBCTL3_BNK_SEL BIT(5) +#define NPCM7XX_SMBCTL3_400K_MODE BIT(4) +#define NPCM7XX_SMBCTL3_IDL_START BIT(3) +#define NPCM7XX_SMBCTL3_ARPMEN BIT(2) +#define NPCM7XX_SMBCTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define NPCM7XX_ADDR_EN BIT(7) +#define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) + +#define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) +#define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) + +#define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) + +/* Reset values */ +#define NPCM7XX_SMB_ST_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST_INIT_VAL 0x10 +#define NPCM7XX_SMB_CST2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CST3_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL1_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL2_INIT_VAL 0x00 +#define NPCM7XX_SMB_CTL3_INIT_VAL 0xc0 +#define NPCM7XX_SMB_CTL4_INIT_VAL 0x07 +#define NPCM7XX_SMB_CTL5_INIT_VAL 0x00 +#define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 +#define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 + +static uint8_t npcm7xx_smbus_get_version(void) +{ + return NPCM7XX_SMBUS_FIFO_EN << 7 | NPCM7XX_SMBUS_VERSION; +} + +static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) +{ + int level; + + if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { + level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && + s->st & NPCM7XX_SMBST_NMATCH) || + (s->st & NPCM7XX_SMBST_BER) || + (s->st & NPCM7XX_SMBST_NEGACK) || + (s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && + s->st & NPCM7XX_SMBST_SDAST) || + (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + + if (level) { + s->cst2 |= NPCM7XX_SMBCST2_INTSTS; + } else { + s->cst2 &= ~NPCM7XX_SMBCST2_INTSTS; + } + qemu_set_irq(s->irq, level); + } +} + +static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) +{ + s->st &= ~NPCM7XX_SMBST_SDAST; + s->st |= NPCM7XX_SMBST_NEGACK; + s->status = NPCM7XX_SMBUS_STATUS_NEGACK; +} + +static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) +{ + int rv = i2c_send(s->bus, value); + + if (rv) { + npcm7xx_smbus_nack(s); + } else { + s->st |= NPCM7XX_SMBST_SDAST; + } + trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) +{ + s->sda = i2c_recv(s->bus); + s->st |= NPCM7XX_SMBST_SDAST; + if (s->st & NPCM7XX_SMBCTL1_ACK) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->st &= NPCM7XX_SMBCTL1_ACK; + } + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), s->sda); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) +{ + /* + * We can start the bus if one of these is true: + * 1. The bus is idle (so we can request it) + * 2. We are the occupier (it's a repeated start condition.) + */ + int available = !i2c_bus_busy(s->bus) || + s->status != NPCM7XX_SMBUS_STATUS_IDLE; + + if (available) { + s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; + s->cst |= NPCM7XX_SMBCST_BUSY; + } else { + s->st &= ~NPCM7XX_SMBST_MODE; + s->cst &= ~NPCM7XX_SMBCST_BUSY; + s->st |= NPCM7XX_SMBST_BER; + } + + trace_npcm7xx_smbus_start(DEVICE(s)->canonical_path, available); + s->cst |= NPCM7XX_SMBCST_BB; + s->status = NPCM7XX_SMBUS_STATUS_IDLE; + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) +{ + int recv; + int rv; + + recv = value & BIT(0); + rv = i2c_start_transfer(s->bus, value >> 1, recv); + trace_npcm7xx_smbus_send_address(DEVICE(s)->canonical_path, + value >> 1, recv, !rv); + if (rv) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: requesting i2c bus for 0x%02x failed: %d\n", + DEVICE(s)->canonical_path, value, rv); + /* Failed to start transfer. NACK to reject.*/ + if (recv) { + s->st &= ~NPCM7XX_SMBST_XMIT; + } else { + s->st |= NPCM7XX_SMBST_XMIT; + } + npcm7xx_smbus_nack(s); + npcm7xx_smbus_update_irq(s); + return; + } + + s->st &= ~NPCM7XX_SMBST_NEGACK; + if (recv) { + s->status = NPCM7XX_SMBUS_STATUS_RECEIVING; + s->st &= ~NPCM7XX_SMBST_XMIT; + } else { + s->status = NPCM7XX_SMBUS_STATUS_SENDING; + s->st |= NPCM7XX_SMBST_XMIT; + } + + if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { + s->st |= NPCM7XX_SMBST_STASTR; + if (!recv) { + s->st |= NPCM7XX_SMBST_SDAST; + } + } else if (recv) { + npcm7xx_smbus_recv_byte(s); + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_execute_stop(NPCM7xxSMBusState *s) +{ + i2c_end_transfer(s->bus); + s->st = 0; + s->cst = 0; + s->status = NPCM7XX_SMBUS_STATUS_IDLE; + s->cst3 |= NPCM7XX_SMBCST3_EO_BUSY; + trace_npcm7xx_smbus_stop(DEVICE(s)->canonical_path); + npcm7xx_smbus_update_irq(s); +} + + +static void npcm7xx_smbus_stop(NPCM7xxSMBusState *s) +{ + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_RECEIVING: + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE; + break; + + case NPCM7XX_SMBUS_STATUS_NEGACK: + s->status = NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK; + break; + + default: + npcm7xx_smbus_execute_stop(s); + break; + } + } +} + +static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) +{ + uint8_t value = s->sda; + + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: + npcm7xx_smbus_execute_stop(s); + break; + + case NPCM7XX_SMBUS_STATUS_RECEIVING: + npcm7xx_smbus_recv_byte(s); + break; + + default: + /* Do nothing */ + break; + } + + return value; +} + +static void npcm7xx_smbus_write_sda(NPCM7xxSMBusState *s, uint8_t value) +{ + s->sda = value; + if (s->st & NPCM7XX_SMBST_MODE) { + switch (s->status) { + case NPCM7XX_SMBUS_STATUS_IDLE: + npcm7xx_smbus_send_address(s, value); + break; + case NPCM7XX_SMBUS_STATUS_SENDING: + npcm7xx_smbus_send_byte(s, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to SDA in invalid status %d: %u\n", + DEVICE(s)->canonical_path, s->status, value); + break; + } + } +} + +static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) +{ + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STP); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_BER); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STASTR); + s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_NMATCH); + + if (value & NPCM7XX_SMBST_NEGACK) { + s->st &= ~NPCM7XX_SMBST_NEGACK; + if (s->status == NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK) { + npcm7xx_smbus_execute_stop(s); + } + } + + if (value & NPCM7XX_SMBST_STASTR && + s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_byte(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_value = s->cst; + + s->cst = WRITE_ONE_CLEAR(new_value, value, NPCM7XX_SMBCST_BB); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_cst3(NPCM7xxSMBusState *s, uint8_t value) +{ + s->cst3 = WRITE_ONE_CLEAR(s->cst3, value, NPCM7XX_SMBCST3_EO_BUSY); + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl1(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, + NPCM7XX_SMBCTL1_START | NPCM7XX_SMBCTL1_STOP | NPCM7XX_SMBCTL1_ACK); + + if (value & NPCM7XX_SMBCTL1_START) { + npcm7xx_smbus_start(s); + } + + if (value & NPCM7XX_SMBCTL1_STOP) { + npcm7xx_smbus_stop(s); + } + + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) +{ + s->ctl2 = value; + + if (!NPCM7XX_SMBUS_ENABLED(s)) { + /* Disable this SMBus module. */ + s->ctl1 = 0; + s->st = 0; + s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); + s->cst = 0; + } +} + +static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t old_ctl3 = s->ctl3; + + /* Write to SDA and SCL bits are ignored. */ + s->ctl3 = KEEP_OLD_BIT(old_ctl3, value, + NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_LVL); +} + +static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCM7xxSMBusState *s = opaque; + uint64_t value = 0; + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + /* The order of the registers are their order in memory. */ + switch (offset) { + case NPCM7XX_SMB_SDA: + value = npcm7xx_smbus_read_sda(s); + break; + + case NPCM7XX_SMB_ST: + value = s->st; + break; + + case NPCM7XX_SMB_CST: + value = s->cst; + break; + + case NPCM7XX_SMB_CTL1: + value = s->ctl1; + break; + + case NPCM7XX_SMB_ADDR1: + value = s->addr[0]; + break; + + case NPCM7XX_SMB_CTL2: + value = s->ctl2; + break; + + case NPCM7XX_SMB_ADDR2: + value = s->addr[1]; + break; + + case NPCM7XX_SMB_CTL3: + value = s->ctl3; + break; + + case NPCM7XX_SMB_CST2: + value = s->cst2; + break; + + case NPCM7XX_SMB_CST3: + value = s->cst3; + break; + + case NPCM7XX_SMB_VER: + value = npcm7xx_smbus_get_version(); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + value = s->addr[2]; + break; + + case NPCM7XX_SMB_ADDR7: + value = s->addr[6]; + break; + + case NPCM7XX_SMB_ADDR4: + value = s->addr[3]; + break; + + case NPCM7XX_SMB_ADDR8: + value = s->addr[7]; + break; + + case NPCM7XX_SMB_ADDR5: + value = s->addr[4]; + break; + + case NPCM7XX_SMB_ADDR9: + value = s->addr[8]; + break; + + case NPCM7XX_SMB_ADDR6: + value = s->addr[5]; + break; + + case NPCM7XX_SMB_ADDR10: + value = s->addr[9]; + break; + + case NPCM7XX_SMB_CTL4: + value = s->ctl4; + break; + + case NPCM7XX_SMB_CTL5: + value = s->ctl5; + break; + + case NPCM7XX_SMB_SCLLT: + value = s->scllt; + break; + + case NPCM7XX_SMB_SCLHT: + value = s->sclht; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } + + trace_npcm7xx_smbus_read(DEVICE(s)->canonical_path, offset, value, size); + + return value; +} + +static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + NPCM7xxSMBusState *s = opaque; + uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; + + trace_npcm7xx_smbus_write(DEVICE(s)->canonical_path, offset, value, size); + + /* The order of the registers are their order in memory. */ + switch (offset) { + case NPCM7XX_SMB_SDA: + npcm7xx_smbus_write_sda(s, value); + break; + + case NPCM7XX_SMB_ST: + npcm7xx_smbus_write_st(s, value); + break; + + case NPCM7XX_SMB_CST: + npcm7xx_smbus_write_cst(s, value); + break; + + case NPCM7XX_SMB_CTL1: + npcm7xx_smbus_write_ctl1(s, value); + break; + + case NPCM7XX_SMB_ADDR1: + s->addr[0] = value; + break; + + case NPCM7XX_SMB_CTL2: + npcm7xx_smbus_write_ctl2(s, value); + break; + + case NPCM7XX_SMB_ADDR2: + s->addr[1] = value; + break; + + case NPCM7XX_SMB_CTL3: + npcm7xx_smbus_write_ctl3(s, value); + break; + + case NPCM7XX_SMB_CST2: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + case NPCM7XX_SMB_CST3: + npcm7xx_smbus_write_cst3(s, value); + break; + + case NPCM7XX_SMB_VER: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + + /* This register is either invalid or banked at this point. */ + default: + if (bank) { + /* Bank 1 */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + } else { + /* Bank 0 */ + switch (offset) { + case NPCM7XX_SMB_ADDR3: + s->addr[2] = value; + break; + + case NPCM7XX_SMB_ADDR7: + s->addr[6] = value; + break; + + case NPCM7XX_SMB_ADDR4: + s->addr[3] = value; + break; + + case NPCM7XX_SMB_ADDR8: + s->addr[7] = value; + break; + + case NPCM7XX_SMB_ADDR5: + s->addr[4] = value; + break; + + case NPCM7XX_SMB_ADDR9: + s->addr[8] = value; + break; + + case NPCM7XX_SMB_ADDR6: + s->addr[5] = value; + break; + + case NPCM7XX_SMB_ADDR10: + s->addr[9] = value; + break; + + case NPCM7XX_SMB_CTL4: + s->ctl4 = value; + break; + + case NPCM7XX_SMB_CTL5: + s->ctl5 = value; + break; + + case NPCM7XX_SMB_SCLLT: + s->scllt = value; + break; + + case NPCM7XX_SMB_SCLHT: + s->sclht = value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } + } + break; + } +} + +static const MemoryRegionOps npcm7xx_smbus_ops = { + .read = npcm7xx_smbus_read, + .write = npcm7xx_smbus_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 1, + .unaligned = false, + }, +}; + +static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + + s->st = NPCM7XX_SMB_ST_INIT_VAL; + s->cst = NPCM7XX_SMB_CST_INIT_VAL; + s->cst2 = NPCM7XX_SMB_CST2_INIT_VAL; + s->cst3 = NPCM7XX_SMB_CST3_INIT_VAL; + s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; + s->ctl2 = NPCM7XX_SMB_CTL2_INIT_VAL; + s->ctl3 = NPCM7XX_SMB_CTL3_INIT_VAL; + s->ctl4 = NPCM7XX_SMB_CTL4_INIT_VAL; + s->ctl5 = NPCM7XX_SMB_CTL5_INIT_VAL; + + for (int i = 0; i < NPCM7XX_SMBUS_NR_ADDRS; ++i) { + s->addr[i] = NPCM7XX_SMB_ADDR_INIT_VAL; + } + s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; + s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; + + s->status = NPCM7XX_SMBUS_STATUS_IDLE; +} + +static void npcm7xx_smbus_hold_reset(Object *obj) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_smbus_init(Object *obj) +{ + NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + sysbus_init_irq(sbd, &s->irq); + memory_region_init_io(&s->iomem, obj, &npcm7xx_smbus_ops, s, + "regs", 4 * KiB); + sysbus_init_mmio(sbd, &s->iomem); + + s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); + s->status = NPCM7XX_SMBUS_STATUS_IDLE; +} + +static const VMStateDescription vmstate_npcm7xx_smbus = { + .name = "npcm7xx-smbus", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(sda, NPCM7xxSMBusState), + VMSTATE_UINT8(st, NPCM7xxSMBusState), + VMSTATE_UINT8(cst, NPCM7xxSMBusState), + VMSTATE_UINT8(cst2, NPCM7xxSMBusState), + VMSTATE_UINT8(cst3, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl1, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl2, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl3, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl4, NPCM7xxSMBusState), + VMSTATE_UINT8(ctl5, NPCM7xxSMBusState), + VMSTATE_UINT8_ARRAY(addr, NPCM7xxSMBusState, NPCM7XX_SMBUS_NR_ADDRS), + VMSTATE_UINT8(scllt, NPCM7xxSMBusState), + VMSTATE_UINT8(sclht, NPCM7xxSMBusState), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_smbus_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx System Management Bus"; + dc->vmsd = &vmstate_npcm7xx_smbus; + rc->phases.enter = npcm7xx_smbus_enter_reset; + rc->phases.hold = npcm7xx_smbus_hold_reset; +} + +static const TypeInfo npcm7xx_smbus_types[] = { + { + .name = TYPE_NPCM7XX_SMBUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxSMBusState), + .class_init = npcm7xx_smbus_class_init, + .instance_init = npcm7xx_smbus_init, + }, +}; +DEFINE_TYPES(npcm7xx_smbus_types); diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 08db8fa689..c3bb70ad04 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -14,3 +14,14 @@ aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t val aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x" aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) "%s recv %d/%d 0x%02x" + +# npcm7xx_smbus.c + +npcm7xx_smbus_read(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_write(const char *id, uint64_t offset, uint64_t value, unsigned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_smbus_start(const char *id, int success) "%s starting, success: %d" +npcm7xx_smbus_send_address(const char *id, uint8_t addr, int recv, int success) "%s sending address: 0x%02x, recv: %d, success: %d" +npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byte: 0x%02x, success: %d" +npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x" +npcm7xx_smbus_stop(const char *id) "%s stopping" +npcm7xx_smbus_nack(const char *id) "%s nacking" diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f6227aa8aa..cea1bd1f62 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/adc/npcm7xx_adc.h" #include "hw/cpu/a9mpcore.h" #include "hw/gpio/npcm7xx_gpio.h" +#include "hw/i2c/npcm7xx_smbus.h" #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" @@ -85,6 +86,7 @@ typedef struct NPCM7xxState { NPCM7xxMCState mc; NPCM7xxRNGState rng; NPCM7xxGPIOState gpio[8]; + NPCM7xxSMBusState smbus[16]; EHCISysBusState ehci; OHCISysBusState ohci; NPCM7xxFIUState fiu[2]; diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h new file mode 100644 index 0000000000..b9761a6993 --- /dev/null +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -0,0 +1,88 @@ +/* + * Nuvoton NPCM7xx SMBus Module. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_SMBUS_H +#define NPCM7XX_SMBUS_H + +#include "exec/memory.h" +#include "hw/i2c/i2c.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +/* + * Number of addresses this module contains. Do not change this without + * incrementing the version_id in the vmstate. + */ +#define NPCM7XX_SMBUS_NR_ADDRS 10 + +typedef enum NPCM7xxSMBusStatus { + NPCM7XX_SMBUS_STATUS_IDLE, + NPCM7XX_SMBUS_STATUS_SENDING, + NPCM7XX_SMBUS_STATUS_RECEIVING, + NPCM7XX_SMBUS_STATUS_NEGACK, + NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE, + NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK, +} NPCM7xxSMBusStatus; + +/* + * struct NPCM7xxSMBusState - System Management Bus device state. + * @bus: The underlying I2C Bus. + * @irq: GIC interrupt line to fire on events (if enabled). + * @sda: The serial data register. + * @st: The status register. + * @cst: The control status register. + * @cst2: The control status register 2. + * @cst3: The control status register 3. + * @ctl1: The control register 1. + * @ctl2: The control register 2. + * @ctl3: The control register 3. + * @ctl4: The control register 4. + * @ctl5: The control register 5. + * @addr: The SMBus module's own addresses on the I2C bus. + * @scllt: The SCL low time register. + * @sclht: The SCL high time register. + * @status: The current status of the SMBus. + */ +typedef struct NPCM7xxSMBusState { + SysBusDevice parent; + + MemoryRegion iomem; + + I2CBus *bus; + qemu_irq irq; + + uint8_t sda; + uint8_t st; + uint8_t cst; + uint8_t cst2; + uint8_t cst3; + uint8_t ctl1; + uint8_t ctl2; + uint8_t ctl3; + uint8_t ctl4; + uint8_t ctl5; + uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS]; + + uint8_t scllt; + uint8_t sclht; + + NPCM7xxSMBusStatus status; +} NPCM7xxSMBusState; + +#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" +#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ + TYPE_NPCM7XX_SMBUS) + +#endif /* NPCM7XX_SMBUS_H */ -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ICx-0003De-KI for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 20:04:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3DV8TYAgKCCASQD6KPODCKKCHA.8KIMAIQ-6NIJKJCJQ.KNC@flex--wuhaotsh.bounces.google.com>) id 1l5ICw-00039Z-3w for qemu-arm@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=5L59xU9wVj0tK8cnn1xfmiztIbM883HqzN6NgU/DUus=; b=Nf+f5MUwNkTJY+eJZdNCxMZK3B/HIuffNkssvcEKghIubYZ84BtBP9GAsUPv90rjxo /HxLGoXNJHGCbjtNxquWLcWI72Q5EhGZa8/OE6Rqik5JkmeDoa6MN474lZ5ZBMbma3At uCWPlzRNw/Lu45EbsH6hD6Vt9GkyX9NSmT6E7vr0qr3yNZpHGkm0mchOwmNxHbTSCMPh KGecsEjbaRueUCJUSMlTQeE3z51sjBtAC6Kbk9+3hZ0MrXC/XsFlMOe1B7qFGapzjeWG AHRrTZklkhaJJ+17DjlgC0Qft0Zh3umKmzu8yVgr1zvlzp+dYrcrKFIFuJQ/6ra42hCP EKBg== X-Gm-Message-State: AOAM531ZlxS9YlFtjwtj5SBfcgEcQl8mjvkN9VD3PczTZCJhf1ukWras xu4tnjT/aDoYY/DKFuBAzW7EtT9JOdBvPw== X-Google-Smtp-Source: ABdhPJytIpPOhP87UEj3VVVqGvq8I7+WpjLx+tb+JAbe9FR6fyoaQuESaUBcLzOu1DB8autMLHqdNcJMvz0t8g== Sender: "wuhaotsh via sendgmr" X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:10:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:90a:d305:: with SMTP id p5mr2059893pju.33.1611882253387; Thu, 28 Jan 2021 17:04:13 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:43 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-5-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 4/6] hw/arm: Add I2C sensors and EEPROM for GSJ machine From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3DV8TYAgKCCASQD6KPODCKKCHA.8KIMAIQ-6NIJKJCJQ.KNC@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:18 -0000 Add AT24 EEPROM and temperature sensors for GSJ machine. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- default-configs/devices/arm-softmmu.mak | 1 + hw/arm/npcm7xx_boards.c | 27 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0500156a0c..d9805dd539 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -7,6 +7,7 @@ CONFIG_ARM_V7M=y # CONFIG_TEST_DEVICES=n CONFIG_ARM_VIRT=y +CONFIG_AT24C=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 47a215bd01..2d757b4013 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -19,6 +19,7 @@ #include "exec/address-spaces.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" +#include "hw/i2c/smbus_eeprom.h" #include "hw/loader.h" #include "hw/qdev-properties.h" #include "qapi/error.h" @@ -104,6 +105,17 @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num) return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); } +static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr, + uint32_t rsize) +{ + I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus); + I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); + DeviceState *dev = DEVICE(i2c_dev); + + qdev_prop_set_uint32(dev, "rom-size", rsize); + i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort); +} + static void npcm750_evb_i2c_init(NPCM7xxState *soc) { /* lm75 temperature sensor on SVB, tmp105 is compatible */ @@ -116,6 +128,20 @@ static void npcm750_evb_i2c_init(NPCM7xxState *soc) i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48); } +static void quanta_gsj_i2c_init(NPCM7xxState *soc) +{ + /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c); + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c); + + at24c_eeprom_init(soc, 9, 0x55, 8192); + at24c_eeprom_init(soc, 10, 0x55, 8192); + + /* TODO: Add addtional i2c devices. */ +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -141,6 +167,7 @@ static void quanta_gsj_init(MachineState *machine) npcm7xx_load_bootrom(machine, soc); npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e", drive_get(IF_MTD, 0, 0)); + quanta_gsj_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ICy-0003GZ-QB for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 20:04:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3D18TYAgKCCIUSF8MRQFEMMEJC.AMKOCKS-8PKLMLELS.MPE@flex--wuhaotsh.bounces.google.com>) id 1l5ICx-0003DM-Ea for qemu-arm@nongnu.org; Thu, 28 Jan 2021 20:04:19 -0500 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]:55318) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3D18TYAgKCCIUSF8MRQFEMMEJC.AMKOCKS-8PKLMLELS.MPE@flex--wuhaotsh.bounces.google.com>) id 1l5ICv-0004Xk-1q for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 17:04:15 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:44 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-6-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 5/6] hw/i2c: Add a QTest for NPCM7XX SMBus Device From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3D18TYAgKCCIUSF8MRQFEMMEJC.AMKOCKS-8PKLMLELS.MPE@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:19 -0000 This patch adds a QTest for NPCM7XX SMBus's single byte mode. It sends a byte to a device in the evaluation board, and verify the retrieved value is equivalent to the sent value. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_smbus-test.c | 352 +++++++++++++++++++++++++++++++ 2 files changed, 353 insertions(+) create mode 100644 tests/qtest/npcm7xx_smbus-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8..aa62d59817 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -138,6 +138,7 @@ qtests_npcm7xx = \ 'npcm7xx_gpio-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', + 'npcm7xx_smbus-test', 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-test.c new file mode 100644 index 0000000000..4594b107df --- /dev/null +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -0,0 +1,352 @@ +/* + * QTests for Nuvoton NPCM7xx SMBus Modules. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/i2c.h" +#include "libqos/libqtest.h" +#include "hw/misc/tmp105_regs.h" + +#define NR_SMBUS_DEVICES 16 +#define SMBUS_ADDR(x) (0xf0080000 + 0x1000 * (x)) +#define SMBUS_IRQ(x) (64 + (x)) + +#define EVB_DEVICE_ADDR 0x48 +#define INVALID_DEVICE_ADDR 0x01 + +const int evb_bus_list[] = {0, 1, 2, 6}; + +/* Offsets */ +enum CommonRegister { + OFFSET_SDA = 0x0, + OFFSET_ST = 0x2, + OFFSET_CST = 0x4, + OFFSET_CTL1 = 0x6, + OFFSET_ADDR1 = 0x8, + OFFSET_CTL2 = 0xa, + OFFSET_ADDR2 = 0xc, + OFFSET_CTL3 = 0xe, + OFFSET_CST2 = 0x18, + OFFSET_CST3 = 0x19, +}; + +enum NPCM7xxSMBusBank0Register { + OFFSET_ADDR3 = 0x10, + OFFSET_ADDR7 = 0x11, + OFFSET_ADDR4 = 0x12, + OFFSET_ADDR8 = 0x13, + OFFSET_ADDR5 = 0x14, + OFFSET_ADDR9 = 0x15, + OFFSET_ADDR6 = 0x16, + OFFSET_ADDR10 = 0x17, + OFFSET_CTL4 = 0x1a, + OFFSET_CTL5 = 0x1b, + OFFSET_SCLLT = 0x1c, + OFFSET_FIF_CTL = 0x1d, + OFFSET_SCLHT = 0x1e, +}; + +enum NPCM7xxSMBusBank1Register { + OFFSET_FIF_CTS = 0x10, + OFFSET_FAIR_PER = 0x11, + OFFSET_TXF_CTL = 0x12, + OFFSET_T_OUT = 0x14, + OFFSET_TXF_STS = 0x1a, + OFFSET_RXF_STS = 0x1c, + OFFSET_RXF_CTL = 0x1e, +}; + +/* ST fields */ +#define ST_STP BIT(7) +#define ST_SDAST BIT(6) +#define ST_BER BIT(5) +#define ST_NEGACK BIT(4) +#define ST_STASTR BIT(3) +#define ST_NMATCH BIT(2) +#define ST_MODE BIT(1) +#define ST_XMIT BIT(0) + +/* CST fields */ +#define CST_ARPMATCH BIT(7) +#define CST_MATCHAF BIT(6) +#define CST_TGSCL BIT(5) +#define CST_TSDA BIT(4) +#define CST_GCMATCH BIT(3) +#define CST_MATCH BIT(2) +#define CST_BB BIT(1) +#define CST_BUSY BIT(0) + +/* CST2 fields */ +#define CST2_INSTTS BIT(7) +#define CST2_MATCH7F BIT(6) +#define CST2_MATCH6F BIT(5) +#define CST2_MATCH5F BIT(4) +#define CST2_MATCH4F BIT(3) +#define CST2_MATCH3F BIT(2) +#define CST2_MATCH2F BIT(1) +#define CST2_MATCH1F BIT(0) + +/* CST3 fields */ +#define CST3_EO_BUSY BIT(7) +#define CST3_MATCH10F BIT(2) +#define CST3_MATCH9F BIT(1) +#define CST3_MATCH8F BIT(0) + +/* CTL1 fields */ +#define CTL1_STASTRE BIT(7) +#define CTL1_NMINTE BIT(6) +#define CTL1_GCMEN BIT(5) +#define CTL1_ACK BIT(4) +#define CTL1_EOBINTE BIT(3) +#define CTL1_INTEN BIT(2) +#define CTL1_STOP BIT(1) +#define CTL1_START BIT(0) + +/* CTL2 fields */ +#define CTL2_SCLFRQ(rv) extract8((rv), 1, 6) +#define CTL2_ENABLE BIT(0) + +/* CTL3 fields */ +#define CTL3_SCL_LVL BIT(7) +#define CTL3_SDA_LVL BIT(6) +#define CTL3_BNK_SEL BIT(5) +#define CTL3_400K_MODE BIT(4) +#define CTL3_IDL_START BIT(3) +#define CTL3_ARPMEN BIT(2) +#define CTL3_SCLFRQ(rv) extract8((rv), 0, 2) + +/* ADDR fields */ +#define ADDR_EN BIT(7) +#define ADDR_A(rv) extract8((rv), 0, 6) + + +static void check_running(QTestState *qts, uint64_t base_addr) +{ + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); +} + +static void check_stopped(QTestState *qts, uint64_t base_addr) +{ + uint8_t cst3; + + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); + + cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_true(cst3 & CST3_EO_BUSY); + qtest_writeb(qts, base_addr + OFFSET_CST3, cst3); + cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); + g_assert_false(cst3 & CST3_EO_BUSY); +} + +static void enable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 |= CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); +} + +static void disable_bus(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); + + ctl2 &= ~CTL2_ENABLE; + qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); +} + +static void start_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1; + + ctl1 = CTL1_START | CTL1_INTEN | CTL1_STASTRE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, + CTL1_INTEN | CTL1_STASTRE | CTL1_INTEN); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_XMIT | ST_SDAST); + check_running(qts, base_addr); +} + +static void stop_transfer(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &= ~(CTL1_START | CTL1_ACK); + ctl1 |= CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); + ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + g_assert_false(ctl1 & CTL1_STOP); +} + +static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_XMIT | ST_SDAST); + qtest_writeb(qts, base_addr + OFFSET_SDA, byte); +} + +static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) +{ + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, + ST_MODE | ST_SDAST); + return qtest_readb(qts, base_addr + OFFSET_SDA); +} + +static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, + bool recv, bool valid) +{ + uint8_t encoded_addr = (addr << 1) | (recv ? 1 : 0); + uint8_t st; + + qtest_writeb(qts, base_addr + OFFSET_SDA, encoded_addr); + st = qtest_readb(qts, base_addr + OFFSET_ST); + + if (valid) { + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_SDAST | ST_STASTR); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST | ST_STASTR); + } + + qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); + st = qtest_readb(qts, base_addr + OFFSET_ST); + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_SDAST); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST); + } + } else { + if (recv) { + g_assert_cmphex(st, ==, ST_MODE | ST_NEGACK); + } else { + g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_NEGACK); + } + } +} + +static void send_nack(QTestState *qts, uint64_t base_addr) +{ + uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); + + ctl1 &= ~(CTL1_START | CTL1_STOP); + ctl1 |= CTL1_ACK | CTL1_INTEN; + qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); +} + +/* Check the SMBus's status is set correctly when disabled. */ +static void test_disable_bus(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + QTestState *qts = qtest_init("-machine npcm750-evb"); + + disable_bus(qts, base_addr); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST3) & CST3_EO_BUSY); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), ==, 0); + qtest_quit(qts); +} + +/* Check the SMBus returns a NACK for an invalid address. */ +static void test_invalid_addr(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + send_address(qts, base_addr, INVALID_DEVICE_ADDR, false, false); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_ST, ST_NEGACK); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_ST) & ST_NEGACK); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +/* Check the SMBus can send and receive bytes to a device in single mode. */ +static void test_single_mode(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + uint8_t value = 0x60; + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + + /* Sending */ + g_assert_false(qtest_get_irq(qts, irq)); + start_transfer(qts, base_addr); + g_assert_true(qtest_get_irq(qts, irq)); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), ==, value); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + +static void smbus_add_test(const char *name, int index, GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf( + "npcm7xx_smbus[%d]/%s", index, name); + qtest_add_data_func(full_name, (void *)(intptr_t)index, fn); +} +#define add_test(name, td) smbus_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + int i; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + + for (i = 0; i < NR_SMBUS_DEVICES; ++i) { + add_test(disable_bus, i); + add_test(invalid_addr, i); + } + + for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) { + add_test(single_mode, evb_bus_list[i]); + } + + return g_test_run(); +} -- 2.30.0.365.g02bc693789-goog From MAILER-DAEMON Thu Jan 28 20:04:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ID3-0003OL-8l for mharc-qemu-arm@gnu.org; Thu, 28 Jan 2021 20:04:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3EV8TYAgKCCQWUHAOTSHGOOGLE.COMQEMU-ARMNONGNU.ORG@flex--wuhaotsh.bounces.google.com>) id 1l5ID1-0003LU-AI for qemu-arm@nongnu.org; Thu, 28 Jan 2021 20:04:23 -0500 Received: from mail-pg1-x54a.google.com ([2607:f8b0:4864:20::54a]:36940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3EV8TYAgKCCQWUHAOTSHGOOGLE.COMQEMU-ARMNONGNU.ORG@flex--wuhaotsh.bounces.google.com>) id 1l5ICx-0004Yz-FG for qemu-arm@nongnu.org; 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Thu, 28 Jan 2021 17:04:17 -0800 (PST) Date: Thu, 28 Jan 2021 16:58:45 -0800 In-Reply-To: <20210129005845.416272-1-wuhaotsh@google.com> Message-Id: <20210129005845.416272-7-wuhaotsh@google.com> Mime-Version: 1.0 References: <20210129005845.416272-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog Subject: [PATCH v2 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, wuhaotsh@google.com, hskinnemoen@google.com, venture@google.com, dje@google.com, cminyard@mvista.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3EV8TYAgKCCQWUHAOTSHGOOGLE.COMQEMU-ARMNONGNU.ORG@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 01:04:24 -0000 This patch implements the FIFO mode of the SMBus module. In FIFO, the user transmits or receives at most 16 bytes at a time. The FIFO mode allows the module to transmit large amount of data faster than single byte mode. Reviewed-by: Doug Evans Reviewed-by: Tyrong Ting Signed-off-by: Hao Wu Reviewed-by: Corey Minyard Ack-by: Corey Minyard --- hw/i2c/npcm7xx_smbus.c | 342 +++++++++++++++++++++++++++++-- hw/i2c/trace-events | 1 + include/hw/i2c/npcm7xx_smbus.h | 25 +++ tests/qtest/npcm7xx_smbus-test.c | 149 +++++++++++++- 4 files changed, 501 insertions(+), 16 deletions(-) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index c72b6e446f..be3253d251 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -27,7 +27,7 @@ #include "trace.h" #define NPCM7XX_SMBUS_VERSION 1 -#define NPCM7XX_SMBUS_FIFO_EN 0 +#define NPCM7XX_SMBUS_FIFO_EN 1 enum NPCM7xxSMBusCommonRegister { NPCM7XX_SMB_SDA = 0x0, @@ -132,10 +132,41 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_ADDR_EN BIT(7) #define NPCM7XX_ADDR_A(rv) extract8((rv), 0, 6) +/* FIFO Mode Register Fields */ +/* FIF_CTL fields */ +#define NPCM7XX_SMBFIF_CTL_FIFO_EN BIT(4) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY_IE BIT(2) +#define NPCM7XX_SMBFIF_CTL_FAIR_RDY BIT(1) +#define NPCM7XX_SMBFIF_CTL_FAIR_BUSY BIT(0) +/* FIF_CTS fields */ +#define NPCM7XX_SMBFIF_CTS_STR BIT(7) +#define NPCM7XX_SMBFIF_CTS_CLR_FIFO BIT(6) +#define NPCM7XX_SMBFIF_CTS_RFTE_IE BIT(3) +#define NPCM7XX_SMBFIF_CTS_RXF_TXE BIT(1) +/* TXF_CTL fields */ +#define NPCM7XX_SMBTXF_CTL_THR_TXIE BIT(6) +#define NPCM7XX_SMBTXF_CTL_TX_THR(rv) extract8((rv), 0, 5) +/* T_OUT fields */ +#define NPCM7XX_SMBT_OUT_ST BIT(7) +#define NPCM7XX_SMBT_OUT_IE BIT(6) +#define NPCM7XX_SMBT_OUT_CLKDIV(rv) extract8((rv), 0, 6) +/* TXF_STS fields */ +#define NPCM7XX_SMBTXF_STS_TX_THST BIT(6) +#define NPCM7XX_SMBTXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_STS fields */ +#define NPCM7XX_SMBRXF_STS_RX_THST BIT(6) +#define NPCM7XX_SMBRXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) +/* RXF_CTL fields */ +#define NPCM7XX_SMBRXF_CTL_THR_RXIE BIT(6) +#define NPCM7XX_SMBRXF_CTL_LAST BIT(5) +#define NPCM7XX_SMBRXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + #define KEEP_OLD_BIT(o, n, b) (((n) & (~(b))) | ((o) & (b))) #define WRITE_ONE_CLEAR(o, n, b) ((n) & (b) ? (o) & (~(b)) : (o)) #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) +#define NPCM7XX_SMBUS_FIFO_ENABLED(s) (NPCM7XX_SMBUS_FIFO_EN && \ + (s)->fif_ctl & NPCM7XX_SMBFIF_CTL_FIFO_EN) /* Reset values */ #define NPCM7XX_SMB_ST_INIT_VAL 0x00 @@ -150,6 +181,14 @@ enum NPCM7xxSMBusBank1Register { #define NPCM7XX_SMB_ADDR_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLLT_INIT_VAL 0x00 #define NPCM7XX_SMB_SCLHT_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_FIF_CTS_INIT_VAL 0x00 +#define NPCM7XX_SMB_FAIR_PER_INIT_VAL 0x00 +#define NPCM7XX_SMB_TXF_CTL_INIT_VAL 0x00 +#define NPCM7XX_SMB_T_OUT_INIT_VAL 0x3f +#define NPCM7XX_SMB_TXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_STS_INIT_VAL 0x00 +#define NPCM7XX_SMB_RXF_CTL_INIT_VAL 0x01 static uint8_t npcm7xx_smbus_get_version(void) { @@ -169,7 +208,13 @@ static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && s->st & NPCM7XX_SMBST_SDAST) || (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && - s->cst3 & NPCM7XX_SMBCST3_EO_BUSY)); + s->cst3 & NPCM7XX_SMBCST3_EO_BUSY) || + (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE && + s->rxf_sts & NPCM7XX_SMBRXF_STS_RX_THST) || + (s->txf_ctl & NPCM7XX_SMBTXF_CTL_THR_TXIE && + s->txf_sts & NPCM7XX_SMBTXF_STS_TX_THST) || + (s->fif_cts & NPCM7XX_SMBFIF_CTS_RFTE_IE && + s->fif_cts & NPCM7XX_SMBFIF_CTS_RXF_TXE)); if (level) { s->cst2 |= NPCM7XX_SMBCST2_INTSTS; @@ -187,6 +232,13 @@ static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) s->status = NPCM7XX_SMBUS_STATUS_NEGACK; } +static void npcm7xx_smbus_clear_buffer(NPCM7xxSMBusState *s) +{ + s->fif_cts &= ~NPCM7XX_SMBFIF_CTS_RXF_TXE; + s->txf_sts = 0; + s->rxf_sts = 0; +} + static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) { int rv = i2c_send(s->bus, value); @@ -195,6 +247,15 @@ static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) npcm7xx_smbus_nack(s); } else { s->st |= NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + if (NPCM7XX_SMBTXF_STS_TX_BYTES(s->txf_sts) == + NPCM7XX_SMBTXF_CTL_TX_THR(s->txf_ctl)) { + s->txf_sts = NPCM7XX_SMBTXF_STS_TX_THST; + } else { + s->txf_sts = 0; + } + } } trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); npcm7xx_smbus_update_irq(s); @@ -213,6 +274,67 @@ static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) npcm7xx_smbus_update_irq(s); } +static void npcm7xx_smbus_recv_fifo(NPCM7xxSMBusState *s) +{ + uint8_t expected_bytes = NPCM7XX_SMBRXF_CTL_RX_THR(s->rxf_ctl); + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + uint8_t pos; + + if (received_bytes == expected_bytes) { + return; + } + + while (received_bytes < expected_bytes && + received_bytes < NPCM7XX_SMBUS_FIFO_SIZE) { + pos = (s->rx_cur + received_bytes) % NPCM7XX_SMBUS_FIFO_SIZE; + s->rx_fifo[pos] = i2c_recv(s->bus); + trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), + s->rx_fifo[pos]); + ++received_bytes; + } + + trace_npcm7xx_smbus_recv_fifo((DEVICE(s)->canonical_path), + received_bytes, expected_bytes); + s->rxf_sts = received_bytes; + if (unlikely(received_bytes < expected_bytes)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid rx_thr value: 0x%02x\n", + DEVICE(s)->canonical_path, expected_bytes); + return; + } + + s->rxf_sts |= NPCM7XX_SMBRXF_STS_RX_THST; + if (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_LAST) { + trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); + i2c_nack(s->bus); + s->rxf_ctl &= ~NPCM7XX_SMBRXF_CTL_LAST; + } + if (received_bytes == NPCM7XX_SMBUS_FIFO_SIZE) { + s->st |= NPCM7XX_SMBST_SDAST; + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + } else if (!(s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE)) { + s->st |= NPCM7XX_SMBST_SDAST; + } else { + s->st &= ~NPCM7XX_SMBST_SDAST; + } + npcm7xx_smbus_update_irq(s); +} + +static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) +{ + uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); + + if (received_bytes == 0) { + npcm7xx_smbus_recv_fifo(s); + return; + } + + s->sda = s->rx_fifo[s->rx_cur]; + s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; + --s->rxf_sts; + npcm7xx_smbus_update_irq(s); +} + static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) { /* @@ -226,6 +348,9 @@ static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) if (available) { s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; s->cst |= NPCM7XX_SMBCST_BUSY; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; + } } else { s->st &= ~NPCM7XX_SMBST_MODE; s->cst &= ~NPCM7XX_SMBCST_BUSY; @@ -277,7 +402,15 @@ static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) s->st |= NPCM7XX_SMBST_SDAST; } } else if (recv) { - npcm7xx_smbus_recv_byte(s); + s->st |= NPCM7XX_SMBST_SDAST; + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } + } else if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + s->st |= NPCM7XX_SMBST_SDAST; + s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; } npcm7xx_smbus_update_irq(s); } @@ -320,11 +453,31 @@ static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) switch (s->status) { case NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE: - npcm7xx_smbus_execute_stop(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) <= 1) { + npcm7xx_smbus_execute_stop(s); + } + if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) == 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read to SDA with an empty rx-fifo buffer, " + "result undefined: %u\n", + DEVICE(s)->canonical_path, s->sda); + break; + } + npcm7xx_smbus_read_byte_fifo(s); + value = s->sda; + } else { + npcm7xx_smbus_execute_stop(s); + } break; case NPCM7XX_SMBUS_STATUS_RECEIVING: - npcm7xx_smbus_recv_byte(s); + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_read_byte_fifo(s); + value = s->sda; + } else { + npcm7xx_smbus_recv_byte(s); + } break; default: @@ -370,8 +523,12 @@ static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) } if (value & NPCM7XX_SMBST_STASTR && - s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { - npcm7xx_smbus_recv_byte(s); + s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { + npcm7xx_smbus_recv_fifo(s); + } else { + npcm7xx_smbus_recv_byte(s); + } } npcm7xx_smbus_update_irq(s); @@ -417,6 +574,7 @@ static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) s->st = 0; s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); s->cst = 0; + npcm7xx_smbus_clear_buffer(s); } } @@ -429,6 +587,70 @@ static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) NPCM7XX_SMBCTL3_SCL_LVL | NPCM7XX_SMBCTL3_SDA_LVL); } +static void npcm7xx_smbus_write_fif_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_ctl = value; + + new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_RDY); + new_ctl = WRITE_ONE_CLEAR(new_ctl, value, NPCM7XX_SMBFIF_CTL_FAIR_RDY); + new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_BUSY); + s->fif_ctl = new_ctl; +} + +static void npcm7xx_smbus_write_fif_cts(NPCM7xxSMBusState *s, uint8_t value) +{ + s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_STR); + s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_RXF_TXE); + s->fif_cts = KEEP_OLD_BIT(value, s->fif_cts, NPCM7XX_SMBFIF_CTS_RFTE_IE); + + if (value & NPCM7XX_SMBFIF_CTS_CLR_FIFO) { + npcm7xx_smbus_clear_buffer(s); + } +} + +static void npcm7xx_smbus_write_txf_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + s->txf_ctl = value; +} + +static void npcm7xx_smbus_write_t_out(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_t_out = value; + + if ((value & NPCM7XX_SMBT_OUT_ST) || (!(s->t_out & NPCM7XX_SMBT_OUT_ST))) { + new_t_out &= ~NPCM7XX_SMBT_OUT_ST; + } else { + new_t_out |= NPCM7XX_SMBT_OUT_ST; + } + + s->t_out = new_t_out; +} + +static void npcm7xx_smbus_write_txf_sts(NPCM7xxSMBusState *s, uint8_t value) +{ + s->txf_sts = WRITE_ONE_CLEAR(s->txf_sts, value, NPCM7XX_SMBTXF_STS_TX_THST); +} + +static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t value) +{ + if (value & NPCM7XX_SMBRXF_STS_RX_THST) { + s->rxf_sts &= ~NPCM7XX_SMBRXF_STS_RX_THST; + if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_fifo(s); + } + } +} + +static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t value) +{ + uint8_t new_ctl = value; + + if (!(value & NPCM7XX_SMBRXF_CTL_LAST)) { + new_ctl = KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_LAST); + } + s->rxf_ctl = new_ctl; +} + static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) { NPCM7xxSMBusState *s = opaque; @@ -485,9 +707,41 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + value = s->fif_cts; + break; + + case NPCM7XX_SMB_FAIR_PER: + value = s->fair_per; + break; + + case NPCM7XX_SMB_TXF_CTL: + value = s->txf_ctl; + break; + + case NPCM7XX_SMB_T_OUT: + value = s->t_out; + break; + + case NPCM7XX_SMB_TXF_STS: + value = s->txf_sts; + break; + + case NPCM7XX_SMB_RXF_STS: + value = s->rxf_sts; + break; + + case NPCM7XX_SMB_RXF_CTL: + value = s->rxf_ctl; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -535,6 +789,10 @@ static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size) value = s->scllt; break; + case NPCM7XX_SMB_FIF_CTL: + value = s->fif_ctl; + break; + case NPCM7XX_SMB_SCLHT: value = s->sclht; break; @@ -616,9 +874,41 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, default: if (bank) { /* Bank 1 */ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", - DEVICE(s)->canonical_path, offset); + switch (offset) { + case NPCM7XX_SMB_FIF_CTS: + npcm7xx_smbus_write_fif_cts(s, value); + break; + + case NPCM7XX_SMB_FAIR_PER: + s->fair_per = value; + break; + + case NPCM7XX_SMB_TXF_CTL: + npcm7xx_smbus_write_txf_ctl(s, value); + break; + + case NPCM7XX_SMB_T_OUT: + npcm7xx_smbus_write_t_out(s, value); + break; + + case NPCM7XX_SMB_TXF_STS: + npcm7xx_smbus_write_txf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_STS: + npcm7xx_smbus_write_rxf_sts(s, value); + break; + + case NPCM7XX_SMB_RXF_CTL: + npcm7xx_smbus_write_rxf_ctl(s, value); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", + DEVICE(s)->canonical_path, offset); + break; + } } else { /* Bank 0 */ switch (offset) { @@ -666,6 +956,10 @@ static void npcm7xx_smbus_write(void *opaque, hwaddr offset, uint64_t value, s->scllt = value; break; + case NPCM7XX_SMB_FIF_CTL: + npcm7xx_smbus_write_fif_ctl(s, value); + break; + case NPCM7XX_SMB_SCLHT: s->sclht = value; break; @@ -712,7 +1006,18 @@ static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type) s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; + s->fif_ctl = NPCM7XX_SMB_FIF_CTL_INIT_VAL; + s->fif_cts = NPCM7XX_SMB_FIF_CTS_INIT_VAL; + s->fair_per = NPCM7XX_SMB_FAIR_PER_INIT_VAL; + s->txf_ctl = NPCM7XX_SMB_TXF_CTL_INIT_VAL; + s->t_out = NPCM7XX_SMB_T_OUT_INIT_VAL; + s->txf_sts = NPCM7XX_SMB_TXF_STS_INIT_VAL; + s->rxf_sts = NPCM7XX_SMB_RXF_STS_INIT_VAL; + s->rxf_ctl = NPCM7XX_SMB_RXF_CTL_INIT_VAL; + + npcm7xx_smbus_clear_buffer(s); s->status = NPCM7XX_SMBUS_STATUS_IDLE; + s->rx_cur = 0; } static void npcm7xx_smbus_hold_reset(Object *obj) @@ -754,6 +1059,17 @@ static const VMStateDescription vmstate_npcm7xx_smbus = { VMSTATE_UINT8_ARRAY(addr, NPCM7xxSMBusState, NPCM7XX_SMBUS_NR_ADDRS), VMSTATE_UINT8(scllt, NPCM7xxSMBusState), VMSTATE_UINT8(sclht, NPCM7xxSMBusState), + VMSTATE_UINT8(fif_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8(fif_cts, NPCM7xxSMBusState), + VMSTATE_UINT8(fair_per, NPCM7xxSMBusState), + VMSTATE_UINT8(txf_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8(t_out, NPCM7xxSMBusState), + VMSTATE_UINT8(txf_sts, NPCM7xxSMBusState), + VMSTATE_UINT8(rxf_sts, NPCM7xxSMBusState), + VMSTATE_UINT8(rxf_ctl, NPCM7xxSMBusState), + VMSTATE_UINT8_ARRAY(rx_fifo, NPCM7xxSMBusState, + NPCM7XX_SMBUS_FIFO_SIZE), + VMSTATE_UINT8(rx_cur, NPCM7xxSMBusState), VMSTATE_END_OF_LIST(), }, }; diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index c3bb70ad04..82fe6f965f 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -25,3 +25,4 @@ npcm7xx_smbus_send_byte(const char *id, uint8_t value, int success) "%s send byt npcm7xx_smbus_recv_byte(const char *id, uint8_t value) "%s recv byte: 0x%02x" npcm7xx_smbus_stop(const char *id) "%s stopping" npcm7xx_smbus_nack(const char *id) "%s nacking" +npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected) "%s recv fifo: received %u, expected %u" diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index b9761a6993..7d59ee917e 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -27,6 +27,9 @@ */ #define NPCM7XX_SMBUS_NR_ADDRS 10 +/* Size of the FIFO buffer. */ +#define NPCM7XX_SMBUS_FIFO_SIZE 16 + typedef enum NPCM7xxSMBusStatus { NPCM7XX_SMBUS_STATUS_IDLE, NPCM7XX_SMBUS_STATUS_SENDING, @@ -53,6 +56,16 @@ typedef enum NPCM7xxSMBusStatus { * @addr: The SMBus module's own addresses on the I2C bus. * @scllt: The SCL low time register. * @sclht: The SCL high time register. + * @fif_ctl: The FIFO control register. + * @fif_cts: The FIFO control status register. + * @fair_per: The fair preriod register. + * @txf_ctl: The transmit FIFO control register. + * @t_out: The SMBus timeout register. + * @txf_sts: The transmit FIFO status register. + * @rxf_sts: The receive FIFO status register. + * @rxf_ctl: The receive FIFO control register. + * @rx_fifo: The FIFO buffer for receiving in FIFO mode. + * @rx_cur: The current position of rx_fifo. * @status: The current status of the SMBus. */ typedef struct NPCM7xxSMBusState { @@ -78,6 +91,18 @@ typedef struct NPCM7xxSMBusState { uint8_t scllt; uint8_t sclht; + uint8_t fif_ctl; + uint8_t fif_cts; + uint8_t fair_per; + uint8_t txf_ctl; + uint8_t t_out; + uint8_t txf_sts; + uint8_t rxf_sts; + uint8_t rxf_ctl; + + uint8_t rx_fifo[NPCM7XX_SMBUS_FIFO_SIZE]; + uint8_t rx_cur; + NPCM7xxSMBusStatus status; } NPCM7xxSMBusState; diff --git a/tests/qtest/npcm7xx_smbus-test.c b/tests/qtest/npcm7xx_smbus-test.c index 4594b107df..4f9f493872 100644 --- a/tests/qtest/npcm7xx_smbus-test.c +++ b/tests/qtest/npcm7xx_smbus-test.c @@ -132,6 +132,44 @@ enum NPCM7xxSMBusBank1Register { #define ADDR_EN BIT(7) #define ADDR_A(rv) extract8((rv), 0, 6) +/* FIF_CTL fields */ +#define FIF_CTL_FIFO_EN BIT(4) + +/* FIF_CTS fields */ +#define FIF_CTS_CLR_FIFO BIT(6) +#define FIF_CTS_RFTE_IE BIT(3) +#define FIF_CTS_RXF_TXE BIT(1) + +/* TXF_CTL fields */ +#define TXF_CTL_THR_TXIE BIT(6) +#define TXF_CTL_TX_THR(rv) extract8((rv), 0, 5) + +/* TXF_STS fields */ +#define TXF_STS_TX_THST BIT(6) +#define TXF_STS_TX_BYTES(rv) extract8((rv), 0, 5) + +/* RXF_CTL fields */ +#define RXF_CTL_THR_RXIE BIT(6) +#define RXF_CTL_LAST BIT(5) +#define RXF_CTL_RX_THR(rv) extract8((rv), 0, 5) + +/* RXF_STS fields */ +#define RXF_STS_RX_THST BIT(6) +#define RXF_STS_RX_BYTES(rv) extract8((rv), 0, 5) + + +static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) +{ + uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3); + + if (bank) { + ctl3 |= CTL3_BNK_SEL; + } else { + ctl3 &= ~CTL3_BNK_SEL; + } + + qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); +} static void check_running(QTestState *qts, uint64_t base_addr) { @@ -203,10 +241,33 @@ static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) qtest_writeb(qts, base_addr + OFFSET_SDA, byte); } +static bool check_recv(QTestState *qts, uint64_t base_addr) +{ + uint8_t st, fif_ctl, rxf_ctl, rxf_sts; + bool fifo; + + st = qtest_readb(qts, base_addr + OFFSET_ST); + choose_bank(qts, base_addr, 0); + fif_ctl = qtest_readb(qts, base_addr + OFFSET_FIF_CTL); + fifo = fif_ctl & FIF_CTL_FIFO_EN; + if (!fifo) { + return st == (ST_MODE | ST_SDAST); + } + + choose_bank(qts, base_addr, 1); + rxf_ctl = qtest_readb(qts, base_addr + OFFSET_RXF_CTL); + rxf_sts = qtest_readb(qts, base_addr + OFFSET_RXF_STS); + + if ((rxf_ctl & RXF_CTL_THR_RXIE) && RXF_STS_RX_BYTES(rxf_sts) < 16) { + return st == ST_MODE; + } else { + return st == (ST_MODE | ST_SDAST); + } +} + static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) { - g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, - ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); return qtest_readb(qts, base_addr + OFFSET_SDA); } @@ -229,7 +290,7 @@ static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); st = qtest_readb(qts, base_addr + OFFSET_ST); if (recv) { - g_assert_cmphex(st, ==, ST_MODE | ST_SDAST); + g_assert_true(check_recv(qts, base_addr)); } else { g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST); } @@ -251,6 +312,29 @@ static void send_nack(QTestState *qts, uint64_t base_addr) qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); } +static void start_fifo_mode(QTestState *qts, uint64_t base_addr) +{ + choose_bank(qts, base_addr, 0); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTL, FIF_CTL_FIFO_EN); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTL) & + FIF_CTL_FIFO_EN); + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, + FIF_CTS_CLR_FIFO | FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_FIF_CTS), ==, + FIF_CTS_RFTE_IE); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), ==, 0); + g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), ==, 0); +} + +static void start_recv_fifo(QTestState *qts, uint64_t base_addr, uint8_t bytes) +{ + choose_bank(qts, base_addr, 1); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0); + qtest_writeb(qts, base_addr + OFFSET_RXF_CTL, + RXF_CTL_THR_RXIE | RXF_CTL_LAST | bytes); +} + /* Check the SMBus's status is set correctly when disabled. */ static void test_disable_bus(gconstpointer data) { @@ -324,6 +408,64 @@ static void test_single_mode(gconstpointer data) qtest_quit(qts); } +/* Check the SMBus can send and receive bytes in FIFO mode. */ +static void test_fifo_mode(gconstpointer data) +{ + intptr_t index = (intptr_t)data; + uint64_t base_addr = SMBUS_ADDR(index); + int irq = SMBUS_IRQ(index); + uint8_t value = 0x60; + QTestState *qts = qtest_init("-machine npcm750-evb"); + + qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); + enable_bus(qts, base_addr); + start_fifo_mode(qts, base_addr); + g_assert_false(qtest_get_irq(qts, irq)); + + /* Sending */ + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + choose_bank(qts, base_addr, 1); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, TXF_CTL_THR_TXIE); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + send_byte(qts, base_addr, value); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_TXF_STS) & + TXF_STS_TX_THST); + g_assert_cmpuint(TXF_STS_TX_BYTES( + qtest_readb(qts, base_addr + OFFSET_TXF_STS)), ==, 0); + g_assert_true(qtest_get_irq(qts, irq)); + stop_transfer(qts, base_addr); + check_stopped(qts, base_addr); + + /* Receiving */ + start_fifo_mode(qts, base_addr); + start_transfer(qts, base_addr); + send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); + send_byte(qts, base_addr, TMP105_REG_CONFIG); + start_transfer(qts, base_addr); + qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, FIF_CTS_RXF_TXE); + start_recv_fifo(qts, base_addr, 1); + send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); + g_assert_false(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & + FIF_CTS_RXF_TXE); + g_assert_true(qtest_readb(qts, base_addr + OFFSET_RXF_STS) & + RXF_STS_RX_THST); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 1); + send_nack(qts, base_addr); + stop_transfer(qts, base_addr); + check_running(qts, base_addr); + g_assert_cmphex(recv_byte(qts, base_addr), ==, value); + g_assert_cmpuint(RXF_STS_RX_BYTES( + qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 0); + check_stopped(qts, base_addr); + qtest_quit(qts); +} + static void smbus_add_test(const char *name, int index, GTestDataFunc fn) { g_autofree char *full_name = g_strdup_printf( @@ -346,6 +488,7 @@ int main(int argc, char **argv) for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) { add_test(single_mode, evb_bus_list[i]); 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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id d17sm4591500wma.2.2021.01.28.23.49.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 23:49:56 -0800 (PST) Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: "Dr. David Alan Gilbert" Cc: Keqian Zhu , Kirti Wankhede , Alex Williamson , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , Igor Mammedov , wanghaibin.wang@huawei.com, Zenghui Yu , jiangkunkun@huawei.com References: <20210111073439.20236-1-zhukeqian1@huawei.com> <20210128200223.GJ2951@work-vm> From: Paolo Bonzini Message-ID: Date: Fri, 29 Jan 2021 08:49:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210128200223.GJ2951@work-vm> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 07:50:04 -0000 On 28/01/21 21:02, Dr. David Alan Gilbert wrote: > * Paolo Bonzini (pbonzini@redhat.com) wrote: >> On 11/01/21 08:34, Keqian Zhu wrote: >>> +static void vfio_listener_log_start(MemoryListener *listener, >>> + MemoryRegionSection *section, >>> + int old, int new) >>> +{ >>> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >>> + >>> + vfio_set_dirty_page_tracking(container, true); >>> +} >> >> This would enable dirty page tracking also just for having a framebuffer >> (DIRTY_MEMORY_VGA). Technically it would be correct, but it would also be >> more heavyweight than expected. > > Wouldn't that only happen on emulated video devices? Yes, but still it's not impossible to have both an emulated VGA and an assigned GPU or vGPU. >> In order to only cover live migration, you can use the log_global_start and >> log_global_stop callbacks instead. >> >> If you want to use log_start and log_stop, you need to add respectively >> >> if (old != 0) { >> return; >> } >> >> and >> >> if (new != 0) { >> return; >> } > > Why 0, wouldn't you be checking for DIRTY_LOG_MIGRATION somewhere? Actually thinking more about it log_start/log_stop are just wrong, because they would be called many times, for each MemoryRegionSection. Paolo From MAILER-DAEMON Fri Jan 29 03:15:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5OwR-00055l-Re for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 03:15:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5OwO-00054n-Ka for qemu-arm@nongnu.org; Fri, 29 Jan 2021 03:15:40 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:31371) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5OwL-0002uh-19 for qemu-arm@nongnu.org; Fri, 29 Jan 2021 03:15:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611908136; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Le1c974EV5lf0TZoOdh+swW2cPXQowAnSWUpwRUymgk=; b=NjI+WPPBW3Hiw4SXQRb1ST9aB483SxItdtmx7wNkg4HnGFvX+0Qy1P6BGO8U2VFw0+ORv6 7aLKoZIz2TlIiJW37RGIGcCVMLUr5tOukGfPXmQRrKOP9dA31N1bWeDmO9CORokCCwdroz mPERXsfuEtV/0pcVwT/7tDNRmNvtm7E= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-278-ygnGwcRtMEC3ImOhTBSR8g-1; Fri, 29 Jan 2021 03:15:34 -0500 X-MC-Unique: ygnGwcRtMEC3ImOhTBSR8g-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BCEEB81A2BD; Fri, 29 Jan 2021 08:15:31 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-113-224.ams2.redhat.com [10.36.113.224]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2745571C9F; Fri, 29 Jan 2021 08:15:21 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 8A3E6113865F; Fri, 29 Jan 2021 09:15:19 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, kraxel@redhat.com, jsnow@redhat.com, kwolf@redhat.com, mreitz@redhat.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, jcd@tribudubois.net, peter.chubb@nicta.com.au, andrew.smirnov@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, chouteau@adacore.com, frederic.konrad@adacore.com, quintela@redhat.com, dgilbert@redhat.com, qemu-arm@nongnu.org, qemu-block@nongnu.org, berrange@redhat.com, ehabkost@redhat.com Subject: [PATCH RFC 0/1] QOM type names and QAPI Date: Fri, 29 Jan 2021 09:15:18 +0100 Message-Id: <20210129081519.3848145-1-armbru@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" Received-SPF: pass client-ip=63.128.21.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 08:15:40 -0000 QAPI has naming rules. docs/devel/qapi-code-gen.txt: === Naming rules and reserved names === All names must begin with a letter, and contain only ASCII letters, digits, hyphen, and underscore. There are two exceptions: enum values may start with a digit, and names that are downstream extensions (see section Downstream extensions) start with underscore. [More on reserved names, upper vs. lower case, '-' vs. '_'...] The generator enforces the rules. Naming rules help in at least three ways: 1. They help with keeping names in interfaces consistent and predictable. 2. They make avoiding collisions with the users' names in the generator simpler. 3. They enable quote-less, evolvable syntax. For instance, keyval_parse() syntax consists of names, values, and special characters ',', '=', '.' Since names cannot contain special characters, there is no need for quoting[*]. Simple. Values are unrestricted, but only ',' is special there. We quote it by doubling. Together, we get exactly the same quoting as in QemuOpts. This is a feature. If we ever decice to extend key syntax, we have plenty of special characters to choose from. This is also a feature. Both features rely on naming rules. QOM has no naming rules whatsoever. Actual names aren't nearly as bad as they could be. Still, there are plenty of "funny" names. This will become a problem when we * Switch from QemuOpts to keyval_parse() QOM type names must not contain special characters, unless we introduce more quoting. Which we shouldn't, because the value of special characters in names is negligible compared to the hassle of having to quote them. * QAPIfy (the compile-time static parts of) QOM QOM type names become QAPI enum values. They must conform to QAPI naming rules. Adopting QAPI naming rules for QOM type names takes care of both. Let's review the existing offenders. 1. We have a few type names containing ',', and one containing ' '. The former require QemuOpts / keyval quoting (double the comma), the latter requires shell quoting. There is no excuse for making our users remember and do such crap. PATCH 1 eliminates it. 2. We have some 550 type names containing '.'. QAPI's naming rules could be relaxed to accept '.', but keyval_parse()'s can't. Aside: I wish keyval_parse() would use '/' instead of '.', but it's designed to be compatible to the block layer's existing use of dotted keys (shoehorned into QemuOpts). 3. We have six type names containing '+'. Four of them also contain '.'. Naming rules could be relaxed to accept '+'. I'm not sure it's worthwhile. 4. We have 19 names starting with a digit. Three of them also contain '.'. Leading digit is okay as QAPI enum, not okay as keyval_parse() key fragment. We can either rename these types, or make keyval_parse() a bit less strict. Of the type names containing '.' or '+'[**], 293 are CPUs, 107 are machines, and 150 are something else. 48 of them can be plugged with -device, all s390x or spapr CPUs. Can we get rid of '.'? I figure we could keep old names as deprecated aliases if we care. Perhaps just the ones that can be plugged with -device. [*] Paolo's "[PATCH 04/25] keyval: accept escaped commas in implied option" provides for comma-quoting. I'm ignoring it here for brevity. I assure you it doesn't weaken my argument. [**] They are: 603e_v1.1-powerpc-cpu 603e_v1.1-powerpc64-cpu 603e_v1.2-powerpc-cpu 603e_v1.2-powerpc64-cpu 603e_v1.3-powerpc-cpu 603e_v1.3-powerpc64-cpu 603e_v1.4-powerpc-cpu 603e_v1.4-powerpc64-cpu 603e_v2.2-powerpc-cpu 603e_v2.2-powerpc64-cpu 603e_v4.1-powerpc-cpu 603e_v4.1-powerpc64-cpu 604e_v1.0-powerpc-cpu 604e_v1.0-powerpc64-cpu 604e_v2.2-powerpc-cpu 604e_v2.2-powerpc64-cpu 604e_v2.4-powerpc-cpu 604e_v2.4-powerpc64-cpu 7400_v1.0-powerpc-cpu 7400_v1.0-powerpc64-cpu 7400_v1.1-powerpc-cpu 7400_v1.1-powerpc64-cpu 7400_v2.0-powerpc-cpu 7400_v2.0-powerpc64-cpu 7400_v2.1-powerpc-cpu 7400_v2.1-powerpc64-cpu 7400_v2.2-powerpc-cpu 7400_v2.2-powerpc64-cpu 7400_v2.6-powerpc-cpu 7400_v2.6-powerpc64-cpu 7400_v2.7-powerpc-cpu 7400_v2.7-powerpc64-cpu 7400_v2.8-powerpc-cpu 7400_v2.8-powerpc64-cpu 7400_v2.9-powerpc-cpu 7400_v2.9-powerpc64-cpu 740_v1.0-powerpc-cpu 740_v1.0-powerpc64-cpu 740_v2.0-powerpc-cpu 740_v2.0-powerpc64-cpu 740_v2.1-powerpc-cpu 740_v2.1-powerpc64-cpu 740_v2.2-powerpc-cpu 740_v2.2-powerpc64-cpu 740_v3.0-powerpc-cpu 740_v3.0-powerpc64-cpu 740_v3.1-powerpc-cpu 740_v3.1-powerpc64-cpu 7410_v1.0-powerpc-cpu 7410_v1.0-powerpc64-cpu 7410_v1.1-powerpc-cpu 7410_v1.1-powerpc64-cpu 7410_v1.2-powerpc-cpu 7410_v1.2-powerpc64-cpu 7410_v1.3-powerpc-cpu 7410_v1.3-powerpc64-cpu 7410_v1.4-powerpc-cpu 7410_v1.4-powerpc64-cpu 7441_v2.1-powerpc-cpu 7441_v2.1-powerpc64-cpu 7441_v2.10-powerpc-cpu 7441_v2.10-powerpc64-cpu 7441_v2.3-powerpc-cpu 7441_v2.3-powerpc64-cpu 7445_v1.0-powerpc-cpu 7445_v1.0-powerpc64-cpu 7445_v2.1-powerpc-cpu 7445_v2.1-powerpc64-cpu 7445_v3.2-powerpc-cpu 7445_v3.2-powerpc64-cpu 7445_v3.3-powerpc-cpu 7445_v3.3-powerpc64-cpu 7445_v3.4-powerpc-cpu 7445_v3.4-powerpc64-cpu 7447_v1.0-powerpc-cpu 7447_v1.0-powerpc64-cpu 7447_v1.1-powerpc-cpu 7447_v1.1-powerpc64-cpu 7447a_v1.0-powerpc-cpu 7447a_v1.0-powerpc64-cpu 7447a_v1.1-powerpc-cpu 7447a_v1.1-powerpc64-cpu 7447a_v1.2-powerpc-cpu 7447a_v1.2-powerpc64-cpu 7448_v1.0-powerpc-cpu 7448_v1.0-powerpc64-cpu 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745_v1.0-powerpc64-cpu 745_v1.1-powerpc-cpu 745_v1.1-powerpc64-cpu 745_v2.0-powerpc-cpu 745_v2.0-powerpc64-cpu 745_v2.1-powerpc-cpu 745_v2.1-powerpc64-cpu 745_v2.2-powerpc-cpu 745_v2.2-powerpc64-cpu 745_v2.3-powerpc-cpu 745_v2.3-powerpc64-cpu 745_v2.4-powerpc-cpu 745_v2.4-powerpc64-cpu 745_v2.5-powerpc-cpu 745_v2.5-powerpc64-cpu 745_v2.6-powerpc-cpu 745_v2.6-powerpc64-cpu 745_v2.7-powerpc-cpu 745_v2.7-powerpc64-cpu 745_v2.8-powerpc-cpu 745_v2.8-powerpc64-cpu 750_v1.0-powerpc-cpu 750_v1.0-powerpc64-cpu 750_v2.0-powerpc-cpu 750_v2.0-powerpc64-cpu 750_v2.1-powerpc-cpu 750_v2.1-powerpc64-cpu 750_v2.2-powerpc-cpu 750_v2.2-powerpc64-cpu 750_v3.0-powerpc-cpu 750_v3.0-powerpc64-cpu 750_v3.1-powerpc-cpu 750_v3.1-powerpc64-cpu 750cl_v1.0-powerpc-cpu 750cl_v1.0-powerpc64-cpu 750cl_v2.0-powerpc-cpu 750cl_v2.0-powerpc64-cpu 750cx_v1.0-powerpc-cpu 750cx_v1.0-powerpc64-cpu 750cx_v2.0-powerpc-cpu 750cx_v2.0-powerpc64-cpu 750cx_v2.1-powerpc-cpu 750cx_v2.1-powerpc64-cpu 750cx_v2.2-powerpc-cpu 750cx_v2.2-powerpc64-cpu 750cxe_v2.1-powerpc-cpu 750cxe_v2.1-powerpc64-cpu 750cxe_v2.2-powerpc-cpu 750cxe_v2.2-powerpc64-cpu 750cxe_v2.3-powerpc-cpu 750cxe_v2.3-powerpc64-cpu 750cxe_v2.4-powerpc-cpu 750cxe_v2.4-powerpc64-cpu 750cxe_v2.4b-powerpc-cpu 750cxe_v2.4b-powerpc64-cpu 750cxe_v3.0-powerpc-cpu 750cxe_v3.0-powerpc64-cpu 750cxe_v3.1-powerpc-cpu 750cxe_v3.1-powerpc64-cpu 750cxe_v3.1b-powerpc-cpu 750cxe_v3.1b-powerpc64-cpu 750fx_v1.0-powerpc-cpu 750fx_v1.0-powerpc64-cpu 750fx_v2.0-powerpc-cpu 750fx_v2.0-powerpc64-cpu 750fx_v2.1-powerpc-cpu 750fx_v2.1-powerpc64-cpu 750fx_v2.2-powerpc-cpu 750fx_v2.2-powerpc64-cpu 750fx_v2.3-powerpc-cpu 750fx_v2.3-powerpc64-cpu 750gx_v1.0-powerpc-cpu 750gx_v1.0-powerpc64-cpu 750gx_v1.1-powerpc-cpu 750gx_v1.1-powerpc64-cpu 750gx_v1.2-powerpc-cpu 750gx_v1.2-powerpc64-cpu 750l_v2.0-powerpc-cpu 750l_v2.0-powerpc64-cpu 750l_v2.1-powerpc-cpu 750l_v2.1-powerpc64-cpu 750l_v2.2-powerpc-cpu 750l_v2.2-powerpc64-cpu 750l_v3.0-powerpc-cpu 750l_v3.0-powerpc64-cpu 750l_v3.2-powerpc-cpu 750l_v3.2-powerpc64-cpu 755_v1.0-powerpc-cpu 755_v1.0-powerpc64-cpu 755_v1.1-powerpc-cpu 755_v1.1-powerpc64-cpu 755_v2.0-powerpc-cpu 755_v2.0-powerpc64-cpu 755_v2.1-powerpc-cpu 755_v2.1-powerpc64-cpu 755_v2.2-powerpc-cpu 755_v2.2-powerpc64-cpu 755_v2.3-powerpc-cpu 755_v2.3-powerpc64-cpu 755_v2.4-powerpc-cpu 755_v2.4-powerpc64-cpu 755_v2.5-powerpc-cpu 755_v2.5-powerpc64-cpu 755_v2.6-powerpc-cpu 755_v2.6-powerpc64-cpu 755_v2.7-powerpc-cpu 755_v2.7-powerpc64-cpu 755_v2.8-powerpc-cpu 755_v2.8-powerpc64-cpu 970_v2.2-powerpc64-cpu 970_v2.2-spapr-cpu-core 970fx_v1.0-powerpc64-cpu 970fx_v2.0-powerpc64-cpu 970fx_v2.1-powerpc64-cpu 970fx_v3.0-powerpc64-cpu 970fx_v3.1-powerpc64-cpu 970mp_v1.0-powerpc64-cpu 970mp_v1.0-spapr-cpu-core 970mp_v1.1-powerpc64-cpu 970mp_v1.1-spapr-cpu-core ALTR.timer Sun-UltraSparc-IIIi+-sparc64-cpu Sun-UltraSparc-IV+-sparc64-cpu arm.cortex-a9-global-timer aspeed.fmc-ast2400 aspeed.fmc-ast2500 aspeed.fmc-ast2600 aspeed.gpio aspeed.gpio-ast2400 aspeed.gpio-ast2500 aspeed.gpio-ast2600 aspeed.gpio-ast2600-1_8v aspeed.i2c aspeed.i2c-ast2400 aspeed.i2c-ast2500 aspeed.i2c-ast2600 aspeed.rtc aspeed.scu aspeed.scu-ast2400 aspeed.scu-ast2500 aspeed.scu-ast2600 aspeed.sdhci aspeed.sdmc aspeed.sdmc-ast2400 aspeed.sdmc-ast2500 aspeed.sdmc-ast2600 aspeed.smc aspeed.smc-ast2400 aspeed.spi1-ast2400 aspeed.spi1-ast2500 aspeed.spi1-ast2600 aspeed.spi2-ast2500 aspeed.spi2-ast2600 aspeed.timer aspeed.timer-ast2400 aspeed.timer-ast2500 aspeed.timer-ast2600 aspeed.vic aspeed.wdt aspeed.wdt-ast2400 aspeed.wdt-ast2500 aspeed.wdt-ast2600 aspeed.xdma cadence.sdhci cfi.pflash01 cfi.pflash02 exynos4210.clk exynos4210.combiner exynos4210.fimd exynos4210.gic exynos4210.i2c exynos4210.irq_gate exynos4210.mct exynos4210.pmu exynos4210.pwm exynos4210.rng exynos4210.rtc exynos4210.uart imx.avic imx.ccm imx.enet imx.epit imx.fec imx.gpio imx.i2c imx.rngc imx.serial imx.spi imx.usbphy imx2.wdt imx25.ccm imx25.gpt imx31.ccm imx31.gpt imx6.ccm imx6.gpt imx6.src imx6ul.ccm imx7.analog imx7.ccm imx7.gpr imx7.gpt imx7.snvs loongson.liointc mchp.pfsoc.ddr_cfg mchp.pfsoc.ddr_sgmii_phy mchp.pfsoc.ioscb mchp.pfsoc.sysreg microbit.i2c microchip.pfsoc nrf51_soc.gpio nrf51_soc.nvm nrf51_soc.rng nrf51_soc.timer nrf51_soc.uart pc-1.0-machine pc-1.1-machine pc-1.2-machine pc-1.3-machine pc-i440fx-1.4-machine pc-i440fx-1.5-machine pc-i440fx-1.6-machine pc-i440fx-1.7-machine pc-i440fx-2.0-machine pc-i440fx-2.1-machine pc-i440fx-2.10-machine pc-i440fx-2.11-machine pc-i440fx-2.12-machine pc-i440fx-2.2-machine pc-i440fx-2.3-machine pc-i440fx-2.4-machine pc-i440fx-2.5-machine pc-i440fx-2.6-machine pc-i440fx-2.7-machine pc-i440fx-2.8-machine pc-i440fx-2.9-machine pc-i440fx-3.0-machine pc-i440fx-3.1-machine pc-i440fx-4.0-machine pc-i440fx-4.1-machine pc-i440fx-4.2-machine pc-i440fx-5.0-machine pc-i440fx-5.1-machine pc-i440fx-5.2-machine pc-i440fx-6.0-machine pc-q35-2.10-machine pc-q35-2.11-machine pc-q35-2.12-machine pc-q35-2.4-machine pc-q35-2.5-machine pc-q35-2.6-machine pc-q35-2.7-machine pc-q35-2.8-machine pc-q35-2.9-machine pc-q35-3.0-machine pc-q35-3.1-machine pc-q35-4.0-machine pc-q35-4.0.1-machine pc-q35-4.1-machine pc-q35-4.2-machine pc-q35-5.0-machine pc-q35-5.1-machine pc-q35-5.2-machine pc-q35-6.0-machine power10_v1.0-pnv-chip power10_v1.0-powernv-cpu-core power10_v1.0-powerpc64-cpu power10_v1.0-spapr-cpu-core power5+_v2.1-powerpc64-cpu power5+_v2.1-spapr-cpu-core power7+_v2.1-powerpc64-cpu power7+_v2.1-spapr-cpu-core power7_v2.3-powerpc64-cpu power7_v2.3-spapr-cpu-core power8_v2.0-pnv-chip power8_v2.0-powernv-cpu-core power8_v2.0-powerpc64-cpu power8_v2.0-spapr-cpu-core power8e_v2.1-pnv-chip power8e_v2.1-powernv-cpu-core power8e_v2.1-powerpc64-cpu power8e_v2.1-spapr-cpu-core power8nvl_v1.0-pnv-chip power8nvl_v1.0-powernv-cpu-core power8nvl_v1.0-powerpc64-cpu power8nvl_v1.0-spapr-cpu-core power9_v1.0-powerpc64-cpu power9_v1.0-spapr-cpu-core power9_v2.0-pnv-chip power9_v2.0-powernv-cpu-core power9_v2.0-powerpc64-cpu power9_v2.0-spapr-cpu-core pseries-2.1-machine pseries-2.10-machine pseries-2.11-machine pseries-2.12-machine pseries-2.12-sxxm-machine pseries-2.2-machine pseries-2.3-machine pseries-2.4-machine pseries-2.5-machine pseries-2.6-machine pseries-2.7-machine pseries-2.8-machine pseries-2.9-machine pseries-3.0-machine pseries-3.1-machine pseries-4.0-machine pseries-4.1-machine pseries-4.2-machine pseries-5.0-machine pseries-5.1-machine pseries-5.2-machine pseries-6.0-machine qemu:dummy qemu:iommu-memory-region qemu:memory-region riscv.hart_array riscv.lowrisc.ibex.soc riscv.sifive.clint riscv.sifive.e.prci riscv.sifive.e.soc riscv.sifive.plic riscv.sifive.test riscv.sifive.u.otp riscv.sifive.u.prci riscv.sifive.u.soc s390-ccw-virtio-2.10-machine s390-ccw-virtio-2.11-machine s390-ccw-virtio-2.12-machine s390-ccw-virtio-2.4-machine s390-ccw-virtio-2.5-machine s390-ccw-virtio-2.6-machine s390-ccw-virtio-2.7-machine s390-ccw-virtio-2.8-machine s390-ccw-virtio-2.9-machine s390-ccw-virtio-3.0-machine s390-ccw-virtio-3.1-machine s390-ccw-virtio-4.0-machine s390-ccw-virtio-4.1-machine s390-ccw-virtio-4.2-machine s390-ccw-virtio-5.0-machine s390-ccw-virtio-5.1-machine s390-ccw-virtio-5.2-machine s390-ccw-virtio-6.0-machine sifive.pdma sifive_soc.gpio virt-2.10-machine virt-2.11-machine virt-2.12-machine virt-2.6-machine virt-2.7-machine virt-2.8-machine virt-2.9-machine virt-3.0-machine virt-3.1-machine virt-4.0-machine virt-4.1-machine virt-4.2-machine virt-5.0-machine virt-5.1-machine virt-5.2-machine virt-6.0-machine xenfv-3.1-machine xenfv-4.2-machine xlnx-zynmp.rtc xlnx.axi-dma xlnx.axi-ethernet xlnx.dpdma xlnx.pmu_io_intc xlnx.ps7-dev-cfg xlnx.ps7-qspi xlnx.ps7-spi xlnx.usmp-gqspi xlnx.v-dp xlnx.versal-usb2 xlnx.versal-usb2-ctrl-regs xlnx.xps-ethernetlite xlnx.xps-intc xlnx.xps-spi xlnx.xps-timer xlnx.xps-uartlite xlnx.zdma xlnx.zynqmp-can xlnx.zynqmp_ipi z10BC.2-base-s390x-cpu z10BC.2-s390x-cpu z10EC.2-base-s390x-cpu z10EC.2-s390x-cpu z10EC.3-base-s390x-cpu z10EC.3-s390x-cpu z13.2-base-s390x-cpu z13.2-s390x-cpu z14.2-base-s390x-cpu z14.2-s390x-cpu z196.2-base-s390x-cpu z196.2-s390x-cpu z890.2-base-s390x-cpu z890.2-s390x-cpu z890.3-base-s390x-cpu z890.3-s390x-cpu z900.2-base-s390x-cpu z900.2-s390x-cpu z900.3-base-s390x-cpu z900.3-s390x-cpu z990.2-base-s390x-cpu z990.2-s390x-cpu z990.3-base-s390x-cpu z990.3-s390x-cpu z990.4-base-s390x-cpu z990.4-s390x-cpu z990.5-base-s390x-cpu z990.5-s390x-cpu z9BC.2-base-s390x-cpu z9BC.2-s390x-cpu z9EC.2-base-s390x-cpu z9EC.2-s390x-cpu z9EC.3-base-s390x-cpu z9EC.3-s390x-cpu zEC12.2-base-s390x-cpu zEC12.2-s390x-cpu Markus Armbruster (1): hw: Replace anti-social QOM type names include/hw/arm/armv7m.h | 2 +- include/hw/arm/fsl-imx25.h | 2 +- include/hw/arm/fsl-imx31.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/fsl-imx7.h | 2 +- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/cris/etraxfs.h | 2 +- include/hw/i386/ich9.h | 2 +- include/hw/misc/grlib_ahb_apb_pnp.h | 4 ++-- include/hw/misc/zynq-xadc.h | 2 +- include/hw/register.h | 2 +- include/hw/sparc/grlib.h | 6 +++--- hw/arm/xilinx_zynq.c | 2 +- hw/audio/cs4231.c | 2 +- hw/block/fdc.c | 4 ++-- hw/char/etraxfs_ser.c | 2 +- hw/cris/axis_dev88.c | 6 +++--- hw/display/tcx.c | 2 +- hw/intc/etraxfs_pic.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- hw/misc/zynq_slcr.c | 2 +- hw/sparc/sun4m.c | 12 ++++++------ hw/timer/etraxfs_timer.c | 2 +- softmmu/vl.c | 2 +- tests/vmstate-static-checker-data/dump1.json | 4 ++-- tests/vmstate-static-checker-data/dump2.json | 4 ++-- 27 files changed, 40 insertions(+), 40 deletions(-) -- 2.26.2 From MAILER-DAEMON Fri Jan 29 03:15:55 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Owd-0005LF-PA for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 03:15:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) 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TLS) by relay.mimecast.com with ESMTP id us-mta-16-2Ce2pkWwO7y1Z5M3bHLaTA-1; Fri, 29 Jan 2021 03:15:48 -0500 X-MC-Unique: 2Ce2pkWwO7y1Z5M3bHLaTA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DA09F801AB1; Fri, 29 Jan 2021 08:15:45 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-113-224.ams2.redhat.com [10.36.113.224]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 28716722C1; Fri, 29 Jan 2021 08:15:21 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 8DF00113861E; Fri, 29 Jan 2021 09:15:19 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, kraxel@redhat.com, jsnow@redhat.com, kwolf@redhat.com, mreitz@redhat.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, jcd@tribudubois.net, peter.chubb@nicta.com.au, andrew.smirnov@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, chouteau@adacore.com, frederic.konrad@adacore.com, quintela@redhat.com, dgilbert@redhat.com, qemu-arm@nongnu.org, qemu-block@nongnu.org, berrange@redhat.com, ehabkost@redhat.com Subject: [PATCH RFC 1/1] hw: Replace anti-social QOM type names Date: Fri, 29 Jan 2021 09:15:19 +0100 Message-Id: <20210129081519.3848145-2-armbru@redhat.com> In-Reply-To: <20210129081519.3848145-1-armbru@redhat.com> References: <20210129081519.3848145-1-armbru@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 08:15:54 -0000 Several QOM type names contain ',': ARM,bitband-memory etraxfs,pic etraxfs,serial etraxfs,timer fsl,imx25 fsl,imx31 fsl,imx6 fsl,imx6ul fsl,imx7 grlib,ahbpnp grlib,apbpnp grlib,apbuart grlib,gptimer grlib,irqmp qemu,register SUNW,bpp SUNW,CS4231 SUNW,DBRI SUNW,DBRI.prom SUNW,fdtwo SUNW,sx SUNW,tcx xilinx,zynq_slcr xlnx,zynqmp xlnx,zynqmp-pmu-soc xlnx,zynq-xadc These are all device types. They can't be plugged with -device / device_add, except for xlnx,zynqmp-pmu-soc, and I doubt that one actually works. They *can* be used with -device / device_add to request help. Usability is poor, though: you have to double the comma, like this: $ qemu-system-x86_64 -device SUNW,,fdtwo,help Trap for the unwary. The fact that this was broken in device-introspect-test for more than six years until commit e27bd49876 fixed it demonstrates that "the unwary" includes seasoned developers. One QOM type name contains ' ': "ICH9 SMB". Because having to remember just one way to quote would be too easy. Summarily replace ',' and ' ' by '-'. Signed-off-by: Markus Armbruster --- include/hw/arm/armv7m.h | 2 +- include/hw/arm/fsl-imx25.h | 2 +- include/hw/arm/fsl-imx31.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/fsl-imx7.h | 2 +- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/cris/etraxfs.h | 2 +- include/hw/i386/ich9.h | 2 +- include/hw/misc/grlib_ahb_apb_pnp.h | 4 ++-- include/hw/misc/zynq-xadc.h | 2 +- include/hw/register.h | 2 +- include/hw/sparc/grlib.h | 6 +++--- hw/arm/xilinx_zynq.c | 2 +- hw/audio/cs4231.c | 2 +- hw/block/fdc.c | 4 ++-- hw/char/etraxfs_ser.c | 2 +- hw/cris/axis_dev88.c | 6 +++--- hw/display/tcx.c | 2 +- hw/intc/etraxfs_pic.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- hw/misc/zynq_slcr.c | 2 +- hw/sparc/sun4m.c | 12 ++++++------ hw/timer/etraxfs_timer.c | 2 +- softmmu/vl.c | 2 +- tests/vmstate-static-checker-data/dump1.json | 4 ++-- tests/vmstate-static-checker-data/dump2.json | 4 ++-- 27 files changed, 40 insertions(+), 40 deletions(-) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 0791dcb68a..189b23a8ce 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -15,7 +15,7 @@ #include "target/arm/idau.h" #include "qom/object.h" -#define TYPE_BITBAND "ARM,bitband-memory" +#define TYPE_BITBAND "ARM-bitband-memory" OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND) struct BitBandState { diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index c1603b2ac2..1b1086e945 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -34,7 +34,7 @@ #include "target/arm/cpu.h" #include "qom/object.h" -#define TYPE_FSL_IMX25 "fsl,imx25" +#define TYPE_FSL_IMX25 "fsl-imx25" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX25State, FSL_IMX25) #define FSL_IMX25_NUM_UARTS 5 diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index b9792d58ae..c116a73e0b 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -30,7 +30,7 @@ #include "target/arm/cpu.h" #include "qom/object.h" -#define TYPE_FSL_IMX31 "fsl,imx31" +#define TYPE_FSL_IMX31 "fsl-imx31" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX31State, FSL_IMX31) #define FSL_IMX31_NUM_UARTS 2 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 29cc425acc..83291457cf 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -36,7 +36,7 @@ #include "cpu.h" #include "qom/object.h" -#define TYPE_FSL_IMX6 "fsl,imx6" +#define TYPE_FSL_IMX6 "fsl-imx6" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6) #define FSL_IMX6_NUM_CPUS 4 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index f8ebfba4f9..7812e516a5 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -40,7 +40,7 @@ #include "cpu.h" #include "qom/object.h" -#define TYPE_FSL_IMX6UL "fsl,imx6ul" +#define TYPE_FSL_IMX6UL "fsl-imx6ul" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) enum FslIMX6ULConfiguration { diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 161fdc36da..f5d527a490 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -41,7 +41,7 @@ #include "cpu.h" #include "qom/object.h" -#define TYPE_FSL_IMX7 "fsl,imx7" +#define TYPE_FSL_IMX7 "fsl-imx7" OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) enum FslIMX7Configuration { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6f45387a17..7941e29c29 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -36,7 +36,7 @@ #include "qom/object.h" #include "net/can_emu.h" -#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" +#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_NUM_APU_CPUS 4 diff --git a/include/hw/cris/etraxfs.h b/include/hw/cris/etraxfs.h index 9e99380e0c..8b01ed67d3 100644 --- a/include/hw/cris/etraxfs.h +++ b/include/hw/cris/etraxfs.h @@ -41,7 +41,7 @@ static inline DeviceState *etraxfs_ser_create(hwaddr addr, DeviceState *dev; SysBusDevice *s; - dev = qdev_new("etraxfs,serial"); + dev = qdev_new("etraxfs-serial"); s = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", chr); sysbus_realize_and_unref(s, &error_fatal); diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index d1ea000d3d..23ee8e371b 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -216,7 +216,7 @@ struct ICH9LPCState { /* D31:F3 SMBus controller */ -#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB" +#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" #define ICH9_A2_SMB_REVISION 0x02 #define ICH9_SMB_PI 0x00 diff --git a/include/hw/misc/grlib_ahb_apb_pnp.h b/include/hw/misc/grlib_ahb_apb_pnp.h index 341451bff6..bab0b5f47f 100644 --- a/include/hw/misc/grlib_ahb_apb_pnp.h +++ b/include/hw/misc/grlib_ahb_apb_pnp.h @@ -25,10 +25,10 @@ #define GRLIB_AHB_APB_PNP_H #include "qom/object.h" -#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp" +#define TYPE_GRLIB_AHB_PNP "grlib-ahbpnp" OBJECT_DECLARE_SIMPLE_TYPE(AHBPnp, GRLIB_AHB_PNP) -#define TYPE_GRLIB_APB_PNP "grlib,apbpnp" +#define TYPE_GRLIB_APB_PNP "grlib-apbpnp" OBJECT_DECLARE_SIMPLE_TYPE(APBPnp, GRLIB_APB_PNP) void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask, diff --git a/include/hw/misc/zynq-xadc.h b/include/hw/misc/zynq-xadc.h index 602bfb4ab1..2017b7a803 100644 --- a/include/hw/misc/zynq-xadc.h +++ b/include/hw/misc/zynq-xadc.h @@ -23,7 +23,7 @@ #define ZYNQ_XADC_NUM_ADC_REGS 128 #define ZYNQ_XADC_FIFO_DEPTH 15 -#define TYPE_ZYNQ_XADC "xlnx,zynq-xadc" +#define TYPE_ZYNQ_XADC "xlnx-zynq-xadc" OBJECT_DECLARE_SIMPLE_TYPE(ZynqXADCState, ZYNQ_XADC) struct ZynqXADCState { diff --git a/include/hw/register.h b/include/hw/register.h index 03c8926d27..b480e3882c 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -87,7 +87,7 @@ struct RegisterInfo { void *opaque; }; -#define TYPE_REGISTER "qemu,register" +#define TYPE_REGISTER "qemu-register" DECLARE_INSTANCE_CHECKER(RegisterInfo, REGISTER, TYPE_REGISTER) diff --git a/include/hw/sparc/grlib.h b/include/hw/sparc/grlib.h index 2104f493f3..ef1946c7f8 100644 --- a/include/hw/sparc/grlib.h +++ b/include/hw/sparc/grlib.h @@ -32,14 +32,14 @@ */ /* IRQMP */ -#define TYPE_GRLIB_IRQMP "grlib,irqmp" +#define TYPE_GRLIB_IRQMP "grlib-irqmp" void grlib_irqmp_ack(DeviceState *dev, int intno); /* GPTimer */ -#define TYPE_GRLIB_GPTIMER "grlib,gptimer" +#define TYPE_GRLIB_GPTIMER "grlib-gptimer" /* APB UART */ -#define TYPE_GRLIB_APB_UART "grlib,apbuart" +#define TYPE_GRLIB_APB_UART "grlib-apbuart" #endif /* GRLIB_H */ diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b72772bc82..8db6cfd47f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -231,7 +231,7 @@ static void zynq_init(MachineState *machine) clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); /* Create slcr, keep a pointer to connect clocks */ - slcr = qdev_new("xilinx,zynq_slcr"); + slcr = qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); diff --git a/hw/audio/cs4231.c b/hw/audio/cs4231.c index 209c05a0a0..8be716ee83 100644 --- a/hw/audio/cs4231.c +++ b/hw/audio/cs4231.c @@ -37,7 +37,7 @@ #define CS_DREGS 32 #define CS_MAXDREG (CS_DREGS - 1) -#define TYPE_CS4231 "SUNW,CS4231" +#define TYPE_CS4231 "SUNW-CS4231" typedef struct CSState CSState; DECLARE_INSTANCE_CHECKER(CSState, CS4231, TYPE_CS4231) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 7fc547c62d..0dd158bf73 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -2547,7 +2547,7 @@ void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, DeviceState *dev; FDCtrlSysBus *sys; - dev = qdev_new("SUNW,fdtwo"); + dev = qdev_new("SUNW-fdtwo"); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sys = SYSBUS_FDC(dev); sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); @@ -2945,7 +2945,7 @@ static void sun4m_fdc_class_init(ObjectClass *klass, void *data) } static const TypeInfo sun4m_fdc_info = { - .name = "SUNW,fdtwo", + .name = "SUNW-fdtwo", .parent = TYPE_SYSBUS_FDC, .instance_init = sun4m_fdc_initfn, .class_init = sun4m_fdc_class_init, diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 6bee3ee18e..e8c3017724 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -50,7 +50,7 @@ #define STAT_TR_IDLE 22 #define STAT_TR_RDY 24 -#define TYPE_ETRAX_FS_SERIAL "etraxfs,serial" +#define TYPE_ETRAX_FS_SERIAL "etraxfs-serial" typedef struct ETRAXSerial ETRAXSerial; DECLARE_INSTANCE_CHECKER(ETRAXSerial, ETRAX_SERIAL, TYPE_ETRAX_FS_SERIAL) diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index b0cb6d84af..af5a0e3517 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -289,7 +289,7 @@ void axisdev88_init(MachineState *machine) &gpio_state.iomem); - dev = qdev_new("etraxfs,pic"); + dev = qdev_new("etraxfs-pic"); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, 0x3001c000); @@ -323,8 +323,8 @@ void axisdev88_init(MachineState *machine) } /* 2 timers. */ - sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL); - sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); + sysbus_create_varargs("etraxfs-timer", 0x3001e000, irq[0x1b], nmi[1], NULL); + sysbus_create_varargs("etraxfs-timer", 0x3005e000, irq[0x1b], nmi[1], NULL); for (i = 0; i < 4; i++) { etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i)); diff --git a/hw/display/tcx.c b/hw/display/tcx.c index 965f92ff6b..b584d39a01 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -56,7 +56,7 @@ #define TCX_THC_CURSMASK 0x900 #define TCX_THC_CURSBITS 0x980 -#define TYPE_TCX "SUNW,tcx" +#define TYPE_TCX "SUNW-tcx" OBJECT_DECLARE_SIMPLE_TYPE(TCXState, TCX) struct TCXState { diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c index 54ed4c77f7..bd37d1cca0 100644 --- a/hw/intc/etraxfs_pic.c +++ b/hw/intc/etraxfs_pic.c @@ -38,7 +38,7 @@ #define R_R_GURU 4 #define R_MAX 5 -#define TYPE_ETRAX_FS_PIC "etraxfs,pic" +#define TYPE_ETRAX_FS_PIC "etraxfs-pic" DECLARE_INSTANCE_CHECKER(struct etrax_pic, ETRAX_FS_PIC, TYPE_ETRAX_FS_PIC) diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index 1d1b4b5c19..5a2016672a 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -28,7 +28,7 @@ /* Define the PMU device */ -#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc" +#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPPMUSoCState, XLNX_ZYNQMP_PMU_SOC) #define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000 diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 66504a9d3a..12290ab8f6 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -182,7 +182,7 @@ REG32(DDRIOB, 0xb40) #define ZYNQ_SLCR_MMIO_SIZE 0x1000 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) -#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr" +#define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr" OBJECT_DECLARE_SIMPLE_TYPE(ZynqSLCRState, ZYNQ_SLCR) struct ZynqSLCRState { diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 38ca1e33c7..d1a7bb79c3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -496,7 +496,7 @@ static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, DeviceState *dev; SysBusDevice *s; - dev = qdev_new("SUNW,tcx"); + dev = qdev_new("SUNW-tcx"); qdev_prop_set_uint32(dev, "vram_size", vram_size); qdev_prop_set_uint16(dev, "width", width); qdev_prop_set_uint16(dev, "height", height); @@ -970,7 +970,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, } if (hwdef->sx_base) { - create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000); + create_unimplemented_device("SUNW-sx", hwdef->sx_base, 0x2000); } dev = qdev_new("sysbus-m48t08"); @@ -1045,23 +1045,23 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, slavio_irq[30], fdc_tc); if (hwdef->cs_base) { - sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, + sysbus_create_simple("SUNW-CS4231", hwdef->cs_base, slavio_irq[5]); } if (hwdef->dbri_base) { /* ISDN chip with attached CS4215 audio codec */ /* prom space */ - create_unimplemented_device("SUNW,DBRI.prom", + create_unimplemented_device("SUNW-DBRI.prom", hwdef->dbri_base + 0x1000, 0x30); /* reg space */ - create_unimplemented_device("SUNW,DBRI", + create_unimplemented_device("SUNW-DBRI", hwdef->dbri_base + 0x10000, 0x100); } if (hwdef->bpp_base) { /* parallel port */ - create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20); + create_unimplemented_device("SUNW-bpp", hwdef->bpp_base, 0x20); } initrd_size = 0; diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index 48f2e3ade2..5379006086 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -48,7 +48,7 @@ #define R_INTR 0x50 #define R_MASKED_INTR 0x54 -#define TYPE_ETRAX_FS_TIMER "etraxfs,timer" +#define TYPE_ETRAX_FS_TIMER "etraxfs-timer" typedef struct ETRAXTimerState ETRAXTimerState; DECLARE_INSTANCE_CHECKER(ETRAXTimerState, ETRAX_TIMER, TYPE_ETRAX_FS_TIMER) diff --git a/softmmu/vl.c b/softmmu/vl.c index 81766cd568..19b69e8c5f 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -917,7 +917,7 @@ static const VGAInterfaceInfo vga_interfaces[VGA_TYPE_MAX] = { [VGA_TCX] = { .opt_name = "tcx", .name = "TCX framebuffer", - .class_names = { "SUNW,tcx" }, + .class_names = { "SUNW-tcx" }, }, [VGA_CG3] = { .opt_name = "cg3", diff --git a/tests/vmstate-static-checker-data/dump1.json b/tests/vmstate-static-checker-data/dump1.json index 786ca0b484..8d024d99c4 100644 --- a/tests/vmstate-static-checker-data/dump1.json +++ b/tests/vmstate-static-checker-data/dump1.json @@ -823,8 +823,8 @@ ] } }, - "SUNW,fdtwo": { - "Name": "SUNW,fdtwo", + "SUNW-fdtwo": { + "Name": "SUNW-fdtwo", "version_id": 2, "minimum_version_id": 2, "Description": { diff --git a/tests/vmstate-static-checker-data/dump2.json b/tests/vmstate-static-checker-data/dump2.json index 75719f5ec9..45d0126d77 100644 --- a/tests/vmstate-static-checker-data/dump2.json +++ b/tests/vmstate-static-checker-data/dump2.json @@ -628,8 +628,8 @@ ] } }, - "SUNW,fdtwo": { - "Name": "SUNW,fdtwo", + "SUNW-fdtwo": { + "Name": "SUNW-fdtwo", "version_id": 2, "minimum_version_id": 2, "Description": { -- 2.26.2 From MAILER-DAEMON Fri Jan 29 04:06:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Pji-0006Zn-Tr for mharc-qemu-arm@gnu.org; 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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id x20sm3436607ejv.66.2021.01.29.01.06.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Jan 2021 01:06:24 -0800 (PST) Subject: Re: [PATCH RFC 1/1] hw: Replace anti-social QOM type names To: Markus Armbruster , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, kraxel@redhat.com, jsnow@redhat.com, kwolf@redhat.com, mreitz@redhat.com, marcandre.lureau@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, jcd@tribudubois.net, peter.chubb@nicta.com.au, andrew.smirnov@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, chouteau@adacore.com, frederic.konrad@adacore.com, quintela@redhat.com, dgilbert@redhat.com, qemu-arm@nongnu.org, qemu-block@nongnu.org, berrange@redhat.com, ehabkost@redhat.com References: <20210129081519.3848145-1-armbru@redhat.com> <20210129081519.3848145-2-armbru@redhat.com> From: Paolo Bonzini Message-ID: <6d69c392-1c53-cc35-d504-0ada33ca37c5@redhat.com> Date: Fri, 29 Jan 2021 10:06:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210129081519.3848145-2-armbru@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 09:06:37 -0000 On 29/01/21 09:15, Markus Armbruster wrote: > diff --git a/hw/block/fdc.c b/hw/block/fdc.c > index 7fc547c62d..0dd158bf73 100644 > --- a/hw/block/fdc.c > +++ b/hw/block/fdc.c > @@ -2547,7 +2547,7 @@ void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, > DeviceState *dev; > FDCtrlSysBus *sys; > > - dev = qdev_new("SUNW,fdtwo"); > + dev = qdev_new("SUNW-fdtwo"); > sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > sys = SYSBUS_FDC(dev); > sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); Missing: fdc_name = object_get_typename(OBJECT(fdc_dev)); drive_suffix = !strcmp(fdc_name, "SUNW,fdtwo") ? "" : i ? "B" : "A"; warn_report("warning: property %s.drive%s is deprecated", fdc_name, drive_suffix); error_printf("Use -device floppy,unit=%d,drive=... instead.\n", i); From MAILER-DAEMON Fri Jan 29 04:18:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Pv5-0007ks-HP for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 04:18:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Pv3-0007jS-T4 for qemu-arm@nongnu.org; Fri, 29 Jan 2021 04:18:21 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:25098) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5Pv1-0004dA-MC for qemu-arm@nongnu.org; Fri, 29 Jan 2021 04:18:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611911895; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; 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Fri, 29 Jan 2021 10:17:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, kraxel@redhat.com, jsnow@redhat.com, kwolf@redhat.com, mreitz@redhat.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, jcd@tribudubois.net, peter.chubb@nicta.com.au, andrew.smirnov@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, chouteau@adacore.com, frederic.konrad@adacore.com, quintela@redhat.com, dgilbert@redhat.com, qemu-arm@nongnu.org, qemu-block@nongnu.org, berrange@redhat.com, ehabkost@redhat.com Subject: Re: [PATCH RFC 0/1] QOM type names and QAPI References: <20210129081519.3848145-1-armbru@redhat.com> Date: Fri, 29 Jan 2021 10:17:59 +0100 In-Reply-To: <20210129081519.3848145-1-armbru@redhat.com> (Markus Armbruster's message of "Fri, 29 Jan 2021 09:15:18 +0100") Message-ID: <87tur02jaw.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=216.205.24.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 09:18:22 -0000 Forgot to mention: Based-on: <20210125162402.1807394-1-armbru@redhat.com> [PATCH 0/3] Drop deprecated floppy config & bogus -drive if=T From MAILER-DAEMON Fri Jan 29 04:19:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Pvm-00089I-UL for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 04:19:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Pvl-000881-EP for qemu-arm@nongnu.org; Fri, 29 Jan 2021 04:19:05 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:41926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5Pvj-0004uX-OO for qemu-arm@nongnu.org; Fri, 29 Jan 2021 04:19:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611911942; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/yz8EbxTd6P8o5Z3b4wxCqcLdps47THMx0uujj+aREc=; b=JDFw23Q6g3EuI22cqlngKiY7XhaY8GVzRN5CrQgl8RKsXLSUDrefZVbLDCBjJOnkxZHIPH isLsgNnRnPhmS81LE1p1os/SojdtBHyx1/WFTUOC02NYcIbCtlNikrxIRXCjsBiKM7zRWO yO0l7HBilTh5zVABcYBlrNwRYO4EAaA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-604-RThDdCvNMCqmVKvhQpDu7w-1; Fri, 29 Jan 2021 04:19:01 -0500 X-MC-Unique: RThDdCvNMCqmVKvhQpDu7w-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3D80D1922961; Fri, 29 Jan 2021 09:18:59 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-113-224.ams2.redhat.com [10.36.113.224]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 055C66268B; Fri, 29 Jan 2021 09:18:50 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 91E4D113865F; Fri, 29 Jan 2021 10:18:48 +0100 (CET) From: Markus Armbruster To: Paolo Bonzini Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, mark.cave-ayland@ilande.co.uk, frederic.konrad@adacore.com, kraxel@redhat.com, edgar.iglesias@gmail.com, jcd@tribudubois.net, qemu-block@nongnu.org, quintela@redhat.com, andrew.smirnov@gmail.com, marcandre.lureau@redhat.com, atar4qemu@gmail.com, ehabkost@redhat.com, alistair@alistair23.me, dgilbert@redhat.com, chouteau@adacore.com, qemu-arm@nongnu.org, peter.chubb@nicta.com.au, jsnow@redhat.com, kwolf@redhat.com, berrange@redhat.com, mreitz@redhat.com Subject: Re: [PATCH RFC 1/1] hw: Replace anti-social QOM type names References: <20210129081519.3848145-1-armbru@redhat.com> <20210129081519.3848145-2-armbru@redhat.com> <6d69c392-1c53-cc35-d504-0ada33ca37c5@redhat.com> Date: Fri, 29 Jan 2021 10:18:48 +0100 In-Reply-To: <6d69c392-1c53-cc35-d504-0ada33ca37c5@redhat.com> (Paolo Bonzini's message of "Fri, 29 Jan 2021 10:06:20 +0100") Message-ID: <87pn1o2j9j.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=63.128.21.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 09:19:05 -0000 Paolo Bonzini writes: > On 29/01/21 09:15, Markus Armbruster wrote: >> diff --git a/hw/block/fdc.c b/hw/block/fdc.c >> index 7fc547c62d..0dd158bf73 100644 >> --- a/hw/block/fdc.c >> +++ b/hw/block/fdc.c >> @@ -2547,7 +2547,7 @@ void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, >> DeviceState *dev; >> FDCtrlSysBus *sys; >> - dev = qdev_new("SUNW,fdtwo"); >> + dev = qdev_new("SUNW-fdtwo"); >> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); >> sys = SYSBUS_FDC(dev); >> sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); > > > Missing: > > fdc_name = object_get_typename(OBJECT(fdc_dev)); > drive_suffix = !strcmp(fdc_name, "SUNW,fdtwo") ? "" : i ? "B" > : "A"; > warn_report("warning: property %s.drive%s is deprecated", > fdc_name, drive_suffix); > error_printf("Use -device floppy,unit=%d,drive=... instead.\n", i); You're right. I based on my "[PATCH 0/3] Drop deprecated floppy config & bogus -drive if=T", where this is gone, then forgot to mention it in my cover letter. Apologies! From MAILER-DAEMON Fri Jan 29 05:17:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Qqi-0006uZ-HB for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 05:17:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Qqh-0006rt-DG; Fri, 29 Jan 2021 05:17:55 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Qqe-0005IM-KS; Fri, 29 Jan 2021 05:17:55 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DRtY76DdzzjDvP; Fri, 29 Jan 2021 18:16:43 +0800 (CST) Received: from [10.174.184.42] (10.174.184.42) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Fri, 29 Jan 2021 18:17:38 +0800 Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: Paolo Bonzini , "Dr. David Alan Gilbert" References: <20210111073439.20236-1-zhukeqian1@huawei.com> <20210128200223.GJ2951@work-vm> CC: Kirti Wankhede , Alex Williamson , , , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , Igor Mammedov , , Zenghui Yu , From: Keqian Zhu Message-ID: <4665c997-ebf1-939d-6a94-fe0f445dbdda@huawei.com> Date: Fri, 29 Jan 2021 18:17:37 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhukeqian1@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 10:17:55 -0000 On 2021/1/29 15:49, Paolo Bonzini wrote: > On 28/01/21 21:02, Dr. David Alan Gilbert wrote: >> * Paolo Bonzini (pbonzini@redhat.com) wrote: >>> On 11/01/21 08:34, Keqian Zhu wrote: >>>> +static void vfio_listener_log_start(MemoryListener *listener, >>>> + MemoryRegionSection *section, >>>> + int old, int new) >>>> +{ >>>> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >>>> + >>>> + vfio_set_dirty_page_tracking(container, true); >>>> +} >>> >>> This would enable dirty page tracking also just for having a framebuffer >>> (DIRTY_MEMORY_VGA). Technically it would be correct, but it would also be >>> more heavyweight than expected. >> >> Wouldn't that only happen on emulated video devices? > > Yes, but still it's not impossible to have both an emulated VGA and an assigned GPU or vGPU. > >>> In order to only cover live migration, you can use the log_global_start and >>> log_global_stop callbacks instead. >>> >>> If you want to use log_start and log_stop, you need to add respectively >>> >>> if (old != 0) { >>> return; >>> } >>> >>> and >>> >>> if (new != 0) { >>> return; >>> } >> >> Why 0, wouldn't you be checking for DIRTY_LOG_MIGRATION somewhere? > > Actually thinking more about it log_start/log_stop are just wrong, because they would be called many times, for each MemoryRegionSection. Agree. This will be called for each MemoryRegionSection and each time when dirty_log_mask changed. KVM uses log_start/log_stop, because it can start dirty tracking for every memslot individually, but vfio just has global start/stop semantics. Anyway, use global start/stop is correct choice. Thanks, Keqian > > Paolo > > . > From MAILER-DAEMON Fri Jan 29 06:55:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5SMt-0006XY-BU for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 06:55:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5SMq-0006WX-Kx for qemu-arm@nongnu.org; Fri, 29 Jan 2021 06:55:12 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:47468) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5SMn-0004p8-CG for qemu-arm@nongnu.org; Fri, 29 Jan 2021 06:55:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611921308; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ElBCiwihzEnLp9k5HTNmbD98dJD+n9yI/cLIg0TigEI=; b=gYLKLRKhI+sh+UyvIxYPIw11MtY5jfy0y4wGT1FL+bmZJs58lBiAh1XPE+RCNDDNfDpHAb Fymp9+Rdud6NuIvgWszi2H8Vm0oSyq0xkTY/sqx3Ji1GlK4uubkyxbvvpdi3vx06BTCJkP JUqo8tL6WN8LuG1n5EjvJqmcCAVD7Uk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-361-ZF13kt_0O3OK48LxpS4tLg-1; Fri, 29 Jan 2021 06:55:07 -0500 X-MC-Unique: ZF13kt_0O3OK48LxpS4tLg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 89C901800D41; Fri, 29 Jan 2021 11:55:04 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-115-51.ams2.redhat.com [10.36.115.51]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8055F620D7; Fri, 29 Jan 2021 11:54:54 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id E51F5113865F; Fri, 29 Jan 2021 12:54:52 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, alistair@alistair23.me, peter.maydell@linaro.org, kraxel@redhat.com, jsnow@redhat.com, kwolf@redhat.com, mreitz@redhat.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, jcd@tribudubois.net, peter.chubb@nicta.com.au, andrew.smirnov@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, chouteau@adacore.com, frederic.konrad@adacore.com, quintela@redhat.com, dgilbert@redhat.com, qemu-arm@nongnu.org, qemu-block@nongnu.org, berrange@redhat.com, ehabkost@redhat.com Subject: Re: [PATCH RFC 0/1] QOM type names and QAPI References: <20210129081519.3848145-1-armbru@redhat.com> Date: Fri, 29 Jan 2021 12:54:52 +0100 In-Reply-To: <20210129081519.3848145-1-armbru@redhat.com> (Markus Armbruster's message of "Fri, 29 Jan 2021 09:15:18 +0100") Message-ID: <875z3g2c1f.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=216.205.24.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 11:55:13 -0000 Markus Armbruster writes: > QAPI has naming rules. docs/devel/qapi-code-gen.txt: > > === Naming rules and reserved names === > > All names must begin with a letter, and contain only ASCII letters, > digits, hyphen, and underscore. There are two exceptions: enum values > may start with a digit, and names that are downstream extensions (see > section Downstream extensions) start with underscore. > > [More on reserved names, upper vs. lower case, '-' vs. '_'...] > > The generator enforces the rules. > > Naming rules help in at least three ways: > > 1. They help with keeping names in interfaces consistent and > predictable. > > 2. They make avoiding collisions with the users' names in the > generator simpler. > > 3. They enable quote-less, evolvable syntax. > > For instance, keyval_parse() syntax consists of names, values, and > special characters ',', '=', '.' > > Since names cannot contain special characters, there is no need for > quoting[*]. Simple. > > Values are unrestricted, but only ',' is special there. We quote > it by doubling. > > Together, we get exactly the same quoting as in QemuOpts. This is > a feature. > > If we ever decice to extend key syntax, we have plenty of special > characters to choose from. This is also a feature. > > Both features rely on naming rules. > > QOM has no naming rules whatsoever. Actual names aren't nearly as bad > as they could be. Still, there are plenty of "funny" names. This > will become a problem when we > > * Switch from QemuOpts to keyval_parse() > > QOM type names must not contain special characters, unless we > introduce more quoting. Which we shouldn't, because the value of > special characters in names is negligible compared to the hassle of > having to quote them. > > * QAPIfy (the compile-time static parts of) QOM > > QOM type names become QAPI enum values. They must conform to QAPI > naming rules. > > Adopting QAPI naming rules for QOM type names takes care of both. > > Let's review the existing offenders. > > 1. We have a few type names containing ',', and one containing ' '. > The former require QemuOpts / keyval quoting (double the comma), > the latter requires shell quoting. There is no excuse for making > our users remember and do such crap. PATCH 1 eliminates it. > > 2. We have some 550 type names containing '.'. QAPI's naming rules > could be relaxed to accept '.', but keyval_parse()'s can't. Thinko: keyval_parse() copes. QOM type names occur as *value*, not as key. One more thing on QAPI naming rules. QAPI names get mapped to (parts of) C identifiers. These mappings are not injective. The basic mapping is simple: replace characters other than letters and digits by '_'. This means names distinct QAPI names can clash in C. Fairly harmless when the only "other" characters are '-' and '_'. The more "others" we permit, the more likely confusing clashes become. Not a show stopper, "merely" an issue of ergonomics. > Aside: I wish keyval_parse() would use '/' instead of '.', but it's > designed to be compatible to the block layer's existing use of > dotted keys (shoehorned into QemuOpts). > > 3. We have six type names containing '+'. Four of them also contain > '.'. Naming rules could be relaxed to accept '+'. I'm not sure > it's worthwhile. > > 4. We have 19 names starting with a digit. Three of them also contain > '.'. Leading digit is okay as QAPI enum, not okay as > keyval_parse() key fragment. We can either rename these types, or > make keyval_parse() a bit less strict. > > Of the type names containing '.' or '+'[**], 293 are CPUs, 107 are > machines, and 150 are something else. 48 of them can be plugged with > -device, all s390x or spapr CPUs. > > Can we get rid of '.'? > > I figure we could keep old names as deprecated aliases if we care. > Perhaps just the ones that can be plugged with -device. > > > [*] Paolo's "[PATCH 04/25] keyval: accept escaped commas in implied > option" provides for comma-quoting. I'm ignoring it here for brevity. > I assure you it doesn't weaken my argument. > > [**] They are: > 603e_v1.1-powerpc-cpu [...] From MAILER-DAEMON Fri Jan 29 07:02:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5STe-0004ak-QO for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 07:02:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5STa-0004ZS-PS for qemu-arm@nongnu.org; Fri, 29 Jan 2021 07:02:10 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:37075) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5STW-0007fi-Vh for qemu-arm@nongnu.org; Fri, 29 Jan 2021 07:02:09 -0500 Received: by mail-ej1-x62c.google.com with SMTP id kg20so12631918ejc.4 for ; Fri, 29 Jan 2021 04:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QZJP1TTfy2iOvpEi6sOsJbistrzDMWyxr83a9LBx14g=; b=FYE2dReq777MZIF9ywJbGKaIPUXzo+GntLXRYR6F8SUhLgfX4eL7XQDSvAacPqXbKP kXMwDO0VEq/+OBMyouvxkHmrCrkAEnGbCwK1ent362TtXjWEIK3Tzlxeq7Tiy2HNe9Wh xWgk3Zrqy3AIvAREIw6yIkrKSBcB5uC7LW/SQJ1yQP0/1i9BlERVXrP/E4c3uIb5tDGB LAuXJHBW2AYLOXwWh9rW4Z3Mfz/ZE0CahotoECyut81EkR5F/fe0E1xHSafOT1vXUMz0 Ah4O4C5qSPWaRaFm3glT6rHiPhJrWv+zWVpWvYkpjh/iXOzljp/u1h6iMr3NlH5tN9lS f6nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QZJP1TTfy2iOvpEi6sOsJbistrzDMWyxr83a9LBx14g=; b=HElJo8dyonNpyvFyB5O7AOOxXVyegu5PqKF1EkCufj5nJ3J7Hd5lbwoN/Jn0HvbbKy uRxxa+yPGpTK5ddcPMBPnprirkL8HAMpSGZpTz9lEqOISgE3MRZDuVVuGiTw6SfpH2Tu Eprs9oaIDid1HQ1BEIrD1K8WH+bMWUh3McvIzpjN4y5RDG8exjUwWxIY/cMB/Z/BsAeo qbxkL9kdDhYZMl2SgHVYd48Vi4od3iDKSggjg5K83Kc/VreqaYgc+QxYLvHq+rRv9r9G Rj3ba+kjeKUZI4Osm7J+JyGvZ+rbyM++XL+K3Eq/ZPdb9qV+gv/DEsfBjEdBlhktzy2K 0wdA== X-Gm-Message-State: AOAM532xevWBiot9c5AqLf8ajUx/gAAENKW0rMUxUJETFckPKeraIGkZ mtjurWWpyL5kCgQkQZ783TMkJgHLUiMeUJoqBjgYKA== X-Google-Smtp-Source: ABdhPJzx08wx81fMSwVaxJ3XiAQa7IM3Ho01Uv8cMFUni1NItmxeSf0Qyuz1KTgNNfTxs0kwBKIsUMq2fqDeis++4f0= X-Received: by 2002:a17:907:1b10:: with SMTP id mp16mr4241344ejc.482.1611921725215; Fri, 29 Jan 2021 04:02:05 -0800 (PST) MIME-Version: 1.0 References: <20210129081519.3848145-1-armbru@redhat.com> In-Reply-To: <20210129081519.3848145-1-armbru@redhat.com> From: Peter Maydell Date: Fri, 29 Jan 2021 12:01:53 +0000 Message-ID: Subject: Re: [PATCH RFC 0/1] QOM type names and QAPI To: Markus Armbruster Cc: QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , Gerd Hoffmann , John Snow , Kevin Wolf , Max Reitz , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Paolo Bonzini , Mark Cave-Ayland , Artyom Tarasenko , Jean-Christophe DUBOIS , Peter Chubb , Andrey Smirnov , "Michael S. Tsirkin" , Marcel Apfelbaum , Fabien Chouteau , KONRAD Frederic , Juan Quintela , "Dr. David Alan Gilbert" , qemu-arm , Qemu-block , "Daniel P. Berrange" , Eduardo Habkost Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 12:02:11 -0000 On Fri, 29 Jan 2021 at 08:15, Markus Armbruster wrote: > 2. We have some 550 type names containing '.'. QAPI's naming rules > could be relaxed to accept '.', but keyval_parse()'s can't. > > Aside: I wish keyval_parse() would use '/' instead of '.', but it's > designed to be compatible to the block layer's existing use of > dotted keys (shoehorned into QemuOpts). > Of the type names containing '.' or '+'[**], 293 are CPUs, 107 are > machines, and 150 are something else. 48 of them can be plugged with > -device, all s390x or spapr CPUs. > > Can we get rid of '.'? On this one, my vote would be "no". "Versioned machine names include the QEMU version number" is pretty well entrenched, and requiring users to remember that when they want version 4.2 they need to remember some other way of writing it than "4.2" seems rather unfriendly. And 550 uses of '.' is a lot. thanks -- PMM From MAILER-DAEMON Fri Jan 29 07:16:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5ShM-0008Ub-Jq for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 07:16:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5ShJ-0008T7-B4; Fri, 29 Jan 2021 07:16:21 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5ShA-0004yB-VC; Fri, 29 Jan 2021 07:16:21 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DRx9T5rBwzjDyZ; Fri, 29 Jan 2021 20:14:53 +0800 (CST) Received: from [10.174.185.179] (10.174.185.179) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Fri, 29 Jan 2021 20:15:47 +0800 Subject: Re: [PATCH] hw/arm/smmuv3: Fix addr_mask for range-based invalidation To: Auger Eric , , , CC: References: <20201225095015.609-1-yuzenghui@huawei.com> <4e114709-e5c2-1860-c760-c05aa3ed5388@redhat.com> <45f3334d-f0b4-9a40-1bd1-78bd04735eaf@redhat.com> From: Zenghui Yu Message-ID: Date: Fri, 29 Jan 2021 20:15:46 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <45f3334d-f0b4-9a40-1bd1-78bd04735eaf@redhat.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.185.179] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=yuzenghui@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 12:16:21 -0000 Hi Eric, On 2021/1/29 5:30, Auger Eric wrote: > Hi Zenghui, > > On 1/28/21 9:25 AM, Auger Eric wrote: >> Hi Zenghui, >> >> On 12/25/20 10:50 AM, Zenghui Yu wrote: >>> When performing range-based IOTLB invalidation, we should decode the TG >>> field into the corresponding translation granule size so that we can pass >>> the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to >>> properly emulate the architecture. >>> >>> Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") >>> Signed-off-by: Zenghui Yu >> >> Good catch! I tested with older guest kernels though. I wonder how I did >> not face the bug? > Please ignore this wrong comment as this corresponds to recent kernels > instead. Still puzzled anyway ;-) I noticed this when looking through your nested SMMU series and I didn't have much clue about the impact on the real setups. I guess we may receive some unexpected fault events with this bug. But I think we may miss it for some reasons: - the stale TLB entries happen to be evicted due to heavy traffic - some form of over-invalidation is performed by your implementation - ... >>> --- >>> hw/arm/smmuv3.c | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >>> index bbca0e9f20..65231c7d52 100644 >>> --- a/hw/arm/smmuv3.c >>> +++ b/hw/arm/smmuv3.c >>> @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, >>> { >>> SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >>> IOMMUTLBEvent event; >>> - uint8_t granule = tg; >>> + uint8_t granule; >>> >>> if (!tg) { >>> SMMUEventInfo event = {.inval_ste_allowed = true}; >>> @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, >>> return; >>> } >>> granule = tt->granule_sz; >>> + } else { >>> + guanule = tg * 2 + 10; >> maybe just init granule to this value above while fixing the typo. My intention is to initialize @granule to this value explicitly for the range-based invalidation case. But I'm okay with either way. Thanks, Zenghui From MAILER-DAEMON Fri Jan 29 07:18:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Sje-0002Or-6o for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 07:18:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44124) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5SjS-0002Lz-5T for qemu-arm@nongnu.org; Fri, 29 Jan 2021 07:18:39 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:25369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5SjN-0005p6-Cq for qemu-arm@nongnu.org; Fri, 29 Jan 2021 07:18:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611922706; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=ZCpBpvcztZfsdnFPJvUirqQrQuAPKuXuq+owsiHvLH0=; b=JrDdHPGAfnu5i0sjTGV+ulGPmF6aGlTbykx1QB886yEraz+34r1NxM02O126y4IFg+MydA lXkUC46+96l9+hO6r7uGENDtDucQ5w6Osa9HuD7gr4zUH4ul7y9oxo75RHqH8TvQ6laxp8 x1WY9PLamr+sn7pclE7fUsfm+HCzdv8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-140-OuMKDblmMQmOHH6CL5MV3w-1; Fri, 29 Jan 2021 07:18:13 -0500 X-MC-Unique: OuMKDblmMQmOHH6CL5MV3w-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4C68C1005504; Fri, 29 Jan 2021 12:18:11 +0000 (UTC) Received: from redhat.com (ovpn-115-94.ams2.redhat.com [10.36.115.94]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C7E2C19D9F; Fri, 29 Jan 2021 12:17:55 +0000 (UTC) Date: Fri, 29 Jan 2021 12:17:52 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Peter Maydell Cc: Markus Armbruster , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , Gerd Hoffmann , John Snow , Kevin Wolf , Max Reitz , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Paolo Bonzini , Mark Cave-Ayland , Artyom Tarasenko , Jean-Christophe DUBOIS , Peter Chubb , Andrey Smirnov , "Michael S. Tsirkin" , Marcel Apfelbaum , Fabien Chouteau , KONRAD Frederic , Juan Quintela , "Dr. David Alan Gilbert" , qemu-arm , Qemu-block , Eduardo Habkost Subject: Re: [PATCH RFC 0/1] QOM type names and QAPI Message-ID: <20210129121752.GJ4001740@redhat.com> Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20210129081519.3848145-1-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.14.6 (2020-07-11) X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=berrange@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.252, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 12:18:41 -0000 On Fri, Jan 29, 2021 at 12:01:53PM +0000, Peter Maydell wrote: > On Fri, 29 Jan 2021 at 08:15, Markus Armbruster wrote: > > 2. We have some 550 type names containing '.'. QAPI's naming rules > > could be relaxed to accept '.', but keyval_parse()'s can't. > > > > Aside: I wish keyval_parse() would use '/' instead of '.', but it's > > designed to be compatible to the block layer's existing use of > > dotted keys (shoehorned into QemuOpts). > > > Of the type names containing '.' or '+'[**], 293 are CPUs, 107 are > > machines, and 150 are something else. 48 of them can be plugged with > > -device, all s390x or spapr CPUs. > > > > Can we get rid of '.'? > > On this one, my vote would be "no". "Versioned machine names > include the QEMU version number" is pretty well entrenched, > and requiring users to remember that when they want version 4.2 > they need to remember some other way of writing it than "4.2" > seems rather unfriendly. And 550 uses of '.' is a lot. We can't make keyval_parse() accept "/" instead of ".", but can we make it accept "/" in addition to ".", and then encourage "/" ? People simply wouldnt be able to use "." as keyval separator if they're using typenames containing "." (or would have to escape the typename. Regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| From MAILER-DAEMON Fri Jan 29 08:11:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TYf-0000a3-E0 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:11:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TYU-0000YP-2O for qemu-arm@nongnu.org; Fri, 29 Jan 2021 08:11:18 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:30581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5TYN-00030y-Mb for qemu-arm@nongnu.org; Fri, 29 Jan 2021 08:11:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611925867; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=a0n2iAz7qZVW82Meqto8Hz6DydlTWNUsMON8L3R8h70=; b=TdDG40/Dg9zk4k4FMOIQIlX1NuOo1MDAjwAEQ1ezAnx/kkVGq4aXAxmjXb8hzTgJzCQZkM eoMMS1usMjp9YDdo0WMSi1bfT7rKtZqmdWRQpmABLTlrmLohqHldu9UF8OOxa0UGx2rDwY 9LKxQdrcMb00yqI3SjXG5OBaUxlUYW4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-79-tHs3kU-RPhKpf3hiodCbUw-1; Fri, 29 Jan 2021 08:11:03 -0500 X-MC-Unique: tHs3kU-RPhKpf3hiodCbUw-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4332C107ACE3; Fri, 29 Jan 2021 13:11:02 +0000 (UTC) Received: from [10.36.114.62] (ovpn-114-62.ams2.redhat.com [10.36.114.62]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 25DBD620D7; Fri, 29 Jan 2021 13:10:59 +0000 (UTC) Subject: Re: [PATCH] hw/arm/smmuv3: Fix addr_mask for range-based invalidation To: Zenghui Yu , qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: wanghaibin.wang@huawei.com References: <20201225095015.609-1-yuzenghui@huawei.com> <4e114709-e5c2-1860-c760-c05aa3ed5388@redhat.com> <45f3334d-f0b4-9a40-1bd1-78bd04735eaf@redhat.com> From: Auger Eric Message-ID: Date: Fri, 29 Jan 2021 14:10:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:11:18 -0000 Hi Zenghui, On 1/29/21 1:15 PM, Zenghui Yu wrote: > Hi Eric, > > On 2021/1/29 5:30, Auger Eric wrote: >> Hi Zenghui, >> >> On 1/28/21 9:25 AM, Auger Eric wrote: >>> Hi Zenghui, >>> >>> On 12/25/20 10:50 AM, Zenghui Yu wrote: >>>> When performing range-based IOTLB invalidation, we should decode the TG >>>> field into the corresponding translation granule size so that we can >>>> pass >>>> the correct invalidation range to backend. Set @granule to (tg * 2 + >>>> 10) to >>>> properly emulate the architecture. >>>> >>>> Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range >>>> invalidation") >>>> Signed-off-by: Zenghui Yu >>> >>> Good catch! I tested with older guest kernels though. I wonder how I did >>> not face the bug? >> Please ignore this wrong comment as this corresponds to recent kernels >> instead. Still puzzled anyway ;-) > > I noticed this when looking through your nested SMMU series and I didn't > have much clue about the impact on the real setups. > > I guess we may receive some unexpected fault events with this bug. But I > think we may miss it for some reasons: > >  - the stale TLB entries happen to be evicted due to heavy traffic >  - some form of over-invalidation is performed by your implementation >  - ... Yep I will further trace things. Anyway thank you for spotting it. > >>>> --- >>>>   hw/arm/smmuv3.c | 4 +++- >>>>   1 file changed, 3 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >>>> index bbca0e9f20..65231c7d52 100644 >>>> --- a/hw/arm/smmuv3.c >>>> +++ b/hw/arm/smmuv3.c >>>> @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion >>>> *mr, >>>>   { >>>>       SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); >>>>       IOMMUTLBEvent event; >>>> -    uint8_t granule = tg; >>>> +    uint8_t granule; >>>>         if (!tg) { >>>>           SMMUEventInfo event = {.inval_ste_allowed = true}; >>>> @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion >>>> *mr, >>>>               return; >>>>           } >>>>           granule = tt->granule_sz; >>>> +    } else { >>>> +        guanule = tg * 2 + 10; >>> maybe just init granule to this value above while fixing the typo. > > My intention is to initialize @granule to this value explicitly for the > range-based invalidation case. But I'm okay with either way. same for me ;-) Eric > > > Thanks, > Zenghui > From MAILER-DAEMON Fri Jan 29 08:23:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tke-0003Wn-Aj for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:23:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tkd-0003Wd-N2; Fri, 29 Jan 2021 08:23:51 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:44664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tkb-0007qW-Ml; Fri, 29 Jan 2021 08:23:51 -0500 Received: by mail-pf1-x42a.google.com with SMTP id t29so6216959pfg.11; Fri, 29 Jan 2021 05:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lmqeHCWqp9qghkyoc/CrFvAqWcZrXsJSJffMK75rvqg=; b=WTvqqt3TparG65WcKlpBXF5YgNWgklHPIm1phSSqCJIpaQeucW1M9gSpxHdrAFvqWB lGLiXO3nkYdWyTU+i+hfcDmSctkLs16yA8bxFDEEp6yUN8oPV4qgdtevXIQjsRoduymn Z0iAXjUrMF00yIs0zmj8ZrIhdjyXPO5OwSjYzjtbt0CVjaWbMazRQHCFN5edwWcxjAEj a+MTpQPo4PoSQS9cTJa0A55hbeGR6bF4ujwE3qEopIYrchUEuV+MDcsMVLeEqlSZYm7h KOYNgvp2h12K1zKnbY5gdTDjq3V9Rmg1DI2FbjgbhrqC4exEV4NUPyw7rXgnyUSuPljH 9fOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lmqeHCWqp9qghkyoc/CrFvAqWcZrXsJSJffMK75rvqg=; b=mctN1NkQnz9BBj3q3BxUWY6qmkdHAoblIJV8zxEoUuLzc9mEboDqE0L7fKMtdThvV8 8FCHVjDgKkyPQzuINdjqF6IXChoba0sStHdpYmmfqLJxYJh1Qvy+oGdzSjUwHPfNlceb i7kwHnxyUhUyBnkMro+r1KFZXWGj4xotNW3pNFvrPlkiIXc5DCLNqH+Q3r74YXm2L15F V8N8d65HRcSDQQ7aqliuD9CkfiwmxMABVj5E4lw3PzDiB76+kK6w5PDaBWvBzTGl2VRF zx2Npci3NbNs2Pfn340xSk/nZnYnPAEdC7IzpVGjSGZ4Db1b6qBx812Iv2U6jl2x63ij YxKg== X-Gm-Message-State: AOAM530myQ4nqhaTYe57ZYpLd37GfD+hR0N4F35lNao8a7h3dFzRmerc 2BaQyqUTRvg/Rq0KUTAZcXU= X-Google-Smtp-Source: ABdhPJy+KnUBTISazWITJ6vtkx9W4wcPMAAvn1RTN7ej0sgwvTuIC4qfdcRQHY4wPMbrjSTyIDgkzg== X-Received: by 2002:a62:a108:0:b029:1c1:119b:8713 with SMTP id b8-20020a62a1080000b02901c1119b8713mr4340831pff.74.1611926627431; Fri, 29 Jan 2021 05:23:47 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:46 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Fri, 29 Jan 2021 21:23:13 +0800 Message-Id: <20210129132323.30946-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:23:52 -0000 From: Bin Meng Starting from v8, the series is based on the following 2 versions: - v5 series sent from Bin http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 - v7 series sent from Philippe http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - remove imx_spi_update_irq() in imx_spi_reset() - chip select signal was not lower down when spi controller is disabled - round up the tx burst length to be multiple of 8 - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect - remove pointless variable (s->burst_length) initialization (Philippe) - rework imx_spi_reset() to keep CONREG register value (Philippe) - rework imx_spi_read() to handle block disabled (Philippe) - rework imx_spi_write() to handle block disabled (Philippe) Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v9: - Add a 'common_reset' function that does most of reset operation, leaving ECSPI_CONREG clear in imx_spi_reset(). - Do the LOG_UNIMP when the unsupported burst length value is written, rather than where it is used. - Squash the 2 LOG_UNIMP warnings down into one line Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag - remove the RFC tag - remove the RFC tag - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value - new patch: [RFC] rework imx_spi_read() to handle block disabled - new patch: [RFC] rework imx_spi_write() to handle block disabled Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() - round up the burst length to be multiple of 8 Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé (4): hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 +- hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++-------------- 2 files changed, 101 insertions(+), 57 deletions(-) -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:23:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tkj-0003dG-B4 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:23:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tkg-0003ZY-Te; Fri, 29 Jan 2021 08:23:54 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:46423) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tkf-0007sb-Cb; Fri, 29 Jan 2021 08:23:54 -0500 Received: by mail-pf1-x42a.google.com with SMTP id f63so6209806pfa.13; Fri, 29 Jan 2021 05:23:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kkLTOezkfKdPVe5VTO0yLce91pnJrqvoONkhLftQoZk=; b=eqEG4lbqJhLaCZLhPB91Aun/2c7Ahu1Agy2+z9p4cSbVDMViJJBZyR0BU9MsExrKwS v9n8skX2ZvtNqDMOWxMoN9iMbo1TwL1PQy3wt1d4ODxQjzo3Rn3V1Rf+7Qsgn0OtDJbR wt+FdK9K5B83+NOMFArOHh26vLPEOrr7e1JgX5iYGkR3qgfslsFORW8XeMzU2x8pGQZa 7xjSkimBdIfc4ncU0aDB7MV7Uld2dtR/1lz99KByhHEkGRlPdetOqme0k256W4w3LOB/ YXYfOYe6zgAoEhdNxH+sYIAZsCbnGEV+p6lOOsO6Y53WMQ7D39UByr2ZWo90K+MasIP2 I1HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kkLTOezkfKdPVe5VTO0yLce91pnJrqvoONkhLftQoZk=; b=fTpQNCBxipFagb/GmD5ROe3otdz1qfmlBLq8/Mi0MJ/9pGgSYvjeruXEVYzXMXUNvE qyN0Fy0X7UQug3UCw93fAWGhnEtyeAuuCjUYyykfdHvHh0mKvl72up/uloQS7THDbPjo THdFfQbRFPaGdsW5tJXTaoev9sNK3j41pavAvCcg8Yx1hVRKWoo5Y5fYZ3eq/0SvsvhD d96zKeAIBj0Mn1tSCRP5Wv4MttGxQ5TBF3pKI1SLzCxi6RS+Hzi5pYy2p6EGT0oRokVr bQ43qRBarRIQEAxzoLvb+WI3Vk3XNwJiyoHfkNQHUVgisZAaN1UVvdEm1CzWxYYMPfmO lbiA== X-Gm-Message-State: AOAM530gwPR4r27IYkqqW8Nk7W+RW3BN+wZ/c0jUwTOk7Z/wuAqZyuU6 2/NUIKBABKl21xeNpzioLpY= X-Google-Smtp-Source: ABdhPJy9NgTS3aaFYc2HlE0ft0ekaDM77VB+t9udjad8wE+2HXMq+woALq+JHIzrf7yi26OV9LoqhA== X-Received: by 2002:a05:6a00:16c7:b029:1bc:6eb9:ee47 with SMTP id l7-20020a056a0016c7b02901bc6eb9ee47mr4539608pfc.0.1611926631946; Fri, 29 Jan 2021 05:23:51 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:51 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng , Juan Quintela Subject: [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Date: Fri, 29 Jan 2021 21:23:14 +0800 Message-Id: <20210129132323.30946-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:23:55 -0000 From: Bin Meng Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Juan Quintela --- (no changes since v1) include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h index b82b17f364..eeaf49bbac 100644 --- a/include/hw/ssi/imx_spi.h +++ b/include/hw/ssi/imx_spi.h @@ -77,6 +77,9 @@ #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH) +/* number of chip selects supported */ +#define ECSPI_NUM_CS 4 + #define TYPE_IMX_SPI "imx.spi" OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI) @@ -89,7 +92,7 @@ struct IMXSPIState { qemu_irq irq; - qemu_irq cs_lines[4]; + qemu_irq cs_lines[ECSPI_NUM_CS]; SSIBus *bus; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index d8885ae454..e605049a21 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, /* We are in master mode */ - for (i = 0; i < 4; i++) { + for (i = 0; i < ECSPI_NUM_CS; i++) { qemu_set_irq(s->cs_lines[i], i == imx_spi_selected_channel(s) ? 0 : 1); } @@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ECSPI_NUM_CS; ++i) { sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tkz-0003k6-5P for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tku-0003ib-Rw; Fri, 29 Jan 2021 08:24:10 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:37752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tkl-0007vi-NZ; Fri, 29 Jan 2021 08:24:03 -0500 Received: by mail-pf1-x435.google.com with SMTP id 11so6229918pfu.4; Fri, 29 Jan 2021 05:23:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ja59qADvqfh/2q+KQY+LSk2zC5zuDWA+c5NUnArnusQ=; b=qIvbNySfjDas6JHaKn94Jzi284Ig8lyM4svVDtouJWOz0XRyzOeMBbXFn/n6Q4kqln eWxbFcmc9JqUXhiRTm0xFRswFsDTIwvKTs4UnXszcC0VLfPsJq7Eiy9EoOkiJObmdHJs S9IM4xFxb0tBrsckaY/x2FRQzAWZjJCMljV9fPAcpS42A+IOIk4v3sYTbnfVRYhjmS2J oBDMOmh/0WUFRl/TW7EMvxRxoJFNX/3X05n+WKG286GYpoQVghx/cy6mDzCG+CtO29K/ ZQu3YMLibD70fQIcgmYcea+AIf9kJx/yE3A7DJeWm1yMJTCfEiIxNxtvCtgtlw0LNHEm Eh+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ja59qADvqfh/2q+KQY+LSk2zC5zuDWA+c5NUnArnusQ=; b=L6Bw4N25zy0jvrIIJlnPgNxqw3OlokaSaT+9ZFfjEhnvDFIJexzQlGSn+GCiqUsLdS FxAQFeRJ4vVvRzYbq5RKK5nF08Pyp/3dPSVQ9RKrHnt2SCRPSVk4d8mEPi4ARwVCj4/o lKEVlRrC9tWTSJArRzIwFjKo4J+oPVVL17NnlXKkXyeDh7ly4n+QOVerV4tkFGvqPI26 ieYiWLb53H0WAK19uSRnFG+4Pk3dgt6qcRW/zxMVeaOa8aBq5eFztCI5VRb9XAWjtIoi RltYYqAk11lek4YVIoUdUnKsKKGuxA88IsN2XUijANV8YDjvQhDL6u3eZPRlHyrPHotk CsDw== X-Gm-Message-State: AOAM532d77fsNzW30fTpv7Kn1jCdwSscjvA6ckQUSXjPUhHgf7WxUC48 IexlRhNWOecrBj6ai58Qjxg= X-Google-Smtp-Source: ABdhPJyP0TXEaXYrtGfOVrtXdfAkWzyJqSHsZvoGjPrBhpiYvfwcQft87rmH0gJO/8No+xbZWNBxHg== X-Received: by 2002:a63:171d:: with SMTP id x29mr4779341pgl.168.1611926638249; Fri, 29 Jan 2021 05:23:58 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:57 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Fri, 29 Jan 2021 21:23:15 +0800 Message-Id: <20210129132323.30946-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:10 -0000 From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v5) Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e605049a21..4d488b159a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,11 +241,16 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); - imx_spi_update_irq(s); - s->burst_length = 0; } +static void imx_spi_soft_reset(IMXSPIState *s) +{ + imx_spi_reset(DEVICE(s)); + + imx_spi_update_irq(s); +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; @@ -351,8 +356,9 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); + return; } -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tl4-0003mK-IB for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tky-0003je-LC; Fri, 29 Jan 2021 08:24:15 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:33962) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tku-0007xw-Ew; Fri, 29 Jan 2021 08:24:11 -0500 Received: by mail-pj1-x1031.google.com with SMTP id my11so6461217pjb.1; Fri, 29 Jan 2021 05:24:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3jrYO5yz/J2x1yetvpXGtvLlgKXHVau4sRG7K210isU=; b=Jsdz9+/f/5wZFbrhXlxddOR3acr3mlGNT9rupY8Zl7SRBzvlgJMLKLEdvV8NY340ip bZHy0JFACntK7/mqWYLmyna29/oXiMNgr44k5kmmqX0LY9tEMiGNahoaA39TP/LZioWj nWRre2JvyEATHPrOMNEyBFqUf5nBENN4SRik/g9B6iMyKngy1zJNsOfhGdmm/gZeSltI Hx24nBjx3LxSmX3xLLgmvPXCOxBk4Vv5Dcktqf0KctWjP1OwQHq8MeYPWQXYGK6P3VGU 7MP3Ga1yypb38NC9FOByRoBmrdNXq5+OctlWta6+Lb3HdXZ+o2F5JdypevovXGrflknV L9dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3jrYO5yz/J2x1yetvpXGtvLlgKXHVau4sRG7K210isU=; b=gdUSVpxcPLVRT7NYVdgIqVli/LpjhnKLGipDOLS2kWBiV/2WV0Cwq9Jrd4ZbR6vqiZ C7lRZXYimcf6O9Xl4L0elCvuXKxGyja0PXDvwzCnoskaAHZc6/2KqL9lj+glSaLDD21E 93viJp6YV+AFfO9MZEkCCroHyRREmQhYfmdeOduWtrnk4AWvGZ3UKIcxwNddLXQK4OtE QQWhHv1wOCgqzEx2X/f2ItMu68qypfgbXSY8x+xWvjUuj0mx+uV99ME4f3R1TssFFhbD zCZwXeRkvq3gQHPMTqtVcHtnTVsyj3cgazoKnsy5g1sZNk2eBh+dSndAdr5EC7wy3AiL fDkA== X-Gm-Message-State: AOAM533TeTf894JP/5Cq9cXQC05SzbUixFazbgHn56CQKrJz29M2ypmr il0PMgrwJKFCbRawCI68AXc= X-Google-Smtp-Source: ABdhPJxwmX9NVkeIvUbjKBU3la09esY60T104AFAGjfoht4KeQ02bm3yVXzmYUjUsbvruLB5c43xdw== X-Received: by 2002:a17:902:9044:b029:df:fa69:1ed1 with SMTP id w4-20020a1709029044b02900dffa691ed1mr4204665plz.11.1611926645606; Fri, 29 Jan 2021 05:24:05 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:05 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Juan Quintela , Bin Meng Subject: [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Date: Fri, 29 Jan 2021 21:23:16 +0800 Message-Id: <20210129132323.30946-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:16 -0000 From: Philippe Mathieu-Daudé 'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-3-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization hw/ssi/imx_spi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4d488b159a..8fb3c9b6d1 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -434,8 +434,6 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); } - s->burst_length = 0; - fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); } -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:24 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TlA-0003ru-JG for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tl8-0003oz-Bq; Fri, 29 Jan 2021 08:24:22 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:39375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tl6-00082F-Nl; Fri, 29 Jan 2021 08:24:22 -0500 Received: by mail-pf1-x42e.google.com with SMTP id e19so6221381pfh.6; Fri, 29 Jan 2021 05:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5mXXyyknt34UXruqKVI1mRb9uaGtIfcaWSlxoOQ+8iA=; b=b0+IhryofXgzeqY/ClfgBYRj1BGdTbR0F00TslTqkjyhVRlWYmUStnxQEK9GO622UB nanKSaSp2uKzgTVTHq1GIE2ey2agSRhilKZX7WbN4AMuOAOJun6amrLbiIPfmfDNeH7M K1y/IFD4sOKXVZsVsQ1Dit27HEn4zvcsJf/zgiuFJoBEOQxF8rTOV3IJzCi0IdZ3+qPO oATD6Fsy98GVAgQJSghr8ycrtBH/cUNrr9il8BBnn8YYqYwMxd8aMM6QVA9vCLB2E95Q OD6ht5ioOnDFnelWfXetB2o8gnnmFxHdyQCjei7aSiLZppjYLFXNzLkMq2vrV80ZEh2d Nb8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5mXXyyknt34UXruqKVI1mRb9uaGtIfcaWSlxoOQ+8iA=; b=CxJ1k75yi+2mvDUjqdVDVyMbd5ULklldt+7iNgHjwuhuEQP6ahnpkye0N7GZwfDZNh 0QXo1GRe4RsxjnvdmvfoU2SUdO2mF/l9aPp84nEFFJwR0vcRNOzDW+J3JuSBuWsBy5aF qDPfIvyYKu4HOl3VHm5fNMIRwuezd4bS/IuqUKkdtwmReQn4784sQ73YsnjTiBMYVQfZ 6UHLV85H1aUzYUX6WiunUlZ19JLXb045uDQ0XCOSNCvEh2oZJUOWvrbbYpIkzXboYrYC 2GWu5wYPqC24lPRfKUdSQmJ/MUT4BemYUg/lcrAPtuK/9k9M9ArymKkeukyzHCNZbPe8 PDOQ== X-Gm-Message-State: AOAM532tEna3Gzd+vPClS42xbvUXun1TyA631UoVc3Lai5xfcNOaQsMi DMWxvxfC8We2pWA66UxiM8Y= X-Google-Smtp-Source: ABdhPJw+kj3ROHXFi8kQDZQTvlZ8HNyZPrzfnTnDsfJf/0ERhh6HxaEW/hWlxWsOXRq2rvVQtepx7g== X-Received: by 2002:a63:c64:: with SMTP id 36mr4751076pgm.282.1611926659235; Fri, 29 Jan 2021 05:24:19 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:18 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Date: Fri, 29 Jan 2021 21:23:17 +0800 Message-Id: <20210129132323.30946-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:22 -0000 From: Philippe Mathieu-Daudé When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé [bmeng: add a 'common_reset' function that does most of reset operation] Signed-off-by: Bin Meng --- Changes in v9: - Add a 'common_reset' function that does most of reset operation, leaving ECSPI_CONREG clear in imx_spi_reset(). Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8fb3c9b6d1..e85be6ae60 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); } -static void imx_spi_reset(DeviceState *dev) +static void imx_spi_common_reset(IMXSPIState *s) { - IMXSPIState *s = IMX_SPI(dev); - - DPRINTF("\n"); - - memset(s->regs, 0, sizeof(s->regs)); + int i; - s->regs[ECSPI_STATREG] = 0x00000003; + for (i = 0; i < ARRAY_SIZE(s->regs); i++) { + switch (i) { + case ECSPI_CONREG: + /* CONREG is not updated on soft reset */ + break; + case ECSPI_STATREG: + s->regs[i] = 0x00000003; + break; + default: + s->regs[i] = 0; + break; + } + } imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); @@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev) static void imx_spi_soft_reset(IMXSPIState *s) { - imx_spi_reset(DEVICE(s)); + imx_spi_common_reset(s); imx_spi_update_irq(s); } +static void imx_spi_reset(DeviceState *dev) +{ + IMXSPIState *s = IMX_SPI(dev); + + imx_spi_common_reset(s); + s->regs[ECSPI_CONREG] = 0; +} + static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) { uint32_t value = 0; -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:30 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TlF-00045o-W2 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TlE-00042c-S6; Fri, 29 Jan 2021 08:24:28 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:44029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlD-00084l-35; Fri, 29 Jan 2021 08:24:28 -0500 Received: by mail-pl1-x62c.google.com with SMTP id 31so5212870plb.10; Fri, 29 Jan 2021 05:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SXP/QcpeVzooZtaZF1E9k2db9E1DHz3DCHI+nO8tjBw=; b=hZjiIhA6dPA+zXViVBMDAzzdbf0phBVB0mp9AJGWUtJELzLciuzF08A7GDSrfRoM0i keYO8x+FmtiFdWjEnmHPrtFmi2kMXGWRlDISpwv9fCjYkWBhwR754+K1DLzPKw3u5c6v WTVshjqoGu3RPM2DDaBJwExM39uemw7EHPt/azYaZDHLeyz2EOcTu+xS3Xplu+QSVLHK opIZSKHnXlTp20xYPdlNstnAaPxGBVY/5TuvqVzPjppyHo/gXLSDO5ax/fPgJTK3U112 6f3eCNPUH85xYkxS7yyfYXW0DxCC3YbxpVfspCWJdWYra3Q7odD4HQryE6ViSEWKjwi0 Yl9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SXP/QcpeVzooZtaZF1E9k2db9E1DHz3DCHI+nO8tjBw=; b=MaQFkOgWL2twO8iFi9YpsJmaBVwuzpbuZ3ZYd1dUaKUgE9A5/zEL1CQfgguXj8mNYG 7mUuDKlw6RPnQuFIvV7YKCqVqAyMdNdculdLspzGFfLUn8ZaZOWy/4x2Jo2G4pIwtVj5 s4PsC5+oCwpDfL1sHHtaUBnDwfyg0febMb3OW5/kE2duDjw9OE/Z520sF4lasAvzYA8h fBTeDYhtS0tqYNvvlTYkmrIdo5OytfCmbe0nGuC1YEmQWzgliehPmoGvoMYEu5v0CrFY xq2JT5BwMqDJE6BdgWMejYNm7RAzQjKwdfCnnkUSnH3Twnb5UaOTBZx4nb/KQGNgyw3C +hzg== X-Gm-Message-State: AOAM5301PYjx5XK8BQpWZy+9Ji6Sm2YrXD5cAnXgxSQR3BkvIyMTBTuR Ol0+Ur4rBt9zc3MYmLroYAaibYVGx/PK2g== X-Google-Smtp-Source: ABdhPJxiM7yYKjosSrFZBr1PDdObFsKr1Q0N0TZ26Tc+VoY12rCpr0QMou5VdAAfEb3bOP9gyo4zIQ== X-Received: by 2002:a17:903:248f:b029:de:c703:9839 with SMTP id p15-20020a170903248fb02900dec7039839mr4318910plw.42.1611926665489; Fri, 29 Jan 2021 05:24:25 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:24 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Juan Quintela , Bin Meng Subject: [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Date: Fri, 29 Jan 2021 21:23:18 +0800 Message-Id: <20210129132323.30946-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:29 -0000 From: Philippe Mathieu-Daudé When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v7) Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_read() to handle block disabled hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index e85be6ae60..21e2c9dea3 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -279,42 +279,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) return 0; } - switch (index) { - case ECSPI_RXDATA: - if (!imx_spi_is_enabled(s)) { - value = 0; - } else if (fifo32_is_empty(&s->rx_fifo)) { - /* value is undefined */ - value = 0xdeadbeef; - } else { - /* read from the RX FIFO */ - value = fifo32_pop(&s->rx_fifo); - } - - break; - case ECSPI_TXDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", - TYPE_IMX_SPI, __func__); - - /* Reading from TXDATA gives 0 */ - - break; - case ECSPI_MSGDATA: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", - TYPE_IMX_SPI, __func__); + value = s->regs[index]; + + if (imx_spi_is_enabled(s)) { + switch (index) { + case ECSPI_RXDATA: + if (fifo32_is_empty(&s->rx_fifo)) { + /* value is undefined */ + value = 0xdeadbeef; + } else { + /* read from the RX FIFO */ + value = fifo32_pop(&s->rx_fifo); + } + break; + case ECSPI_TXDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from TX FIFO\n", + TYPE_IMX_SPI, __func__); - /* Reading from MSGDATA gives 0 */ + /* Reading from TXDATA gives 0 */ + break; + case ECSPI_MSGDATA: + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: Trying to read from MSG FIFO\n", + TYPE_IMX_SPI, __func__); + /* Reading from MSGDATA gives 0 */ + break; + default: + break; + } - break; - default: - value = s->regs[index]; - break; + imx_spi_update_irq(s); } - DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); - imx_spi_update_irq(s); - return (uint64_t)value; } -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TlO-0004QH-3N for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TlM-0004M4-GI; Fri, 29 Jan 2021 08:24:36 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:39116) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlK-00087N-TP; Fri, 29 Jan 2021 08:24:36 -0500 Received: by mail-pj1-x102c.google.com with SMTP id d2so349483pjs.4; Fri, 29 Jan 2021 05:24:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CYYrdLg8vwL1EwiAwyU49IXmkoVufUhG59tZxDTUReI=; b=PMe3wFhDhgPzoDfad4eKyVep97acC75SIQEExp6Jj+Vc3sqFul7qCtxdbCnfPAq9Ir 78AvJJ44Lov7iaoW5cAtW+Ty/NX4VqLxk3XLgIDpVlT0rxF229no3Gkab29cSi00VZPX IYnXWbu7L6H4YwN6hQBya5RCUK/mwwUSIzuXTg5s5V+rUqGm/BHC8XD1Gk7f1z8u1F5x 0Mt6zWdJ5Bh7c+cKdWw0/0Uo9LwRhHZcPLQl5FhZ/WgL4TerJucN4mJ7hvpqnhY/GPbA yjNhMDvAVSG8obxsIetjjoBqkSYQvOLo3fgJ5JfjHEnO/Sa1Ey7gDegpYo2lI3rDncYn 5i5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CYYrdLg8vwL1EwiAwyU49IXmkoVufUhG59tZxDTUReI=; b=ReGpJLfR8ByHwcO+j76RHC2+FKwvWiJYQCLU8SFxyjx+l0jxTBsT00GfUzptWNI3cc 8GBtlYwsfX3438xs90BQnzE3yScpSzqQBXAt0SBsxSNUd0I516AFHqfOYkX4XixlUkQD Kl4FHAzLlMH3It+r/h/Ltxw0hzs7Ilf4deZR3+rog97hw8NFXTQjgI9L5mwGnbUigJ2Q GO3umgv7mlw2/ChqvqAPVZ4VAzcGqT8X6xw5EH1ZqsuykVSl1z5KIDB2IV4NQWc67KTb nGZlDPRYZo9dRUIkGABhDu8uBCi6WZX3cd3p+8Atz4mQk+sQ/3kD46wolHZD8azJ5j1W m2BA== X-Gm-Message-State: AOAM531k9fXaxdBYks0T/txGl/oSMWROYhnsHxIqGxzJ2/lELQxef7vE WCgNQq3CX/DXr9XQM/J24bA= X-Google-Smtp-Source: ABdhPJx7683h5kyDUCY3JNpP/22LqpFP9fj3vAM4rO5zJi36v7/7QQUGC9/CwkaFUhQYghahsMhqwg== X-Received: by 2002:a17:90b:350b:: with SMTP id ls11mr4558026pjb.166.1611926673237; Fri, 29 Jan 2021 05:24:33 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:32 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Date: Fri, 29 Jan 2021 21:23:19 +0800 Message-Id: <20210129132323.30946-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:36 -0000 From: Philippe Mathieu-Daudé When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v8) Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag Changes in v6: - new patch: [RFC] rework imx_spi_write() to handle block disabled hw/ssi/imx_spi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 21e2c9dea3..4cfbb73e35 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -332,6 +332,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + } + change_mask = s->regs[index] ^ value; switch (index) { @@ -340,10 +348,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; } -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TlV-0004k4-HT for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5TlU-0004fw-0o; Fri, 29 Jan 2021 08:24:44 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:34096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlS-0008BS-Ar; Fri, 29 Jan 2021 08:24:43 -0500 Received: by mail-pf1-x434.google.com with SMTP id m6so6233925pfk.1; Fri, 29 Jan 2021 05:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=arRlN344IEUt++/WHKWnko22ZyvawohyzOe7fEOUZng=; b=dXXRH7+HALphmZwtowWgWVoD9g01u3ZkMMwybZiPR0dEB5gWsNBn7AbfpA4j4rrKhn JiCYNFZOVRZpiw+gOdUH+woomiEB/lrac5V3bPm1dQCQFtXuAAVnvgaesGJAKUsbh4V3 ukI/2cRrBXJZmbRMJkRtK7jIOdhmPCm0VYKlCWy1NzLZFj09pN6o3nGvqiJ3QEgYU+nZ 6ao3CRdiiCl5VmGFVbvGzBBBiLNu7727JYDc1uJP6Bi+XQIXzAwTWzHdvRpQccZMzeTC +YhJlbiVVKrX06Br7cMtGQMimjzY+ld+jt6Q/pOHw7KXkduLniVlvzGsZCMP27kC14Ur LDmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=arRlN344IEUt++/WHKWnko22ZyvawohyzOe7fEOUZng=; b=a1XcS6MyJiZSyIwQnWNB7lLqlYYtTA6MicFY3ecQDZHJbdrG2+yG+miBYDdw1Or7sH SQlsJhtyOQ11U0/oXE5KkODHnJTkc3c7qTsxZvH3u/BXjXTf5r8/1mEaaGZ9YA4+qEqq ygIgqtr1j3ijFvfOt2DdLkZZGO/yxHfLo9qdv7FYJjHMqYc7pgGAW7qk01Cl/LsHal3t jlFp3B/mK67YvHeauqeW0oeaxLEUlbSpBYhpjIj2zkU3bgrcRalqmfMTN4fqNBe8ETXO t5cbjG3OBgOU4Jb3HjQ5D0MqT/SlXTzb40/DSWOtNx0psESh/BaQaelbRQycmtL9Ijf8 FZCQ== X-Gm-Message-State: AOAM533jHyog9E59QokXA/ZOzj/Y5PkYj9y1i4Oj70nzwoTM67QTInb5 PhbIwdy2tbBPROGlDi9lzwqJ7yHEnRTJ3Q== X-Google-Smtp-Source: ABdhPJyeDaszL+aAJHwbf4bAc976WnzFYmUiUnOfHZu9EnsUjO6o3Mq4JHdwUdQjLJ2dmVQfffTZBQ== X-Received: by 2002:a63:c441:: with SMTP id m1mr4659328pgg.353.1611926680772; Fri, 29 Jan 2021 05:24:40 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:40 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Xuzhou Cheng , Bin Meng Subject: [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Fri, 29 Jan 2021 21:23:20 +0800 Message-Id: <20210129132323.30946-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:44 -0000 From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_soft_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 4cfbb73e35..2fb65498c3 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s) static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_common_reset(s); imx_spi_update_irq(s); + + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static void imx_spi_reset(DeviceState *dev) -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:24:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tld-0004xD-NO for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:24:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tla-0004vE-92; Fri, 29 Jan 2021 08:24:50 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:39898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5TlY-0008EE-Jo; Fri, 29 Jan 2021 08:24:50 -0500 Received: by mail-pg1-x52a.google.com with SMTP id o63so6649561pgo.6; Fri, 29 Jan 2021 05:24:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LFsuI0BABtR2qo+SroCf7kUB6qpaMqblWl0znWx3WO8=; b=KlXJxjm7esUMyRKo6adtW3JPyDDQb0UuMcWWb/KUNRlRNzaxQ10p0IM+Y6MaBZNjrZ Ic3e5wmhGrLVSv5BOhDW9z68GTYz3Ttdf//JEZnqSBXjxaMvUIN0u95V0eEwL8N+zZ+e huVJWOosgVOqExr6rY7XNnYeu+9u5ogZ8vZWuJSiDX0XqPVsr8jgB3PCK7nGWbwOvxeB G6Gr20976+FLPBVDZnUcdw403nD3UNH+GJ6CiX7aRDphPkLbdd9lEhxRPMZl8zz+zhs3 eYXxVMfEL0X77wgRT3xOu2e3/EwS4BJ6hTiT/kxZYwhuPoUO6UvaswDCNr8pysy5UsZh mkDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LFsuI0BABtR2qo+SroCf7kUB6qpaMqblWl0znWx3WO8=; b=GzMJtvrKCY/vcjs3kntBVUU4mbnfee1WQWv5sq0fIbL+g2SKJnhiyavBNz/GcAnk9v mViuL9syCkECo+kcM4vGf7Z06VpgScBo18O3X2EdI6YqQCvwjD0PineROfgiqY+8oD9C JeskOIp/oFlMWBT/5QBmu5FmxUFVRg9DoeoJJPOSbvTfAsVB7mV/hDG1NaLE5aTbWmrZ 1WggfcCuTsLnC6E7EuhOWc+9ryW2UyTtCQoRYeoick+CvG4um3fMwzfeEp5Gq4q17yyM 6lsD+aPo2aTpyiw0o6x4ibwCreYUJZ3Ktzcgtu2nseeBQyrZg9sPaNIqdiBKmSaCyHcN OG0Q== X-Gm-Message-State: AOAM530mTvOoeAMJ2bdGMY92mzbSeeUdw4zkyqs04upXhZJzseFu6Eke 5ngWVD5KXrpjWGBw54NpSgMjOy9NgwGV7Q== X-Google-Smtp-Source: ABdhPJyramRlfvvjxqOVjQnQmZ3mTD0h+BvuhHA5Rzk02dtUIs82J8hxnVWMNa2DWgdmSDLCtkX38A== X-Received: by 2002:aa7:99db:0:b029:1ba:5263:63c4 with SMTP id v27-20020aa799db0000b02901ba526363c4mr4272972pfi.53.1611926687117; Fri, 29 Jan 2021 05:24:47 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:46 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Date: Fri, 29 Jan 2021 21:23:21 +0800 Message-Id: <20210129132323.30946-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:24:50 -0000 From: Bin Meng Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng --- Changes in v9: - Do the LOG_UNIMP when the unsupported burst length value is written, rather than where it is used. - Squash the 2 LOG_UNIMP warnings down into one line Changes in v5: - round up the burst length to be multiple of 8 Changes in v4: - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: log unimplemented burst length hw/ssi/imx_spi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 2fb65498c3..41fe199c9f 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -128,7 +128,14 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s) static uint32_t imx_spi_burst_length(IMXSPIState *s) { - return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + uint32_t burst; + + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + burst = ROUND_UP(burst, 8); + } + + return burst; } static bool imx_spi_is_enabled(IMXSPIState *s) @@ -328,6 +335,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, IMXSPIState *s = opaque; uint32_t index = offset >> 2; uint32_t change_mask; + uint32_t burst; if (index >= ECSPI_MAX) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" @@ -380,6 +388,13 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, case ECSPI_CONREG: s->regs[ECSPI_CONREG] = value; + burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; + if (burst % 8) { + qemu_log_mask(LOG_UNIMP, + "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n", + TYPE_IMX_SPI, __func__, burst); + } + if (!imx_spi_is_enabled(s)) { /* device is disabled, so this is a soft reset */ imx_spi_soft_reset(s); -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:25:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tly-00050x-Nk for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:25:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tli-0004yY-1S; Fri, 29 Jan 2021 08:24:59 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:36006) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tle-0008Gl-KS; Fri, 29 Jan 2021 08:24:57 -0500 Received: by mail-pj1-x1036.google.com with SMTP id gx1so6367217pjb.1; Fri, 29 Jan 2021 05:24:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hwvGbS5LDh3Z8XeKXBpeFCpn6ZrLyIA6WHiWs4apvvk=; b=mr4LoVFyg9DSHeXNRf7unLz5ftmUe5SWWI34UulD/YDMDV1YEA1S+mz5v2MFpjGTjm KO5b5bLoI6Nwu3S2lmRp6iEpfPKLs9dtXsuf92QLCZJLccVSvtUDmYZfSyQiMjbPs62T 6+MIwLBmff0zGTg08J4MVleQyxJRyNKBBnFMPPQLe8P8g/ets5x2+i3IiGJrkHfMlnJP 5WkzvMV/0Ey3ZT8HDxaEXYYjrFOFEwIQuE4IOBV2MozAsq2CFbMNaK7N8QLWdiIG8whM BziRgKHJGw8BfLW+oLZKCVCxHwhNi6b8Jt3PW12/SIImDhgaIVJiYCjNvhZIQUFsqfH+ Cu4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hwvGbS5LDh3Z8XeKXBpeFCpn6ZrLyIA6WHiWs4apvvk=; b=kNPROJLL80Sam/efVDvdes/A8+60rg75DWtuh30lb/mF8CAvXebzA6KasMkIqNscuI mWOtriXw9UFpqyh6IN7CTu+5eVFc6o6oKDLn0rP2l6CYcRGFAQ7itNIzVF4Oq1AyAthW 7d7/UIxX0MmELDSdzeUvpX5MBnBnqW4eMhw7Egs3AXUDG+abiX7lFZkuYVseNeuEPeEt pJHEVJ+k3+yMg5zJmhNTFsYNWT+qhYIE+vSQ/ashKBpj+Jdh9QzmP2oQ6eJu/KTyv1mH 9cHPU0BLfAo2vsDWzv4fpUSAQ/bltpUn4oG2O5HmsMeMxo5hzyl+VBBsdyqE3TSxeSGd PdxA== X-Gm-Message-State: AOAM530ny35j5LxHnAu7H8Vve0KKrhLzX2rFDBK2kMduBprlDEU+RtY4 Fzry8h5gPUS/iPEYPX1j5P4= X-Google-Smtp-Source: ABdhPJyKu6/e2RK/0Ch51/84uwiGqDVYoOvjHpnzV27QN6DO7vupw1JjvGe/SqtFZo4+lBW62R+YBw== X-Received: by 2002:a17:90b:3792:: with SMTP id mz18mr4505328pjb.23.1611926692580; Fri, 29 Jan 2021 05:24:52 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:52 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Date: Fri, 29 Jan 2021 21:23:22 +0800 Message-Id: <20210129132323.30946-10-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:25:00 -0000 From: Bin Meng For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- (no changes since v2) Changes in v2: - Use ternary operator as Philippe suggested hw/ssi/imx_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 41fe199c9f..a34194c1b0 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -185,7 +185,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("data tx:0x%08x\n", tx); - tx_burst = MIN(s->burst_length, 32); + tx_burst = (s->burst_length % 32) ? : 32; rx = 0; -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:25:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5TmB-00051w-80 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:25:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tlq-0004zC-L0; Fri, 29 Jan 2021 08:25:09 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:39118) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5Tlk-0008KT-JL; Fri, 29 Jan 2021 08:25:06 -0500 Received: by mail-pj1-x102c.google.com with SMTP id d2so350031pjs.4; Fri, 29 Jan 2021 05:24:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m0BdiYb2aO99L/y+s2LkY0AUaYKp2VRWJME7aRkjESk=; b=Ye19j0Hcekw+MArdFXSXZqQ0YaD/Pu6ySTpe1zmcgYsZs949nH3W/fQHgIc8uUEgdI zXk7SJeUn+re+yGURTkWdJTM7OirSioegfaWipkgraR/NpW5fbXtNmr/vSzLzRDYTWxN +po9w8ZLkwVvM4ZDpaDLWKEFVE2OXh1wHx3UPEzXRY0SToc5GAykajZn75HzXNLAlybu 836fQ4bON+dpsF6c3w9y34ZYjGqgJHLk3LqJo83RBuXjffKtYw1UhdxtaKDAUTaLD0dN QZx41Hmy5mv+/VSBnYXAScbdHuMoAHVjaKds6VakFhPCHwPtAtrFy/R1iJtWpjEhiDzo JplQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m0BdiYb2aO99L/y+s2LkY0AUaYKp2VRWJME7aRkjESk=; b=SmSvChea63SizAq34q2Z8db3MYwaYAyRXFpOxXhwWcG3m2YNHyWIXFSuuYG2uzgFtB Nk+Tuz+/Hy4+2ubk456rRii/8vwIUehYSZWys974y9nIVsTbDmBnSsaMsg6RRORFRDf9 GyIf3tziY+mw51I/kJ6iXNqhWY+dAgbui1CLpATIRZGfH2WJs0aTY0kp7zTsTdpk2vba ciqbOCKaHlRXEcb9qUdpzFNB6DkKzqFite+H8xaqYltuXjw2OhTBH0+xo0Zh5xsWFvOX 1pIDn6v5f3gQXL9fZO0up1O840/lawT8Rf3OPQA/RbIKNNqGYDc9XKwo2YiffvzQt1kM wvUQ== X-Gm-Message-State: AOAM531I0iRUUlUoguAG7s82GUbp1pKhi4q3CT0F+5/5WMZ/YuCkxipf kXwko0pBbULoybjuO1r4QP4= X-Google-Smtp-Source: ABdhPJwAFrc6RveqiX+PcFtbEz0D6jtRlGRjLinj3n0u+YF9grcRCW/ujnYWI5VlfaH26z8BxLuU7g== X-Received: by 2002:a17:90a:8006:: with SMTP id b6mr4577952pjn.108.1611926699170; Fri, 29 Jan 2021 05:24:59 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:24:58 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng Subject: [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Date: Fri, 29 Jan 2021 21:23:23 +0800 Message-Id: <20210129132323.30946-11-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com> References: <20210129132323.30946-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:25:09 -0000 From: Bin Meng The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng Reviewed-by: Peter Maydell --- (no changes since v3) Changes in v3: - Simplify the tx fifo endianness handling hw/ssi/imx_spi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index a34194c1b0..189423bb3a 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -169,7 +169,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) while (!fifo32_is_empty(&s->tx_fifo)) { int tx_burst = 0; - int index = 0; if (s->burst_length <= 0) { s->burst_length = imx_spi_burst_length(s); @@ -190,7 +189,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) rx = 0; while (tx_burst > 0) { - uint8_t byte = tx & 0xff; + uint8_t byte = tx >> (tx_burst - 8); DPRINTF("writing 0x%02x\n", (uint32_t)byte); @@ -199,13 +198,11 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) DPRINTF("0x%02x read\n", (uint32_t)byte); - tx = tx >> 8; - rx |= (byte << (index * 8)); + rx = (rx << 8) | byte; /* Remove 8 bits from the actual burst */ tx_burst -= 8; s->burst_length -= 8; - index++; } DPRINTF("data rx:0x%08x\n", rx); -- 2.25.1 From MAILER-DAEMON Fri Jan 29 08:26:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Tn4-0005Pj-1P for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 08:26:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Tmz-0005Nh-23 for qemu-arm@nongnu.org; Fri, 29 Jan 2021 08:26:17 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:29541) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5Tmm-0000OI-6T for qemu-arm@nongnu.org; Fri, 29 Jan 2021 08:26:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611926762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4DTIlqlzKHu/MH0vna3+FLcXFx3UeJ+NZ435qFT+9Cw=; b=DkIqsUC7gAnx+QdJ8cpzQK8wt87DA434CXyGFEa4tZxUdCijIE0oyV6IZeU8CQSg5BM85B VeT+JjgDOGsi6xMvlVeUC8BPVgv/M67f4qTP8dXmd3PXfZJ8+LOildckjl72rkGeugN39V TtFuNGYYDYMpkv5vRU64X/PijbZHQzE= Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-257-oNI1fABRM0eiqQJZg7bkyg-1; Fri, 29 Jan 2021 08:26:01 -0500 X-MC-Unique: oNI1fABRM0eiqQJZg7bkyg-1 Received: by mail-wr1-f71.google.com with SMTP id j8so5056533wrx.17 for ; Fri, 29 Jan 2021 05:26:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=4DTIlqlzKHu/MH0vna3+FLcXFx3UeJ+NZ435qFT+9Cw=; b=JDpHCB8SEgkX/rEl1RufcL9xifGx/Op763PQtYMYWAF2Rgjl7FGRBUA36YPM5Y2Xbe kEmz/qX9hZcxPKmQMtLOs5lVBRVSZtuJhoKCWf34YptN3uSVLNNxJyhu37heAhWW9TUV JVhKMdI/M9XgkV+omovqnMMj3LP/eS+6txUjd5sYxhUJN/pVNoU4SDXahP/luUq0g/by GIolA1VbNo+MtWgTZX28BH+YfuG4dYJGb34W/AT7Vo6FKUthnsr62hSWluY3Toqa6Olc Nv5BwvpacHStKnng8LKYzppiM7bgchgHRHTFrXlsYpNNDQHs2Lq4I2oKiLdLsXjQYjtj 2CpA== X-Gm-Message-State: AOAM532POeP9BJCVXAy4m1hL+GyTd8PWcPMH+blw8EnOjSM2gCAfG2E6 FVjXMF03L6GDxRHCoFyjQgIYZ6t28OiOM/2XT4l7Xx+QNReMlU7au/xBBBUzRyUQsMG9OagmZf8 puZf2czQ5QZoq X-Received: by 2002:adf:eacc:: with SMTP id o12mr4541818wrn.202.1611926760041; Fri, 29 Jan 2021 05:26:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJwf5C+zUojbwKD/S7hjo6X/LXxzFIjmdmTwbvtyuRN9lv5srbjeEuRSxjtzzu0cRyA/WLabkA== X-Received: by 2002:adf:eacc:: with SMTP id o12mr4541778wrn.202.1611926759874; Fri, 29 Jan 2021 05:25:59 -0800 (PST) Received: from ?IPv6:2001:b07:6468:f312:c8dd:75d4:99ab:290a? ([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id b11sm12236438wrp.60.2021.01.29.05.25.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Jan 2021 05:25:58 -0800 (PST) Subject: Re: [PATCH RFC 0/1] QOM type names and QAPI To: =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Peter Maydell Cc: Markus Armbruster , QEMU Developers , "Edgar E. Iglesias" , Alistair Francis , Gerd Hoffmann , John Snow , Kevin Wolf , Max Reitz , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Mark Cave-Ayland , Artyom Tarasenko , Jean-Christophe DUBOIS , Peter Chubb , Andrey Smirnov , "Michael S. Tsirkin" , Marcel Apfelbaum , Fabien Chouteau , KONRAD Frederic , Juan Quintela , "Dr. David Alan Gilbert" , qemu-arm , Qemu-block , Eduardo Habkost References: <20210129081519.3848145-1-armbru@redhat.com> <20210129121752.GJ4001740@redhat.com> From: Paolo Bonzini Message-ID: Date: Fri, 29 Jan 2021 14:25:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210129121752.GJ4001740@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 13:26:17 -0000 On 29/01/21 13:17, Daniel P. Berrangé wrote: >> On this one, my vote would be "no". "Versioned machine names >> include the QEMU version number" is pretty well entrenched, >> and requiring users to remember that when they want version 4.2 >> they need to remember some other way of writing it than "4.2" >> seems rather unfriendly. And 550 uses of '.' is a lot. > We can't make keyval_parse() accept "/" instead of ".", but can > we make it accept "/" in addition to ".", and then encourage "/" ? > > People simply wouldnt be able to use "." as keyval separator if > they're using typenames containing "." (or would have to escape > the typename. '.' is much more common than '/', and is shared by about all programming languages that have JSON-ish data structures natively. So using '/' seems decidedly worse to me. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id p17sm10251524wmg.46.2021.01.29.06.00.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Jan 2021 06:00:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Bin Meng References: <20210129132323.30946-1-bmeng.cn@gmail.com> <20210129132323.30946-5-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <26c7af92-ae7f-a522-b27c-854575a5b078@amsat.org> Date: Fri, 29 Jan 2021 15:00:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210129132323.30946-5-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 14:00:40 -0000 On 1/29/21 2:23 PM, Bin Meng wrote: > From: Philippe Mathieu-Daudé > > When the block is disabled, all registers are reset with the > exception of the ECSPI_CONREG. It is initialized to zero > when the instance is created. > > Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), > chapter 21.7.3: Control Register (ECSPIx_CONREG) > > Signed-off-by: Philippe Mathieu-Daudé > [bmeng: add a 'common_reset' function that does most of reset operation] > Signed-off-by: Bin Meng > > --- > > Changes in v9: > - Add a 'common_reset' function that does most of reset operation, > leaving ECSPI_CONREG clear in imx_spi_reset(). > > Changes in v7: > - remove the RFC tag > > Changes in v6: > - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value > > hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++-------- > 1 file changed, 24 insertions(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Fri Jan 29 11:47:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5Ww6-0007TE-Db for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 11:47:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5Ww4-0007PD-P6 for qemu-arm@nongnu.org; Fri, 29 Jan 2021 11:47:52 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:46021) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5Ww0-0005qk-Vt for qemu-arm@nongnu.org; Fri, 29 Jan 2021 11:47:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611938867; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EPVxtxHxIUq9zEdlN142XeBBUBWg/58YUqpF6UM0V5Y=; b=azCgDM2KPdQiD1KdPIE3AJG8yOnGvcB2wzlO08mW9k/K42ZPmCwfEW+cg+pQtQe3zshl3f Cqa//RBLizsUFs6nAjP1ZFQkoiJmtaZrs6jCKM/bnrZnYRi6BrnfMJ4xG9m5zF23pVV22L 5xvsZXU7jUa+xyUrZldBLYKwEU+3Xes= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-212-uvyfzPXDOL6tZkkSs8luFQ-1; Fri, 29 Jan 2021 11:47:45 -0500 X-MC-Unique: uvyfzPXDOL6tZkkSs8luFQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 609D08030A7; Fri, 29 Jan 2021 16:47:43 +0000 (UTC) Received: from omen.home.shazbot.org (ovpn-112-255.phx2.redhat.com [10.3.112.255]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8C8035C1B4; Fri, 29 Jan 2021 16:47:36 +0000 (UTC) Date: Fri, 29 Jan 2021 09:47:36 -0700 From: Alex Williamson To: Paolo Bonzini Cc: "Dr. David Alan Gilbert" , Keqian Zhu , Kirti Wankhede , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Philippe =?UTF-8?B?TWF0aGll?= =?UTF-8?B?dS1EYXVkw6k=?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , Igor Mammedov , wanghaibin.wang@huawei.com, Zenghui Yu , jiangkunkun@huawei.com Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener Message-ID: <20210129094736.230023cc@omen.home.shazbot.org> In-Reply-To: References: <20210111073439.20236-1-zhukeqian1@huawei.com> <20210128200223.GJ2951@work-vm> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 16:47:53 -0000 On Fri, 29 Jan 2021 08:49:53 +0100 Paolo Bonzini wrote: > On 28/01/21 21:02, Dr. David Alan Gilbert wrote: > > * Paolo Bonzini (pbonzini@redhat.com) wrote: > >> On 11/01/21 08:34, Keqian Zhu wrote: > >>> +static void vfio_listener_log_start(MemoryListener *listener, > >>> + MemoryRegionSection *section, > >>> + int old, int new) > >>> +{ > >>> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); > >>> + > >>> + vfio_set_dirty_page_tracking(container, true); > >>> +} > >> > >> This would enable dirty page tracking also just for having a framebuffer > >> (DIRTY_MEMORY_VGA). Technically it would be correct, but it would also be > >> more heavyweight than expected. > > > > Wouldn't that only happen on emulated video devices? > > Yes, but still it's not impossible to have both an emulated VGA and an > assigned GPU or vGPU. In fact, that's often the recommended configuration, particularly for vGPU where we don't have a vBIOS. Thanks, Alex From MAILER-DAEMON Fri Jan 29 13:13:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5YH6-0007JN-11 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 13:13:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5YH4-0007HT-KO for qemu-arm@nongnu.org; Fri, 29 Jan 2021 13:13:38 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41470) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5YGz-0007O3-2B for qemu-arm@nongnu.org; Fri, 29 Jan 2021 13:13:38 -0500 Received: by mail-wr1-x42f.google.com with SMTP id p15so9746854wrq.8 for ; Fri, 29 Jan 2021 10:13:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=zdmfvGuYJTDTydgoHUl776axD7+1d+L0GaH+C6UnN1Q=; b=mBJQ6nkTV0dcchXG5RWLxk3Vnrn6dvswGyIrEQm6o4VToE1XJ/OEpWd1yV/htOzZXm KRZAniTNx/NpckeLTK+sr2YOvAz7miq3TQmEqDyPYW6//zhREmlKmXh4zzZ3DmeN6c03 0mGM8kYWeCFYUT9rBuuOvLJHL3hf4o4y2V70hJlUazIN13rnwBeUYLbgfMeD5qKyGq59 c/yKDDeiRmflV4LwgDLLK9g7V2RIsnM2c/Nfg+EYTQ3wVuqCMBO8+tyqgAS79UEPr0cW INvzKft0aa8YSUdron7AptCM94771SHCumjuym+/KWSWLvpsW0evtQ9f0lUKDu3AxUHf 9RQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=zdmfvGuYJTDTydgoHUl776axD7+1d+L0GaH+C6UnN1Q=; b=B+RwCTynWUjMUWQ7U7TzU4JKUZGZocr8zbcQUHdbeJMtAmpVu0k4U/shWpVN7A+gId +CxMwRnGaQX1UvjkB9x5jhSen/vlXYlrX2bl1Xk9ZfQPy1zLKGMOdML6cgeGL/mcaM/+ zhbD5r/bpq5xgDx+t/w2Tg4GhK6yPFMmBNtLWenGYZtwLLKl7XR5jsppAIldgxShfZQR YVeWASQW7UJHqYQ5f6XaBMs/5gQQehvCwfjxGw1GzG6lV+1EBnmUfoZEtblT6TtNBC9h jvN6SOpLqsyPIi4zmPdhH7EHXY8JgXTzRhFoo1qNW7rK70dJ/6Dd7QTHo8oeAhSAIbgR KnWg== X-Gm-Message-State: AOAM5336qhAuSVP8yih5T3B1weBMBwF7j6wydxg2nZ6yQ7kD79BWWnM+ IjKnnagkF+A9Br2Vwui6wdz74g== X-Google-Smtp-Source: ABdhPJwNQxI2kVJBC9oJMsrfPu1dfceaZLpwCiFtHbM8ddkA0zQoaFXG561bvIr26FKXIQubbC0Dbw== X-Received: by 2002:adf:fd52:: with SMTP id h18mr5973311wrs.295.1611944008477; Fri, 29 Jan 2021 10:13:28 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m10sm12337769wro.7.2021.01.29.10.13.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 10:13:27 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CBCED1FF7E; Fri, 29 Jan 2021 18:13:26 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Anders Roxell , Aurelien Jarno , Peter Maydell Subject: [PATCH] docs/system: document an example booting the versatilepb machine Date: Fri, 29 Jan 2021 18:13:19 +0000 Message-Id: <20210129181319.2992-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 18:13:38 -0000 There is a bit more out there including Aurelien's excellent write up and older Debian images here: https://www.aurel32.net/info/debian_arm_qemu.php https://people.debian.org/~aurel32/qemu/armel/ However the web is transitory and git is forever so lets add something to the fine manual. Cc: Anders Roxell Cc: Aurelien Jarno Signed-off-by: Alex Bennée --- docs/system/arm/versatile.rst | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/docs/system/arm/versatile.rst b/docs/system/arm/versatile.rst index 51221c30a4..d16f20ccae 100644 --- a/docs/system/arm/versatile.rst +++ b/docs/system/arm/versatile.rst @@ -27,3 +27,35 @@ The Arm Versatile baseboard is emulated with the following devices: devices. - PL181 MultiMedia Card Interface with SD card. + +Booting a Linux kernel +---------------------- + +Building a current Linux kernel with ``versatile_defconfig`` should be +enough to get something running. + +.. code-block:: bash + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-linux-gnueabihf- + $ make versatile_defconfig + $ make + +You may want to enable some additional modules if you want to boot +something from the SCSI interface:: + + CONFIG_PCI=y + CONFIG_PCI_VERSATILE=y + CONFIG_SCSI=y + CONFIG_SCSI_SYM53C8XX_2=y + +You can then boot with a command line like: + +.. code-block:: bash + + $ qemu-system-arm -machine type=versatilepb \ + -serial mon:stdio \ + -drive if=scsi,driver=file,filename=debian-buster-armel-rootfs.ext4 \ + -kernel zImage \ + -dtb versatile-pb.dtb \ + -append "console=ttyAMA0 ro root=/dev/sda" -- 2.20.1 From MAILER-DAEMON Fri Jan 29 13:53:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5YtO-0007SA-3s for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 13:53:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5YtM-0007RT-FZ for qemu-arm@nongnu.org; Fri, 29 Jan 2021 13:53:12 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:56124) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l5YtJ-0007tv-4y for qemu-arm@nongnu.org; Fri, 29 Jan 2021 13:53:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1611946387; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v2lQG7NOq1Y30ihZ3JvjW7LHsEzNf1l5ZIU262Ux5yw=; b=c0PgIOjsr976CNPR89OESQ0xSsQ9hu4Lw3TcbFho97eBvzcNxipZGJzdi1cOaStyx7zRJ3 0YGYQjvlWUkJU4g2Ww88KsHp2txdbOWmDSs/aE+xXzKi2KvZeXZUnWhsyn8QfMbda/cD0T Y1phN9Ph0/y16LurcAA3uGkojVefAMg= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-148-Ax8__L49NlaFqj75TyNyEA-1; Fri, 29 Jan 2021 13:53:04 -0500 X-MC-Unique: Ax8__L49NlaFqj75TyNyEA-1 Received: by mail-wr1-f69.google.com with SMTP id n18so5734856wrm.8 for ; Fri, 29 Jan 2021 10:53:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=v2lQG7NOq1Y30ihZ3JvjW7LHsEzNf1l5ZIU262Ux5yw=; b=OBaCk+yzHHxrHrrggvIENea0lvXKebl/2YQYaWnXd9sKjZYbdTZWc2Y2a0dANAw8qS H5MNZOaf+h2TBFoyFEHPpIm7zrAlHxZQIG6i8vGxtTigQSqZt5/lQNcF1ggJLmuTJxjX OcW4W+RKratBxFE0EtkliJwXJ6YDKPn5W22GTfIe/SElOCLp2HpTHxZ1Sv/grevAgD46 Xlg18xWm7K41xtOd+UvmC1fzclFN1GPmAUKUJ39D1Sk2T4XQ+VQVXdo5r3w4YBuQZPaz B/RA3am59xYGzuLQOqdm7U3riiwwt8f+lPRulDJWqktYU/rCPIO/D1K0WekmeUivD7qz uDkQ== X-Gm-Message-State: AOAM533a9f8CAcuXXV/EFBmgbWmzid7+NHGTmGJTkf1SHZKs9Zzm69GW dyQ7gHjuTazjDFTL8qBCr2yMzANyo678QGbhjGD/gwnZKKIP6TiRtcEyHCqTcIMGoDbohAqta1G XZiuTSUqltbWD X-Received: by 2002:a1c:9609:: with SMTP id y9mr5027775wmd.75.1611946383045; Fri, 29 Jan 2021 10:53:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJyhbUhkw2usSXuyBhWcgXQlVTDKUdIPuIMDaI+Sf+8W+zkgRq8BrEHInJgZztI5WgVvi9yPgw== X-Received: by 2002:a1c:9609:: with SMTP id y9mr5027741wmd.75.1611946382729; Fri, 29 Jan 2021 10:53:02 -0800 (PST) Received: from [192.168.1.36] (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id 9sm3199432wra.80.2021.01.29.10.53.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Jan 2021 10:53:01 -0800 (PST) Subject: Re: [PATCH v4 09/12] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M To: Richard Henderson , qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= Cc: Thomas Huth , Fam Zheng , Peter Maydell , kvm@vger.kernel.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm@nongnu.org, Richard Henderson References: <20200929224355.1224017-1-philmd@redhat.com> <20200929224355.1224017-10-philmd@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 29 Jan 2021 19:53:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.249, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2021 18:53:12 -0000 On 10/3/20 11:48 AM, Richard Henderson wrote: > On 9/29/20 5:43 PM, Philippe Mathieu-Daudé wrote: >> +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) >> + >> arm_ss.add(zlib) >> >> arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) >> +arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) > > I'm a bit surprised about adding the file twice. > Since ARM_V7M depends on TCG, isn't the second line redundant? This does: if TCG if CONFIG_ARM_V7M files('m_helper.c') else #!V7M files('m_helper-stub.c')) endif else #!TCG files('m_helper-stub.c')) endif So: if !TCG or !V7M files('m_helper-stub.c')) else files('m_helper.c') endif There might be a better way to express that in Meson... I only understood how to do AND with arrays, but not OR. Paolo/Marc-André, is it possible? Thanks, Phil. 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id e4sm15520107wrw.96.2021.01.29.17.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 00/11] Support disabling TCG on ARM (part 2) Date: Sat, 30 Jan 2021 02:52:16 +0100 Message-Id: <20210130015227.4071332-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:38 -0000 Cover from Samuel Ortiz from (part 1) [1]:=0D =0D This patchset allows for building and running ARM targets with TCG=0D disabled. [...]=0D =0D The rationale behind this work comes from the NEMU project where we're=0D trying to only support x86 and ARM 64-bit architectures, without=0D including the TCG code base. We can only do so if we can build and run=0D ARM binaries with TCG disabled.=0D =0D v5:=0D - addressed Paolo/Richard/Thomas review comments from v4 [5].=0D =0D v4 almost 2 years later... [2]:=0D - Rebased on Meson=0D - Addressed Richard review comments=0D - Addressed Claudio review comments=0D =0D v3 almost 18 months later [3]:=0D - Rebased=0D - Addressed Thomas review comments=0D - Added Travis-CI job to keep building --disable-tcg on ARM=0D =0D v2 [4]:=0D - Addressed review comments from Richard and Thomas from v1 [1]=0D =0D Regards,=0D =0D Phil.=0D =0D [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html=0D [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html=0D [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html=0D [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html=0D [5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html=0D =0D Philippe Mathieu-Daud=C3=A9 (9):=0D exec: Restrict TCG specific headers=0D default-configs: Remove unnecessary SEMIHOSTING selection=0D target/arm: Restrict ARMv4 cpus to TCG accel=0D target/arm: Restrict ARMv5 cpus to TCG accel=0D target/arm: Restrict ARMv6 cpus to TCG accel=0D target/arm: Restrict ARMv7 R-profile cpus to TCG accel=0D target/arm: Restrict ARMv7 M-profile cpus to TCG accel=0D target/arm: Reorder meson.build rules=0D .travis.yml: Add a KVM-only Aarch64 job=0D =0D Samuel Ortiz (1):=0D target/arm: Do not build TCG objects when TCG is off=0D =0D Thomas Huth (1):=0D target/arm: Make m_helper.c optional via CONFIG_ARM_V7M=0D =0D default-configs/devices/aarch64-softmmu.mak | 1 -=0D default-configs/devices/arm-softmmu.mak | 28 --------=0D include/exec/helper-proto.h | 2 +=0D target/arm/cpu.h | 12 ----=0D hw/arm/realview.c | 7 +-=0D target/arm/cpu_tcg.c | 4 +-=0D target/arm/helper.c | 7 --=0D target/arm/m_helper-stub.c | 73 +++++++++++++++++++++=0D .travis.yml | 32 +++++++++=0D hw/arm/Kconfig | 66 +++++++++++++++++--=0D target/arm/meson.build | 28 +++++---=0D 11 files changed, 196 insertions(+), 64 deletions(-)=0D create mode 100644 target/arm/m_helper-stub.c=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Fri Jan 29 20:52:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRM-0006gC-Vt for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:52:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRH-0006ei-JL; Fri, 29 Jan 2021 20:52:40 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:37546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRG-0008Sq-5z; Fri, 29 Jan 2021 20:52:39 -0500 Received: by mail-wr1-x430.google.com with SMTP id v15so10648515wrx.4; Fri, 29 Jan 2021 17:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TWOO2zfu8P4UM754zwKeQRqNcelSJ+Vi3BwaB87IrgI=; b=EZ4R0A6K45GJEpt3ikVxK/mZ5uOp/qSvLKwjO7LS5PbjeX+3sWdmNlr+4p56lnPtqL CUdY1yW1rTe7NWAKG6FtSRNNZKnZUAI2VEHfT9t/GySrE8ds9BQbysvGJYiW2faVZNpm DGZ+2ZzDYpOjHkDu0jST31KidNc+L9/fohOoZJZMRjKENmO2boj+1Bne8nOdoKsZZOk2 hms4LiJZ9snctfQC29BzW0EhHYsmNCX7dzY+CxfZJyC29i8WBBxcI2hmd0NS7su5sU/F vCixTZjkQ3F8hOmBQQBzuo5d3mfiya1x/ZzCDk9XbkWe7CW7UiXUFmxJzINuRhOtpEh6 vHGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TWOO2zfu8P4UM754zwKeQRqNcelSJ+Vi3BwaB87IrgI=; b=jEywqhePV6AGM6PdtMPBs30MAn3rm1DrX0P+UiHZjTE2mRZoUETUsYXuKmDnJ+Tl/C QJ9pI89QRXduM5LPoEjM/WXzYN8UGqB5FuxkmWfCnaD8426nIne39rTSmMFFHUjIxs8N pqWqJan+Qc5mxHcWHGrMKyRT74mXBnPTIDVZWlW53M8tRAQijdRJuJnHgePyaoeHZlDU zwM7++Mhuvph2OhaVFdfFoRMmijI2Sk4Q4KjJC8i3C/Niuj9Uy2euFlCjNMtmiYtocJQ eAsPwzAJeu5kDx5AzNzPXsvsjr+jKLGHo+rbRMw004SllpEfsXLhwCK4ncj1prrEqgw5 nGwg== X-Gm-Message-State: AOAM530K47B2pG4JUILlLSV1SAG/pC9F/8GlGZyA+8HbSnmf4MyhVC9F mumEeoyWPc9Ml3yhgaZookWeFC8Etbs= X-Google-Smtp-Source: ABdhPJwm3L7bSc0x4zKW4ljahz5/V9fkUWnJDpwudDy2IcbG2e/6dOTMtKI7Na8SK+4UY4kLg/lEbg== X-Received: by 2002:adf:e4c9:: with SMTP id v9mr7191301wrm.277.1611971555621; Fri, 29 Jan 2021 17:52:35 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u14sm11707719wml.19.2021.01.29.17.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 01/11] exec: Restrict TCG specific headers Date: Sat, 30 Jan 2021 02:52:17 +0100 Message-Id: <20210130015227.4071332-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:42 -0000 Fixes when building with --disable-tcg: In file included from target/arm/helper.c:16: include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory 42 | #include "tcg-runtime.h" | ^~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé --- include/exec/helper-proto.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 659f9298e8f..740bff3bb4d 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ #include "helper.h" #include "trace/generated-helpers.h" +#ifdef CONFIG_TCG #include "tcg-runtime.h" #include "plugin-helpers.h" +#endif /* CONFIG_TCG */ #undef IN_HELPER_PROTO -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:52:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRO-0006iV-O7 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:52:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRM-0006g0-CJ; Fri, 29 Jan 2021 20:52:44 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39535) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRK-0008Us-Op; Fri, 29 Jan 2021 20:52:43 -0500 Received: by mail-wm1-x32d.google.com with SMTP id u14so8523868wmq.4; Fri, 29 Jan 2021 17:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G9dNmRIohMTgXAElzkQ+lpMLRmxhHG61au1rY6dJdIw=; b=PEjpazXUgk6kR6UqDmwU45UySoXQLcz5AUjh6P8ScUgFkBsPisn+Tm/qm9hBMUWlxU bXEcLJ8UugY9aEVPQbo6p4m/Hux6j9xRlGgX4nFBl3CdGdq2BBIrSjLEO86Z4aoFc8pO sOUDNxqSQ0sq11WskYH43JUY8ipQhlYj/w/bYvz/VXaBRpbw+O5FYEX3aiwba24dV37x eXoZz8Ukp5kBBqvvXXbiR7M0vIrCWLxvkVDzdRwwembHyYCl3SSmuG6HSoiE25+STMef fVEoHq1XKPD0QMR5koqBX/Yf7PEsrpn+QnhlP/GxxXqA9IDdom/mYPcwNcgu4Y2ATxaQ whbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=G9dNmRIohMTgXAElzkQ+lpMLRmxhHG61au1rY6dJdIw=; b=KbV4sAiA36R4qUDTgcCl/qrBAkfis1jFNh/rcAMjxgSB2nH1ReOVRal3BJ484zuABf rW3KYIbOO67KIdGxADr7lmms6QrAAdUbvXk79rx1mKxHZ4VcwyJhvF+drk/N0nz/Ad4N MXP0IUT4rghtoeQq7IoLGI82aHWwlNPSHB2AOsP0I0GD8TirX95MbMPnamf7dGqGknR+ 4T4s4FSvPc2GjGhgquqoF/dNjvGbHF54ftWtGYbolEXTZbzY682rHeLbMqpJ/pLTwy3M ys5xBhld1WMOIDVNdU/bfD+Z1Y6xGclyA7hGbkKCrwk6VWc9eelkbgR9al976KBM0Ah2 tJVw== X-Gm-Message-State: AOAM530yW2rUUON9tCFsHw9uuCqAMcQjKL+sTrCxgrki/kgCZwwRXfwv 7dGvS2q8GhEEpNj8TdkiFWCDwrBN9M4= X-Google-Smtp-Source: ABdhPJwskto+f53o9TCaynYuVK8iQ1uBoTdTN+CKWcrz2acq5nnSN55h/BCj1DXRiUJLZD6Cr+Hp6Q== X-Received: by 2002:a1c:21c6:: with SMTP id h189mr5786718wmh.173.1611971560647; Fri, 29 Jan 2021 17:52:40 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id w126sm12485133wma.43.2021.01.29.17.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/11] default-configs: Remove unnecessary SEMIHOSTING selection Date: Sat, 30 Jan 2021 02:52:18 +0100 Message-Id: <20210130015227.4071332-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:45 -0000 Commit 56b5170c87e ("semihosting: Move ARM semihosting code to shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which already selects SEMIHOSTING. No need to select it again. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 1 - 1 file changed, 1 deletion(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0500156a0c7..341d439de6f 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -41,6 +41,5 @@ CONFIG_MICROBIT=y CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y -CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:52:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRT-0006mX-7X for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:52:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40458) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRR-0006kF-4L; Fri, 29 Jan 2021 20:52:49 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:36445) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRP-00004w-Lz; Fri, 29 Jan 2021 20:52:48 -0500 Received: by mail-wm1-x332.google.com with SMTP id i9so8542671wmq.1; Fri, 29 Jan 2021 17:52:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vcCVSF3XdYkCqqZi7utKwViQKx4YjOvtKjolDPxsZVA=; b=uuOQE2bVc/AXhQEPhQ6gdsToWOMtR7/LcnPqZ5MlFP7kxA9NkXZRlPLIuIGcDAICaH ssfdEX74NQKHWvbMKF1O0arKgDrgBDsd8FqdoI/5wNZzzclE5eRj9Kpm6bGoGr5+cZdI Jg5zG6cmCMmNVfGLW3zUisi7sd7SUqp60e7Hpum16Q1olADlzRwBFv2K8f8X18j8D47y 58iyx4+nB5prF66v4obJKkL3bwkP1u0ZTkyuBYVj1LfX8505z2oyoDPPp1zNI+EnKisD o5O/sJHYTlK/TxPX7i+7nbbtSy/f7B6U9/cTk8WL2l7kXtk/9VzZhNismcBX99UrM8es TVZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vcCVSF3XdYkCqqZi7utKwViQKx4YjOvtKjolDPxsZVA=; b=Zg3uu+5myc/fzr0l3DUaSSXqKCmUpKOo/SP0fSmKqERsvAokR6t5n/4MMMy5SbdifA cBLAXANY9/GW22eV9kjO7ONITjfUx7jQbTTF0aPIgFfpKob7PLDDBSGW8dqxG75kH2ia lQAX6Hx4CT1XjRfvSsUEtT8CXX0cPvhiKny+BzX6onie081N4tKNA6S6KDQcdOuGHJiQ NZeTUVnxJxFHSOmS/HnXKVrw+OHyGlfzxxEp41y2tfzszStST+2HGGoTKRXcEgWHnhex o9udw+/RJSp/S4RNUrOQr/lziCLtWjW5NXXwi27lQ+LrJIzT+8+Tb5TrNV/Ruds2xUl/ F9aA== X-Gm-Message-State: AOAM532GiD3YO8F5SOqLUV6d5VnVcqTmNX3bGqziazM2O8gNlVZWJ/r/ efQC7yGq4kCVJT8IzAAEytdYPbpKuXI= X-Google-Smtp-Source: ABdhPJxjjNgvntexhnAMkjHR5dHZDBe4a6Ehpw1OZ8B2xG9qLvuQMF7WDg1InhxkhCshzCAD0AspzA== X-Received: by 2002:a05:600c:154f:: with SMTP id f15mr6167686wmg.46.1611971565884; Fri, 29 Jan 2021 17:52:45 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id b4sm15215041wrn.12.2021.01.29.17.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:19 +0100 Message-Id: <20210130015227.4071332-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:50 -0000 KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv4 CPUs when TCG is available: - StrongARM (SA1100/1110) - OMAP1510 (TI925T) The following machines are no more built when TCG is disabled: - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310) - sx1 Siemens SX1 (OMAP310) V2 - sx1-v1 Siemens SX1 (OMAP310) V1 Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/Kconfig | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 341d439de6f..8a53e637d23 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y CONFIG_MUSICPAL=y CONFIG_MUSCA=y -CONFIG_CHEETAH=y -CONFIG_SX1=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 223016bb4e8..7126d82f6ce 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,3 +1,7 @@ +config ARM_V4 + bool + depends on TCG + config ARM_VIRT bool imply PCI_DEVICES @@ -31,6 +35,8 @@ config ARM_VIRT config CHEETAH bool + default y if TCG + select ARM_V4 select OMAP select TSC210X @@ -249,6 +255,8 @@ config COLLIE config SX1 bool + default y if TCG + select ARM_V4 select OMAP config VERSATILE -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:52:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRY-00070b-CT for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:52:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRW-0006vo-JF; Fri, 29 Jan 2021 20:52:54 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40432) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRU-000065-On; Fri, 29 Jan 2021 20:52:54 -0500 Received: by mail-wr1-x436.google.com with SMTP id c12so10628072wrc.7; Fri, 29 Jan 2021 17:52:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AIZXZm6d3zsn85EInNhmu0X2HUAdFADt4XuIzrFLo50=; b=JK8OynKD3b/XAd5IOwUaUSZL3h4xFiIGScxh9ajv5/hQv6fFGA3IGW1/DMnBKeMEQR V3Z7hOTVfKN2RLjfn4xgBUhXwjsLFgcrhcbIDR6RRYnAQMbIE9Gz5RCA+F1/TMWz9cOZ Bwv00xaAhqk7mModnA5Lr6pCL3wGAAp126InW50Cd6hGDw/HEENn2Ja7C5ZTrj+jcLSI XTaaejU/NLcaGoCMIASY8BEf1xCRMqDHecP5kpRE7Zp17pL/Fqg0glrRaOUtPbIeKTmT NbY3B3Q9Xqy+/KmZdi0fxeVK2x9/V/vK39DNKtK2hKk7ke3Hdy3d+Q/MJ3HipcXuDAG0 Q4zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AIZXZm6d3zsn85EInNhmu0X2HUAdFADt4XuIzrFLo50=; b=K8OuxNI47r+U4ddnn2/WBHFdPn9clgEun6foek3ahz3IKFpPHDBz86WWQAW9sleNVC XR9Q2zgEHQPmvsJe0P3S3+ML55u+/wTmRVgApboMYorIWW0e2F2lpWiS/HAunhijJit3 JJ49AjbBmKX94IMb/PEA1ppZcGZjbq0OaHUA2258KR6ct8sRCsbj46Hdqp2wrAxkD1ik xTJ8Fhn59CP/seveklt6ttZyw7Xlf+iUJlX+OjZ6eTXAtmKCxHiyiqgUZiMzvFJi7v5G qySrBFC3U6m/+cMQcnWK8dvtxEefbWLTDNQ85yxkz08hf9Wsf5GFZe6o3G0gjZL7Ij1N XfIw== X-Gm-Message-State: AOAM532q8/LoYLBc/n5pt07GoWQVJI+o7lymtRMt9AmWrjNlNbVlw8VM ZAkxOxqgC1J9alBUQS1pbbCZbQy+SME= X-Google-Smtp-Source: ABdhPJyG3IfNKn92dIJ/BqxY8b6yA8upkz3X+oX15/dbRXoTtTOXkskldv0xqkOnW90v7URAiwFqRw== X-Received: by 2002:a5d:40c5:: with SMTP id b5mr7441592wrq.121.1611971570862; Fri, 29 Jan 2021 17:52:50 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u6sm15859725wro.75.2021.01.29.17.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 04/11] target/arm: Restrict ARMv5 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:20 +0100 Message-Id: <20210130015227.4071332-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:55 -0000 KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv5 CPUs when TCG is available: - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) The following machines are no more built when TCG is disabled: - akita Sharp SL-C1000 (Akita) PDA (PXA270) - ast2500-evb Aspeed AST2500 EVB (ARM1176) - ast2600-evb Aspeed AST2600 EVB (Cortex A7) - borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270) - canon-a1100 Canon PowerShot A1100 IS - collie Sharp SL-5500 (Collie) PDA (SA-1110) - connex Gumstix Connex (PXA255) - g220a-bmc Bytedance G220A BMC (ARM1176) - imx25-pdk ARM i.MX25 PDK board (ARM926) - integratorcp ARM Integrator/CP (ARM926EJ-S) - mainstone Mainstone II (PXA27x) - musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S) - palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S) - realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S) - romulus-bmc OpenPOWER Romulus BMC (ARM1176) - sonorapass-bmc OCP SonoraPass BMC (ARM1176) - spitz Sharp SL-C3000 (Spitz) PDA (PXA270) - supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S) - swift-bmc OpenPOWER Swift BMC (ARM1176) - tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7) - terrier Sharp SL-C3200 (Terrier) PDA (PXA270) - tosa Sharp SL-6000 (Tosa) PDA (PXA255) - verdex Gumstix Verdex (PXA270) - versatileab ARM Versatile/AB (ARM926EJ-S) - versatilepb ARM Versatile/PB (ARM926EJ-S) - witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176) - z2 Zipit Z2 (PXA27x) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 12 ------------ hw/arm/realview.c | 5 ++++- hw/arm/Kconfig | 23 +++++++++++++++++++++++ 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 8a53e637d23..5b25fafc9ab 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y -CONFIG_MUSICPAL=y CONFIG_MUSCA=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y -CONFIG_VERSATILE=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y -CONFIG_MAINSTONE=y -CONFIG_GUMSTIX=y -CONFIG_SPITZ=y -CONFIG_TOSA=y -CONFIG_Z2=y CONFIG_NPCM7XX=y -CONFIG_COLLIE=y -CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y -CONFIG_DIGIC=y CONFIG_SABRELITE=y CONFIG_EMCRAFT_SF2=y CONFIG_MICROBIT=y -CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 0831159d158..cd37b501287 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -18,6 +18,7 @@ #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" #include "exec/address-spaces.h" @@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = { static void realview_machine_init(void) { - type_register_static(&realview_eb_type); + if (tcg_enabled()) { + type_register_static(&realview_eb_type); + } type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7126d82f6ce..bdb8c63af7b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -2,6 +2,10 @@ config ARM_V4 bool depends on TCG +config ARM_V5 + bool + depends on TCG + config ARM_VIRT bool imply PCI_DEVICES @@ -46,6 +50,8 @@ config CUBIEBOARD config DIGIC bool + default y if TCG + select ARM_V5 select PTIMER select PFLASH_CFI02 @@ -76,6 +82,8 @@ config HIGHBANK config INTEGRATOR bool + default y if TCG + select ARM_V5 select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -88,6 +96,7 @@ config INTEGRATOR config MAINSTONE bool + default y if TCG select PXA2XX select PFLASH_CFI01 select SMC91C111 @@ -102,6 +111,8 @@ config MUSCA config MUSICPAL bool + default y if TCG + select ARM_V5 select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -142,6 +153,7 @@ config OMAP config PXA2XX bool + select ARM_V5 select FRAMEBUFFER select I2C select SERIAL @@ -151,12 +163,14 @@ config PXA2XX config GUMSTIX bool + default y if TCG select PFLASH_CFI01 select SMC91C111 select PXA2XX config TOSA bool + default y if TCG select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -164,6 +178,7 @@ config TOSA config SPITZ bool + default y if TCG select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -176,6 +191,7 @@ config SPITZ config Z2 bool + default y if TCG select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -249,6 +265,7 @@ config STRONGARM config COLLIE bool + default y if TCG select PFLASH_CFI01 select ZAURUS # scoop select STRONGARM @@ -261,6 +278,8 @@ config SX1 config VERSATILE bool + default y if TCG + select ARM_V5 select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -382,6 +401,8 @@ config NPCM7XX config FSL_IMX25 bool + default y if TCG + select ARM_V5 select IMX select IMX_FEC select IMX_I2C @@ -408,6 +429,8 @@ config FSL_IMX6 config ASPEED_SOC bool + default y if TCG + select ARM_V5 select DS1338 select FTGMAC100 select I2C -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRc-0007Bb-LM for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id g12sm11835695wmh.14.2021.01.29.17.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 05/11] target/arm: Restrict ARMv6 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:21 +0100 Message-Id: <20210130015227.4071332-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:52:59 -0000 KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv6 CPUs when TCG is available: - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 The following machines are no more built when TCG is disabled: - kzm ARM KZM Emulation Baseboard (ARM1136) - microbit BBC micro:bit (Cortex-M0) - n800 Nokia N800 tablet aka. RX-34 (OMAP2420) - n810 Nokia N810 tablet aka. RX-44 (OMAP2420) - realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/realview.c | 2 +- hw/arm/Kconfig | 11 +++++++++++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 5b25fafc9ab..ee80bf15150 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_FSL_IMX31=y CONFIG_MUSCA=y -CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index cd37b501287..57a37608e39 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -463,8 +463,8 @@ static void realview_machine_init(void) { if (tcg_enabled()) { type_register_static(&realview_eb_type); + type_register_static(&realview_eb_mpcore_type); } - type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index bdb8c63af7b..daab7081994 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -6,6 +6,11 @@ config ARM_V5 bool depends on TCG +config ARM_V6 + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + config ARM_VIRT bool imply PCI_DEVICES @@ -131,6 +136,8 @@ config NETDUINOPLUS2 config NSERIES bool + default y if TCG + select ARM_V6 select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -411,6 +418,8 @@ config FSL_IMX25 config FSL_IMX31 bool + default y if TCG + select ARM_V6 select SERIAL select IMX select IMX_I2C @@ -488,11 +497,13 @@ config FSL_IMX6UL config MICROBIT bool + default y if TCG select NRF51_SOC config NRF51_SOC bool select I2C + select ARM_V6 select ARM_V7M select UNIMP -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRh-0007Ne-Pg for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:53:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRg-0007Kv-Mj; Fri, 29 Jan 2021 20:53:04 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:33486) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRf-0000AC-8V; Fri, 29 Jan 2021 20:53:04 -0500 Received: by mail-wm1-x331.google.com with SMTP id s24so7991082wmj.0; Fri, 29 Jan 2021 17:53:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g1KU5IE9TGCZM/lU61E2LYHQF94GVZ2sjp5LehjcIJU=; b=mFXWLnEV2J7F5vMWemzgA7H5rDlvI6++w0fS0CrZkpYvnv+K+N3XgEO3GKqwwuaANV d0g2d43AkRHBIhnX13fL4uJHnEss03yuMlReAv0aU0IicAz94GcfWh5K7Snxt8N8VR2K m2+R3VOFvTNVyzdmxAUUMMumOrI7WSHzLPeDPs3BE1Awvg7fhIjOEoY+KbEEZ3F+6VdF 6FPqa4w4nqQkxvEZACD/7lmP+n2g0PSuWwn57rp18al9fjHH4i5rs8wkEYgX4/S1vteX co1K1JfSZCh937LeyFh7KfxD9XXT2OfA3b5Ooc/YPg83R/j8K/T+OOmAzvb9jg4OXvX5 t53g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=g1KU5IE9TGCZM/lU61E2LYHQF94GVZ2sjp5LehjcIJU=; b=pb+d6dAfGTL3/VtdGAtlkQpuOQI3CpyPIJbM35DDlrlwuKXKBLYVHIj+t89oRQCjoy cenJ7wCcXGD2z+Wkn24Fkc/u1Kof2A1k9SLzhpMqRwoQw4hGS49GT2mrn1yPpzGVzAna QJKdutcoJco4djgR1hzQv6WvjPeMyyilPKQSYkq4dQnA7uT6lSzt7+mVKTCDGkiMd9p9 GUnD6E8elYeuDdrTyL4cwSxF8Ac/cQrnokhFbJuNOJiSjRXoo0w2XxM/mdsaKH1n8NyS iV7iALg7V4c0hIm0tDrme0enwsYl4i9r4jIo+qSjWX6t/nRNUQRbTFi3Z5kkXubRvtEg 9mHg== X-Gm-Message-State: AOAM530tFvBiK5P4W6e/mDLUROWj8XyZq1XLaMHDQOKExHOEO35xqn1Q xCAFkSPNDkqZgHwqkD+lv3pDXWNMs48= X-Google-Smtp-Source: ABdhPJyA4Coz/8piVvaPk4EIcoOTmtcPznXjAqGGyUN4FELubBKdNdl58zv0jN7k1O/K2eCj4Luk0Q== X-Received: by 2002:a1c:b78b:: with SMTP id h133mr6103963wmf.151.1611971581368; Fri, 29 Jan 2021 17:53:01 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id w25sm12591514wmc.42.2021.01.29.17.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:22 +0100 Message-Id: <20210130015227.4071332-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:05 -0000 A KVM-only build won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F The following machine is no more built when TCG is disabled: - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/aarch64-softmmu.mak | 1 - hw/arm/Kconfig | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak index 958b1e08e40..a4202f56817 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -CONFIG_XLNX_ZYNQMP_ARM=y CONFIG_XLNX_VERSAL=y CONFIG_SBSA_REF=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index daab7081994..320428bf97e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -11,6 +11,11 @@ config ARM_V6 depends on TCG select ARM_COMPATIBLE_SEMIHOSTING +config ARM_V7R + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + config ARM_VIRT bool imply PCI_DEVICES @@ -377,8 +382,10 @@ config STM32F405_SOC config XLNX_ZYNQMP_ARM bool + default y if TCG select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRo-0007b3-3q for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:53:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRm-0007XQ-3C; Fri, 29 Jan 2021 20:53:10 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:41279) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRk-0000BI-DA; Fri, 29 Jan 2021 20:53:09 -0500 Received: by mail-wr1-x435.google.com with SMTP id p15so10596827wrq.8; Fri, 29 Jan 2021 17:53:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pL3VFUfes4LLPpgaJDy8jU3gYau+sjFrKic4/sFvnNY=; b=QlPx5vk/bo8ydtxxW9jNTxI4BE08Ejo8IlC/WMnhi4Wbme1fYmhJgyU1Upki/92NmF WC2DbHcdeOoGbbqkX3uzvTl8MPRzbcKjiR9DkW3t+gelrCpi6lbR+YljJPOX4B/pNnJR jLROfdsvWr2JLoQ3ukaZTPfmPpHIQ2tX5RT3QafM9bvIGcGYCZ4JbSGyIOolFM9zj2wp 8Lk2wKKiOifSwg1YsFs8CXFAh+ZPmwh7tkYJaYlPsNhSagHtmcD7TetDYtI5mpUQKEuJ UxtEsewFWr9ZiT2uXhIw/Szt607GBXaZ6aLcK0stqf2PdjzbROXSDKfZ0OHCM4ASM64Z ZiGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pL3VFUfes4LLPpgaJDy8jU3gYau+sjFrKic4/sFvnNY=; b=T7tCExzc7iRBpgtgk84CC1LQYPFWK98tfOfZWgG7T/+z2fJPrh8dE0rnlbC3LhHpD6 5UqXqrAM+GH1SekRi4j/sQ78YZYg4df+HMEvm/CFTt7riKnj4uvIalieip/xqbJO94Ju tslq5qovj4lu84uyk4GZXp4cmiMaH7Y9NRqXe6bzwxaJgpzKkvjuhBjIs1YWed35pi0O EJ9LWrFLneb/YhJtapJMZEUAh3JqbVtDCu/IdCCp8GTZxoXph4O9vvvkJZvTLIBvQvFf X7BKchmMbWTVPHsy2W7qDtCWNG7ycfe81EZjlqV1ctiOSeffV8bGOR28SgSKA49BoYw4 Q6OQ== X-Gm-Message-State: AOAM530q4mXLrTbq9pCZLA4RbuQVAXwUbwTRgPmw3MVcVJny+8X1Y0YU wc+weECV1/sFRIvtilfpxTcEY/q/h3M= X-Google-Smtp-Source: ABdhPJwbM5w0TDBpvxYm44nUc4AYAH45EnulcrjfYKeG5PWB96HJ5mDacgEs5qWvrmDx0pRxmhlO2w== X-Received: by 2002:adf:a31d:: with SMTP id c29mr7307582wrb.306.1611971586564; Fri, 29 Jan 2021 17:53:06 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id f13sm8277528wmf.1.2021.01.29.17.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:23 +0100 Message-Id: <20210130015227.4071332-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:10 -0000 A KVM-only build won't be able to run M-profile cpus. Only enable the following ARMv7 M-Profile CPUs when TCG is available: - Cortex-M0 - Cortex-M3 - Cortex-M4 - Cortex-M33 The following machines are no more built when TCG is disabled: - emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010) - highbank Calxeda Highbank (ECX-1000) - lm3s6965evb Stellaris LM3S6965EVB - lm3s811evb Stellaris LM3S811EVB - midway Calxeda Midway (ECX-2000) - mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3 - mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4 - mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7 - mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33 - mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3 - mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33 - musca-a ARM Musca-A board (dual Cortex-M33) - musca-b1 ARM Musca-B1 board (dual Cortex-M33) - netduino2 Netduino 2 Machine - netduinoplus2 Netduino Plus 2 Machine We don't need to enforce CONFIG_ARM_V7M in default-configs anymore. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 11 ----------- hw/arm/Kconfig | 17 +++++++++++++---- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index ee80bf15150..b72926b8fce 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -1,28 +1,17 @@ # Default configuration for arm-softmmu -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=y - # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y -CONFIG_HIGHBANK=y -CONFIG_MUSCA=y -CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y CONFIG_NPCM7XX=y -CONFIG_NETDUINO2=y -CONFIG_NETDUINOPLUS2=y -CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_SABRELITE=y -CONFIG_EMCRAFT_SF2=y -CONFIG_MICROBIT=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 320428bf97e..f56c05c00a8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -16,6 +16,12 @@ config ARM_V7R depends on TCG select ARM_COMPATIBLE_SEMIHOSTING +config ARM_V7M + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + select PTIMER + config ARM_VIRT bool imply PCI_DEVICES @@ -78,6 +84,7 @@ config EXYNOS4 config HIGHBANK bool + default y if TCG select A9MPCORE select A15MPCORE select AHCI @@ -113,6 +120,7 @@ config MAINSTONE config MUSCA bool + default y if TCG select ARMSSE select PL011 select PL031 @@ -133,10 +141,12 @@ config MUSICPAL config NETDUINO2 bool + default y if TCG select STM32F205_SOC config NETDUINOPLUS2 bool + default y if TCG select STM32F405_SOC config NSERIES @@ -258,6 +268,7 @@ config SABRELITE config STELLARIS bool + default y if TCG select ARM_V7M select CMSDK_APB_WATCHDOG select I2C @@ -331,10 +342,6 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG -config ARM_V7M - bool - select PTIMER - config ALLWINNER_A10 bool select AHCI @@ -463,6 +470,7 @@ config ASPEED_SOC config MPS2 bool + default y if TCG select ARMSSE select LAN9118 select MPS2_FPGAIO @@ -516,6 +524,7 @@ config NRF51_SOC config EMCRAFT_SF2 bool + default y if TCG select MSF2 select SSI_M25P80 -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRs-0007iR-Gl for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:53:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fRr-0007g5-7D; Fri, 29 Jan 2021 20:53:15 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:32826) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fRp-0000DU-Gu; Fri, 29 Jan 2021 20:53:14 -0500 Received: by mail-wr1-x42e.google.com with SMTP id 7so10651866wrz.0; Fri, 29 Jan 2021 17:53:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aLdl19C96C3GXRdvC9mwI7cbyJbYzl+Xi4/pdqV71I=; b=qxXJ6NS7gc+UGhx5DFTb2Xpax6DoUp1XDT6myxKlLWhft2T2JpgY0t/GcrbkAPA74S BYKzJUMJSUVzfGy8ahib79MmmFBxyR4C51gAaIk+IKe1ruKX31rhr/sQZfQIyKw5wrU/ 1hK3oMV0KFDk+pOoGsgAUL+Hzg3rp9RQLtbIAqNNQSgjushYDTMLUHnbKDGjBim56g9o NTH4trP5zRt4Djgg0ZMAiE0OskvRk8sUWZA13bfYoWDLJzMlRkxdTNC6X0pPEQosKjFj ZGk1FnxF2wKo59dWkyxHUJ3YCi/wdcYYO+prik3UxDZMOGyh0yuE3NsD7O32wT0hwbKE 1BUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9aLdl19C96C3GXRdvC9mwI7cbyJbYzl+Xi4/pdqV71I=; b=jJsb9knr8yS8ItuvSwxsC+NgU6RbAIyiz0Uu+TobB8q5MMwhTVWzbaZOhJ8oUZNag4 4WHZmMsB7OTasxnht/MBemZpwNmW/ZMVXK94xVbouU75pQzUqVu9SiFF3pbe2MmSxqUd hfWl7IEJ6xW6VnIAo3TZL7SMt7EVK95nTFMpwrOmbJRFM1q3RyLqRVVoga82hNElZqqL ILbhuJWJJvGrd8DGBr8QskgoyrFkYBkVAmbA8guWhzRjNJz/hc/eJqPD+IjqS9WNyWWj Ob0zPRq3S6YnryjRJcoJQ0FGuJvPJxmw8vAzoMGL3U83SW8cocGdadfCRtzOpDvyLDKc EuPA== X-Gm-Message-State: AOAM530X7A8QlwTwU5g22NbJS+agG2xltxVzI2d7JKOHBQvYwZcpl6GQ 9PYrhrKTKOhmG0C23V3XVUO1RNjlbHs= X-Google-Smtp-Source: ABdhPJzhiN23pGf2VqmdiIvY6PxgrMl9QORmviZzT3M+r/7egpP7DCxDAaxeN5Yt/ZE6GzZQSHs8ew== X-Received: by 2002:a5d:5051:: with SMTP id h17mr7627630wrt.164.1611971591652; Fri, 29 Jan 2021 17:53:11 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id c18sm20017355wmk.0.2021.01.29.17.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Date: Sat, 30 Jan 2021 02:52:24 +0100 Message-Id: <20210130015227.4071332-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:15 -0000 From: Thomas Huth We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth Message-Id: <20190903154810.27365-4-thuth@redhat.com> [PMD: Keep m_helper-stub.c but extend it, rewrite the rest] Signed-off-by: Philippe Mathieu-Daudé --- Rewrite since v3, therefore removed Richard R-b tag. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 12 ------- target/arm/cpu_tcg.c | 4 ++- target/arm/helper.c | 7 ---- target/arm/m_helper-stub.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 4 ++- 5 files changed, 79 insertions(+), 21 deletions(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c..0bd0e51e498 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY bool armv7m_nvic_can_take_pending_exception(void *opaque); -#else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) -{ - return true; -} -#endif /** * armv7m_nvic_set_pending: mark the specified exception as pending * @opaque: the NVIC @@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque); * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ -#ifndef CONFIG_USER_ONLY bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) -{ - return false; -} #endif /* Interface for defining coprocessor registers. diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 98544db2df3..3e1c9b40353 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifndef CONFIG_USER_ONLY static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return ret; } +#endif /* CONFIG_USER_ONLY */ static void arm926_initfn(Object *obj) { @@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt; + cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; #endif - cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; cc->gdb_core_xml_file = "arm-m-profile.xml"; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e64..fe3d0291f9c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } -#ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - g_assert_not_reached(); -} -#endif - ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 00000000000..6d751424e86 --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,73 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + g_assert_not_reached(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + g_assert_not_reached(); +} + +#ifndef CONFIG_USER_ONLY + +bool armv7m_nvic_can_take_pending_exception(void *opaque) +{ + g_assert_not_reached(); +} + +void arm_v7m_cpu_do_interrupt(CPUState *cs) +{ + g_assert_not_reached(); +} + +#endif /* CONFIG_USER_ONLY */ diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c1010..6c6081966cd 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -21,7 +21,6 @@ 'gdbstub.c', 'helper.c', 'iwmmxt_helper.c', - 'm_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', @@ -32,6 +31,9 @@ )) arm_ss.add(zlib) +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) + arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fRy-0007xL-6s for mharc-qemu-arm@gnu.org; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id p18sm10429022wrx.84.2021.01.29.17.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org Subject: [PATCH v5 09/11] target/arm: Reorder meson.build rules Date: Sat, 30 Jan 2021 02:52:25 +0100 Message-Id: <20210130015227.4071332-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:20 -0000 From: Philippe Mathieu-Daudé Reorder the rules to make this file easier to modify. No logical change introduced in this commit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6c6081966cd..aac9a383a61 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,31 +14,36 @@ arm_ss = ss.source_set() arm_ss.add(gen) +arm_ss.add(zlib) arm_ss.add(files( 'cpu.c', - 'crypto_helper.c', - 'debug_helper.c', 'gdbstub.c', 'helper.c', + 'vfp_helper.c', +)) + +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c', +)) + +arm_ss.add(files( + 'crypto_helper.c', + 'debug_helper.c', 'iwmmxt_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', 'translate.c', 'vec_helper.c', - 'vfp_helper.c', 'cpu_tcg.c', )) -arm_ss.add(zlib) - arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fSD-00082B-UO for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:53:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fS1-00080Q-FM; Fri, 29 Jan 2021 20:53:27 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:37388) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fS0-0000GN-0p; Fri, 29 Jan 2021 20:53:25 -0500 Received: by mail-wm1-x331.google.com with SMTP id m1so5253867wml.2; Fri, 29 Jan 2021 17:53:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=S8gP7rmCHgjQ7YTM/ADW7lbRknMIzFi/kvGjnDTBiXVwxuHAweAduqVLnoWGJLI2Ik JfdEKMmuSM3Uo8wpGPc7O5efkIfwempgLB5LYyAxcpbOduzxSzOy25mGYctn0157CNuf zV0ZhHXDZP2UT03nYTizMXR4Vs40tQPbvbnOmuxLCvtPCrY0PMsdGMwTdM2ArhKkBchH TWyvRrzcqLAWdaanShYSz+sOqcrd7NvfsPGFpWW+5oIunY8vE5ZXCX2iLvPjoaAaSoPR DrMJQdIPKVgaAINimQlPBxGcMGIfkres1tY3aYap3kkTCgMibqAulTso5blHDtdlfoUu cwiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=Ca5/CC1lJtVxGo0MmmRz/WHaYmzBiMzk4p+P0GVBfWir0RSp3JHvszRMM3p9IID1Pw 1qz1EGsP5Hyhq7YsMUsSePeO6TyP0ukuH2kB0D3PLqiJbLRCScsZAuGmNPAY+7B9vDgW FwyxOojLIQ6aeqkeJVIYAz3QnsxnjD8T/096CyvJEP4JvNDnUMKCTXxidEI+7Dwr+5Hp wI/9eL/ci/PJHQYW7thD6cC1fpHNWa3nRgwIsW3wMeW3d+oCYDEWKfV+ASJJdOeyRH6d dM0Wl+3aFSnK/UCuuayod5GIjCI+pM0BMuR/ToYFUgLkMMr60gRPdngSd+PgdzMb0xlh 3vjQ== X-Gm-Message-State: AOAM531W0qda1TF9AuX9Z9WL8i8FextQYyyHxbHslrVdNa1tThh2s6P/ PMHlWDJBxmW+ASaMXxTvt81QcvM2Hgg= X-Google-Smtp-Source: ABdhPJyiwfRfgUFvof6J96IEb3nlU6yPh2kst4/42gIlUzuKzVr51L9y/LCynY6WSCm+1mWXoo7usg== X-Received: by 2002:a05:600c:2204:: with SMTP id z4mr5915886wml.138.1611971601791; Fri, 29 Jan 2021 17:53:21 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id g1sm15181177wrq.30.2021.01.29.17.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Samuel Ortiz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 10/11] target/arm: Do not build TCG objects when TCG is off Date: Sat, 30 Jan 2021 02:52:26 +0100 Message-Id: <20210130015227.4071332-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:33 -0000 From: Samuel Ortiz We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz [PMD: Heavily rebased during more than 2 years then finally rewritten] Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index aac9a383a61..11b7c0e18fe 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,7 +27,8 @@ 'gdbstub64.c', )) -arm_ss.add(files( +arm_tcg_ss = ss.source_set() +arm_tcg_ss.add(files( 'crypto_helper.c', 'debug_helper.c', 'iwmmxt_helper.c', @@ -38,12 +39,12 @@ 'vec_helper.c', 'cpu_tcg.c', )) -arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( +arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files( 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', @@ -52,14 +53,16 @@ 'translate-sve.c', )) +arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss) + arm_softmmu_ss = ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'machine.c', 'monitor.c', - 'psci.c', )) +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c')) target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:53:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fSH-00082w-GE for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:53:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fS6-00080p-4U; Fri, 29 Jan 2021 20:53:31 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:32824) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fS4-0000I9-Ip; Fri, 29 Jan 2021 20:53:29 -0500 Received: by mail-wr1-x42a.google.com with SMTP id 7so10652170wrz.0; Fri, 29 Jan 2021 17:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=e7psjHWNaDe5BRPalel5z+UrUPQyCYHO0ADPAqwnXvE6/jKDRHnq865wvhM3CvcziS 81EyjqLup5Sso5l2NVZ/0wY2xzImn5JfNEpSNIBoIBengxfy1LzI66lsP+ni/80f/evR U7QLC+B3eBq5pi+hy3v4oWie/DVjl15VvVl+DUC7b4bFZ82n+IBpLOg69cciuSH0bv0o ugmYLJK5GlHsO6ioN/+OP/utD5jbLp9Mf2b2fwCAn07n5bGBKAg2Ljhf/XruZU6V7ADq ieVbF8YOSHcYMgG6rdoDn8FpNs1Ulo8zayvnM2zRRrDOTV3lmjsv5yKhGHhUzizRmIXS CcDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=HpcuIS8zbKMlUrQswy8Ke0V1dIFhaN93nWdO/i0yCXV08ASnJVVjk2MbgrR42cOd/s xRe3mqE1AoMMxCftg3BQJUT9x1AKjTsEE9K7dQRIykO7PZcg7AFCqGBi3xJYtqRfBerx ju2i5kOzbwKGBNjm22HsqXHhE3yvZgL1H9JmqhvD79ubGOHmRwhpdaYbUB+G6RFyCMzF imMXEcv6aPgIwqSoy+caTAd8O416s/eAMcvrHxu3BCPyAGtxjVOnVO/oLZuB35WrsYVD HdJp7y+smIdksOgEAgNNDs6J/Dle4rlKPqQR7MUXQtQVmztXmrTMhgq60OIikrDnPUCk 2amw== X-Gm-Message-State: AOAM530ylYUx7Zyrb34+/Clbmx1Sm56ed64u43h/rQ/LB/esvyo1HVVz 9RMUR0Y9ti8y8pMs6ypULcxC5CWO6tg= X-Google-Smtp-Source: ABdhPJxaH/w2Fme7el93QIXUQzDffvAxEB63h7HSmXGa9jkoVnLMptaWM3d09a23cIwVkku9tHUZXg== X-Received: by 2002:a5d:5049:: with SMTP id h9mr7559886wrt.404.1611971606779; Fri, 29 Jan 2021 17:53:26 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id d13sm14972889wrx.93.2021.01.29.17.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org Subject: [PATCH v5 11/11] .travis.yml: Add a KVM-only Aarch64 job Date: Sat, 30 Jan 2021 02:52:27 +0100 Message-Id: <20210130015227.4071332-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:53:37 -0000 From: Philippe Mathieu-Daudé Add a job to build QEMU on Aarch64 with TCG disabled, so this configuration won't bitrot over time. We explicitly modify default-configs/aarch64-softmmu.mak to only select the 'virt' and 'SBSA-REF' machines. Signed-off-by: Philippe Mathieu-Daudé --- Job ran for 7 min 30 sec https://travis-ci.org/github/philmd/qemu/jobs/731428859 --- .travis.yml | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/.travis.yml b/.travis.yml index 5f1dea873ec..4f1d662b5fc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -264,6 +264,38 @@ jobs: - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}" - UNRELIABLE=true + - name: "[aarch64] GCC (disable-tcg)" + arch: arm64 + dist: focal + addons: + apt_packages: + - libaio-dev + - libattr1-dev + - libbrlapi-dev + - libcap-ng-dev + - libgcrypt20-dev + - libgnutls28-dev + - libgtk-3-dev + - libiscsi-dev + - liblttng-ust-dev + - libncurses5-dev + - libnfs-dev + - libnss3-dev + - libpixman-1-dev + - libpng-dev + - librados-dev + - libsdl2-dev + - libseccomp-dev + - liburcu-dev + - libusb-1.0-0-dev + - libvdeplug-dev + - libvte-2.91-dev + - ninja-build + env: + - CONFIG="--disable-containers --disable-tcg --enable-kvm --disable-xen --disable-tools --disable-docs" + - TEST_CMD="make check-unit" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64" + - name: "[ppc64] GCC check-tcg" arch: ppc64le dist: focal -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:55:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fU5-0002o7-UA for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:55:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fTz-0002ka-FC; Fri, 29 Jan 2021 20:55:27 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:37556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fTy-0000qn-2h; Fri, 29 Jan 2021 20:55:27 -0500 Received: by mail-wr1-x42e.google.com with SMTP id v15so10651638wrx.4; Fri, 29 Jan 2021 17:55:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=juwQODmtdvn6bCkwoawWQSLQCGd025TFqesErnaNJGk=; b=aXo/BvSNo1mvBU3NnkxeQi8TkxlnnlCBbz/JTlhSc1P2uBAB+GdYaWbRmPJz5Qo0hZ bqP98JT7yZHWwWWG0Q0DnOjejVaHk/DnK8A7ScGdZyfc2kOrbmTDDDvSmakyhsFveVwa dSNC13s6qE8DYs49ckmXtVma4e9CLG3h5wQQnOY7C3JJP2vMZf0Nt0heler6VZG/xE5+ 0nRfXqOfyozeweDklBeVEJQWir5aZkxCD2n663McgKgvLUQVJaGiS1hy6FArdD/tDkMo kcWUmHE3oiv/fXS5or4ZsZFbS414WIwvbU/YhO+IVWpzhxkcwpDUtnvqeSkiqKIlHsa2 8sqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=juwQODmtdvn6bCkwoawWQSLQCGd025TFqesErnaNJGk=; b=TGS8v2kJikgstAnbTy8xBAjoBwGEh63f4VjxiPPz67/0lsDmoIZFZPC12MM8RGgiyK aWAgLSsyvAb/NZ1fZA1Tt2PmCTWK7enJlukVxKic1r6y+57n1VoEA4glsS6IIovN5bXb 6ekHS81ZJ/+/tMkhwaiZFZS4UnM7cdB7oSZfEhEPAAAUS9+1X104RQ+Fr8PMfj9kRxK6 jZd74LuBPfQRzxhDokean20KKEK5y+8If55AGa/F9c0kzD17nudM80aKv97J7a/eukSH IaAHmCh3o3qe6rSiwSVk6JSDD/bHfYMY+LlkbGcEgxySGVfXXeL9jxigrztLUpsU42Y3 kf9w== X-Gm-Message-State: AOAM531DttIRhjzmppODCAKbToidT6/JKwAOBRuNECJ5OqmsKbf+yYSs 8mWfG2RAyGqAnk0fyQZvlF8a+ggJ4fg= X-Google-Smtp-Source: ABdhPJwATqa7akZxhOTXvXQr704cZQzfALE6d38hH/ZEMByZ6nleBgH/5Nbdi1P3oeX/wJ6n+aKSzQ== X-Received: by 2002:adf:f452:: with SMTP id f18mr7158826wrp.11.1611971722179; Fri, 29 Jan 2021 17:55:22 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s25sm16116986wrs.49.2021.01.29.17.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:55:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Joel Stanley , qemu-trivial@nongnu.org, Laurent Vivier , Peter Maydell , Antony Pavlov , Alistair Francis , Michael Tokarev , Niek Linnenbank , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/3] hw/arm: Misc trivial fixes/cleanups Date: Sat, 30 Jan 2021 02:55:16 +0100 Message-Id: <20210130015519.4072469-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:55:27 -0000 A pair of bugfixes and cleanup patches noticed while=0D rebasing my "Support disabling TCG on ARM (part 2)" series.=0D =0D Philippe Mathieu-Daud=C3=A9 (3):=0D hw/arm/Kconfig: Add missing dependency STM32F405 -> OR_IRQ=0D hw/arm/Kconfig: Add missing dependency EXYNOS4210 -> OR_IRQ=0D hw/arm: Display CPU type in machine description=0D =0D hw/arm/digic_boards.c | 2 +-=0D hw/arm/microbit.c | 2 +-=0D hw/arm/netduino2.c | 2 +-=0D hw/arm/netduinoplus2.c | 2 +-=0D hw/arm/orangepi.c | 2 +-=0D hw/arm/stellaris.c | 4 ++--=0D hw/arm/Kconfig | 2 ++=0D 7 files changed, 9 insertions(+), 7 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Fri Jan 29 20:55:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fUI-0002qW-D4 for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:55:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fU2-0002mE-R5; Fri, 29 Jan 2021 20:55:33 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:53399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fU1-0000sX-GF; Fri, 29 Jan 2021 20:55:30 -0500 Received: by mail-wm1-x329.google.com with SMTP id j18so8146571wmi.3; Fri, 29 Jan 2021 17:55:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=BZTRcOn/HJkpWsRhLv0QpZri9dtTj9FhDkxOHuyJAqjGBTJaQzZVNL5WyOC21THEAS IzTqxmkDU5ePXyBLSWvji/9MjOkJBxOe8N5616ednCW1h+emp+Xw2NFIogFZS/wiD+Mm J8ASjop3aQ3wyVi6hF8VhLhaZG27DBg/t0azC5Dc2HQKG1n2YirYiVVvirb1owUWvJzr yscTazLhBVy+1p9ePd+ByVPUJZbAs1J8UTEukJQgoDffUqPvGp0nJF3ZTIE0Ep4E6dXn zuJaT3rnVLcWhaTV1kfk/MGweZJlBCPXlnbRZxlf9gq7ZI1sLdAdG4NEDPWLGXcHK797 1zIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=aL+teRMArEQ6fvV7QrvXr65h6FQ8X5ni7yeJrEyvHplm0WMOlEq9imBscwod72bw5c RlsprdFHEy5tlQiMiPUND7xeGN4IL/QtV+eEs+cyMGztIY86sk/OrNZ30KxO7XuPGlP9 qPHEJLOefIABS+Tj1YYDtfc8XBbtJqAanyvQ4FC0qL16jU/seLfN3iqo1g42/gykzT+5 W4Jkwz2VsZYFomXLugRmzOurtAoYCC+oyWDOgPQbjFhJa+W2pMzmdHCQy/MV01PQUMOf qovmPbeeDlX8dsrke7QX4e0JvwuSswxzlXfGoli2MnjupH0TWy0dcPe0/XGMeCQvUFI7 n16Q== X-Gm-Message-State: AOAM533cuTXJbedaMWjAzWh+YWzc8+IBrfjmSDlbu6oNy5+BGlnTDUCM dl1gOE9F76oGexLgwCL1CbLSttB/53o= X-Google-Smtp-Source: ABdhPJzxzPBg4SeY+Z6XReaUVeRJ6xga5fOttyCGezTucRzWBU4vTP6FOuodsFF+cO3/geJk/sy++A== X-Received: by 2002:a7b:c188:: with SMTP id y8mr5772912wmi.173.1611971727158; Fri, 29 Jan 2021 17:55:27 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id d2sm16883840wre.39.2021.01.29.17.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:55:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Joel Stanley , qemu-trivial@nongnu.org, Laurent Vivier , Peter Maydell , Antony Pavlov , Alistair Francis , Michael Tokarev , Niek Linnenbank , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/3] hw/arm/Kconfig: Add missing dependency STM32F405 -> OR_IRQ Date: Sat, 30 Jan 2021 02:55:17 +0100 Message-Id: <20210130015519.4072469-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015519.4072469-1-f4bug@amsat.org> References: <20210130015519.4072469-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:55:33 -0000 The STM32F405 SoC uses an OR gate on its ADC IRQs. Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC") Signed-off-by: Philippe Mathieu-Daudé --- Cc: alistair@alistair23.me --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 13cc42dcc84..a320a124855 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -336,6 +336,7 @@ config STM32F205_SOC config STM32F405_SOC bool select ARM_V7M + select OR_IRQ select STM32F4XX_SYSCFG select STM32F4XX_EXTI -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:55:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fUK-0002u9-NV for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:55:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fU8-0002oK-Oy; Fri, 29 Jan 2021 20:55:41 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:43112) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fU6-0000uG-RH; Fri, 29 Jan 2021 20:55:36 -0500 Received: by mail-wr1-x42d.google.com with SMTP id z6so10572199wrq.10; Fri, 29 Jan 2021 17:55:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0V4s5H5BNAAAhx8ZOQKz6ZBT7eCkPLs40vaKE8q9iFo=; b=APEse49A8zK0chpt6sp8oLYngL46dVofgjHcagLSV/788H7B+zhuhPJcbysfMy4nz9 7yFpIwdiozY3UH6COinIyhLWTpcQyuvzJ8wPie3wcmipNmy++QCvOGM8jy5ppfP0aVCh LXXOhE/eLhSK4PTnH1NziZ68dYjW9lPQtKcU9NtJQ+EKFa6KW/O9W9jB8H4FiOSAvQ9A MmcVFLZIzI+mT2wQRMiUov1wW/WyonwMGHJigitn3RAud4MkwCZ9qSeIVBY8ER9rU+TS QusOVR6pjG/Vvm74qn6i7z0nQDSZ6PvpSOJdCntz2V1WfFLlb6zT3piprJ2a4ApNa6aI aw1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0V4s5H5BNAAAhx8ZOQKz6ZBT7eCkPLs40vaKE8q9iFo=; b=PHpyYllOfj5ee7s2vs1qMKkGcwhWJnTPdW65ZfehZYoGmmDhuBxojqWlnhRbP8nfRM 6/mEhNNDK7Ew6e9IYwLm5M/c5/fDMSyus92udXjW3SWWeGA2js5oPfekDBXbedakj2e8 E/3wiU79X+a0RWFVX/2lnoEiLlnpVHYzvuR+8UMbrJT3LX1z0hkuJipZHBveX7hf2MWM kIh4qW4ipUFF0nsX1vKoYQLFInVWlbESJC8Uz2UFAF4MYb1Gh3yxoYWA02v03SSbrSj3 TkbxRLmhVztGXHodOVv5sBMZHWoRF5ZhL8T5RrlpT3xD/yGwh8hvRUfx2Ok1omo/7YpJ mo5A== X-Gm-Message-State: AOAM532po/96k/zmTQ/lcEGyEkwjMSpT6KdbshfU6WtpWDIm4GfBrRt3 Ct3PRbSYvS/h/pW0qa7CEO0YMrkguOs= X-Google-Smtp-Source: ABdhPJztBFrHwR7cyMvGx0PTknqjLiLVu6pDu8HNJL0HmBuBrCqF9fW1FiCM4aLH3J/OEcBqHp8BTA== X-Received: by 2002:a5d:60c2:: with SMTP id x2mr7649542wrt.248.1611971732203; Fri, 29 Jan 2021 17:55:32 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id s23sm11913258wmc.35.2021.01.29.17.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:55:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Joel Stanley , qemu-trivial@nongnu.org, Laurent Vivier , Peter Maydell , Antony Pavlov , Alistair Francis , Michael Tokarev , Niek Linnenbank , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/3] hw/arm/Kconfig: Add missing dependency EXYNOS4210 -> OR_IRQ Date: Sat, 30 Jan 2021 02:55:18 +0100 Message-Id: <20210130015519.4072469-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015519.4072469-1-f4bug@amsat.org> References: <20210130015519.4072469-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:55:44 -0000 The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines. Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization") Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a320a124855..223016bb4e8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -52,6 +52,7 @@ config EXYNOS4 select PTIMER select SDHCI select USB_EHCI_SYSBUS + select OR_IRQ config HIGHBANK bool -- 2.26.2 From MAILER-DAEMON Fri Jan 29 20:55:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5fUO-0002us-Gd for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 20:55:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5fUE-0002pH-Rp; Fri, 29 Jan 2021 20:55:44 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5fUB-0000vF-Oh; Fri, 29 Jan 2021 20:55:41 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m13so10621048wro.12; Fri, 29 Jan 2021 17:55:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=WgnMZojyiZx5lKB4qw0pSqL5QpZH65Z4MwQDqUMZM2RWGZuS8sMWrtFuGc1fN3KRJg sNkeEjdUsh/SrkrIgOvXF4INgjLmXB6aIjAoKfGSOSocLcCT57BSyM2BLnE6BkEttZ1j jP8CNfcpWinztNrSi0CKiCxb/ct6hX19JL4vBWUTf8e36Nl8sfbSmCP4blkpXvreGBw7 w+A9hoe9ITYRaKwq+L0LHmSsvGdRFirk3gMT6R0PjZnZNVrw7npmu5W9pMUysT6OOqLp W7vswo4+kYSe+RX9bjPERa1OgmGGmJiH7vvLS1uzCX6/o9/LB9qpA8I7Gjpz6CpTk5XP UD5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=RGCEWpP5RBcmRVXfrdPEzCwCGbIbN2hDzwo/b+ZFMpPqiJV49lh8f90XRF+HLQ1nCf mrROlPUvHLohEWbubsv2nf8YMCe4VngJ974t1GExXy9jS9RVfwVvBp7cZbsZBumO/21c epaNQKVtFBiKqnfZar4L+rgURHUV4hwxT3y6Dyfkr3rLXl4i7k7ogZaXITK/KjQtLxXn XsGTqzJlMfif33f3U/pgT7DiAorhTIbwULI/OBeAQZN3Ru2sYmdAD41qpArPX8StdSI6 3YxE6skY2yqKRZ1PnDGnDGbcvGIDQKoT8WCsT46UND2KtBoWrSrJgaXJElZjBffSncRv Wh8Q== X-Gm-Message-State: AOAM531YuqsciM1g4Mbt7r3qhgmrvVl/cmTuHlQKKTDR93mh3QQXMM3B xSSVxRxjl9jFW9k/4OGSAg/oZeP3lWw= X-Google-Smtp-Source: ABdhPJwNDKiEtCsNKC4h5nbi85ikz6c+r19mxOIwcAsv4JOWkdlDVH6LMJvnFFPqPNw2qIfTu4RMrQ== X-Received: by 2002:adf:8464:: with SMTP id 91mr7164004wrf.188.1611971737537; Fri, 29 Jan 2021 17:55:37 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id f17sm15861336wrv.0.2021.01.29.17.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:55:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Joel Stanley , qemu-trivial@nongnu.org, Laurent Vivier , Peter Maydell , Antony Pavlov , Alistair Francis , Michael Tokarev , Niek Linnenbank , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/3] hw/arm: Display CPU type in machine description Date: Sat, 30 Jan 2021 02:55:19 +0100 Message-Id: <20210130015519.4072469-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015519.4072469-1-f4bug@amsat.org> References: <20210130015519.4072469-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 01:55:46 -0000 Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/digic_boards.c | 2 +- hw/arm/microbit.c | 2 +- hw/arm/netduino2.c | 2 +- hw/arm/netduinoplus2.c | 2 +- hw/arm/orangepi.c | 2 +- hw/arm/stellaris.c | 4 ++-- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index be12873673b..6cdc1d83fca 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine) static void canon_a1100_machine_init(MachineClass *mc) { - mc->desc = "Canon PowerShot A1100 IS"; + mc->desc = "Canon PowerShot A1100 IS (ARM946)"; mc->init = &canon_a1100_init; mc->ignore_memory_transaction_failures = true; mc->default_ram_size = 64 * MiB; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 0947491cb97..e9494334ce7 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "BBC micro:bit"; + mc->desc = "BBC micro:bit (Cortex-M0)"; mc->init = microbit_init; mc->max_cpus = 1; } diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 8f103341443..1733b71507c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine) static void netduino2_machine_init(MachineClass *mc) { - mc->desc = "Netduino 2 Machine"; + mc->desc = "Netduino 2 Machine (Cortex-M3)"; mc->init = netduino2_init; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 68abd3ec69d..d3ad7a2b675 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { - mc->desc = "Netduino Plus 2 Machine"; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index d6306dfddae..40cdb5c6d2c 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine) static void orangepi_machine_init(MachineClass *mc) { - mc->desc = "Orange Pi PC"; + mc->desc = "Orange Pi PC (Cortex-A7)"; mc->init = orangepi_init; mc->block_default_type = IF_SD; mc->units_per_default_bus = 1; diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ad72c0959f1..27292ec4113 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S811EVB"; + mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; mc->init = lm3s811evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); @@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S6965EVB"; + mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; mc->init = lm3s6965evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); -- 2.26.2 From MAILER-DAEMON Fri Jan 29 23:32:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5hwF-0003e4-Ck for mharc-qemu-arm@gnu.org; Fri, 29 Jan 2021 23:32:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5hwD-0003dr-Uj; Fri, 29 Jan 2021 23:32:45 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5hwB-0008Ip-BQ; Fri, 29 Jan 2021 23:32:45 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DSLrP4FBRzjBJ7; Sat, 30 Jan 2021 12:31:33 +0800 (CST) Received: from DESKTOP-8RFUVS3.china.huawei.com (10.174.185.179) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Sat, 30 Jan 2021 12:32:27 +0800 From: Zenghui Yu To: , , , CC: , Zenghui Yu Subject: [PATCH v2] hw/arm/smmuv3: Fix addr_mask for range-based invalidation Date: Sat, 30 Jan 2021 12:32:20 +0800 Message-ID: <20210130043220.1345-1-yuzenghui@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.174.185.179] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=yuzenghui@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 04:32:46 -0000 When handling guest range-based IOTLB invalidation, we should decode the TG field into the corresponding translation granule size so that we can pass the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to properly emulate the architecture. Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") Signed-off-by: Zenghui Yu --- * From v1: - Fix the compilation error hw/arm/smmuv3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bbca0e9f20..98b99d4fe8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, { SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); IOMMUTLBEvent event; - uint8_t granule = tg; + uint8_t granule; if (!tg) { SMMUEventInfo event = {.inval_ste_allowed = true}; @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, return; } granule = tt->granule_sz; + } else { + granule = tg * 2 + 10; } event.type = IOMMU_NOTIFIER_UNMAP; -- 2.19.1 From MAILER-DAEMON Sat Jan 30 01:30:45 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5jmO-00042n-8r for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 01:30:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5jmM-00042X-Nl; Sat, 30 Jan 2021 01:30:42 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5jmG-0002qO-PN; Sat, 30 Jan 2021 01:30:42 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DSPS921QJzjDTN; Sat, 30 Jan 2021 14:29:13 +0800 (CST) Received: from [10.174.184.42] (10.174.184.42) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.498.0; Sat, 30 Jan 2021 14:30:05 +0800 Subject: Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener To: Kirti Wankhede , Alex Williamson , , References: <20210111073439.20236-1-zhukeqian1@huawei.com> <590a2752-9bba-6971-51b0-a8accee6e814@nvidia.com> CC: Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Stefan Hajnoczi , Peter Maydell , Andrew Jones , Eduardo Habkost , Peter Xu , "Dr . David Alan Gilbert" , "Igor Mammedov" , , Zenghui Yu , From: Keqian Zhu Message-ID: <5c4b616c-9e73-17c6-b9a4-1ab0a6079780@huawei.com> Date: Sat, 30 Jan 2021 14:30:04 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <590a2752-9bba-6971-51b0-a8accee6e814@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhukeqian1@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 06:30:42 -0000 Hi Kirti, On 2021/1/28 5:03, Kirti Wankhede wrote: > > > On 1/11/2021 1:04 PM, Keqian Zhu wrote: >> For now the switch of vfio dirty page tracking is integrated into >> the vfio_save_handler, it causes some problems [1]. >> > > Sorry, I missed [1] mail, somehow it didn't landed in my inbox. > >> The object of dirty tracking is guest memory, but the object of >> the vfio_save_handler is device state. This mixed logic produces >> unnecessary coupling and conflicts: >> >> 1. Coupling: Their saving granule is different (perVM vs perDevice). >> vfio will enable dirty_page_tracking for each devices, actually >> once is enough. > > That's correct, enabling dirty page tracking once is enough. But log_start and log_stop gets called on address space update transaction, region_add() or region_del(), at this point migration may not be active. We don't want to allocate bitmap memory in kernel for lifetime of VM, without knowing migration will be happen or not. vfio_iommu_type1 module should allocate bitmap memory only while migration is active. > Yeah, we can use global start/stop callbacks as suggested by Paolo, which solves this problem. > Paolo's suggestion here to use log_global_start and log_global_stop callbacks seems correct here. But at this point vfio device state is not yet changed to |_SAVING as you had identified it in [1]. May be we can start tracking bitmap in iommu_type1 module while device is not yet _SAVING, but getting dirty bitmap while device is yet not in _SAVING|_RUNNING state doesn't seem optimal solution. > > Pasting here your question from [1] > >> Before start dirty tracking, we will check and ensure that the device >> is at _SAVING state and return error otherwise. But the question is >> that what is the rationale? Why does the VFIO_IOMMU_DIRTY_PAGES >> ioctl have something to do with the device state? > > Lets walk through the types of devices we are supporting: > 1. mdev devices without IOMMU backed device > Vendor driver pins pages as and when required during runtime. We can say that vendor driver is smart which identifies the pages to pin. We are good here. > > 2. mdev device with IOMMU backed device > This is similar to vfio-pci, direct assigned device, where all pages are pinned at VM bootup. Vendor driver is not smart, so bitmap query will report all pages dirty always. If --auto-converge is not set, VM stucks infinitely in pre-copy phase. This is known to us. > little question here ;-) . Why auto-converge (slow down vCPU) helps to ease the case of full dirty? > 3. mdev device with IOMMU backed device with smart vendor driver > In this case as well all pages are pinned at VM bootup, but vendor driver is smart to identify the pages and pin them explicitly. > Pages can be pinned anytime, i.e. during normal VM runtime or on setting _SAVING flag (entering pre-copy phase) or while in iterative pre-copy phase. There is no restriction based on these phases for calling vfio_pin_pages(). Vendor driver can start pinning pages based on its device state when _SAVING flag is set. In that case, if dirty bitmap is queried before that then it will report all sysmem as dirty with an unnecessary copy of sysmem. > As an optimal solution, I think its better to query bitmap only after all vfio devices are in pre-copy phase, i.e. after _SAVING flag is set. OK, I get your idea. But Qemu assumes all pages are dirty initially, this seems not a problem. Let's assume we have a device of type 3, and this device starts to pin pages on setting _SAVING flag. Before this patch, the work flow is: { ram_save_setup() memory_global_dirty_log_start(): start dirty tracking excludes vfio part. migration_bitmap_sync_precopy(): try to sync dirty log from kvm, vhost etc, including vfio (as all device saving is not satisfied, fail to get log from vfio). The result is that bitmap of ramblock is all dirty. vfio_save_setup() of this device vfio_migration_set_state(): Add SAVING state to this device, and vfio starts to log dirty page of this device. first round (i.e. bulk stage) of ram saving: only handle dirty log which is collected from the first call of migration_bitmap_sync_precopy(). iterative stage of ram saving: when the remaining dirty log is less than threshold, call migration_bitmap_sync_precopy() again. At this stage, all device is saving, so success to get log from vfio. } With this patch, the work flow is: { ram_save_setup() memory_global_dirty_log_start(): start dirty tracking includes vfio part. migration_bitmap_sync_precopy(): try to sync dirty log from kvm, vhost etc, including vfio (as all device saving is not checked, success to get full dirty log from vfio). The result is that bitmap of ramblock is all dirty. vfio_save_setup() of this device vfio_migration_set_state(): Add SAVING state to this device, and vfio starts to log dirty page of this device. first round of ram saving: only handles dirty log which is collected from the first call of migration_bitmap_sync_precopy(). iterative stage of ram saving: when the remaining dirty log is less than a threshold, calls migration_bitmap_sync_precopy() again. At this stage, all device is saving, so success to get log from vfio. } We can see that there is no unnecessary copy of guest memory with this patch. > >> 2. Conflicts: The ram_save_setup() traverses all memory_listeners >> to execute their log_start() and log_sync() hooks to get the >> first round dirty bitmap, which is used by the bulk stage of >> ram saving. However, it can't get dirty bitmap from vfio, as >> @savevm_ram_handlers is registered before @vfio_save_handler. >> > Right, but it can get dirty bitmap from vfio device in it's iterative callback > ram_save_pending -> > migration_bitmap_sync_precopy() .. -> > vfio_listerner_log_sync > Yeah, this work flow is OK. But we are not able to handle vfio dirty log at the first round of ram saving. We plan to add a new interface named manual_log_clear in vfio[1]. If this interface is enabled, kernel vfio doesn't automatically clear and repopulate dirty bitmap when report dirty log to Qemu. These actions will be triggered by Qemu when it invokes manual_log_clear (memory_region_clear_dirty_bitmap()) before handles the dirty log. Under the following conditions: (1)Qemu can handles vfio dirty log at the first round of ram saving. (2)device is of type1. (3)manual_log_clear is enabled. (3)device driver unpins some scopes during the first round of ram saving (before Qemu actually handles these scopes). Then these unpinned scope is not reported to Qemu at iterative stage (manual_log_clear clears them and re-population does not contains them), which avoid unnecessary copy of guest memory. Thanks, Keqian [1]https://lore.kernel.org/kvmarm/20210128151742.18840-1-zhukeqian1@huawei.com/ > Thanks, > Kirti > >> Move the switch of vfio dirty_page_tracking into vfio_memory_listener >> can solve above problems. Besides, Do not require devices in SAVING >> state for vfio_sync_dirty_bitmap(). >> >> [1] https://www.spinics.net/lists/kvm/msg229967.html >> >> Reported-by: Zenghui Yu >> Signed-off-by: Keqian Zhu >> --- >> hw/vfio/common.c | 53 +++++++++++++++++++++++++++++++++++++-------- >> hw/vfio/migration.c | 35 ------------------------------ >> 2 files changed, 44 insertions(+), 44 deletions(-) >> >> diff --git a/hw/vfio/common.c b/hw/vfio/common.c >> index 6ff1daa763..9128cd7ee1 100644 >> --- a/hw/vfio/common.c >> +++ b/hw/vfio/common.c >> @@ -311,7 +311,7 @@ bool vfio_mig_active(void) >> return true; >> } >> -static bool vfio_devices_all_saving(VFIOContainer *container) >> +static bool vfio_devices_all_dirty_tracking(VFIOContainer *container) >> { >> VFIOGroup *group; >> VFIODevice *vbasedev; >> @@ -329,13 +329,8 @@ static bool vfio_devices_all_saving(VFIOContainer *container) >> return false; >> } >> - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { >> - if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) >> - && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { >> - return false; >> - } >> - continue; >> - } else { >> + if ((vbasedev->pre_copy_dirty_page_tracking == ON_OFF_AUTO_OFF) >> + && (migration->device_state & VFIO_DEVICE_STATE_RUNNING)) { >> return false; >> } >> } >> @@ -987,6 +982,44 @@ static void vfio_listener_region_del(MemoryListener *listener, >> } >> } >> +static void vfio_set_dirty_page_tracking(VFIOContainer *container, bool start) >> +{ >> + int ret; >> + struct vfio_iommu_type1_dirty_bitmap dirty = { >> + .argsz = sizeof(dirty), >> + }; >> + >> + if (start) { >> + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; >> + } else { >> + dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; >> + } >> + >> + ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); >> + if (ret) { >> + error_report("Failed to set dirty tracking flag 0x%x errno: %d", >> + dirty.flags, errno); >> + } >> +} >> + >> +static void vfio_listener_log_start(MemoryListener *listener, >> + MemoryRegionSection *section, >> + int old, int new) >> +{ >> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >> + >> + vfio_set_dirty_page_tracking(container, true); >> +} >> + >> +static void vfio_listener_log_stop(MemoryListener *listener, >> + MemoryRegionSection *section, >> + int old, int new) >> +{ >> + VFIOContainer *container = container_of(listener, VFIOContainer, listener); >> + >> + vfio_set_dirty_page_tracking(container, false); >> +} >> + >> static int vfio_get_dirty_bitmap(VFIOContainer *container, uint64_t iova, >> uint64_t size, ram_addr_t ram_addr) >> { >> @@ -1128,7 +1161,7 @@ static void vfio_listerner_log_sync(MemoryListener *listener, >> return; >> } >> - if (vfio_devices_all_saving(container)) { >> + if (vfio_devices_all_dirty_tracking(container)) { >> vfio_sync_dirty_bitmap(container, section); >> } >> } >> @@ -1136,6 +1169,8 @@ static void vfio_listerner_log_sync(MemoryListener *listener, >> static const MemoryListener vfio_memory_listener = { >> .region_add = vfio_listener_region_add, >> .region_del = vfio_listener_region_del, >> + .log_start = vfio_listener_log_start, >> + .log_stop = vfio_listener_log_stop, >> .log_sync = vfio_listerner_log_sync, >> }; >> diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c >> index 00daa50ed8..c0f646823a 100644 >> --- a/hw/vfio/migration.c >> +++ b/hw/vfio/migration.c >> @@ -395,40 +395,10 @@ static int vfio_load_device_config_state(QEMUFile *f, void *opaque) >> return qemu_file_get_error(f); >> } >> -static int vfio_set_dirty_page_tracking(VFIODevice *vbasedev, bool start) >> -{ >> - int ret; >> - VFIOMigration *migration = vbasedev->migration; >> - VFIOContainer *container = vbasedev->group->container; >> - struct vfio_iommu_type1_dirty_bitmap dirty = { >> - .argsz = sizeof(dirty), >> - }; >> - >> - if (start) { >> - if (migration->device_state & VFIO_DEVICE_STATE_SAVING) { >> - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_START; >> - } else { >> - return -EINVAL; >> - } >> - } else { >> - dirty.flags = VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP; >> - } >> - >> - ret = ioctl(container->fd, VFIO_IOMMU_DIRTY_PAGES, &dirty); >> - if (ret) { >> - error_report("Failed to set dirty tracking flag 0x%x errno: %d", >> - dirty.flags, errno); >> - return -errno; >> - } >> - return ret; >> -} >> - >> static void vfio_migration_cleanup(VFIODevice *vbasedev) >> { >> VFIOMigration *migration = vbasedev->migration; >> - vfio_set_dirty_page_tracking(vbasedev, false); >> - >> if (migration->region.mmaps) { >> vfio_region_unmap(&migration->region); >> } >> @@ -469,11 +439,6 @@ static int vfio_save_setup(QEMUFile *f, void *opaque) >> return ret; >> } >> - ret = vfio_set_dirty_page_tracking(vbasedev, true); >> - if (ret) { >> - return ret; >> - } >> - >> qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE); >> ret = qemu_file_get_error(f); >> > . > From MAILER-DAEMON Sat Jan 30 09:48:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5rXp-0001np-1C for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 09:48:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5rXn-0001lP-A5; Sat, 30 Jan 2021 09:48:11 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:37556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5rXl-0004Ty-P3; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id a17sm14650465wrx.63.2021.01.30.06.48.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Jan 2021 06:48:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , Richard Henderson , Claudio Fontana , =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm@nongnu.org References: <20210130015227.4071332-1-f4bug@amsat.org> <20210130015227.4071332-4-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sat, 30 Jan 2021 15:48:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210130015227.4071332-4-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 14:48:11 -0000 On 1/30/21 2:52 AM, Philippe Mathieu-Daudé wrote: > KVM requires a cpu based on (at least) the ARMv7 architecture. > > Only enable the following ARMv4 CPUs when TCG is available: > > - StrongARM (SA1100/1110) > - OMAP1510 (TI925T) > > The following machines are no more built when TCG is disabled: > > - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310) > - sx1 Siemens SX1 (OMAP310) V2 > - sx1-v1 Siemens SX1 (OMAP310) V1 > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 2 -- > hw/arm/Kconfig | 8 ++++++++ > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 341d439de6f..8a53e637d23 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y > CONFIG_FSL_IMX31=y > CONFIG_MUSICPAL=y > CONFIG_MUSCA=y > -CONFIG_CHEETAH=y > -CONFIG_SX1=y > CONFIG_NSERIES=y > CONFIG_STELLARIS=y > CONFIG_REALVIEW=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 223016bb4e8..7126d82f6ce 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -1,3 +1,7 @@ > +config ARM_V4 > + bool > + depends on TCG > + > config ARM_VIRT > bool > imply PCI_DEVICES > @@ -31,6 +35,8 @@ config ARM_VIRT > > config CHEETAH > bool > + default y if TCG This doesn't work as being added to all targets... > + select ARM_V4 > select OMAP > select TSC210X From MAILER-DAEMON Sat Jan 30 10:37:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5sJj-00087e-0V for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 10:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5sJh-00086O-ST for qemu-arm@nongnu.org; Sat, 30 Jan 2021 10:37:41 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]:42450) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5sJf-0007rh-VD for qemu-arm@nongnu.org; Sat, 30 Jan 2021 10:37:41 -0500 Received: by mail-ej1-x62e.google.com with SMTP id r12so17457155ejb.9 for ; Sat, 30 Jan 2021 07:37:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=78kOyNsh9PFQ35W6G6J34UFL3WJ0plW3fjCLydvhNGU=; b=evI+JCiN4q9fC6wQYJuhNtFMDoH0y/ah6iDJRi+XmLvWYdNKZghG075xgvVS6nEH63 QdOKU1s/tbYWcdHwDvDugZGRZzCkn/NBqE3cYw+ytxwNgNK7h9d4lF1nfdaX2dqkhC1s m4+eSEQWVVB2kCpgZVbmzfVhV2dfOIYlq6Vn8FQITksyJmROd5NLThrkFBPHH5OqjzTl COIOuFHypRtV5TiZdLH/9lecUqz5sRcjDl+DEHJb6ojwly5a2AJDEb3Bk7F64IO5s7Q0 DlGL1cp0xxiiP+UvlIJqJPxke6LXOQduMAUGGia1Z027oaon4bMF7R08U/DuutijOrQs ViAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=78kOyNsh9PFQ35W6G6J34UFL3WJ0plW3fjCLydvhNGU=; b=NuVyf75z1IA2DdJz61F/Ct/ZFHnTL/Pu+QJ8xqTp/Z60N+Vy3TpN87aACeL5pyCFL8 HsdSoHFPCyJQLq5y34iFrCdKE0Yv+hfRvvvCZxDF+tUQTRECSc4yVNp3r5OgWRD9d3tN PRsTxpg6vmX8yiuivBFIhkqfEH8jjw0+HwHQZ1jiY2LW3LI3oyxGO1SwDjA4nwEViNMk 1W9Pg/Spqf0D7q3FXUPUt/65GiMc4sAZMMQmAe91zHyCqBbhZGXZyJ7A8OFc5aYoESo3 JBL617zqqUPSK2c/4vP5cSqMJYiJTO/0+d71mNG81wTISTknAaHYYksmAjxwDRdC0+jX /CUg== X-Gm-Message-State: AOAM531xF/2w0wv0RHpZj4oBrM9LguLi7fZPR9YvwO0X2k6vVgXenAOd w1sBuT8idsLXLDX+TZBuSwxFMoKdSOS2yonTxh6AlQ== X-Google-Smtp-Source: ABdhPJyD++UlciKvmROO24kS3r/XXDVKijRu1H7xIYaJRV48MHyTsJtFtdfA1zpizwOdbfEwhqs6mx4IqJ20F8mkBMc= X-Received: by 2002:a17:906:b215:: with SMTP id p21mr9386002ejz.407.1612021058129; Sat, 30 Jan 2021 07:37:38 -0800 (PST) MIME-Version: 1.0 References: <20210130015227.4071332-1-f4bug@amsat.org> <20210130015227.4071332-4-f4bug@amsat.org> In-Reply-To: <20210130015227.4071332-4-f4bug@amsat.org> From: Peter Maydell Date: Sat, 30 Jan 2021 15:37:26 +0000 Message-ID: Subject: Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Richard Henderson , kvm-devel , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?B?QWxleCBCZW5uw6ll?= , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 15:37:42 -0000 On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daud=C3=A9 = wrote: > > KVM requires a cpu based on (at least) the ARMv7 architecture. These days it requires ARMv8, because we dropped 32-bit host support, and all 64-bit host CPUs are v8. thanks -- PMM From MAILER-DAEMON Sat Jan 30 13:36:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5v6l-0007j7-TW for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 13:36:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5v6k-0007iD-FL; Sat, 30 Jan 2021 13:36:30 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:35311) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5v6i-00044L-Nr; Sat, 30 Jan 2021 13:36:30 -0500 Received: by mail-wm1-x32b.google.com with SMTP id e15so9733903wme.0; Sat, 30 Jan 2021 10:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=1mNh9mlH0J+zMjgMzcqZVDvGumB7ljSHk0DeAaBnlyo=; b=WbGzkcuAeKstM9npuwuwjBnsuEZm3r5ywk/P67nlhSNsqQWcxGtIyp/B/UlSUyJqWe rWBBL0Hz04hYGcGKDbdlr+Q5TbjmlDYeP5aAaN0R5Ay5zodmCvmp+ggN5wHssG7x7vyD 3JMGGA5AK75ov59qdcqNoZf8s+vtn2UJxw1pfb79km+kvaVW4eKgDH3lx4Mh0ZHyu1Es c8DrTbZ1CxgbbiLIZJsUSSC8Q0FPV6OGKMYCyFML2qBkeE7xTcngCuC6pXhF6fRDpxw8 rRY35sV+EjjJAipw1mYL04unB71LVdiuXGyJ5HxfzbLH8oo7/z0NEn0QORV5RNgzd6a6 q3Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=1mNh9mlH0J+zMjgMzcqZVDvGumB7ljSHk0DeAaBnlyo=; b=TnzJAUBfZyY5Akaw9ecHeNrSi0wE6bT0nxX7YYXsTgkdm889qlA2pWBFTyixysf8pO ErtgZlPRyv9Bsd4BZPf4tCtInqj1YK8CtlswhMbm3rYmdD1Wfb9xfRpaHSOl5+7W1KAL YVlthZOAju5EMVUTKhpWbePlReuuNCOx/JaTW7/pikLUW3ZmgpXU391I5HAtJsdFJRb7 un3aAUnmvrguDOrLGNQyY1xmuzIGJtFR9sLYd4J1QxArPDSF7ypEpizLOVA/u778zUrj 1TeJivZf2o3Rf0TEI1/vmiwk0BpMbnlZfNcDlcBDF+9sxk5ASqBxzwCROnPjbFdY7Z+Z wIqg== X-Gm-Message-State: AOAM533pmPXaWcMzeUnJX4+B1tU+CU2P45QjQI2JQQ/+TVOPa+f5/K9z A2R3ufxsrNlwzXwDQUBxDX+EfhFot+c= X-Google-Smtp-Source: ABdhPJyXkcz3LAR4E0+PEoeKblLFblLD+ThxjmdYgyS8ayJSPNpoC+HMjVsKg7NDgRMrHhT3Y4wlJQ== X-Received: by 2002:a1c:3587:: with SMTP id c129mr8531992wma.76.1612031785730; Sat, 30 Jan 2021 10:36:25 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id y67sm15807411wmg.47.2021.01.30.10.36.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Jan 2021 10:36:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: Peter Maydell Cc: QEMU Developers , Richard Henderson , kvm-devel , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Claudio Fontana , =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm References: <20210130015227.4071332-1-f4bug@amsat.org> <20210130015227.4071332-4-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <2871f7db-fe0a-51d6-312d-6d05ffa281a3@amsat.org> Date: Sat, 30 Jan 2021 19:36:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 18:36:30 -0000 Hi Peter, On 1/30/21 4:37 PM, Peter Maydell wrote: > On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé wrote: >> >> KVM requires a cpu based on (at least) the ARMv7 architecture. > > These days it requires ARMv8, because we dropped 32-bit host > support, and all 64-bit host CPUs are v8. Oh, this comment is about the target, to justify it is pointless to include pre-v7 target cpus/machines in a KVM-only binary. I'll update as: "KVM requires the target cpu based on (at least) the ARMv7 architecture." Is that OK? Thanks, Phil. From MAILER-DAEMON Sat Jan 30 13:42:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5vCl-00011k-Cq for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 13:42:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5vCk-00011e-GU for qemu-arm@nongnu.org; Sat, 30 Jan 2021 13:42:42 -0500 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]:40310) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5vCg-0006WC-Sj for qemu-arm@nongnu.org; Sat, 30 Jan 2021 13:42:42 -0500 Received: by mail-io1-xd2c.google.com with SMTP id n2so12995242iom.7 for ; Sat, 30 Jan 2021 10:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=modwiz-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7xN3NWujt0MZ4nsv093+6CZQ4eRij5kiYXwtNg1RWPc=; b=PdIoDgAQ4rA9KCjUsfE2HvoJ9FJv9RY2tPeFVbHmrrMr74SihQhLuOq8TxWCNRidAD zhu+nPVScrV4mM+U+uARN5A6cTAQxXwMcq1SONj70pVGwk6yg2hX/HBWGXGtX1m5dnHo PkCwIn/8DYEZflLO5FPgLBdN2UUU+TQ/ydvhJ+sMauskJE6qLaMhedKGmGPnxPpdfCf8 mYsClvyvH9NdiDtDfcF1ZJLuvRYBYrJB/nz93L7o7pPRR4xgd9IFVavGmfjizQUXVDMm HdDuTdg/8M1ruNJtUXstxNJX+JpNqtRJslCnjImizdgJZCWz9lH2Yfz3dKbkA/mh5zj0 evnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7xN3NWujt0MZ4nsv093+6CZQ4eRij5kiYXwtNg1RWPc=; b=CiNp8QC/siYL0jyhgqdETWzZuwUrAaBXrRQIAEEbyoNE91bMasB8DXgr3EJMZyYrYg epSMKoba2ImmT4pR6qY0xFa2aIvdtSXqFHc/8ZsvUr1uC9T3K1h8lHHAZOhmEODbGAnj 3+gvWtjAXgXazPmZnVsqy0W8PoENiDyXNkRQxazcJIC35zKTzdVap277OjBNrR6tY87Z sKRMTY2CAxlq8EtfoJWP9yVYNJdNrskR7PHpGHf0Ubtv5wryIZHOKE5e3gB4mQj+lOvZ Jyrqw1zoYAobNLQ7S6fcLR/UuBNEiSKVVnyyygXUOXATFPkwaMLtu5q0FskKUanpuKSr Zphg== X-Gm-Message-State: AOAM53135uRT2TG5CF9z6boWa7oDGLNkd4vUbTg9DeB3yVJfg0ckj36W u58fF/7uSDh8lrjhurCPIrMjcQ== X-Google-Smtp-Source: ABdhPJxfE9/GMp7qpg8557Tvt8pHTUEI+jvAkCa2ybrT5cz7viIb7kkD+2mTBlObYL2zs8WOZkhhYA== X-Received: by 2002:a05:6638:138e:: with SMTP id w14mr8281564jad.98.1612032153675; Sat, 30 Jan 2021 10:42:33 -0800 (PST) Received: from localhost.localdomain (c-98-223-182-45.hsd1.il.comcast.net. [98.223.182.45]) by smtp.gmail.com with ESMTPSA id n193sm5662253iod.21.2021.01.30.10.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Jan 2021 10:42:33 -0800 (PST) From: Iris Johnson To: Cc: Iris Johnson , Igor Mitsyanko , Peter Maydell , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , qemu-arm@nongnu.org (open list:Exynos), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH] hw/char/exynos4210_uart: Fix missing call to report ready for input Date: Sat, 30 Jan 2021 18:40:17 +0000 Message-Id: <20210130184016.1787097-1-iris@modwiz.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::d2c; envelope-from=iris@modwiz.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 18:42:42 -0000 When the frontend device has no space for a read the fd is removed from polling to allow time for the guest to read and clear the buffer. Without the call to qemu_chr_fe_accept_input(), the poll will not be broken out of when the guest has cleared the buffer causing significant IO delays that get worse with smaller buffers. Buglink: https://bugs.launchpad.net/qemu/+bug/1913341 Signed-off-by: Iris Johnson --- hw/char/exynos4210_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index 6361df2ad3..51ba862d0b 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -519,6 +519,7 @@ static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; res = s->reg[I_(URXH)]; } + qemu_chr_fe_accept_input(&s->chr); exynos4210_uart_update_dmabusy(s); trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset), res); -- 2.25.1 From MAILER-DAEMON Sat Jan 30 13:54:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5vOX-0005w0-S7 for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 13:54:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5vOV-0005r1-Ly for qemu-arm@nongnu.org; Sat, 30 Jan 2021 13:54:51 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:35540) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5vOU-0003SV-5i for qemu-arm@nongnu.org; Sat, 30 Jan 2021 13:54:51 -0500 Received: by mail-ej1-x62b.google.com with SMTP id ox12so18042483ejb.2 for ; Sat, 30 Jan 2021 10:54:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=oXtPVE2IbtRRYCpvUtiVFQgbW5mh8YjoQMknIuSaeAc=; b=b1rE5reO+/ylwUvWHDQ6gFBD1ZMLvjmBVj7z6iHZEtOIrt85KafbIsrJiUTFMjgkMv EO239Ch7/2vVc0sITyLPdJw79Y+DCrMrThTp86B/tp4yto0D8J7B2oagD+F+VrSA1ciu I5poKTCsVbT2lrqibfeCp+VtxN5qYq2t6UgtTQzNfWSNTueccgRu9w7NSq60zrXpqF00 E+yG6zYuZ31QrSrfccmyDg4uryatxiI+pF7o1OOGRbojYu5vd9czNJSN+4ROCzG5yfv6 OGKU/10X2cC0Qells3y39Jm9YWDAtsEjcdG3fj0bTfhFF3WPV5yrPTu2+mgt4gwFPh4s n7BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=oXtPVE2IbtRRYCpvUtiVFQgbW5mh8YjoQMknIuSaeAc=; b=VvHB34F7D0WahsqM19akKNA4UU5s+A2nYrMVtzooZqkUfF+b3KsXLc5yQ62Ag9RFZB rZ7ccTp77ajkjNnoJeejpBRgWzVqURTCvIXnxQ7tVzHx5HSzrVk3FRhXNMVbP/uxnNDy Adj5MOjlvLmb6RCJOdeIiuuPqNjKNdB/O9qY3L5pgIMBUQTGkKCWaUP9OFU6I2tt3lBe lZqOJK5+/l1RIbg+Qcb2APW039nueC/pDB5E8Xvod1Q/JiqMvzMv5ilwWySRkWAnK7yT ToAZZbVoSi4YEdXluh884qMDtU1ffSSL9FQHBb8h9w38qkzuPhkY8paGXi2XHHPzw4TT 5Pig== X-Gm-Message-State: AOAM532PLD02rgVUqbSz5AS+/s+TOlkQ46trt10DYBzItmdr15eohsTb DNEpgg8lkkyhA4D0YiouGhWb09N+gCIqQr7a2Mcidw== X-Google-Smtp-Source: ABdhPJwo7gvPhPJtvirAJL3BBx+tVDxaTzL7yXGFz6XeyRrStm+3laD7Nmfgez99qF2/kAXH8/BrkdUPl35U/QOjqxg= X-Received: by 2002:a17:906:b215:: with SMTP id p21mr10088000ejz.407.1612032888158; Sat, 30 Jan 2021 10:54:48 -0800 (PST) MIME-Version: 1.0 References: <20210130015227.4071332-1-f4bug@amsat.org> <20210130015227.4071332-4-f4bug@amsat.org> <2871f7db-fe0a-51d6-312d-6d05ffa281a3@amsat.org> In-Reply-To: <2871f7db-fe0a-51d6-312d-6d05ffa281a3@amsat.org> From: Peter Maydell Date: Sat, 30 Jan 2021 18:54:37 +0000 Message-ID: Subject: Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Richard Henderson , kvm-devel , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Richard Henderson , Claudio Fontana , =?UTF-8?B?QWxleCBCZW5uw6ll?= , qemu-arm Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 18:54:52 -0000 On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daud=C3=A9 = wrote: > > Hi Peter, > > On 1/30/21 4:37 PM, Peter Maydell wrote: > > On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daud=C3=A9 wrote: > >> > >> KVM requires a cpu based on (at least) the ARMv7 architecture. > > > > These days it requires ARMv8, because we dropped 32-bit host > > support, and all 64-bit host CPUs are v8. > > Oh, this comment is about the target, to justify it is pointless to > include pre-v7 target cpus/machines in a KVM-only binary. > > I'll update as: > > "KVM requires the target cpu based on (at least) the ARMv7 > architecture." KVM requires the target CPU to be at least ARMv8, because we only support the "host" cpu type, and all KVM host CPUs are v8, which means you can't pass a v7 CPU as the target CPU. (This used to not be true when we still supported running KVM on a v7 CPU like the Cortex-A15, in which case you could pass it to the guest.) thanks -- PMM From MAILER-DAEMON Sat Jan 30 14:04:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l5vY6-0002c1-MB for mharc-qemu-arm@gnu.org; Sat, 30 Jan 2021 14:04:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l5vY5-0002bI-At for qemu-arm@nongnu.org; Sat, 30 Jan 2021 14:04:45 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:41124) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l5vY1-0007zm-Ms for qemu-arm@nongnu.org; Sat, 30 Jan 2021 14:04:45 -0500 Received: by mail-ed1-x532.google.com with SMTP id s5so1512548edw.8 for ; Sat, 30 Jan 2021 11:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=modwiz-com.20150623.gappssmtp.com; s=20150623; h=mime-version:from:date:message-id:subject:to:cc; bh=g9ov0VVs1sCdcd4GwD2Rn1yejaNO5CuETR3oztC0Xkg=; b=CIA8NvEulkN+vLw83eXXsBwWIUXXqW/Jpc4iD01+5FBwHdK2T5VfjHyP+Eel4YI+H8 JyXiJPCHNWsy2+J9t73XriTuRvntpXPDn2psNuxGy+UHs+ZiRFq53cadFtxKiogZfxgf +m6Z+X8ThmF9W/97AQAP2l9V4xojFyH+XWGCeDAMXWLrH39EZav0J4BUVfPBQ2Uz9ii0 E2yn8EfRWja9XAC5wCWphCOBw/h70alSLIF6rxYWq1gdxKOwLbvRsZ1DyjvIDgfwOYdA 2RbCFoBrlNi3OP7cWduVsnBoRmVgizuCBq+gdCItCQLuysNZgo3AMmuM2BoaQliWAp+X jy0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=g9ov0VVs1sCdcd4GwD2Rn1yejaNO5CuETR3oztC0Xkg=; b=Js+n84KM+ZYM/qzKovL+oFa8RmnLL3i98b9b8nP5dUo9OYhBNRSEKayRAZntVkbBdp gM/t/q15qPn503hTk8xgkDfHDFUlunKCGH1YpmgrW54nOr1jpW9wY96Rq/Llc+MZdQbi 6TT81AuB/AX23Twpv0arji4TloErWgwcGLK7OlzwM2knJRZ1HPO62dyq0gfdNk7TW/XK D5zSRRjYt3xiTeLsSnhTtPYigkzCyffnqU5BbCI3NEh0I7AHdtaRu64CA0xmkmIaivMA 2H9CUuRX7cc1JqAwHxggp2S/lzMJslJfn6YPrMltcbsPMJyIPLZArGAkXRrmWWtgOOUg XX/Q== X-Gm-Message-State: AOAM533Ao+Wv9e9qMKPFeBm/aLvlG5iEsvD56nR8aut3nNy0tJ6/KCia Udh3uqsd1pVN/jgt5x9KT7za+3zSXEo2/dmu/wm/dahZ7fpj9YqfBh8= X-Google-Smtp-Source: ABdhPJzgGTWh2a39lrSBTZbk0IOWJW/yztogMklO1WEmrblNo0ijn5vT5vlpOseaCogKyqEPjKTkSDgWiGqoOOi6FAs= X-Received: by 2002:a05:6402:13c8:: with SMTP id a8mr11164355edx.191.1612033479865; Sat, 30 Jan 2021 11:04:39 -0800 (PST) MIME-Version: 1.0 From: Iris Johnson Date: Sat, 30 Jan 2021 13:04:28 -0600 Message-ID: Subject: Question: Adding emulated machine support for Apple M1 mac To: QEMU Arm Cc: QEMU devel Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::532; envelope-from=iris@modwiz.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jan 2021 19:04:45 -0000 Hi all, In light of attempts to get Linux bootstrapped on the new M1 macs I've been working on supporting them in QEMU as a new machine type, I think this has benefits for testing and potentially there is desire for an M1 Mac running QEMU to natively support emulating an M1 Mac and potentially booting OS X under such a setup (although this is not something I can personally test). Adding a new machine type is hardly a straightforward process though and there's a lot of paths the existing code takes that aren't ideal. Constructing the memory map and how to handle initialization of the hardware before jumping into code that would expect to be loaded from firmware bootloaders are two examples of cases that are handled in a multitude of different ways. I'm looking for some feedback on the possible approaches, you can find the current progress of my work on what might (eventually) turn into a potential patch adding support here: https://github.com/modwizcode/qemu/tree/add_M1_test. Currently I'm focused on booting m1n1 (https://github.com/AsahiLinux/m1n1/), a sort of linux loader, with the goal to have enough support to not need any qemu specific m1n1 patches to handle qemu differences. This goal has been achieved well enough to start work on basic framebuffer and interrupt controller implementation. The most objectionable area at the moment is that I currently just modify the cortex-a72 to stub out a few Apple M1 specific MSRs, obviously a real coretype for the M1 should be added (probably two to account for differences between the two types of cores it has). Currently I have an "AppleM1SoC" object that will hold all the peripherals, and then I add a simple machine definition called "apple-m1" that (once more information is available) should simulate the hardware environment of an M1 based mac mini. Feedback would be appreciated on desire for this, implementation suggestions, critiques (although there's some cleanup I'm saving for later once I've decided on a more correct approach) Thanks Iris Johnson From MAILER-DAEMON Sun Jan 31 05:34:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6A3X-00069E-1V for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:34:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6A3V-00068e-Dt; Sun, 31 Jan 2021 05:34:09 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42503) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6A3T-0005xO-Or; Sun, 31 Jan 2021 05:34:09 -0500 Received: by mail-wr1-x429.google.com with SMTP id c4so10680373wru.9; Sun, 31 Jan 2021 02:34:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TlmiqcRxjsssX02CFLK39hXDZo97/1WckvKX+iMFcz0=; b=kSTX42T1U/H9fd10+d/dkvU1dXVdNY0QUyhraMC9ZGsACTJcdhvGup+5c/9cOesDIQ J7FzvWKcXme9bxYM9wL9iQoN+jvqgF9TG1E7+MMPLATDFm1iQLyUK/BbX9h7exHeKIzc FNcRyjVBPnIQDrBKvvpyGrE81WUzN97AwJN5vuAkc1kxd9oxy1PumKycrS+hPh3NHESU AbmZTOynGsCLGX8F4kYiV2fnY0dzsc1Dn4YE5xwwK6rn42CGO/tYVghoGQk+3ql5vOGV 76O1T6vysOemodgGBII/aTeb9RPE7urJUWX7U3d9TtMWgI7DhflvwNCkKI1j+hMDlvAL x28Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=TlmiqcRxjsssX02CFLK39hXDZo97/1WckvKX+iMFcz0=; b=Doyalt7TDdSXKVchXjiUgaugjiXL4dA8+dKb3L1AlNjTfHIZzmdvEEVL5xmVyniLTj XDA1YafwvKL+lVSJrlowtEbilb3C2+VjAYGi/5yezAEtfycsDLQ0FWe9AtHImc/b4kET 7GthT4/0dTZdCs0b4+CltAsv1bxClE87oNXctiuqE6Ij0cvRxNmfd2+uglxisze72ohM 54IGTdbK/ZybjFYrInbcdeMMbK6gGzY6vS9yT+wvJQPnQ5xUzyA8Py7IZrG9qfVAlqOQ d/NAKvJPldczR70+fcueWJkwMUzSHRZd9nYoPHrNv93Ku/LinyR/VQ5vCqtu8585wKr3 nB5g== X-Gm-Message-State: AOAM531cMf6wYh5ISc3WkSF4MkR011Oyt7bkvd5lZuUVprhqby5FsA2T EK2B/qO1Jv45W9RmvTqStghVxGPoGI0= X-Google-Smtp-Source: ABdhPJwNdu6avs5DDRRIsR1uCCk31tFyCa0LFR40Mdyrio5YaoF8jLmFA3JWLnMy2jhYhBoQUegTTw== X-Received: by 2002:a5d:4b0b:: with SMTP id v11mr12861857wrq.226.1612089244724; Sun, 31 Jan 2021 02:34:04 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id z185sm19143322wmb.0.2021.01.31.02.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:34:03 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Li Qiang , Peter Maydell , Darren Kenny , qemu-arm@nongnu.org, Luc Michel , "Edgar E . Iglesias" , Prasad J Pandit , Sai Pavan Boddu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Alexander Bulekov Subject: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register Date: Sun, 31 Jan 2021 11:34:01 +0100 Message-Id: <20210131103401.217160-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:34:09 -0000 Per the ARM Generic Interrupt Controller Architecture specification (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, not 10: - 4.3 Distributor register descriptions - 4.3.15 Software Generated Interrupt Register, GICD_SG - Table 4-21 GICD_SGIR bit assignments The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. Correct the irq mask to fix an undefined behavior (which eventually lead to a heap-buffer-overflow, see [Buglink]): $ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio [I 1612088147.116987] OPENED [R +0.278293] writel 0x8000f00 0xff4affb0 ../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]' SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13 Cc: qemu-stable@nongnu.org Fixes: 9ee6e8bb853 ("ARMv7 support.") Buglink: https://bugs.launchpad.net/qemu/+bug/1913916 Reported-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé --- Isnt it worth a CVE to help distributions track backports? --- hw/intc/arm_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index af41e2fb448..75316329516 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1476,7 +1476,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int target_cpu; cpu = gic_get_current_cpu(s); - irq = value & 0x3ff; + irq = value & 0xf; switch ((value >> 24) & 3) { case 0: mask = (value >> 16) & ALL_CPU_MASK; -- 2.26.2 From MAILER-DAEMON Sun Jan 31 05:43:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ACK-0008Uq-6h for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ACE-0008UL-FC; Sun, 31 Jan 2021 05:43:10 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ACC-0001Ol-RR; Sun, 31 Jan 2021 05:43:10 -0500 Received: by mail-wr1-x433.google.com with SMTP id g10so13405512wrx.1; Sun, 31 Jan 2021 02:43:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=QxB7I+r8+V4xA23p+DNTd+vmCSZ/WgkR+HXPJJCiVFg=; b=kKco8a5xVmIoRQNh4Gaz1exxGF39CTNEQsqic2Z85/xjkyaDO1+41bGtQef0/WCAZC 2JCvt0sKU2I/LxtmuHMQuSNnjjFel29+sTL0iHUEqw1RGJxVjokMX0VkfAJySfXKFeKu O97iIPqFQcGWzk3myqJnXn5p1iS8ccmqH8aLDxZ/93K5ryPChR6Nk6WRmCvk1pOXzXyW cnqq1Oezyce0CGjyCHdt2JfT8yu6r96V9A8FMNKZHbHnN4A4WKqP4fGxEcgouWUAb0sn 2g4/013DKuGlonFz1OkBFna7vaIgP8m4kKNP3CgPlLwc9difVZxw0f05PuOQYZ+Z9BcH FN1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=QxB7I+r8+V4xA23p+DNTd+vmCSZ/WgkR+HXPJJCiVFg=; b=MkdSwTkkY4qsQnZ68VhVaFa431gdSNKwLeb64CUfA768+Im8Pr/jXRsbMS1JO0mOZs 4lz8XNldD4EFWLm6OPZzM79NWp2B78hNc/KmEjxkYA4OYyriAOwDxl5m61vQ1G8P0dAD PPXoh9d8XBC7zZ1Wvn9PnKaEbHKCStg93l3qMGgJ/BpchTMJkC4H99fCvJIJosXhUtxk FAvV0KAYYs8vUlieJWY4yxPrzQzo3SF4gFQuP1v+Oi8h6JaJPvzFTtoThlRGVohyc3nv 8D8WnS5HLnRy5UbnIGntheyHz+HZ6+ztlQc/iZIhtf4oSKG3/31E39Fk6ukqfR0Q3Q2Y cRAA== X-Gm-Message-State: AOAM530lxXlqDfFjNkFksrgxs3rvFhbo6Q+BU7IE/6Ft4dy8X7xuyop0 zChe0uUEu/7Kg43xkqKswMs= X-Google-Smtp-Source: ABdhPJxf15RYUCFfHcDBrg+oru1D4DK/U6JAuNFA1H4N61utPKYmCHXCAn18f5Dvpb9FjtjRjt/DHA== X-Received: by 2002:adf:9523:: with SMTP id 32mr13561898wrs.361.1612089786157; Sun, 31 Jan 2021 02:43:06 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id m12sm17978586wmc.10.2021.01.31.02.43.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 02:43:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register To: qemu-devel@nongnu.org Cc: "Edgar E . Iglesias" , Peter Maydell , Alexander Bulekov , Sai Pavan Boddu , qemu-stable@nongnu.org, Li Qiang , Prasad J Pandit , Darren Kenny , qemu-arm@nongnu.org, Luc Michel References: <20210131103401.217160-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <3a94e327-0454-bf43-552a-1c84407e1d7d@amsat.org> Date: Sun, 31 Jan 2021 11:43:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131103401.217160-1-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:43:10 -0000 On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: > Per the ARM Generic Interrupt Controller Architecture specification > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, > not 10: > > - 4.3 Distributor register descriptions > - 4.3.15 Software Generated Interrupt Register, GICD_SG > > - Table 4-21 GICD_SGIR bit assignments > > The Interrupt ID of the SGI to forward to the specified CPU > interfaces. The value of this field is the Interrupt ID, in > the range 0-15, for example a value of 0b0011 specifies > Interrupt ID 3. > > Correct the irq mask to fix an undefined behavior (which eventually > lead to a heap-buffer-overflow, see [Buglink]): > > $ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio > [I 1612088147.116987] OPENED > [R +0.278293] writel 0x8000f00 0xff4affb0 > ../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]' > SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13 > > Cc: qemu-stable@nongnu.org > Fixes: 9ee6e8bb853 ("ARMv7 support.") > Buglink: https://bugs.launchpad.net/qemu/+bug/1913916 Also: Buglink: https://bugs.launchpad.net/qemu/+bug/1913917 > Reported-by: Alexander Bulekov > Signed-off-by: Philippe Mathieu-Daudé > --- > Isnt it worth a CVE to help distributions track backports? > --- > hw/intc/arm_gic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index af41e2fb448..75316329516 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -1476,7 +1476,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, > int target_cpu; > > cpu = gic_get_current_cpu(s); > - irq = value & 0x3ff; > + irq = value & 0xf; > switch ((value >> 24) & 3) { > case 0: > mask = (value >> 16) & ALL_CPU_MASK; > From MAILER-DAEMON Sun Jan 31 05:59:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AS0-0006mq-Gc for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57122) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ARx-0006l7-Ch; Sun, 31 Jan 2021 05:59:25 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:37244) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ARv-0000Eu-V5; Sun, 31 Jan 2021 05:59:25 -0500 Received: by mail-wr1-x42e.google.com with SMTP id v15so13448794wrx.4; Sun, 31 Jan 2021 02:59:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=xn8k8+mGs9XJdl/4elQ+sUFuX+oW3atWPyLWH373rMI=; b=nM060cCkw60FS6adkEsjm3lKDTGFfz4+RKlgj/ylpZaonfEWY6Rx609zraCwzwwK2T HPfrpMeqWr1Y1QLap7GTh8BAIlRHkseHhnHKFhhdn+mxzlurw/2vcvffpjmkI4YKdHg9 WDS5TowWSebiPHdNexjEe1MhyoHGGEXPerputJ66f41AVkjTxHf6bibcXazKmKIqffnV ZxAZUF1ueXNKH2yp63MxG66kQwC/IpyV+ZjU5Lu4Kifqx5m7Sc57xnWpiz4Lw3LUL43j g88H8nzO35YxiMxmei7y1Awlmy7h1jjyRi8EN6BtDoT+cTYwBnUVxjAWC2z0/Z907qcA rljQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=xn8k8+mGs9XJdl/4elQ+sUFuX+oW3atWPyLWH373rMI=; b=oR2vsDrQ8M9uV8OkDMJyI5bxXyxqPX4HJUmvABZ4omGOpxgNjissMKeElg22jY6vra nwa9DYdpd1R2Crc5z0xVNS8pau6mAjOXvg+Xpg7jQ2v9XzDtthrgQWFWOYwKl+RB3ro7 X8REgIlrameBJgZNlX/7rAzLwcPloh3aUPN0bVxiXBllcxAfC/sW4gHOAUk5KatNGlSm UUaXm1Hrly58z6tcWHUQJiu7J1qcOF69n8HgSV0k+Wvk2h5C5/oAQ61Qz870K0N5E/fc w3LmBkJhlDdfE/2vTN2VqzD62M2ovGVCYSS08y+X7dWES0Ta4TczweevLdbs4lrm7SsJ tBiQ== X-Gm-Message-State: AOAM532PC5a3Oi+6Wig2q+xhIX4K1zylB7S64uY/6/hCokVrOrrdFgDG i91Q81dnjzsxRzFdyp65enXe5WL78i8= X-Google-Smtp-Source: ABdhPJyyWXXZViJFnLDcTp7MOL5uWWhn/S/Qw/3TncbERWFV8WPomSMqkL8W2fqLADEh3l+5GffpEg== X-Received: by 2002:a5d:68c6:: with SMTP id p6mr13163198wrw.332.1612090761631; Sun, 31 Jan 2021 02:59:21 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id v25sm18141225wmh.4.2021.01.31.02.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 0/7] hw/arm: Misc trivial fixes/cleanups Date: Sun, 31 Jan 2021 11:59:11 +0100 Message-Id: <20210131105918.228787-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:26 -0000 Trivial bugfixes and cleanup patches noticed while rebasing=0D my "Support disabling TCG on ARM (part 2)" series.=0D =0D Since v1:=0D - added patches to remove 64-bit specific features on 32-bit build.=0D =0D Philippe Mathieu-Daud=C3=A9 (7):=0D hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ=0D hw/arm/exynos4210: Add missing dependency on OR_IRQ=0D hw/arm/xlnx-versal: Versal SoC requires ZDMA=0D hw/arm/virt: Do not include 64-bit CPUs in 32-bit build=0D hw/arm/sbsa-ref: Restrict SBSA-ref board to 64-bit build=0D hw/arm/xlnx-zcu102: Restrict ZynqMP ZCU102 board to 64-bit build=0D hw/arm: Display CPU type in machine description=0D =0D hw/arm/digic_boards.c | 2 +-=0D hw/arm/microbit.c | 2 +-=0D hw/arm/netduino2.c | 2 +-=0D hw/arm/netduinoplus2.c | 2 +-=0D hw/arm/orangepi.c | 2 +-=0D hw/arm/stellaris.c | 4 ++--=0D hw/arm/virt.c | 2 ++=0D hw/arm/Kconfig | 4 ++++=0D hw/arm/meson.build | 4 ++--=0D hw/dma/Kconfig | 3 +++=0D hw/dma/meson.build | 2 +-=0D 11 files changed, 19 insertions(+), 10 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 05:59:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AS8-0006tG-Mq for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AS4-0006qY-7a; Sun, 31 Jan 2021 05:59:32 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:38078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AS1-0000GF-Ff; Sun, 31 Jan 2021 05:59:30 -0500 Received: by mail-wm1-x32a.google.com with SMTP id y187so10699677wmd.3; Sun, 31 Jan 2021 02:59:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=FBl+lcqUTya8HKBOBUjNAvbvJrnnQb2bBX6sxXCl1at2OWMR//TOqWUCih+ZBTl3Xi xTxv4V/T+AiwRAu3GeInds6GetaqebvE1Dd0u5YodgGI48B2/UmPZj2mhIkhOyJH2X8e N1DaicF/faZKL84596Vh3b/W1rX9uJn4SnsPssPsl0IkzI3jUqgbzeiD2jl43bhz9Fgk A9IXjeD330azawEpzc6mkoUKCn0+6A5KnnZ6zQOzvfxi/Rf5aSskVIbeHcVfajwj7IPq yYohMb+h3/M74a3nH5kE2AcoDETax5XPxnkxsYIqvdp9FYWNrsItyXgfApbM2t3WI6jl IbsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=kq6OjqxdUTaQjyXFKe3crQdQlSqjWRzzkyFlydvnMIlNGF28E4hCDTH6BG9et7rpq/ 77Nqv9AfOyEImjSzC7QUkV3htO3sUbszwZdRfWfIJEfziVOlZNN0w3LLtrx6jBK8wb+U TJVmgTzHTog0/1V2P3Cw99Wf1FVZXVGm8eCDYSJ41M/EDdTiI2+CCzNyBB9zcq+Zt+e/ ZVlRKjQ0iZJGsk0SyUYZRzxxhsGWWjChm9PXWtd9rzNOTGk8zkqPei4gRWemug/4y/Fg aA7DnDXpTCYOrM0Ub4wq9I69pPTGHHSivFkAbQEjwEe1T8ZV3kleBBatkdyaWM1HXe5F uI+w== X-Gm-Message-State: AOAM532x6mcEwWgLsxWFjBY1dIGWfRogGHH/v37GER98KyeR32TtFJVW kNkvcWsVLCEj3mpCpsQyc01jjZgN8VE= X-Google-Smtp-Source: ABdhPJxqYOpHB+boItZFAvhV6fqD5vG8CqOeRrEFqjLo/vhS4KwyQTd/ApVwIoRo88AouJIe9L0mlA== X-Received: by 2002:a1c:6402:: with SMTP id y2mr10534889wmb.43.1612090767213; Sun, 31 Jan 2021 02:59:27 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id h18sm22581661wru.65.2021.01.31.02.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/7] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Date: Sun, 31 Jan 2021 11:59:12 +0100 Message-Id: <20210131105918.228787-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:32 -0000 The STM32F405 SoC uses an OR gate on its ADC IRQs. Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC") Signed-off-by: Philippe Mathieu-Daudé --- Cc: alistair@alistair23.me --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 13cc42dcc84..a320a124855 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -336,6 +336,7 @@ config STM32F205_SOC config STM32F405_SOC bool select ARM_V7M + select OR_IRQ select STM32F4XX_SYSCFG select STM32F4XX_EXTI -- 2.26.2 From MAILER-DAEMON Sun Jan 31 05:59:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ASC-0006z1-9h for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AS7-0006t1-Sa; Sun, 31 Jan 2021 05:59:36 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AS6-0000IW-Hw; Sun, 31 Jan 2021 05:59:35 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m2so10188410wmm.1; Sun, 31 Jan 2021 02:59:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jtbqU34AXRgK7JucvFyMPpEvpdP/cEkbkCwJzoZsw+I=; b=vFB1SLLOVA8z1esZfr+efHXGjtpbRDRKqxEr0+XiTMYueGRRO8M/pprq+Ef4/KsxHa joocEje6xS3Gk3xC6E30gOMRzrg25mC0cajUE3Oi70BtKoSyMyAgZXUDlF7GBVlNCTq9 61Jna5sD+OuCCDAhBOrVn2jnnPRl3UW7giw3RR2JTeKFdDmda3b6dX+IBp/iCXfmzyrh qIaHGIih4ZZWSZ6qR98Bt+TagXa1f8hhSldfEor7JpNqQXRrgu+ys/aeMbrXyl9T5AYD md2NxvIiSejyxUSLM4Ub1722iSSAsNgCwb7WnJ9kgpk8ed/CM436mCELPCr7/Y9JcS+5 HzAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jtbqU34AXRgK7JucvFyMPpEvpdP/cEkbkCwJzoZsw+I=; b=Ca37G05hRpK3QJotXzcvu/+WSvrHZDDt3O7pvdpBP7ItgZJbaX3x9gt5NKz2T384XK 3TY4oWBonS+fOibt2r/eV1bbAfb4Wr4ZHv7SomU3FxW9akv2JaWZhOULSEexeeJiRWLj T2kEWNqSjZAOESzoVolUZFmzdZwKNcNg8YtSOaNrWvrnJeylUombvnSH0wk8wRbvdLNs vM1YuUcx8ThS6q1ISiLo6Vqc0GQ6hMALxmpYFwXHfQsJgnKBI4waSdyl70M5aa4Iwzs3 ZML3KCoiWlIf1bqT++TWJ3RPES+QPP9e9buQRFAkAkVjcff7FyVRNkC0wi7NUeonMHI/ 6J7A== X-Gm-Message-State: AOAM530O/7FoC3Zgc+XRusY2/dc1fV1fpBZ2E4vQ5gV+heHy2pkesikD lLc678xPUeTDs2cR5QHIoUuKhSOfdcU= X-Google-Smtp-Source: ABdhPJz3rL6GTv4/ZBU2bl7Dm4ct0pyORHXhWH4J37W9yNXtege8fVkTHrzGefx6WHdJKlLLjnHC0g== X-Received: by 2002:a1c:9d08:: with SMTP id g8mr10683440wme.112.1612090772413; Sun, 31 Jan 2021 02:59:32 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id c18sm27417714wmk.0.2021.01.31.02.59.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mitsyanko Subject: [PATCH v2 2/7] hw/arm/exynos4210: Add missing dependency on OR_IRQ Date: Sun, 31 Jan 2021 11:59:13 +0100 Message-Id: <20210131105918.228787-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:38 -0000 The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines. Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization") Signed-off-by: Philippe Mathieu-Daudé --- Cc: Igor Mitsyanko --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a320a124855..223016bb4e8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -52,6 +52,7 @@ config EXYNOS4 select PTIMER select SDHCI select USB_EHCI_SYSBUS + select OR_IRQ config HIGHBANK bool -- 2.26.2 From MAILER-DAEMON Sun Jan 31 05:59:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ASF-00078f-G7 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ASE-000752-7J; Sun, 31 Jan 2021 05:59:42 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:40793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ASB-0000Kn-S2; Sun, 31 Jan 2021 05:59:41 -0500 Received: by mail-wm1-x331.google.com with SMTP id c127so10676571wmf.5; Sun, 31 Jan 2021 02:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rhmZGh+lLqk8y/kN/amckU6sgJUtIz3ObCH4gQGYjHc=; b=VdrvC+Wfqci72UDt7L8R8zMk3X+PU6jgBeh7dDJgh8GPVt9Dhat48Cu/EukJAsfawO SARDR7W2ZMfcP+5j3FrTXZ74B3y4pG13g32phI6Xs2Rnr8k53VYVIebIZWSPn6J+i60L wUJApDAa/m0I7kXEWm2xlmRlYyHqcXym4ODMGR6yz3b4T/6judTUaOxhZZ0rU5KO7ocN UdaSx4/rmM3qzS4ScMIpiYhYOpUx1rNvV16KdKdOyn1//KSWeLwxSUXYcKfw8zxQ7rGK JpJaOlfXNZHDSeeGLUWMleruP6ujuKIw+bBEPoLN0p6dDu2u4BdOPrTnFYaoHzno2Irv Va9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rhmZGh+lLqk8y/kN/amckU6sgJUtIz3ObCH4gQGYjHc=; b=YJH18qPoq0hjGg+74WbcFombFGR+oxnnKqL0IMZHj+QEGvOi5fhWZk/YNuALGpdZRx 6Q9yXr/GiDbbB7kNkLRahhFlpH3jvOPXUMZ5lsuAS2fePkh5v+HFDsUOv32U/5tF4wY8 DKlmy4XRe84kfZkKiDoHhoig5uUZZNIE/iT3FM5TRc5r/PPnFVVcpS299T3z9+JHqLf6 rHkjRyyywl0VKMOnnMe/45Av/W8yfTnLln8FihdGaBnoSJKfO4HPszS/DJ4OYf2srPp+ YwBuWGFzELumY2eWEv7wXkxKg6sEUkemaxKDxOFvttLxa8NMBKmqqMUT0bjzU6GkYE8b a7Zw== X-Gm-Message-State: AOAM5316N4Tt0PneCoT+CnrO+Lm1SPzTyonffvVw1NN9M+bb/R8mr1uw bCTMIAfcGPuEk1B1KQ59OZQSxMlrE8M= X-Google-Smtp-Source: ABdhPJyCgwincAAHTuwt7n13FPHmZr2kJpz6qcOW0mEG38XTaG2SXdOUjVex0Q/jy2LbXmtB7SKA5Q== X-Received: by 2002:a1c:4e05:: with SMTP id g5mr10841953wmh.105.1612090777586; Sun, 31 Jan 2021 02:59:37 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id h207sm15597265wme.18.2021.01.31.02.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v2 3/7] hw/arm/xlnx-versal: Versal SoC requires ZDMA Date: Sun, 31 Jan 2021 11:59:14 +0100 Message-Id: <20210131105918.228787-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:42 -0000 The Versal SoC instantiates the TYPE_XLNX_ZDMA object in versal_create_admas(). Introduce the XLNX_ZDMA configuration and select it to fix: $ qemu-system-aarch64 -M xlnx-versal-virt ... qemu-system-aarch64: missing object type 'xlnx.zdma' Signed-off-by: Philippe Mathieu-Daudé --- Cc: Alistair Francis Cc: "Edgar E. Iglesias" --- hw/arm/Kconfig | 2 ++ hw/dma/Kconfig | 3 +++ hw/dma/meson.build | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 223016bb4e8..09298881f2f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -354,6 +354,7 @@ config XLNX_ZYNQMP_ARM select XILINX_AXI select XILINX_SPIPS select XLNX_ZYNQMP + select XLNX_ZDMA config XLNX_VERSAL bool @@ -362,6 +363,7 @@ config XLNX_VERSAL select CADENCE select VIRTIO_MMIO select UNIMP + select XLNX_ZDMA config NPCM7XX bool diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index d67492d36c1..5d6be1a7a7a 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -18,6 +18,9 @@ config ZYNQ_DEVCFG bool select REGISTER +config XLNX_ZDMA + bool + config STP2000 bool diff --git a/hw/dma/meson.build b/hw/dma/meson.build index b991d7698c7..47b4a7cb47b 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -9,7 +9,7 @@ softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_dma.c')) softmmu_ss.add(when: 'CONFIG_STP2000', if_true: files('sparc32_dma.c')) softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dpdma.c')) -softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZDMA', if_true: files('xlnx-zdma.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 05:59:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ASK-0007LO-4q for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ASI-0007H8-Gi; Sun, 31 Jan 2021 05:59:46 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45323) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ASH-0000OS-2n; Sun, 31 Jan 2021 05:59:46 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m13so13424182wro.12; Sun, 31 Jan 2021 02:59:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kNgfhjPiw9171QK4YrLx8o/lKUJjzdxMB/0DtTDI5HQ=; b=qDjRF+0ndp85DpCMzIrhPpNfUsERWwiOZI7/uwPu1ErC9b8kl/ykCGgGrxlg4a9Bsl r/WmJmM75cJjlvhWXh0UIhpVBgF0oD6uDr58SF2Okr0t66zghYgcVzpgkCF8QHBuA4jO Mn7yPQYM0WVm3BdD7T1O62lMHo0xJCJ1Hc2aC+GNc2CBMm/3s22fGi5zasxYyyobf9cR JQuMGg+QN6hM+mj8OWkmMOQqYXNkZchvWRFn9CmVPdqkPUixwym8ClHDKAzq0Z/Ji3yP jfhKHAT4XbxRuUR0jKfsjrKVR0f3BZOourWAM7IeuFtdhQm5ylugxrb8H/FizUKPFxyV dylg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kNgfhjPiw9171QK4YrLx8o/lKUJjzdxMB/0DtTDI5HQ=; b=i0fYjD3ehY5fslx2YVOuKnZ+Qhr2Fk72fBapSyHayL9RlubW+Upd6z8nZgzVH2l46a wJSDEUMyYwTNnraSfxC4a93/hpWDy3i2E3CWS8kNX/Da3AgqxPu3bl4Vf4Bm3OpiF+KC zjUDE4QHfuI2W56NXhAKJ/+gZpquSB0DFo2s34gCJslIKB/eFQsi7ROSjxFO7EnMgrfQ ism6fZhsv/nWeGPJnqlZjw8WgIciX1oMMrc17PtdoM5yBGxIBOC0nQ1cYqpMl1EXTSZA D0BewRuoKnJVRRkTDJ8aYwt8Rc5aj4wav6rTdj3RnfpGT5V8mzBdOT0ztXmFpF34bsAd IXZQ== X-Gm-Message-State: AOAM532eqtGQHnAjlyQv8XJmHz9wiAIBZuOG45spCCiN2pRAG1cTJDg6 iThSo/HS27sXMK4JLbpBbFZGuhaNZzc= X-Google-Smtp-Source: ABdhPJxZCR+z+3577SkyRfEhG9RwDBvB5aUFyHvyoZzotMTiYVS/VSwCAnlC1+7O2XFjRiGKzDAGng== X-Received: by 2002:adf:d1cb:: with SMTP id b11mr13397588wrd.118.1612090782910; Sun, 31 Jan 2021 02:59:42 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id b4sm22732200wrn.12.2021.01.31.02.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/7] hw/arm/virt: Do not include 64-bit CPUs in 32-bit build Date: Sun, 31 Jan 2021 11:59:15 +0100 Message-Id: <20210131105918.228787-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:47 -0000 Similarly to commit 210f47840dd, remove 64-bit CPUs (which have never been available on 32-bit build, see commit d14d42f19bf), to fix: $ make check-qtest-arm ... Running test qtest-arm/device-introspect-test missing object type 'cortex-a53-arm-cpu' Broken pipe ../tests/qtest/libqtest.c:181: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped) ERROR qtest-arm/device-introspect-test - too few tests run (expected 6, got 5) Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 399da734548..f0e9d7dd7d8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -199,9 +199,11 @@ static const int a15irqmap[] = { static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a7"), ARM_CPU_TYPE_NAME("cortex-a15"), +#ifdef TARGET_AARCH64 ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), +#endif /* TARGET_AARCH64 */ ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; -- 2.26.2 From MAILER-DAEMON Sun Jan 31 05:59:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AST-0007Wg-Rg for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 05:59:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ASO-0007Tl-Rh; Sun, 31 Jan 2021 05:59:52 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ASM-0000RF-H9; Sun, 31 Jan 2021 05:59:51 -0500 Received: by mail-wr1-x435.google.com with SMTP id s7so10436444wru.5; Sun, 31 Jan 2021 02:59:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZQoiucDIT4rSjEAY4ZuvMUxbDYBSZFNnjg1m60zIj8E=; b=ZeHl/siOlsjFxeuZteA5wZuvh/8NM5Q/I2spUpfS0cqhWQBuY9YgwoDKLtaByXCpsv b0l2aiuzFIE3GaVjOEgo5w3uUWtoV2d7riKMBtfaVJ1kcmy1TDVcMviNmkVSc50FUIl8 RrgEgL711CCUFwBVMPacRJlikKGRdcdCvhRV9rDU50nyaf9FSdjlo0LKOVx8NE/An6Yu 61dk28LtGZmnuUCSGprEiOQlo0nr4rlbWsq36QoRMDGQxhppeXn1SOKISZh6VVgpMrLE KLvyHAfmSA2gQpgT+pv2cCgdiaymRAn0USUG9JZhRcUFLTvmKSyFbU+nMMvDVbwRc+KV 5j9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZQoiucDIT4rSjEAY4ZuvMUxbDYBSZFNnjg1m60zIj8E=; b=eeGpwlW2OHj4k5qAGY5UBjSrVFvZnzEvbNEKkWfjX21z/FQ6xaOKstoyJgpuYdU4HM LxAk+Wem85tX+3N0pr4Gxjv7MLT2p6uSG/5U9G0Cp7Lx2HVahsekdzf2XuzIH+K6K3nD 1pGEv7IszrWP5zNUA5AkI0cMdxierXrx4cAkx4n1K3DbOisafhbxw8ofefSs00rraYNJ IkkR1XrkjnMul+W1vcWLgocrbbFW8mWeQyrenFtM4Kc89Zg9IxeAwCbqIjJdofq5Cm+7 ZDjtXpgcCni2+RQXL1xsISlejawbnwIDmHR/Dt74nP6WqsYhaFv54pe2hnko/cqyoSSQ tNmQ== X-Gm-Message-State: AOAM532CVrzRTsZNXYi+fRl3zfcR3ZgIfSUby5mOa26GUv+PM/WsxmAF eRfYZJNS38eIuqnxHOOCWrxAOAfV19I= X-Google-Smtp-Source: ABdhPJxVJS0UB3XcqSG9ZrQEJVPZb3WoW36SwkkysF0aEYp4+I6Gla/yX1CHAc/ThxX2mutk7FEQww== X-Received: by 2002:adf:e9cf:: with SMTP id l15mr13003391wrn.317.1612090788500; Sun, 31 Jan 2021 02:59:48 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id d5sm22464661wrs.21.2021.01.31.02.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Radoslaw Biernacki , Leif Lindholm Subject: [PATCH v2 5/7] hw/arm/sbsa-ref: Restrict SBSA-ref board to 64-bit build Date: Sun, 31 Jan 2021 11:59:16 +0100 Message-Id: <20210131105918.228787-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:54 -0000 The SBSA-ref board only use CPUs available in the 64-bit build, it is pointless to have it available in the 32-bit build. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Radoslaw Biernacki Cc: Leif Lindholm --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index be39117b9b6..059ff7382f2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -22,7 +22,7 @@ arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) -arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) +arm_ss.add(when: ['CONFIG_SBSA_REF', 'TARGET_AARCH64'], if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:00:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ASW-0007Yd-B2 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:00:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AST-0007WZ-Eg; Sun, 31 Jan 2021 05:59:57 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36255) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ASR-0000Sa-Tq; Sun, 31 Jan 2021 05:59:57 -0500 Received: by mail-wr1-x432.google.com with SMTP id 6so13415142wri.3; Sun, 31 Jan 2021 02:59:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K1GY+CrGWLNKk4VjoQeZ9qm50XB2sG8rwszIkKr7Jqk=; b=HPsDKu0PbsmcYP4UG3Hicq8cpwlvvUW4qW/gmBKuMHCa8hdR5bL3/3/ZItGtYFpsTT mDvvb8wUDAAFol6ZNlljn0WRYc71vICmgQSWEPPblanSXRHyByMWGN8PVZ0D2Iwrb3MH Dydwd2Biq4CiM0aK2oCwdIuJcRO4rGntZUSN8rFjxns9+5BZd+ZV8jl7NNdePkPzrJ7u 3BqApBC0GbyqgzPH6BL8XNcDiQlx7l3aPfOek8jsy4r15IRgnmhRBZ2Yg3GwkeHu+s1V MRNJcwztz135kzI0K1woinW1reEf7UaQSDbYD/vaVGOqcwa89Bezua6K1YCs/4vgZJCH MfQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=K1GY+CrGWLNKk4VjoQeZ9qm50XB2sG8rwszIkKr7Jqk=; b=eij4ihk9U6Np5/h5YLSOXtQRBESG7DmwFXEHBUiApkrcoofOCVziJyzPeZ6EIA0Tno eRqVovUOw0CdqxyK5a2BpI1+drCG8Mbs1/Hc0/55gWF9GuvczpUWJbYWFOjboXGuoXMS kt/2oID6diafFxVnEqLoWxiGR7w2iRCXZMhCDri3b3QGOvCusz2zclXf7S4cP7lIX3rs TQo06Cs4p28YbM7+ZNSXgHwH20C5/sddm4lqTTtbabgeANWuBxVvjL9ZG6g0BUubykii EMyqEX7MIUWXrc5BXI2kae1Iwj6wv0c2N2jIBVkp5TTZNNpU+LVsj4w3POXMOGYpUgeM oX7g== X-Gm-Message-State: AOAM531HNVme8Nxh5oHOkxXleERiJKqfFkQ54Qu/fOEpxpUjAHee5ShL TQErGDyFBseK1eb8zdL+4p4P3Kqzdls= X-Google-Smtp-Source: ABdhPJxKNEYJ5VvvJzCCmtbw1/g2mbbDx3EPmWrYWzj6CY26h/S9CXQeuFKtaNO73YMh+/NQl+f7Zg== X-Received: by 2002:a5d:58dc:: with SMTP id o28mr13079263wrf.414.1612090793758; Sun, 31 Jan 2021 02:59:53 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id l14sm22091419wrq.87.2021.01.31.02.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:53 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v2 6/7] hw/arm/xlnx-zcu102: Restrict ZynqMP ZCU102 board to 64-bit build Date: Sun, 31 Jan 2021 11:59:17 +0100 Message-Id: <20210131105918.228787-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 10:59:59 -0000 The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which is only available in the 64-bit build. It is pointless to have this board present in the 32-bit build where this CPU is not available. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Alistair Francis Cc: "Edgar E. Iglesias" --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 059ff7382f2..345099f5a1b 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -41,7 +41,7 @@ arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) -arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) +arm_ss.add(when: ['CONFIG_XLNX_ZYNQMP_ARM', 'TARGET_AARCH64'], if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:00:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ASj-0007c3-Nm for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:00:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6ASZ-0007ZD-2i; Sun, 31 Jan 2021 06:00:06 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:45330) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6ASX-0000Ua-5f; Sun, 31 Jan 2021 06:00:02 -0500 Received: by mail-wr1-x431.google.com with SMTP id m13so13424601wro.12; Sun, 31 Jan 2021 03:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=CzQnvB+wAGG+ZM98ASAkFFlNd5GPT7S2Vr0TiFcZ9h1nMzE2O3ZNyjO7hWErIt03de fjSp7c3iPq/2WxBlx9/sTwl9uWSpjUMS8Z9R5+KnFlkYDqHVxfEqUkhcCYVpFHFpCZM1 EyLsvmW25ZLIKF7VVERw6T5y147X8Rf21Oqsnijpb1ttu6lpZdu65CIdYeNp/l43ebJq RJ7CKc7F4X7q8342OojNpsZNi8u0rAVDJuaCUrkqntY654FYzosO++jtpr8e268GlFTh AyGqp9+70R1Y7OxX4WxOGP24+uK/tA6sDIaiCQa0aAFKIH0+jLBEBLgh6AcSBw5oR9Zo IKbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=rVSBvL4RML67YWRBJFHOe0+GzprMB3W40ijmMdqjeaZ9KVYg2NzGGfu/QLfOgBI8+B gYer0y8EJb33Wm2x4mxrmUnCU47H484NZpBZpoNrTzVEeshYL1BgM0PkzMRX5yKqHRFT qZo8GPECrCMfqRhBwbpShtdt0r/cHPVOxcDOFWH6UkIll+U0vXdM7kKU55I6IxQNwisz YXR1IxxneBYSlMKOqbxc12g7sRY1D512RHzAKuRPc6H6IGBW4L/75DI4UU/A9gIIKjl5 1u0c+NestB53nCGc+HW3z+WO118ipYT85/ma+rm0kP6cu7lkAI/DImI++I7FMZ3HDuTv HuVw== X-Gm-Message-State: AOAM530sk2v686e6jcH/HRg6cG1iPz+c4w7581MhkGJ4vc/AxfO+DmFD cEdhVPsez3DlKvToQi6dpaLWN/vhU2A= X-Google-Smtp-Source: ABdhPJyY553CHznXAkhgaIPNfhNT33w0WY2gzsrGRR8vsbuHKvEQywFza4gZYWFnvuBdxlbytBMrNA== X-Received: by 2002:adf:f747:: with SMTP id z7mr13068572wrp.384.1612090799066; Sun, 31 Jan 2021 02:59:59 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id e11sm22314803wrx.14.2021.01.31.02.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 02:59:58 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Antony Pavlov , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, qemu-trivial@nongnu.org, Alistair Francis , Niek Linnenbank , Laurent Vivier , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 7/7] hw/arm: Display CPU type in machine description Date: Sun, 31 Jan 2021 11:59:18 +0100 Message-Id: <20210131105918.228787-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131105918.228787-1-f4bug@amsat.org> References: <20210131105918.228787-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:00:10 -0000 Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/digic_boards.c | 2 +- hw/arm/microbit.c | 2 +- hw/arm/netduino2.c | 2 +- hw/arm/netduinoplus2.c | 2 +- hw/arm/orangepi.c | 2 +- hw/arm/stellaris.c | 4 ++-- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index be12873673b..6cdc1d83fca 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine) static void canon_a1100_machine_init(MachineClass *mc) { - mc->desc = "Canon PowerShot A1100 IS"; + mc->desc = "Canon PowerShot A1100 IS (ARM946)"; mc->init = &canon_a1100_init; mc->ignore_memory_transaction_failures = true; mc->default_ram_size = 64 * MiB; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 0947491cb97..e9494334ce7 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "BBC micro:bit"; + mc->desc = "BBC micro:bit (Cortex-M0)"; mc->init = microbit_init; mc->max_cpus = 1; } diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 8f103341443..1733b71507c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine) static void netduino2_machine_init(MachineClass *mc) { - mc->desc = "Netduino 2 Machine"; + mc->desc = "Netduino 2 Machine (Cortex-M3)"; mc->init = netduino2_init; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 68abd3ec69d..d3ad7a2b675 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { - mc->desc = "Netduino Plus 2 Machine"; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index d6306dfddae..40cdb5c6d2c 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine) static void orangepi_machine_init(MachineClass *mc) { - mc->desc = "Orange Pi PC"; + mc->desc = "Orange Pi PC (Cortex-A7)"; mc->init = orangepi_init; mc->block_default_type = IF_SD; mc->units_per_default_bus = 1; diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ad72c0959f1..27292ec4113 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S811EVB"; + mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; mc->init = lm3s811evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); @@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S6965EVB"; + mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; mc->init = lm3s6965evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:13:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Afc-0001bk-Fz for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id l5sm22224061wrv.44.2021.01.31.03.13.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 00/10] target: Provide target-specific Kconfig Date: Sun, 31 Jan 2021 12:13:06 +0100 Message-Id: <20210131111316.232778-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:13:30 -0000 Hi,=0D =0D This series add a Kconfig file to each target, allowing=0D to select target-specific features there, instead of from=0D the hardware Kconfig.=0D =0D This simplifies managing multi-arch features such semihosting.=0D =0D Series organization:=0D =0D 1/ Some targets use the architecture symbol to select boards and=0D peripherals (SH4 and LM32), we need to clean that first.=0D =0D 2/ Introduce empty target Kconfig, update meson.=0D =0D 3/ Move architectural features out of hardware:=0D - x86 SEV=0D - ARM v7m=0D - generic semihosting=0D =0D [following only important to patchew, unrelated to this series]=0D Based-on: <20210131105918.228787-1-f4bug@amsat.org>=0D =0D Philippe Mathieu-Daud=C3=A9 (10):=0D hw/sh4/Kconfig: Rename CONFIG_SH4 -> CONFIG_SH4_PERIPHERALS=0D hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards=0D hw/sh4/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_PERIPHERALS=0D hw/lm32/Kconfig: Have MILKYMIST select LM32_PERIPHERALS=0D meson: Introduce target-specific Kconfig=0D target/i386: Move SEV feature to target Kconfig=0D target/arm: Move V7M feature to target Kconfig=0D default-configs: Remove unnecessary SEMIHOSTING selection=0D target: Move ARM_COMPATIBLE_SEMIHOSTING feature to target Kconfig=0D target: Move SEMIHOSTING feature to target Kconfig=0D =0D default-configs/devices/arm-softmmu.mak | 2 --=0D default-configs/devices/lm32-softmmu.mak | 4 +---=0D default-configs/devices/m68k-softmmu.mak | 2 --=0D .../devices/mips-softmmu-common.mak | 3 ---=0D default-configs/devices/nios2-softmmu.mak | 2 --=0D default-configs/devices/riscv32-softmmu.mak | 2 --=0D default-configs/devices/riscv64-softmmu.mak | 2 --=0D default-configs/devices/unicore32-softmmu.mak | 1 -=0D default-configs/devices/xtensa-softmmu.mak | 2 --=0D meson.build | 3 ++-=0D Kconfig | 1 +=0D hw/arm/Kconfig | 4 ----=0D hw/block/meson.build | 2 +-=0D hw/char/meson.build | 6 ++---=0D hw/i386/Kconfig | 4 ----=0D hw/intc/meson.build | 4 ++--=0D hw/lm32/Kconfig | 10 +++++---=0D hw/lm32/meson.build | 2 +-=0D hw/sh4/Kconfig | 6 ++---=0D hw/timer/meson.build | 4 ++--=0D target/Kconfig | 23 +++++++++++++++++++=0D target/alpha/Kconfig | 2 ++=0D target/arm/Kconfig | 11 +++++++++=0D target/avr/Kconfig | 2 ++=0D target/cris/Kconfig | 2 ++=0D target/hppa/Kconfig | 2 ++=0D target/i386/Kconfig | 9 ++++++++=0D target/lm32/Kconfig | 3 +++=0D target/m68k/Kconfig | 3 +++=0D target/microblaze/Kconfig | 2 ++=0D target/mips/Kconfig | 7 ++++++=0D target/moxie/Kconfig | 2 ++=0D target/nios2/Kconfig | 3 +++=0D target/openrisc/Kconfig | 2 ++=0D target/ppc/Kconfig | 5 ++++=0D target/riscv/Kconfig | 7 ++++++=0D target/rx/Kconfig | 2 ++=0D target/s390x/Kconfig | 2 ++=0D target/sh4/Kconfig | 2 ++=0D target/sparc/Kconfig | 5 ++++=0D target/tilegx/Kconfig | 2 ++=0D target/tricore/Kconfig | 2 ++=0D target/unicore32/Kconfig | 3 +++=0D target/xtensa/Kconfig | 3 +++=0D 44 files changed, 129 insertions(+), 43 deletions(-)=0D create mode 100644 target/Kconfig=0D create mode 100644 target/alpha/Kconfig=0D create mode 100644 target/arm/Kconfig=0D create mode 100644 target/avr/Kconfig=0D create mode 100644 target/cris/Kconfig=0D create mode 100644 target/hppa/Kconfig=0D create mode 100644 target/i386/Kconfig=0D create mode 100644 target/lm32/Kconfig=0D create mode 100644 target/m68k/Kconfig=0D create mode 100644 target/microblaze/Kconfig=0D create mode 100644 target/mips/Kconfig=0D create mode 100644 target/moxie/Kconfig=0D create mode 100644 target/nios2/Kconfig=0D create mode 100644 target/openrisc/Kconfig=0D create mode 100644 target/ppc/Kconfig=0D create mode 100644 target/riscv/Kconfig=0D create mode 100644 target/rx/Kconfig=0D create mode 100644 target/s390x/Kconfig=0D create mode 100644 target/sh4/Kconfig=0D create mode 100644 target/sparc/Kconfig=0D create mode 100644 target/tilegx/Kconfig=0D create mode 100644 target/tricore/Kconfig=0D create mode 100644 target/unicore32/Kconfig=0D create mode 100644 target/xtensa/Kconfig=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 06:13:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Aff-0001gI-4v for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Afc-0001bW-3i; Sun, 31 Jan 2021 06:13:32 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Afa-0006J6-Hx; Sun, 31 Jan 2021 06:13:31 -0500 Received: by mail-wr1-x431.google.com with SMTP id p15so13409527wrq.8; Sun, 31 Jan 2021 03:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id b13sm21667614wrt.31.2021.01.31.03.13.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 01/10] hw/sh4/Kconfig: Rename CONFIG_SH4 -> CONFIG_SH4_PERIPHERALS Date: Sun, 31 Jan 2021 12:13:07 +0100 Message-Id: <20210131111316.232778-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:13:34 -0000 We want to be able to use the 'SH4' config for architecture specific features. As CONFIG_SH4 is only used to select peripherals, rename it CONFIG_SH4_PERIPHERALS. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/meson.build | 2 +- hw/char/meson.build | 2 +- hw/intc/meson.build | 2 +- hw/sh4/Kconfig | 6 +++--- hw/timer/meson.build | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/block/meson.build b/hw/block/meson.build index 602ca6c8541..7f24b42c283 100644 --- a/hw/block/meson.build +++ b/hw/block/meson.build @@ -12,7 +12,7 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c')) softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c')) -softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('tc58128.c')) +softmmu_ss.add(when: 'CONFIG_SH4_PERIPHERALS', if_true: files('tc58128.c')) softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c')) specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c')) diff --git a/hw/char/meson.build b/hw/char/meson.build index 196ac91fa29..3b8cb6a2f5b 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -31,7 +31,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c')) -softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) +softmmu_ss.add(when: 'CONFIG_SH4_PERIPHERALS', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 53cba115690..b05bab2f4b6 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -47,7 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c')) -specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) +specific_ss.add(when: 'CONFIG_SH4_PERIPHERALS', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c')) specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c')) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig index 4cbce3a0ed5..fbac8c09152 100644 --- a/hw/sh4/Kconfig +++ b/hw/sh4/Kconfig @@ -9,16 +9,16 @@ config R2D select USB_OHCI_PCI select PCI select SM501 - select SH4 + select SH4_PERIPHERALS config SHIX bool select SH7750 - select SH4 + select SH4_PERIPHERALS config SH7750 bool -config SH4 +config SH4_PERIPHERALS bool select PTIMER diff --git a/hw/timer/meson.build b/hw/timer/meson.build index be343f68fed..d3f53dce400 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -30,7 +30,7 @@ softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_ost.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c')) -softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c')) +softmmu_ss.add(when: 'CONFIG_SH4_PERIPHERALS', if_true: files('sh_timer.c')) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:13:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Afk-0001tX-Np for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id s19sm25233016wrf.72.2021.01.31.03.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 02/10] hw/lm32/Kconfig: Introduce CONFIG_LM32_EVR for lm32-evr/uclinux boards Date: Sun, 31 Jan 2021 12:13:08 +0100 Message-Id: <20210131111316.232778-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:13:39 -0000 We want to be able to use the 'LM32' config for architecture specific features. Introduce CONFIG_LM32_EVR to select the lm32-evr / lm32-uclinux boards. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/lm32-softmmu.mak | 2 +- hw/lm32/Kconfig | 6 +++++- hw/lm32/meson.build | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/default-configs/devices/lm32-softmmu.mak b/default-configs/devices/lm32-softmmu.mak index 115b3e34c98..1bce3f6e8b6 100644 --- a/default-configs/devices/lm32-softmmu.mak +++ b/default-configs/devices/lm32-softmmu.mak @@ -8,5 +8,5 @@ CONFIG_SEMIHOSTING=y # Boards: # -CONFIG_LM32=y +CONFIG_LM32_EVR=y CONFIG_MILKYMIST=y diff --git a/hw/lm32/Kconfig b/hw/lm32/Kconfig index ed2e3060b04..20c36edc402 100644 --- a/hw/lm32/Kconfig +++ b/hw/lm32/Kconfig @@ -1,7 +1,6 @@ config LM32 bool select PTIMER - select PFLASH_CFI02 config MILKYMIST bool @@ -12,3 +11,8 @@ config MILKYMIST select FRAMEBUFFER select SD select USB_OHCI + +config LM32_EVR + bool + select LM32 + select PFLASH_CFI02 diff --git a/hw/lm32/meson.build b/hw/lm32/meson.build index 8caf0a727ff..42d6f8db3d9 100644 --- a/hw/lm32/meson.build +++ b/hw/lm32/meson.build @@ -1,6 +1,6 @@ lm32_ss = ss.source_set() # LM32 boards -lm32_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_boards.c')) +lm32_ss.add(when: 'CONFIG_LM32_EVR', if_true: files('lm32_boards.c')) lm32_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist.c')) hw_arch += {'lm32': lm32_ss} -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:13:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Afr-0002CB-MT for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:13:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Afp-00026B-KN; Sun, 31 Jan 2021 06:13:45 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:34143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Afn-0006Og-TN; Sun, 31 Jan 2021 06:13:45 -0500 Received: by mail-wm1-x32c.google.com with SMTP id o10so9598517wmc.1; Sun, 31 Jan 2021 03:13:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fYQAVaNNfllVHQX0jOIMlQzoC4zDZBjKHd4G1bFe6gE=; b=VtsFlqIBtqo1kXig1EeJWLBVRMox9I8WX2P/8PRWsWkbAckwzpSZIZoFEczXG6Wgnb 6SlPCptAu7PFm3akwbHlaYFbePl01zvC4eLGG4ahfyOye7dl6CjxQG9/jWwiXEXCwy4L dtWnpYz97KrNvOFHlKNsDfYtBehZOBkcb+HScuBj9Wf6aezOwyKRQ9pbeA+hkuCnRBfR 5qPKsGkUfJxuuRsgpjNRxZ6hMnOoJnqHu+Arh2e5cJnS5kl8bRmds/aqfboawpLoczrl F7GoyE9FJyOqHTjCdvVg5KKNA6+XWYVt/aivp0giwV6JgDm1J+v0aKkfHzXE7d2EKpoa go5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fYQAVaNNfllVHQX0jOIMlQzoC4zDZBjKHd4G1bFe6gE=; b=tjMQJCCWMmnl2OJ0aX/ht8I5AZEiJCLMoO/u2r3ce2vlI/yY6igJyKv1RoyFObHR1u jL25MEZ0xLpHm46pZB2eSmnj2oBzP+9qkMnTiNNQbK10qxD/xdvs7AMCWAs38/ajIl8G cxLRBgS4PTqyols+b5gojEL1es+ysT1YzBY7uqnjfZJkF0WNMxIuopY1XYOfXABnVcTr tJ4twgeMH0oMOqpF+tSTgdJVW3cDDZv2holp/g9gVPU2tGuoq8C/c+LZY82OTOdTjGCA pcxr7JviB9Ksx/U4UhdVA12ALLDOrgEdIu+6kYdzfvEno3VpYbQtn6wUhL3/4uKQU7nP gTjw== X-Gm-Message-State: AOAM530eDU5yWGxwzNbG+bIVaLZQsh/SkrdSPjRTDM8lynBmbvGK3crQ Wma3OK3X3OfLdyyDGE/YLS6KYYyR0mo= X-Google-Smtp-Source: ABdhPJygYyM+WH/1+ddpYuuvNeuUZ11kFCnNJRQVgkKeFFsZxyw0wUwCZKD+WJAIXr4jn58+npJiTQ== X-Received: by 2002:a05:600c:4fc2:: with SMTP id o2mr10585388wmq.90.1612091620427; Sun, 31 Jan 2021 03:13:40 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id x81sm18641566wmg.40.2021.01.31.03.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 03/10] hw/sh4/Kconfig: Rename CONFIG_LM32 -> CONFIG_LM32_PERIPHERALS Date: Sun, 31 Jan 2021 12:13:09 +0100 Message-Id: <20210131111316.232778-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:13:46 -0000 We want to be able to use the 'LM32' config for architecture specific features. As CONFIG_LM32 is only used to select peripherals, rename it CONFIG_LM32_PERIPHERALS. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/meson.build | 4 ++-- hw/intc/meson.build | 2 +- hw/lm32/Kconfig | 4 ++-- hw/timer/meson.build | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/char/meson.build b/hw/char/meson.build index 3b8cb6a2f5b..b05dcc41c59 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -8,8 +8,8 @@ softmmu_ss.add(when: 'CONFIG_IPACK', if_true: files('ipoctal232.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('parallel-isa.c')) softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugcon.c')) -softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_juart.c')) -softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_uart.c')) +softmmu_ss.add(when: 'CONFIG_LM32_PERIPHERALS', if_true: files('lm32_juart.c')) +softmmu_ss.add(when: 'CONFIG_LM32_PERIPHERALS', if_true: files('lm32_uart.c')) softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-uart.c')) softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_uart.c')) softmmu_ss.add(when: 'CONFIG_PARALLEL', if_true: files('parallel.c')) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index b05bab2f4b6..bfaab908ac7 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -14,7 +14,7 @@ softmmu_ss.add(when: 'CONFIG_I8259', if_true: files('i8259_common.c', 'i8259.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_avic.c', 'imx_gpcv2.c')) softmmu_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic_common.c')) -softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_pic.c')) +softmmu_ss.add(when: 'CONFIG_LM32_PERIPHERALS', if_true: files('lm32_pic.c')) softmmu_ss.add(when: 'CONFIG_OPENPIC', if_true: files('openpic.c')) softmmu_ss.add(when: 'CONFIG_PL190', if_true: files('pl190.c')) softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_intc.c')) diff --git a/hw/lm32/Kconfig b/hw/lm32/Kconfig index 20c36edc402..5867f4db0cf 100644 --- a/hw/lm32/Kconfig +++ b/hw/lm32/Kconfig @@ -1,4 +1,4 @@ -config LM32 +config LM32_PERIPHERALS bool select PTIMER @@ -14,5 +14,5 @@ config MILKYMIST config LM32_EVR bool - select LM32 + select LM32_PERIPHERALS select PFLASH_CFI02 diff --git a/hw/timer/meson.build b/hw/timer/meson.build index d3f53dce400..36ca0d34942 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -19,7 +19,7 @@ softmmu_ss.add(when: 'CONFIG_I8254', if_true: files('i8254_common.c', 'i8254.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_epit.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpt.c')) -softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_timer.c')) +softmmu_ss.add(when: 'CONFIG_LM32_PERIPHERALS', if_true: files('lm32_timer.c')) softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-sysctl.c')) softmmu_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gictimer.c')) softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-timer.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:13:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Ag0-0002Ro-KU for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id u14sm17326317wmq.45.2021.01.31.03.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:46 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 04/10] hw/lm32/Kconfig: Have MILKYMIST select LM32_PERIPHERALS Date: Sun, 31 Jan 2021 12:13:10 +0100 Message-Id: <20210131111316.232778-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:13:54 -0000 The Milkymist board requires more than the PTIMER. Directly select the LM32_PERIPHERALS. This fixes: /usr/bin/ld: libqemu-lm32-softmmu.fa.p/target_lm32_gdbstub.c.o: in function `lm32_cpu_gdb_read_register': target/lm32/gdbstub.c:46: undefined reference to `lm32_pic_get_im' target/lm32/gdbstub.c:48: undefined reference to `lm32_pic_get_ip' libqemu-lm32-softmmu.fa.p/target_lm32_op_helper.c.o: in function `helper_wcsr_im': target/lm32/op_helper.c:107: undefined reference to `lm32_pic_set_im' libqemu-lm32-softmmu.fa.p/target_lm32_op_helper.c.o: in function `helper_wcsr_ip': target/lm32/op_helper.c:114: undefined reference to `lm32_pic_set_ip' libqemu-lm32-softmmu.fa.p/target_lm32_op_helper.c.o: in function `helper_wcsr_jtx': target/lm32/op_helper.c:120: undefined reference to `lm32_juart_set_jtx' libqemu-lm32-softmmu.fa.p/target_lm32_op_helper.c.o: in function `helper_wcsr_jrx': target/lm32/op_helper.c:125: undefined reference to `lm32_juart_set_jrx' libqemu-lm32-softmmu.fa.p/target_lm32_translate.c.o: in function `lm32_cpu_dump_state': target/lm32/translate.c:1161: undefined reference to `lm32_pic_get_ip' target/lm32/translate.c:1161: undefined reference to `lm32_pic_get_im' Signed-off-by: Philippe Mathieu-Daudé --- hw/lm32/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/lm32/Kconfig b/hw/lm32/Kconfig index 5867f4db0cf..38ad22c54e4 100644 --- a/hw/lm32/Kconfig +++ b/hw/lm32/Kconfig @@ -6,11 +6,11 @@ config MILKYMIST bool # FIXME: disabling it results in compile-time errors select MILKYMIST_TMU2 if OPENGL && X11 - select PTIMER select PFLASH_CFI01 select FRAMEBUFFER select SD select USB_OHCI + select LM32_PERIPHERALS config LM32_EVR bool -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:14:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Ag7-0002bQ-Fk for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:14:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Ag3-0002Vl-Lw; Sun, 31 Jan 2021 06:13:59 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:34147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Ag1-0006Ve-BH; Sun, 31 Jan 2021 06:13:58 -0500 Received: by mail-wm1-x32f.google.com with SMTP id o10so9598771wmc.1; Sun, 31 Jan 2021 03:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fKIfvtq/P4RYttCZaDmgRPWiT/b+dH3aZ+07k+ffCOU=; b=MLzvE4BzySHsO5ful+O0CcZLDsEHwdwzcg2n6/ilNkD5bzPOaPGXvVpsJINZOmaNna 6hRCefkv49UGlXkG3As92xVTPXRowhugUYyKFFyXhd6ohD4Ca4i37c3nYREYQG7Uvope Sl3v8rCvwDhLtx3sxZ9gdgP20BYQc7mOhGZWRqxLWif6+j0h5pubGnrFVo+eD/hiZnBh tjd77Va79EqJgK5c/DcyDmBRwo3WiBPvgEZP2k4o0g53j2rKofN+N2kuFRgK/9Ooy6px J2Vw4/4HW6lDZa9nH9KPr/uN4lgnkNT+uQwSwEAyzSQW+sT4yzl4dLTEx8WjpS6ri7fs CjuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fKIfvtq/P4RYttCZaDmgRPWiT/b+dH3aZ+07k+ffCOU=; b=nryPKtbZD1wLmpVZblksun1h3hGAx4aIVlOzxascjt+yCZdwaGjFE72arDcBJ4vCW6 B0MsJTZnREjUVBkPXdf6fUM7ngSTpKhiN6dGyp8Trje3qPKFUrlLUVAs/IqSCKqyg/3s 9RsPXpyT4t3jOtUcwMNqi+qLFE7CVUBkFBG+7gSYEl5Birp4GaqviCc6Tx6yy1YDmxbh o738kd02X3bF7jI2/qoyCJDR6R/u6AgAV6YLt+etU7ff/YqIt6hcAoXxmeg6RCp89OND yS+iX1z7n+QHalAWxIWaVNTpDqJZQnk3i5TW+fhyTNKPh0ePkEBoJD0LvQ61Pe3xcjj+ 3JzQ== X-Gm-Message-State: AOAM533QQuGg6LVlXO4bxZhJOUbo1B/2J6CaqS27VAwIT6VNYE4OFe9n RCp6KRZnU+WNAWOMbt+6f+bDdGC5rec= X-Google-Smtp-Source: ABdhPJxJn7I1TqZqFnPB4jxTvDpNmaOxrth0ldzvkIsEXfvQ4D1kiB4Cf1sD8aIGlvuN1yHxEdasFw== X-Received: by 2002:a1c:7402:: with SMTP id p2mr10614546wmc.43.1612091633442; Sun, 31 Jan 2021 03:13:53 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id o13sm24191897wrh.88.2021.01.31.03.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 05/10] meson: Introduce target-specific Kconfig Date: Sun, 31 Jan 2021 12:13:11 +0100 Message-Id: <20210131111316.232778-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:00 -0000 Add a target-specific Kconfig. Target foo now has CONFIG_FOO defined. Two architecture have a particularity, ARM and MIPS: their 64-bit version include the 32-bit subset. Signed-off-by: Philippe Mathieu-Daudé --- I suppose X86_64 should also select I386? No clue about PPC/RISCV. --- meson.build | 3 ++- Kconfig | 1 + target/Kconfig | 23 +++++++++++++++++++++++ target/alpha/Kconfig | 2 ++ target/arm/Kconfig | 6 ++++++ target/avr/Kconfig | 2 ++ target/cris/Kconfig | 2 ++ target/hppa/Kconfig | 2 ++ target/i386/Kconfig | 5 +++++ target/lm32/Kconfig | 2 ++ target/m68k/Kconfig | 2 ++ target/microblaze/Kconfig | 2 ++ target/mips/Kconfig | 6 ++++++ target/moxie/Kconfig | 2 ++ target/nios2/Kconfig | 2 ++ target/openrisc/Kconfig | 2 ++ target/ppc/Kconfig | 5 +++++ target/riscv/Kconfig | 5 +++++ target/rx/Kconfig | 2 ++ target/s390x/Kconfig | 2 ++ target/sh4/Kconfig | 2 ++ target/sparc/Kconfig | 5 +++++ target/tilegx/Kconfig | 2 ++ target/tricore/Kconfig | 2 ++ target/unicore32/Kconfig | 2 ++ target/xtensa/Kconfig | 2 ++ 26 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 target/Kconfig create mode 100644 target/alpha/Kconfig create mode 100644 target/arm/Kconfig create mode 100644 target/avr/Kconfig create mode 100644 target/cris/Kconfig create mode 100644 target/hppa/Kconfig create mode 100644 target/i386/Kconfig create mode 100644 target/lm32/Kconfig create mode 100644 target/m68k/Kconfig create mode 100644 target/microblaze/Kconfig create mode 100644 target/mips/Kconfig create mode 100644 target/moxie/Kconfig create mode 100644 target/nios2/Kconfig create mode 100644 target/openrisc/Kconfig create mode 100644 target/ppc/Kconfig create mode 100644 target/riscv/Kconfig create mode 100644 target/rx/Kconfig create mode 100644 target/s390x/Kconfig create mode 100644 target/sh4/Kconfig create mode 100644 target/sparc/Kconfig create mode 100644 target/tilegx/Kconfig create mode 100644 target/tricore/Kconfig create mode 100644 target/unicore32/Kconfig create mode 100644 target/xtensa/Kconfig diff --git a/meson.build b/meson.build index f00b7754fd4..a2dda0ce95e 100644 --- a/meson.build +++ b/meson.build @@ -1322,7 +1322,8 @@ command: [minikconf, get_option('default_devices') ? '--defconfig' : '--allnoconfig', config_devices_mak, '@DEPFILE@', '@INPUT@', - host_kconfig, accel_kconfig]) + host_kconfig, accel_kconfig, + 'CONFIG_' + config_target['TARGET_ARCH'].to_upper() + '=y']) config_devices_data = configuration_data() config_devices = keyval.load(config_devices_mak) diff --git a/Kconfig b/Kconfig index bf694c42afe..c01e261e4e9 100644 --- a/Kconfig +++ b/Kconfig @@ -1,4 +1,5 @@ source Kconfig.host source backends/Kconfig source accel/Kconfig +source target/Kconfig source hw/Kconfig diff --git a/target/Kconfig b/target/Kconfig new file mode 100644 index 00000000000..a6f719f223a --- /dev/null +++ b/target/Kconfig @@ -0,0 +1,23 @@ +source alpha/Kconfig +source arm/Kconfig +source avr/Kconfig +source cris/Kconfig +source hppa/Kconfig +source i386/Kconfig +source lm32/Kconfig +source m68k/Kconfig +source microblaze/Kconfig +source mips/Kconfig +source moxie/Kconfig +source nios2/Kconfig +source openrisc/Kconfig +source ppc/Kconfig +source riscv/Kconfig +source rx/Kconfig +source s390x/Kconfig +source sh4/Kconfig +source sparc/Kconfig +source tilegx/Kconfig +source tricore/Kconfig +source unicore32/Kconfig +source xtensa/Kconfig diff --git a/target/alpha/Kconfig b/target/alpha/Kconfig new file mode 100644 index 00000000000..267222c05b8 --- /dev/null +++ b/target/alpha/Kconfig @@ -0,0 +1,2 @@ +config ALPHA + bool diff --git a/target/arm/Kconfig b/target/arm/Kconfig new file mode 100644 index 00000000000..3f3394a22b2 --- /dev/null +++ b/target/arm/Kconfig @@ -0,0 +1,6 @@ +config ARM + bool + +config AARCH64 + bool + select ARM diff --git a/target/avr/Kconfig b/target/avr/Kconfig new file mode 100644 index 00000000000..155592d3537 --- /dev/null +++ b/target/avr/Kconfig @@ -0,0 +1,2 @@ +config AVR + bool diff --git a/target/cris/Kconfig b/target/cris/Kconfig new file mode 100644 index 00000000000..3fdc309fbbd --- /dev/null +++ b/target/cris/Kconfig @@ -0,0 +1,2 @@ +config CRIS + bool diff --git a/target/hppa/Kconfig b/target/hppa/Kconfig new file mode 100644 index 00000000000..395a35d799c --- /dev/null +++ b/target/hppa/Kconfig @@ -0,0 +1,2 @@ +config HPPA + bool diff --git a/target/i386/Kconfig b/target/i386/Kconfig new file mode 100644 index 00000000000..ce6968906ee --- /dev/null +++ b/target/i386/Kconfig @@ -0,0 +1,5 @@ +config I386 + bool + +config X86_64 + bool diff --git a/target/lm32/Kconfig b/target/lm32/Kconfig new file mode 100644 index 00000000000..09de5b703a3 --- /dev/null +++ b/target/lm32/Kconfig @@ -0,0 +1,2 @@ +config LM32 + bool diff --git a/target/m68k/Kconfig b/target/m68k/Kconfig new file mode 100644 index 00000000000..23debad519a --- /dev/null +++ b/target/m68k/Kconfig @@ -0,0 +1,2 @@ +config M68K + bool diff --git a/target/microblaze/Kconfig b/target/microblaze/Kconfig new file mode 100644 index 00000000000..a5410d9218d --- /dev/null +++ b/target/microblaze/Kconfig @@ -0,0 +1,2 @@ +config MICROBLAZE + bool diff --git a/target/mips/Kconfig b/target/mips/Kconfig new file mode 100644 index 00000000000..6adf1453548 --- /dev/null +++ b/target/mips/Kconfig @@ -0,0 +1,6 @@ +config MIPS + bool + +config MIPS64 + bool + select MIPS diff --git a/target/moxie/Kconfig b/target/moxie/Kconfig new file mode 100644 index 00000000000..52391bbd289 --- /dev/null +++ b/target/moxie/Kconfig @@ -0,0 +1,2 @@ +config MOXIE + bool diff --git a/target/nios2/Kconfig b/target/nios2/Kconfig new file mode 100644 index 00000000000..1529ab8950d --- /dev/null +++ b/target/nios2/Kconfig @@ -0,0 +1,2 @@ +config NIOS2 + bool diff --git a/target/openrisc/Kconfig b/target/openrisc/Kconfig new file mode 100644 index 00000000000..e0da4ac1dfc --- /dev/null +++ b/target/openrisc/Kconfig @@ -0,0 +1,2 @@ +config OPENRISC + bool diff --git a/target/ppc/Kconfig b/target/ppc/Kconfig new file mode 100644 index 00000000000..3ff152051a3 --- /dev/null +++ b/target/ppc/Kconfig @@ -0,0 +1,5 @@ +config PPC + bool + +config PPC64 + bool diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig new file mode 100644 index 00000000000..b9e5932f13f --- /dev/null +++ b/target/riscv/Kconfig @@ -0,0 +1,5 @@ +config RISCV32 + bool + +config RISCV64 + bool diff --git a/target/rx/Kconfig b/target/rx/Kconfig new file mode 100644 index 00000000000..aceb5ed28fe --- /dev/null +++ b/target/rx/Kconfig @@ -0,0 +1,2 @@ +config RX + bool diff --git a/target/s390x/Kconfig b/target/s390x/Kconfig new file mode 100644 index 00000000000..72da48136c6 --- /dev/null +++ b/target/s390x/Kconfig @@ -0,0 +1,2 @@ +config S390X + bool diff --git a/target/sh4/Kconfig b/target/sh4/Kconfig new file mode 100644 index 00000000000..2397c860280 --- /dev/null +++ b/target/sh4/Kconfig @@ -0,0 +1,2 @@ +config SH4 + bool diff --git a/target/sparc/Kconfig b/target/sparc/Kconfig new file mode 100644 index 00000000000..70cc0f3a210 --- /dev/null +++ b/target/sparc/Kconfig @@ -0,0 +1,5 @@ +config SPARC + bool + +config SPARC64 + bool diff --git a/target/tilegx/Kconfig b/target/tilegx/Kconfig new file mode 100644 index 00000000000..aad882826ab --- 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id l11sm21775517wrt.23.2021.01.31.03.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:13:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 06/10] target/i386: Move SEV feature to target Kconfig Date: Sun, 31 Jan 2021 12:13:12 +0100 Message-Id: <20210131111316.232778-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:06 -0000 SEV is an architecture feature, move its declaration to target/i386/. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/Kconfig | 4 ---- target/i386/Kconfig | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 7f91f30877f..3d67c172dab 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -1,7 +1,3 @@ -config SEV - bool - depends on KVM - config PC bool imply APPLESMC diff --git a/target/i386/Kconfig b/target/i386/Kconfig index ce6968906ee..27c76c554c7 100644 --- a/target/i386/Kconfig +++ b/target/i386/Kconfig @@ -3,3 +3,7 @@ config I386 config X86_64 bool + +config SEV + bool + depends on KVM && I386 -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:14:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AgH-00031E-9H for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:14:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AgF-0002uz-1v; Sun, 31 Jan 2021 06:14:11 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:36620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AgD-0006cE-Ig; Sun, 31 Jan 2021 06:14:10 -0500 Received: by mail-wm1-x32e.google.com with SMTP id i9so10727339wmq.1; Sun, 31 Jan 2021 03:14:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eh0nPPe+ccMxW9Cb/jr3NHaD25Nxmw47W22jriJyAa0=; b=qG77/DVNuWObaYdxvSPXp5aG31DRU/wwuuwJi7XpKzBbIN+GO30SCqSe+Ev8IPFx+J 7AOHuOBnnOi2Mu1p26bxIbkAg7mNr8kTMVGj/d1RRoOyYaqlCOwSAECWsxACrs55ND4j XBxBOZ+46U6R2MmtCyyv/rI3TwxL8+lpwzo9N4P0iCRcWIv6FhslDGiBGYJzyyNRJOJM 0Fya/lNgbOvAl16FrnWD4NIAPg8hdSNvc03xmCdsePxHZDJIexs3p+Kfa5NsO5eQ1ydy FFXy9x/slDkUf+t14rafYvKY3wcV5qpkcGGfm9UC6tWBQth6w+81RT82O9phB5VVKoFr h6JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Eh0nPPe+ccMxW9Cb/jr3NHaD25Nxmw47W22jriJyAa0=; b=lwlOKu226O6K1Mlo0Pc4ZYAxJPHocrCzADWgba3R/JHDlhIgy0gYHuO9cr1rxsa37v rTvrhKsOwUuEemKkyfharDXXbRkCjLm8/zxfZULAUHHGIQNCXQ6XMVAKtGKBqkpwd/yK 0dpvDfju0vKDEY18Er3iUwOgkv/Mu/81Fag8+i33B4ga9QriXbIMyMLNN3q/lHUQ1jX6 ytNyRagOJK9QoXpn9O+EArpA+yNjkxpiX3elUBeuc9+vAMG3iPdPw/63y0OmNDnW/Y+L 0e8c5Vw5VlqeHSlTVM6eIk/cU8wJaYC5gY+R4x13mpqd/yO0KV870h2Fe3Qyy0DEL0hX xAyQ== X-Gm-Message-State: AOAM5303aIAQtfS5z1//CBDcJZWFPq4d8Jvm6T46jMqTFNF2LhjpjLLk 7biATAL5KSbyH11DMz/udI+1G4YhaF4= X-Google-Smtp-Source: ABdhPJz4doJnrW/LDttNtT/C/l19beETvSJdy/mFd/0h+4oo2oFT/uS3U7LQJZd1vVQMdWC5gHeIMw== X-Received: by 2002:a1c:4107:: with SMTP id o7mr10703980wma.33.1612091646092; Sun, 31 Jan 2021 03:14:06 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id p15sm22584734wrt.15.2021.01.31.03.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:14:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 07/10] target/arm: Move V7M feature to target Kconfig Date: Sun, 31 Jan 2021 12:13:13 +0100 Message-Id: <20210131111316.232778-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:12 -0000 V7M is an architecture feature, move its declaration to target/arm/. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/Kconfig | 4 ---- target/arm/Kconfig | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 09298881f2f..f3ecb73a3d8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -292,10 +292,6 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG -config ARM_V7M - bool - select PTIMER - config ALLWINNER_A10 bool select AHCI diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 3f3394a22b2..1f05de47ca6 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -4,3 +4,7 @@ config ARM config AARCH64 bool select ARM + +config ARM_V7M + bool + select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:14:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AgN-0003JL-Lp for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:14:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AgL-0003D5-7h; Sun, 31 Jan 2021 06:14:17 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:39697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AgJ-0006hB-LK; Sun, 31 Jan 2021 06:14:16 -0500 Received: by mail-wm1-x331.google.com with SMTP id u14so10707749wmq.4; Sun, 31 Jan 2021 03:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GDkI+rwKtjNKilVNRpLbahjwFzHqXAoDQm6Y6hyZ/4A=; b=leLcc6pFkG2sud5rWI+np/GSNmk62nWtvomlIRSzn4Ps4W4u0zcCv9+YPncGta2nOk zojnlppJSKiqHsmhu4SMXg9Sqb3Nho20dwRvOZu88vHcEoIyLCwBIwgwPC6qkGR8SGjL mDOi057bPcyru2ek9N1L9V9YoqMQiiYOVJ7P1lRvK0U/qB5QmOkczRl7tbDXxThWuHvg NDUxTIVV1kg0sYo20cJ/D46E6W/6YFEUGy5kZmYktcCAwspqomi+1r5IuzzJ7dlfnJR4 jSraOTY7DNRBaBcm24oskY1FGrU55g878fdQuGIoCSgpemOyATgpaDpx8l/aG/31ITJ+ fC1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GDkI+rwKtjNKilVNRpLbahjwFzHqXAoDQm6Y6hyZ/4A=; b=IdGasWBdK5lAJyBApByBrFM5fZ5u3qEp5ONkwDsAhPVbYvF3A8keVuabTDuWDAJEMu 2a1NkOKpeSUoWN1VRbEXU7i/8pd+xQpn9VAOrzu8MpR4X5/yl4rB7vyl4Lepl/xMFx91 ih6b0ovBJ99iotECYobYGyT/Ww2VxMcL+u8kBvv1Dv0mmOHzlw0oiqCrPwqm8UEEpsRB ZxxZ8PlJCJykKkOTvo8KvZlmSZHZACUlyzwfAczZbamfAcOdQ98pVhs0qwNpBdOwela1 QlgvnMEeZO7vkdErYDboUek7CFfPtNZCdfDOeMPrTR3F5qnYJLzjb3U9STgQ3UldeuHr 07OQ== X-Gm-Message-State: AOAM5310ylY9zqicyjctH/iSUpPrQjSDTtdTsXAHjX6K87YqlE/v2R6R fa0Ro7rB6K1MIrcPS5NhUP3+Kf+TBxc= X-Google-Smtp-Source: ABdhPJxnjopGFqmpUKqaP8zHmFxUTRSBU1pnTi6CbH65zn6PNcQ5hIQXrup6Ok2s8PWmQ9nwRghYPw== X-Received: by 2002:a7b:c08f:: with SMTP id r15mr10912239wmh.22.1612091652608; Sun, 31 Jan 2021 03:14:12 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id h1sm23178056wrr.73.2021.01.31.03.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:14:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 08/10] default-configs: Remove unnecessary SEMIHOSTING selection Date: Sun, 31 Jan 2021 12:13:14 +0100 Message-Id: <20210131111316.232778-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:18 -0000 Commit 56b5170c87e ("semihosting: Move ARM semihosting code to shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which already selects SEMIHOSTING. No need to select it again. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 1 - default-configs/devices/riscv32-softmmu.mak | 1 - default-configs/devices/riscv64-softmmu.mak | 1 - 3 files changed, 3 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0500156a0c7..341d439de6f 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -41,6 +41,5 @@ CONFIG_MICROBIT=y CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y -CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index d847bd5692e..5c9ad2590ef 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,7 +3,6 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n -CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index d5eec75f05e..d5b2e25b6df 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,7 +3,6 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n -CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:14:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6AgU-0003af-I5 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:14:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59058) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AgR-0003SF-Hv; Sun, 31 Jan 2021 06:14:23 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AgQ-0006nV-0d; Sun, 31 Jan 2021 06:14:23 -0500 Received: by mail-wr1-x42d.google.com with SMTP id a1so13469233wrq.6; Sun, 31 Jan 2021 03:14:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E+U3nLCLAwB5cFSUB8M9sBsCoJgPFLGLn3AiQdETqYc=; b=F7xvz2a4Av9sQ1J9xlj0W/SmUCWPaAf/0CAl9b76xFlgd3Ytn6xlEVysgmoLA//gwV Fz6eLoh2H2dcE3xuCpdg1Sr/HLsW6AwUAL2lf9WxOf4LqraNJIuuSS4XH5L/nwBaSaMy 9YuQhbCAK/xKKMe6SUWazsFHadNxZSika87+p8A5uNbHdcvWxNIqlkja8JCP+LeZzAld Cm7PLKH7OfOOSGzDus7KJeYeCUz/xY4HV+VXd6tNnqqVWTJ0GfPLCuy8/yuxt9iA82Yi dCSD2p24tt4KAyc+WvQz9fFx4qOQ4dy8o6Vdj9NHFJ4/PCpZM+qYfH4MLJi0OBFAlw5Y 7HHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=E+U3nLCLAwB5cFSUB8M9sBsCoJgPFLGLn3AiQdETqYc=; b=d28Y88VWh57Q1LBQmB4uE4YVbU+cdyt/W0FgQ484CRs/9obFjLpH8ltkO5dtNx75Jh Ndq2gwg9nRvRy5vIPtfn1IHtKTP3ZbgDBA4sXuOXsa7V83m279ZXDhiZMl4C5qNvY4BZ FS+Sn6zM7oJ/R15iSzXdzSFkzMIHlEAd2Y0Iz9V+jCL8RoZ3RKfJsIFsbI7pRODhndHr a8uTqUT3rMSMrNbjJXpLkWvjCwip8QBy75pjojqAKm2GSuKdyVISq9ymN6O0BhGhJ/gY hM49Dok/8bH1RIlEXZTHqMm9bN3CB+yMGb55Bh5E7hqVS05RJABgnBsKqEUNkpcK6tC+ OB5w== X-Gm-Message-State: AOAM530/C473gX9pmJh5R+jWouxtSKQxyShNlzNiT8jFfG3v1YFEe7t7 ju8w/CkpwsZW1I7pkfb3YoKKRX6Tz0s= X-Google-Smtp-Source: ABdhPJy30l58DKSg0ZGp97k54Lb3Vy3dgfEEA0Qiy7Cu/d9Ok8KuwBLumNkzx3d49+pKEvKyVuELcw== X-Received: by 2002:adf:f606:: with SMTP id t6mr13317727wrp.360.1612091658986; Sun, 31 Jan 2021 03:14:18 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id i15sm11407947wmq.26.2021.01.31.03.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:14:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 09/10] target: Move ARM_COMPATIBLE_SEMIHOSTING feature to target Kconfig Date: Sun, 31 Jan 2021 12:13:15 +0100 Message-Id: <20210131111316.232778-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:24 -0000 ARM_COMPATIBLE_SEMIHOSTING is an architecture feature, move its declaration to each target/ARCH/. Note, we do not modify the linux-user targets, as user-mode builds don't use Kconfig. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 1 - default-configs/devices/riscv32-softmmu.mak | 1 - default-configs/devices/riscv64-softmmu.mak | 1 - target/arm/Kconfig | 1 + target/riscv/Kconfig | 2 ++ 5 files changed, 3 insertions(+), 3 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 341d439de6f..0824e9be795 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -41,5 +41,4 @@ CONFIG_MICROBIT=y CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y -CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 5c9ad2590ef..94a236c9c25 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,7 +3,6 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n -CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index d5b2e25b6df..76b61956489 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,7 +3,6 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n -CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 1f05de47ca6..ae89d05c7e5 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -1,5 +1,6 @@ config ARM bool + select ARM_COMPATIBLE_SEMIHOSTING config AARCH64 bool diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig index b9e5932f13f..c3b9d8a1cf1 100644 --- a/target/riscv/Kconfig +++ b/target/riscv/Kconfig @@ -1,5 +1,7 @@ config RISCV32 bool + select ARM_COMPATIBLE_SEMIHOSTING config RISCV64 bool + select ARM_COMPATIBLE_SEMIHOSTING -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:14:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Agc-0003vL-29 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:14:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6AgZ-0003nG-2o; Sun, 31 Jan 2021 06:14:31 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33637) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6AgX-0006qG-Ad; Sun, 31 Jan 2021 06:14:30 -0500 Received: by mail-wr1-x42d.google.com with SMTP id 7so13472851wrz.0; Sun, 31 Jan 2021 03:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G4MEjoHCumEr6ZmgdVDdQeeb4uA9ELO8JMQqAxzVyEA=; b=kGMjQPgg+PuwWLXGyfFpAH63DQkfaoEntKmcDz1/HZ9D/AtSihntOewrXVzp7HFMPn FkoHU+MLckF0Mbzyocu5SZqX+nDDx2bn4b1AKSWcAs9tmxWmoA36iMin6KW+E1QhmA7R Wnh2f8X5qRZ+R+KHroUdSn+8wJoL2v4Ku33SP2lMN37u6T+KWIOdR0Cwus3wEKO746jR RM4GWWLBT/DrZlNHWoVUqMFzu9ZkEmlX/CEkHQltWE/jRPJjcHnN5Vxe6tDdSe4vmYpV S9Yu/uB8iH3boeEwvSLm4lLnBzSmoXvAO90kaD3drrLDEU56y4FHpyHwUN5BIdKSEYzh UbcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=G4MEjoHCumEr6ZmgdVDdQeeb4uA9ELO8JMQqAxzVyEA=; b=W70u+igidiT5zzFC3mMP5WBBg9ERvXaRWjEc8oTnYRexxQJr1qgzZBpIYbpTLS7g1B 4ixjY4zUniY/osrCtf3Yp4l7wJLKivqxpugqGpsHEomYhjsRSnRkBMKrleOZZXB+354l h84jdzyfjvcbW5EWvXXctpCRHRyvbvasHgX69B+M6SUd6KVgCAkjHUAacNt6Ku8G6DCt iuuJbzkCZel/6MCcJGsM0a0j6Bc25sCpphxtVRBxiephBx/KUuBFwn377tVEYm4LQNe3 90GMAhliuRS3FSom9OrTz87v4+NcZrchgAS7ixahs2VPS8/BnvHxpBiBqgCuPAlenKJh 6dQw== X-Gm-Message-State: AOAM533Tvrnq17rkOAKUzgWg3iBjmyCbiJuWP4tfGFnMKN5ErcIYf0jb jNbyZSf+qBoT5bEeGA4QTiJtwYPTKKc= X-Google-Smtp-Source: ABdhPJzivnxdg4uwYTO9s34IycaEKC0liscUg/7SHIKGsTpDu0hLg9F4T5rLfBlKWXqlg0yGSirx9g== X-Received: by 2002:a5d:6847:: with SMTP id o7mr13249603wrw.216.1612091666004; Sun, 31 Jan 2021 03:14:26 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id 36sm23685585wrj.97.2021.01.31.03.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:14:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , Artyom Tarasenko , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Subject: [PATCH 10/10] target: Move SEMIHOSTING feature to target Kconfig Date: Sun, 31 Jan 2021 12:13:16 +0100 Message-Id: <20210131111316.232778-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131111316.232778-1-f4bug@amsat.org> References: <20210131111316.232778-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:14:32 -0000 SEMIHOSTING is an architecture feature, move its declaration to each target/ARCH/. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/lm32-softmmu.mak | 2 -- default-configs/devices/m68k-softmmu.mak | 2 -- default-configs/devices/mips-softmmu-common.mak | 3 --- default-configs/devices/nios2-softmmu.mak | 2 -- default-configs/devices/unicore32-softmmu.mak | 1 - default-configs/devices/xtensa-softmmu.mak | 2 -- target/lm32/Kconfig | 1 + target/m68k/Kconfig | 1 + target/mips/Kconfig | 1 + target/nios2/Kconfig | 1 + target/unicore32/Kconfig | 1 + target/xtensa/Kconfig | 1 + 12 files changed, 6 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/lm32-softmmu.mak b/default-configs/devices/lm32-softmmu.mak index 1bce3f6e8b6..1f69795b749 100644 --- a/default-configs/devices/lm32-softmmu.mak +++ b/default-configs/devices/lm32-softmmu.mak @@ -4,8 +4,6 @@ # #CONFIG_MILKYMIST_TMU2=n # disabling it actually causes compile-time failures -CONFIG_SEMIHOSTING=y - # Boards: # CONFIG_LM32_EVR=y diff --git a/default-configs/devices/m68k-softmmu.mak b/default-configs/devices/m68k-softmmu.mak index 6629fd2aa33..4fef4bd731d 100644 --- a/default-configs/devices/m68k-softmmu.mak +++ b/default-configs/devices/m68k-softmmu.mak @@ -1,7 +1,5 @@ # Default configuration for m68k-softmmu -CONFIG_SEMIHOSTING=y - # Boards: # CONFIG_AN5206=y diff --git a/default-configs/devices/mips-softmmu-common.mak b/default-configs/devices/mips-softmmu-common.mak index ea78fe72759..af652ec7bdd 100644 --- a/default-configs/devices/mips-softmmu-common.mak +++ b/default-configs/devices/mips-softmmu-common.mak @@ -1,8 +1,5 @@ # Common mips*-softmmu CONFIG defines -# CONFIG_SEMIHOSTING is always required on this architecture -CONFIG_SEMIHOSTING=y - CONFIG_ISA_BUS=y CONFIG_PCI=y CONFIG_PCI_DEVICES=y diff --git a/default-configs/devices/nios2-softmmu.mak b/default-configs/devices/nios2-softmmu.mak index 1bc4082ea99..e130d024e62 100644 --- a/default-configs/devices/nios2-softmmu.mak +++ b/default-configs/devices/nios2-softmmu.mak @@ -1,7 +1,5 @@ # Default configuration for nios2-softmmu -CONFIG_SEMIHOSTING=y - # Boards: # CONFIG_NIOS2_10M50=y diff --git a/default-configs/devices/unicore32-softmmu.mak b/default-configs/devices/unicore32-softmmu.mak index 899288e3d71..0bfce48c6da 100644 --- a/default-configs/devices/unicore32-softmmu.mak +++ b/default-configs/devices/unicore32-softmmu.mak @@ -3,4 +3,3 @@ # Boards: # CONFIG_PUV3=y -CONFIG_SEMIHOSTING=y diff --git a/default-configs/devices/xtensa-softmmu.mak b/default-configs/devices/xtensa-softmmu.mak index 4fe1bf00c94..49e4c9da88c 100644 --- a/default-configs/devices/xtensa-softmmu.mak +++ b/default-configs/devices/xtensa-softmmu.mak @@ -1,7 +1,5 @@ # Default configuration for Xtensa -CONFIG_SEMIHOSTING=y - # Boards: # CONFIG_XTENSA_SIM=y diff --git a/target/lm32/Kconfig b/target/lm32/Kconfig index 09de5b703a3..286710fd47b 100644 --- a/target/lm32/Kconfig +++ b/target/lm32/Kconfig @@ -1,2 +1,3 @@ config LM32 bool + select SEMIHOSTING diff --git a/target/m68k/Kconfig b/target/m68k/Kconfig index 23debad519a..9eae71486ff 100644 --- a/target/m68k/Kconfig +++ b/target/m68k/Kconfig @@ -1,2 +1,3 @@ config M68K bool + select SEMIHOSTING diff --git a/target/mips/Kconfig b/target/mips/Kconfig index 6adf1453548..eb19c94c7d4 100644 --- a/target/mips/Kconfig +++ b/target/mips/Kconfig @@ -1,5 +1,6 @@ config MIPS bool + select SEMIHOSTING config MIPS64 bool diff --git a/target/nios2/Kconfig b/target/nios2/Kconfig index 1529ab8950d..c65550c861a 100644 --- a/target/nios2/Kconfig +++ b/target/nios2/Kconfig @@ -1,2 +1,3 @@ config NIOS2 bool + select SEMIHOSTING diff --git a/target/unicore32/Kconfig b/target/unicore32/Kconfig index 62c9d10b38f..c699d5238ea 100644 --- a/target/unicore32/Kconfig +++ b/target/unicore32/Kconfig @@ -1,2 +1,3 @@ config UNICORE32 bool + select SEMIHOSTING diff --git a/target/xtensa/Kconfig b/target/xtensa/Kconfig index a3c8dc7f6d7..5e46049262d 100644 --- a/target/xtensa/Kconfig +++ b/target/xtensa/Kconfig @@ -1,2 +1,3 @@ config XTENSA bool + select SEMIHOSTING -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:40:38 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6B5q-0006Tt-FK for mharc-qemu-arm@gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+3Nd22psx3BA6b2UgCxA5Llk29z9FeosWF7EXjokeME=; b=YKVrA50q+farFoKwOrteszy6/QZrqvgrCOOFG/vbZFq9UJ9Phmkk87tNmuxPrqa/w1 ioGJMf0R0NYU3i+d5dum+gfE1+3cIOkTBz//Adrf3zi1tAJqIhP/vqbDdW6XuuzIn5AI GPdNz7Ef6thRuOKQgzAs93DOSxSXY/MTEzTBtoFswDMuKW+FwiKoRtnJk5ekFnusPLMD +rbHuIMctWTtPmlccY1c85y//DPsi4Wj5RapOIQ2b5At5XR2ckrHB4jXkOXOLbwG01Bb 10Y580OPG/zbid+gET43wkDdD5TeQ3krANYCvnpgjQqHd8GVGTZyMyEDnk9kJ7E/hDmZ 0/GA== X-Gm-Message-State: AOAM530BycKj0TTiyC1HP0zdNejavaTUoIamhXOP5BFixEA4fpdupR2m yLrDOPP4GYhqZZgC12FMhB9vdX86APkydvD9GNQ= X-Google-Smtp-Source: ABdhPJyF+o+xmbWvH1gmE2N3KoqkYGCiOmOr5dAulcgi+Ufvs+lEN+ucEyAq4g2U5u8da2YaTyZDsk6uoxnGxD5U/fo= X-Received: by 2002:a37:e10b:: with SMTP id c11mr11551105qkm.176.1612093212344; Sun, 31 Jan 2021 03:40:12 -0800 (PST) MIME-Version: 1.0 References: <20210131111316.232778-1-f4bug@amsat.org> <20210131111316.232778-6-f4bug@amsat.org> In-Reply-To: <20210131111316.232778-6-f4bug@amsat.org> From: Artyom Tarasenko Date: Sun, 31 Jan 2021 12:40:00 +0100 Message-ID: Subject: Re: [PATCH 05/10] meson: Introduce target-specific Kconfig To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Sarah Harris , Max Filippov , qemu-block@nongnu.org, "Michael S. Tsirkin" , Eduardo Habkost , Laurent Vivier , Yoshinori Sato , qemu-s390x@nongnu.org, Richard Henderson , Anthony Green , Kevin Wolf , Max Reitz , Chris Wulff , Guan Xuetao , qemu-riscv@nongnu.org, David Hildenbrand , qemu-arm@nongnu.org, Marcel Apfelbaum , Mark Cave-Ayland , Michael Walle , Greg Kurz , qemu-ppc@nongnu.org, Peter Maydell , Stafford Horne , Cornelia Huck , Marek Vasut , Aleksandar Rikalo , Sagar Karandikar , Bastian Koppelmann , Jiaxun Yang , "Edgar E. Iglesias" , Thomas Huth , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Palmer Dabbelt , Michael Rolnik , Aurelien Jarno , Alistair Francis , David Gibson Content-Type: multipart/alternative; boundary="00000000000044447605ba30b361" Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=a.tarasenko@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:40:36 -0000 --00000000000044447605ba30b361 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =D0=B2=D1=81, 31 =D1=8F=D0=BD=D0=B2. 2021 =D0=B3., 12:13 Philippe Mathieu-D= aud=C3=A9 : > Add a target-specific Kconfig. > > Target foo now has CONFIG_FOO defined. > > Two architecture have a particularity, ARM and MIPS: > their 64-bit version include the 32-bit subset. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > For SPARC part: Acked-by: Artyom Tarasenko --- > I suppose X86_64 should also select I386? > No clue about PPC/RISCV. > --- > meson.build | 3 ++- > Kconfig | 1 + > target/Kconfig | 23 +++++++++++++++++++++++ > target/alpha/Kconfig | 2 ++ > target/arm/Kconfig | 6 ++++++ > target/avr/Kconfig | 2 ++ > target/cris/Kconfig | 2 ++ > target/hppa/Kconfig | 2 ++ > target/i386/Kconfig | 5 +++++ > target/lm32/Kconfig | 2 ++ > target/m68k/Kconfig | 2 ++ > target/microblaze/Kconfig | 2 ++ > target/mips/Kconfig | 6 ++++++ > target/moxie/Kconfig | 2 ++ > target/nios2/Kconfig | 2 ++ > target/openrisc/Kconfig | 2 ++ > target/ppc/Kconfig | 5 +++++ > target/riscv/Kconfig | 5 +++++ > target/rx/Kconfig | 2 ++ > target/s390x/Kconfig | 2 ++ > target/sh4/Kconfig | 2 ++ > target/sparc/Kconfig | 5 +++++ > target/tilegx/Kconfig | 2 ++ > target/tricore/Kconfig | 2 ++ > target/unicore32/Kconfig | 2 ++ > target/xtensa/Kconfig | 2 ++ > 26 files changed, 92 insertions(+), 1 deletion(-) > create mode 100644 target/Kconfig > create mode 100644 target/alpha/Kconfig > create mode 100644 target/arm/Kconfig > create mode 100644 target/avr/Kconfig > create mode 100644 target/cris/Kconfig > create mode 100644 target/hppa/Kconfig > create mode 100644 target/i386/Kconfig > create mode 100644 target/lm32/Kconfig > create mode 100644 target/m68k/Kconfig > create mode 100644 target/microblaze/Kconfig > create mode 100644 target/mips/Kconfig > create mode 100644 target/moxie/Kconfig > create mode 100644 target/nios2/Kconfig > create mode 100644 target/openrisc/Kconfig > create mode 100644 target/ppc/Kconfig > create mode 100644 target/riscv/Kconfig > create mode 100644 target/rx/Kconfig > create mode 100644 target/s390x/Kconfig > create mode 100644 target/sh4/Kconfig > create mode 100644 target/sparc/Kconfig > create mode 100644 target/tilegx/Kconfig > create mode 100644 target/tricore/Kconfig > create mode 100644 target/unicore32/Kconfig > create mode 100644 target/xtensa/Kconfig > > diff --git a/meson.build b/meson.build > index f00b7754fd4..a2dda0ce95e 100644 > --- a/meson.build > +++ b/meson.build > @@ -1322,7 +1322,8 @@ > command: [minikconf, > get_option('default_devices') ? '--defconfig' : > '--allnoconfig', > config_devices_mak, '@DEPFILE@', '@INPUT@', > - host_kconfig, accel_kconfig]) > + host_kconfig, accel_kconfig, > + 'CONFIG_' + config_target['TARGET_ARCH'].to_upper() + > '=3Dy']) > > config_devices_data =3D configuration_data() > config_devices =3D keyval.load(config_devices_mak) > diff --git a/Kconfig b/Kconfig > index bf694c42afe..c01e261e4e9 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -1,4 +1,5 @@ > source Kconfig.host > source backends/Kconfig > source accel/Kconfig > +source target/Kconfig > source hw/Kconfig > diff --git a/target/Kconfig b/target/Kconfig > new file mode 100644 > index 00000000000..a6f719f223a > --- /dev/null > +++ b/target/Kconfig > @@ -0,0 +1,23 @@ > +source alpha/Kconfig > +source arm/Kconfig > +source avr/Kconfig > +source cris/Kconfig > +source hppa/Kconfig > +source i386/Kconfig > +source lm32/Kconfig > +source m68k/Kconfig > +source microblaze/Kconfig > +source mips/Kconfig > +source moxie/Kconfig > +source nios2/Kconfig > +source openrisc/Kconfig > +source ppc/Kconfig > +source riscv/Kconfig > +source rx/Kconfig > +source s390x/Kconfig > +source sh4/Kconfig > +source sparc/Kconfig > +source tilegx/Kconfig > +source tricore/Kconfig > +source unicore32/Kconfig > +source xtensa/Kconfig > diff --git a/target/alpha/Kconfig b/target/alpha/Kconfig > new file mode 100644 > index 00000000000..267222c05b8 > --- /dev/null > +++ b/target/alpha/Kconfig > @@ -0,0 +1,2 @@ > +config ALPHA > + bool > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > new file mode 100644 > index 00000000000..3f3394a22b2 > --- /dev/null > +++ b/target/arm/Kconfig > @@ -0,0 +1,6 @@ > +config ARM > + bool > + > +config AARCH64 > + bool > + select ARM > diff --git a/target/avr/Kconfig b/target/avr/Kconfig > new file mode 100644 > index 00000000000..155592d3537 > --- /dev/null > +++ b/target/avr/Kconfig > @@ -0,0 +1,2 @@ > +config AVR > + bool > diff --git a/target/cris/Kconfig b/target/cris/Kconfig > new file mode 100644 > index 00000000000..3fdc309fbbd > --- /dev/null > +++ b/target/cris/Kconfig > @@ -0,0 +1,2 @@ > +config CRIS > + bool > diff --git a/target/hppa/Kconfig b/target/hppa/Kconfig > new file mode 100644 > index 00000000000..395a35d799c > --- /dev/null > +++ b/target/hppa/Kconfig > @@ -0,0 +1,2 @@ > +config HPPA > + bool > diff --git a/target/i386/Kconfig b/target/i386/Kconfig > new file mode 100644 > index 00000000000..ce6968906ee > --- /dev/null > +++ b/target/i386/Kconfig > @@ -0,0 +1,5 @@ > +config I386 > + bool > + > +config X86_64 > + bool > diff --git a/target/lm32/Kconfig b/target/lm32/Kconfig > new file mode 100644 > index 00000000000..09de5b703a3 > --- /dev/null > +++ b/target/lm32/Kconfig > @@ -0,0 +1,2 @@ > +config LM32 > + bool > diff --git a/target/m68k/Kconfig b/target/m68k/Kconfig > new file mode 100644 > index 00000000000..23debad519a > --- /dev/null > +++ b/target/m68k/Kconfig > @@ -0,0 +1,2 @@ > +config M68K > + bool > diff --git a/target/microblaze/Kconfig b/target/microblaze/Kconfig > new file mode 100644 > index 00000000000..a5410d9218d > --- /dev/null > +++ b/target/microblaze/Kconfig > @@ -0,0 +1,2 @@ > +config MICROBLAZE > + bool > diff --git a/target/mips/Kconfig b/target/mips/Kconfig > new file mode 100644 > index 00000000000..6adf1453548 > --- /dev/null > +++ b/target/mips/Kconfig > @@ -0,0 +1,6 @@ > +config MIPS > + bool > + > +config MIPS64 > + bool > + select MIPS > diff --git a/target/moxie/Kconfig b/target/moxie/Kconfig > new file mode 100644 > index 00000000000..52391bbd289 > --- /dev/null > +++ b/target/moxie/Kconfig > @@ -0,0 +1,2 @@ > +config MOXIE > + bool > diff --git a/target/nios2/Kconfig b/target/nios2/Kconfig > new file mode 100644 > index 00000000000..1529ab8950d > --- /dev/null > +++ b/target/nios2/Kconfig > @@ -0,0 +1,2 @@ > +config NIOS2 > + bool > diff --git a/target/openrisc/Kconfig b/target/openrisc/Kconfig > new file mode 100644 > index 00000000000..e0da4ac1dfc > --- /dev/null > +++ b/target/openrisc/Kconfig > @@ -0,0 +1,2 @@ > +config OPENRISC > + bool > diff --git a/target/ppc/Kconfig b/target/ppc/Kconfig > new file mode 100644 > index 00000000000..3ff152051a3 > --- /dev/null > +++ b/target/ppc/Kconfig > @@ -0,0 +1,5 @@ > +config PPC > + bool > + > +config PPC64 > + bool > diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig > new file mode 100644 > index 00000000000..b9e5932f13f > --- /dev/null > +++ b/target/riscv/Kconfig > @@ -0,0 +1,5 @@ > +config RISCV32 > + bool > + > +config RISCV64 > + bool > diff --git a/target/rx/Kconfig b/target/rx/Kconfig > new file mode 100644 > index 00000000000..aceb5ed28fe > --- /dev/null > +++ b/target/rx/Kconfig > @@ -0,0 +1,2 @@ > +config RX > + bool > diff --git a/target/s390x/Kconfig b/target/s390x/Kconfig > new file mode 100644 > index 00000000000..72da48136c6 > --- /dev/null > +++ b/target/s390x/Kconfig > @@ -0,0 +1,2 @@ > +config S390X > + bool > diff --git a/target/sh4/Kconfig b/target/sh4/Kconfig > new file mode 100644 > index 00000000000..2397c860280 > --- /dev/null > +++ b/target/sh4/Kconfig > @@ -0,0 +1,2 @@ > +config SH4 > + bool > diff --git a/target/sparc/Kconfig b/target/sparc/Kconfig > new file mode 100644 > index 00000000000..70cc0f3a210 > --- /dev/null > +++ b/target/sparc/Kconfig > @@ -0,0 +1,5 @@ > +config SPARC > + bool > + > +config SPARC64 > + bool > diff --git a/target/tilegx/Kconfig b/target/tilegx/Kconfig > new file mode 100644 > index 00000000000..aad882826ab > --- /dev/null > +++ b/target/tilegx/Kconfig > @@ -0,0 +1,2 @@ > +config TILEGX > + bool > diff --git a/target/tricore/Kconfig b/target/tricore/Kconfig > new file mode 100644 > index 00000000000..93134093093 > --- /dev/null > +++ b/target/tricore/Kconfig > @@ -0,0 +1,2 @@ > +config TRICORE > + bool > diff --git a/target/unicore32/Kconfig b/target/unicore32/Kconfig > new file mode 100644 > index 00000000000..62c9d10b38f > --- /dev/null > +++ b/target/unicore32/Kconfig > @@ -0,0 +1,2 @@ > +config UNICORE32 > + bool > diff --git a/target/xtensa/Kconfig b/target/xtensa/Kconfig > new file mode 100644 > index 00000000000..a3c8dc7f6d7 > --- /dev/null > +++ b/target/xtensa/Kconfig > @@ -0,0 +1,2 @@ > +config XTENSA > + bool > -- > 2.26.2 > > --00000000000044447605ba30b361 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=D0=B2=D1=81, 31 =D1=8F=D0=BD=D0=B2. 2021 =D0=B3., 12:= 13 Philippe Mathieu-Daud=C3=A9 <f4bug= @amsat.org>:
Add a target-sp= ecific Kconfig.

Target foo now has CONFIG_FOO defined.

Two architecture have a particularity, ARM and MIPS:
their 64-bit version include the 32-bit subset.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>

=
For SPARC part:
Acked-by: Artyom T= arasenko <atar4qemu@gmail.com= >

---
I suppose X86_64 should also select I386?
No clue about PPC/RISCV.
---
=C2=A0meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 3 ++-
=C2=A0Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0|=C2=A0 1 +
=C2=A0target/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 23 ++++++++= +++++++++++++++
=C2=A0target/alpha/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 6 ++++++
=C2=A0target/avr/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/cris/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/hppa/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/i386/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 5 +++++
=C2=A0target/lm32/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/m68k/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/microblaze/Kconfig |=C2=A0 2 ++
=C2=A0target/mips/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 6 ++++++
=C2=A0target/moxie/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/nios2/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/openrisc/Kconfig=C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/ppc/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 5 +++++
=C2=A0target/riscv/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 5 +++++
=C2=A0target/rx/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/s390x/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/sh4/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/sparc/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 5 +++++
=C2=A0target/tilegx/Kconfig=C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0target/tricore/Kconfig=C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/unicore32/Kconfig=C2=A0 |=C2=A0 2 ++
=C2=A0target/xtensa/Kconfig=C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A026 files changed, 92 insertions(+), 1 deletion(-)
=C2=A0create mode 100644 target/Kconfig
=C2=A0create mode 100644 target/alpha/Kconfig
=C2=A0create mode 100644 target/arm/Kconfig
=C2=A0create mode 100644 target/avr/Kconfig
=C2=A0create mode 100644 target/cris/Kconfig
=C2=A0create mode 100644 target/hppa/Kconfig
=C2=A0create mode 100644 target/i386/Kconfig
=C2=A0create mode 100644 target/lm32/Kconfig
=C2=A0create mode 100644 target/m68k/Kconfig
=C2=A0create mode 100644 target/microblaze/Kconfig
=C2=A0create mode 100644 target/mips/Kconfig
=C2=A0create mode 100644 target/moxie/Kconfig
=C2=A0create mode 100644 target/nios2/Kconfig
=C2=A0create mode 100644 target/openrisc/Kconfig
=C2=A0create mode 100644 target/ppc/Kconfig
=C2=A0create mode 100644 target/riscv/Kconfig
=C2=A0create mode 100644 target/rx/Kconfig
=C2=A0create mode 100644 target/s390x/Kconfig
=C2=A0create mode 100644 target/sh4/Kconfig
=C2=A0create mode 100644 target/sparc/Kconfig
=C2=A0create mode 100644 target/tilegx/Kconfig
=C2=A0create mode 100644 target/tricore/Kconfig
=C2=A0create mode 100644 target/unicore32/Kconfig
=C2=A0create mode 100644 target/xtensa/Kconfig

diff --git a/meson.build b/meson.build
index f00b7754fd4..a2dda0ce95e 100644
--- a/meson.build
+++ b/meson.build
@@ -1322,7 +1322,8 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0command: [minikconf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0get_option(&#= 39;default_devices') ? '--defconfig' : '--allnoconfig',=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config_device= s_mak, '@DEPFILE@', '@INPUT@',
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 host_kconfig, acce= l_kconfig])
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 host_kconfig, acce= l_kconfig,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 'CONFIG_' = + config_target['TARGET_ARCH'].to_upper() + '=3Dy'])

=C2=A0 =C2=A0 =C2=A0config_devices_data =3D configuration_data()
=C2=A0 =C2=A0 =C2=A0config_devices =3D keyval.load(config_devices_mak)
diff --git a/Kconfig b/Kconfig
index bf694c42afe..c01e261e4e9 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,4 +1,5 @@
=C2=A0source Kconfig.host
=C2=A0source backends/Kconfig
=C2=A0source accel/Kconfig
+source target/Kconfig
=C2=A0source hw/Kconfig
diff --git a/target/Kconfig b/target/Kconfig
new file mode 100644
index 00000000000..a6f719f223a
--- /dev/null
+++ b/target/Kconfig
@@ -0,0 +1,23 @@
+source alpha/Kconfig
+source arm/Kconfig
+source avr/Kconfig
+source cris/Kconfig
+source hppa/Kconfig
+source i386/Kconfig
+source lm32/Kconfig
+source m68k/Kconfig
+source microblaze/Kconfig
+source mips/Kconfig
+source moxie/Kconfig
+source nios2/Kconfig
+source openrisc/Kconfig
+source ppc/Kconfig
+source riscv/Kconfig
+source rx/Kconfig
+source s390x/Kconfig
+source sh4/Kconfig
+source sparc/Kconfig
+source tilegx/Kconfig
+source tricore/Kconfig
+source unicore32/Kconfig
+source xtensa/Kconfig
diff --git a/target/alpha/Kconfig b/target/alpha/Kconfig
new file mode 100644
index 00000000000..267222c05b8
--- /dev/null
+++ b/target/alpha/Kconfig
@@ -0,0 +1,2 @@
+config ALPHA
+=C2=A0 =C2=A0 bool
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
new file mode 100644
index 00000000000..3f3394a22b2
--- /dev/null
+++ b/target/arm/Kconfig
@@ -0,0 +1,6 @@
+config ARM
+=C2=A0 =C2=A0 bool
+
+config AARCH64
+=C2=A0 =C2=A0 bool
+=C2=A0 =C2=A0 select ARM
diff --git a/target/avr/Kconfig b/target/avr/Kconfig
new file mode 100644
index 00000000000..155592d3537
--- /dev/null
+++ b/target/avr/Kconfig
@@ -0,0 +1,2 @@
+config AVR
+=C2=A0 =C2=A0 bool
diff --git a/target/cris/Kconfig b/target/cris/Kconfig
new file mode 100644
index 00000000000..3fdc309fbbd
--- /dev/null
+++ b/target/cris/Kconfig
@@ -0,0 +1,2 @@
+config CRIS
+=C2=A0 =C2=A0 bool
diff --git a/target/hppa/Kconfig b/target/hppa/Kconfig
new file mode 100644
index 00000000000..395a35d799c
--- /dev/null
+++ b/target/hppa/Kconfig
@@ -0,0 +1,2 @@
+config HPPA
+=C2=A0 =C2=A0 bool
diff --git a/target/i386/Kconfig b/target/i386/Kconfig
new file mode 100644
index 00000000000..ce6968906ee
--- /dev/null
+++ b/target/i386/Kconfig
@@ -0,0 +1,5 @@
+config I386
+=C2=A0 =C2=A0 bool
+
+config X86_64
+=C2=A0 =C2=A0 bool
diff --git a/target/lm32/Kconfig b/target/lm32/Kconfig
new file mode 100644
index 00000000000..09de5b703a3
--- /dev/null
+++ b/target/lm32/Kconfig
@@ -0,0 +1,2 @@
+config LM32
+=C2=A0 =C2=A0 bool
diff --git a/target/m68k/Kconfig b/target/m68k/Kconfig
new file mode 100644
index 00000000000..23debad519a
--- /dev/null
+++ b/target/m68k/Kconfig
@@ -0,0 +1,2 @@
+config M68K
+=C2=A0 =C2=A0 bool
diff --git a/target/microblaze/Kconfig b/target/microblaze/Kconfig
new file mode 100644
index 00000000000..a5410d9218d
--- /dev/null
+++ b/target/microblaze/Kconfig
@@ -0,0 +1,2 @@
+config MICROBLAZE
+=C2=A0 =C2=A0 bool
diff --git a/target/mips/Kconfig b/target/mips/Kconfig
new file mode 100644
index 00000000000..6adf1453548
--- /dev/null
+++ b/target/mips/Kconfig
@@ -0,0 +1,6 @@
+config MIPS
+=C2=A0 =C2=A0 bool
+
+config MIPS64
+=C2=A0 =C2=A0 bool
+=C2=A0 =C2=A0 select MIPS
diff --git a/target/moxie/Kconfig b/target/moxie/Kconfig
new file mode 100644
index 00000000000..52391bbd289
--- /dev/null
+++ b/target/moxie/Kconfig
@@ -0,0 +1,2 @@
+config MOXIE
+=C2=A0 =C2=A0 bool
diff --git a/target/nios2/Kconfig b/target/nios2/Kconfig
new file mode 100644
index 00000000000..1529ab8950d
--- /dev/null
+++ b/target/nios2/Kconfig
@@ -0,0 +1,2 @@
+config NIOS2
+=C2=A0 =C2=A0 bool
diff --git a/target/openrisc/Kconfig b/target/openrisc/Kconfig
new file mode 100644
index 00000000000..e0da4ac1dfc
--- /dev/null
+++ b/target/openrisc/Kconfig
@@ -0,0 +1,2 @@
+config OPENRISC
+=C2=A0 =C2=A0 bool
diff --git a/target/ppc/Kconfig b/target/ppc/Kconfig
new file mode 100644
index 00000000000..3ff152051a3
--- /dev/null
+++ b/target/ppc/Kconfig
@@ -0,0 +1,5 @@
+config PPC
+=C2=A0 =C2=A0 bool
+
+config PPC64
+=C2=A0 =C2=A0 bool
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
new file mode 100644
index 00000000000..b9e5932f13f
--- /dev/null
+++ b/target/riscv/Kconfig
@@ -0,0 +1,5 @@
+config RISCV32
+=C2=A0 =C2=A0 bool
+
+config RISCV64
+=C2=A0 =C2=A0 bool
diff --git a/target/rx/Kconfig b/target/rx/Kconfig
new file mode 100644
index 00000000000..aceb5ed28fe
--- /dev/null
+++ b/target/rx/Kconfig
@@ -0,0 +1,2 @@
+config RX
+=C2=A0 =C2=A0 bool
diff --git a/target/s390x/Kconfig b/target/s390x/Kconfig
new file mode 100644
index 00000000000..72da48136c6
--- /dev/null
+++ b/target/s390x/Kconfig
@@ -0,0 +1,2 @@
+config S390X
+=C2=A0 =C2=A0 bool
diff --git a/target/sh4/Kconfig b/target/sh4/Kconfig
new file mode 100644
index 00000000000..2397c860280
--- /dev/null
+++ b/target/sh4/Kconfig
@@ -0,0 +1,2 @@
+config SH4
+=C2=A0 =C2=A0 bool
diff --git a/target/sparc/Kconfig b/target/sparc/Kconfig
new file mode 100644
index 00000000000..70cc0f3a210
--- /dev/null
+++ b/target/sparc/Kconfig
@@ -0,0 +1,5 @@
+config SPARC
+=C2=A0 =C2=A0 bool
+
+config SPARC64
+=C2=A0 =C2=A0 bool
diff --git a/target/tilegx/Kconfig b/target/tilegx/Kconfig
new file mode 100644
index 00000000000..aad882826ab
--- /dev/null
+++ b/target/tilegx/Kconfig
@@ -0,0 +1,2 @@
+config TILEGX
+=C2=A0 =C2=A0 bool
diff --git a/target/tricore/Kconfig b/target/tricore/Kconfig
new file mode 100644
index 00000000000..93134093093
--- /dev/null
+++ b/target/tricore/Kconfig
@@ -0,0 +1,2 @@
+config TRICORE
+=C2=A0 =C2=A0 bool
diff --git a/target/unicore32/Kconfig b/target/unicore32/Kconfig
new file mode 100644
index 00000000000..62c9d10b38f
--- /dev/null
+++ b/target/unicore32/Kconfig
@@ -0,0 +1,2 @@
+config UNICORE32
+=C2=A0 =C2=A0 bool
diff --git a/target/xtensa/Kconfig b/target/xtensa/Kconfig
new file mode 100644
index 00000000000..a3c8dc7f6d7
--- /dev/null
+++ b/target/xtensa/Kconfig
@@ -0,0 +1,2 @@
+config XTENSA
+=C2=A0 =C2=A0 bool
--
2.26.2

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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id g194sm17384967wme.39.2021.01.31.03.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 00/11] Support disabling TCG on ARM (part 2) Date: Sun, 31 Jan 2021 12:50:11 +0100 Message-Id: <20210131115022.242570-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:50:31 -0000 Cover from Samuel Ortiz from (part 1) [1]:=0D =0D This patchset allows for building and running ARM targets with TCG=0D disabled. [...]=0D =0D The rationale behind this work comes from the NEMU project where=0D we're trying to only support x86 and ARM 64-bit architectures,=0D without including the TCG code base. We can only do so if we can=0D build and run ARM binaries with TCG disabled.=0D =0D Peter mentioned in v5 [6] that since 32-bit host has been removed,=0D we have to remove v7 targets. This is not done in this series, as=0D linking succeeds, and there is enough material to review (no need=0D to spend time on that extra patch if the current approach is not=0D accepted).=0D =0D CI: https://gitlab.com/philmd/qemu/-/pipelines/249272441=0D =0D v6:=0D - rebased on "target/arm/Kconfig" series=0D - introduce/use tcg_builtin() for realview machines=0D =0D v5:=0D - addressed Paolo/Richard/Thomas review comments from v4 [5].=0D =0D v4 almost 2 years later... [2]:=0D - Rebased on Meson=0D - Addressed Richard review comments=0D - Addressed Claudio review comments=0D =0D v3 almost 18 months later [3]:=0D - Rebased=0D - Addressed Thomas review comments=0D - Added Travis-CI job to keep building --disable-tcg on ARM=0D =0D v2 [4]:=0D - Addressed review comments from Richard and Thomas from v1 [1]=0D =0D Regards,=0D =0D Phil.=0D =0D [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html=0D [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html=0D [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html=0D [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html=0D [5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html=0D [6]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777669.html=0D =0D Based-on: <20210131111316.232778-1-f4bug@amsat.org>=0D "target: Provide target-specific Kconfig"=0D =0D Philippe Mathieu-Daud=C3=A9 (9):=0D sysemu/tcg: Introduce tcg_builtin() helper=0D exec: Restrict TCG specific headers=0D target/arm: Restrict ARMv4 cpus to TCG accel=0D target/arm: Restrict ARMv5 cpus to TCG accel=0D target/arm: Restrict ARMv6 cpus to TCG accel=0D target/arm: Restrict ARMv7 R-profile cpus to TCG accel=0D target/arm: Restrict ARMv7 M-profile cpus to TCG accel=0D target/arm: Reorder meson.build rules=0D .travis.yml: Add a KVM-only Aarch64 job=0D =0D Samuel Ortiz (1):=0D target/arm: Do not build TCG objects when TCG is off=0D =0D Thomas Huth (1):=0D target/arm: Make m_helper.c optional via CONFIG_ARM_V7M=0D =0D default-configs/devices/aarch64-softmmu.mak | 1 -=0D default-configs/devices/arm-softmmu.mak | 27 --------=0D include/exec/helper-proto.h | 2 +=0D include/sysemu/tcg.h | 2 +=0D target/arm/cpu.h | 12 ----=0D hw/arm/realview.c | 7 +-=0D target/arm/cpu_tcg.c | 4 +-=0D target/arm/helper.c | 7 --=0D target/arm/m_helper-stub.c | 73 +++++++++++++++++++++=0D tests/qtest/cdrom-test.c | 6 +-=0D .travis.yml | 32 +++++++++=0D hw/arm/Kconfig | 38 +++++++++++=0D target/arm/Kconfig | 17 +++++=0D target/arm/meson.build | 28 +++++---=0D 14 files changed, 196 insertions(+), 60 deletions(-)=0D create mode 100644 target/arm/m_helper-stub.c=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 06:50:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BFV-0001t6-NA for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:50:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BFT-0001r2-Rq; Sun, 31 Jan 2021 06:50:35 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:32793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFR-0005Fo-Uq; Sun, 31 Jan 2021 06:50:35 -0500 Received: by mail-wr1-x429.google.com with SMTP id 7so13527428wrz.0; Sun, 31 Jan 2021 03:50:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NbTS4eSvhYMRXHU2vVjE8jfBdk95n+pM+UWftFmVvfU=; b=h1LzEJAXnr2fpxrCr74qTa92E0dAQb5YiEWfKSWN16Ei7mKBJSZQMVHDtkutWVDdYD QqYbWZZHSoxyuWQZ0pIEs9v6rLkDln3JPGHTftQ6RA5bwJSd93SlGR2L+ITnjWAutK0g tIS1BhDZkCAnE9y0tqhEZkdrRtZlLeW8E5mcViIcVkm0C6Wv07Py5VZXtuO1xTDY3Dc7 mvaI5qvAC6+T8+Mvqn86Ru7LvFhZ9yPMrtGUe0qq02OGSlaFwVC0zKhpVON0ICphi4MA y3ISRBAX0Z+MYNv5DS5/to54WQKzMmf73GoOvsshWv3hWIjt2qa4xFrh33b18Zx6xf8E pYWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NbTS4eSvhYMRXHU2vVjE8jfBdk95n+pM+UWftFmVvfU=; b=V7bhBnT73P1G0o/xzmCyKwIMpdzF6NbD58/Yv2ZN5e273OOI2j/gnXe9ZmE5FR102R oKdej8wNN3S1hOQlJXE6JnufW3C81VoPFDT9SE1TVQK/bFZ1jlBZJVBr6WxxYGKDc7w3 ea+1r1Dn7eZvtuJEpETkzs4l5yoPUwHG/W0E++kxtF8SkJNimGMoFLhZ/9+aOSW9WwXa 9cQZYl2NO73rdLh46dsEImpvD61q9uHVN6IHTYh3E7lyw5cp/HCJIEBsx0oqiTstGDMM vGtOCcQTc+3Q6pj294sD5jeMYMqEtTO4t68m9ilQBUuYRGpljXiy1kFRj3397a50JHgR SJqQ== X-Gm-Message-State: AOAM530s1Eos9kLUsRiA2Tu2n0XP71XtwPPQoZ1oXYe28IvIFaOcnaKY 2DmkQHEeyYaj2pxjJyepsZT47/zr33I= X-Google-Smtp-Source: ABdhPJzbicD1HJnXpjT27xzPC9x3I2AWZtVjzXvYLMRzjxZrSarnOD5x4M7qz2f/ytk+RI73IOJ3pg== X-Received: by 2002:a5d:458a:: with SMTP id p10mr13399523wrq.168.1612093831543; Sun, 31 Jan 2021 03:50:31 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id c62sm5346752wmd.43.2021.01.31.03.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Markus Armbruster Subject: [PATCH v6 01/11] sysemu/tcg: Introduce tcg_builtin() helper Date: Sun, 31 Jan 2021 12:50:12 +0100 Message-Id: <20210131115022.242570-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:50:36 -0000 Modules are registered early with type_register_static(). We would like to call tcg_enabled() when registering QOM types, but tcg_enabled() returns tcg_allowed which is a runtime property initialized later (See commit 2f181fbd5a9 which introduced the MachineInitPhase in "hw/qdev-core.h" representing the different phases of machine initialization and commit 0427b6257e2 which document the initialization order). As we are only interested if the TCG accelerator is builtin, regardless of being enabled, introduce the tcg_builtin() helper. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Markus Armbruster --- include/sysemu/tcg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 00349fb18a7..6ac5c2ca89d 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -13,8 +13,10 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); #ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) +#define tcg_builtin() 1 #else #define tcg_enabled() 0 +#define tcg_builtin() 0 #endif #endif -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:50:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BFb-00022A-V8 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:50:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BFY-0001xJ-V1; Sun, 31 Jan 2021 06:50:40 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:34278) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFX-0005L7-7K; Sun, 31 Jan 2021 06:50:40 -0500 Received: by mail-wm1-x32c.google.com with SMTP id o10so9638786wmc.1; Sun, 31 Jan 2021 03:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VqrmhVxmrVpTinVk4e74EOokFJxAnJGleMWOvxObkGo=; b=lyvsp3J4UkNurQZJVFz9o4JYa1UA1x5dEPXNh3rSqZoz/D+ftmCq5kSipCIzpP4yYJ nSMUwmKcyyFsbqMKa8oxpCNGlXb93gGlqm4bjingFBgZuIWD7AbI0OZpdaMufJDvHG9c qC5+dIBepWCX6LFsUMA77xsp6mvys75KRB+jURkPOHD/pN99OOtyoQ9btbVCGzoyfl6G MxbJzJi5FBOYnndo2ohyVKrRVbQ75AEh0rEWOFzVWJCmjvCGgSofwmaqh36oRozeOnfA jlgBJb1qNwvqao+3AOuUECbxkneAizqC36qIYrHOlMkRF5uKw5qN2ZdR2YCXPAzeFzfO Mz/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VqrmhVxmrVpTinVk4e74EOokFJxAnJGleMWOvxObkGo=; b=EoG4wdNPzLBSq8l8lcdNcy8JiNf9/lBxipdDmxgdwUqi+mE+RvDudawafxFPa6DFwN xbysb5ajbH/MFqWIDZn0p3QDTOG4LZ6gmIgb9c4SVdEFOw9MUj81bxeTLCZ4kTsW3kwl ZGyalTrHQJaVdAxNCeW30d5Puvum1FbaFtEpjbzn3V2UhHOJnyTTG/jM2lxqoDM46YDq /UvWZdpFTGnFniBIJpPTp4CyT9ulT8N/57kWEG3fYPWW6vmD2rb8ybjryXvhn/AdlCUD CBeLSJ0Q+Hyr02SGdTuxpcXoTsBk8gpiljH5jgLjvqwn+2bpkKOE0QRaqEcUCxP69ZsH dJUg== X-Gm-Message-State: AOAM533Lov2XjxzLL7SzqnB+4rGORPMBqZiU4IlLCmepsIXVxvHP6i7b /bKL74KFQWw0UpiB0MOy204FdMIY0ao= X-Google-Smtp-Source: ABdhPJzlUZ0PoftyMhnvPgCuDfPl7bBhNXVdBlytKA4JLNnnwx1y1kPvC5kny0EUlqDJX52wkKjIyA== X-Received: by 2002:a7b:c196:: with SMTP id y22mr10912502wmi.91.1612093836938; Sun, 31 Jan 2021 03:50:36 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id a17sm19517259wrx.63.2021.01.31.03.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 02/11] exec: Restrict TCG specific headers Date: Sun, 31 Jan 2021 12:50:13 +0100 Message-Id: <20210131115022.242570-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:50:41 -0000 Fixes when building with --disable-tcg on ARM: In file included from target/arm/helper.c:16: include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory 42 | #include "tcg-runtime.h" | ^~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé --- include/exec/helper-proto.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 659f9298e8f..740bff3bb4d 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ #include "helper.h" #include "trace/generated-helpers.h" +#ifdef CONFIG_TCG #include "tcg-runtime.h" #include "plugin-helpers.h" +#endif /* CONFIG_TCG */ #undef IN_HELPER_PROTO -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:50:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BFh-0002CR-Lf for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:50:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BFe-00028x-Fz; Sun, 31 Jan 2021 06:50:46 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:42917) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFc-0005Qw-Q4; Sun, 31 Jan 2021 06:50:46 -0500 Received: by mail-wr1-x434.google.com with SMTP id c4so10793773wru.9; Sun, 31 Jan 2021 03:50:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fh28JukriQ8n71FXrOcLQmLKpZgUpaavJogE1lG2lKE=; b=V9jvv1aL3pv839Xy1/0k6WXm66MH9MuJ++7EvsG8qCa8S/wu6yqaRlsHWM/6QNB9nq otF67bI38HB/w9Q6MYBXxVOV5UBCfzchBKzB7qzo23tC+CtVSDEiuDhSZgH2dTnQIoYd 6joAcsNUIBk61d62T+9j0tEWV0NdSA6ytJkUxnBG0i3S908YNLWEon8evQ47X9B2sLl4 nYV4yaQ2owvFrejRRcFu4R05XEV7WMKV9GrqyrPq04KqW0pgCUzJ6KMZIWHx1H0HXq9X d3lwh952RSMVU6+mG+0RM+tLEOoLrQ673P9FK4aAUMuTDxUGUjXBbhRSvwjSbsfKJ1+J eQvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fh28JukriQ8n71FXrOcLQmLKpZgUpaavJogE1lG2lKE=; b=t1pHnxDdeHwVmCCaPR2yg4XDbCRrKsOqi7VOyIhHSOxjf4Ipg8is8uhVzpiLLKuKNk EL9UuHG2ENXmmOb7gPPHKV34tP1n83Q1TExkSHup2Ab9R4Fp4A2PnEWcvZ67T/7k1HI3 7oTNX8L5E9Lzjw+dbt7T/0fxR5tLc29Q+/TWc2s+R6+oienzaPYzSprL3sz+tQibxJbv L/iGghl4k4lqW8j2z7L+AD70/XlDRsw7X/6sUqfyJgqW3agOT0qTTR0GacDLeWDUGlvK o44sfPFof0YfoWiy8CuU/y3v9W9QgxKZTZP1dmdnh4nnb5zL1/KsB8FgHWeutuznvTBL NB/A== X-Gm-Message-State: AOAM531V9mhLexS1QYz+uBqDJZyDk/9ihPHUCfbFllNoI4QfyGJI0Yvv XZEgbMimp2sD0lE+7+xvtxResPlQWZE= X-Google-Smtp-Source: ABdhPJzPZYCyk9Lid3tGRWhj4ZiT3g9tiJCZJewZhjiHAEXNm3DGC368mGAO4xLutOTTbFfAQmbXoQ== X-Received: by 2002:adf:f303:: with SMTP id i3mr13248696wro.60.1612093842413; Sun, 31 Jan 2021 03:50:42 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id c18sm27536097wmk.0.2021.01.31.03.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 03/11] target/arm: Restrict ARMv4 cpus to TCG accel Date: Sun, 31 Jan 2021 12:50:14 +0100 Message-Id: <20210131115022.242570-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:50:47 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). Only enable the following ARMv4 CPUs when TCG is available: - StrongARM (SA1100/1110) - OMAP1510 (TI925T) The following machines are no more built when TCG is disabled: - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310) - sx1 Siemens SX1 (OMAP310) V2 - sx1-v1 Siemens SX1 (OMAP310) V1 Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/Kconfig | 4 ++++ target/arm/Kconfig | 4 ++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0824e9be795..6ae964c14fd 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y CONFIG_MUSICPAL=y CONFIG_MUSCA=y -CONFIG_CHEETAH=y -CONFIG_SX1=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f3ecb73a3d8..f2957b33bee 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -31,6 +31,8 @@ config ARM_VIRT config CHEETAH bool + default y if TCG && ARM + select ARM_V4 select OMAP select TSC210X @@ -249,6 +251,8 @@ config COLLIE config SX1 bool + default y if TCG && ARM + select ARM_V4 select OMAP config VERSATILE diff --git a/target/arm/Kconfig b/target/arm/Kconfig index ae89d05c7e5..811e1e81652 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -6,6 +6,10 @@ config AARCH64 bool select ARM +config ARM_V4 + bool + depends on TCG && ARM + config ARM_V7M bool select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:51:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BG3-0002N7-Au for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:51:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BFo-0002IZ-AA; Sun, 31 Jan 2021 06:50:56 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45593) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFm-0005T7-G2; Sun, 31 Jan 2021 06:50:56 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m13so13502681wro.12; Sun, 31 Jan 2021 03:50:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jAQNkZyQmguYUbpG6RAooFLTF+LkPeMScVQdPuM6a40=; b=ixKvjc/EM+COzd/8zxx92XqGNuV3/KESCLzWaBkZIRcantYLmcmpylMmMK1AJx2jFE cuGm88zp9PC+wZ+KY57F2pigz8jKDIGbtvjWcoU8aEM/nGEg27OQm5dGfgVezOdw1Gd0 1FkULN2tU2CmTtGU2cbXW4wpUoB9wJt3wC0xkiwOWN4HKbkf7ezFy/qfSmw5qWkNJafh L2NoH+RgS9jT/5Srq/FaVLqx5TFXZSmvu/NPvrbpb/stecX4jUwzkXAxNa8OGss5YV/s TVK2rJKTCYy448KHIZDG1ALx4Y0vk3f1zUClD6O1RYBuCUV4B33Liak3YWHgZxQ6JvxS +UcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jAQNkZyQmguYUbpG6RAooFLTF+LkPeMScVQdPuM6a40=; b=J4v42ZEc+BHH1rvRri22wWekmROaE4eYvPdAros0HgyupT9i+9DUmbvj/VQSA4HAaz JdFsv/0TI4Ax/FATbfEdAAV9t2oPeSjIdEnc25CCS8IM10X7ZBWWNpFxfjmfzDSjWlsx YOnKyMSiCWvh09idJNycO7wnmrmFX1nN+EEQI0JyaciIwT4c8iiVDVlkAjHpjsmD/MMS Wwbeac0hdEiELV6CtU4yuRh+Q6XM+59MdI0KD+2fJ+6hx1PpwGBPPkkw52TvYoB5Lf1O eREWL3EwK61pSnc+7bkmfrE1cnNKxzcFI5T0iz3ll2S87M1lhRcE5coqn688WRbNJbqZ NGDg== X-Gm-Message-State: AOAM533TtTMWz8sccSwEWANPWXYtSupA5kTeC+Y2Em4JK74tTbEuoJZ7 zuT6X1Vm/WeSwZao4poOF8gK7eRykBU= X-Google-Smtp-Source: ABdhPJxm51d3yxh6L+XBF7RlyMnDsyEgQnz37oiRF4PWsrAoOK263P8yLKKWDXW81l+tMCZwpYvWfw== X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr13099821wry.398.1612093848309; Sun, 31 Jan 2021 03:50:48 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id q19sm6049801wmj.23.2021.01.31.03.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 04/11] target/arm: Restrict ARMv5 cpus to TCG accel Date: Sun, 31 Jan 2021 12:50:15 +0100 Message-Id: <20210131115022.242570-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:50:56 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). Only enable the following ARMv5 CPUs when TCG is available: - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) The following machines are no more built when TCG is disabled: - akita Sharp SL-C1000 (Akita) PDA (PXA270) - ast2500-evb Aspeed AST2500 EVB (ARM1176) - ast2600-evb Aspeed AST2600 EVB (Cortex A7) - borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270) - canon-a1100 Canon PowerShot A1100 IS (ARM946) - collie Sharp SL-5500 (Collie) PDA (SA-1110) - connex Gumstix Connex (PXA255) - g220a-bmc Bytedance G220A BMC (ARM1176) - imx25-pdk ARM i.MX25 PDK board (ARM926) - integratorcp ARM Integrator/CP (ARM926EJ-S) - mainstone Mainstone II (PXA27x) - musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S) - palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S) - realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S) - romulus-bmc OpenPOWER Romulus BMC (ARM1176) - sonorapass-bmc OCP SonoraPass BMC (ARM1176) - spitz Sharp SL-C3000 (Spitz) PDA (PXA270) - supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S) - swift-bmc OpenPOWER Swift BMC (ARM1176) - tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7) - terrier Sharp SL-C3200 (Terrier) PDA (PXA270) - tosa Sharp SL-6000 (Tosa) PDA (PXA255) - verdex Gumstix Verdex (PXA270) - versatileab ARM Versatile/AB (ARM926EJ-S) - versatilepb ARM Versatile/PB (ARM926EJ-S) - witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176) - z2 Zipit Z2 (PXA27x) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 12 ------------ hw/arm/realview.c | 5 ++++- tests/qtest/cdrom-test.c | 6 +++++- hw/arm/Kconfig | 19 +++++++++++++++++++ target/arm/Kconfig | 4 ++++ 5 files changed, 32 insertions(+), 14 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 6ae964c14fd..0aad35da0c4 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y -CONFIG_MUSICPAL=y CONFIG_MUSCA=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y -CONFIG_VERSATILE=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y -CONFIG_MAINSTONE=y -CONFIG_GUMSTIX=y -CONFIG_SPITZ=y -CONFIG_TOSA=y -CONFIG_Z2=y CONFIG_NPCM7XX=y -CONFIG_COLLIE=y -CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y -CONFIG_DIGIC=y CONFIG_SABRELITE=y CONFIG_EMCRAFT_SF2=y CONFIG_MICROBIT=y -CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 0831159d158..2dcf0a4c23e 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -18,6 +18,7 @@ #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" #include "exec/address-spaces.h" @@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = { static void realview_machine_init(void) { - type_register_static(&realview_eb_type); + if (tcg_builtin()) { + type_register_static(&realview_eb_type); + } type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 5af944a5fb7..1f1bc26fa7a 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -222,7 +222,11 @@ int main(int argc, char **argv) add_cdrom_param_tests(mips64machines); } else if (g_str_equal(arch, "arm") || g_str_equal(arch, "aarch64")) { const char *armmachines[] = { - "realview-eb", "realview-eb-mpcore", "realview-pb-a8", +#ifdef CONFIG_TCG + "realview-eb", +#endif /* CONFIG_TCG */ + "realview-eb-mpcore", + "realview-pb-a8", "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15", "vexpress-a9", "virt", NULL }; diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f2957b33bee..560442bfc5c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -42,6 +42,8 @@ config CUBIEBOARD config DIGIC bool + default y if TCG && ARM + select ARM_V5 select PTIMER select PFLASH_CFI02 @@ -72,6 +74,8 @@ config HIGHBANK config INTEGRATOR bool + default y if TCG && ARM + select ARM_V5 select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -84,6 +88,7 @@ config INTEGRATOR config MAINSTONE bool + default y if TCG && ARM select PXA2XX select PFLASH_CFI01 select SMC91C111 @@ -98,6 +103,8 @@ config MUSCA config MUSICPAL bool + default y if TCG && ARM + select ARM_V5 select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -138,6 +145,7 @@ config OMAP config PXA2XX bool + select ARM_V5 select FRAMEBUFFER select I2C select SERIAL @@ -147,12 +155,14 @@ config PXA2XX config GUMSTIX bool + default y if TCG && ARM select PFLASH_CFI01 select SMC91C111 select PXA2XX config TOSA bool + default y if TCG && ARM select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -160,6 +170,7 @@ config TOSA config SPITZ bool + default y if TCG && ARM select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -172,6 +183,7 @@ config SPITZ config Z2 bool + default y if TCG && ARM select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -245,6 +257,7 @@ config STRONGARM config COLLIE bool + default y if TCG && ARM select PFLASH_CFI01 select ZAURUS # scoop select STRONGARM @@ -257,6 +270,8 @@ config SX1 config VERSATILE bool + default y if TCG && ARM + select ARM_V5 select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -376,6 +391,8 @@ config NPCM7XX config FSL_IMX25 bool + default y if TCG && ARM + select ARM_V5 select IMX select IMX_FEC select IMX_I2C @@ -402,6 +419,8 @@ config FSL_IMX6 config ASPEED_SOC bool + default y if TCG && ARM + select ARM_V5 select DS1338 select FTGMAC100 select I2C diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 811e1e81652..9b3635617dc 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -10,6 +10,10 @@ config ARM_V4 bool depends on TCG && ARM +config ARM_V5 + bool + depends on TCG && ARM + config ARM_V7M bool select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:51:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGH-0002Qp-B0 for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id b3sm19907224wme.32.2021.01.31.03.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:51:03 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Date: Sun, 31 Jan 2021 12:50:18 +0100 Message-Id: <20210131115022.242570-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:21 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). Beside, KVM only supports A-profile, thus won't be able to run M-profile cpus. Only enable the following ARMv7 M-Profile CPUs when TCG is available: - Cortex-M0 - Cortex-M3 - Cortex-M4 - Cortex-M33 The following machines are no more built when TCG is disabled: - emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010) - highbank Calxeda Highbank (ECX-1000) - lm3s6965evb Stellaris LM3S6965EVB (Cortex-M3) - lm3s811evb Stellaris LM3S811EVB (Cortex-M3) - midway Calxeda Midway (ECX-2000) - mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3 - mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4 - mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7 - mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33 - mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3 - mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33 - musca-a ARM Musca-A board (dual Cortex-M33) - musca-b1 ARM Musca-B1 board (dual Cortex-M33) - netduino2 Netduino 2 Machine (Cortex-M3) - netduinoplus2 Netduino Plus 2 Machine(Cortex-M4) We don't need to enforce CONFIG_ARM_V7M in default-configs anymore. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 11 ----------- hw/arm/Kconfig | 7 +++++++ target/arm/Kconfig | 1 + 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 175530595ce..0fc80d7d6df 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -1,28 +1,17 @@ # Default configuration for arm-softmmu -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=y - # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y -CONFIG_HIGHBANK=y -CONFIG_MUSCA=y -CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y CONFIG_NPCM7XX=y -CONFIG_NETDUINO2=y -CONFIG_NETDUINOPLUS2=y -CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_SABRELITE=y -CONFIG_EMCRAFT_SF2=y -CONFIG_MICROBIT=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4baf1f97694..62f8b0d24e7 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -60,6 +60,7 @@ config EXYNOS4 config HIGHBANK bool + default y if TCG && ARM select A9MPCORE select A15MPCORE select AHCI @@ -95,6 +96,7 @@ config MAINSTONE config MUSCA bool + default y if TCG && ARM select ARMSSE select PL011 select PL031 @@ -115,10 +117,12 @@ config MUSICPAL config NETDUINO2 bool + default y if TCG && ARM select STM32F205_SOC config NETDUINOPLUS2 bool + default y if TCG && ARM select STM32F405_SOC config NSERIES @@ -240,6 +244,7 @@ config SABRELITE config STELLARIS bool + default y if TCG && ARM select ARM_V7M select CMSDK_APB_WATCHDOG select I2C @@ -443,6 +448,7 @@ config ASPEED_SOC config MPS2 bool + default y if TCG && ARM select ARMSSE select LAN9118 select MPS2_FPGAIO @@ -496,6 +502,7 @@ config NRF51_SOC config EMCRAFT_SF2 bool + default y if TCG && ARM select MSF2 select SSI_M25P80 diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 4dc96c46520..07a2fad7a2b 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -24,4 +24,5 @@ config ARM_V7R config ARM_V7M bool + depends on TCG && ARM select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGu-0002fl-AX for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:52:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BG6-0002O3-Oa; Sun, 31 Jan 2021 06:51:15 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:34851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BG4-0005ZN-0b; Sun, 31 Jan 2021 06:51:13 -0500 Received: by mail-wm1-x32a.google.com with SMTP id e15so10755771wme.0; Sun, 31 Jan 2021 03:51:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aLdl19C96C3GXRdvC9mwI7cbyJbYzl+Xi4/pdqV71I=; b=sRiuwmALg9U8wrF+nK7mVUs+HXcy3GG/kZwoT3Ky0fRx9392Xk6PlerBKMECc3uHhq +yEZaCAi2myKtOwXsL10XN5dYu8Q4lK7UBTHJ3cMuwjgLxM9+XSiRL3YrTJPe0l8/a/u h+naApUI8PLoHdg3NlxtwFO6hG3iOnqc8AADrzk3ryeB4Xm5F4S0d8qwaf5oc8cZ5hAR YgxVZapFmkxXd0HX5bwBqbhZkgHKgaJzj/4J7yPtjueODMnIOooBfdV/qgcFB8zCxzv5 EUR/LB1cNPPQXtqQGokgkIe/EGWziL1d1OtZbsb2cxJwAnHXJ/H+ySW/Hl2kSIvnb2Es KUZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9aLdl19C96C3GXRdvC9mwI7cbyJbYzl+Xi4/pdqV71I=; b=BDQQvSTvvJKat5tbFC8XnSW7JiHiNhyaHzEVkvIr7F2DMRjACOJUK1vQmP2OF43JWL 9TbckGSn9CRu6VMkse2wS4aaDJ4ojE37OQw6ggS0GFR3QuhCdaXHG+B94xuKoeDelcqA ESevsjBzk0mSKXWXeOBzp6Mjvli0irRNiklLmsM3f9d3GWV0ykbprZvT6frEukSOab8o yBJKHXqwsPSr5apgK+IXMV00T8ReRv2xIGY07M0J27pB2Jupt0wavdXGQeVbWJCcpalF sifuPGpV+/m84xwdfrnYQEfBX+xSASmDqEau/3AmWWXuYyabcYDox5vOxF9K1AAqVk2Q zbmQ== X-Gm-Message-State: AOAM533i2/S6+UBMwHE3SxkYpqEIhUB+TIe0J7OwSJPILMDonIuF6+th e3Ixp0IICF9TSLoyJv3ANpBU9IYEMSM= X-Google-Smtp-Source: ABdhPJwEOUHvqTzGHiWAoaq4Jn7Z8VpdizCzuGier0I9RK/FHNRiq3u4Ge8nQolOUjmT1NuInZpoKw== X-Received: by 2002:a05:600c:4f48:: with SMTP id m8mr1541406wmq.12.1612093869810; Sun, 31 Jan 2021 03:51:09 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id c62sm3325143wme.16.2021.01.31.03.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:51:09 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Date: Sun, 31 Jan 2021 12:50:19 +0100 Message-Id: <20210131115022.242570-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:21 -0000 From: Thomas Huth We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth Message-Id: <20190903154810.27365-4-thuth@redhat.com> [PMD: Keep m_helper-stub.c but extend it, rewrite the rest] Signed-off-by: Philippe Mathieu-Daudé --- Rewrite since v3, therefore removed Richard R-b tag. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 12 ------- target/arm/cpu_tcg.c | 4 ++- target/arm/helper.c | 7 ---- target/arm/m_helper-stub.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 4 ++- 5 files changed, 79 insertions(+), 21 deletions(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c..0bd0e51e498 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY bool armv7m_nvic_can_take_pending_exception(void *opaque); -#else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) -{ - return true; -} -#endif /** * armv7m_nvic_set_pending: mark the specified exception as pending * @opaque: the NVIC @@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque); * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ -#ifndef CONFIG_USER_ONLY bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) -{ - return false; -} #endif /* Interface for defining coprocessor registers. diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 98544db2df3..3e1c9b40353 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifndef CONFIG_USER_ONLY static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return ret; } +#endif /* CONFIG_USER_ONLY */ static void arm926_initfn(Object *obj) { @@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt; + cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; #endif - cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; cc->gdb_core_xml_file = "arm-m-profile.xml"; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e64..fe3d0291f9c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } -#ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - g_assert_not_reached(); -} -#endif - ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 00000000000..6d751424e86 --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,73 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + g_assert_not_reached(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + g_assert_not_reached(); +} + +#ifndef CONFIG_USER_ONLY + +bool armv7m_nvic_can_take_pending_exception(void *opaque) +{ + g_assert_not_reached(); +} + +void arm_v7m_cpu_do_interrupt(CPUState *cs) +{ + g_assert_not_reached(); +} + +#endif /* CONFIG_USER_ONLY */ diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c1010..6c6081966cd 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -21,7 +21,6 @@ 'gdbstub.c', 'helper.c', 'iwmmxt_helper.c', - 'm_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', @@ -32,6 +31,9 @@ )) arm_ss.add(zlib) +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) + arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGu-0002gO-Hz for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id r16sm1563538wrt.68.2021.01.31.03.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:51:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell Subject: [PATCH v6 09/11] target/arm: Reorder meson.build rules Date: Sun, 31 Jan 2021 12:50:20 +0100 Message-Id: <20210131115022.242570-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:25 -0000 From: Philippe Mathieu-Daudé Reorder the rules to make this file easier to modify. No logical change introduced in this commit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6c6081966cd..aac9a383a61 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,31 +14,36 @@ arm_ss = ss.source_set() arm_ss.add(gen) +arm_ss.add(zlib) arm_ss.add(files( 'cpu.c', - 'crypto_helper.c', - 'debug_helper.c', 'gdbstub.c', 'helper.c', + 'vfp_helper.c', +)) + +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c', +)) + +arm_ss.add(files( + 'crypto_helper.c', + 'debug_helper.c', 'iwmmxt_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', 'translate.c', 'vec_helper.c', - 'vfp_helper.c', 'cpu_tcg.c', )) -arm_ss.add(zlib) - arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGv-0002jH-Hk for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:52:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BG2-0002N6-VN; Sun, 31 Jan 2021 06:51:13 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:53266) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFt-0005Wx-Ge; Sun, 31 Jan 2021 06:51:09 -0500 Received: by mail-wm1-x32b.google.com with SMTP id j18so10241371wmi.3; Sun, 31 Jan 2021 03:51:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=55M93vKE1ahVgefWyZvIGcKvoJvAwdKqopFIoeHKkkA=; b=freBR3tIPtKMjI2+MuKbji7ZAmhWoqg3OKGAyKpW5xTZpNL67hf8t/x55QZPJTsMKz yEgpK6BA74aoPJ3neWrEuMTCkKXHqYvDm8EEuhQyQq+J9Qdipr6EZ9TB9ia301pTOoz9 vv9A7BlPEvFHTRQ3M8w0tWlUePeXhLMgnZjd3JfMdtm30/IKP2UnSGsQS5fQkz5uSsxt ceUquXDjHUU1rTo7hKFajd/mUnA7Mi6K/dt+TtlgJYUl86XLQH7/EFyjqFqD7mwzCzQ0 iT9EJe0qFQ90dsHDB1V8YvULyo5X3sBy5qnHmUGWDwe8TzgD3Z9yRx6ltBfOJRZHPZow zY3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=55M93vKE1ahVgefWyZvIGcKvoJvAwdKqopFIoeHKkkA=; b=QKAkMHqmtxS0LFer8WNUs6ZRqubr2D6ADtjmI4dG8AZ4dytq2r6W4DrY1SbxzbqGFG vUoStxzfNjZQNORlFN27J9ohRJ0/pgr5sWgepdEgIQakSZxNFSb7jpzma7jwZpbWtlG6 hA83ehS+jPr5qQ5nF0vobPoIxz//d75dBxHp3cqgIbWc9Hpfor1bAlNBInAWvDQRIGdC mpe6+Re0htximF6jOe/2jyPgUQyg6GYUC2X6zY/owKk8DVXQRPUkzKNSCKgkLVHcDwGm nH/KVnrqJM+fDY3dJDUbe+xu1HINRNOblROuuur5r1AwN/WapI+QKWC64wqjB5WO1EMi mSvQ== X-Gm-Message-State: AOAM5305l2JrM86H3YIPhEFeJXAprRmRlDiZaL8EwtwtqNQxEYxACjWM uItWFEP0KWSVM8xpBrxfZHEVwygK6Ow= X-Google-Smtp-Source: ABdhPJwJ9hes8lhe7OgVqiDeXshE4pGmaMbjuBMuK73ScXw3dz3Zg0MEOl283XRP7LZaLbEaQLBqZA== X-Received: by 2002:a1c:a406:: with SMTP id n6mr10935564wme.53.1612093858925; Sun, 31 Jan 2021 03:50:58 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id u5sm18602187wmg.9.2021.01.31.03.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:58 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Sun, 31 Jan 2021 12:50:17 +0100 Message-Id: <20210131115022.242570-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:21 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). Beside, KVM only supports A-profile, thus won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F The following machine is no more built when TCG is disabled: - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/aarch64-softmmu.mak | 1 - hw/arm/Kconfig | 2 ++ target/arm/Kconfig | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak index 958b1e08e40..a4202f56817 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -CONFIG_XLNX_ZYNQMP_ARM=y CONFIG_XLNX_VERSAL=y CONFIG_SBSA_REF=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 6c4bce4d637..4baf1f97694 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -360,8 +360,10 @@ config STM32F405_SOC config XLNX_ZYNQMP_ARM bool + default y if TCG && ARM select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD diff --git a/target/arm/Kconfig b/target/arm/Kconfig index fbb7bba9018..4dc96c46520 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -18,6 +18,10 @@ config ARM_V6 bool depends on TCG && ARM +config ARM_V7R + bool + depends on TCG && ARM + config ARM_V7M bool select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGv-0002jg-PS for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:52:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BFp-0002Kc-Ii; Sun, 31 Jan 2021 06:50:58 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:35701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BFn-0005Tw-VZ; Sun, 31 Jan 2021 06:50:57 -0500 Received: by mail-wr1-x434.google.com with SMTP id l12so13519334wry.2; Sun, 31 Jan 2021 03:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ELWTSu1rl/DhvuIH4cal4USbDecgDqC8O4/05ndhpXE=; b=atxpO5/Camn9p7jABxjl2WTPortxY8V1F0jxEhdR2VF0SBEfPL9LK5Vq47+Eod8YM4 aSZuSFtkdwJyK3FzZaGake8jsnv3T1MqlWW+JvnWt/YTtBuI0fzJvdhdooOiQHAYpA8U UVFjEvV4zBNtllHFhkwQzhLAeGmiSs62p2SIMZjyQGGHFYpj8/nWFB0rzW5VU5sTmUgU qArFne3BXB4GxsdEsUtx2RothKht8yJaLcLGwCRcFLJ64xxggBPETOdIxL3w2xWx/eHW kp9nxOa9ngRX8eU7jbkiS5Yj9hDjtee2VaqEn0fy7cAe7jyw4/p9JLsxgkBb5WKz3a/P MdEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ELWTSu1rl/DhvuIH4cal4USbDecgDqC8O4/05ndhpXE=; b=hmCeJJ5TXyLT9abBPQXh8S2DRDLspWJxkGjlTQTbaj/VkC8glDhF4aq2De2IF50sot TUSb/qjuMYH/OmIV1NkbO4bChocKAABlVi1IANDcgPpj9+HazLV83JgoTiqp5PmQYnQL FLwEZ6UN9v/DX3P9x/gPzXZeRri/3Xipl1QUDf8sF2EPp79Ky/jR8Eb29xA7o5l2jniP ROqeSFEzDcixoiWgRCW8p90O6/oQyRKCSWh5ZVUk4RrPKpkKS/D92W3ykSlleC4Qa6or N1iSz7xmhHT+8idfnCUWpQtKjOsuKIb9iSvgbWYWFmsAbHXDtNk0BTEfOAFyEZ/ZtFbW /3xw== X-Gm-Message-State: AOAM530EZ3N+P80otBQyg+ImIlcRvVNBXUWLRLV3/i3gp/fuwpdbM/ut SPFZ6iE6fCWlGdMYLASxsHMtpxoLj0A= X-Google-Smtp-Source: ABdhPJw052bc5n0sg8qrUOVnPuK+eGRq0Nn6pE/jzM3JbJxgQX3UIdClky2OLAwF4K5l6GeEHLBoOw== X-Received: by 2002:adf:9427:: with SMTP id 36mr13393596wrq.271.1612093853746; Sun, 31 Jan 2021 03:50:53 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id w4sm2862428wrt.69.2021.01.31.03.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:50:53 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 05/11] target/arm: Restrict ARMv6 cpus to TCG accel Date: Sun, 31 Jan 2021 12:50:16 +0100 Message-Id: <20210131115022.242570-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:16 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). Only enable the following ARMv6 CPUs when TCG is available: - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 The following machines are no more built when TCG is disabled: - kzm ARM KZM Emulation Baseboard (ARM1136) - microbit BBC micro:bit (Cortex-M0) - n800 Nokia N800 tablet aka. RX-34 (OMAP2420) - n810 Nokia N810 tablet aka. RX-44 (OMAP2420) - realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/realview.c | 2 +- tests/qtest/cdrom-test.c | 2 +- hw/arm/Kconfig | 6 ++++++ target/arm/Kconfig | 4 ++++ 5 files changed, 12 insertions(+), 4 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0aad35da0c4..175530595ce 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_FSL_IMX31=y CONFIG_MUSCA=y -CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 2dcf0a4c23e..0606d22da14 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -463,8 +463,8 @@ static void realview_machine_init(void) { if (tcg_builtin()) { type_register_static(&realview_eb_type); + type_register_static(&realview_eb_mpcore_type); } - type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); } diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 1f1bc26fa7a..cb0409c5a11 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -224,8 +224,8 @@ int main(int argc, char **argv) const char *armmachines[] = { #ifdef CONFIG_TCG "realview-eb", -#endif /* CONFIG_TCG */ "realview-eb-mpcore", +#endif /* CONFIG_TCG */ "realview-pb-a8", "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15", "vexpress-a9", "virt", NULL diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 560442bfc5c..6c4bce4d637 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -123,6 +123,8 @@ config NETDUINOPLUS2 config NSERIES bool + default y if TCG && ARM + select ARM_V6 select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -401,6 +403,8 @@ config FSL_IMX25 config FSL_IMX31 bool + default y if TCG && ARM + select ARM_V6 select SERIAL select IMX select IMX_I2C @@ -478,11 +482,13 @@ config FSL_IMX6UL config MICROBIT bool + default y if TCG && ARM select NRF51_SOC config NRF51_SOC bool select I2C + select ARM_V6 select ARM_V7M select UNIMP diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 9b3635617dc..fbb7bba9018 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -14,6 +14,10 @@ config ARM_V5 bool depends on TCG && ARM +config ARM_V6 + bool + depends on TCG && ARM + config ARM_V7M bool select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGx-0002ng-2k for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:52:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BGG-0002Qd-DO; Sun, 31 Jan 2021 06:51:25 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:40390) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BGF-0005dB-0t; Sun, 31 Jan 2021 06:51:24 -0500 Received: by mail-wr1-x42c.google.com with SMTP id c12so13511893wrc.7; Sun, 31 Jan 2021 03:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=slxe/n+gWVTJ0YqCL3Bn1rdJcLxnKsXS1n7WF9oDy93hJBrTu2I3a2iCbMx2QDDRf6 cvW4fsFH+RBNOH8Xizz/iAt4S26E5y/x/GNkhqNZmKoFK0IiYXFUyThdM4/jwqc/fgDh Y8sSf3tw+ovhP/bOMS00qPGcsrcwEr4MAVjaD4Adx0t14YzqI1NvnOJU9VgFgQeaG54O V+6f04a2Rwu6cmu95TNxszsXA3x1TBUu0rBat0w9gSOTxcp7PNPqNvAJyHXskdJMCaKx yFY9GcHTyxHSb+UJ+i+xVssw6kxrn3Nc/CZDLYpgrtE9kqvzklrUNMRkM1Y9GXFVF1zD r1Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=IwEIa9v4EqoLNPq/v0nDuNplk0V+9thwoHcd0oIpHMkDNTkjcpuxtKTfDorz6B+f24 QKs/PHZ/bj7+vvTyopR3hRj45QuHY3Nrq1dQawkIO1FjZzXUsDM2767DjAc0J72u7oO6 9M5Ik/Ue1EyIV/hfBM1MyOVc6PQhVsipUBZoQxqZFzWpasWr86tt6U2Q3Ljn3ReZIMMH TLoVRUKfD75xP547LX0BsiLtqypTj7w0tu+5mnCvqvm+6TMQpDHEoY9U+ZHdGTDoBb5V 3i+RAi3tuvf0k/U1jKplWJj54VY3dRCHtWxRbeTtmvURq5YAaxo7FsvaxJ4URUb3bv9W VcQw== X-Gm-Message-State: AOAM531ZGCoLVZNx9BTHAiK/v6GlUXDPJmsU3SMG4im2yhyMIXAFmBZq rn93I2WIa0PCiesPOIaEIN8vbsAtfKE= X-Google-Smtp-Source: ABdhPJyhH4FzLWznIwV2JMINXQ8Kq1HB+Q7Ewfh1h/EdNga37TZknXhQRMlYya4ZrjBKEH1uV/ip3A== X-Received: by 2002:a5d:6c6b:: with SMTP id r11mr13497246wrz.38.1612093880944; Sun, 31 Jan 2021 03:51:20 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id h23sm17669371wmi.26.2021.01.31.03.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:51:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , Samuel Ortiz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 10/11] target/arm: Do not build TCG objects when TCG is off Date: Sun, 31 Jan 2021 12:50:21 +0100 Message-Id: <20210131115022.242570-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:27 -0000 From: Samuel Ortiz We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz [PMD: Heavily rebased during more than 2 years then finally rewritten] Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index aac9a383a61..11b7c0e18fe 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,7 +27,8 @@ 'gdbstub64.c', )) -arm_ss.add(files( +arm_tcg_ss = ss.source_set() +arm_tcg_ss.add(files( 'crypto_helper.c', 'debug_helper.c', 'iwmmxt_helper.c', @@ -38,12 +39,12 @@ 'vec_helper.c', 'cpu_tcg.c', )) -arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( +arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files( 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', @@ -52,14 +53,16 @@ 'translate-sve.c', )) +arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss) + arm_softmmu_ss = ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'machine.c', 'monitor.c', - 'psci.c', )) +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c')) target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:52:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BGz-0002s2-1n for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:52:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BGL-0002TB-Vr; Sun, 31 Jan 2021 06:51:35 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:51883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BGK-0005fl-Eo; Sun, 31 Jan 2021 06:51:29 -0500 Received: by mail-wm1-x329.google.com with SMTP id m2so10248877wmm.1; Sun, 31 Jan 2021 03:51:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=GPA3cPX5JqpAFpzVcjZKg1cO1/9FihznwxhN41y6BZVikFsYSNE6B0F3b9X4VO71cp GyaFWx06W4d8AT7wOOpbEv7rWLR6Qtiz0j5zPdW4jmA03AE7iBWAl+qefDWnlBg1V4z9 2hzf0FUOYthAF2ms02+vvuipScW5aEoQfhM5Srd93RmxYebfiQUiVZHh2JesAfrjbQB0 cMFWV7UC3rXS0EBZiWNOOLMzmTv768bnbQkOi/XMIRHsBx16z36CUzwuUgCR8NuoQrgW IawFdKNFLz9n71Y6SFOU0j45CXgLpwvg9ZqphDDITLGf2fxUdnKHiy3pt17p/Z2oEROU U1cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=CCh+3IxYlTir+MIrGd424CcbvPoA7E2l0REym4cvVZ7w3wcRXX8IxTDW+KH6cxuc2/ KncFPeHJxjV194P4t+tAdAASwAMnDy+733XymEGUDjOz+MFrK0xUcfWBy8CwX1T/g0Cl M7GAMSZdDeNhJI2tIsYiBVHnBCWWg73r3UIUNA0VsqSqcQh8pAb9eDVgE3JO50WMbp1D TIitmAVMN8M/m7k8CeT67RKJT/ktPfBMFBrPQm63sqicDQzCFl1BBHi96Xi1R5qVd7GD 9ETcndhBmaHkW2LaWg5vITIFx/az+ssWm7lrsYebzw9M8PU+yotN8YoKsOzZ/m0J02ec 65dQ== X-Gm-Message-State: AOAM5313MHmsGOtCC66eCswXGqO+OWLzTdAUu5Bvunm1gWcC4OVGesAj SU5KnkJcLhh3y7pdx4nkl28au3Ninw4= X-Google-Smtp-Source: ABdhPJw2bZG4ateZlH907WN0fRnTRmRpW0onowzIJAbKbCMmlTsxOnsYabaEy2SQ4dqJh8Bjumsguw== X-Received: by 2002:a1c:6289:: with SMTP id w131mr2722637wmb.0.1612093886306; Sun, 31 Jan 2021 03:51:26 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id n19sm17298998wmq.25.2021.01.31.03.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 03:51:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell Subject: [PATCH v6 11/11] .travis.yml: Add a KVM-only Aarch64 job Date: Sun, 31 Jan 2021 12:50:22 +0100 Message-Id: <20210131115022.242570-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> References: <20210131115022.242570-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:51:36 -0000 From: Philippe Mathieu-Daudé Add a job to build QEMU on Aarch64 with TCG disabled, so this configuration won't bitrot over time. We explicitly modify default-configs/aarch64-softmmu.mak to only select the 'virt' and 'SBSA-REF' machines. Signed-off-by: Philippe Mathieu-Daudé --- Job ran for 7 min 30 sec https://travis-ci.org/github/philmd/qemu/jobs/731428859 --- .travis.yml | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/.travis.yml b/.travis.yml index 5f1dea873ec..4f1d662b5fc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -264,6 +264,38 @@ jobs: - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}" - UNRELIABLE=true + - name: "[aarch64] GCC (disable-tcg)" + arch: arm64 + dist: focal + addons: + apt_packages: + - libaio-dev + - libattr1-dev + - libbrlapi-dev + - libcap-ng-dev + - libgcrypt20-dev + - libgnutls28-dev + - libgtk-3-dev + - libiscsi-dev + - liblttng-ust-dev + - libncurses5-dev + - libnfs-dev + - libnss3-dev + - libpixman-1-dev + - libpng-dev + - librados-dev + - libsdl2-dev + - libseccomp-dev + - liburcu-dev + - libusb-1.0-0-dev + - libvdeplug-dev + - libvte-2.91-dev + - ninja-build + env: + - CONFIG="--disable-containers --disable-tcg --enable-kvm --disable-xen --disable-tools --disable-docs" + - TEST_CMD="make check-unit" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64" + - name: "[ppc64] GCC check-tcg" arch: ppc64le dist: focal -- 2.26.2 From MAILER-DAEMON Sun Jan 31 06:57:25 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BM5-0008ED-1o for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:57:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BM2-0008BP-1F; Sun, 31 Jan 2021 06:57:22 -0500 Received: from mail-oi1-f173.google.com ([209.85.167.173]:46633) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BLx-00082p-Vv; Sun, 31 Jan 2021 06:57:19 -0500 Received: by mail-oi1-f173.google.com with SMTP id k25so15513224oik.13; Sun, 31 Jan 2021 03:57:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=YVkInRJxpduhbRvqa9xcBthpuPzf7AjKpZhjK7Cpckg=; b=U4btTzAGYpjIvDeplimZ2uqLXcDl+6ZriVoE2Oxllnw17qbfWKws2ecwV4NF4bsFu+ FYBY1JYL3cLR164Ji1Bd9EFuhTL4L0Nba7pjkOe/KkRDNpq6V0bfV6oijJ1j6wpATrrL 3JvTs2ImWIeCFBEO2+28vrfFA3DOarQC9pka2iIyTtM/1jlR8X5MddclfI13xGXdng3l Y8W4QxUokO7tMXwzWijE6e2aqwJStpKU+N8As4olKilOc2Iyink3IyDIOplmXiFMo66W tDYBNfR1glRRSeQYgHBuZVOTTpvQ+mw4H2gMyND4Kw0C07NPG6CizKJ267VWpzOK9vf7 l+YQ== X-Gm-Message-State: AOAM530tzQnMcmi/MHnV5JNID/QottG7qC4q9LE9R+EZDcrGzfXVCVZN Yqh4qwHtRALqZul0Lu7XRlciVGfdMrmTSJVjwMR6y0SmoqM= X-Google-Smtp-Source: ABdhPJzTsVYWTiFYHJJoplW61B8aLyILK891rvibXykh/sCNgQ3gvSZtbxkhWSacPEQCBANMrvfh/48uBylcMZS22go= X-Received: by 2002:aca:f1d4:: with SMTP id p203mr7974934oih.46.1612094235899; Sun, 31 Jan 2021 03:57:15 -0800 (PST) MIME-Version: 1.0 References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-12-f4bug@amsat.org> In-Reply-To: <20210131115022.242570-12-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Date: Sun, 31 Jan 2021 12:57:04 +0100 Message-ID: Subject: Re: [PATCH v6 11/11] .travis.yml: Add a KVM-only Aarch64 job To: "qemu-devel@nongnu.org Developers" Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , "open list:Block layer core" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , kvm , Laurent Vivier , qemu-arm , Richard Henderson , John Snow , Peter Maydell Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=209.85.167.173; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-oi1-f173.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:57:22 -0000 On Sun, Jan 31, 2021 at 12:51 PM Philippe Mathieu-Daud=C3=A9 wrote: > > From: Philippe Mathieu-Daud=C3=A9 > > Add a job to build QEMU on Aarch64 with TCG disabled, so > this configuration won't bitrot over time. > > We explicitly modify default-configs/aarch64-softmmu.mak to > only select the 'virt' and 'SBSA-REF' machines. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > Job ran for 7 min 30 sec > https://travis-ci.org/github/philmd/qemu/jobs/731428859 BTW I added this patch for completeness but I couldn't test it again as I don't have anymore Travis-CI credit. I however tested it on a similar Ubuntu Aarch64 host. From MAILER-DAEMON Sun Jan 31 06:57:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6BMV-00007N-BK for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 06:57:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6BMO-000054-KN for qemu-arm@nongnu.org; Sun, 31 Jan 2021 06:57:44 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:37247) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l6BMK-0008AF-7H for qemu-arm@nongnu.org; Sun, 31 Jan 2021 06:57:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1612094258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/eB22EK6Sxe6tquaW0oxDejbZSU1tflyFzbU5sPweqk=; b=ae9yjPMZtRufmN6sgXs7t0NcDYtg+/rdLV5fHnjj6tpjAfpL2kDsnIOYnOi4D/gZOaEZBq LffhVvGaxpoOE5MzFuexyq+0G5Xiy195Eyex8RWhvWsf4ZtPhwIuljR8MqxjBv0knEdPSH vDJkEa197+jTuj5GC6YwfMCd5IjnYFU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-460-B6ZazDrIP5C0GuiN5ReEGw-1; Sun, 31 Jan 2021 06:57:34 -0500 X-MC-Unique: B6ZazDrIP5C0GuiN5ReEGw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E086F801B16; Sun, 31 Jan 2021 11:57:32 +0000 (UTC) Received: from kaapi (ovpn-112-95.phx2.redhat.com [10.3.112.95]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 05D0B5C3E0; Sun, 31 Jan 2021 11:57:26 +0000 (UTC) Date: Sun, 31 Jan 2021 17:27:20 +0530 (IST) From: P J P To: =?ISO-8859-15?Q?Philippe_Mathieu-Daud=E9?= cc: qemu-devel@nongnu.org, "Edgar E . Iglesias" , Peter Maydell , Alexander Bulekov , Sai Pavan Boddu , qemu-stable@nongnu.org, Li Qiang , Darren Kenny , qemu-arm@nongnu.org, Luc Michel Subject: Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register In-Reply-To: <3a94e327-0454-bf43-552a-1c84407e1d7d@amsat.org> Message-ID: <20p82p5p-ns25-n434-37os-n55013s6313@erqung.pbz> References: <20210131103401.217160-1-f4bug@amsat.org> <3a94e327-0454-bf43-552a-1c84407e1d7d@amsat.org> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ppandit@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/mixed; boundary="-1463811718-1923904730-1612094251=:1010257" Received-SPF: pass client-ip=63.128.21.124; envelope-from=ppandit@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.351, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 11:57:45 -0000 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. ---1463811718-1923904730-1612094251=:1010257 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT +-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+ | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: | > Per the ARM Generic Interrupt Controller Architecture specification | > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, | > not 10: | > | > - Table 4-21 GICD_SGIR bit assignments | > | > The Interrupt ID of the SGI to forward to the specified CPU | > interfaces. The value of this field is the Interrupt ID, in | > the range 0-15, for example a value of 0b0011 specifies | > Interrupt ID 3. | > | > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c | > index af41e2fb448..75316329516 100644 | > --- a/hw/intc/arm_gic.c | > +++ b/hw/intc/arm_gic.c | > @@ -1476,7 +1476,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, | > int target_cpu; | > | > cpu = gic_get_current_cpu(s); | > - irq = value & 0x3ff; | > + irq = value & 0xf; | > switch ((value >> 24) & 3) { | > case 0: | > mask = (value >> 16) & ALL_CPU_MASK; | > * Looks okay. | > Correct the irq mask to fix an undefined behavior (which eventually | > lead to a heap-buffer-overflow, see [Buglink]): | > | > $ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio | > [I 1612088147.116987] OPENED | > [R +0.278293] writel 0x8000f00 0xff4affb0 | > ../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]' | > SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13 | > | > Cc: qemu-stable@nongnu.org | > Fixes: 9ee6e8bb853 ("ARMv7 support.") | > Buglink: https://bugs.launchpad.net/qemu/+bug/1913916 | > Buglink: https://bugs.launchpad.net/qemu/+bug/1913917 | | > --- | > Isnt it worth a CVE to help distributions track backports? | > --- * Please send such report(s) to 'qemu-security' list to be triaged as potential security ones. Thank you. -- Prasad J Pandit / Red Hat Product Security Team 8685 545E B54C 486B C6EB 271E E285 8B5A F050 DE8D ---1463811718-1923904730-1612094251=:1010257-- From MAILER-DAEMON Sun Jan 31 07:31:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Bss-0004zm-MO for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 07:31:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Bsr-0004zT-Oq; Sun, 31 Jan 2021 07:31:17 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:34892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Bsp-0005J4-Ib; Sun, 31 Jan 2021 07:31:17 -0500 Received: by mail-wr1-x433.google.com with SMTP id l12so13585381wry.2; Sun, 31 Jan 2021 04:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=ArDxDd++XiL9ldRFmwikYY0GhMalIcaTHNsk/ofhIwM=; b=hK3zHJiQXtURacBXGDySP+Z3SC/dAu9hf/955L2cPsAbu1YXQsxqYQG4djm3dkhBpC HB06dFCsASoClqwQnLryiiOrJ6e5HF2g/7K1GSBSY/3Hxkpk0/pWjQLKTih82B0an3Y9 7sXwUcENXuFJg/p/h5VCkZgJr2duuo7cM7vL71GEh9rIqDIOJfyXOUnU9dc3XD0/IDZB /j7MeaZ5c/+r4K8hvT6A0DfwofBNdevrLPCsYGegEj2VhtN8a8+KZpQsKeFWXosG2Skw noo92Kq2qSFEAHZHerrW+5OxxxM3TynUat+nnALhMCyxTd4iL9Cz5nFvxV5as9cRvEke oZlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ArDxDd++XiL9ldRFmwikYY0GhMalIcaTHNsk/ofhIwM=; b=WyrIemGdQ26w6xbBCVv3JoT4Y81Idei7Pa5xm2X/SuTo00deIql9nxJu5X2F9djruZ yTEMIr/GP5vXeLi3aTJZT0zZFJI0nxhHa03+bNqrQUEZmS3cePYiwouLjrIOC+bQixvA s0MRvjQQKWIMfcGFEmSwiu5f/w0vPbv6/2HkVXzxBGAamk3TTa9Bpc4sXI4XbmPdxx7r yXgC1EmrxjNwRDwj0ke2IK9AuzeuQW9gDc7W2ipO1hljnw0Dksks6lhJeLo/MTNguw+A 8zLsujBil/E77jfey2Nis1G/wO4UAyZg0MZaNGpzx0s3dWW2ZCP+h65xR/CtB9o5wwuW PExg== X-Gm-Message-State: AOAM531RKq1H6Gmyj4OaiNUZtRuR/ULH5mCx4dpq4birCObHNDpj+Ta7 HYS8DQq9/y8CHxwwNI7/GB8= X-Google-Smtp-Source: ABdhPJwAH327u5WJJs1N1sI1ZQhiCyqzbUp0JmJZObD5NbLIHvb/P2yffXwv8nWVonrbKUwV+Q2rqA== X-Received: by 2002:adf:f749:: with SMTP id z9mr13137870wrp.327.1612096272524; Sun, 31 Jan 2021 04:31:12 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id u206sm7468795wme.12.2021.01.31.04.31.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 04:31:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 5/7] hw/arm/sbsa-ref: Restrict SBSA-ref board to 64-bit build To: qemu-devel@nongnu.org Cc: Peter Maydell , Radoslaw Biernacki , qemu-trivial@nongnu.org, Alistair Francis , Michael Tokarev , Laurent Vivier , Niek Linnenbank , qemu-arm@nongnu.org, Antony Pavlov , Leif Lindholm , Joel Stanley References: <20210131105918.228787-1-f4bug@amsat.org> <20210131105918.228787-6-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sun, 31 Jan 2021 13:31:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131105918.228787-6-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 12:31:18 -0000 On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote: > The SBSA-ref board only use CPUs available in the 64-bit build, > it is pointless to have it available in the 32-bit build. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Radoslaw Biernacki > Cc: Leif Lindholm > --- > hw/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index be39117b9b6..059ff7382f2 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -22,7 +22,7 @@ > arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) > arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) > arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) > -arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) > +arm_ss.add(when: ['CONFIG_SBSA_REF', 'TARGET_AARCH64'], if_true: files('sbsa-ref.c')) Please disregard this patch, it shows that my other patch "meson: Introduce target-specific Kconfig" is incorrect: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07989.html Probably because per docs/devel/kconfig.rst "devices are usually ``default y`` if and only if they have at least one ``depends on``". I'll try another approach such: -- >8 -- --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -227,6 +227,8 @@ config REALVIEW config SBSA_REF bool + default y + depends on AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 --- From MAILER-DAEMON Sun Jan 31 07:32:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Bth-0005Vb-6U for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 07:32:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Btb-0005TU-FD; Sun, 31 Jan 2021 07:32:04 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6BtZ-0005Zx-Qe; Sun, 31 Jan 2021 07:32:03 -0500 Received: by mail-wr1-x432.google.com with SMTP id d16so13532058wro.11; Sun, 31 Jan 2021 04:32:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=k5JMa0AuMQ5zNAh1DKBCn904vYAejWRzzqIP53M8nVw=; b=Ha3/fcdJR6PMcFWNGbMzq5PKC8u7RUkC90Svf1iNXGpaYZjkU5hYa41jujxQXz07/H 21Zpu2MCCk16Z4loWJjULKlXOR61WvgML3mOU2LX9MhRQybfjO0neZH/68stX3e08hK7 7eG5kUgI+5i0QnJ3XYoqBC4IFeq7HByiwwwfl6nm7qDBGOFaTrV6bZCqWH4PZO2ElerW uBQlGSyPDSHy1fWQSsrLni4iP4EVQaPCjbscjnIBcIP26GTkFvzr4KstUrwDeGEMUBJm Lgo4hxuM1BYt4vvjk+hvWWDeBksOJ5MoTC0V93inam7mzujZNnuFuvVPjvkJyWx23vEn vTNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=k5JMa0AuMQ5zNAh1DKBCn904vYAejWRzzqIP53M8nVw=; b=S9PK/ChfCtsRnYXukjnIIt8WFSFEBudkOS2/ZsklX3Geuy+zVE6WgV2QJrWYmDDFNL VK3h+TBx3uCYn4W3u3v2co6pYwsQ4OSuRdfBkk/fzstZ7DIzgt/rmEpAwaOEo7e46XwP yG1KZKc/1RiYXQCCwknRM7Fzu5cmFjwdblj2oTGTMwzgpnlty58qwyf6o6HetjFHWLAS 6Dd7KLvvriEKhp/LqBAjJKZc43AVG/4FQ7yJ2yNbs4U8f1ELdyai5GmerRUbr3vDNMnn VlwNoI+K7dRUex026H/t6D7dwxLzaFnu6chJPfjE8ZyNOtHEfoI0HHh/VEpYqsDNoXso e/gQ== X-Gm-Message-State: AOAM532nakIhJXc/+2qpqvEdUT7mX0Ok1SS6tHxJFAStZzeNhhZclZgT rkKdHKGmHzhy3dbAF72UIy8= X-Google-Smtp-Source: ABdhPJxx1Yq0G1qNJREk5beS0j6CmxnHuevyGU2oR/1UDrrqpn9EKWMHwYGFLVcZN7Mtr4w4+dtGkA== X-Received: by 2002:adf:e511:: with SMTP id j17mr13465047wrm.17.1612096319701; Sun, 31 Jan 2021 04:31:59 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id m22sm22890806wrh.66.2021.01.31.04.31.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 04:31:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 6/7] hw/arm/xlnx-zcu102: Restrict ZynqMP ZCU102 board to 64-bit build To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-trivial@nongnu.org, Alistair Francis , Michael Tokarev , Laurent Vivier , Niek Linnenbank , qemu-arm@nongnu.org, Antony Pavlov , "Edgar E. Iglesias" , Joel Stanley References: <20210131105918.228787-1-f4bug@amsat.org> <20210131105918.228787-7-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <5cb160b9-f9a4-05af-9a94-ade51bf4beb7@amsat.org> Date: Sun, 31 Jan 2021 13:31:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131105918.228787-7-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 12:32:06 -0000 On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote: > The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which > is only available in the 64-bit build. It is pointless to > have this board present in the 32-bit build where this CPU > is not available. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Alistair Francis > Cc: "Edgar E. Iglesias" > --- > hw/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index 059ff7382f2..345099f5a1b 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -41,7 +41,7 @@ > arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) > arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) > arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) > -arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) > +arm_ss.add(when: ['CONFIG_XLNX_ZYNQMP_ARM', 'TARGET_AARCH64'], if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) Please disregard this patch, it shows that my other patch "meson: Introduce target-specific Kconfig" is incorrect: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07989.html Probably because per docs/devel/kconfig.rst "devices are usually ``default y`` if and only if they have at least one ``depends on``". I'll try another approach such: -- >8 -- --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -389,6 +391,8 @@ config XLNX_ZYNQMP_ARM config XLNX_VERSAL bool + default y + depends on AARCH64 select ARM_GIC select PL011 select CADENCE --- From MAILER-DAEMON Sun Jan 31 07:36:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6ByB-0007mt-Qx for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 07:36:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6By6-0007lG-2q; Sun, 31 Jan 2021 07:36:42 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:38998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6By1-0007VV-Qs; Sun, 31 Jan 2021 07:36:39 -0500 Received: by mail-wr1-x42b.google.com with SMTP id a1so13598428wrq.6; Sun, 31 Jan 2021 04:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=SlPVp/QhGLIucOeXf2GAys5Xs3M9ZcVjsvA0z2gXN4o=; b=GqF9nNkgn2avmaYgMPwoNKRqTrCOmYlhjcSJIIM1a525tHHZGokwelM3VxqW9GfU3A HEeLfJ26Y8GiggTDcd8voUsssPtXfKtE9pl6TB9a8171kJ6lbfYQB//8UBw9PCbYH7a6 EqVY3pwGeNTAS9MVRXwig/mcReaRpUFYSZF7nvLvr6zyDvesdvIlynLasC41Ohrv8hfv fZbPuFsaA9kHV91Xku1duzJ1qzyxSpwDpGL42iPrk/lWGl+rilDElZWKztrBCbBw/Ade PgbwkfTGoY/QMivj+j+fXN5p1X7sum2107zX4v8e5dIT6Tmo5kZS7c5IcvS9Vg+wTuIM UoNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=SlPVp/QhGLIucOeXf2GAys5Xs3M9ZcVjsvA0z2gXN4o=; b=KjkAfAne9ByPXD788TL/SVRVJqQ/6+yedC+Ilzl0PRH2CAI1neFHdxEzCI/8b+uMYM BqmTB0ZQOj8M3+V/GKNnTux+CAWt5KtWxq9dYL5pJXfF8rg3QJ7r7CzWHJyb2/cnGb1J rYotngEoS8HHzeQUmHWuMTEP9/HNspE2GD8XBUeH0MZPWrDI9WjmIrclxMya1lwPZvMv 21Pj8GtSbLOSg1Hjty1y2xGQJqfFmieq7e1Z373E3QG1LaM/YP1CfLuX/0LpWxpZK654 mOkzO3B+scBPAsv+b2I+RHZWpPPOnQ1352cNI9KLD9TaCGUwsNSgmP1pnTlfd3xDU5NA INLw== X-Gm-Message-State: AOAM532Haiy+Hn5FWM++ilisd3TnTJuyClGKR6kxMx2g3G3qeGpsms+U ljtA5Bl3268zP8mj5iO/+wI= X-Google-Smtp-Source: ABdhPJwav7PbpTPE6lRzujkZ6yrrDC5Aycgug4nFeHODSjoMTWkGUOKecg5Ror2BMadj4R5bOHipCA== X-Received: by 2002:adf:e511:: with SMTP id j17mr13477973wrm.17.1612096594084; Sun, 31 Jan 2021 04:36:34 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id q6sm21580414wrw.43.2021.01.31.04.36.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 04:36:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 05/10] meson: Introduce target-specific Kconfig To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: Peter Maydell , Sarah Harris , Cornelia Huck , Sagar Karandikar , "Michael S. Tsirkin" , Anthony Green , Mark Cave-Ayland , Thomas Huth , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Guan Xuetao , Marek Vasut , qemu-block@nongnu.org, David Hildenbrand , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Richard Henderson , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik , Stafford Horne , Palmer Dabbelt , David Gibson , Kevin Wolf , qemu-riscv@nongnu.org, Yoshinori Sato , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Max Reitz , Michael Walle , qemu-ppc@nongnu.org, Aurelien Jarno References: <20210131111316.232778-1-f4bug@amsat.org> <20210131111316.232778-6-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Sun, 31 Jan 2021 13:36:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131111316.232778-6-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 12:36:43 -0000 On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote: > Add a target-specific Kconfig. > > Target foo now has CONFIG_FOO defined. > > Two architecture have a particularity, ARM and MIPS: > their 64-bit version include the 32-bit subset. > > Signed-off-by: Philippe Mathieu-Daudé > --- ... > diff --git a/meson.build b/meson.build > index f00b7754fd4..a2dda0ce95e 100644 > --- a/meson.build > +++ b/meson.build > @@ -1322,7 +1322,8 @@ > command: [minikconf, > get_option('default_devices') ? '--defconfig' : '--allnoconfig', > config_devices_mak, '@DEPFILE@', '@INPUT@', > - host_kconfig, accel_kconfig]) > + host_kconfig, accel_kconfig, > + 'CONFIG_' + config_target['TARGET_ARCH'].to_upper() + '=y']) > > config_devices_data = configuration_data() > config_devices = keyval.load(config_devices_mak) > diff --git a/Kconfig b/Kconfig > index bf694c42afe..c01e261e4e9 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -1,4 +1,5 @@ > source Kconfig.host > source backends/Kconfig > source accel/Kconfig > +source target/Kconfig > source hw/Kconfig > diff --git a/target/Kconfig b/target/Kconfig > new file mode 100644 > index 00000000000..a6f719f223a > --- /dev/null > +++ b/target/Kconfig > @@ -0,0 +1,23 @@ > +source alpha/Kconfig > +source arm/Kconfig > +source avr/Kconfig > +source cris/Kconfig > +source hppa/Kconfig > +source i386/Kconfig > +source lm32/Kconfig > +source m68k/Kconfig > +source microblaze/Kconfig > +source mips/Kconfig > +source moxie/Kconfig > +source nios2/Kconfig > +source openrisc/Kconfig > +source ppc/Kconfig > +source riscv/Kconfig > +source rx/Kconfig > +source s390x/Kconfig > +source sh4/Kconfig > +source sparc/Kconfig > +source tilegx/Kconfig > +source tricore/Kconfig > +source unicore32/Kconfig > +source xtensa/Kconfig > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > new file mode 100644 > index 00000000000..3f3394a22b2 > --- /dev/null > +++ b/target/arm/Kconfig > @@ -0,0 +1,6 @@ > +config ARM > + bool > + > +config AARCH64 > + bool > + select ARM This isn't correct yet, as Kconfig is primarly designed for devices, and per docs/devel/kconfig.rst: "devices are usually ``default y`` if and only if they have at least one ``depends on``;" So having one machine "depends on AARCH64" selects AARCH64 on ARM :/ I'll see if explicit each arch as 'default n' helps... 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id h207sm15855648wme.18.2021.01.31.04.42.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 04:42:43 -0800 (PST) Subject: Re: [PATCH v6 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Fam Zheng , Claudio Fontana , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-7-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <80af7db7-2311-7cc5-93a0-f0609b0222d0@redhat.com> Date: Sun, 31 Jan 2021 13:42:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-7-f4bug@amsat.org> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.351, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 12:42:53 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Beside, KVM only supports A-profile, thus won't be able to run > R-profile cpus. > > Only enable the following ARMv7 R-Profile CPUs when TCG is available: > > - Cortex-R5 > - Cortex-R5F > > The following machine is no more built when TCG is disabled: > > - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/aarch64-softmmu.mak | 1 - > hw/arm/Kconfig | 2 ++ > target/arm/Kconfig | 4 ++++ > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak > index 958b1e08e40..a4202f56817 100644 > --- a/default-configs/devices/aarch64-softmmu.mak > +++ b/default-configs/devices/aarch64-softmmu.mak > @@ -3,6 +3,5 @@ > # We support all the 32 bit boards so need all their config > include arm-softmmu.mak > > -CONFIG_XLNX_ZYNQMP_ARM=y > CONFIG_XLNX_VERSAL=y > CONFIG_SBSA_REF=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 6c4bce4d637..4baf1f97694 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -360,8 +360,10 @@ config STM32F405_SOC > > config XLNX_ZYNQMP_ARM > bool > + default y if TCG && ARM The correct line is: "default y if TCG && AARCH64" > select AHCI > select ARM_GIC > + select ARM_V7R > select CADENCE > select DDC > select DPCD > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index fbb7bba9018..4dc96c46520 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -18,6 +18,10 @@ config ARM_V6 > bool > depends on TCG && ARM > > +config ARM_V7R > + bool > + depends on TCG && ARM > + > config ARM_V7M > bool > select PTIMER > From MAILER-DAEMON Sun Jan 31 08:19:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6CdX-0002oI-Ih for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id h207sm15947682wme.18.2021.01.31.05.19.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 05:19:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register To: P J P , QEMU Security Cc: "Edgar E . Iglesias" , Peter Maydell , Darren Kenny , Sai Pavan Boddu , Li Qiang , qemu-stable@nongnu.org, qemu-devel@nongnu.org, Alexander Bulekov , qemu-arm@nongnu.org, Luc Michel References: <20210131103401.217160-1-f4bug@amsat.org> <3a94e327-0454-bf43-552a-1c84407e1d7d@amsat.org> <20p82p5p-ns25-n434-37os-n55013s6313@erqung.pbz> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6d29aa57-2e6e-e81d-831f-803d9aae798f@amsat.org> Date: Sun, 31 Jan 2021 14:19:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20p82p5p-ns25-n434-37os-n55013s6313@erqung.pbz> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 13:19:30 -0000 Forwarding to qemu-security@ to see if this issue is worth a CVE. On 1/31/21 12:57 PM, P J P wrote: > +-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+ > | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: > | > Per the ARM Generic Interrupt Controller Architecture specification > | > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, > | > not 10: > | > > | > - Table 4-21 GICD_SGIR bit assignments > | > > | > The Interrupt ID of the SGI to forward to the specified CPU > | > interfaces. The value of this field is the Interrupt ID, in > | > the range 0-15, for example a value of 0b0011 specifies > | > Interrupt ID 3. > | > > | > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > | > index af41e2fb448..75316329516 100644 > | > --- a/hw/intc/arm_gic.c > | > +++ b/hw/intc/arm_gic.c > | > @@ -1476,7 +1476,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, > | > int target_cpu; > | > > | > cpu = gic_get_current_cpu(s); > | > - irq = value & 0x3ff; > | > + irq = value & 0xf; > | > switch ((value >> 24) & 3) { > | > case 0: > | > mask = (value >> 16) & ALL_CPU_MASK; > | > > > * Looks okay. > > > | > Correct the irq mask to fix an undefined behavior (which eventually > | > lead to a heap-buffer-overflow, see [Buglink]): > | > > | > $ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio > | > [I 1612088147.116987] OPENED > | > [R +0.278293] writel 0x8000f00 0xff4affb0 > | > ../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]' > | > SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13 > | > > | > Cc: qemu-stable@nongnu.org > | > Fixes: 9ee6e8bb853 ("ARMv7 support.") > | > Buglink: https://bugs.launchpad.net/qemu/+bug/1913916 > | > Buglink: https://bugs.launchpad.net/qemu/+bug/1913917 > | > | > --- > | > Isnt it worth a CVE to help distributions track backports? > | > --- > > * Please send such report(s) to 'qemu-security' list to be triaged as > potential security ones. > > > Thank you. > -- > Prasad J Pandit / Red Hat Product Security Team > 8685 545E B54C 486B C6EB 271E E285 8B5A F050 DE8D > From MAILER-DAEMON Sun Jan 31 09:18:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6DYS-0000yk-S5 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:18:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DYN-0000yJ-UY; Sun, 31 Jan 2021 09:18:19 -0500 Received: from mx2.suse.de ([195.135.220.15]:54196) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DYM-0007aE-By; Sun, 31 Jan 2021 09:18:15 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id C0275ABDA; Sun, 31 Jan 2021 14:18:10 +0000 (UTC) Subject: Re: [PATCH v6 01/11] sysemu/tcg: Introduce tcg_builtin() helper To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , Markus Armbruster References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-2-f4bug@amsat.org> From: Claudio Fontana Message-ID: <87d562ba-20e5-ee50-8793-59d77564f4da@suse.de> Date: Sun, 31 Jan 2021 15:18:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-2-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:18:19 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > Modules are registered early with type_register_static(). > > We would like to call tcg_enabled() when registering QOM types, Hi Philippe, could this not be controlled by meson at this stage? On X86, I register the tcg-specific types in tcg/* in modules that are only built for TCG. Maybe tcg_builtin() is useful anyway, thinking long term at loadable modules, but there we are interested in whether tcg code is available or not, regardless of whether it's builtin, or needs to be loaded via a .so plugin.. maybe tcg_available()? Ciao, Claudio > but tcg_enabled() returns tcg_allowed which is a runtime property > initialized later (See commit 2f181fbd5a9 which introduced the > MachineInitPhase in "hw/qdev-core.h" representing the different > phases of machine initialization and commit 0427b6257e2 which > document the initialization order). > > As we are only interested if the TCG accelerator is builtin, > regardless of being enabled, introduce the tcg_builtin() helper. > > Signed-off-by: Philippe Mathieu-Daudé > --- > Cc: Markus Armbruster > --- > include/sysemu/tcg.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h > index 00349fb18a7..6ac5c2ca89d 100644 > --- a/include/sysemu/tcg.h > +++ b/include/sysemu/tcg.h > @@ -13,8 +13,10 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); > #ifdef CONFIG_TCG > extern bool tcg_allowed; > #define tcg_enabled() (tcg_allowed) > +#define tcg_builtin() 1 > #else > #define tcg_enabled() 0 > +#define tcg_builtin() 0 > #endif > > #endif > From MAILER-DAEMON Sun Jan 31 09:19:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Da2-00034n-Fb for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:19:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DZr-00031S-Pc; Sun, 31 Jan 2021 09:19:49 -0500 Received: from mx2.suse.de ([195.135.220.15]:54550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DZq-00085q-7e; Sun, 31 Jan 2021 09:19:47 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 57DB1AF13; Sun, 31 Jan 2021 14:19:44 +0000 (UTC) Subject: Re: [PATCH v6 02/11] exec: Restrict TCG specific headers To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-3-f4bug@amsat.org> From: Claudio Fontana Message-ID: <7a8bedbb-7e76-61bc-f158-f550d78539fa@suse.de> Date: Sun, 31 Jan 2021 15:19:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-3-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:19:49 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > Fixes when building with --disable-tcg on ARM: > > In file included from target/arm/helper.c:16: > include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory > 42 | #include "tcg-runtime.h" > | ^~~~~~~~~~~~~~~ > > Signed-off-by: Philippe Mathieu-Daudé > --- > include/exec/helper-proto.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h > index 659f9298e8f..740bff3bb4d 100644 > --- a/include/exec/helper-proto.h > +++ b/include/exec/helper-proto.h > @@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ > > #include "helper.h" > #include "trace/generated-helpers.h" > +#ifdef CONFIG_TCG > #include "tcg-runtime.h" > #include "plugin-helpers.h" > +#endif /* CONFIG_TCG */ > > #undef IN_HELPER_PROTO > > Ok, this would go away when applying the refactoring to ARM though right? Ie the file should not need including at all later on right? Anyway: Reviewed-by: Claudio Fontana From MAILER-DAEMON Sun Jan 31 09:21:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6DbK-00046A-6I for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:21:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DbG-00042g-VN; Sun, 31 Jan 2021 09:21:15 -0500 Received: from mx2.suse.de ([195.135.220.15]:54862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DbF-0000EI-B1; Sun, 31 Jan 2021 09:21:14 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 01E3FB159; Sun, 31 Jan 2021 14:21:11 +0000 (UTC) Subject: Re: [PATCH v6 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-4-f4bug@amsat.org> From: Claudio Fontana Message-ID: <7798c062-b657-336d-ee51-e24465c5bd2c@suse.de> Date: Sun, 31 Jan 2021 15:21:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-4-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:21:16 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Only enable the following ARMv4 CPUs when TCG is available: > > - StrongARM (SA1100/1110) > - OMAP1510 (TI925T) > > The following machines are no more built when TCG is disabled: > > - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310) > - sx1 Siemens SX1 (OMAP310) V2 > - sx1-v1 Siemens SX1 (OMAP310) V1 > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 2 -- > hw/arm/Kconfig | 4 ++++ > target/arm/Kconfig | 4 ++++ > 3 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 0824e9be795..6ae964c14fd 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y > CONFIG_FSL_IMX31=y > CONFIG_MUSICPAL=y > CONFIG_MUSCA=y > -CONFIG_CHEETAH=y > -CONFIG_SX1=y > CONFIG_NSERIES=y > CONFIG_STELLARIS=y > CONFIG_REALVIEW=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index f3ecb73a3d8..f2957b33bee 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -31,6 +31,8 @@ config ARM_VIRT > > config CHEETAH > bool > + default y if TCG && ARM > + select ARM_V4 > select OMAP > select TSC210X > > @@ -249,6 +251,8 @@ config COLLIE > > config SX1 > bool > + default y if TCG && ARM > + select ARM_V4 > select OMAP > > config VERSATILE > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index ae89d05c7e5..811e1e81652 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -6,6 +6,10 @@ config AARCH64 > bool > select ARM > > +config ARM_V4 > + bool > + depends on TCG && ARM > + > config ARM_V7M > bool > select PTIMER > Looks good to me Acked-by: Claudio Fontana From MAILER-DAEMON Sun Jan 31 09:23:07 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Dd5-0006RV-11 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:23:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dd3-0006O8-AI; Sun, 31 Jan 2021 09:23:05 -0500 Received: from mx2.suse.de ([195.135.220.15]:55226) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dcy-00010q-Lt; Sun, 31 Jan 2021 09:23:05 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id CBB57ABD6; Sun, 31 Jan 2021 14:22:58 +0000 (UTC) Subject: Re: [PATCH v6 04/11] target/arm: Restrict ARMv5 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-5-f4bug@amsat.org> From: Claudio Fontana Message-ID: <553ccc92-5188-0779-fed7-be77f9c160e8@suse.de> Date: Sun, 31 Jan 2021 15:22:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-5-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:23:06 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Only enable the following ARMv5 CPUs when TCG is available: > > - ARM926 > - ARM946 > - ARM1026 > - XScale (PXA250/255/260/261/262/270) > > The following machines are no more built when TCG is disabled: > > - akita Sharp SL-C1000 (Akita) PDA (PXA270) > - ast2500-evb Aspeed AST2500 EVB (ARM1176) > - ast2600-evb Aspeed AST2600 EVB (Cortex A7) > - borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270) > - canon-a1100 Canon PowerShot A1100 IS (ARM946) > - collie Sharp SL-5500 (Collie) PDA (SA-1110) > - connex Gumstix Connex (PXA255) > - g220a-bmc Bytedance G220A BMC (ARM1176) > - imx25-pdk ARM i.MX25 PDK board (ARM926) > - integratorcp ARM Integrator/CP (ARM926EJ-S) > - mainstone Mainstone II (PXA27x) > - musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S) > - palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S) > - realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S) > - romulus-bmc OpenPOWER Romulus BMC (ARM1176) > - sonorapass-bmc OCP SonoraPass BMC (ARM1176) > - spitz Sharp SL-C3000 (Spitz) PDA (PXA270) > - supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S) > - swift-bmc OpenPOWER Swift BMC (ARM1176) > - tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7) > - terrier Sharp SL-C3200 (Terrier) PDA (PXA270) > - tosa Sharp SL-6000 (Tosa) PDA (PXA255) > - verdex Gumstix Verdex (PXA270) > - versatileab ARM Versatile/AB (ARM926EJ-S) > - versatilepb ARM Versatile/PB (ARM926EJ-S) > - witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176) > - z2 Zipit Z2 (PXA27x) > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 12 ------------ > hw/arm/realview.c | 5 ++++- > tests/qtest/cdrom-test.c | 6 +++++- > hw/arm/Kconfig | 19 +++++++++++++++++++ > target/arm/Kconfig | 4 ++++ > 5 files changed, 32 insertions(+), 14 deletions(-) > > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 6ae964c14fd..0aad35da0c4 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y > CONFIG_CUBIEBOARD=y > CONFIG_EXYNOS4=y > CONFIG_HIGHBANK=y > -CONFIG_INTEGRATOR=y > CONFIG_FSL_IMX31=y > -CONFIG_MUSICPAL=y > CONFIG_MUSCA=y > CONFIG_NSERIES=y > CONFIG_STELLARIS=y > CONFIG_REALVIEW=y > -CONFIG_VERSATILE=y > CONFIG_VEXPRESS=y > CONFIG_ZYNQ=y > -CONFIG_MAINSTONE=y > -CONFIG_GUMSTIX=y > -CONFIG_SPITZ=y > -CONFIG_TOSA=y > -CONFIG_Z2=y > CONFIG_NPCM7XX=y > -CONFIG_COLLIE=y > -CONFIG_ASPEED_SOC=y > CONFIG_NETDUINO2=y > CONFIG_NETDUINOPLUS2=y > CONFIG_MPS2=y > CONFIG_RASPI=y > -CONFIG_DIGIC=y > CONFIG_SABRELITE=y > CONFIG_EMCRAFT_SF2=y > CONFIG_MICROBIT=y > -CONFIG_FSL_IMX25=y > CONFIG_FSL_IMX7=y > CONFIG_FSL_IMX6UL=y > CONFIG_ALLWINNER_H3=y > diff --git a/hw/arm/realview.c b/hw/arm/realview.c > index 0831159d158..2dcf0a4c23e 100644 > --- a/hw/arm/realview.c > +++ b/hw/arm/realview.c > @@ -18,6 +18,7 @@ > #include "hw/pci/pci.h" > #include "net/net.h" > #include "sysemu/sysemu.h" > +#include "sysemu/tcg.h" > #include "hw/boards.h" > #include "hw/i2c/i2c.h" > #include "exec/address-spaces.h" > @@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = { > > static void realview_machine_init(void) > { > - type_register_static(&realview_eb_type); > + if (tcg_builtin()) { > + type_register_static(&realview_eb_type); > + } > type_register_static(&realview_eb_mpcore_type); > type_register_static(&realview_pb_a8_type); > type_register_static(&realview_pbx_a9_type); > diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c > index 5af944a5fb7..1f1bc26fa7a 100644 > --- a/tests/qtest/cdrom-test.c > +++ b/tests/qtest/cdrom-test.c > @@ -222,7 +222,11 @@ int main(int argc, char **argv) > add_cdrom_param_tests(mips64machines); > } else if (g_str_equal(arch, "arm") || g_str_equal(arch, "aarch64")) { > const char *armmachines[] = { > - "realview-eb", "realview-eb-mpcore", "realview-pb-a8", > +#ifdef CONFIG_TCG > + "realview-eb", > +#endif /* CONFIG_TCG */ > + "realview-eb-mpcore", > + "realview-pb-a8", > "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15", > "vexpress-a9", "virt", NULL > }; > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index f2957b33bee..560442bfc5c 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -42,6 +42,8 @@ config CUBIEBOARD > > config DIGIC > bool > + default y if TCG && ARM > + select ARM_V5 > select PTIMER > select PFLASH_CFI02 > > @@ -72,6 +74,8 @@ config HIGHBANK > > config INTEGRATOR > bool > + default y if TCG && ARM > + select ARM_V5 > select ARM_TIMER > select INTEGRATOR_DEBUG > select PL011 # UART > @@ -84,6 +88,7 @@ config INTEGRATOR > > config MAINSTONE > bool > + default y if TCG && ARM > select PXA2XX > select PFLASH_CFI01 > select SMC91C111 > @@ -98,6 +103,8 @@ config MUSCA > > config MUSICPAL > bool > + default y if TCG && ARM > + select ARM_V5 > select OR_IRQ > select BITBANG_I2C > select MARVELL_88W8618 > @@ -138,6 +145,7 @@ config OMAP > > config PXA2XX > bool > + select ARM_V5 > select FRAMEBUFFER > select I2C > select SERIAL > @@ -147,12 +155,14 @@ config PXA2XX > > config GUMSTIX > bool > + default y if TCG && ARM > select PFLASH_CFI01 > select SMC91C111 > select PXA2XX > > config TOSA > bool > + default y if TCG && ARM > select ZAURUS # scoop > select MICRODRIVE > select PXA2XX > @@ -160,6 +170,7 @@ config TOSA > > config SPITZ > bool > + default y if TCG && ARM > select ADS7846 # touch-screen controller > select MAX111X # A/D converter > select WM8750 # audio codec > @@ -172,6 +183,7 @@ config SPITZ > > config Z2 > bool > + default y if TCG && ARM > select PFLASH_CFI01 > select WM8750 > select PL011 # UART > @@ -245,6 +257,7 @@ config STRONGARM > > config COLLIE > bool > + default y if TCG && ARM > select PFLASH_CFI01 > select ZAURUS # scoop > select STRONGARM > @@ -257,6 +270,8 @@ config SX1 > > config VERSATILE > bool > + default y if TCG && ARM > + select ARM_V5 > select ARM_TIMER # sp804 > select PFLASH_CFI01 > select LSI_SCSI_PCI > @@ -376,6 +391,8 @@ config NPCM7XX > > config FSL_IMX25 > bool > + default y if TCG && ARM > + select ARM_V5 > select IMX > select IMX_FEC > select IMX_I2C > @@ -402,6 +419,8 @@ config FSL_IMX6 > > config ASPEED_SOC > bool > + default y if TCG && ARM > + select ARM_V5 > select DS1338 > select FTGMAC100 > select I2C > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index 811e1e81652..9b3635617dc 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -10,6 +10,10 @@ config ARM_V4 > bool > depends on TCG && ARM > > +config ARM_V5 > + bool > + depends on TCG && ARM > + > config ARM_V7M > bool > select PTIMER > Looks good to me Acked-by: Claudio Fontana From MAILER-DAEMON Sun Jan 31 09:29:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Dj8-0002os-S6 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:29:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dj7-0002oQ-ME; Sun, 31 Jan 2021 09:29:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:56152) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dj5-0003f4-LX; Sun, 31 Jan 2021 09:29:21 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 86722AD37; Sun, 31 Jan 2021 14:29:17 +0000 (UTC) Subject: Re: [PATCH v6 05/11] target/arm: Restrict ARMv6 cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell , Eduardo Habkost References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-6-f4bug@amsat.org> From: Claudio Fontana Message-ID: <795e5835-bd91-8857-11b5-7d366a0a84df@suse.de> Date: Sun, 31 Jan 2021 15:29:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-6-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:29:21 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Only enable the following ARMv6 CPUs when TCG is available: > > - ARM1136 > - ARM1176 > - ARM11MPCore > - Cortex-M0 > > The following machines are no more built when TCG is disabled: > > - kzm ARM KZM Emulation Baseboard (ARM1136) > - microbit BBC micro:bit (Cortex-M0) > - n800 Nokia N800 tablet aka. RX-34 (OMAP2420) > - n810 Nokia N810 tablet aka. RX-44 (OMAP2420) > - realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore) > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 2 -- > hw/arm/realview.c | 2 +- > tests/qtest/cdrom-test.c | 2 +- > hw/arm/Kconfig | 6 ++++++ > target/arm/Kconfig | 4 ++++ > 5 files changed, 12 insertions(+), 4 deletions(-) > > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 0aad35da0c4..175530595ce 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y > CONFIG_CUBIEBOARD=y > CONFIG_EXYNOS4=y > CONFIG_HIGHBANK=y > -CONFIG_FSL_IMX31=y > CONFIG_MUSCA=y > -CONFIG_NSERIES=y > CONFIG_STELLARIS=y > CONFIG_REALVIEW=y > CONFIG_VEXPRESS=y > diff --git a/hw/arm/realview.c b/hw/arm/realview.c > index 2dcf0a4c23e..0606d22da14 100644 > --- a/hw/arm/realview.c > +++ b/hw/arm/realview.c > @@ -463,8 +463,8 @@ static void realview_machine_init(void) > { > if (tcg_builtin()) { > type_register_static(&realview_eb_type); > + type_register_static(&realview_eb_mpcore_type); > } > - type_register_static(&realview_eb_mpcore_type); > type_register_static(&realview_pb_a8_type); > type_register_static(&realview_pbx_a9_type); > } > diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c > index 1f1bc26fa7a..cb0409c5a11 100644 > --- a/tests/qtest/cdrom-test.c > +++ b/tests/qtest/cdrom-test.c > @@ -224,8 +224,8 @@ int main(int argc, char **argv) > const char *armmachines[] = { > #ifdef CONFIG_TCG > "realview-eb", > -#endif /* CONFIG_TCG */ > "realview-eb-mpcore", > +#endif /* CONFIG_TCG */ > "realview-pb-a8", > "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15", > "vexpress-a9", "virt", NULL > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 560442bfc5c..6c4bce4d637 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -123,6 +123,8 @@ config NETDUINOPLUS2 > > config NSERIES > bool > + default y if TCG && ARM > + select ARM_V6 > select OMAP > select TMP105 # tempature sensor > select BLIZZARD # LCD/TV controller > @@ -401,6 +403,8 @@ config FSL_IMX25 > > config FSL_IMX31 > bool > + default y if TCG && ARM > + select ARM_V6 > select SERIAL > select IMX > select IMX_I2C > @@ -478,11 +482,13 @@ config FSL_IMX6UL > > config MICROBIT > bool > + default y if TCG && ARM > select NRF51_SOC > > config NRF51_SOC > bool > select I2C > + select ARM_V6 > select ARM_V7M > select UNIMP > > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index 9b3635617dc..fbb7bba9018 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -14,6 +14,10 @@ config ARM_V5 > bool > depends on TCG && ARM > > +config ARM_V6 > + bool > + depends on TCG && ARM > + > config ARM_V7M > bool > select PTIMER > Added Cc: Eduardo, Looks good to me in general, Acked-by: Claudio Fontana I am just wondering about that if (tcg_builtin()) / (or _available() as I suggest elsewhere), should we instead use the build system already at this stage, so no such check is necessary? It could be a successive change, but then tcg_builtin() would be introduced, only to become useless after the proper refactoring is done, and the build system is used to select the right modules to compile, which would do the registration. Ciao, Claudio From MAILER-DAEMON Sun Jan 31 09:30:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Djj-0003N6-9f for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:30:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Djh-0003Li-5v; Sun, 31 Jan 2021 09:29:57 -0500 Received: from mx2.suse.de ([195.135.220.15]:56208) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Djf-0003v6-G5; Sun, 31 Jan 2021 09:29:56 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 473A1AD29; Sun, 31 Jan 2021 14:29:53 +0000 (UTC) Subject: Re: [PATCH v6 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-7-f4bug@amsat.org> From: Claudio Fontana Message-ID: <66aa95e5-8849-ca1f-9413-be17dea61179@suse.de> Date: Sun, 31 Jan 2021 15:29:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-7-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:29:57 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Beside, KVM only supports A-profile, thus won't be able to run > R-profile cpus. > > Only enable the following ARMv7 R-Profile CPUs when TCG is available: > > - Cortex-R5 > - Cortex-R5F > > The following machine is no more built when TCG is disabled: > > - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/aarch64-softmmu.mak | 1 - > hw/arm/Kconfig | 2 ++ > target/arm/Kconfig | 4 ++++ > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak > index 958b1e08e40..a4202f56817 100644 > --- a/default-configs/devices/aarch64-softmmu.mak > +++ b/default-configs/devices/aarch64-softmmu.mak > @@ -3,6 +3,5 @@ > # We support all the 32 bit boards so need all their config > include arm-softmmu.mak > > -CONFIG_XLNX_ZYNQMP_ARM=y > CONFIG_XLNX_VERSAL=y > CONFIG_SBSA_REF=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 6c4bce4d637..4baf1f97694 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -360,8 +360,10 @@ config STM32F405_SOC > > config XLNX_ZYNQMP_ARM > bool > + default y if TCG && ARM > select AHCI > select ARM_GIC > + select ARM_V7R > select CADENCE > select DDC > select DPCD > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index fbb7bba9018..4dc96c46520 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -18,6 +18,10 @@ config ARM_V6 > bool > depends on TCG && ARM > > +config ARM_V7R > + bool > + depends on TCG && ARM > + > config ARM_V7M > bool > select PTIMER > Acked-by: Claudio Fontana From MAILER-DAEMON Sun Jan 31 09:30:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6DkW-0003vV-20 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:30:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DkQ-0003sA-0i; Sun, 31 Jan 2021 09:30:43 -0500 Received: from mx2.suse.de ([195.135.220.15]:56344) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6DkJ-0004Gi-OX; Sun, 31 Jan 2021 09:30:41 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B8E87AD3E; Sun, 31 Jan 2021 14:30:33 +0000 (UTC) Subject: Re: [PATCH v6 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-8-f4bug@amsat.org> From: Claudio Fontana Message-ID: Date: Sun, 31 Jan 2021 15:30:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-8-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:30:43 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > Beside, KVM only supports A-profile, thus won't be able to run > M-profile cpus. > > Only enable the following ARMv7 M-Profile CPUs when TCG is available: > > - Cortex-M0 > - Cortex-M3 > - Cortex-M4 > - Cortex-M33 > > The following machines are no more built when TCG is disabled: > > - emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010) > - highbank Calxeda Highbank (ECX-1000) > - lm3s6965evb Stellaris LM3S6965EVB (Cortex-M3) > - lm3s811evb Stellaris LM3S811EVB (Cortex-M3) > - midway Calxeda Midway (ECX-2000) > - mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3 > - mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4 > - mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7 > - mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33 > - mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3 > - mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33 > - musca-a ARM Musca-A board (dual Cortex-M33) > - musca-b1 ARM Musca-B1 board (dual Cortex-M33) > - netduino2 Netduino 2 Machine (Cortex-M3) > - netduinoplus2 Netduino Plus 2 Machine(Cortex-M4) > > We don't need to enforce CONFIG_ARM_V7M in default-configs anymore. > > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 11 ----------- > hw/arm/Kconfig | 7 +++++++ > target/arm/Kconfig | 1 + > 3 files changed, 8 insertions(+), 11 deletions(-) > > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 175530595ce..0fc80d7d6df 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -1,28 +1,17 @@ > # Default configuration for arm-softmmu > > -# TODO: ARM_V7M is currently always required - make this more flexible! > -CONFIG_ARM_V7M=y > - > # CONFIG_PCI_DEVICES=n > # CONFIG_TEST_DEVICES=n > > CONFIG_ARM_VIRT=y > CONFIG_CUBIEBOARD=y > CONFIG_EXYNOS4=y > -CONFIG_HIGHBANK=y > -CONFIG_MUSCA=y > -CONFIG_STELLARIS=y > CONFIG_REALVIEW=y > CONFIG_VEXPRESS=y > CONFIG_ZYNQ=y > CONFIG_NPCM7XX=y > -CONFIG_NETDUINO2=y > -CONFIG_NETDUINOPLUS2=y > -CONFIG_MPS2=y > CONFIG_RASPI=y > CONFIG_SABRELITE=y > -CONFIG_EMCRAFT_SF2=y > -CONFIG_MICROBIT=y > CONFIG_FSL_IMX7=y > CONFIG_FSL_IMX6UL=y > CONFIG_ALLWINNER_H3=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 4baf1f97694..62f8b0d24e7 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -60,6 +60,7 @@ config EXYNOS4 > > config HIGHBANK > bool > + default y if TCG && ARM > select A9MPCORE > select A15MPCORE > select AHCI > @@ -95,6 +96,7 @@ config MAINSTONE > > config MUSCA > bool > + default y if TCG && ARM > select ARMSSE > select PL011 > select PL031 > @@ -115,10 +117,12 @@ config MUSICPAL > > config NETDUINO2 > bool > + default y if TCG && ARM > select STM32F205_SOC > > config NETDUINOPLUS2 > bool > + default y if TCG && ARM > select STM32F405_SOC > > config NSERIES > @@ -240,6 +244,7 @@ config SABRELITE > > config STELLARIS > bool > + default y if TCG && ARM > select ARM_V7M > select CMSDK_APB_WATCHDOG > select I2C > @@ -443,6 +448,7 @@ config ASPEED_SOC > > config MPS2 > bool > + default y if TCG && ARM > select ARMSSE > select LAN9118 > select MPS2_FPGAIO > @@ -496,6 +502,7 @@ config NRF51_SOC > > config EMCRAFT_SF2 > bool > + default y if TCG && ARM > select MSF2 > select SSI_M25P80 > > diff --git a/target/arm/Kconfig b/target/arm/Kconfig > index 4dc96c46520..07a2fad7a2b 100644 > --- a/target/arm/Kconfig > +++ b/target/arm/Kconfig > @@ -24,4 +24,5 @@ config ARM_V7R > > config ARM_V7M > bool > + depends on TCG && ARM > select PTIMER > Acked-by: Claudio Fontana From MAILER-DAEMON Sun Jan 31 09:40:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Dtg-0000lh-Ew for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 09:40:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dte-0000kw-W5; Sun, 31 Jan 2021 09:40:15 -0500 Received: from mx2.suse.de ([195.135.220.15]:58140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Dtc-0008Ru-Td; Sun, 31 Jan 2021 09:40:14 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id A668DAD2B; Sun, 31 Jan 2021 14:40:10 +0000 (UTC) Subject: Re: [PATCH v6 00/11] Support disabling TCG on ARM (part 2) To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Fam Zheng , Laurent Vivier , Thomas Huth , kvm@vger.kernel.org, qemu-block@nongnu.org, Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Richard Henderson , John Snow , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20210131115022.242570-1-f4bug@amsat.org> From: Claudio Fontana Message-ID: <9924223e-3aeb-5200-c7fa-f120a7ae30fe@suse.de> Date: Sun, 31 Jan 2021 15:40:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20210131115022.242570-1-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 14:40:15 -0000 On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: > Cover from Samuel Ortiz from (part 1) [1]: > > This patchset allows for building and running ARM targets with TCG > disabled. [...] > > The rationale behind this work comes from the NEMU project where > we're trying to only support x86 and ARM 64-bit architectures, > without including the TCG code base. We can only do so if we can > build and run ARM binaries with TCG disabled. > > Peter mentioned in v5 [6] that since 32-bit host has been removed, > we have to remove v7 targets. This is not done in this series, as > linking succeeds, and there is enough material to review (no need > to spend time on that extra patch if the current approach is not > accepted). > > CI: https://gitlab.com/philmd/qemu/-/pipelines/249272441 > > v6: > - rebased on "target/arm/Kconfig" series > - introduce/use tcg_builtin() for realview machines > > v5: > - addressed Paolo/Richard/Thomas review comments from v4 [5]. > > v4 almost 2 years later... [2]: > - Rebased on Meson > - Addressed Richard review comments > - Addressed Claudio review comments > > v3 almost 18 months later [3]: > - Rebased > - Addressed Thomas review comments > - Added Travis-CI job to keep building --disable-tcg on ARM > > v2 [4]: > - Addressed review comments from Richard and Thomas from v1 [1] > > Regards, > > Phil. > > [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html > [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html > [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html > [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html > [5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html > [6]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777669.html > > Based-on: <20210131111316.232778-1-f4bug@amsat.org> > "target: Provide target-specific Kconfig" > > Philippe Mathieu-Daudé (9): > sysemu/tcg: Introduce tcg_builtin() helper > exec: Restrict TCG specific headers > target/arm: Restrict ARMv4 cpus to TCG accel > target/arm: Restrict ARMv5 cpus to TCG accel > target/arm: Restrict ARMv6 cpus to TCG accel > target/arm: Restrict ARMv7 R-profile cpus to TCG accel > target/arm: Restrict ARMv7 M-profile cpus to TCG accel > target/arm: Reorder meson.build rules > .travis.yml: Add a KVM-only Aarch64 job > > Samuel Ortiz (1): > target/arm: Do not build TCG objects when TCG is off > > Thomas Huth (1): > target/arm: Make m_helper.c optional via CONFIG_ARM_V7M > > default-configs/devices/aarch64-softmmu.mak | 1 - > default-configs/devices/arm-softmmu.mak | 27 -------- > include/exec/helper-proto.h | 2 + > include/sysemu/tcg.h | 2 + > target/arm/cpu.h | 12 ---- > hw/arm/realview.c | 7 +- > target/arm/cpu_tcg.c | 4 +- > target/arm/helper.c | 7 -- > target/arm/m_helper-stub.c | 73 +++++++++++++++++++++ > tests/qtest/cdrom-test.c | 6 +- > .travis.yml | 32 +++++++++ > hw/arm/Kconfig | 38 +++++++++++ > target/arm/Kconfig | 17 +++++ > target/arm/meson.build | 28 +++++--- > 14 files changed, 196 insertions(+), 60 deletions(-) > create mode 100644 target/arm/m_helper-stub.c > Looking at this series, just my 2 cents on how I would suggest to go forward: I could again split my series in two parts, with only the TCG Ops in the first part. Then this series could be merged, enabling --disable-tcg for ARM, then I could extend the second part of my series to include ARM as well. Wdyt? (Probably Richard?) Thanks, Claudio From MAILER-DAEMON Sun Jan 31 10:14:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6EQd-0002dc-A6 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:14:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EQb-0002cd-IF; Sun, 31 Jan 2021 10:14:17 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40463) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EQZ-0006iF-Kt; Sun, 31 Jan 2021 10:14:17 -0500 Received: by mail-wr1-x42a.google.com with SMTP id c12so13855013wrc.7; Sun, 31 Jan 2021 07:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Tau/sJuxIvYCq+2aNAnlvFVViJN2yuLitklopPIVzDY=; b=TtWZB8/t2fGCTKPS9HwAzJglAjEs3XhKNgQ10V6CGv/IVr2o4NQWZSxN4e/9qWsQr/ s7c+vSi0yTUrpWbYHyA6LuZ82fgKj4MzZZIDqP15vj7/2W6qSEcrMUI6CpomFOYcBCZP 4ZD/V0TegzVx382HwYrfnONiumFDbruq3vHNLUd2rommJNCsfmM9bDonINn2UsllBbjJ hp2vrE34cF1ZnDFgRQAlXNlStJRO1RYlH8MaDzKQUY46qEDK+nQJHtR8Ym/jcA1Tr+xx BnUwm2+p6gqip7L0BJLPHJk7zvgfDbHIr+Uqr19agZdfydwDpGjESuvORj4VxqcKWNNh jW6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=Tau/sJuxIvYCq+2aNAnlvFVViJN2yuLitklopPIVzDY=; b=AgHb7sufZma/iV3h7qw53Km5hb6efz+ThTVFZQNGftlnVkpL5YcGJ+j6A1M/gCj+m3 DrXn/VW/xsmhQsSOQGrhPW2OEg6fm7P4pxcfmHHBx+U0p3U85S1Qiktwou15eqhc7c4N MXIfrcUNBx/TZKAotrL/m1bCxkeogpB6hAMo2y7NDejubQpkteM6BV0sGJ7Yne6QO8Yp EElmu4V3QhiZ1c7vam/9+UWc9M7RA9ZU3lc9dJq1rVOyRerrG3ku0feeHlLsEKp9Q62I DpWkTeFqqnr6m0zdNCY2EdYJxls/mK4VG22U5hv3rCXgjRS7AzZ3KVNqazg6d5CKsWk8 l2RQ== X-Gm-Message-State: AOAM532rd9IdtyIGLIWVrc1pCPsEwPUwGbe2BYYht6dKSt1IE0q+H6uj qIHZaLAENB44vG9W0AwfIeGxfeqNl2s= X-Google-Smtp-Source: ABdhPJwIgDlwpI0/S1QdPSb+DE/CDxzfaK+tdTPSaQKdt/hWlLehBqr8egeHHFfgTj0FZ4pV4lbaZg== X-Received: by 2002:a05:6000:1372:: with SMTP id q18mr13720695wrz.280.1612106052749; Sun, 31 Jan 2021 07:14:12 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id t205sm18622237wmt.28.2021.01.31.07.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 07:14:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Luc Michel , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Tokarev , Andrew Baumann , Laurent Vivier Subject: [RFC PATCH 0/2] hw/arm/raspi: Restrict BCM2835 / BCM2836 SoC to TCG Date: Sun, 31 Jan 2021 16:14:08 +0100 Message-Id: <20210131151410.318649-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:14:18 -0000 Peter mentioned [*] KVM only support ARMv8 targets. Restrict the=0D non-ARMv8 machines to TCG.=0D =0D While this is still not enough to boot a raspi3 image using KVM:=0D =0D $ qemu-system-aarch64 -M raspi3b -enable-kvm ...=0D qemu-system-aarch64: ../../softmmu/physmem.c:745: cpu_address_space_init:= A=3D=0D ssertion `asidx =3D3D=3D3D 0 || !kvm_enabled()' failed.=0D Aborted (core dumped)=0D =0D This increases the odds to have a KVM-only build pass qtests.=0D =0D [*]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777669.html=0D =0D Philippe Mathieu-Daud=3DC3=3DA9 (2):=0D hw/arm/raspi: Trivial code movement=0D hw/arm/raspi: Restrict BCM2835 / BCM2836 SoC to TCG=0D =0D hw/arm/bcm2836.c | 38 +++++++++++++++++++++++---------------=0D hw/arm/raspi.c | 22 ++++++++++++++--------=0D 2 files changed, 37 insertions(+), 23 deletions(-)=0D =0D --=3D20=0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 10:14:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6EQg-0002ml-P2 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:14:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EQf-0002j6-FD; Sun, 31 Jan 2021 10:14:21 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EQd-0006ko-Tw; Sun, 31 Jan 2021 10:14:21 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m13so13851765wro.12; Sun, 31 Jan 2021 07:14:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ldhPTzxA4UPWiOW+LZ2h6Ki08VC7Oo3bcq6ZAuAin0w=; b=SrJXQmjd7iWFGHl3EDknBIdB0mMy5DNuZNVkW+dhCAOwwwaT6d3vqof3LR6THZz5XS CRKNKxQ4vvef235fsMX0jEpaw0ZeJxod+44Cakg7oc4inzeuh7hfthIv2lbW5uLJt994 j04cN+hlE8/b+DKikyYT6ZrKoi4uJHXyg67vYeuNgpDPknjE04ThO8H+rbTCaMoWs1wO RmukcZvwCO8XMxHVH7spkWvpvSG8QQdVFyOSkOETvKulaWTeK4YHrGgWfTBybWh9dZbK kiAhvPmNflrqwnF5JtTTCGyPLqWTgSsXqtg8tFo+5zW/nxTcHSuU1wpexpraeKKcCTSx n6bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ldhPTzxA4UPWiOW+LZ2h6Ki08VC7Oo3bcq6ZAuAin0w=; b=lEyD4xMC399oSFoetaUk+WhHu/QP7f/TkPNzAuc8y+IsL0udnjgNVa+F8w/f5/7SPv GY+RA5DG732e5vFBw5zCa7rEU7A9lrj0ytmBULGe+pGiMX8djBx0iPzj0SYEVQmyIga2 YhwYRzCg7kQB9Lz0H+ARGIMpGW3iCgRvf2ArpwZSVdHV3/q5CcMWdRBi4S66aneSuyV3 YMjwrRZ7AL5u6E7uGbxhWKEAEjd4khpCS4elRUxjRvtoqPKiAvS+3rkbVnbIy2+PFjvd okhKW0b33qb07iE7eEJ52z6qcHxLUxY2StyAXQuVO/LFH8Q2jikGroPA3j8BLZJmSiNS b57w== X-Gm-Message-State: AOAM532/UM5ZdndHA75Gt01v2uZLWg8cMsWJeOkktCQ/n7u0jntAzl5I m0R9FmkEOYp+qheDIi0TEUsXDo9iveE= X-Google-Smtp-Source: ABdhPJyNAI0PM+G/fGs4RplR8Pdh0f69b5dnX+34byLVepNCbGPIe90MKxk2XngzOfMp92h/ba199A== X-Received: by 2002:a5d:690b:: with SMTP id t11mr13995267wru.12.1612106057720; Sun, 31 Jan 2021 07:14:17 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id d17sm13763448wma.2.2021.01.31.07.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 07:14:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Luc Michel , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Tokarev , Andrew Baumann , Laurent Vivier Subject: [RFC PATCH 1/2] hw/arm/raspi: Trivial code movement Date: Sun, 31 Jan 2021 16:14:09 +0100 Message-Id: <20210131151410.318649-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131151410.318649-1-f4bug@amsat.org> References: <20210131151410.318649-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:14:22 -0000 Move the abstract TYPE_BCM283X and TYPE_RASPI_MACHINE declarations earlier to make the next commit easier to review. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 32 +++++++++++++++++--------------- hw/arm/raspi.c | 18 ++++++++++-------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index de7ade2878e..fd16ed87c40 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -219,20 +219,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) static const TypeInfo bcm283x_types[] = { { - .name = TYPE_BCM2835, - .parent = TYPE_BCM283X, - .class_init = bcm2835_class_init, - }, { - .name = TYPE_BCM2836, - .parent = TYPE_BCM283X, - .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 - }, { - .name = TYPE_BCM2837, - .parent = TYPE_BCM283X, - .class_init = bcm2837_class_init, -#endif - }, { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, .instance_size = sizeof(BCM283XState), @@ -240,7 +226,23 @@ static const TypeInfo bcm283x_types[] = { .class_size = sizeof(BCM283XClass), .class_init = bcm283x_class_init, .abstract = true, - } + }, + { + .name = TYPE_BCM2835, + .parent = TYPE_BCM283X, + .class_init = bcm2835_class_init, + }, { + .name = TYPE_BCM2836, + .parent = TYPE_BCM283X, + .class_init = bcm2836_class_init, + }, +#ifdef TARGET_AARCH64 + { + .name = TYPE_BCM2837, + .parent = TYPE_BCM283X, + .class_init = bcm2837_class_init, + }, +#endif }; DEFINE_TYPES(bcm283x_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 990509d3852..dce966a4dd8 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -369,6 +369,13 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) #endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { + { + .name = TYPE_RASPI_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(RaspiMachineState), + .class_size = sizeof(RaspiMachineClass), + .abstract = true, + }, { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, @@ -381,8 +388,9 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, + }, #ifdef TARGET_AARCH64 - }, { + { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, @@ -390,14 +398,8 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, + }, #endif - }, { - .name = TYPE_RASPI_MACHINE, - .parent = TYPE_MACHINE, - .instance_size = sizeof(RaspiMachineState), - .class_size = sizeof(RaspiMachineClass), - .abstract = true, - } }; DEFINE_TYPES(raspi_machine_types) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 10:14:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6EQn-00034f-FQ for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:14:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EQk-0002xq-SF; Sun, 31 Jan 2021 10:14:26 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:35717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EQj-0006mv-7l; Sun, 31 Jan 2021 10:14:26 -0500 Received: by mail-wm1-x32b.google.com with SMTP id e15so11033207wme.0; Sun, 31 Jan 2021 07:14:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r+g1tP1DkDesVdYhAnUOBWvR86/+XyTKbQQZsxh+ijo=; b=hSIFqsW4F8vJBfeIY+WbylKHqyBILO/QWN+oHD5gx2tRowQtjti8gFbzGRtW2PQzKu mHCciR6q/vLXCBJXLPTrg+JYVpTT8H5PRUXZp8S0hRmhRjztg6u2ohFMhv1uyQQmgxZn 7Ek+MdiIv/p3yf2VYrTzBWk38OKpGo5mHwvTMvcOnthRdZzodkHWp+7PtS3fO8vNQkEh eUzGHNUh5ddXDvUq3I+vzabRFbPyeeNWPhhqLOmQfdNAxZxZaocC8U7TjTHalL6ZaCn+ xV1YNZ6QujS4GoCxx5h8GTHWhllqLFlrYKVn835J0+vY/sOfc4MsScjA9EotivNG9NlN xAeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=r+g1tP1DkDesVdYhAnUOBWvR86/+XyTKbQQZsxh+ijo=; b=clBWSr2z/5vLgurb63OwdrbZu79y7UdiOKnV/6sjNlaB5K+PzpjFhknX6W5KMtJm97 k1Bg/s50HsHzhxSTN9sjdGosVjx5ntneOaqBoaHuS14kqY8wYB50XmvIF6SjbxYBXUgP N0lRcNXZopScW7JGZXXT3V98n3kOG8p3c9ZwNh1fGbkpBFZuTZe74nxlGF2x/k7Vde5O qFZ/zLkzp3hiOKJi602nGUbXxf4m4eMmLUAQ0ts7qNWyiv+jfMlB6yMiZWG/sL+HGU08 rGFK3IZTWijSdQBcNTUSYlxQMKfrokWJkhJhHGjc48LrzE9POLGls9BipXUmhrrtEGj1 b+dw== X-Gm-Message-State: AOAM531G/8dvwIAK5i6Npohi1z2jnIJ2iJqzHD2AaYqB2ViBQ7vV2hus NgInxEeK1wNpyv55AjvYhd/4izS4iLE= X-Google-Smtp-Source: ABdhPJxidqpTr3QzQlIyLmEZ1bbwOq7P/2eRvmnG+JeWWBFUdRv1yZstRnQY9MvACPPC5SLu2g+j9w== X-Received: by 2002:a05:600c:210b:: with SMTP id u11mr11676843wml.16.1612106062785; Sun, 31 Jan 2021 07:14:22 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id s4sm18304850wme.38.2021.01.31.07.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 07:14:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Luc Michel , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Tokarev , Andrew Baumann , Laurent Vivier Subject: [RFC PATCH 2/2] hw/arm/raspi: Restrict BCM2835 / BCM2836 SoC to TCG Date: Sun, 31 Jan 2021 16:14:10 +0100 Message-Id: <20210131151410.318649-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131151410.318649-1-f4bug@amsat.org> References: <20210131151410.318649-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:14:27 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). >From the various SoC used by the Raspberry Pi machines, only the BCM2837 is an ARMv8 (Cortex-A53). Restrict the BCM2835 (ARM1176) and BCM2836 (Cortex-A7) to TCG. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 6 ++++++ hw/arm/raspi.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index fd16ed87c40..3051764f2dc 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -89,6 +89,7 @@ static bool bcm283x_common_realize(DeviceState *dev, Error **errp) return true; } +#ifdef CONFIG_TCG static void bcm2835_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); @@ -107,6 +108,7 @@ static void bcm2835_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); } +#endif /* CONFIG_TCG */ static void bcm2836_realize(DeviceState *dev, Error **errp) { @@ -178,6 +180,7 @@ static void bcm283x_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; } +#ifdef CONFIG_TCG static void bcm2835_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -201,6 +204,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) bc->clusterid = 0xf; dc->realize = bcm2836_realize; }; +#endif /* CONFIG_TCG */ #ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, void *data) @@ -227,6 +231,7 @@ static const TypeInfo bcm283x_types[] = { .class_init = bcm283x_class_init, .abstract = true, }, +#ifdef CONFIG_TCG { .name = TYPE_BCM2835, .parent = TYPE_BCM283X, @@ -236,6 +241,7 @@ static const TypeInfo bcm283x_types[] = { .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, }, +#endif /* CONFIG_TCG */ #ifdef TARGET_AARCH64 { .name = TYPE_BCM2837, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index dce966a4dd8..cfa15504d9c 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -319,6 +319,7 @@ static void raspi_machine_class_common_init(MachineClass *mc, mc->default_ram_id = "ram"; }; +#ifdef CONFIG_TCG static void raspi0_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -346,6 +347,7 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = 0xa21041; raspi_machine_class_common_init(mc, rmc->board_rev); }; +#endif /* CONFIG_TCG */ #ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) @@ -376,6 +378,7 @@ static const TypeInfo raspi_machine_types[] = { .class_size = sizeof(RaspiMachineClass), .abstract = true, }, +#ifdef CONFIG_TCG { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, @@ -389,6 +392,7 @@ static const TypeInfo raspi_machine_types[] = { .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, }, +#endif /* CONFIG_TCG */ #ifdef TARGET_AARCH64 { .name = MACHINE_TYPE_NAME("raspi3ap"), -- 2.26.2 From MAILER-DAEMON Sun Jan 31 10:23:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6EZI-0001Kk-86 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EZH-0001Ih-4Y; Sun, 31 Jan 2021 10:23:15 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:41317) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EZF-0002UW-Bh; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id l7sm18733011wmg.41.2021.01.31.07.23.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:23:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v6 00/11] Support disabling TCG on ARM (part 2) To: Claudio Fontana , qemu-devel@nongnu.org Cc: Fam Zheng , Laurent Vivier , Thomas Huth , kvm@vger.kernel.org, qemu-block@nongnu.org, Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Richard Henderson , John Snow , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20210131115022.242570-1-f4bug@amsat.org> <9924223e-3aeb-5200-c7fa-f120a7ae30fe@suse.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9e3503ce-0d01-8958-9f36-6892dfe80e93@amsat.org> Date: Sun, 31 Jan 2021 16:23:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <9924223e-3aeb-5200-c7fa-f120a7ae30fe@suse.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:23:15 -0000 On 1/31/21 3:40 PM, Claudio Fontana wrote: > On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: >> Cover from Samuel Ortiz from (part 1) [1]: >> >> This patchset allows for building and running ARM targets with TCG >> disabled. [...] >> >> The rationale behind this work comes from the NEMU project where >> we're trying to only support x86 and ARM 64-bit architectures, >> without including the TCG code base. We can only do so if we can >> build and run ARM binaries with TCG disabled. >> >> Peter mentioned in v5 [6] that since 32-bit host has been removed, >> we have to remove v7 targets. This is not done in this series, as >> linking succeeds, and there is enough material to review (no need >> to spend time on that extra patch if the current approach is not >> accepted). >> >> CI: https://gitlab.com/philmd/qemu/-/pipelines/249272441 >> >> v6: >> - rebased on "target/arm/Kconfig" series >> - introduce/use tcg_builtin() for realview machines >> >> v5: >> - addressed Paolo/Richard/Thomas review comments from v4 [5]. >> >> v4 almost 2 years later... [2]: >> - Rebased on Meson >> - Addressed Richard review comments >> - Addressed Claudio review comments >> >> v3 almost 18 months later [3]: >> - Rebased >> - Addressed Thomas review comments >> - Added Travis-CI job to keep building --disable-tcg on ARM >> >> v2 [4]: >> - Addressed review comments from Richard and Thomas from v1 [1] >> >> Regards, >> >> Phil. >> >> [1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html >> [2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html >> [3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html >> [4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html >> [5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html >> [6]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg777669.html >> >> Based-on: <20210131111316.232778-1-f4bug@amsat.org> >> "target: Provide target-specific Kconfig" >> >> Philippe Mathieu-Daudé (9): >> sysemu/tcg: Introduce tcg_builtin() helper >> exec: Restrict TCG specific headers >> target/arm: Restrict ARMv4 cpus to TCG accel >> target/arm: Restrict ARMv5 cpus to TCG accel >> target/arm: Restrict ARMv6 cpus to TCG accel >> target/arm: Restrict ARMv7 R-profile cpus to TCG accel >> target/arm: Restrict ARMv7 M-profile cpus to TCG accel >> target/arm: Reorder meson.build rules >> .travis.yml: Add a KVM-only Aarch64 job >> >> Samuel Ortiz (1): >> target/arm: Do not build TCG objects when TCG is off >> >> Thomas Huth (1): >> target/arm: Make m_helper.c optional via CONFIG_ARM_V7M >> >> default-configs/devices/aarch64-softmmu.mak | 1 - >> default-configs/devices/arm-softmmu.mak | 27 -------- >> include/exec/helper-proto.h | 2 + >> include/sysemu/tcg.h | 2 + >> target/arm/cpu.h | 12 ---- >> hw/arm/realview.c | 7 +- >> target/arm/cpu_tcg.c | 4 +- >> target/arm/helper.c | 7 -- >> target/arm/m_helper-stub.c | 73 +++++++++++++++++++++ >> tests/qtest/cdrom-test.c | 6 +- >> .travis.yml | 32 +++++++++ >> hw/arm/Kconfig | 38 +++++++++++ >> target/arm/Kconfig | 17 +++++ >> target/arm/meson.build | 28 +++++--- >> 14 files changed, 196 insertions(+), 60 deletions(-) >> create mode 100644 target/arm/m_helper-stub.c >> > > Looking at this series, just my 2 cents on how I would suggest to go forward: > I could again split my series in two parts, with only the TCG Ops in the first part. > > Then this series could be merged, enabling --disable-tcg for ARM, > > then I could extend the second part of my series to include ARM as well. > > Wdyt? (Probably Richard?) ¯\_(ツ)_/¯ I respun because Richard unqueue your series, and it looks there is no big clashing. Anyhow meanwhile peer review is useful, and thanks for yours ;) > > Thanks, > > Claudio > > > > From MAILER-DAEMON Sun Jan 31 10:24:00 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Ea0-0001gE-46 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:24:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EZy-0001ef-Mz; Sun, 31 Jan 2021 10:23:58 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:42031) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EZw-0002ml-E5; Sun, 31 Jan 2021 10:23:58 -0500 Received: by mail-wr1-x433.google.com with SMTP id c4so11159764wru.9; Sun, 31 Jan 2021 07:23:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=N9YuyM8sxr9NPcEXWnKAb5THAcC1TmnrrWWYKnUD3jo=; b=QBi5WIRtPEQ20BhqZCqNGroe7Kj3kTG7qijOUvw5YJ/tN4HHiqcSHyH5XGgJP+zAKt gp8WG3M0WgVR0e4G/WMajghyQFC2LZ86rzXianKzBJdLw3RDkGNQ/qbLDYbtnFSFCxvd hehhFMabetZWd5+OjZ4mkYb62tRGzEpgs1Z3D1OUwV4UwJACASy7jFm33cEaVynAQ1W9 Av3kuVXkszEVdiBhfW8OBSKhoha3psg+Meg82ohA3OEXNoiNcNdLLL2T3hg3e5lGdVDl lxP67x33kOWmzCdiefkqMRvzwPnOlC2Hkp4fIoLNCjsVTFgtdn4xcwk5vwn+170OGb4r rWzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:to:cc:references:from:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=N9YuyM8sxr9NPcEXWnKAb5THAcC1TmnrrWWYKnUD3jo=; b=BWBDFvF+bae4SZUS++stJmfvBLEkXEHqWw85vWvwkutzwKjHcs7SJq8gNzrX6llw0s oejMosaXX/0sjc/FTlISf32HUrhsAyqqvQ8FpIkpf7fd58sl0D+68XQzfrCQF1wKaqOI 2Wk/P0j+SPu4Vr5Y8XZbCIK4Q4rckFRL4jn80JVj2QnJpzWnzI+pNSUCy4MkTt9vNvUU i/MDW46cdQqNISh7W8fe/FKel2GtJWv0r+5f7O7PZvgo1g626thZBqDQAjhUSUC2+yrx sAkZdyH/9bdqPxnanUdzF49MjaBD4n8MwEPZ0rULjM0IINM6GMKhzLXM6nWNF/TK/uOp OqlA== X-Gm-Message-State: AOAM532v25d4VRR/pE717bq5oZTKDzb6hYjMaY1fgIK+GfZqFcHwa7aI sE67sr8NNv4W8z7xcldpwdA= X-Google-Smtp-Source: ABdhPJwncVqETyvOb+KhyNe7T0QWTADFBqIuV3MWSERnkmt6/qSkcUJk6CTvmLkvvF5XQK+vWk9HBA== X-Received: by 2002:a5d:6a45:: with SMTP id t5mr13717252wrw.252.1612106633502; Sun, 31 Jan 2021 07:23:53 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id d3sm26390267wrp.79.2021.01.31.07.23.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:23:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v6 01/11] sysemu/tcg: Introduce tcg_builtin() helper To: Claudio Fontana , qemu-devel@nongnu.org, Eduardo Habkost , Igor Mammedov , Markus Armbruster Cc: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Fam Zheng , Paolo Bonzini , qemu-block@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , kvm@vger.kernel.org, Laurent Vivier , qemu-arm@nongnu.org, Richard Henderson , John Snow , Peter Maydell References: <20210131115022.242570-1-f4bug@amsat.org> <20210131115022.242570-2-f4bug@amsat.org> <87d562ba-20e5-ee50-8793-59d77564f4da@suse.de> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <009b3856-cc7d-af85-0094-69490aa6e824@amsat.org> Date: Sun, 31 Jan 2021 16:23:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <87d562ba-20e5-ee50-8793-59d77564f4da@suse.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:23:58 -0000 On 1/31/21 3:18 PM, Claudio Fontana wrote: > On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote: >> Modules are registered early with type_register_static(). >> >> We would like to call tcg_enabled() when registering QOM types, > > > Hi Philippe, > > could this not be controlled by meson at this stage? > On X86, I register the tcg-specific types in tcg/* in modules that are only built for TCG. > > Maybe tcg_builtin() is useful anyway, thinking long term at loadable modules, > but there we are interested in whether tcg code is available or not, regardless of whether it's builtin, > or needs to be loaded via a .so plugin.. > > maybe tcg_available()? The alternatives I found: - reorder things in vl.c? - use ugly #ifdef'ry, see this patch: https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg08037.html - this earlier approach I previously discarded: -- >8 -- diff --git a/include/qom/object.h b/include/qom/object.h index d378f13a116..30590c6fac3 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -403,9 +403,12 @@ struct Object * parent class initialization has occurred, but before the class itself * is initialized. This is the function to use to undo the effects of * memcpy from the parent class to the descendants. - * @class_data: Data to pass to the @class_init, + * @class_data: Data to pass to the @class_registerable, @class_init, * @class_base_init. This can be useful when building dynamic * classes. + * @registerable: This function is called when modules are registered, + * prior to any class initialization. When present and returning %false, + * the type is not registered, the class is not present (not usable). * @interfaces: The list of interfaces associated with this type. This * should point to a static array that's terminated with a zero filled * element. @@ -428,6 +431,7 @@ struct TypeInfo void (*class_base_init)(ObjectClass *klass, void *data); void *class_data; + bool (*registerable)(void *data); InterfaceInfo *interfaces; }; diff --git a/qom/object.c b/qom/object.c index 2fa0119647c..0febaffa12e 100644 --- a/qom/object.c +++ b/qom/object.c @@ -138,6 +138,10 @@ static TypeImpl *type_new(const TypeInfo *info) static TypeImpl *type_register_internal(const TypeInfo *info) { TypeImpl *ti; + + if (info->registerable && !info->registerable(info->class_data)) { + return NULL; + } ti = type_new(info); type_table_add(ti); diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 990509d3852..1a2b1889da4 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -24,6 +24,7 @@ #include "hw/loader.h" #include "hw/arm/boot.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" #include "qom/object.h" #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ @@ -368,18 +369,26 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) }; #endif /* TARGET_AARCH64 */ +static bool raspi_machine_requiring_tcg_accel(void *data) +{ + return tcg_builtin(); +} + static const TypeInfo raspi_machine_types[] = { { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, + .registerable = raspi_machine_requiring_tcg_accel, .class_init = raspi0_machine_class_init, }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, + .registerable = raspi_machine_requiring_tcg_accel, .class_init = raspi1ap_machine_class_init, }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, + .registerable = raspi_machine_requiring_tcg_accel, .class_init = raspi2b_machine_class_init, #ifdef TARGET_AARCH64 }, { --- > > Ciao, > > Claudio > >> but tcg_enabled() returns tcg_allowed which is a runtime property >> initialized later (See commit 2f181fbd5a9 which introduced the >> MachineInitPhase in "hw/qdev-core.h" representing the different >> phases of machine initialization and commit 0427b6257e2 which >> document the initialization order). >> >> As we are only interested if the TCG accelerator is builtin, >> regardless of being enabled, introduce the tcg_builtin() helper. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> Cc: Markus Armbruster >> --- >> include/sysemu/tcg.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h >> index 00349fb18a7..6ac5c2ca89d 100644 >> --- a/include/sysemu/tcg.h >> +++ b/include/sysemu/tcg.h >> @@ -13,8 +13,10 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); >> #ifdef CONFIG_TCG >> extern bool tcg_allowed; >> #define tcg_enabled() (tcg_allowed) >> +#define tcg_builtin() 1 >> #else >> #define tcg_enabled() 0 >> +#define tcg_builtin() 0 >> #endif >> >> #endif >> > From MAILER-DAEMON Sun Jan 31 10:30:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6EgM-0007J5-Og for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:30:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6EgM-0007Iu-6B; Sun, 31 Jan 2021 10:30:34 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:54642) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6EgK-00068L-Cz; Sun, 31 Jan 2021 10:30:33 -0500 Received: by mail-wm1-x330.google.com with SMTP id u14so10522532wml.4; Sun, 31 Jan 2021 07:30:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id e11sm23243632wrt.35.2021.01.31.07.30.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:30:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 6/7] hw/arm/xlnx-zcu102: Restrict ZynqMP ZCU102 board to 64-bit build From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-trivial@nongnu.org, Alistair Francis , Michael Tokarev , Laurent Vivier , Niek Linnenbank , qemu-arm@nongnu.org, Antony Pavlov , Joel Stanley References: <20210131105918.228787-1-f4bug@amsat.org> <20210131105918.228787-7-f4bug@amsat.org> <5cb160b9-f9a4-05af-9a94-ade51bf4beb7@amsat.org> Message-ID: <4134e248-b7ba-a6cf-a1b8-9409e8051c1b@amsat.org> Date: Sun, 31 Jan 2021 16:30:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <5cb160b9-f9a4-05af-9a94-ade51bf4beb7@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:30:34 -0000 On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote: > On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote: >> The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which >> is only available in the 64-bit build. It is pointless to >> have this board present in the 32-bit build where this CPU >> is not available. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> Cc: Alistair Francis >> Cc: "Edgar E. Iglesias" >> --- >> hw/arm/meson.build | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/hw/arm/meson.build b/hw/arm/meson.build >> index 059ff7382f2..345099f5a1b 100644 >> --- a/hw/arm/meson.build >> +++ b/hw/arm/meson.build >> @@ -41,7 +41,7 @@ >> arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) >> arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) >> arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) >> -arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) >> +arm_ss.add(when: ['CONFIG_XLNX_ZYNQMP_ARM', 'TARGET_AARCH64'], if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) > > Please disregard this patch, it shows that my other patch > "meson: Introduce target-specific Kconfig" is incorrect: > https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07989.html > Probably because per docs/devel/kconfig.rst "devices are usually > ``default y`` if and only if they have at least one ``depends on``". The problem is the XLNX_ZYNQMP_ARM was incorrectly selected, enabling AARCH64. https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg08014.html With this change there is no problem (and this patch is not necessary): config XLNX_ZYNQMP_ARM bool - default y if TCG && ARM + default y if TCG && AARCH64 Regards, Phil. From MAILER-DAEMON Sun Jan 31 10:31:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Eh2-0008Ga-EC for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 10:31:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Eh0-0008Ed-GO; Sun, 31 Jan 2021 10:31:14 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:39758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Egy-0006Tr-Pt; Sun, 31 Jan 2021 10:31:14 -0500 Received: by mail-wm1-x32f.google.com with SMTP id u14so11054985wmq.4; Sun, 31 Jan 2021 07:31:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:subject:from:to:cc:references:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=WbS215fq3M5FNOsNXG+850EpFpOkfDvezmq6L7LpRAY=; b=YAUM4UZmFHtZGRDkP+q2Z0Bps/Jf6VhDAJBusGF1hc9ZFxKz+qx0wJCjFVzYUpV2DG VtsdZXPxLYCkJixB5L9DTTeT7h6RgyqOG1zrjUxprI86StmpprKiD6MWY0m+oBxbu2iU vW2uBw4LADj2COpb7IUeZ6Mf5x20BoKCyt/gXyC9u644oXsEp+wB6e2aDtwC2hB9lan8 FVSRp8LFJwG21o/XH7jYg9q2cYNf5npGMmcY4r8o5gz7LYD/nHXnDq3QKJsNwv1kcoNG 0jDz9E+JM06AdqaMqwcNg22dcWNWXlhNSX6/0LvwHoZnda/qpqbE3vQb483lVwfrpUWH dYJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:subject:from:to:cc:references:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=WbS215fq3M5FNOsNXG+850EpFpOkfDvezmq6L7LpRAY=; b=GbvI6NcQ8mADs7oXrPFjUUQraqw2qLLQbsjn7nb9p3t+LsfUJGtrkXw3Ab/pMtIBts 8k0tGtE1S4onTVLMr5zRDIqRGAGa++9lb8FbiJ2EUPwQldzobz+MT7mgvRnojB7GYSDT LsaFlxeZYhDvS8Tb5map2uJZ8V/u0//GFP2zetHQqLMNN5PMvepHFhyDWNmYHgGAX5vz evvja3tBjibNRNDS/fRszele5dvzFN7CQ1A3EZtpntUoPQFHAcjZ+mDwmkfvCR/cDZ1o VDedZaKMFeGdrBck9ZtNXrJCAMcINsPpy1q5iRYvw7mdcUhjYMjguo11j3Q/C3PrxzUL 2VNA== X-Gm-Message-State: AOAM531liwiOixFNcQDuRr6ARO5BevmuaNLT4fXMnhSrPLor1bjMH8tQ mgK/SSHg9Tu55+fwTCp5vCw= X-Google-Smtp-Source: ABdhPJz3MewsfDe+l0bYnko3lOO37PYucIvII8K3CtXNGbVKvaPhW/PbNviSLWzlIaFcD1UgITGAAQ== X-Received: by 2002:a7b:c8cb:: with SMTP id f11mr11393681wml.157.1612107070657; Sun, 31 Jan 2021 07:31:10 -0800 (PST) Received: from [192.168.1.36] (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id r15sm23820444wrq.1.2021.01.31.07.31.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:31:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v2 5/7] hw/arm/sbsa-ref: Restrict SBSA-ref board to 64-bit build From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Alistair Francis , qemu-trivial@nongnu.org, Radoslaw Biernacki , Michael Tokarev , Laurent Vivier , Niek Linnenbank , qemu-arm@nongnu.org, Antony Pavlov , Leif Lindholm , Joel Stanley References: <20210131105918.228787-1-f4bug@amsat.org> <20210131105918.228787-6-f4bug@amsat.org> Message-ID: <6a392fbc-edac-5cf6-0a26-c8df2e8c4469@amsat.org> Date: Sun, 31 Jan 2021 16:31:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:31:14 -0000 On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote: > On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote: >> The SBSA-ref board only use CPUs available in the 64-bit build, >> it is pointless to have it available in the 32-bit build. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> Cc: Radoslaw Biernacki >> Cc: Leif Lindholm >> --- >> hw/arm/meson.build | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/hw/arm/meson.build b/hw/arm/meson.build >> index be39117b9b6..059ff7382f2 100644 >> --- a/hw/arm/meson.build >> +++ b/hw/arm/meson.build >> @@ -22,7 +22,7 @@ >> arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) >> arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) >> arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) >> -arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) >> +arm_ss.add(when: ['CONFIG_SBSA_REF', 'TARGET_AARCH64'], if_true: files('sbsa-ref.c')) > > Please disregard this patch, it shows that my other patch > "meson: Introduce target-specific Kconfig" is incorrect: > https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07989.html > Probably because per docs/devel/kconfig.rst "devices are usually > ``default y`` if and only if they have at least one ``depends on``". The problem is the XLNX_ZYNQMP_ARM was incorrectly selected, enabling AARCH64, pulling in CONFIG_SBSA_REF on 32-bit. https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg08014.html With this change there is no problem (and this patch is not necessary): config XLNX_ZYNQMP_ARM bool - default y if TCG && ARM + default y if TCG && AARCH64 Regards, Phil. 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id q18sm23411770wrr.55.2021.01.31.07.34.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:34:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 05/10] meson: Introduce target-specific Kconfig From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: Peter Maydell , Sarah Harris , Chris Wulff , Sagar Karandikar , "Michael S. Tsirkin" , Anthony Green , Mark Cave-Ayland , Aleksandar Rikalo , Max Filippov , Alistair Francis , Guan Xuetao , Marek Vasut , qemu-block@nongnu.org, David Hildenbrand , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Artyom Tarasenko , Thomas Huth , Eduardo Habkost , Richard Henderson , Greg Kurz , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Stafford Horne , David Gibson , Kevin Wolf , qemu-riscv@nongnu.org, Yoshinori Sato , Bastian Koppelmann , Cornelia Huck , Laurent Vivier , Max Reitz , Michael Walle , Palmer Dabbelt , Aurelien Jarno References: <20210131111316.232778-1-f4bug@amsat.org> <20210131111316.232778-6-f4bug@amsat.org> Message-ID: <4e0131d8-80a4-a0ad-f911-cd3f1f521105@amsat.org> Date: Sun, 31 Jan 2021 16:34:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:34:17 -0000 On 1/31/21 1:36 PM, Philippe Mathieu-Daudé wrote: > On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote: >> Add a target-specific Kconfig. >> >> Target foo now has CONFIG_FOO defined. >> >> Two architecture have a particularity, ARM and MIPS: >> their 64-bit version include the 32-bit subset. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- > ... > >> diff --git a/meson.build b/meson.build >> index f00b7754fd4..a2dda0ce95e 100644 >> --- a/meson.build >> +++ b/meson.build >> @@ -1322,7 +1322,8 @@ >> command: [minikconf, >> get_option('default_devices') ? '--defconfig' : '--allnoconfig', >> config_devices_mak, '@DEPFILE@', '@INPUT@', >> - host_kconfig, accel_kconfig]) >> + host_kconfig, accel_kconfig, >> + 'CONFIG_' + config_target['TARGET_ARCH'].to_upper() + '=y']) >> >> config_devices_data = configuration_data() >> config_devices = keyval.load(config_devices_mak) >> diff --git a/Kconfig b/Kconfig >> index bf694c42afe..c01e261e4e9 100644 >> --- a/Kconfig >> +++ b/Kconfig >> @@ -1,4 +1,5 @@ >> source Kconfig.host >> source backends/Kconfig >> source accel/Kconfig >> +source target/Kconfig >> source hw/Kconfig >> diff --git a/target/Kconfig b/target/Kconfig >> new file mode 100644 >> index 00000000000..a6f719f223a >> --- /dev/null >> +++ b/target/Kconfig >> @@ -0,0 +1,23 @@ >> +source alpha/Kconfig >> +source arm/Kconfig >> +source avr/Kconfig >> +source cris/Kconfig >> +source hppa/Kconfig >> +source i386/Kconfig >> +source lm32/Kconfig >> +source m68k/Kconfig >> +source microblaze/Kconfig >> +source mips/Kconfig >> +source moxie/Kconfig >> +source nios2/Kconfig >> +source openrisc/Kconfig >> +source ppc/Kconfig >> +source riscv/Kconfig >> +source rx/Kconfig >> +source s390x/Kconfig >> +source sh4/Kconfig >> +source sparc/Kconfig >> +source tilegx/Kconfig >> +source tricore/Kconfig >> +source unicore32/Kconfig >> +source xtensa/Kconfig >> diff --git a/target/arm/Kconfig b/target/arm/Kconfig >> new file mode 100644 >> index 00000000000..3f3394a22b2 >> --- /dev/null >> +++ b/target/arm/Kconfig >> @@ -0,0 +1,6 @@ >> +config ARM >> + bool >> + >> +config AARCH64 >> + bool >> + select ARM > > This isn't correct yet, as Kconfig is primarly designed for devices, > and per docs/devel/kconfig.rst: > > "devices are usually ``default y`` if and only if they have at > least one ``depends on``;" > > So having one machine "depends on AARCH64" selects AARCH64 on ARM :/ > I'll see if explicit each arch as 'default n' helps... Taking this comment back, the approach works but is fragile, as an incorrect dependency can select the wrong arch and it is hard to detect. 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id f4sm23839332wrs.34.2021.01.31.07.35.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 07:35:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel To: Peter Maydell Cc: QEMU Developers , Richard Henderson , kvm-devel , Fam Zheng , Thomas Huth , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Richard Henderson , Claudio Fontana , =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm References: <20210130015227.4071332-1-f4bug@amsat.org> <20210130015227.4071332-4-f4bug@amsat.org> <2871f7db-fe0a-51d6-312d-6d05ffa281a3@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <40ca4720-7adf-8469-2593-6e6689d03fd6@amsat.org> Date: Sun, 31 Jan 2021 16:35:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 15:36:04 -0000 On 1/30/21 7:54 PM, Peter Maydell wrote: > On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé wrote: >> >> Hi Peter, >> >> On 1/30/21 4:37 PM, Peter Maydell wrote: >>> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé wrote: >>>> >>>> KVM requires a cpu based on (at least) the ARMv7 architecture. >>> >>> These days it requires ARMv8, because we dropped 32-bit host >>> support, and all 64-bit host CPUs are v8. >> >> Oh, this comment is about the target, to justify it is pointless to >> include pre-v7 target cpus/machines in a KVM-only binary. >> >> I'll update as: >> >> "KVM requires the target cpu based on (at least) the ARMv7 >> architecture." > > KVM requires the target CPU to be at least ARMv8, because > we only support the "host" cpu type, and all KVM host CPUs > are v8, which means you can't pass a v7 CPU as the target CPU. > (This used to not be true when we still supported running > KVM on a v7 CPU like the Cortex-A15, in which case you could > pass it to the guest.) Indeed: $ qemu-system-aarch64 -M xilinx-zynq-a9 qemu-system-aarch64: KVM is not supported for this guest CPU type qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument From MAILER-DAEMON Sun Jan 31 11:12:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6FKy-00073j-UI for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:12:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6FKw-00072U-Pm for qemu-arm@nongnu.org; Sun, 31 Jan 2021 11:12:30 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:24814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1l6FKt-0007mU-KX for qemu-arm@nongnu.org; Sun, 31 Jan 2021 11:12:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1612109545; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/j+Zjll2kbbDasMODKwZPcNmLazi6q4NpcAEHcCfmtQ=; b=Xud0Pp5yHNV6/8Bf5+fTA1wwcpRqZVrRn6/yOOlz1pi2riCHljyCqwOLNRyMHWoIF84Qkh wf63AmfFf1QW/sPjRQRjfsEDEWmWK+trZIu4sCUMcs3bmOBTGcnbQKAtfTFHHYCdlMhQ8A RvcDH1gRy5MmBXBGU7LBFisRN0d2RlY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-218-s84SLo8AODO0VSeRKqRARA-1; Sun, 31 Jan 2021 11:12:23 -0500 X-MC-Unique: s84SLo8AODO0VSeRKqRARA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id E63851005504; Sun, 31 Jan 2021 16:12:21 +0000 (UTC) Received: from [10.36.114.62] (ovpn-114-62.ams2.redhat.com [10.36.114.62]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 771342BFEC; Sun, 31 Jan 2021 16:12:19 +0000 (UTC) Subject: Re: [PATCH v2] hw/arm/smmuv3: Fix addr_mask for range-based invalidation To: Zenghui Yu , qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Cc: wanghaibin.wang@huawei.com References: <20210130043220.1345-1-yuzenghui@huawei.com> From: Auger Eric Message-ID: Date: Sun, 31 Jan 2021 17:12:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20210130043220.1345-1-yuzenghui@huawei.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=63.128.21.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.351, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:12:31 -0000 Hi Zenghui, On 1/30/21 5:32 AM, Zenghui Yu wrote: > When handling guest range-based IOTLB invalidation, we should decode the TG > field into the corresponding translation granule size so that we can pass > the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to > properly emulate the architecture. > > Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") > Signed-off-by: Zenghui Yu > --- > * From v1: > - Fix the compilation error > > hw/arm/smmuv3.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index bbca0e9f20..98b99d4fe8 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > { > SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); > IOMMUTLBEvent event; > - uint8_t granule = tg; > + uint8_t granule; > > if (!tg) { > SMMUEventInfo event = {.inval_ste_allowed = true}; > @@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, > return; > } > granule = tt->granule_sz; > + } else { > + granule = tg * 2 + 10; > } > > event.type = IOMMU_NOTIFIER_UNMAP; > Acked-by: Eric Auger Thanks Eric From MAILER-DAEMON Sun Jan 31 11:44:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fpf-00085e-IH for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:44:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Fpd-00084v-K0; Sun, 31 Jan 2021 11:44:13 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:39937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Fpc-0001PZ-03; Sun, 31 Jan 2021 11:44:13 -0500 Received: by mail-wr1-x436.google.com with SMTP id c12so14026745wrc.7; Sun, 31 Jan 2021 08:44:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qTXl26BhYMMkC6cZxuxgFnk+gqy5Q4bDto7VeuMgqds=; b=jzxLW/69ks5l7t/9iBxuGGFkFJ//lIEVx3ozA1fyoN+IRfCpRvwNnvOm3uAe2M9kTD eDdQZWZBeDPOHRFJ4YzPx2g/jeuNXTvOb7njI8dULz1/T6ZRISeflY+RZ0LFoXvek1yu lxCnnywUh3QJQhRWaMceGoyomJuLq6a8ABCRhFHAtYz4ofYl7dUtu/a4K8b7+5Eio4V5 HdtPbGQeC9Z/yWdf6/OHCKINZ4/ZEAAYweDT7DH5uJjpvJdJTqLPWkJzTEdvD297pOkm LgmqHK2SweGyoSoW8wdEeoRjJ6f5IUcuMYApatXZ9VUVbChFpeePv2JJQw3U6cQv2mUx s8CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=qTXl26BhYMMkC6cZxuxgFnk+gqy5Q4bDto7VeuMgqds=; b=Aw3VS3XZk5aglL2+4/KW9J2y2Ld9bvtLJqj290WpbtpNLbirTln42dXIoha4gg8BhT yiQWKUQP+qzd7YT2NANR8KdKdP92m/PIow3tSsy6XcqNb4mxTt2m4T9uHKVK8rNXLzPs 9Sqz1107HAkfLcs8yq5YIfrdIoJJxz0Ami1VZCmgtj/vRVhenhzXnERJf6DtuqYwf6jB xVAccmhRQCNl6nU5mY1HGpWGwme3EvDrYD2W4r7V79uREcxC6UZsC1tRaqREk9rkYAV4 UW/d2IpprpxYWCt0/Lve/ta7IpD30bhW6015FS7PpN3g+ZqB5NJ6nTpaVwbTNMohxUbk UvfQ== X-Gm-Message-State: AOAM530qa4GlXNCcIuGwyvgCseoV40G3Kx++2PvCElPcXbOwT/kHuO95 QZu2NaB+Iqngi/3AZ/Xsg8T+HY8QuI4= X-Google-Smtp-Source: ABdhPJzMzBbzGyYjhed9A72B/uRi/ajJP0Yn3+dInSgI424n9GagdeuLjbSD/0j2EW6j2UEsdDSAJQ== X-Received: by 2002:a05:6000:143:: with SMTP id r3mr12930181wrx.357.1612111449892; Sun, 31 Jan 2021 08:44:09 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id a6sm17936335wmj.27.2021.01.31.08.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/5] target/arm: Restrict v7A TCG cpus to TCG accel Date: Sun, 31 Jan 2021 17:44:01 +0100 Message-Id: <20210131164406.349825-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:13 -0000 KVM requires the target cpu to be at least ARMv8 architecture.=0D =0D Restrict the last ARMv7 CPUs (A-profile) to TCG.=0D =0D (This is where I realize no need to split the v7 A/R/M profiles=0D anymore... I could have use a single ARM_V7, although it is useful=0D to have the M-profile separated).=0D =0D Based-on: <20210131115022.242570-1-f4bug@amsat.org>=0D =0D Philippe Mathieu-Daud=C3=A9 (5):=0D hw/arm: Use Kconfig 'default y' syntax instead of default-configs=0D hw/arm: Restrict ARMv7 A-profile cpus to TCG accel=0D target/arm: Restrict v8M IDAU to TCG=0D target/arm/cpu: Update coding style to make checkpatch.pl happy=0D target/arm: Restrict v7A TCG cpus to TCG accel=0D =0D default-configs/devices/aarch64-softmmu.mak | 3 -=0D default-configs/devices/arm-softmmu.mak | 12 -=0D target/arm/cpu.c | 330 --------------------=0D target/arm/cpu_tcg.c | 318 +++++++++++++++++++=0D hw/arm/Kconfig | 15 +=0D 5 files changed, 333 insertions(+), 345 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 11:44:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fpk-0008Cd-QR for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:44:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Fpi-0008AK-SK; Sun, 31 Jan 2021 11:44:18 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:38527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Fph-0001TN-DP; Sun, 31 Jan 2021 11:44:18 -0500 Received: by mail-wm1-x32a.google.com with SMTP id y187so11178079wmd.3; Sun, 31 Jan 2021 08:44:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LWcS/B5Wc5Bm+4irRgdKOqKVWu12IJGBF6ND+Mb33fs=; b=anoCizJ7OAjnCNZnGdVmDBAHuktDHRQIsqoI5jgJYZn0zabHpm+jNdkCc+vqnzx63K 9Ue3/lGyWMfxiEL+PbGytv660/CWvKx0LtvBq6SHX4el2j5FHGltHuwJ3nXA8JOTYy8Y iXZx4FrY+V8E62QX1y0RXHieCv8z5Zseev1NXebkXSgdUQN/FPNrg1cR6Q4VXnF9gzyV HQwP4YXE9tKiVKXaYoXs7q352dgP12TfcJ5EujAmVbHflq8m71fk9M+lvZLlSWZyvTnW HatxuF37Yb/ik2lUQO153PgGoWYpKWOiQ9jGtF+uecCTryM5nYTdMtlPD/IDQ5KjlCuY tvQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LWcS/B5Wc5Bm+4irRgdKOqKVWu12IJGBF6ND+Mb33fs=; b=KRNFPmQXfxcaFa1coc4USFx9pp1JNnXY9d3w5DeWLZvqYje0+yJeg9FW1awcN3wKYx sLlna6FEHnXkgQXTndr35ikWHBbrRO4M/OlhFnjTba9oDXAVUGqetntP5uHbZbrS+6UH 0mNKZ+mncIQ5WBKJVcZ+LwchrOCqwcD62/fhzJcy8vOoLrUMQGqbH/zvCUVXCZhZHY2e fbRuDaR+I57g/GL7b8MX2HuYOTtVXG/KGVnl93Nd62WCma3cpJqt7SMuCdWWUq3QUDF2 NfupKaQrUTejgnjv09qWSmGP85J3iCe+kK61xLQeE1qZ84EuRVhIkNd1Ns825VEDCTRB vBqQ== X-Gm-Message-State: AOAM531XC/KMfOJLbFpSUE909uL/mBci3v6II5u5RAGbrEXM9JiKgIRa pAomFz8+wc/y2foXPR8Db2m9UeppFBs= X-Google-Smtp-Source: ABdhPJxYIw/qvvO3O2JOAKYBup7Fp378tFGnJbB6mqrew5n+HG+MMMbyz42p5+bVyP5zlgZbtYsqgg== X-Received: by 2002:a1c:7211:: with SMTP id n17mr3899005wmc.102.1612111455278; Sun, 31 Jan 2021 08:44:15 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id b13sm22561953wrt.31.2021.01.31.08.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] hw/arm: Use Kconfig 'default y' syntax instead of default-configs Date: Sun, 31 Jan 2021 17:44:02 +0100 Message-Id: <20210131164406.349825-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:19 -0000 Machines can be automatically selected using the Kconfig 'default y' syntax. This change allow deselecting these machines without having to modify default-configs/ files. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/aarch64-softmmu.mak | 3 --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/Kconfig | 4 ++++ 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak index a4202f56817..a94c7786919 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -2,6 +2,3 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak - -CONFIG_XLNX_VERSAL=y -CONFIG_SBSA_REF=y diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0fc80d7d6df..7d55c156bab 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -3,14 +3,12 @@ # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n -CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y CONFIG_NPCM7XX=y -CONFIG_RASPI=y CONFIG_SABRELITE=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 768830cc28c..043710be3df 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + default y if ARM imply PCI_DEVICES imply TEST_DEVICES imply VFIO_AMD_XGBE @@ -224,6 +225,7 @@ config REALVIEW config SBSA_REF bool + default y if AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 @@ -341,6 +343,7 @@ config ALLWINNER_H3 config RASPI bool + default y if ARM select FRAMEBUFFER select PL011 # UART select SDHCI @@ -382,6 +385,7 @@ config XLNX_ZYNQMP_ARM config XLNX_VERSAL bool + default y if AARCH64 select ARM_GIC select PL011 select CADENCE -- 2.26.2 From MAILER-DAEMON Sun Jan 31 11:44:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fpq-0008OV-3o for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:44:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Fpo-0008KI-4g; Sun, 31 Jan 2021 11:44:24 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:44239) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Fpm-0001Vp-Et; Sun, 31 Jan 2021 11:44:23 -0500 Received: by mail-wr1-x436.google.com with SMTP id d16so13985392wro.11; Sun, 31 Jan 2021 08:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ti3pGdZyEpwOiFw7/yoi3CPSUbET3rJXN1FI6GYYqTs=; b=WJZAC5oI/+0J1i4hjINE/PpdCPxgSq7PhS84z14HABHVkvXxR3dyxfxgnhG9k1VCic JOXkt/OvHylX/FFFtyd0WuN8m2gH+o0oaaqYP+TsUAXmujpFrnRf9V7KMKf2I7GE+tHD b5v3QIuxJEGs3lGQq7J1Vio0QlDrLgbr3foiv8c3KRrrZtJS80I22PhO6Qp1fJ3UmmQx fJEn4LithI/Mgz5y7kjyVQmvgaYk8yuCBOI2WjcjjLBpMryHfONwBK2auaZG1l3XkvtM 7sKPUJIYiRwuMkE+jGwI8cTwamVxs6EGugcyKEMgHb++Lz4l7VTxW50VCyd8MvLVZfqh MGig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Ti3pGdZyEpwOiFw7/yoi3CPSUbET3rJXN1FI6GYYqTs=; b=dj5IEltChSfF6bIB4vBwKEttYs5S1hRqXlldd/dhI1+99QB3fQK7EB21fAGlfk6W9Q wv2NocfbjOtqHXvWUxIzJqXSmuZlZ2vfAxtMmtvNuHLIJe5hSfnJAiZSjO7lVw5kTuX/ dIolVtUfqPe5tFUB8rPLaEC1ppkPj1SYYah/5YiClaZPvsMWqSLGafKr/HJRpFXmTBSM 0YU1DolTIJgPQFrQYdTWsos1auqWcR/4WFiiZC1WS1YZ0w3wGR7NsaeRH7p6a1hYdgcg JUUcLdm4ltvUV5dPPIwt/9wddMmbddrIURP3bUkJPFylHKhhh9H3x/FdqkPy7o93VzrJ sYfg== X-Gm-Message-State: AOAM532EWBUBR7FFKdRskIirog4W7lI8ySi3AYWGAYBsMwVevKNmsnJ/ QL8b6yoHNjCg+RSarYcdTqV/6sZpBzM= X-Google-Smtp-Source: ABdhPJyiPKUqMKiYoPKOERdZKupUQY1NbrLiW0EKYwuuOeb8WmWIw8PZQzp6KCcCGrvM0TsBOD28YQ== X-Received: by 2002:a05:6000:104:: with SMTP id o4mr14080822wrx.419.1612111460654; Sun, 31 Jan 2021 08:44:20 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id m184sm19779832wmf.12.2021.01.31.08.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/5] hw/arm: Restrict ARMv7 A-profile cpus to TCG accel Date: Sun, 31 Jan 2021 17:44:03 +0100 Message-Id: <20210131164406.349825-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:24 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). The following machines are no more built when TCG is disabled: - cubieboard cubietech cubieboard (Cortex-A8) - mcimx6ul-evk Freescale i.MX6UL Evaluation Kit (Cortex A7) - mcimx7d-sabre Freescale i.MX7 DUAL SABRE (Cortex A7) - npcm750-evb Nuvoton NPCM750 Evaluation Board (Cortex A9) - nuri Samsung NURI board (Exynos4210) - orangepi-pc Orange Pi PC (Cortex-A7) - quanta-gsj Quanta GSJ (Cortex A9) - realview-pb-a8 ARM RealView Platform Baseboard for Cortex-A8 - realview-pbx-a9 ARM RealView Platform Baseboard Explore for Cortex-A9 - sabrelite Freescale i.MX6 Quad SABRE Lite Board (Cortex A9) - smdkc210 Samsung SMDKC210 board (Exynos4210) - vexpress-a15 ARM Versatile Express for Cortex-A15 - vexpress-a9 ARM Versatile Express for Cortex-A9 - xilinx-zynq-a9 Xilinx Zynq Platform Baseboard for Cortex-A9 Reported-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 10 ---------- hw/arm/Kconfig | 11 +++++++++++ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 7d55c156bab..1ffa3dbe4bf 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -3,13 +3,3 @@ # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n -CONFIG_CUBIEBOARD=y -CONFIG_EXYNOS4=y -CONFIG_REALVIEW=y -CONFIG_VEXPRESS=y -CONFIG_ZYNQ=y -CONFIG_NPCM7XX=y -CONFIG_SABRELITE=y -CONFIG_FSL_IMX7=y -CONFIG_FSL_IMX6UL=y -CONFIG_ALLWINNER_H3=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 043710be3df..263f22a80c1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -39,6 +39,7 @@ config CHEETAH config CUBIEBOARD bool + default y if TCG && ARM select ALLWINNER_A10 config DIGIC @@ -50,6 +51,7 @@ config DIGIC config EXYNOS4 bool + default y if TCG && ARM select A9MPCORE select I2C select LAN9118 @@ -198,6 +200,7 @@ config Z2 config REALVIEW bool + default y if TCG && ARM imply PCI_DEVICES imply PCI_TESTDEV select SMC91C111 @@ -241,6 +244,7 @@ config SBSA_REF config SABRELITE bool + default y if TCG && ARM select FSL_IMX6 select SSI_M25P80 @@ -292,6 +296,7 @@ config VERSATILE config VEXPRESS bool + default y if TCG && ARM select A9MPCORE select A15MPCORE select ARM_MPTIMER @@ -307,6 +312,7 @@ config VEXPRESS config ZYNQ bool + default y if TCG && ARM select A9MPCORE select CADENCE # UART select PFLASH_CFI02 @@ -331,6 +337,7 @@ config ALLWINNER_A10 config ALLWINNER_H3 bool + default y if TCG && ARM select ALLWINNER_A10_PIT select ALLWINNER_SUN8I_EMAC select SERIAL @@ -395,6 +402,7 @@ config XLNX_VERSAL config NPCM7XX bool + default y if TCG && ARM select A9MPCORE select ARM_GIC select PL310 # cache controller @@ -424,6 +432,7 @@ config FSL_IMX31 config FSL_IMX6 bool + default y if TCG && ARM select A9MPCORE select IMX select IMX_FEC @@ -467,6 +476,7 @@ config MPS2 config FSL_IMX7 bool + default y if TCG && ARM imply PCI_DEVICES imply TEST_DEVICES select A15MPCORE @@ -484,6 +494,7 @@ config ARM_SMMUV3 config FSL_IMX6UL bool + default y if TCG && ARM select A15MPCORE select IMX select IMX_FEC -- 2.26.2 From MAILER-DAEMON Sun Jan 31 11:44:33 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fpx-0008TQ-0a for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id v126sm19002105wma.22.2021.01.31.08.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/5] target/arm: Restrict v8M IDAU to TCG Date: Sun, 31 Jan 2021 17:44:04 +0100 Message-Id: <20210131164406.349825-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:30 -0000 IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 7 ------- target/arm/cpu_tcg.c | 8 ++++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141e..d0853fae5ae 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2352,12 +2352,6 @@ static const TypeInfo arm_cpu_type_info = { .class_init = arm_cpu_class_init, }; -static const TypeInfo idau_interface_type_info = { - .name = TYPE_IDAU_INTERFACE, - .parent = TYPE_INTERFACE, - .class_size = sizeof(IDAUInterfaceClass), -}; - static void arm_cpu_register_types(void) { const size_t cpu_count = ARRAY_SIZE(arm_cpus); @@ -2371,7 +2365,6 @@ static void arm_cpu_register_types(void) if (cpu_count) { size_t i; - type_register_static(&idau_interface_type_info); for (i = 0; i < cpu_count; ++i) { arm_cpu_register(&arm_cpus[i]); } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3e1c9b40353..bddfbf5e3a9 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "target/arm/idau.h" /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -719,10 +720,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, }; +static const TypeInfo idau_interface_type_info = { + .name = TYPE_IDAU_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(IDAUInterfaceClass), +}; + static void arm_tcg_cpu_register_types(void) { size_t i; + type_register_static(&idau_interface_type_info); for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } -- 2.26.2 From MAILER-DAEMON Sun Jan 31 11:44:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fq7-000077-5k for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:44:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Fpz-0008Vj-Rj; Sun, 31 Jan 2021 11:44:35 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:34257) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Fpy-0001Ym-9k; Sun, 31 Jan 2021 11:44:35 -0500 Received: by mail-wm1-x331.google.com with SMTP id o10so9975605wmc.1; Sun, 31 Jan 2021 08:44:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P3RGtYOfTPa/4QX/PpSq+3Pw4Nd81ZJXrAdtTbdsm7Q=; b=A/dTHcDqqwc/tv3bQIAUAgwkqkP9ogdiVYTHvGv4iS35a2bxwgVuewcC+imA8Fy/Dm 9z8r+8Dz2f4j2yM5Zjwu7RZFN9ZeJlnWYz+El1ZewH64ly3EXRycrTgWz5utguWbI3mP f63oCoK/vERG7govyVTx2HOnU19BwZgdqHP3uDAIO+SKM9bWxBYaLsuvq+ZAA0cFYjHd owSiGCbvLHh86Ik9nixpSBy3859VTpWySRlnKU6AJz47ETY6a9riCJxSMbDvFccJjdOE v0Jn+pon3g2pbVh7IOiSWTYVuMokX3myMIN+wwIvYvgAmkbMxtGS0MAwfUsVAMlDlC01 e7EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=P3RGtYOfTPa/4QX/PpSq+3Pw4Nd81ZJXrAdtTbdsm7Q=; b=OgqhXRS2TjXIDQBQNzTXMRAYGvTx9o0eNDW5lUfM7gweu29RIcUbbqmaMAEZfOxWZS tBGbwvokvamrMbOu1ZV9UHQaQywUiUcXYEj1sfv2iszHi7AIoYWSUuTqZREo+6u6n6Rx IJ1Nc4ZPIbg51ApgJ4wNWSsy/fabjz1C94vSdNY2xLDaPTNWWzMkWA3cj2pHSIZFI+Qz q1bYYJL9iqqTmCG/YDPzFsy+HbgXWj0Gcc7SNq9p6x4tuqqZrLaBQZQAwDxejwy766fE 4qSbeJhTu5VeU4ov6h+fKpDW/lLcbTaQadMJFOZq0++SSuceGYZAWnjE+xN+xjdWzCL/ ffyQ== X-Gm-Message-State: AOAM533P9vPrKYPtf54phqdMnnHZOJ+n1+y6Z79a+qOLq8rJGmf4j2MV pJmcmbfaQPNVL5WwJ70iSFXMP5iBX10= X-Google-Smtp-Source: ABdhPJyBJV9qNbR5DPTz0HUp0DyXl1ZIzB9xoOCs3LTwCfRoVPiZP6SqvsQYCveB1TIND08YEA7Xkg== X-Received: by 2002:a1c:9e4d:: with SMTP id h74mr7608936wme.103.1612111471488; Sun, 31 Jan 2021 08:44:31 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id d3sm26664724wrp.79.2021.01.31.08.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/5] target/arm/cpu: Update coding style to make checkpatch.pl happy Date: Sun, 31 Jan 2021 17:44:05 +0100 Message-Id: <20210131164406.349825-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:39 -0000 We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d0853fae5ae..2d8312267f7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1956,7 +1956,8 @@ static void cortex_a8_initfn(Object *obj) } static const ARMCPRegInfo cortexa9_cp_reginfo[] = { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -1993,7 +1994,8 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -2030,7 +2032,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { MachineState *ms = MACHINE(qdev_get_machine()); - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((ms->smp.cpus - 1) << 24) | (1 << 23); @@ -2077,7 +2080,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_mmfr1 = 0x40000000; cpu->isar.id_mmfr2 = 0x01240000; cpu->isar.id_mmfr3 = 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 = 0x02101110; -- 2.26.2 From MAILER-DAEMON Sun Jan 31 11:44:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Fq8-0000B0-D7 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 11:44:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Fq7-000073-3Z; Sun, 31 Jan 2021 11:44:43 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44234) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Fq3-0001Zv-Kt; Sun, 31 Jan 2021 11:44:42 -0500 Received: by mail-wr1-x42f.google.com with SMTP id d16so13985904wro.11; Sun, 31 Jan 2021 08:44:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HAQsUmSJv4RsQU5o8at7OdfU6YsAfj1cwMNlNa7h8w0=; b=vO8GS+iB+KSqO9O7llYrgD3yQDaBw0NTqXO/AIDpoQlTFvU5BdFxQ5Xmi9Yq7DHU5M XVaYjGfP1kOkKpI84MNDF6ii8nD0AMFUAO/zswYYuzRm8a0wOw20L+tw/jl1c/t4ZXoS aP+g3laMj14w0FAtzJwXz2dWuTMbBp1a8yLZ9uDUfscUOuJkDijwLG2wXx81E7uGbwEN 3Z68lQeaXlALlBXfbL0XXuMoPY3acbqrHrL74iAPrv96KhShA2FIdQgLLlnQ8ByQ3KTf KFORs1RtxZq1ebUQ4png+sGXuF/A4e0lSzp4mNZaIcTpg9i4nbP5TzmeieMVL18isJMU Gy5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HAQsUmSJv4RsQU5o8at7OdfU6YsAfj1cwMNlNa7h8w0=; b=dR8DbJnnlD/zA82WW0KNM4NhVccg0QpZVwieNt/VqCuOQzNCss7s+4ypQL53VC1gmS SVI6KIjelXRw2De8+ixeHWoSNkUkp9vd8usLFEWnREeKzu3+SAUl1pFT5OKtUHXrhaUq /UijQdkaemhzmaepiP9zXgiE4Y79VaVrwre4Psk/jGkbTkz4HNbW/wbtPKQbyS6YeoZq o/PbOnktYT3GWly2q2WoIErTiI2A5k3J4YTston1pbXkB2D6qrIA5A8JISh6ReClTw8s wivrvTnyHUvntvZRwUp4nrHwNDVeAtTI2mqT7Hq7YfNhwuhlFgl/KrEs8ivHTB0ybqpf lXPQ== X-Gm-Message-State: AOAM530D5F9Cflk54bhPQsce/1LW4p4D6U6xr3MiMRWuWqJbmlDbMJPl HnJqOX5H5g83Oj/yA3/OX+g1rB073Yw= X-Google-Smtp-Source: ABdhPJwY9NgrzsoxviLa/LENSWrK/Wolx0RxjKY6AcjLe2BJb/XGu6d/umDr0/dSrPadU+FvU4iaSw== X-Received: by 2002:a5d:4391:: with SMTP id i17mr14233857wrq.57.1612111477032; Sun, 31 Jan 2021 08:44:37 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id e16sm23643904wrp.24.2021.01.31.08.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 08:44:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/5] target/arm: Restrict v7A TCG cpus to TCG accel Date: Sun, 31 Jan 2021 17:44:06 +0100 Message-Id: <20210131164406.349825-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131164406.349825-1-f4bug@amsat.org> References: <20210131164406.349825-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 16:44:43 -0000 KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). A KVM-only build won't be able to run TCG cpus, move the v7A CPU definitions to cpu_tcg.c. Reported-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 327 ------------------------------------------- target/arm/cpu_tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 310 insertions(+), 327 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2d8312267f7..3f10614778b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1906,323 +1906,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) return oc; } -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - -static const ARMCPRegInfo cortexa8_cp_reginfo[] = { - { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a8_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,cortex-a8"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr = 0x410fc080; - cpu->reset_fpsid = 0x410330c0; - cpu->isar.mvfr0 = 0x11110222; - cpu->isar.mvfr1 = 0x00011111; - cpu->ctr = 0x82048004; - cpu->reset_sctlr = 0x00c50078; - cpu->isar.id_pfr0 = 0x1031; - cpu->isar.id_pfr1 = 0x11; - cpu->isar.id_dfr0 = 0x400; - cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x31100003; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01202000; - cpu->isar.id_mmfr3 = 0x11; - cpu->isar.id_isar0 = 0x00101111; - cpu->isar.id_isar1 = 0x12112111; - cpu->isar.id_isar2 = 0x21232031; - cpu->isar.id_isar3 = 0x11112131; - cpu->isar.id_isar4 = 0x00111142; - cpu->isar.dbgdidr = 0x15141000; - cpu->clidr = (1 << 27) | (2 << 24) | 3; - cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ - cpu->reset_auxcr = 2; - define_arm_cp_regs(cpu, cortexa8_cp_reginfo); -} - -static const ARMCPRegInfo cortexa9_cp_reginfo[] = { - /* - * power_control should be set to maximum latency. Again, - * default to 0 and set by private hook - */ - { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, - { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, - { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, - { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, - /* TLB lockdown control */ - { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, - .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, - { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, - .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, - { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, - { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, - { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, - REGINFO_SENTINEL -}; - -static void cortex_a9_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,cortex-a9"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_EL3); - /* - * Note that A9 supports the MP extensions even for - * A9UP and single-core A9MP (which are both different - * and valid configurations; we don't model A9UP). - */ - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_CBAR); - cpu->midr = 0x410fc090; - cpu->reset_fpsid = 0x41033090; - cpu->isar.mvfr0 = 0x11110222; - cpu->isar.mvfr1 = 0x01111111; - cpu->ctr = 0x80038003; - cpu->reset_sctlr = 0x00c50078; - cpu->isar.id_pfr0 = 0x1031; - cpu->isar.id_pfr1 = 0x11; - cpu->isar.id_dfr0 = 0x000; - cpu->id_afr0 = 0; - cpu->isar.id_mmfr0 = 0x00100103; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01230000; - cpu->isar.id_mmfr3 = 0x00002111; - cpu->isar.id_isar0 = 0x00101111; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232041; - cpu->isar.id_isar3 = 0x11112131; - cpu->isar.id_isar4 = 0x00111142; - cpu->isar.dbgdidr = 0x35141000; - cpu->clidr = (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); -} - -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms = MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] = { -#ifndef CONFIG_USER_ONLY - { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, - .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, - .writefn = arm_cp_write_ignore, }, -#endif - { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a7_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,cortex-a7"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; - cpu->midr = 0x410fc075; - cpu->reset_fpsid = 0x41023075; - cpu->isar.mvfr0 = 0x10110222; - cpu->isar.mvfr1 = 0x11111111; - cpu->ctr = 0x84448003; - cpu->reset_sctlr = 0x00c50078; - cpu->isar.id_pfr0 = 0x00001131; - cpu->isar.id_pfr1 = 0x00011011; - cpu->isar.id_dfr0 = 0x02010555; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10101105; - cpu->isar.id_mmfr1 = 0x40000000; - cpu->isar.id_mmfr2 = 0x01240000; - cpu->isar.id_mmfr3 = 0x02102211; - /* - * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but - * table 4-41 gives 0x02101110, which includes the arm div insns. - */ - cpu->isar.id_isar0 = 0x02101110; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232041; - cpu->isar.id_isar3 = 0x11112131; - cpu->isar.id_isar4 = 0x10011142; - cpu->isar.dbgdidr = 0x3515f005; - cpu->clidr = 0x0a200023; - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ -} - -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cpu->dtb_compatible = "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr = 0x412fc0f1; - cpu->reset_fpsid = 0x410430f0; - cpu->isar.mvfr0 = 0x10110222; - cpu->isar.mvfr1 = 0x11111111; - cpu->ctr = 0x8444c004; - cpu->reset_sctlr = 0x00c50078; - cpu->isar.id_pfr0 = 0x00001131; - cpu->isar.id_pfr1 = 0x00011011; - cpu->isar.id_dfr0 = 0x02010555; - cpu->id_afr0 = 0x00000000; - cpu->isar.id_mmfr0 = 0x10201105; - cpu->isar.id_mmfr1 = 0x20000000; - cpu->isar.id_mmfr2 = 0x01240000; - cpu->isar.id_mmfr3 = 0x02102211; - cpu->isar.id_isar0 = 0x02101110; - cpu->isar.id_isar1 = 0x13112111; - cpu->isar.id_isar2 = 0x21232041; - cpu->isar.id_isar3 = 0x11112131; - cpu->isar.id_isar4 = 0x10011142; - cpu->isar.dbgdidr = 0x3515f021; - cpu->clidr = 0x0a200023; - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - -#ifndef TARGET_AARCH64 -/* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; - * this only needs to handle 32 bits, and need not care about KVM. - */ -static void arm_max_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - cortex_a15_initfn(obj); - - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t = cpu->isar.id_isar5; - t = FIELD_DP32(t, ID_ISAR5, AES, 2); - t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t = FIELD_DP32(t, ID_ISAR5, RDM, 1); - t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 = t; - - t = cpu->isar.id_isar6; - t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t = FIELD_DP32(t, ID_ISAR6, DP, 1); - t = FIELD_DP32(t, ID_ISAR6, FHM, 1); - t = FIELD_DP32(t, ID_ISAR6, SB, 1); - t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - cpu->isar.id_isar6 = t; - - t = cpu->isar.mvfr1; - t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 = t; - - t = cpu->isar.mvfr2; - t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 = t; - - t = cpu->isar.id_mmfr3; - t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 = t; - - t = cpu->isar.id_mmfr4; - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 = t; - } -#endif -} -#endif - -#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ - -static const ARMCPUInfo arm_cpus[] = { -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name = "cortex-a7", .initfn = cortex_a7_initfn }, - { .name = "cortex-a8", .initfn = cortex_a8_initfn }, - { .name = "cortex-a9", .initfn = cortex_a9_initfn }, - { .name = "cortex-a15", .initfn = cortex_a15_initfn }, -#ifndef TARGET_AARCH64 - { .name = "max", .initfn = arm_max_initfn }, -#endif -#ifdef CONFIG_USER_ONLY - { .name = "any", .initfn = arm_max_initfn }, -#endif -#endif -}; - static Property arm_cpu_properties[] = { DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), @@ -2358,21 +2041,11 @@ static const TypeInfo arm_cpu_type_info = { static void arm_cpu_register_types(void) { - const size_t cpu_count = ARRAY_SIZE(arm_cpus); - type_register_static(&arm_cpu_type_info); #ifdef CONFIG_KVM type_register_static(&host_arm_cpu_type_info); #endif - - if (cpu_count) { - size_t i; - - for (i = 0; i < cpu_count; ++i) { - arm_cpu_register(&arm_cpus[i]); - } - } } type_init(arm_cpu_register_types) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bddfbf5e3a9..1572620fba9 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -12,6 +12,9 @@ #include "cpu.h" #include "internals.h" #include "target/arm/idau.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/boards.h" +#endif /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -252,6 +255,236 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr = 1; } +static const ARMCPRegInfo cortexa8_cp_reginfo[] = { + { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a8_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a8"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr = 0x410fc080; + cpu->reset_fpsid = 0x410330c0; + cpu->isar.mvfr0 = 0x11110222; + cpu->isar.mvfr1 = 0x00011111; + cpu->ctr = 0x82048004; + cpu->reset_sctlr = 0x00c50078; + cpu->isar.id_pfr0 = 0x1031; + cpu->isar.id_pfr1 = 0x11; + cpu->isar.id_dfr0 = 0x400; + cpu->id_afr0 = 0; + cpu->isar.id_mmfr0 = 0x31100003; + cpu->isar.id_mmfr1 = 0x20000000; + cpu->isar.id_mmfr2 = 0x01202000; + cpu->isar.id_mmfr3 = 0x11; + cpu->isar.id_isar0 = 0x00101111; + cpu->isar.id_isar1 = 0x12112111; + cpu->isar.id_isar2 = 0x21232031; + cpu->isar.id_isar3 = 0x11112131; + cpu->isar.id_isar4 = 0x00111142; + cpu->isar.dbgdidr = 0x15141000; + cpu->clidr = (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ + cpu->reset_auxcr = 2; + define_arm_cp_regs(cpu, cortexa8_cp_reginfo); +} + +static const ARMCPRegInfo cortexa9_cp_reginfo[] = { + /* + * power_control should be set to maximum latency. Again, + * default to 0 and set by private hook + */ + { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, + { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, + { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, + { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, + /* TLB lockdown control */ + { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, + .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, + { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, + .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, + { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, + { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, + { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, + REGINFO_SENTINEL +}; + +static void cortex_a9_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a9"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); + /* + * Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); + cpu->midr = 0x410fc090; + cpu->reset_fpsid = 0x41033090; + cpu->isar.mvfr0 = 0x11110222; + cpu->isar.mvfr1 = 0x01111111; + cpu->ctr = 0x80038003; + cpu->reset_sctlr = 0x00c50078; + cpu->isar.id_pfr0 = 0x1031; + cpu->isar.id_pfr1 = 0x11; + cpu->isar.id_dfr0 = 0x000; + cpu->id_afr0 = 0; + cpu->isar.id_mmfr0 = 0x00100103; + cpu->isar.id_mmfr1 = 0x20000000; + cpu->isar.id_mmfr2 = 0x01230000; + cpu->isar.id_mmfr3 = 0x00002111; + cpu->isar.id_isar0 = 0x00101111; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232041; + cpu->isar.id_isar3 = 0x11112131; + cpu->isar.id_isar4 = 0x00111142; + cpu->isar.dbgdidr = 0x35141000; + cpu->clidr = (1 << 27) | (1 << 24) | 3; + cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); +} + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +static const ARMCPRegInfo cortexa15_cp_reginfo[] = { +#ifndef CONFIG_USER_ONLY + { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, + .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, + .writefn = arm_cp_write_ignore, }, +#endif + { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a7_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a7"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; + cpu->midr = 0x410fc075; + cpu->reset_fpsid = 0x41023075; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x11111111; + cpu->ctr = 0x84448003; + cpu->reset_sctlr = 0x00c50078; + cpu->isar.id_pfr0 = 0x00001131; + cpu->isar.id_pfr1 = 0x00011011; + cpu->isar.id_dfr0 = 0x02010555; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x10101105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01240000; + cpu->isar.id_mmfr3 = 0x02102211; + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232041; + cpu->isar.id_isar3 = 0x11112131; + cpu->isar.id_isar4 = 0x10011142; + cpu->isar.dbgdidr = 0x3515f005; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ +} + +static void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr = 0x412fc0f1; + cpu->reset_fpsid = 0x410430f0; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x11111111; + cpu->ctr = 0x8444c004; + cpu->reset_sctlr = 0x00c50078; + cpu->isar.id_pfr0 = 0x00001131; + cpu->isar.id_pfr1 = 0x00011011; + cpu->isar.id_dfr0 = 0x02010555; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x20000000; + cpu->isar.id_mmfr2 = 0x01240000; + cpu->isar.id_mmfr3 = 0x02102211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232041; + cpu->isar.id_isar3 = 0x11112131; + cpu->isar.id_isar4 = 0x10011142; + cpu->isar.dbgdidr = 0x3515f021; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -675,6 +908,73 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) cc->gdb_core_xml_file = "arm-m-profile.xml"; } +#ifndef TARGET_AARCH64 +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits, and need not care about KVM. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + +#ifdef CONFIG_USER_ONLY + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t = cpu->isar.id_isar5; + t = FIELD_DP32(t, ID_ISAR5, AES, 2); + t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t = FIELD_DP32(t, ID_ISAR5, RDM, 1); + t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 = t; + + t = cpu->isar.id_isar6; + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t = FIELD_DP32(t, ID_ISAR6, DP, 1); + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); + t = FIELD_DP32(t, ID_ISAR6, SB, 1); + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 = t; + + t = cpu->isar.mvfr1; + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 = t; + + t = cpu->isar.mvfr2; + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 = t; + + t = cpu->isar.id_mmfr3; + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 = t; + + t = cpu->isar.id_mmfr4; + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 = t; + } +#endif +} +#endif + static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "arm926", .initfn = arm926_initfn }, { .name = "arm946", .initfn = arm946_initfn }, @@ -688,6 +988,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "arm1136", .initfn = arm1136_initfn }, { .name = "arm1176", .initfn = arm1176_initfn }, { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, + { .name = "cortex-a7", .initfn = cortex_a7_initfn }, + { .name = "cortex-a8", .initfn = cortex_a8_initfn }, + { .name = "cortex-a9", .initfn = cortex_a9_initfn }, + { .name = "cortex-a15", .initfn = cortex_a15_initfn }, { .name = "cortex-m0", .initfn = cortex_m0_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, @@ -718,6 +1022,12 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name = "max", .initfn = arm_max_initfn }, +#endif +#ifdef CONFIG_USER_ONLY + { .name = "any", .initfn = arm_max_initfn }, +#endif }; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id i18sm15848918wrn.29.2021.01.31.10.33.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Jan 2021 10:33:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Subject: Re: [PATCH 2/5] hw/arm: Restrict ARMv7 A-profile cpus to TCG accel To: qemu-devel@nongnu.org Cc: Peter Maydell , Thomas Huth , qemu-arm@nongnu.org, Richard Henderson References: <20210131164406.349825-1-f4bug@amsat.org> <20210131164406.349825-3-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <53c946a7-e79a-6a45-d342-6104efc166b3@amsat.org> Date: Sun, 31 Jan 2021 19:33:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210131164406.349825-3-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:33:38 -0000 On 1/31/21 5:44 PM, Philippe Mathieu-Daudé wrote: > KVM requires the target cpu to be at least ARMv8 architecture > (support on ARMv7 has been dropped in commit 82bf7ae84ce: > "target/arm: Remove KVM support for 32-bit Arm hosts"). > > The following machines are no more built when TCG is disabled: > > - cubieboard cubietech cubieboard (Cortex-A8) > - mcimx6ul-evk Freescale i.MX6UL Evaluation Kit (Cortex A7) > - mcimx7d-sabre Freescale i.MX7 DUAL SABRE (Cortex A7) > - npcm750-evb Nuvoton NPCM750 Evaluation Board (Cortex A9) > - nuri Samsung NURI board (Exynos4210) > - orangepi-pc Orange Pi PC (Cortex-A7) > - quanta-gsj Quanta GSJ (Cortex A9) > - realview-pb-a8 ARM RealView Platform Baseboard for Cortex-A8 > - realview-pbx-a9 ARM RealView Platform Baseboard Explore for Cortex-A9 > - sabrelite Freescale i.MX6 Quad SABRE Lite Board (Cortex A9) > - smdkc210 Samsung SMDKC210 board (Exynos4210) > - vexpress-a15 ARM Versatile Express for Cortex-A15 > - vexpress-a9 ARM Versatile Express for Cortex-A9 > - xilinx-zynq-a9 Xilinx Zynq Platform Baseboard for Cortex-A9 > > Reported-by: Peter Maydell > Signed-off-by: Philippe Mathieu-Daudé > --- > default-configs/devices/arm-softmmu.mak | 10 ---------- > hw/arm/Kconfig | 11 +++++++++++ > 2 files changed, 11 insertions(+), 10 deletions(-) ... > > config REALVIEW > bool > + default y if TCG && ARM > imply PCI_DEVICES > imply PCI_TESTDEV > select SMC91C111 > @@ -241,6 +244,7 @@ config SBSA_REF > > config SABRELITE > bool > + default y if TCG && ARM > select FSL_IMX6 > select SSI_M25P80 > > @@ -292,6 +296,7 @@ config VERSATILE > > config VEXPRESS > bool > + default y if TCG && ARM > select A9MPCORE > select A15MPCORE > select ARM_MPTIMER > @@ -307,6 +312,7 @@ config VEXPRESS > > config ZYNQ > bool > + default y if TCG && ARM > select A9MPCORE > select CADENCE # UART > select PFLASH_CFI02 Missing: -- >8 -- diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index cb0409c5a11..c1746284ee2 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -225,10 +225,11 @@ int main(int argc, char **argv) #ifdef CONFIG_TCG "realview-eb", "realview-eb-mpcore", -#endif /* CONFIG_TCG */ "realview-pb-a8", "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15", - "vexpress-a9", "virt", NULL + "vexpress-a9", +#endif /* CONFIG_TCG */ + "virt", NULL }; add_cdrom_param_tests(armmachines); } else { diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c83bc211b6a..d8ebd5bf98e 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -159,10 +159,10 @@ (cpu != 'arm' ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') ? ['xlnx-can-test'] : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'xlnx-can-test', 'migration-test'] qtests_s390x = \ --- From MAILER-DAEMON Sun Jan 31 13:44:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HiU-0001j6-Ij for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:44:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6HiS-0001hT-74; Sun, 31 Jan 2021 13:44:56 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:50949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6HiQ-0007Te-NH; Sun, 31 Jan 2021 13:44:55 -0500 Received: by mail-wm1-x336.google.com with SMTP id 190so10801011wmz.0; Sun, 31 Jan 2021 10:44:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=uooJJLyBqSH0JLXgEvaOK715zFIDOmfUz5/9bBdSXd0=; b=QqkEqhsOTKjkj7hY1wmRpIvOUmd7yCC4n3U4eQW3IazSe4PwpIiDAjaosvX8cwD6TQ EjMWdRM7BAnB2eaKBwKBa2fk/Fi6wz4DWXcMyv/cE4R3PYvZaDaRYPkPF1VrNALguIv0 ctKumlFkv4f802ZsaVWwSOMW6ccXIQevBBlRexmoi7LJEkuNvMG32uoNPixwTxtP6olQ Fe8aJuZ7SaoBOQMMl7jh7KcX4rb3mTe5B+b3ggH7MKcl2V/orwXxGi19KIz+Dvax+DWR iYNVXzBT8Fyri40exuLdFW753HuXImdCNzoG3/zFF2jqzaE2yxlnlUjfO/sAurxtnydw F7Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=uooJJLyBqSH0JLXgEvaOK715zFIDOmfUz5/9bBdSXd0=; b=n3JgxDvddrRNaZIYNqJVRePxf+PQOX9KBhbo2BLLxJd3SBovfSgxLr0ip/kmqwQCOk /MIzEdtppmHfGy3WgXq80rwSdNrhLwSLN1MfyYLieWqO2fQBiuOgcBkK5FYExpT8mg5/ B0awCvepivFFK9mClFu6vU6J0tvJR6Ic1qHvK4d7zyI1/SVXcc42oMON4wpA8fWamab/ RajknstSyjGxcV8+5RWMBtigfT46DqYF9pHiZSNP1uPBi/PjhteCImSojyaqn0AxPNAv KvmFX8CUavl1dIf3FSdH++eP2Bt1YABdY0Hss4j1rLzRuwaFyYLcDEnlZOYgGF5xNApD /e8A== X-Gm-Message-State: AOAM532K0YOWIBIxg+ulXhapgssYjBVaMpY41PrfxfQPMeE4+tZJ4I+J m7Lrstsol634W0mtMt1K3LrB5cZ08yg= X-Google-Smtp-Source: ABdhPJx52LK3EuWyH747I2iWnc9vIO23uTSULOhBKWVeWp5hn66cQGus1RPK+lFfkNQzuzHsposfiQ== X-Received: by 2002:a1c:f70c:: with SMTP id v12mr11762822wmh.77.1612118692428; Sun, 31 Jan 2021 10:44:52 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id b4sm24051410wrn.12.2021.01.31.10.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:44:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 0/6] hw/arm: Misc trivial fixes/cleanups Date: Sun, 31 Jan 2021 19:44:43 +0100 Message-Id: <20210131184449.382425-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:44:56 -0000 Trivial bugfixes and cleanup patches noticed while rebasing=0D my "Support disabling TCG on ARM (part 2)" series.=0D =0D Since v2:=0D - removed incorrect patches added in v2 =3D)=0D - more fixes for Versal board (CAN, RTC)=0D =0D Since v1:=0D - added patches to remove 64-bit specific features on 32-bit build.=0D =0D Philippe Mathieu-Daud=C3=A9 (6):=0D hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ=0D hw/arm/exynos4210: Add missing dependency on OR_IRQ=0D hw/arm/xlnx-versal: Versal SoC requires ZDMA=0D hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals=0D hw/net/can: ZynqMP CAN device requires PTIMER=0D hw/arm: Display CPU type in machine description=0D =0D hw/arm/digic_boards.c | 2 +-=0D hw/arm/microbit.c | 2 +-=0D hw/arm/netduino2.c | 2 +-=0D hw/arm/netduinoplus2.c | 2 +-=0D hw/arm/orangepi.c | 2 +-=0D hw/arm/stellaris.c | 4 ++--=0D hw/Kconfig | 1 +=0D hw/arm/Kconfig | 5 +++++=0D hw/dma/Kconfig | 3 +++=0D hw/dma/meson.build | 2 +-=0D 10 files changed, 17 insertions(+), 8 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D From MAILER-DAEMON Sun Jan 31 13:45:03 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HiZ-0001t7-9q for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:45:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6HiX-0001pv-LE; Sun, 31 Jan 2021 13:45:01 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:52985) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6HiW-0007W5-7W; Sun, 31 Jan 2021 13:45:01 -0500 Received: by mail-wm1-x32d.google.com with SMTP id o5so1145135wmq.2; Sun, 31 Jan 2021 10:44:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=Ar83hyG1wfqk990LmyX56lvWVmRRWSUEpVqyMnuuaaHJmSx9fQuhZTQWz5jZAwbPmj wp3f+NM1Dlntqul213WvJHoGbrHt/JOBCaIwLwd8mMwZqkk/a1WSyVB5yOyhQFj+ucf/ VoYH1Lq32TXiBWgiYVXVg4QrCqnGScz9PlJr1izmus4bIu3abO/LdTnzgyReyZVhtGXL 5XVCirWVxwIE7Vkpc5U+OmR/A4JO68UGLAkC0MCOFdIn9ESnH8jitD0Yz/Wu+eKyGuOm n6VosZs4M5Xa8LFs848I0PZUknvG1ILFBOKmmvfdVuhoV1XFpeGvPKKsXdroZHS/feR3 7wMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KjWr4TKlwB/IJcVo6npcfvEPrPb22EOYTZC5O8IwCfc=; b=k24sDsUaksK01Yo3Mv6hOBuJIGm+m4Af433SRdyOBCVw/6MzR0M99jEv9YQnqK1OZr fscWY9TVU1zONlNUqHDLkLGpb7S7X7hZxIU6wxzyB9OP1yk62kiWoRDDmmy2oIFT+YQQ 7OsDsfLAthn9b7o6peYkxObpyOAs3i2NLsthoA+uXFxj6fROYQYKHtj8iu0ZlX12lFov YBOYig3/IiOEyXxybzm/ZSpQfDRVWzKcfSVzf4JYiDxdp72l7Pzqe7dB41hnhzk+YFIb 32XIpDTOPBAfZigeDrr2UvNtPpPzvLfwBvYBKpLrZlbsNfIP/Zar7oRLYI1m4jQBwdaD R/4A== X-Gm-Message-State: AOAM531P6Qf66iQuUzuL1wznTV2DYlXFXoF2VtregBTBMRKm+a8J6sEv 7mTuup8yrYwW2rJxn4TxLzxVH1LsJgM= X-Google-Smtp-Source: ABdhPJyYvINpxyBLy+SG1ryCF0bcAlkAQlIphE5zpao88S66RKUpceyH9ZeaGvOesvSS8l5ovJ9sPA== X-Received: by 2002:a05:600c:268b:: with SMTP id 11mr12117657wmt.132.1612118697963; Sun, 31 Jan 2021 10:44:57 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id v4sm27450035wrw.42.2021.01.31.10.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:44:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 1/6] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Date: Sun, 31 Jan 2021 19:44:44 +0100 Message-Id: <20210131184449.382425-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:02 -0000 The STM32F405 SoC uses an OR gate on its ADC IRQs. Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC") Signed-off-by: Philippe Mathieu-Daudé --- Cc: alistair@alistair23.me --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 13cc42dcc84..a320a124855 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -336,6 +336,7 @@ config STM32F205_SOC config STM32F405_SOC bool select ARM_V7M + select OR_IRQ select STM32F4XX_SYSCFG select STM32F4XX_EXTI -- 2.26.2 From MAILER-DAEMON Sun Jan 31 13:45:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HjH-00024u-FK for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:45:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55238) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Hii-0001yE-2e; Sun, 31 Jan 2021 13:45:16 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:33308) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Hib-0007Zm-Fb; Sun, 31 Jan 2021 13:45:06 -0500 Received: by mail-wm1-x32a.google.com with SMTP id s24so10111919wmj.0; Sun, 31 Jan 2021 10:45:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jtbqU34AXRgK7JucvFyMPpEvpdP/cEkbkCwJzoZsw+I=; b=VF6E2NXWtD3zEAXLxVC2hK7Xfw+t82rTxtn7y+LFa8QYc9gEzoBxDBPmHaYwec7x8o LrYX6BHL7XdNGODXIuOz5zEAc43+hPzBqi1DYvi+ByFyTxuAy01gwxyAp31Nu5ldicRj RKw+hdSgZaG5yPmS29wZB12XDVPxkbmtCOabb01srH22WqD0/jLx9SLPKtGrUBnJebBL XTjnIJlZTQtQlNDGI9DDWEvhvS7Bf3fdiQaKJ6XMb6OXqk2bwTTFAjcfT5iUqwQ/m3Ce qlyiBBx8MKKQX2VIQBNMDHSiy+i0QxGImWgz4fg12CDwDec430LcEU9xVyeJJym2PF9g aNBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jtbqU34AXRgK7JucvFyMPpEvpdP/cEkbkCwJzoZsw+I=; b=p77M+lYcHnuuwyUv6cC+qpxvtGAKCPzqo+F/zSQYfiNcoE5I3xcKwZCjA05Vmj7DYB aGusMUiY+Lgh7xQD8kegkC9zntUVVUkelByCyumtzmdLcUzXrFA+ZAaXEB0kRUwMy6sV gROVDcGiN9BQ0+34SgKVlqsau1Gm8CkDwBNDbWLGyB3D+Zx2bIXNyUUF17ogVcbWW2WE qylGhQrioK7v9hKA3oL1BCd5zupyYuPZIUZJOM3tzJcmESTGXNuHuXIonpZa3mQojhqo rrHps1yaqJKdJ08Vy9lDtuM4iTd5pAfm3MiWIxNWHTTwk/oF0nNn253d5ja88FQ2rDmw 4KaQ== X-Gm-Message-State: AOAM531FJWTYHRe7E6FlNy1kkiof1PRpHTnO6WVr5WtY+zQYzla9bsf0 CQ+JlENNkWvR94X1MTU73JK/2bKNj64= X-Google-Smtp-Source: ABdhPJxU15vx8xnGdlqkUvGg8ERV48eMOGbdkiBcOqh01PjQ4ZH0IIbRq2SQ/8gv7gXCXsbocm8sgA== X-Received: by 2002:a05:600c:3545:: with SMTP id i5mr6404850wmq.134.1612118703233; Sun, 31 Jan 2021 10:45:03 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id p12sm3807281wmq.1.2021.01.31.10.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:45:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mitsyanko Subject: [PATCH v3 2/6] hw/arm/exynos4210: Add missing dependency on OR_IRQ Date: Sun, 31 Jan 2021 19:44:45 +0100 Message-Id: <20210131184449.382425-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:23 -0000 The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines. Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization") Signed-off-by: Philippe Mathieu-Daudé --- Cc: Igor Mitsyanko --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a320a124855..223016bb4e8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -52,6 +52,7 @@ config EXYNOS4 select PTIMER select SDHCI select USB_EHCI_SYSBUS + select OR_IRQ config HIGHBANK bool -- 2.26.2 From MAILER-DAEMON Sun Jan 31 13:45:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HjJ-00025g-A0 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:45:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Him-0001yT-6y; Sun, 31 Jan 2021 13:45:22 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:40645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Hii-0007ay-CJ; Sun, 31 Jan 2021 13:45:14 -0500 Received: by mail-wm1-x330.google.com with SMTP id c127so11307023wmf.5; Sun, 31 Jan 2021 10:45:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rhmZGh+lLqk8y/kN/amckU6sgJUtIz3ObCH4gQGYjHc=; b=KktWREIcOO5ckerD0vQCUtP4hMxuWXaLfxmQON2F4aRCM4glautuQG9RCoLYyI2M6h V5StizOVibqs6xX8hjhe6EaeR18syvb1pzBY4HniKeGb8haWPCQx0/qunzKBe2uvvrFD JS00J8PUevkFld4jV7mYwH/iRNTKVHzEOWWmeWoR7bmRoXuVHGWOHP5gw5hRaEjtLVIZ CoTvhGT9JNhDgl8qttOjgAcdmAEnNQuzjakEop2W6CZ/OLm7OUttK7PfRgOhmQOi7omc /RRwEEarVBBOqddOibrEpxgGZpQfQqrdinkeRt+RGl42Pn6cSUy/dn1LOp6anFDowVe1 3c3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rhmZGh+lLqk8y/kN/amckU6sgJUtIz3ObCH4gQGYjHc=; b=XHJZb92cdGVpO+IxrgLPePbTU5aflUvqc4pKYx0xZsMHDx5w1CoyG6WeoFupOvNNIF GLEvryYUwHnFcIPulRw11dHyynndNd2+vdfyjiXlBXIwegQNDfk59yAlWuJM8GnWBjbt AdQ1mD58n6XLjFCP5dItW8n1GZoXvch6oIuC+ZyfRt5bvyTTpqg/LRXVKPRZ1MXr/gNo noPCb9M1zb5MDP+7hX0J3pLkN/2WyrHCWD2+6xL+oizJOxpjDRUN4hKoXd2WaXVwkYT4 a0l6KT9YjQszGonffMm/dR9pNpPnBLFuGjgDtsgN04aDdqjNDJ9D8/qyBRvH1UJffe66 55kQ== X-Gm-Message-State: AOAM532ewHyJ4ZvtWYVPWhJi7U7Omz0XFMXF2qv19X7EpkIjNlNnQhxV kNsf/1+KjCQ5dSwXUKsvsXv1Rs3uYkM= X-Google-Smtp-Source: ABdhPJy2U3symi2Ebr1QVVCT1n7huoL+wZ6CzrXYlmU6uoecugntaCtgbRamJdWwc+4aZQcmR36yvw== X-Received: by 2002:a7b:c09a:: with SMTP id r26mr12176695wmh.64.1612118708340; Sun, 31 Jan 2021 10:45:08 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id r17sm9680432wro.46.2021.01.31.10.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:45:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v3 3/6] hw/arm/xlnx-versal: Versal SoC requires ZDMA Date: Sun, 31 Jan 2021 19:44:46 +0100 Message-Id: <20210131184449.382425-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:31 -0000 The Versal SoC instantiates the TYPE_XLNX_ZDMA object in versal_create_admas(). Introduce the XLNX_ZDMA configuration and select it to fix: $ qemu-system-aarch64 -M xlnx-versal-virt ... qemu-system-aarch64: missing object type 'xlnx.zdma' Signed-off-by: Philippe Mathieu-Daudé --- Cc: Alistair Francis Cc: "Edgar E. Iglesias" --- hw/arm/Kconfig | 2 ++ hw/dma/Kconfig | 3 +++ hw/dma/meson.build | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 223016bb4e8..09298881f2f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -354,6 +354,7 @@ config XLNX_ZYNQMP_ARM select XILINX_AXI select XILINX_SPIPS select XLNX_ZYNQMP + select XLNX_ZDMA config XLNX_VERSAL bool @@ -362,6 +363,7 @@ config XLNX_VERSAL select CADENCE select VIRTIO_MMIO select UNIMP + select XLNX_ZDMA config NPCM7XX bool diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index d67492d36c1..5d6be1a7a7a 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -18,6 +18,9 @@ config ZYNQ_DEVCFG bool select REGISTER +config XLNX_ZDMA + bool + config STP2000 bool diff --git a/hw/dma/meson.build b/hw/dma/meson.build index b991d7698c7..47b4a7cb47b 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -9,7 +9,7 @@ softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_dma.c')) softmmu_ss.add(when: 'CONFIG_STP2000', if_true: files('sparc32_dma.c')) softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dpdma.c')) -softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZDMA', if_true: files('xlnx-zdma.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) -- 2.26.2 From MAILER-DAEMON Sun Jan 31 13:45:57 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HjO-00026M-Or for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:45:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Hin-0001yc-Vw; Sun, 31 Jan 2021 13:45:22 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:39522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Him-0007c5-Lv; Sun, 31 Jan 2021 13:45:17 -0500 Received: by mail-wm1-x32a.google.com with SMTP id u14so11322068wmq.4; Sun, 31 Jan 2021 10:45:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dNCf/fnSg4i/RlVqvC4tpeAa/bGn7I/5i5RyvqlkfeM=; b=fm19mkj0jseLfnTszAPO7p6gj1tm7wIOqL2VuFSCAIXWsbmSABwfpdKaz1VQ7gGPCk bjlBOwASltuCQ971kuwmkacU5564b9IXM5DqZJdil7kFc2Vmuvfsi6L1rab8ZWhpYpCo c0GHQtk9OXdVI9sd9gZKb2MblWu6psSPGfZ9c+M9sRMOcLIe6KX+/751+j+KvKO61pEw knfG+Hl1uH4wWoBJDhq4bThOxBRssJ0VuQ7PIybgAoxKPg98r+wadKZg1GfQ6vAKKlRc 2Lc8BPAiH9MN9SZAGp7dJRTBgZP/Ja0680mOdGM/THHmeHu+TRqJPz7ayCpv/SzVrf/B hJwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dNCf/fnSg4i/RlVqvC4tpeAa/bGn7I/5i5RyvqlkfeM=; b=C8GCurOFdp9TX8jAQZhNLWhYghGgN51fzUAKDVUhj6jr/Urq3R6P4a1JLpb/uQZEri J/0VC1VcjxNW74ZpdEaupY9P4sQnabZly47NNQNJPY0GaFHzmu8oQFE0jtck6FWNnE/f Xr7TEk/pCqJ3Y1CJ5kAVaK1u1xwgcICDmf7feIy2rdfWe2bGulB30vmtXJFwwgb7457d H3q1lbrxI1Hxzf2oHj4cm9chMSVSlz3QtrAV79vEGKE3IHBBQFB3IE09+LmbXqoxlWF9 Pdl5t7hCYPHuwcO6hOkjMNzQi6zHXWtCr/CUKZEpHZ3WSxY7DCBihEjxM4wvMzT5szCN OODw== X-Gm-Message-State: AOAM532Kb5v3Jxx5eDBn2gbOjK/v8LU34ZpYtcM8LYYGZiGusird6OQh LBIaB741Pi8BS1X8mWLODggh2OSOgKk= X-Google-Smtp-Source: ABdhPJxvohrFT03xquIXL3mgZHbueGWaf183+KT7lJtfXbBT3NpbMWwjJQhNLgDJR/6Dh98B8OuJ+w== X-Received: by 2002:a1c:65d5:: with SMTP id z204mr6641246wmb.184.1612118713233; Sun, 31 Jan 2021 10:45:13 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id b18sm23653374wrm.57.2021.01.31.10.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:45:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E. Iglesias" Subject: [PATCH v3 4/6] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals Date: Sun, 31 Jan 2021 19:44:47 +0100 Message-Id: <20210131184449.382425-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:31 -0000 The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix: $ make check-qtest-aarch64 ... Running test qtest-aarch64/qom-test qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc' Broken pipe Signed-off-by: Philippe Mathieu-Daudé --- Cc: Alistair Francis Cc: "Edgar E. Iglesias" --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 09298881f2f..be017b997ab 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -364,6 +364,7 @@ config XLNX_VERSAL select VIRTIO_MMIO select UNIMP select XLNX_ZDMA + select XLNX_ZYNQMP config NPCM7XX bool -- 2.26.2 From MAILER-DAEMON Sun Jan 31 13:45:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HjR-000272-68 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 13:45:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Hj0-00021k-60; Sun, 31 Jan 2021 13:45:31 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:36433) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l6Hiw-0007fb-8Y; Sun, 31 Jan 2021 13:45:29 -0500 Received: by mail-wm1-x32e.google.com with SMTP id i9so11346153wmq.1; Sun, 31 Jan 2021 10:45:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=Xex9yBlF2YBcUJZkVQebz+LHHVE0PmtFKcD4mns2pqWsWtmf+WRdiGPDWVf4zj8u8V blPpNzVMbbh7TYy5sdVI9nfnPpa2QzMKq8r2rCm9qSD6AoscmPIkXiFreAOZnRk/2sie 1KjRrq+dfFFhFtcmwkrdhyxmk2svUeUrVPhD9eTEyBuPAqU0iQVQonwyeYH1E6P6v/wt kxij9zFc+z941w7GR6W2oYBYrhSYWQiOOW0/+1slbi+GyiVkD7nIWC8oAgbfhBuiHdh5 8r6+ebCXr7kFQr2A6NIDL9F0etJUN3P83WA+ghAu6Ie9IRygrBPan8fVHn16P9e61QUU ZuIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZTEQksi03h84QrtUmTk444gEe+iL7OPLaC2gCq3Rbc4=; b=IxTkO/zqt0ittEDoSFaUhKs8F9+wTZp8Nh91/t6B521elmk4Jc8N5PKlUr77VjBSNz iD9Y55MIbWgOqm1fd+cQMWMYcmviNIlEKAwM1xhHVVz7KHzlxV7TMppBZUPU6uzizhPX PXz56fW+NLJVt78NAAGV2o3rldW0MARYP9Pk9fZdPZW9d9GWn+0M/MyRaYDvQNWq5RLp lrm3CXUXhmeQeM50qlIwDAWyEF2bevBzoFdMTcD8yRxKdtLiLWX29rfnLKMSTwqXObgU EbC2ZA7JQw7RCIMui52OS9pPmaiSRGKI0/WPU6rbIaxNEDr/QmQh/0+L5jiKNYJMxlX6 T92Q== X-Gm-Message-State: AOAM532QuEWGTjw9cLz2YlSonolXqbuXYT1rJm0kP/Dfa5J6E41p7wjk yNT+QtUcmPOXreJz/o4Sml6OtIZwRvA= X-Google-Smtp-Source: ABdhPJytmgX7NpBiYVAEOpecQTzLjVd7W9PQaVd3V+gt2o4Yoj3QRIztr6bT4LXUEIESEqZGnRXESQ== X-Received: by 2002:a1c:27c3:: with SMTP id n186mr12017398wmn.96.1612118723210; Sun, 31 Jan 2021 10:45:23 -0800 (PST) Received: from localhost.localdomain (7.red-83-57-171.dynamicip.rima-tde.net. [83.57.171.7]) by smtp.gmail.com with ESMTPSA id m16sm14368847wmq.36.2021.01.31.10.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:45:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 6/6] hw/arm: Display CPU type in machine description Date: Sun, 31 Jan 2021 19:44:49 +0100 Message-Id: <20210131184449.382425-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:44 -0000 Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/digic_boards.c | 2 +- hw/arm/microbit.c | 2 +- hw/arm/netduino2.c | 2 +- hw/arm/netduinoplus2.c | 2 +- hw/arm/orangepi.c | 2 +- hw/arm/stellaris.c | 4 ++-- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index be12873673b..6cdc1d83fca 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine) static void canon_a1100_machine_init(MachineClass *mc) { - mc->desc = "Canon PowerShot A1100 IS"; + mc->desc = "Canon PowerShot A1100 IS (ARM946)"; mc->init = &canon_a1100_init; mc->ignore_memory_transaction_failures = true; mc->default_ram_size = 64 * MiB; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 0947491cb97..e9494334ce7 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "BBC micro:bit"; + mc->desc = "BBC micro:bit (Cortex-M0)"; mc->init = microbit_init; mc->max_cpus = 1; } diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 8f103341443..1733b71507c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine) static void netduino2_machine_init(MachineClass *mc) { - mc->desc = "Netduino 2 Machine"; + mc->desc = "Netduino 2 Machine (Cortex-M3)"; mc->init = netduino2_init; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 68abd3ec69d..d3ad7a2b675 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine) static void netduinoplus2_machine_init(MachineClass *mc) { - mc->desc = "Netduino Plus 2 Machine"; + mc->desc = "Netduino Plus 2 Machine (Cortex-M4)"; mc->init = netduinoplus2_init; } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index d6306dfddae..40cdb5c6d2c 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine) static void orangepi_machine_init(MachineClass *mc) { - mc->desc = "Orange Pi PC"; + mc->desc = "Orange Pi PC (Cortex-A7)"; mc->init = orangepi_init; mc->block_default_type = IF_SD; mc->units_per_default_bus = 1; diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ad72c0959f1..27292ec4113 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S811EVB"; + mc->desc = "Stellaris LM3S811EVB (Cortex-M3)"; mc->init = lm3s811evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); @@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Stellaris LM3S6965EVB"; + mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)"; mc->init = lm3s6965evb_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); -- 2.26.2 From MAILER-DAEMON Sun Jan 31 13:46:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6HjW-0002DQ-8K for mharc-qemu-arm@gnu.org; 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[83.57.171.7]) by smtp.gmail.com with ESMTPSA id 17sm18042395wmk.48.2021.01.31.10.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 10:45:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Niek Linnenbank , Laurent Vivier , Antony Pavlov , Peter Maydell , Michael Tokarev , qemu-arm@nongnu.org, Joel Stanley , Alistair Francis , qemu-trivial@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 5/6] hw/net/can: ZynqMP CAN device requires PTIMER Date: Sun, 31 Jan 2021 19:44:48 +0100 Message-Id: <20210131184449.382425-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131184449.382425-1-f4bug@amsat.org> References: <20210131184449.382425-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 18:45:31 -0000 Add a dependency XLNX_ZYNQMP -> PTIMER to fix: /usr/bin/ld: libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function `xlnx_zynqmp_can_realize': hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init' hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to `ptimer_transaction_begin' hw/net/can/xlnx-zynqmp-can.c:1087: undefined reference to `ptimer_set_freq' hw/net/can/xlnx-zynqmp-can.c:1088: undefined reference to `ptimer_set_limit' hw/net/can/xlnx-zynqmp-can.c:1089: undefined reference to `ptimer_run' hw/net/can/xlnx-zynqmp-can.c:1090: undefined reference to `ptimer_transaction_commit' libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o:(.data.rel+0x2c8): undefined reference to `vmstate_ptimer' Signed-off-by: Philippe Mathieu-Daudé --- hw/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/Kconfig b/hw/Kconfig index 5ad3c6b5a4b..d4cec9e476c 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -81,3 +81,4 @@ config XLNX_ZYNQMP bool select REGISTER select CAN_BUS + select PTIMER -- 2.26.2 From MAILER-DAEMON Sun Jan 31 16:53:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Kej-0005UF-Oa for mharc-qemu-arm@gnu.org; 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boundary="0000000000008a00b405ba39431a" Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=nieklinnenbank@gmail.com; helo=mail-io1-xd33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 Jan 2021 21:53:17 -0000 --0000000000008a00b405ba39431a Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable For Orange Pi PC: Reviewed-by: Niek Linnenbank Op zo 31 jan. 2021 19:45 schreef Philippe Mathieu-Daud=C3=A9 : > Most of ARM machines display their CPU when QEMU list the available > machines (-M help). Some machines do not. Fix to unify the help > output. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/arm/digic_boards.c | 2 +- > hw/arm/microbit.c | 2 +- > hw/arm/netduino2.c | 2 +- > hw/arm/netduinoplus2.c | 2 +- > hw/arm/orangepi.c | 2 +- > hw/arm/stellaris.c | 4 ++-- > 6 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c > index be12873673b..6cdc1d83fca 100644 > --- a/hw/arm/digic_boards.c > +++ b/hw/arm/digic_boards.c > @@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine) > > static void canon_a1100_machine_init(MachineClass *mc) > { > - mc->desc =3D "Canon PowerShot A1100 IS"; > + mc->desc =3D "Canon PowerShot A1100 IS (ARM946)"; > mc->init =3D &canon_a1100_init; > mc->ignore_memory_transaction_failures =3D true; > mc->default_ram_size =3D 64 * MiB; > diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c > index 0947491cb97..e9494334ce7 100644 > --- a/hw/arm/microbit.c > +++ b/hw/arm/microbit.c > @@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc= , > void *data) > { > MachineClass *mc =3D MACHINE_CLASS(oc); > > - mc->desc =3D "BBC micro:bit"; > + mc->desc =3D "BBC micro:bit (Cortex-M0)"; > mc->init =3D microbit_init; > mc->max_cpus =3D 1; > } > diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c > index 8f103341443..1733b71507c 100644 > --- a/hw/arm/netduino2.c > +++ b/hw/arm/netduino2.c > @@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine) > > static void netduino2_machine_init(MachineClass *mc) > { > - mc->desc =3D "Netduino 2 Machine"; > + mc->desc =3D "Netduino 2 Machine (Cortex-M3)"; > mc->init =3D netduino2_init; > mc->ignore_memory_transaction_failures =3D true; > } > diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c > index 68abd3ec69d..d3ad7a2b675 100644 > --- a/hw/arm/netduinoplus2.c > +++ b/hw/arm/netduinoplus2.c > @@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine) > > static void netduinoplus2_machine_init(MachineClass *mc) > { > - mc->desc =3D "Netduino Plus 2 Machine"; > + mc->desc =3D "Netduino Plus 2 Machine (Cortex-M4)"; > mc->init =3D netduinoplus2_init; > } > > diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c > index d6306dfddae..40cdb5c6d2c 100644 > --- a/hw/arm/orangepi.c > +++ b/hw/arm/orangepi.c > @@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine) > > static void orangepi_machine_init(MachineClass *mc) > { > - mc->desc =3D "Orange Pi PC"; > + mc->desc =3D "Orange Pi PC (Cortex-A7)"; > mc->init =3D orangepi_init; > mc->block_default_type =3D IF_SD; > mc->units_per_default_bus =3D 1; > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index ad72c0959f1..27292ec4113 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, > void *data) > { > MachineClass *mc =3D MACHINE_CLASS(oc); > > - mc->desc =3D "Stellaris LM3S811EVB"; > + mc->desc =3D "Stellaris LM3S811EVB (Cortex-M3)"; > mc->init =3D lm3s811evb_init; > mc->ignore_memory_transaction_failures =3D true; > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); > @@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, > void *data) > { > MachineClass *mc =3D MACHINE_CLASS(oc); > > - mc->desc =3D "Stellaris LM3S6965EVB"; > + mc->desc =3D "Stellaris LM3S6965EVB (Cortex-M3)"; > mc->init =3D lm3s6965evb_init; > mc->ignore_memory_transaction_failures =3D true; > mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); > -- > 2.26.2 > > --0000000000008a00b405ba39431a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
For Orange Pi PC:

= Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>

Op zo 31 jan. 2021 19:45 schr= eef Philippe Mathieu-Daud=C3=A9 <f4bu= g@amsat.org>:
Most of ARM ma= chines display their CPU when QEMU list the available
machines (-M help). Some machines do not. Fix to unify the help
output.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0hw/arm/digic_boards.c=C2=A0 | 2 +-
=C2=A0hw/arm/microbit.c=C2=A0 =C2=A0 =C2=A0 | 2 +-
=C2=A0hw/arm/netduino2.c=C2=A0 =C2=A0 =C2=A0| 2 +-
=C2=A0hw/arm/netduinoplus2.c | 2 +-
=C2=A0hw/arm/orangepi.c=C2=A0 =C2=A0 =C2=A0 | 2 +-
=C2=A0hw/arm/stellaris.c=C2=A0 =C2=A0 =C2=A0| 4 ++--
=C2=A06 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index be12873673b..6cdc1d83fca 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine)

=C2=A0static void canon_a1100_machine_init(MachineClass *mc)
=C2=A0{
-=C2=A0 =C2=A0 mc->desc =3D "Canon PowerShot A1100 IS";
+=C2=A0 =C2=A0 mc->desc =3D "Canon PowerShot A1100 IS (ARM946)"= ;;
=C2=A0 =C2=A0 =C2=A0mc->init =3D &canon_a1100_init;
=C2=A0 =C2=A0 =C2=A0mc->ignore_memory_transaction_failures =3D true;
=C2=A0 =C2=A0 =C2=A0mc->default_ram_size =3D 64 * MiB;
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 0947491cb97..e9494334ce7 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc, = void *data)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0MachineClass *mc =3D MACHINE_CLASS(oc);

-=C2=A0 =C2=A0 mc->desc =3D "BBC micro:bit";
+=C2=A0 =C2=A0 mc->desc =3D "BBC micro:bit (Cortex-M0)";
=C2=A0 =C2=A0 =C2=A0mc->init =3D microbit_init;
=C2=A0 =C2=A0 =C2=A0mc->max_cpus =3D 1;
=C2=A0}
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 8f103341443..1733b71507c 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine)

=C2=A0static void netduino2_machine_init(MachineClass *mc)
=C2=A0{
-=C2=A0 =C2=A0 mc->desc =3D "Netduino 2 Machine";
+=C2=A0 =C2=A0 mc->desc =3D "Netduino 2 Machine (Cortex-M3)";<= br> =C2=A0 =C2=A0 =C2=A0mc->init =3D netduino2_init;
=C2=A0 =C2=A0 =C2=A0mc->ignore_memory_transaction_failures =3D true;
=C2=A0}
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 68abd3ec69d..d3ad7a2b675 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine)

=C2=A0static void netduinoplus2_machine_init(MachineClass *mc)
=C2=A0{
-=C2=A0 =C2=A0 mc->desc =3D "Netduino Plus 2 Machine";
+=C2=A0 =C2=A0 mc->desc =3D "Netduino Plus 2 Machine (Cortex-M4)&qu= ot;;
=C2=A0 =C2=A0 =C2=A0mc->init =3D netduinoplus2_init;
=C2=A0}

diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d6306dfddae..40cdb5c6d2c 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine)

=C2=A0static void orangepi_machine_init(MachineClass *mc)
=C2=A0{
-=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC";
+=C2=A0 =C2=A0 mc->desc =3D "Orange Pi PC (Cortex-A7)";
=C2=A0 =C2=A0 =C2=A0mc->init =3D orangepi_init;
=C2=A0 =C2=A0 =C2=A0mc->block_default_type =3D IF_SD;
=C2=A0 =C2=A0 =C2=A0mc->units_per_default_bus =3D 1;
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index ad72c0959f1..27292ec4113 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, vo= id *data)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0MachineClass *mc =3D MACHINE_CLASS(oc);

-=C2=A0 =C2=A0 mc->desc =3D "Stellaris LM3S811EVB";
+=C2=A0 =C2=A0 mc->desc =3D "Stellaris LM3S811EVB (Cortex-M3)"= ;
=C2=A0 =C2=A0 =C2=A0mc->init =3D lm3s811evb_init;
=C2=A0 =C2=A0 =C2=A0mc->ignore_memory_transaction_failures =3D true;
=C2=A0 =C2=A0 =C2=A0mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cor= tex-m3");
@@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, v= oid *data)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0MachineClass *mc =3D MACHINE_CLASS(oc);

-=C2=A0 =C2=A0 mc->desc =3D "Stellaris LM3S6965EVB";
+=C2=A0 =C2=A0 mc->desc =3D "Stellaris LM3S6965EVB (Cortex-M3)"= ;;
=C2=A0 =C2=A0 =C2=A0mc->init =3D lm3s6965evb_init;
=C2=A0 =C2=A0 =C2=A0mc->ignore_memory_transaction_failures =3D true;
=C2=A0 =C2=A0 =C2=A0mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cor= tex-m3");
--
2.26.2

--0000000000008a00b405ba39431a-- From MAILER-DAEMON Sun Jan 31 22:12:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1l6Pdn-0003Vf-81 for mharc-qemu-arm@gnu.org; Sun, 31 Jan 2021 22:12:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Pdm-0003VO-6M; Sun, 31 Jan 2021 22:12:38 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:2604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Pdi-0007tw-AT; Sun, 31 Jan 2021 22:12:37 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DTXys5L03zjFs6; Mon, 1 Feb 2021 11:11:17 +0800 (CST) Received: from [10.174.184.214] (10.174.184.214) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Mon, 1 Feb 2021 11:12:12 +0800 Subject: Re: [RFC PATCH v2 3/3] vfio: Avoid disabling and enabling vectors repeatedly in VFIO migration To: Alex Williamson CC: Kirti Wankhede , Cornelia Huck , "Dr . David Alan Gilbert" , Eric Auger , , Marcel Apfelbaum , , , Neo Jia , Marc Zyngier , Lorenzo Pieralisi , , References: <20201209080919.156-1-lushenming@huawei.com> <20201209080919.156-4-lushenming@huawei.com> <20210126143614.175e271c@omen.home.shazbot.org> <7e61e7ae-e351-4228-d250-660251dcb0c0@huawei.com> <20210127072131.1c778247@x1.home.shazbot.org> From: Shenming Lu Message-ID: <2fc2db52-0677-c92e-f3c3-10fe9a77d75c@huawei.com> Date: Mon, 1 Feb 2021 11:12:12 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: <20210127072131.1c778247@x1.home.shazbot.org> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.184.214] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.32; envelope-from=lushenming@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.079, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Feb 2021 03:12:38 -0000 On 2021/1/27 22:21, Alex Williamson wrote: > On Wed, 27 Jan 2021 19:27:35 +0800 > Shenming Lu wrote: > >> On 2021/1/27 5:36, Alex Williamson wrote: >>> On Wed, 9 Dec 2020 16:09:19 +0800 >>> Shenming Lu wrote: >>> >>>> Different from the normal situation when the guest starts, we can >>>> know the max unmasked vetctor (at the beginning) after msix_load() >>>> in VFIO migration. So in order to avoid ineffectively disabling and >>> >>> s/ineffectively/inefficiently/? It's "effective" either way I think. >> >> Yeah, I should say "inefficiently". :-) >> >>> >>>> enabling vectors repeatedly, let's allocate all needed vectors first >>>> and then enable these unmasked vectors one by one without disabling. >>>> >>>> Signed-off-by: Shenming Lu >>>> --- >>>> hw/pci/msix.c | 17 +++++++++++++++++ >>>> hw/vfio/pci.c | 10 ++++++++-- >>>> include/hw/pci/msix.h | 2 ++ >>>> 3 files changed, 27 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/hw/pci/msix.c b/hw/pci/msix.c >>>> index 67e34f34d6..bf291d3ff8 100644 >>>> --- a/hw/pci/msix.c >>>> +++ b/hw/pci/msix.c >>>> @@ -557,6 +557,23 @@ unsigned int msix_nr_vectors_allocated(const PCIDevice *dev) >>>> return dev->msix_entries_nr; >>>> } >>>> >>>> +int msix_get_max_unmasked_vector(PCIDevice *dev) >>>> +{ >>>> + int max_unmasked_vector = -1; >>>> + int vector; >>>> + >>>> + if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & >>>> + (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) { >>>> + for (vector = 0; vector < dev->msix_entries_nr; vector++) { >>>> + if (!msix_is_masked(dev, vector)) { >>>> + max_unmasked_vector = vector; >>>> + } >>>> + } >>>> + } >>>> + >>>> + return max_unmasked_vector; >>>> +} >>> >>> Comments from QEMU PCI folks? >>> >>>> + >>>> static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector) >>>> { >>>> MSIMessage msg; >>>> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c >>>> index 51dc373695..e755ed2514 100644 >>>> --- a/hw/vfio/pci.c >>>> +++ b/hw/vfio/pci.c >>>> @@ -568,6 +568,9 @@ static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) >>>> >>>> static void vfio_msix_enable(VFIOPCIDevice *vdev) >>>> { >>>> + int max_unmasked_vector = msix_get_max_unmasked_vector(&vdev->pdev); >>>> + unsigned int used_vector = MAX(max_unmasked_vector, 0); >>>> + >>> >>> The above PCI function could also be done inline here pretty easily too: >>> >>> unsigned int nr, max_vec = 0; >>> >>> if (!msix_masked(&vdev->pdev)) >>> for (nr = 0; nr < msix_nr_vectors_allocated(&vdev->pdev); nr++) { >>> if (!msix_is_masked(&vdev->pdev, nr)) { >>> max_vec = nr; >>> } >>> } >>> } >>> >>> It's a bit cleaner than the msix utility function, imo. >> >> Yeah, it makes sense. >> >>> >>>> vfio_disable_interrupts(vdev); >>>> >>>> vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); >>>> @@ -586,9 +589,12 @@ static void vfio_msix_enable(VFIOPCIDevice *vdev) >>>> * triggering to userspace, then immediately release the vector, leaving >>>> * the physical device with no vectors enabled, but MSI-X enabled, just >>>> * like the guest view. >>>> + * If there are unmasked vectors (such as in migration) which will be >>>> + * enabled soon, we can allocate them here to avoid ineffectively disabling >>>> + * and enabling vectors repeatedly later. >>> >>> It just happens that migration triggers this usage model where the >>> MSI-X enable bit is set with vectors unmasked in the vector table, but >>> this is not unique to migration, guests can follow this pattern as well. >>> Has this been tested with a variety of guests? Logically it seems >>> correct, but always good to prove so. Thanks, >> >> I have tested it in migration and normal guest startup (only the latest Linux). >> And I can try to test with some other kernels, could you be more specific about this? > > Minimally also Windows, ideally a BSD as well. Thanks, > Hi Alex, I have tested this patch with a Windows guest (Windows Server 2012 R2 Datacenter, Intel X722 Ethernet controller (passthrough)) and nothing went wrong. And I found that it does trigger our usage model in the normal guest startup: has all needed vectors already unmasked in the vector table when calling vfio_msix_enable()... Thanks, Shenming