From MAILER-DAEMON Fri Oct 01 05:28:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mWEpm-0002Iz-CI for mharc-qemu-commits@gnu.org; Fri, 01 Oct 2021 05:28:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34898) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWEpl-0002H4-G6 for qemu-commits@nongnu.org; Fri, 01 Oct 2021 05:28:01 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:39493) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWEph-00020U-Hl for qemu-commits@nongnu.org; Fri, 01 Oct 2021 05:28:00 -0400 Received: from github.com (hubbernetes-node-89caa29.ac4-iad.github.net [10.52.201.75]) by smtp.github.com (Postfix) with ESMTPA id A8BC660003E for ; Fri, 1 Oct 2021 02:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633080476; bh=3ELYKtON1DrujgoZC9vFxI8UL87lX/JR6nz2Rc2hTfY=; h=Date:From:To:Subject:From; b=dzgun1sMxlcoAXM0IEhP3VNX9R+AW19v1mns8McM4oJ49rUDCK5uqq3+FyMnzIKeu m0zftoXtedflZcwfJBotoqT/EWc8oCbID7bzewJePJAbLCz6oxxftEVKuMY2FoV9eS LBgYaszUoBhjrRb75BNf0vSr+1MtE+RST+3PKZXI= Date: Fri, 01 Oct 2021 02:27:56 -0700 From: Peter Maydell To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 01e75d: allwinner-h3: Switch to SMC as PSCI conduit X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Oct 2021 09:28:01 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 01e75d87834a5188f98defa2d1f88b69dca7e9a0=0D https://github.com/qemu/qemu/commit/01e75d87834a5188f98defa2d1f88b6= 9dca7e9a0=0D Author: Alexander Graf =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/arm/allwinner-h3.c=0D =0D Log Message:=0D -----------=0D allwinner-h3: Switch to SMC as PSCI conduit=0D =0D The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.=0D= However, today we are configuring QEMU to use HVC as PSCI conduit.=0D =0D That means HVC calls get trapped into QEMU instead of the guest's own=0D emulated CPU and thus break the guest's ability to execute virtualization= .=0D =0D Fix this by moving to SMC as conduit, freeing up HYP completely to the VM= .=0D =0D Signed-off-by: Alexander Graf =0D Message-id: 20210920203931.66527-1-agraf@csgraf.de=0D Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")=0D Reviewed-by: Niek Linnenbank =0D Tested-by: Niek Linnenbank =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 9fcd15b9193e819b6cc2fd0a45e3506148812bb4=0D https://github.com/qemu/qemu/commit/9fcd15b9193e819b6cc2fd0a45e3506= 148812bb4=0D Author: Alexander Graf =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M target/arm/psci.c=0D =0D Log Message:=0D -----------=0D arm: tcg: Adhere to SMCCC 1.3 section 5.2=0D =0D The SMCCC 1.3 spec section 5.2 says=0D =0D The Unknown SMC Function Identifier is a sign-extended value of (-1)=0D= that is returned in the R0, W0 or X0 registers. An implementation must=0D= return this error code when it receives:=0D =0D * An SMC or HVC call with an unknown Function Identifier=0D * An SMC or HVC call for a removed Function Identifier=0D * An SMC64/HVC64 call from AArch32 state=0D =0D To comply with these statements, let's always return -1 when we encounter= =0D an unknown HVC or SMC call.=0D =0D Signed-off-by: Alexander Graf =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 68fbcc344ef6fb2dff0eb4cac0319ea7af010a7f=0D https://github.com/qemu/qemu/commit/68fbcc344ef6fb2dff0eb4cac0319ea= 7af010a7f=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/nvram/Kconfig=0D M hw/nvram/meson.build=0D A hw/nvram/xlnx-efuse-crc.c=0D A hw/nvram/xlnx-efuse.c=0D A include/hw/nvram/xlnx-efuse.h=0D =0D Log Message:=0D -----------=0D hw/nvram: Introduce Xilinx eFuse QOM=0D =0D This introduces the QOM for Xilinx eFuse, an one-time=0D field-programmable storage bit array.=0D =0D The actual mmio interface to the array varies by device=0D families and will be provided in different change-sets.=0D =0D Co-authored-by: Edgar E. Iglesias =0D Co-authored-by: Sai Pavan Boddu =0D =0D Signed-off-by: Edgar E. Iglesias =0D Signed-off-by: Sai Pavan Boddu =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 9e4aa1fafef624ee4ae6006497bed0cc112135d3=0D https://github.com/qemu/qemu/commit/9e4aa1fafef624ee4ae6006497bed0c= c112135d3=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/nvram/Kconfig=0D M hw/nvram/meson.build=0D A hw/nvram/xlnx-versal-efuse-cache.c=0D A hw/nvram/xlnx-versal-efuse-ctrl.c=0D A include/hw/nvram/xlnx-versal-efuse.h=0D =0D Log Message:=0D -----------=0D hw/nvram: Introduce Xilinx Versal eFuse device=0D =0D This implements the Xilinx Versal eFuse, an one-time=0D field-programmable non-volatile storage device. There is=0D only one such device in the Xilinx Versal product family.=0D =0D This device has two separate mmio interfaces, a controller=0D and a flatten readback.=0D =0D The controller provides interfaces for field-programming,=0D configuration, control, and status.=0D =0D The flatten readback is a cache to provide a byte-accessible=0D read-only interface to efficiently read efuse array.=0D =0D Co-authored-by: Edgar E. Iglesias =0D Co-authored-by: Sai Pavan Boddu =0D =0D Signed-off-by: Edgar E. Iglesias =0D Signed-off-by: Sai Pavan Boddu =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 67fa02f89fbf7510b70080bbbea8ac0aa752e8ba=0D https://github.com/qemu/qemu/commit/67fa02f89fbf7510b70080bbbea8ac0= aa752e8ba=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/nvram/Kconfig=0D M hw/nvram/meson.build=0D A hw/nvram/xlnx-zynqmp-efuse.c=0D A include/hw/nvram/xlnx-zynqmp-efuse.h=0D =0D Log Message:=0D -----------=0D hw/nvram: Introduce Xilinx ZynqMP eFuse device=0D =0D This implements the Xilinx ZynqMP eFuse, an one-time=0D field-programmable non-volatile storage device. There is=0D only one such device in the Xilinx ZynqMP product family.=0D =0D Co-authored-by: Edgar E. Iglesias =0D Co-authored-by: Sai Pavan Boddu =0D =0D Signed-off-by: Edgar E. Iglesias =0D Signed-off-by: Sai Pavan Boddu =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 461a6a6f199944e466ddb808516e63cf064c0105=0D https://github.com/qemu/qemu/commit/461a6a6f199944e466ddb808516e63c= f064c0105=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/nvram/Kconfig=0D M hw/nvram/meson.build=0D A hw/nvram/xlnx-bbram.c=0D A include/hw/nvram/xlnx-bbram.h=0D =0D Log Message:=0D -----------=0D hw/nvram: Introduce Xilinx battery-backed ram=0D =0D This device is present in Versal and ZynqMP product=0D families to store a 256-bit encryption key.=0D =0D Co-authored-by: Edgar E. Iglesias =0D Co-authored-by: Sai Pavan Boddu =0D =0D Signed-off-by: Edgar E. Iglesias =0D Signed-off-by: Sai Pavan Boddu =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 393185bc9de599d82725c2a17d5db91d037745be=0D https://github.com/qemu/qemu/commit/393185bc9de599d82725c2a17d5db91= d037745be=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/arm/Kconfig=0D M hw/arm/xlnx-versal-virt.c=0D M hw/arm/xlnx-versal.c=0D M include/hw/arm/xlnx-versal.h=0D =0D Log Message:=0D -----------=0D hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device=0D =0D Connect the support for Versal Battery-Backed RAM (BBRAM)=0D =0D The command argument:=0D -drive if=3Dpflash,index=3D0,...=0D Can be used to optionally connect the bbram to a backend=0D storage, such that field-programmed values in one=0D invocation can be made available to next invocation.=0D =0D The backend storage must be a seekable binary file, and=0D its size must be 36 bytes or larger. A file with all=0D binary 0's is a 'blank'.=0D =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 5f4910ff12f88f9750608cbfe07895204405bed1=0D https://github.com/qemu/qemu/commit/5f4910ff12f88f9750608cbfe078952= 04405bed1=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/arm/Kconfig=0D M hw/arm/xlnx-versal-virt.c=0D M hw/arm/xlnx-versal.c=0D M include/hw/arm/xlnx-versal.h=0D =0D Log Message:=0D -----------=0D hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device=0D =0D Connect the support for Versal eFUSE one-time field-programmable=0D bit array.=0D =0D The command argument:=0D -drive if=3Dpflash,index=3D1,...=0D Can be used to optionally connect the bit array to a=0D backend storage, such that field-programmed values=0D in one invocation can be made available to next=0D invocation.=0D =0D The backend storage must be a seekable binary file, and=0D its size must be 3072 bytes or larger. A file with all=0D binary 0's is a 'blank'.=0D =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 7e47e15c8b47ac866e8f07998276b01e612a360a=0D https://github.com/qemu/qemu/commit/7e47e15c8b47ac866e8f07998276b01= e612a360a=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/Kconfig=0D M hw/arm/xlnx-zcu102.c=0D M hw/arm/xlnx-zynqmp.c=0D M include/hw/arm/xlnx-zynqmp.h=0D =0D Log Message:=0D -----------=0D hw/arm: xlnx-zcu102: Add Xilinx BBRAM device=0D =0D Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)=0D =0D The command argument:=0D -drive if=3Dpflash,index=3D2,...=0D Can be used to optionally connect the bbram to a backend=0D storage, such that field-programmed values in one=0D invocation can be made available to next invocation.=0D =0D The backend storage must be a seekable binary file, and=0D its size must be 36 bytes or larger. A file with all=0D binary 0's is a 'blank'.=0D =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: db1264df32d5482cb49ea5acbd6dcf2f466325c2=0D https://github.com/qemu/qemu/commit/db1264df32d5482cb49ea5acbd6dcf2= f466325c2=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/Kconfig=0D M hw/arm/xlnx-zcu102.c=0D M hw/arm/xlnx-zynqmp.c=0D M include/hw/arm/xlnx-zynqmp.h=0D =0D Log Message:=0D -----------=0D hw/arm: xlnx-zcu102: Add Xilinx eFUSE device=0D =0D Connect the support for ZynqMP eFUSE one-time field-programmable=0D bit array.=0D =0D The command argument:=0D -drive if=3Dpflash,index=3D3,...=0D Can be used to optionally connect the bit array to a=0D backend storage, such that field-programmed values=0D in one invocation can be made available to next=0D invocation.=0D =0D The backend storage must be a seekable binary file, and=0D its size must be 768 bytes or larger. A file with all=0D binary 0's is a 'blank'.=0D =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 09e010aedeb0a20aefa1fa0c06cf421e80f25edd=0D https://github.com/qemu/qemu/commit/09e010aedeb0a20aefa1fa0c06cf421= e80f25edd=0D Author: Tong Ho =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M docs/system/arm/xlnx-versal-virt.rst=0D =0D Log Message:=0D -----------=0D docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage=0D =0D Add BBRAM and eFUSE usage to the Xilinx Versal Virt board=0D document.=0D =0D Signed-off-by: Tong Ho =0D Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: 0e2a76110465ec95fd9f2c4820f186ca8106ab49=0D https://github.com/qemu/qemu/commit/0e2a76110465ec95fd9f2c4820f186c= a8106ab49=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M configs/targets/aarch64-linux-user.mak=0D M configs/targets/aarch64_be-linux-user.mak=0D =0D Log Message:=0D -----------=0D configs: Don't include 32-bit-only GDB XML in aarch64 linux configs=0D =0D The aarch64-linux QEMU usermode binaries can never run 32-bit=0D code, so they do not need to include the GDB XML for it.=0D (arm_cpu_register_gdb_regs_for_features() will not use these=0D XML files if the CPU has ARM_FEATURE_AARCH64, so we will not=0D advertise to gdb that we have them.)=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Richard Henderson =0D Message-id: 20210921162901.17508-2-peter.maydell@linaro.org=0D =0D =0D Commit: d59b7cdccc6558f126c3081f7582131029c35660=0D https://github.com/qemu/qemu/commit/d59b7cdccc6558f126c3081f7582131= 029c35660=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M target/arm/helper.c=0D =0D Log Message:=0D -----------=0D target/arm: Fix coding style issues in gdbstub code in helper.c=0D =0D We're going to move this code to a different file; fix the coding=0D style first so checkpatch doesn't complain. This includes deleting=0D the spurious 'break' statements after returns in the=0D vfp_gdb_get_reg() function.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-id: 20210921162901.17508-3-peter.maydell@linaro.org=0D =0D =0D Commit: 89f4f20e276e6e5dc08fca5e75e2bfbd92280072=0D https://github.com/qemu/qemu/commit/89f4f20e276e6e5dc08fca5e75e2bfb= d92280072=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M target/arm/gdbstub.c=0D M target/arm/gdbstub64.c=0D M target/arm/helper.c=0D M target/arm/internals.h=0D =0D Log Message:=0D -----------=0D target/arm: Move gdbstub related code out of helper.c=0D =0D Currently helper.c includes some code which is part of the arm=0D target's gdbstub support. This code has a better home: in gdbstub.c=0D and gdbstub64.c. Move it there.=0D =0D Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move=0D into gdbstub64.c, this means that they're now compiled only for=0D TARGET_AARCH64 rather than always. That is the only case when they=0D would ever be used, but it does mean that the ifdef in=0D arm_cpu_register_gdb_regs_for_features() needs to be adjusted to=0D match.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-id: 20210921162901.17508-4-peter.maydell@linaro.org=0D =0D =0D Commit: b355f08a3724d3f29e1c177dde3a01b649108f98=0D https://github.com/qemu/qemu/commit/b355f08a3724d3f29e1c177dde3a01b= 649108f98=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M configs/targets/aarch64-softmmu.mak=0D M configs/targets/arm-linux-user.mak=0D M configs/targets/arm-softmmu.mak=0D M configs/targets/armeb-linux-user.mak=0D M gdb-xml/arm-neon.xml=0D A gdb-xml/arm-vfp-sysregs.xml=0D M gdb-xml/arm-vfp.xml=0D M gdb-xml/arm-vfp3.xml=0D M target/arm/gdbstub.c=0D =0D Log Message:=0D -----------=0D target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML=0D =0D Currently we send VFP XML which includes D0..D15 or D0..D31, plus=0D FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its=0D definition of this XML feature does not include FPSID or FPEXC. In=0D particular, for M-profile cores there are no FPSID or FPEXC=0D registers, so advertising those is wrong.=0D =0D Move FPSID and FPEXC into their own bit of XML which we only send for=0D A and R profile cores. This brings our definition of the XML=0D org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for=0D non-Neon cores...) and means we don't claim to have FPSID and FPEXC=0D on M-profile.=0D =0D (It seems unlikely to me that any gdbstub users really care about=0D being able to look at FPEXC and FPSID; but we've supplied them to gdb=0D for a decade and it's not hard to keep doing so.)=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Richard Henderson =0D Message-id: 20210921162901.17508-5-peter.maydell@linaro.org=0D =0D =0D Commit: 739e95f5741b8efd74331bb74b9446bcb5ede71e=0D https://github.com/qemu/qemu/commit/739e95f5741b8efd74331bb74b9446b= cb5ede71e=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/scsi/esp-pci.c=0D M hw/scsi/esp.c=0D M hw/scsi/lsi53c895a.c=0D M hw/scsi/megasas.c=0D M hw/scsi/mptsas.c=0D M hw/scsi/scsi-bus.c=0D M hw/scsi/spapr_vscsi.c=0D M hw/scsi/virtio-scsi.c=0D M hw/scsi/vmw_pvscsi.c=0D M hw/usb/dev-storage-bot.c=0D M hw/usb/dev-storage-classic.c=0D M hw/usb/dev-uas.c=0D M include/hw/scsi/scsi.h=0D =0D Log Message:=0D -----------=0D scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named(= )=0D =0D The function scsi_bus_new() creates a new SCSI bus; callers can=0D either pass in a name argument to specify the name of the new bus, or=0D they can pass in NULL to allow the bus to be given an automatically=0D generated unique name. Almost all callers want to use the=0D autogenerated name; the only exception is the virtio-scsi device.=0D =0D Taking a name argument that should almost always be NULL is an=0D easy-to-misuse API design -- it encourages callers to think perhaps=0D they should pass in some standard name like "scsi" or "scsi-bus". We=0D don't do this anywhere for SCSI, but we do (incorrectly) do it for=0D other bus types such as i2c.=0D =0D The function name also implies that it will return a newly allocated=0D object, when it in fact does in-place allocation. We more commonly=0D name such functions foo_init(), with foo_new() being the=0D allocate-and-return variant.=0D =0D Replace all the scsi_bus_new() callsites with either:=0D * scsi_bus_init() for the usual case where the caller wants=0D an autogenerated bus name=0D * scsi_bus_init_named() for the rare case where the caller=0D needs to specify the bus name=0D =0D and document that for the _named() version it's then the caller's=0D responsibility to think about uniqueness of bus names.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Acked-by: Paolo Bonzini =0D Message-id: 20210923121153.23754-2-peter.maydell@linaro.org=0D =0D =0D Commit: 43417c0c27fd0851707a1f3bf50244d24aeeaf82=0D https://github.com/qemu/qemu/commit/43417c0c27fd0851707a1f3bf50244d= 24aeeaf82=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/ipack/ipack.c=0D M hw/ipack/tpci200.c=0D M include/hw/ipack/ipack.h=0D =0D Log Message:=0D -----------=0D ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()=0D =0D Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to=0D line with a "_init for in-place init, _new for allocate-and-return"=0D convention. Drop the 'name' argument, because the only caller does=0D not pass in a name. If a future caller does need to specify the bus=0D name, we should create an ipack_bus_init_named() function at that=0D point.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Message-id: 20210923121153.23754-3-peter.maydell@linaro.org=0D =0D =0D Commit: 8d4cdf01f89fd834b952df2dd08f55e897a72ea8=0D https://github.com/qemu/qemu/commit/8d4cdf01f89fd834b952df2dd08f55e= 897a72ea8=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/pci-host/raven.c=0D M hw/pci-host/versatile.c=0D M hw/pci/pci.c=0D M include/hw/pci/pci.h=0D =0D Log Message:=0D -----------=0D pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()=0D =0D Rename the pci_root_bus_new_inplace() function to=0D pci_root_bus_init(); this brings the bus type in to line with a=0D "_init for in-place init, _new for allocate-and-return" convention.=0D To do this we need to rename the implementation-internal function=0D that was using the pci_root_bus_init() name to=0D pci_root_bus_internal_init().=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Message-id: 20210923121153.23754-4-peter.maydell@linaro.org=0D =0D =0D Commit: d637e1dc6de0e171dca6fbb5384668c642aa5ab6=0D https://github.com/qemu/qemu/commit/d637e1dc6de0e171dca6fbb5384668c= 642aa5ab6=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/audio/intel-hda.c=0D M hw/block/fdc.c=0D M hw/block/swim.c=0D M hw/char/virtio-serial-bus.c=0D M hw/core/bus.c=0D M hw/core/sysbus.c=0D M hw/gpio/bcm2835_gpio.c=0D M hw/ide/qdev.c=0D M hw/ipack/ipack.c=0D M hw/misc/mac_via.c=0D M hw/misc/macio/cuda.c=0D M hw/misc/macio/macio.c=0D M hw/misc/macio/pmu.c=0D M hw/nubus/nubus-bridge.c=0D M hw/nvme/ctrl.c=0D M hw/nvme/subsys.c=0D M hw/pci/pci.c=0D M hw/pci/pci_bridge.c=0D M hw/s390x/event-facility.c=0D M hw/s390x/virtio-ccw.c=0D M hw/scsi/scsi-bus.c=0D M hw/sd/allwinner-sdhost.c=0D M hw/sd/bcm2835_sdhost.c=0D M hw/sd/pl181.c=0D M hw/sd/pxa2xx_mmci.c=0D M hw/sd/sdhci.c=0D M hw/sd/ssi-sd.c=0D M hw/usb/bus.c=0D M hw/usb/dev-smartcard-reader.c=0D M hw/virtio/virtio-mmio.c=0D M hw/virtio/virtio-pci.c=0D M include/hw/qdev-core.h=0D =0D Log Message:=0D -----------=0D qbus: Rename qbus_create_inplace() to qbus_init()=0D =0D Rename qbus_create_inplace() to qbus_init(); this is more in line=0D with our usual naming convention for functions that in-place=0D initialize objects.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Message-id: 20210923121153.23754-5-peter.maydell@linaro.org=0D =0D =0D Commit: 9388d1701efa87095d31ed5f68793dfc82cdd47e=0D https://github.com/qemu/qemu/commit/9388d1701efa87095d31ed5f68793df= c82cdd47e=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/core/bus.c=0D M hw/hyperv/vmbus.c=0D M hw/i2c/core.c=0D M hw/isa/isa-bus.c=0D M hw/misc/auxbus.c=0D M hw/pci/pci.c=0D M hw/ppc/spapr_vio.c=0D M hw/s390x/ap-bridge.c=0D M hw/s390x/css-bridge.c=0D M hw/s390x/s390-pci-bus.c=0D M hw/ssi/ssi.c=0D M hw/xen/xen-bus.c=0D M hw/xen/xen-legacy-backend.c=0D M include/hw/qdev-core.h=0D =0D Log Message:=0D -----------=0D qbus: Rename qbus_create() to qbus_new()=0D =0D Rename the "allocate and return" qbus creation function to=0D qbus_new(), to bring it into line with our _init vs _new convention.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Reviewed-by: Corey Minyard =0D Message-id: 20210923121153.23754-6-peter.maydell@linaro.org=0D =0D =0D Commit: 82c74ac42e1b9e564a3c011dca6215d130b7e6a0=0D https://github.com/qemu/qemu/commit/82c74ac42e1b9e564a3c011dca6215d= 130b7e6a0=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/ide/ahci.c=0D M hw/ide/cmd646.c=0D M hw/ide/isa.c=0D M hw/ide/macio.c=0D M hw/ide/microdrive.c=0D M hw/ide/mmio.c=0D M hw/ide/piix.c=0D M hw/ide/qdev.c=0D M hw/ide/sii3112.c=0D M hw/ide/via.c=0D M include/hw/ide/internal.h=0D =0D Log Message:=0D -----------=0D ide: Rename ide_bus_new() to ide_bus_init()=0D =0D The function ide_bus_new() does an in-place initialization. Rename=0D it to ide_bus_init() to follow our _init vs _new convention.=0D =0D Signed-off-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Michael S. Tsirkin =0D Reviewed-by: Corey Minyard =0D Reviewed-by: John Snow =0D Acked-by: John Snow (Feel free to merge.)=0D Message-id: 20210923121153.23754-7-peter.maydell@linaro.org=0D =0D =0D Commit: 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b=0D https://github.com/qemu/qemu/commit/1f4b2ec701b9d73d3fa7bb90c8b4376= bc7d3c42b=0D Author: Xuzhou Cheng =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M hw/arm/sabrelite.c=0D =0D Log Message:=0D -----------=0D hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19=0D =0D The Linux spi-imx driver does not work on QEMU. The reason is that the=0D= state of m25p80 loops in STATE_READING_DATA state after receiving=0D RDSR command, the new command is ignored. Before sending a new command,=0D= CS line should be pulled high to make the state of m25p80 back to IDLE.=0D= =0D Currently the SPI flash CS line is connected to the SPI controller, but=0D= on the real board, it's connected to GPIO3_19. This matches the ecspi1=0D= device node in the board dts.=0D =0D ecspi1 node in imx6qdl-sabrelite.dtsi:=0D &ecspi1 {=0D cs-gpios =3D <&gpio3 19 GPIO_ACTIVE_LOW>;=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&pinctrl_ecspi1>;=0D status =3D "okay";=0D =0D flash: m25p80@0 {=0D compatible =3D "sst,sst25vf016b", "jedec,spi-nor";=0D spi-max-frequency =3D <20000000>;=0D reg =3D <0>;=0D };=0D };=0D =0D Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to=0D spi1 on sabrelite machine.=0D =0D Verified this patch on Linux v5.14.=0D =0D Logs:=0D # echo "01234567899876543210" > test=0D # mtd_debug erase /dev/mtd0 0x0 0x1000=0D Erased 4096 bytes from address 0x00000000 in flash=0D # mtd_debug write /dev/mtdblock0 0x0 20 test=0D Copied 20 bytes from test to address 0x00000000 in flash=0D # mtd_debug read /dev/mtdblock0 0x0 20 test_out=0D Copied 20 bytes from address 0x00000000 in flash to test_out=0D # cat test_out=0D 01234567899876543210#=0D =0D Signed-off-by: Xuzhou Cheng =0D Reported-by: Guenter Roeck =0D Reviewed-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210927142825.491-1-xchengl.cn@gmail.com=0D Signed-off-by: Peter Maydell =0D =0D =0D Commit: bb4aa8f59e18412cff0d69f14aee7abba153161a=0D https://github.com/qemu/qemu/commit/bb4aa8f59e18412cff0d69f14aee7ab= ba153161a=0D Author: Peter Maydell =0D Date: 2021-09-30 (Thu, 30 Sep 2021)=0D =0D Changed paths:=0D M configs/targets/aarch64-linux-user.mak=0D M configs/targets/aarch64-softmmu.mak=0D M configs/targets/aarch64_be-linux-user.mak=0D M configs/targets/arm-linux-user.mak=0D M configs/targets/arm-softmmu.mak=0D M configs/targets/armeb-linux-user.mak=0D M docs/system/arm/xlnx-versal-virt.rst=0D M gdb-xml/arm-neon.xml=0D A gdb-xml/arm-vfp-sysregs.xml=0D M gdb-xml/arm-vfp.xml=0D M gdb-xml/arm-vfp3.xml=0D M hw/Kconfig=0D M hw/arm/Kconfig=0D M hw/arm/allwinner-h3.c=0D M hw/arm/sabrelite.c=0D M hw/arm/xlnx-versal-virt.c=0D M hw/arm/xlnx-versal.c=0D M hw/arm/xlnx-zcu102.c=0D M hw/arm/xlnx-zynqmp.c=0D M hw/audio/intel-hda.c=0D M hw/block/fdc.c=0D M hw/block/swim.c=0D M hw/char/virtio-serial-bus.c=0D M hw/core/bus.c=0D M hw/core/sysbus.c=0D M hw/gpio/bcm2835_gpio.c=0D M hw/hyperv/vmbus.c=0D M hw/i2c/core.c=0D M hw/ide/ahci.c=0D M hw/ide/cmd646.c=0D M hw/ide/isa.c=0D M hw/ide/macio.c=0D M hw/ide/microdrive.c=0D M hw/ide/mmio.c=0D M hw/ide/piix.c=0D M hw/ide/qdev.c=0D M hw/ide/sii3112.c=0D M hw/ide/via.c=0D M hw/ipack/ipack.c=0D M hw/ipack/tpci200.c=0D M hw/isa/isa-bus.c=0D M hw/misc/auxbus.c=0D M hw/misc/mac_via.c=0D M hw/misc/macio/cuda.c=0D M hw/misc/macio/macio.c=0D M hw/misc/macio/pmu.c=0D M hw/nubus/nubus-bridge.c=0D M hw/nvme/ctrl.c=0D M hw/nvme/subsys.c=0D M hw/nvram/Kconfig=0D M hw/nvram/meson.build=0D A hw/nvram/xlnx-bbram.c=0D A hw/nvram/xlnx-efuse-crc.c=0D A hw/nvram/xlnx-efuse.c=0D A hw/nvram/xlnx-versal-efuse-cache.c=0D A hw/nvram/xlnx-versal-efuse-ctrl.c=0D A hw/nvram/xlnx-zynqmp-efuse.c=0D M hw/pci-host/raven.c=0D M hw/pci-host/versatile.c=0D M hw/pci/pci.c=0D M hw/pci/pci_bridge.c=0D M hw/ppc/spapr_vio.c=0D M hw/s390x/ap-bridge.c=0D M hw/s390x/css-bridge.c=0D M hw/s390x/event-facility.c=0D M hw/s390x/s390-pci-bus.c=0D M hw/s390x/virtio-ccw.c=0D M hw/scsi/esp-pci.c=0D M hw/scsi/esp.c=0D M hw/scsi/lsi53c895a.c=0D M hw/scsi/megasas.c=0D M hw/scsi/mptsas.c=0D M hw/scsi/scsi-bus.c=0D M hw/scsi/spapr_vscsi.c=0D M hw/scsi/virtio-scsi.c=0D M hw/scsi/vmw_pvscsi.c=0D M hw/sd/allwinner-sdhost.c=0D M hw/sd/bcm2835_sdhost.c=0D M hw/sd/pl181.c=0D M hw/sd/pxa2xx_mmci.c=0D M hw/sd/sdhci.c=0D M hw/sd/ssi-sd.c=0D M hw/ssi/ssi.c=0D M hw/usb/bus.c=0D M hw/usb/dev-smartcard-reader.c=0D M hw/usb/dev-storage-bot.c=0D M hw/usb/dev-storage-classic.c=0D M hw/usb/dev-uas.c=0D M hw/virtio/virtio-mmio.c=0D M hw/virtio/virtio-pci.c=0D M hw/xen/xen-bus.c=0D M hw/xen/xen-legacy-backend.c=0D M include/hw/arm/xlnx-versal.h=0D M include/hw/arm/xlnx-zynqmp.h=0D M include/hw/ide/internal.h=0D M include/hw/ipack/ipack.h=0D A include/hw/nvram/xlnx-bbram.h=0D A include/hw/nvram/xlnx-efuse.h=0D A include/hw/nvram/xlnx-versal-efuse.h=0D A include/hw/nvram/xlnx-zynqmp-efuse.h=0D M include/hw/pci/pci.h=0D M include/hw/qdev-core.h=0D M include/hw/scsi/scsi.h=0D M target/arm/gdbstub.c=0D M target/arm/gdbstub64.c=0D M target/arm/helper.c=0D M target/arm/internals.h=0D M target/arm/psci.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-202= 10930' into staging=0D =0D target-arm queue:=0D * allwinner-h3: Switch to SMC as PSCI conduit=0D * arm: tcg: Adhere to SMCCC 1.3 section 5.2=0D * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices=0D * gdbstub related code cleanups=0D * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML=0D * Use _init vs _new convention in bus creation function names=0D * sabrelite: Connect SPI flash CS line to GPIO3_19=0D =0D # gpg: Signature made Thu 30 Sep 2021 16:11:20 BST=0D # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360= CDE=0D # gpg: issuer "peter.maydell@linaro.org"=0D # gpg: Good signature from "Peter Maydell " [ul= timate]=0D # gpg: aka "Peter Maydell " [ultimate= ]=0D # gpg: aka "Peter Maydell " [ultimate]=0D # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 = 0CDE=0D =0D * remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits)=0D hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19=0D ide: Rename ide_bus_new() to ide_bus_init()=0D qbus: Rename qbus_create() to qbus_new()=0D qbus: Rename qbus_create_inplace() to qbus_init()=0D pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()=0D ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()=0D scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named(= )=0D target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML=0D target/arm: Move gdbstub related code out of helper.c=0D target/arm: Fix coding style issues in gdbstub code in helper.c=0D configs: Don't include 32-bit-only GDB XML in aarch64 linux configs=0D docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage=0D hw/arm: xlnx-zcu102: Add Xilinx eFUSE device=0D hw/arm: xlnx-zcu102: Add Xilinx BBRAM device=0D hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device=0D hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device=0D hw/nvram: Introduce Xilinx battery-backed ram=0D hw/nvram: Introduce Xilinx ZynqMP eFuse device=0D hw/nvram: Introduce Xilinx Versal eFuse device=0D hw/nvram: Introduce Xilinx eFuse QOM=0D ...=0D =0D Signed-off-by: Peter Maydell =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/0021c4765a6b...bb4aa8f59e18= =0D From MAILER-DAEMON Fri Oct 01 13:45:20 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mWMb2-0000Kb-FY for mharc-qemu-commits@gnu.org; Fri, 01 Oct 2021 13:45:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWMax-0000GF-ON for qemu-commits@nongnu.org; Fri, 01 Oct 2021 13:45:17 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:57957 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWMas-0006IJ-69 for qemu-commits@nongnu.org; Fri, 01 Oct 2021 13:45:15 -0400 Received: from github.com (hubbernetes-node-cc91d20.ac4-iad.github.net [10.52.211.57]) by smtp.github.com (Postfix) with ESMTPA id 5C5885604C8 for ; Fri, 1 Oct 2021 10:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633110309; bh=zIOZn4t9i3Hy/uDNreCAqHn0ol1Uf9Mr+tkxKND0X6g=; h=Date:From:To:Subject:From; b=gmVmtPM9+pXrMRy+tveHXM9i1qk7vEGlRObilulIsJ0LXs9ojyR9ovQuEdYLB0/7L PWpX0bS+gjAvKmkRyAE/v4wrVbW2uw/qqZDRUv817Rwx2okngl4kBJ8EDXCdVy2Q9e 88hvhR7YYTG5876jHubRJAweJroRMBe8q0M24H/w= Date: Fri, 01 Oct 2021 10:45:09 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7237c7: qapi/machine: Fix an incorrect comment of SMPConfi... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Oct 2021 17:45:17 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 7237c7ce772794d6be10b8b987fe4d02dfd76562=0D https://github.com/qemu/qemu/commit/7237c7ce772794d6be10b8b987fe4d0= 2dfd76562=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M qapi/machine.json=0D =0D Log Message:=0D -----------=0D qapi/machine: Fix an incorrect comment of SMPConfiguration=0D =0D The explanation of @cores should be "number of cores per die" but=0D not "number of cores per thread". Let's fix it.=0D =0D Fixes: 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse")=0D Signed-off-by: Yanan Wang =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-2-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: c2511b1632e109130df524121dfb7d2413216d3c=0D https://github.com/qemu/qemu/commit/c2511b1632e109130df524121dfb7d2= 413216d3c=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M hw/core/machine.c=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Deprecate "parameter=3D0" SMP configurations=0D =0D In the SMP configuration, we should either provide a topology=0D parameter with a reasonable value (greater than zero) or just=0D omit it and QEMU will compute the missing value.=0D =0D The users shouldn't provide a configuration with any parameter=0D of it specified as zero (e.g. -smp 8,sockets=3D0) which could=0D possibly cause unexpected results in the -smp parsing. So we=0D deprecate this kind of configurations since 6.2 by adding the=0D explicit sanity check.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Cornelia Huck =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-3-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 5d8b5a505571b7927095015c805646f78fc56578=0D https://github.com/qemu/qemu/commit/5d8b5a505571b7927095015c805646f= 78fc56578=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Minor refactor/fix for the smp parsers=0D =0D To pave the way for the functional improvement in later patches,=0D make some refactor/cleanup for the smp parsers, including using=0D local maxcpus instead of ms->smp.max_cpus in the calculation,=0D defaulting dies to 0 initially like other members, cleanup the=0D sanity check for dies.=0D =0D We actually also fix a hidden defect by avoiding directly using=0D the provided *zero value* in the calculation, which could cause=0D a segment fault (e.g. using dies=3D0 in the calculation).=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-4-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9a52b508061163df4dae05e708cd2a9cd790ad04=0D https://github.com/qemu/qemu/commit/9a52b508061163df4dae05e708cd2a9= cd790ad04=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Uniformly use maxcpus to calculate the omitted parameters=0D =0D We are currently using maxcpus to calculate the omitted sockets=0D but using cpus to calculate the omitted cores/threads. This makes=0D cmdlines like:=0D -smp cpus=3D8,maxcpus=3D16=0D -smp cpus=3D8,cores=3D4,maxcpus=3D16=0D -smp cpus=3D8,threads=3D2,maxcpus=3D16=0D work fine but the ones like:=0D -smp cpus=3D8,sockets=3D2,maxcpus=3D16=0D -smp cpus=3D8,sockets=3D2,cores=3D4,maxcpus=3D16=0D -smp cpus=3D8,sockets=3D2,threads=3D2,maxcpus=3D16=0D break the sanity check.=0D =0D Since we require for a valid config that the product of "sockets * cores=0D= * threads" should equal to the maxcpus, we should uniformly use maxcpus=0D= to calculate their omitted values.=0D =0D Also the if-branch of "cpus =3D=3D 0 || sockets =3D=3D 0" was split into = two=0D branches of "cpus =3D=3D 0" and "sockets =3D=3D 0" so that we can clearly= read=0D that we are parsing the configuration with a preference on cpus over=0D sockets over cores over threads.=0D =0D Note: change in this patch won't affect any existing working cmdlines=0D but improves consistency and allows more incomplete configs to be valid.=0D= =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-5-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7d8c5a39628820f6927b8b70c8f54872f5d1a196=0D https://github.com/qemu/qemu/commit/7d8c5a39628820f6927b8b70c8f5487= 2f5d1a196=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Set the value of cpus to match maxcpus if it's omitted=0D =0D Currently we directly calculate the omitted cpus based on the given=0D incomplete collection of parameters. This makes some cmdlines like:=0D -smp maxcpus=3D16=0D -smp sockets=3D2,maxcpus=3D16=0D -smp sockets=3D2,dies=3D2,maxcpus=3D16=0D -smp sockets=3D2,cores=3D4,maxcpus=3D16=0D not work. We should probably set the value of cpus to match maxcpus=0D if it's omitted, which will make above configs start to work.=0D =0D So the calculation logic of cpus/maxcpus after this patch will be:=0D When both maxcpus and cpus are omitted, maxcpus will be calculated=0D from the given parameters and cpus will be set equal to maxcpus.=0D When only one of maxcpus and cpus is given then the omitted one=0D will be set to its counterpart's value. Both maxcpus and cpus may=0D be specified, but maxcpus must be equal to or greater than cpus.=0D =0D Note: change in this patch won't affect any existing working cmdlines=0D but allows more incomplete configs to be valid.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-6-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 52082d3ba4e81bf9df23d3cd5ddfb2a620e9b267=0D https://github.com/qemu/qemu/commit/52082d3ba4e81bf9df23d3cd5ddfb2a= 620e9b267=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Improve the error reporting of smp parsing=0D =0D We have two requirements for a valid SMP configuration:=0D the product of "sockets * cores * threads" must represent all the=0D possible cpus, i.e., max_cpus, and then must include the initially=0D present cpus, i.e., smp_cpus.=0D =0D So we only need to ensure 1) "sockets * cores * threads =3D=3D maxcpus"=0D= at first and then ensure 2) "maxcpus >=3D cpus". With a reasonable=0D order of the sanity check, we can simplify the error reporting code.=0D When reporting an error message we also report the exact value of=0D each topology member to make users easily see what's going on.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-7-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: afc8e9aaa7915ebfe1af8eba6994a38b3e556ba9=0D https://github.com/qemu/qemu/commit/afc8e9aaa7915ebfe1af8eba6994a38= b3e556ba9=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D qtest/numa-test: Use detailed -smp CLIs in pc_dynamic_cpu_cfg=0D =0D Since commit 80d7835749 (qemu-options: rewrite help for -smp options),=0D= the preference of sockets/cores in -smp parsing is considered liable=0D to change, and actually we are going to change it in a coming commit.=0D So it'll be more stable to use detailed -smp CLIs in testing if we=0D have strong dependency on the parsing results.=0D =0D pc_dynamic_cpu_cfg currently assumes/needs that there will be 2 CPU=0D sockets with "-smp 2". To avoid breaking the test because of parsing=0D logic change, now explicitly use "-smp 2,sockets=3D2".=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-8-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bbb0c0ec6da8a739b02fbff941b44afc5513d6e4=0D https://github.com/qemu/qemu/commit/bbb0c0ec6da8a739b02fbff941b44af= c5513d6e4=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D qtest/numa-test: Use detailed -smp CLIs in test_def_cpu_split=0D =0D Since commit 80d7835749 (qemu-options: rewrite help for -smp options),=0D= the preference of sockets/cores in -smp parsing is considered liable=0D to change, and actually we are going to change it in a coming commit.=0D So it'll be more stable to use detailed -smp CLIs in the testcases=0D that have strong dependency on the parsing results.=0D =0D Currently, test_def_cpu_split use "-smp 8" and will get 8 CPU sockets=0D based on current parsing rule. But if we change to prefer cores over=0D sockets we will get one CPU socket with 8 cores, and this testcase=0D will not get expected numa set by default on x86_64 (Ok on aarch64).=0D =0D So now explicitly use "-smp 8,sockets=3D8" to avoid affect from parsing=0D= logic change.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-9-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4a0af2930a4e4f64ce551152fdb4b9e7be106408=0D https://github.com/qemu/qemu/commit/4a0af2930a4e4f64ce551152fdb4b9e= 7be106408=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Prefer cores over sockets in smp parsing since 6.2=0D =0D In the real SMP hardware topology world, it's much more likely that=0D we have high cores-per-socket counts and few sockets totally. While=0D the current preference of sockets over cores in smp parsing results=0D in a virtual cpu topology with low cores-per-sockets counts and a=0D large number of sockets, which is just contrary to the real world.=0D =0D Given that it is better to make the virtual cpu topology be more=0D reflective of the real world and also for the sake of compatibility,=0D we start to prefer cores over sockets over threads in smp parsing=0D since machine type 6.2 for different arches.=0D =0D In this patch, a boolean "smp_prefer_sockets" is added, and we only=0D enable the old preference on older machines and enable the new one=0D since type 6.2 for all arches by using the machine compat mechanism.=0D =0D Suggested-by: Daniel P. Berrange =0D Signed-off-by: Yanan Wang =0D Acked-by: David Gibson =0D Acked-by: Cornelia Huck =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-10-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69fc28a78dbff2d3414bbafce38320b4433ed583=0D https://github.com/qemu/qemu/commit/69fc28a78dbff2d3414bbafce38320b= 4433ed583=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Use ms instead of global current_machine in sanity-check=0D =0D In the sanity-check of smp_cpus and max_cpus against mc in function=0D machine_set_smp(), we are now using ms->smp.max_cpus for the check=0D but using current_machine->smp.max_cpus in the error message.=0D Tweak this by uniformly using the local ms.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Cornelia Huck =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-11-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 003f230e37d724ac52004d7f8270159da105780f=0D https://github.com/qemu/qemu/commit/003f230e37d724ac52004d7f8270159= da105780f=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Tweak the order of topology members in struct CpuTopology=0D =0D Now that all the possible topology parameters are integrated in struct=0D= CpuTopology, tweak the order of topology members to be "cpus/sockets/=0D dies/cores/threads/maxcpus" for readability and consistency. We also=0D tweak the comment by adding explanation of dies parameter.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-12-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e4a97a893bcd7511aba812969d1fa6fe42dc1931=0D https://github.com/qemu/qemu/commit/e4a97a893bcd7511aba812969d1fa6f= e42dc1931=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Make smp_parse generic enough for all arches=0D =0D Currently the only difference between smp_parse and pc_smp_parse=0D is the support of dies parameter and the related error reporting.=0D With some arch compat variables like "bool dies_supported", we can=0D make smp_parse generic enough for all arches and the PC specific=0D one can be removed.=0D =0D Making smp_parse() generic enough can reduce code duplication and=0D ease the code maintenance, and also allows extending the topology=0D with more arch specific members (e.g., clusters) in the future.=0D =0D Suggested-by: Andrew Jones =0D Suggested-by: Daniel P. Berrang=C3=A9 =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-13-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7687b2b3edc3f29ad58e8d6593d5c10dde406c34=0D https://github.com/qemu/qemu/commit/7687b2b3edc3f29ad58e8d6593d5c10= dde406c34=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Remove smp_parse callback from MachineClass=0D =0D Now we have a generic smp parser for all arches, and there will=0D not be any other arch specific ones, so let's remove the callback=0D from MachineClass and call the parser directly.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-14-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2b52619994ab48504c5fc0d32a1af24159405ce0=0D https://github.com/qemu/qemu/commit/2b52619994ab48504c5fc0d32a1af24= 159405ce0=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Move smp_prefer_sockets to struct SMPCompatProps=0D =0D Now we have a common structure SMPCompatProps used to store information=0D= about SMP compatibility stuff, so we can also move smp_prefer_sockets=0D there for cleaner code.=0D =0D No functional change intended.=0D =0D Signed-off-by: Yanan Wang =0D Acked-by: David Gibson =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-15-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e7f944bb94a375e8ee7469ffa535ea6e11ce59e1=0D https://github.com/qemu/qemu/commit/e7f944bb94a375e8ee7469ffa535ea6= e11ce59e1=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Use g_autoptr in machine_set_smp=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8bdfec393a2ac67df9cecc0983d130db4a6bba58=0D https://github.com/qemu/qemu/commit/8bdfec393a2ac67df9cecc0983d130d= b4a6bba58=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Put all sanity-check in the generic SMP parser=0D =0D Put both sanity-check of the input SMP configuration and sanity-check=0D of the output SMP configuration uniformly in the generic parser. Then=0D machine_set_smp() will become cleaner, also all the invalid scenarios=0D can be tested only by calling the parser.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-16-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 988f7b8bfeffbf521814d1e48c321f7674277512=0D https://github.com/qemu/qemu/commit/988f7b8bfeffbf521814d1e48c321f7= 674277512=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Support KVM_CAP_ENFORCE_PV_FEATURE_CPUID=0D =0D By default, KVM allows the guest to use all currently supported PV featur= es=0D even when they were not announced in guest visible CPUIDs. Introduce a ne= w=0D "kvm-pv-enforce-cpuid" flag to limit the supported feature set to the=0D exposed features. The feature is supported by Linux >=3D 5.10 and is not=0D= enabled by default in QEMU.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-4-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 70367f091777419f42e5f68f4206deb641335877=0D https://github.com/qemu/qemu/commit/70367f091777419f42e5f68f4206deb= 641335877=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Support KVM_CAP_HYPERV_ENFORCE_CPUID=0D =0D By default, KVM allows the guest to use all currently supported Hyper-V=0D= enlightenments when Hyper-V CPUID interface was exposed, regardless of if= =0D some features were not announced in guest visible CPUIDs. hv-enforce-cpui= d=0D feature alters this behavior and only allows the guest to use exposed=0D Hyper-V enlightenments. The feature is supported by Linux >=3D 5.14 and i= s=0D not enabled by default in QEMU.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-5-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 050716292a63f4969b32cac32b85774521738ef5=0D https://github.com/qemu/qemu/commit/050716292a63f4969b32cac32b85774= 521738ef5=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Move HV_APIC_ACCESS_RECOMMENDED bit setting to hyperv_fill_cpuids= ()=0D =0D In preparation to enabling Hyper-V + APICv/AVIC move=0D HV_APIC_ACCESS_RECOMMENDED setting out of kvm_hyperv_properties[]: the=0D= 'real' feature bit for the vAPIC features is HV_APIC_ACCESS_AVAILABLE,=0D= HV_APIC_ACCESS_RECOMMENDED is a recommendation to use the feature which=0D= we may not always want to give.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-6-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e1f9a8e8c90ae54387922e33e5ac4fd759747d01=0D https://github.com/qemu/qemu/commit/e1f9a8e8c90ae54387922e33e5ac4fd= 759747d01=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/hyperv-proto.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Implement pseudo 'hv-avic' ('hv-apicv') enlightenment=0D =0D The enlightenment allows to use Hyper-V SynIC with hardware APICv/AVIC=0D= enabled. Normally, Hyper-V SynIC disables these hardware features and=0D suggests the guest to use paravirtualized AutoEOI feature. Linux-4.15=0D gains support for conditional APICv/AVIC disablement, the feature=0D stays on until the guest tries to use AutoEOI feature with SynIC. With=0D= 'HV_DEPRECATING_AEOI_RECOMMENDED' bit exposed, modern enough Windows/=0D Hyper-V versions should follow the recommendation and not use the=0D (unwanted) feature.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-7-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: af7228b88dbe80ed5d5258b49be8b48ab351a476=0D https://github.com/qemu/qemu/commit/af7228b88dbe80ed5d5258b49be8b48= ab351a476=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Make Hyper-V version id configurable=0D =0D Currently, we hardcode Hyper-V version id (CPUID 0x40000002) to=0D WS2008R2 and it is known that certain tools in Windows check this. It=0D seems useful to provide some flexibility by making it possible to change=0D= this info at will. CPUID information is defined in TLFS as:=0D =0D EAX: Build Number=0D EBX Bits 31-16: Major Version=0D Bits 15-0: Minor Version=0D ECX Service Pack=0D EDX Bits 31-24: Service Branch=0D Bits 23-0: Service Number=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-8-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f701ecec2bbaae2d04985eba87924a7329534e9a=0D https://github.com/qemu/qemu/commit/f701ecec2bbaae2d04985eba87924a7= 329534e9a=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M hw/i386/pc.c=0D M target/i386/cpu.c=0D =0D Log Message:=0D -----------=0D i386: Change the default Hyper-V version to match WS2016=0D =0D KVM implements some Hyper-V 2016 functions so providing WS2008R2 version=0D= is somewhat incorrect. While generally guests shouldn't care about it=0D and always check feature bits, it is known that some tools in Windows=0D actually check version info.=0D =0D For compatibility reasons make the change for 6.2 machine types only.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-9-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bcfdfae78f111fa3c0f81b2708098a545201bb68=0D https://github.com/qemu/qemu/commit/bcfdfae78f111fa3c0f81b2708098a5= 45201bb68=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D R docs/devel/ci-definitions.rst=0D A docs/devel/ci-definitions.rst.inc=0D R docs/devel/ci-jobs.rst=0D A docs/devel/ci-jobs.rst.inc=0D R docs/devel/ci-runners.rst=0D A docs/devel/ci-runners.rst.inc=0D M docs/devel/ci.rst=0D =0D Log Message:=0D -----------=0D docs: name included files ".rst.inc"=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f9df7aac758fed5cc2fb9210ad0edba79434aeed=0D https://github.com/qemu/qemu/commit/f9df7aac758fed5cc2fb9210ad0edba= 79434aeed=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/multi-process.rst=0D =0D Log Message:=0D -----------=0D docs: move notes inside the body of the document=0D =0D Make all documents start with a heading.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8b8939e44fc8315885598a9e1ee8deeea3b68a96=0D https://github.com/qemu/qemu/commit/8b8939e44fc8315885598a9e1ee8dee= ea3b68a96=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/build-system.rst=0D =0D Log Message:=0D -----------=0D docs: put "make" information together in build-system.rst=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 768f14f94ec50fe57a3964fff75d8b3456b588b5=0D https://github.com/qemu/qemu/commit/768f14f94ec50fe57a3964fff75d8b3= 456b588b5=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qgraph.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize qgraph.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~, and move the comman= d line=0D building near to the other execution steps.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e9adb4ace229dfa742176e9ddb629dbb6a6081bc=0D https://github.com/qemu/qemu/commit/e9adb4ace229dfa742176e9ddb629db= b6a6081bc=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/tcg-plugins.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize tcg-plugins.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~, and create a new "w= riting=0D plugins" section.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9fce3601761779f14d8d1ea32e2b6abf2f704edb=0D https://github.com/qemu/qemu/commit/9fce3601761779f14d8d1ea32e2b6ab= f2f704edb=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/testing.rst=0D =0D Log Message:=0D -----------=0D docs: move gcov section at the end of testing.rst=0D =0D gcov testing applies to all tests, not just make check. Move it=0D out of the make check section.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 16e79e1b01a698908e14eda3078d4a8e7b1b9c2b=0D https://github.com/qemu/qemu/commit/16e79e1b01a698908e14eda3078d4a8= e7b1b9c2b=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/testing.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize testing.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~ ^^^ '''. Reorganize= the=0D outline for the Avocado part, and always include headings for the=0D class names.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 5f992102383ed8ed97076548e1c897c7034ed8a4=0D https://github.com/qemu/qemu/commit/5f992102383ed8ed97076548e1c897c= 7034ed8a4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/build-system.rst=0D R docs/devel/ci-definitions.rst=0D A docs/devel/ci-definitions.rst.inc=0D R docs/devel/ci-jobs.rst=0D A docs/devel/ci-jobs.rst.inc=0D R docs/devel/ci-runners.rst=0D A docs/devel/ci-runners.rst.inc=0D M docs/devel/ci.rst=0D M docs/devel/multi-process.rst=0D M docs/devel/qgraph.rst=0D M docs/devel/tcg-plugins.rst=0D M docs/devel/testing.rst=0D M docs/hyperv.txt=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D M qapi/machine.json=0D M qemu-options.hx=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/hyperv-proto.h=0D M target/i386/kvm/kvm.c=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * -smp cleanpus=0D * Hyper-V englightenment functionality=0D * Documentation cleanups=0D =0D # gpg: Signature made Fri 01 Oct 2021 01:11:00 PM EDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (29 commits)=0D docs: reorganize testing.rst=0D docs: move gcov section at the end of testing.rst=0D docs: reorganize tcg-plugins.rst=0D docs: reorganize qgraph.rst=0D docs: put "make" information together in build-system.rst=0D docs: move notes inside the body of the document=0D docs: name included files ".rst.inc"=0D i386: Change the default Hyper-V version to match WS2016=0D i386: Make Hyper-V version id configurable=0D i386: Implement pseudo 'hv-avic' ('hv-apicv') enlightenment=0D i386: Move HV_APIC_ACCESS_RECOMMENDED bit setting to hyperv_fill_cpuids= ()=0D i386: Support KVM_CAP_HYPERV_ENFORCE_CPUID=0D i386: Support KVM_CAP_ENFORCE_PV_FEATURE_CPUID=0D machine: Put all sanity-check in the generic SMP parser=0D machine: Use g_autoptr in machine_set_smp=0D machine: Move smp_prefer_sockets to struct SMPCompatProps=0D machine: Remove smp_parse callback from MachineClass=0D machine: Make smp_parse generic enough for all arches=0D machine: Tweak the order of topology members in struct CpuTopology=0D machine: Use ms instead of global current_machine in sanity-check=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/bb4aa8f59e18...5f992102383e= =0D From MAILER-DAEMON Fri Oct 01 20:38:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mWT2X-0006BW-D7 for mharc-qemu-commits@gnu.org; Fri, 01 Oct 2021 20:38:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWT2V-0006BI-4G for qemu-commits@nongnu.org; Fri, 01 Oct 2021 20:38:07 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:52753 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWT2Q-00072y-4E for qemu-commits@nongnu.org; Fri, 01 Oct 2021 20:38:06 -0400 Received: from github.com (hubbernetes-node-aea12a0.va3-iad.github.net [10.48.206.70]) by smtp.github.com (Postfix) with ESMTPA id 051915C0844 for ; Fri, 1 Oct 2021 17:38:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633135081; bh=NGeQxhnvHjgiK+M7zeH1szPQGry47AGcGEVP6f17HV4=; h=Date:From:To:Subject:From; b=tcdEYtDK+pa43vi+QBA+pZmZrpgqhazdsxA9UemTK/sX9WgeXSZ/UEL9MeIVNC6PU ZGWzOSEz4IrYTwV2s+Bl/33QBYqb8VwhQ0Uhq2gul9v0CSrBdeZxDW14qsNnVMeIRR KM0fW248c/i8fMUeyc2jajWCgjbAZkaJ8Wbfdv4E= Date: Fri, 01 Oct 2021 17:38:01 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7237c7: qapi/machine: Fix an incorrect comment of SMPConfi... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Oct 2021 00:38:07 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 7237c7ce772794d6be10b8b987fe4d02dfd76562=0D https://github.com/qemu/qemu/commit/7237c7ce772794d6be10b8b987fe4d0= 2dfd76562=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M qapi/machine.json=0D =0D Log Message:=0D -----------=0D qapi/machine: Fix an incorrect comment of SMPConfiguration=0D =0D The explanation of @cores should be "number of cores per die" but=0D not "number of cores per thread". Let's fix it.=0D =0D Fixes: 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse")=0D Signed-off-by: Yanan Wang =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-2-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: c2511b1632e109130df524121dfb7d2413216d3c=0D https://github.com/qemu/qemu/commit/c2511b1632e109130df524121dfb7d2= 413216d3c=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M hw/core/machine.c=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Deprecate "parameter=3D0" SMP configurations=0D =0D In the SMP configuration, we should either provide a topology=0D parameter with a reasonable value (greater than zero) or just=0D omit it and QEMU will compute the missing value.=0D =0D The users shouldn't provide a configuration with any parameter=0D of it specified as zero (e.g. -smp 8,sockets=3D0) which could=0D possibly cause unexpected results in the -smp parsing. So we=0D deprecate this kind of configurations since 6.2 by adding the=0D explicit sanity check.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Cornelia Huck =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-3-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 5d8b5a505571b7927095015c805646f78fc56578=0D https://github.com/qemu/qemu/commit/5d8b5a505571b7927095015c805646f= 78fc56578=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Minor refactor/fix for the smp parsers=0D =0D To pave the way for the functional improvement in later patches,=0D make some refactor/cleanup for the smp parsers, including using=0D local maxcpus instead of ms->smp.max_cpus in the calculation,=0D defaulting dies to 0 initially like other members, cleanup the=0D sanity check for dies.=0D =0D We actually also fix a hidden defect by avoiding directly using=0D the provided *zero value* in the calculation, which could cause=0D a segment fault (e.g. using dies=3D0 in the calculation).=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-4-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9a52b508061163df4dae05e708cd2a9cd790ad04=0D https://github.com/qemu/qemu/commit/9a52b508061163df4dae05e708cd2a9= cd790ad04=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Uniformly use maxcpus to calculate the omitted parameters=0D =0D We are currently using maxcpus to calculate the omitted sockets=0D but using cpus to calculate the omitted cores/threads. This makes=0D cmdlines like:=0D -smp cpus=3D8,maxcpus=3D16=0D -smp cpus=3D8,cores=3D4,maxcpus=3D16=0D -smp cpus=3D8,threads=3D2,maxcpus=3D16=0D work fine but the ones like:=0D -smp cpus=3D8,sockets=3D2,maxcpus=3D16=0D -smp cpus=3D8,sockets=3D2,cores=3D4,maxcpus=3D16=0D -smp cpus=3D8,sockets=3D2,threads=3D2,maxcpus=3D16=0D break the sanity check.=0D =0D Since we require for a valid config that the product of "sockets * cores=0D= * threads" should equal to the maxcpus, we should uniformly use maxcpus=0D= to calculate their omitted values.=0D =0D Also the if-branch of "cpus =3D=3D 0 || sockets =3D=3D 0" was split into = two=0D branches of "cpus =3D=3D 0" and "sockets =3D=3D 0" so that we can clearly= read=0D that we are parsing the configuration with a preference on cpus over=0D sockets over cores over threads.=0D =0D Note: change in this patch won't affect any existing working cmdlines=0D but improves consistency and allows more incomplete configs to be valid.=0D= =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-5-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7d8c5a39628820f6927b8b70c8f54872f5d1a196=0D https://github.com/qemu/qemu/commit/7d8c5a39628820f6927b8b70c8f5487= 2f5d1a196=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Set the value of cpus to match maxcpus if it's omitted=0D =0D Currently we directly calculate the omitted cpus based on the given=0D incomplete collection of parameters. This makes some cmdlines like:=0D -smp maxcpus=3D16=0D -smp sockets=3D2,maxcpus=3D16=0D -smp sockets=3D2,dies=3D2,maxcpus=3D16=0D -smp sockets=3D2,cores=3D4,maxcpus=3D16=0D not work. We should probably set the value of cpus to match maxcpus=0D if it's omitted, which will make above configs start to work.=0D =0D So the calculation logic of cpus/maxcpus after this patch will be:=0D When both maxcpus and cpus are omitted, maxcpus will be calculated=0D from the given parameters and cpus will be set equal to maxcpus.=0D When only one of maxcpus and cpus is given then the omitted one=0D will be set to its counterpart's value. Both maxcpus and cpus may=0D be specified, but maxcpus must be equal to or greater than cpus.=0D =0D Note: change in this patch won't affect any existing working cmdlines=0D but allows more incomplete configs to be valid.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-6-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 52082d3ba4e81bf9df23d3cd5ddfb2a620e9b267=0D https://github.com/qemu/qemu/commit/52082d3ba4e81bf9df23d3cd5ddfb2a= 620e9b267=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D =0D Log Message:=0D -----------=0D machine: Improve the error reporting of smp parsing=0D =0D We have two requirements for a valid SMP configuration:=0D the product of "sockets * cores * threads" must represent all the=0D possible cpus, i.e., max_cpus, and then must include the initially=0D present cpus, i.e., smp_cpus.=0D =0D So we only need to ensure 1) "sockets * cores * threads =3D=3D maxcpus"=0D= at first and then ensure 2) "maxcpus >=3D cpus". With a reasonable=0D order of the sanity check, we can simplify the error reporting code.=0D When reporting an error message we also report the exact value of=0D each topology member to make users easily see what's going on.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-7-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: afc8e9aaa7915ebfe1af8eba6994a38b3e556ba9=0D https://github.com/qemu/qemu/commit/afc8e9aaa7915ebfe1af8eba6994a38= b3e556ba9=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D qtest/numa-test: Use detailed -smp CLIs in pc_dynamic_cpu_cfg=0D =0D Since commit 80d7835749 (qemu-options: rewrite help for -smp options),=0D= the preference of sockets/cores in -smp parsing is considered liable=0D to change, and actually we are going to change it in a coming commit.=0D So it'll be more stable to use detailed -smp CLIs in testing if we=0D have strong dependency on the parsing results.=0D =0D pc_dynamic_cpu_cfg currently assumes/needs that there will be 2 CPU=0D sockets with "-smp 2". To avoid breaking the test because of parsing=0D logic change, now explicitly use "-smp 2,sockets=3D2".=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-8-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bbb0c0ec6da8a739b02fbff941b44afc5513d6e4=0D https://github.com/qemu/qemu/commit/bbb0c0ec6da8a739b02fbff941b44af= c5513d6e4=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D qtest/numa-test: Use detailed -smp CLIs in test_def_cpu_split=0D =0D Since commit 80d7835749 (qemu-options: rewrite help for -smp options),=0D= the preference of sockets/cores in -smp parsing is considered liable=0D to change, and actually we are going to change it in a coming commit.=0D So it'll be more stable to use detailed -smp CLIs in the testcases=0D that have strong dependency on the parsing results.=0D =0D Currently, test_def_cpu_split use "-smp 8" and will get 8 CPU sockets=0D based on current parsing rule. But if we change to prefer cores over=0D sockets we will get one CPU socket with 8 cores, and this testcase=0D will not get expected numa set by default on x86_64 (Ok on aarch64).=0D =0D So now explicitly use "-smp 8,sockets=3D8" to avoid affect from parsing=0D= logic change.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-9-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4a0af2930a4e4f64ce551152fdb4b9e7be106408=0D https://github.com/qemu/qemu/commit/4a0af2930a4e4f64ce551152fdb4b9e= 7be106408=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D machine: Prefer cores over sockets in smp parsing since 6.2=0D =0D In the real SMP hardware topology world, it's much more likely that=0D we have high cores-per-socket counts and few sockets totally. While=0D the current preference of sockets over cores in smp parsing results=0D in a virtual cpu topology with low cores-per-sockets counts and a=0D large number of sockets, which is just contrary to the real world.=0D =0D Given that it is better to make the virtual cpu topology be more=0D reflective of the real world and also for the sake of compatibility,=0D we start to prefer cores over sockets over threads in smp parsing=0D since machine type 6.2 for different arches.=0D =0D In this patch, a boolean "smp_prefer_sockets" is added, and we only=0D enable the old preference on older machines and enable the new one=0D since type 6.2 for all arches by using the machine compat mechanism.=0D =0D Suggested-by: Daniel P. Berrange =0D Signed-off-by: Yanan Wang =0D Acked-by: David Gibson =0D Acked-by: Cornelia Huck =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-10-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69fc28a78dbff2d3414bbafce38320b4433ed583=0D https://github.com/qemu/qemu/commit/69fc28a78dbff2d3414bbafce38320b= 4433ed583=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Use ms instead of global current_machine in sanity-check=0D =0D In the sanity-check of smp_cpus and max_cpus against mc in function=0D machine_set_smp(), we are now using ms->smp.max_cpus for the check=0D but using current_machine->smp.max_cpus in the error message.=0D Tweak this by uniformly using the local ms.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Cornelia Huck =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-11-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 003f230e37d724ac52004d7f8270159da105780f=0D https://github.com/qemu/qemu/commit/003f230e37d724ac52004d7f8270159= da105780f=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Tweak the order of topology members in struct CpuTopology=0D =0D Now that all the possible topology parameters are integrated in struct=0D= CpuTopology, tweak the order of topology members to be "cpus/sockets/=0D dies/cores/threads/maxcpus" for readability and consistency. We also=0D tweak the comment by adding explanation of dies parameter.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929025816.21076-12-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e4a97a893bcd7511aba812969d1fa6fe42dc1931=0D https://github.com/qemu/qemu/commit/e4a97a893bcd7511aba812969d1fa6f= e42dc1931=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Make smp_parse generic enough for all arches=0D =0D Currently the only difference between smp_parse and pc_smp_parse=0D is the support of dies parameter and the related error reporting.=0D With some arch compat variables like "bool dies_supported", we can=0D make smp_parse generic enough for all arches and the PC specific=0D one can be removed.=0D =0D Making smp_parse() generic enough can reduce code duplication and=0D ease the code maintenance, and also allows extending the topology=0D with more arch specific members (e.g., clusters) in the future.=0D =0D Suggested-by: Andrew Jones =0D Suggested-by: Daniel P. Berrang=C3=A9 =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-13-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7687b2b3edc3f29ad58e8d6593d5c10dde406c34=0D https://github.com/qemu/qemu/commit/7687b2b3edc3f29ad58e8d6593d5c10= dde406c34=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Remove smp_parse callback from MachineClass=0D =0D Now we have a generic smp parser for all arches, and there will=0D not be any other arch specific ones, so let's remove the callback=0D from MachineClass and call the parser directly.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-14-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2b52619994ab48504c5fc0d32a1af24159405ce0=0D https://github.com/qemu/qemu/commit/2b52619994ab48504c5fc0d32a1af24= 159405ce0=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D =0D Log Message:=0D -----------=0D machine: Move smp_prefer_sockets to struct SMPCompatProps=0D =0D Now we have a common structure SMPCompatProps used to store information=0D= about SMP compatibility stuff, so we can also move smp_prefer_sockets=0D there for cleaner code.=0D =0D No functional change intended.=0D =0D Signed-off-by: Yanan Wang =0D Acked-by: David Gibson =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-15-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e7f944bb94a375e8ee7469ffa535ea6e11ce59e1=0D https://github.com/qemu/qemu/commit/e7f944bb94a375e8ee7469ffa535ea6= e11ce59e1=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Use g_autoptr in machine_set_smp=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8bdfec393a2ac67df9cecc0983d130db4a6bba58=0D https://github.com/qemu/qemu/commit/8bdfec393a2ac67df9cecc0983d130d= b4a6bba58=0D Author: Yanan Wang =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D =0D Log Message:=0D -----------=0D machine: Put all sanity-check in the generic SMP parser=0D =0D Put both sanity-check of the input SMP configuration and sanity-check=0D of the output SMP configuration uniformly in the generic parser. Then=0D machine_set_smp() will become cleaner, also all the invalid scenarios=0D can be tested only by calling the parser.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Pankaj Gupta =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210929025816.21076-16-wangyanan55@huawei.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 988f7b8bfeffbf521814d1e48c321f7674277512=0D https://github.com/qemu/qemu/commit/988f7b8bfeffbf521814d1e48c321f7= 674277512=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Support KVM_CAP_ENFORCE_PV_FEATURE_CPUID=0D =0D By default, KVM allows the guest to use all currently supported PV featur= es=0D even when they were not announced in guest visible CPUIDs. Introduce a ne= w=0D "kvm-pv-enforce-cpuid" flag to limit the supported feature set to the=0D exposed features. The feature is supported by Linux >=3D 5.10 and is not=0D= enabled by default in QEMU.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-4-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 70367f091777419f42e5f68f4206deb641335877=0D https://github.com/qemu/qemu/commit/70367f091777419f42e5f68f4206deb= 641335877=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Support KVM_CAP_HYPERV_ENFORCE_CPUID=0D =0D By default, KVM allows the guest to use all currently supported Hyper-V=0D= enlightenments when Hyper-V CPUID interface was exposed, regardless of if= =0D some features were not announced in guest visible CPUIDs. hv-enforce-cpui= d=0D feature alters this behavior and only allows the guest to use exposed=0D Hyper-V enlightenments. The feature is supported by Linux >=3D 5.14 and i= s=0D not enabled by default in QEMU.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-5-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 050716292a63f4969b32cac32b85774521738ef5=0D https://github.com/qemu/qemu/commit/050716292a63f4969b32cac32b85774= 521738ef5=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Move HV_APIC_ACCESS_RECOMMENDED bit setting to hyperv_fill_cpuids= ()=0D =0D In preparation to enabling Hyper-V + APICv/AVIC move=0D HV_APIC_ACCESS_RECOMMENDED setting out of kvm_hyperv_properties[]: the=0D= 'real' feature bit for the vAPIC features is HV_APIC_ACCESS_AVAILABLE,=0D= HV_APIC_ACCESS_RECOMMENDED is a recommendation to use the feature which=0D= we may not always want to give.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-6-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e1f9a8e8c90ae54387922e33e5ac4fd759747d01=0D https://github.com/qemu/qemu/commit/e1f9a8e8c90ae54387922e33e5ac4fd= 759747d01=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/hyperv-proto.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Implement pseudo 'hv-avic' ('hv-apicv') enlightenment=0D =0D The enlightenment allows to use Hyper-V SynIC with hardware APICv/AVIC=0D= enabled. Normally, Hyper-V SynIC disables these hardware features and=0D suggests the guest to use paravirtualized AutoEOI feature. Linux-4.15=0D gains support for conditional APICv/AVIC disablement, the feature=0D stays on until the guest tries to use AutoEOI feature with SynIC. With=0D= 'HV_DEPRECATING_AEOI_RECOMMENDED' bit exposed, modern enough Windows/=0D Hyper-V versions should follow the recommendation and not use the=0D (unwanted) feature.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-7-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: af7228b88dbe80ed5d5258b49be8b48ab351a476=0D https://github.com/qemu/qemu/commit/af7228b88dbe80ed5d5258b49be8b48= ab351a476=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/kvm.c=0D =0D Log Message:=0D -----------=0D i386: Make Hyper-V version id configurable=0D =0D Currently, we hardcode Hyper-V version id (CPUID 0x40000002) to=0D WS2008R2 and it is known that certain tools in Windows check this. It=0D seems useful to provide some flexibility by making it possible to change=0D= this info at will. CPUID information is defined in TLFS as:=0D =0D EAX: Build Number=0D EBX Bits 31-16: Major Version=0D Bits 15-0: Minor Version=0D ECX Service Pack=0D EDX Bits 31-24: Service Branch=0D Bits 23-0: Service Number=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-8-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f701ecec2bbaae2d04985eba87924a7329534e9a=0D https://github.com/qemu/qemu/commit/f701ecec2bbaae2d04985eba87924a7= 329534e9a=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/hyperv.txt=0D M hw/i386/pc.c=0D M target/i386/cpu.c=0D =0D Log Message:=0D -----------=0D i386: Change the default Hyper-V version to match WS2016=0D =0D KVM implements some Hyper-V 2016 functions so providing WS2008R2 version=0D= is somewhat incorrect. While generally guests shouldn't care about it=0D and always check feature bits, it is known that some tools in Windows=0D actually check version info.=0D =0D For compatibility reasons make the change for 6.2 machine types only.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20210902093530.345756-9-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bcfdfae78f111fa3c0f81b2708098a545201bb68=0D https://github.com/qemu/qemu/commit/bcfdfae78f111fa3c0f81b2708098a5= 45201bb68=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D R docs/devel/ci-definitions.rst=0D A docs/devel/ci-definitions.rst.inc=0D R docs/devel/ci-jobs.rst=0D A docs/devel/ci-jobs.rst.inc=0D R docs/devel/ci-runners.rst=0D A docs/devel/ci-runners.rst.inc=0D M docs/devel/ci.rst=0D =0D Log Message:=0D -----------=0D docs: name included files ".rst.inc"=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f9df7aac758fed5cc2fb9210ad0edba79434aeed=0D https://github.com/qemu/qemu/commit/f9df7aac758fed5cc2fb9210ad0edba= 79434aeed=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/multi-process.rst=0D =0D Log Message:=0D -----------=0D docs: move notes inside the body of the document=0D =0D Make all documents start with a heading.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8b8939e44fc8315885598a9e1ee8deeea3b68a96=0D https://github.com/qemu/qemu/commit/8b8939e44fc8315885598a9e1ee8dee= ea3b68a96=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/build-system.rst=0D =0D Log Message:=0D -----------=0D docs: put "make" information together in build-system.rst=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 768f14f94ec50fe57a3964fff75d8b3456b588b5=0D https://github.com/qemu/qemu/commit/768f14f94ec50fe57a3964fff75d8b3= 456b588b5=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qgraph.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize qgraph.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~, and move the comman= d line=0D building near to the other execution steps.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e9adb4ace229dfa742176e9ddb629dbb6a6081bc=0D https://github.com/qemu/qemu/commit/e9adb4ace229dfa742176e9ddb629db= b6a6081bc=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/tcg-plugins.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize tcg-plugins.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~, and create a new "w= riting=0D plugins" section.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9fce3601761779f14d8d1ea32e2b6abf2f704edb=0D https://github.com/qemu/qemu/commit/9fce3601761779f14d8d1ea32e2b6ab= f2f704edb=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/testing.rst=0D =0D Log Message:=0D -----------=0D docs: move gcov section at the end of testing.rst=0D =0D gcov testing applies to all tests, not just make check. Move it=0D out of the make check section.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 16e79e1b01a698908e14eda3078d4a8e7b1b9c2b=0D https://github.com/qemu/qemu/commit/16e79e1b01a698908e14eda3078d4a8= e7b1b9c2b=0D Author: Paolo Bonzini =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/testing.rst=0D =0D Log Message:=0D -----------=0D docs: reorganize testing.rst=0D =0D Clean up the heading levels to use =3D=3D=3D --- ~~~ ^^^ '''. Reorganize= the=0D outline for the Avocado part, and always include headings for the=0D class names.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 5f992102383ed8ed97076548e1c897c7034ed8a4=0D https://github.com/qemu/qemu/commit/5f992102383ed8ed97076548e1c897c= 7034ed8a4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/build-system.rst=0D R docs/devel/ci-definitions.rst=0D A docs/devel/ci-definitions.rst.inc=0D R docs/devel/ci-jobs.rst=0D A docs/devel/ci-jobs.rst.inc=0D R docs/devel/ci-runners.rst=0D A docs/devel/ci-runners.rst.inc=0D M docs/devel/ci.rst=0D M docs/devel/multi-process.rst=0D M docs/devel/qgraph.rst=0D M docs/devel/tcg-plugins.rst=0D M docs/devel/testing.rst=0D M docs/hyperv.txt=0D M hw/arm/virt.c=0D M hw/core/machine.c=0D M hw/i386/pc.c=0D M hw/i386/pc_piix.c=0D M hw/i386/pc_q35.c=0D M hw/ppc/spapr.c=0D M hw/s390x/s390-virtio-ccw.c=0D M include/hw/boards.h=0D M qapi/machine.json=0D M qemu-options.hx=0D M target/i386/cpu.c=0D M target/i386/cpu.h=0D M target/i386/kvm/hyperv-proto.h=0D M target/i386/kvm/kvm.c=0D M tests/qtest/numa-test.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * -smp cleanpus=0D * Hyper-V englightenment functionality=0D * Documentation cleanups=0D =0D # gpg: Signature made Fri 01 Oct 2021 01:11:00 PM EDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (29 commits)=0D docs: reorganize testing.rst=0D docs: move gcov section at the end of testing.rst=0D docs: reorganize tcg-plugins.rst=0D docs: reorganize qgraph.rst=0D docs: put "make" information together in build-system.rst=0D docs: move notes inside the body of the document=0D docs: name included files ".rst.inc"=0D i386: Change the default Hyper-V version to match WS2016=0D i386: Make Hyper-V version id configurable=0D i386: Implement pseudo 'hv-avic' ('hv-apicv') enlightenment=0D i386: Move HV_APIC_ACCESS_RECOMMENDED bit setting to hyperv_fill_cpuids= ()=0D i386: Support KVM_CAP_HYPERV_ENFORCE_CPUID=0D i386: Support KVM_CAP_ENFORCE_PV_FEATURE_CPUID=0D machine: Put all sanity-check in the generic SMP parser=0D machine: Use g_autoptr in machine_set_smp=0D machine: Move smp_prefer_sockets to struct SMPCompatProps=0D machine: Remove smp_parse callback from MachineClass=0D machine: Make smp_parse generic enough for all arches=0D machine: Tweak the order of topology members in struct CpuTopology=0D machine: Use ms instead of global current_machine in sanity-check=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/bb4aa8f59e18...5f992102383e= =0D From MAILER-DAEMON Sat Oct 02 09:13:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mWepn-0006FF-GC for mharc-qemu-commits@gnu.org; Sat, 02 Oct 2021 09:13:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWepk-0006AJ-A0 for qemu-commits@nongnu.org; Sat, 02 Oct 2021 09:13:44 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:58259) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWeph-00062D-ET for qemu-commits@nongnu.org; Sat, 02 Oct 2021 09:13:43 -0400 Received: from github.com (hubbernetes-node-4a7d9e9.ac4-iad.github.net [10.52.125.72]) by smtp.github.com (Postfix) with ESMTPA id D8229600384 for ; Sat, 2 Oct 2021 06:13:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633180419; bh=hEA5l5KjmkRC2iZWHIjtPfhQ6dEMz3YZU50X/J/juao=; h=Date:From:To:Subject:From; b=Smdh5HJUJ3CuLfC/LquzBszzgRiUWo5bCIE51JEZ03Wt6QUdRlLj+676GPCjO9gG8 DGvVXFxnnHTnBMAeccBaukHWVsz/DIQI8z4w7NHp2ctWPW4rW9CAk6FdoiDJuEnGrx ASWDLbRBu6mfbYiCIXdthNXzgQUBhAezKfVVS+Wo= Date: Sat, 02 Oct 2021 06:13:39 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 1c0091: qapi/pylintrc: ignore 'consider-using-f-string' wa... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Oct 2021 13:13:44 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 1c00917409c9604cfc587045ba37395a48337dff https://github.com/qemu/qemu/commit/1c00917409c9604cfc587045ba37395a48337dff Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/pylintrc Log Message: ----------- qapi/pylintrc: ignore 'consider-using-f-string' warning Pylint 2.11.x adds this warning. We're not yet ready to pursue that conversion, so silence it for now. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-2-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 2adb988ed4ca31813d237c475a6a327ef16c5432 https://github.com/qemu/qemu/commit/2adb988ed4ca31813d237c475a6a327ef16c5432 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/gen.py Log Message: ----------- qapi/gen: use dict.items() to iterate over _modules New pylint warning. I could silence it, but this is the only occurrence in the entire tree, including everything in iotests/ and python/. Easier to just change this one instance. (The warning is emitted in cases where you are fetching the values anyway, so you may as well just take advantage of the iterator to avoid redundant lookups.) Signed-off-by: John Snow Message-Id: <20210930205716.1148693-3-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 012336a152641b264a65176a388a7fb0118e1781 https://github.com/qemu/qemu/commit/012336a152641b264a65176a388a7fb0118e1781 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py M tests/qapi-schema/doc-bad-feature.err Log Message: ----------- qapi/parser: fix unused check_args_section arguments Pylint informs us we're not using these arguments. Oops, it's right. Correct the error message and remove the remaining unused parameter. Fix test output now that the error message is improved. Fixes: e151941d1b Signed-off-by: John Snow Message-Id: <20210930205716.1148693-4-jsnow@redhat.com> [Commit message formatting tweaked] Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: a9e2eb06ed061f37c3ba6ad52722eef20afd713a https://github.com/qemu/qemu/commit/a9e2eb06ed061f37c3ba6ad52722eef20afd713a Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M qapi/block-core.json M qga/qapi-schema.json M tests/qapi-schema/doc-good.json Log Message: ----------- qapi: Add spaces after symbol declaration for consistency Several QGA definitions omit a blank line after the symbol declaration. This works OK currently, but it's the only place where we do this. Adjust it for consistency. Future commits may wind up enforcing this formatting. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-5-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: cd87c14cde5db42a2f13bfdbba1f3cbeb347a411 https://github.com/qemu/qemu/commit/cd87c14cde5db42a2f13bfdbba1f3cbeb347a411 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py M tests/qapi-schema/doc-empty-symbol.err Log Message: ----------- qapi/parser: remove FIXME comment from _append_body_line True, we do not check the validity of this symbol -- but we don't check the validity of definition names during parse, either -- that happens later, during the expr check. I don't want to introduce a dependency on expr.py:check_name_str here and introduce a cycle. Instead, rest assured that a documentation block is required for each definition. This requirement uses the names of each section to ensure that we fulfilled this requirement. e.g., let's say that block-core.json has a comment block for "Snapshot!Info" by accident. We'll see this error message: In file included from ../../qapi/block.json:8: ../../qapi/block-core.json: In struct 'SnapshotInfo': ../../qapi/block-core.json:38: documentation comment is for 'Snapshot!Info' That's a pretty decent error message. Now, let's say that we actually mangle it twice, identically: ../../qapi/block-core.json: In struct 'Snapshot!Info': ../../qapi/block-core.json:38: struct has an invalid name That's also pretty decent. If we forget to fix it in both places, we'll just be back to the first error. Therefore, let's just drop this FIXME and adjust the error message to not imply a more thorough check than is actually performed. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-6-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 1e20a77576dedf1489ce1cdb6abc4b34663637a4 https://github.com/qemu/qemu/commit/1e20a77576dedf1489ce1cdb6abc4b34663637a4 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: clarify _end_section() logic The "if self._section" clause in end_section is mysterious: In which circumstances might we end a section when we don't have one? QAPIDoc always expects there to be a "current section", only except after a call to end_comment(). This actually *shouldn't* ever be 'None', so let's remove that logic so I don't wonder why it's like this again in three months. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-7-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: f4c05aaf148a44d80855eb45b9342feaeeb4764a https://github.com/qemu/qemu/commit/f4c05aaf148a44d80855eb45b9342feaeeb4764a Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Introduce NullSection Here's the weird bit. QAPIDoc generally expects -- virtually everywhere -- that it will always have a current section. The sole exception to this is in the case that end_comment() is called, which leaves us with *no* section. However, in this case, we also don't expect to actually ever mutate the comment contents ever again. NullSection is just a Null-object that allows us to maintain the invariant that we *always* have a current section, enforced by static typing -- allowing us to type that field as QAPIDoc.Section instead of the more ambiguous Optional[QAPIDoc.Section]. end_section is renamed to switch_section and now accepts as an argument the new section to activate, clarifying that no callers ever just unilaterally end a section; they only do so when starting a new section. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-8-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: e7ac60fcd0623fe255f54c33f2bed2e7b2f780f5 https://github.com/qemu/qemu/commit/e7ac60fcd0623fe255f54c33f2bed2e7b2f780f5 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: add import cycle workaround Adding static types causes a cycle in the QAPI generator: [schema -> expr -> parser -> schema]. It exists because the QAPIDoc class needs the names of types defined by the schema module, but the schema module needs to import both expr.py/parser.py to do its actual parsing. Ultimately, the layering violation is that parser.py should not have any knowledge of specifics of the Schema. QAPIDoc performs double-duty here both as a parser *and* as a finalized object that is part of the schema. In this patch, add the offending type hints alongside the workaround to avoid the cycle becoming a problem at runtime. See https://mypy.readthedocs.io/en/latest/runtime_troubles.html#import-cycles for more information on this workaround technique. I see three ultimate resolutions here: (1) Just keep this patch and use the TYPE_CHECKING trick to eliminate the cycle which is only present during static analysis. (2) Don't bother to annotate connect_member() et al, give them 'object' or 'Any'. I don't particularly like this, because it diminishes the usefulness of type hints for documentation purposes. Still, it's an extremely quick fix. (3) Reimplement doc <--> definition correlation directly in schema.py, integrating doc fields directly into QAPISchemaMember and relieving the QAPIDoc class of the responsibility. Users of the information would instead visit the members first and retrieve their documentation instead of the inverse operation -- visiting the documentation and retrieving their members. My preference is (3), but in the short-term (1) is the easiest way to have my cake (strong type hints) and eat it too (Not have import cycles). Do (1) for now, but plan for (3). Signed-off-by: John Snow Message-Id: <20210930205716.1148693-9-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 5f0d9f3bc762fcbb1637b5e257c9cd8b9a8aa9ab https://github.com/qemu/qemu/commit/5f0d9f3bc762fcbb1637b5e257c9cd8b9a8aa9ab Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: add type hint annotations (QAPIDoc) Annotations do not change runtime behavior. This commit consists of only annotations. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-10-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 15acf48cfed15b37771922093693007d1ad09219 https://github.com/qemu/qemu/commit/15acf48cfed15b37771922093693007d1ad09219 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Add FIXME for consolidating JSON-related types The fix for this comment is forthcoming in a future commit, but this will keep me honest. The linting configuration in ./python/setup.cfg prohibits 'FIXME' comments. A goal of this long-running series is to move ./scripts/qapi to ./python/qemu/qapi so that the QAPI generator is regularly type-checked by GitLab CI. This comment is a time-bomb to force me to address this issue prior to that step. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-11-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 2e28283e419357f0ee03a33a9224f908f9f67b04 https://github.com/qemu/qemu/commit/2e28283e419357f0ee03a33a9224f908f9f67b04 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/mypy.ini Log Message: ----------- qapi/parser: enable mypy checks Signed-off-by: John Snow Message-Id: <20210930205716.1148693-12-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 18e3673e0f8479e392e55245ad70c1eedb383507 https://github.com/qemu/qemu/commit/18e3673e0f8479e392e55245ad70c1eedb383507 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Silence too-few-public-methods warning Eh. Not worth the fuss today. There are bigger fish to fry. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-13-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: d183e0481b1510b253ac94e702c76115f3bb6450 https://github.com/qemu/qemu/commit/d183e0481b1510b253ac94e702c76115f3bb6450 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/pylintrc Log Message: ----------- qapi/parser: enable pylint checks Signed-off-by: John Snow Message-Id: <20210930205716.1148693-14-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: f50ecf548c7313c27037f7b7fb8ecc5a5e89249c https://github.com/qemu/qemu/commit/f50ecf548c7313c27037f7b7fb8ecc5a5e89249c Author: Richard Henderson Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M qapi/block-core.json M qga/qapi-schema.json M scripts/qapi/gen.py M scripts/qapi/mypy.ini M scripts/qapi/parser.py M scripts/qapi/pylintrc M tests/qapi-schema/doc-bad-feature.err M tests/qapi-schema/doc-empty-symbol.err M tests/qapi-schema/doc-good.json Log Message: ----------- Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-02' into staging QAPI patches patches for 2021-10-02 # gpg: Signature made Sat 02 Oct 2021 01:37:11 AM EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster " [full] # gpg: aka "Markus Armbruster " [full] * remotes/armbru/tags/pull-qapi-2021-10-02: qapi/parser: enable pylint checks qapi/parser: Silence too-few-public-methods warning qapi/parser: enable mypy checks qapi/parser: Add FIXME for consolidating JSON-related types qapi/parser: add type hint annotations (QAPIDoc) qapi/parser: add import cycle workaround qapi/parser: Introduce NullSection qapi/parser: clarify _end_section() logic qapi/parser: remove FIXME comment from _append_body_line qapi: Add spaces after symbol declaration for consistency qapi/parser: fix unused check_args_section arguments qapi/gen: use dict.items() to iterate over _modules qapi/pylintrc: ignore 'consider-using-f-string' warning Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/5f992102383e...f50ecf548c73 From MAILER-DAEMON Sat Oct 02 16:31:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mWlfb-0006wD-Ei for mharc-qemu-commits@gnu.org; Sat, 02 Oct 2021 16:31:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWlfa-0006sJ-B5 for qemu-commits@nongnu.org; Sat, 02 Oct 2021 16:31:42 -0400 Received: from out-19.smtp.github.com ([192.30.252.202]:46343) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mWlfW-0000jp-M6 for qemu-commits@nongnu.org; Sat, 02 Oct 2021 16:31:41 -0400 Received: from github.com (hubbernetes-node-8c42859.va3-iad.github.net [10.48.206.76]) by smtp.github.com (Postfix) with ESMTPA id BB387E0407 for ; Sat, 2 Oct 2021 13:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633206697; bh=oJIJCL3UW0UsAb7V5RzOGk7ePzgYl+hQfTUmxqt5EwA=; h=Date:From:To:Subject:From; b=S/XOzDIvtIg+B/7f8luKsldsdhD4i0P0cFnNuVhvmFeqZnexRL5s2O2k2FOECZ2GZ hCUVFce44bxEUTRDVAluiseKy+Uq3ElLdlznF5/5y5pswk91wURcUXzGughJ3q6l6z 2y+YD36AMCpEK/TpuH+eJ6nO/23RMs8NjKUVsk9o= Date: Sat, 02 Oct 2021 13:31:37 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.202; envelope-from=noreply@github.com; helo=out-19.smtp.github.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 1c0091: qapi/pylintrc: ignore 'consider-using-f-string' wa... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Oct 2021 20:31:42 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: 1c00917409c9604cfc587045ba37395a48337dff https://github.com/qemu/qemu/commit/1c00917409c9604cfc587045ba37395a48337dff Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/pylintrc Log Message: ----------- qapi/pylintrc: ignore 'consider-using-f-string' warning Pylint 2.11.x adds this warning. We're not yet ready to pursue that conversion, so silence it for now. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-2-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 2adb988ed4ca31813d237c475a6a327ef16c5432 https://github.com/qemu/qemu/commit/2adb988ed4ca31813d237c475a6a327ef16c5432 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/gen.py Log Message: ----------- qapi/gen: use dict.items() to iterate over _modules New pylint warning. I could silence it, but this is the only occurrence in the entire tree, including everything in iotests/ and python/. Easier to just change this one instance. (The warning is emitted in cases where you are fetching the values anyway, so you may as well just take advantage of the iterator to avoid redundant lookups.) Signed-off-by: John Snow Message-Id: <20210930205716.1148693-3-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 012336a152641b264a65176a388a7fb0118e1781 https://github.com/qemu/qemu/commit/012336a152641b264a65176a388a7fb0118e1781 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py M tests/qapi-schema/doc-bad-feature.err Log Message: ----------- qapi/parser: fix unused check_args_section arguments Pylint informs us we're not using these arguments. Oops, it's right. Correct the error message and remove the remaining unused parameter. Fix test output now that the error message is improved. Fixes: e151941d1b Signed-off-by: John Snow Message-Id: <20210930205716.1148693-4-jsnow@redhat.com> [Commit message formatting tweaked] Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: a9e2eb06ed061f37c3ba6ad52722eef20afd713a https://github.com/qemu/qemu/commit/a9e2eb06ed061f37c3ba6ad52722eef20afd713a Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M qapi/block-core.json M qga/qapi-schema.json M tests/qapi-schema/doc-good.json Log Message: ----------- qapi: Add spaces after symbol declaration for consistency Several QGA definitions omit a blank line after the symbol declaration. This works OK currently, but it's the only place where we do this. Adjust it for consistency. Future commits may wind up enforcing this formatting. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-5-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: cd87c14cde5db42a2f13bfdbba1f3cbeb347a411 https://github.com/qemu/qemu/commit/cd87c14cde5db42a2f13bfdbba1f3cbeb347a411 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py M tests/qapi-schema/doc-empty-symbol.err Log Message: ----------- qapi/parser: remove FIXME comment from _append_body_line True, we do not check the validity of this symbol -- but we don't check the validity of definition names during parse, either -- that happens later, during the expr check. I don't want to introduce a dependency on expr.py:check_name_str here and introduce a cycle. Instead, rest assured that a documentation block is required for each definition. This requirement uses the names of each section to ensure that we fulfilled this requirement. e.g., let's say that block-core.json has a comment block for "Snapshot!Info" by accident. We'll see this error message: In file included from ../../qapi/block.json:8: ../../qapi/block-core.json: In struct 'SnapshotInfo': ../../qapi/block-core.json:38: documentation comment is for 'Snapshot!Info' That's a pretty decent error message. Now, let's say that we actually mangle it twice, identically: ../../qapi/block-core.json: In struct 'Snapshot!Info': ../../qapi/block-core.json:38: struct has an invalid name That's also pretty decent. If we forget to fix it in both places, we'll just be back to the first error. Therefore, let's just drop this FIXME and adjust the error message to not imply a more thorough check than is actually performed. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-6-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 1e20a77576dedf1489ce1cdb6abc4b34663637a4 https://github.com/qemu/qemu/commit/1e20a77576dedf1489ce1cdb6abc4b34663637a4 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: clarify _end_section() logic The "if self._section" clause in end_section is mysterious: In which circumstances might we end a section when we don't have one? QAPIDoc always expects there to be a "current section", only except after a call to end_comment(). This actually *shouldn't* ever be 'None', so let's remove that logic so I don't wonder why it's like this again in three months. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-7-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: f4c05aaf148a44d80855eb45b9342feaeeb4764a https://github.com/qemu/qemu/commit/f4c05aaf148a44d80855eb45b9342feaeeb4764a Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Introduce NullSection Here's the weird bit. QAPIDoc generally expects -- virtually everywhere -- that it will always have a current section. The sole exception to this is in the case that end_comment() is called, which leaves us with *no* section. However, in this case, we also don't expect to actually ever mutate the comment contents ever again. NullSection is just a Null-object that allows us to maintain the invariant that we *always* have a current section, enforced by static typing -- allowing us to type that field as QAPIDoc.Section instead of the more ambiguous Optional[QAPIDoc.Section]. end_section is renamed to switch_section and now accepts as an argument the new section to activate, clarifying that no callers ever just unilaterally end a section; they only do so when starting a new section. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-8-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: e7ac60fcd0623fe255f54c33f2bed2e7b2f780f5 https://github.com/qemu/qemu/commit/e7ac60fcd0623fe255f54c33f2bed2e7b2f780f5 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: add import cycle workaround Adding static types causes a cycle in the QAPI generator: [schema -> expr -> parser -> schema]. It exists because the QAPIDoc class needs the names of types defined by the schema module, but the schema module needs to import both expr.py/parser.py to do its actual parsing. Ultimately, the layering violation is that parser.py should not have any knowledge of specifics of the Schema. QAPIDoc performs double-duty here both as a parser *and* as a finalized object that is part of the schema. In this patch, add the offending type hints alongside the workaround to avoid the cycle becoming a problem at runtime. See https://mypy.readthedocs.io/en/latest/runtime_troubles.html#import-cycles for more information on this workaround technique. I see three ultimate resolutions here: (1) Just keep this patch and use the TYPE_CHECKING trick to eliminate the cycle which is only present during static analysis. (2) Don't bother to annotate connect_member() et al, give them 'object' or 'Any'. I don't particularly like this, because it diminishes the usefulness of type hints for documentation purposes. Still, it's an extremely quick fix. (3) Reimplement doc <--> definition correlation directly in schema.py, integrating doc fields directly into QAPISchemaMember and relieving the QAPIDoc class of the responsibility. Users of the information would instead visit the members first and retrieve their documentation instead of the inverse operation -- visiting the documentation and retrieving their members. My preference is (3), but in the short-term (1) is the easiest way to have my cake (strong type hints) and eat it too (Not have import cycles). Do (1) for now, but plan for (3). Signed-off-by: John Snow Message-Id: <20210930205716.1148693-9-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 5f0d9f3bc762fcbb1637b5e257c9cd8b9a8aa9ab https://github.com/qemu/qemu/commit/5f0d9f3bc762fcbb1637b5e257c9cd8b9a8aa9ab Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: add type hint annotations (QAPIDoc) Annotations do not change runtime behavior. This commit consists of only annotations. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-10-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 15acf48cfed15b37771922093693007d1ad09219 https://github.com/qemu/qemu/commit/15acf48cfed15b37771922093693007d1ad09219 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Add FIXME for consolidating JSON-related types The fix for this comment is forthcoming in a future commit, but this will keep me honest. The linting configuration in ./python/setup.cfg prohibits 'FIXME' comments. A goal of this long-running series is to move ./scripts/qapi to ./python/qemu/qapi so that the QAPI generator is regularly type-checked by GitLab CI. This comment is a time-bomb to force me to address this issue prior to that step. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-11-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 2e28283e419357f0ee03a33a9224f908f9f67b04 https://github.com/qemu/qemu/commit/2e28283e419357f0ee03a33a9224f908f9f67b04 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/mypy.ini Log Message: ----------- qapi/parser: enable mypy checks Signed-off-by: John Snow Message-Id: <20210930205716.1148693-12-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: 18e3673e0f8479e392e55245ad70c1eedb383507 https://github.com/qemu/qemu/commit/18e3673e0f8479e392e55245ad70c1eedb383507 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/parser.py Log Message: ----------- qapi/parser: Silence too-few-public-methods warning Eh. Not worth the fuss today. There are bigger fish to fry. Signed-off-by: John Snow Message-Id: <20210930205716.1148693-13-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: d183e0481b1510b253ac94e702c76115f3bb6450 https://github.com/qemu/qemu/commit/d183e0481b1510b253ac94e702c76115f3bb6450 Author: John Snow Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M scripts/qapi/pylintrc Log Message: ----------- qapi/parser: enable pylint checks Signed-off-by: John Snow Message-Id: <20210930205716.1148693-14-jsnow@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster Commit: f50ecf548c7313c27037f7b7fb8ecc5a5e89249c https://github.com/qemu/qemu/commit/f50ecf548c7313c27037f7b7fb8ecc5a5e89249c Author: Richard Henderson Date: 2021-10-02 (Sat, 02 Oct 2021) Changed paths: M qapi/block-core.json M qga/qapi-schema.json M scripts/qapi/gen.py M scripts/qapi/mypy.ini M scripts/qapi/parser.py M scripts/qapi/pylintrc M tests/qapi-schema/doc-bad-feature.err M tests/qapi-schema/doc-empty-symbol.err M tests/qapi-schema/doc-good.json Log Message: ----------- Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-02' into staging QAPI patches patches for 2021-10-02 # gpg: Signature made Sat 02 Oct 2021 01:37:11 AM EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster " [full] # gpg: aka "Markus Armbruster " [full] * remotes/armbru/tags/pull-qapi-2021-10-02: qapi/parser: enable pylint checks qapi/parser: Silence too-few-public-methods warning qapi/parser: enable mypy checks qapi/parser: Add FIXME for consolidating JSON-related types qapi/parser: add type hint annotations (QAPIDoc) qapi/parser: add import cycle workaround qapi/parser: Introduce NullSection qapi/parser: clarify _end_section() logic qapi/parser: remove FIXME comment from _append_body_line qapi: Add spaces after symbol declaration for consistency qapi/parser: fix unused check_args_section arguments qapi/gen: use dict.items() to iterate over _modules qapi/pylintrc: ignore 'consider-using-f-string' warning Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/5f992102383e...f50ecf548c73 From MAILER-DAEMON Sun Oct 03 08:46:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mX0sa-0007XD-8C for mharc-qemu-commits@gnu.org; Sun, 03 Oct 2021 08:46:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mX0sY-0007X5-Rb for qemu-commits@nongnu.org; Sun, 03 Oct 2021 08:46:06 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:44607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mX0sW-0001ve-4G for qemu-commits@nongnu.org; Sun, 03 Oct 2021 08:46:06 -0400 Received: from github.com (hubbernetes-node-1056f2a.ac4-iad.github.net [10.52.200.51]) by smtp.github.com (Postfix) with ESMTPA id 3A5C060079D for ; Sun, 3 Oct 2021 05:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633265163; bh=DP74hbcvxDq/oIffOkGhcLoW9vdPM80qZ+D/9OycFPk=; h=Date:From:To:Subject:From; b=SrW4899BE/lGl/TD3wPmhCcM6sywfupfM4C+yQ8NNrV2SSnBYszzgL4Z6kwEELfEL MWv4tAEq7G5dqEIVlW0oevax9P3Q9MVF7U2+Vri7Hexsvd2yIO1piFIDsLqq+k003I bBbKI5C/ALSevQr4/aqO6EeaCETQEdarltdgxO+0= Date: Sun, 03 Oct 2021 05:46:03 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.055, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 3830df: configure: Loosen GCC requirement from 7.5.0 to 7.4.0 X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Oct 2021 12:46:07 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 3830df5f83b9b52d9496763ce1a50afb9231c998=0D https://github.com/qemu/qemu/commit/3830df5f83b9b52d9496763ce1a50af= b9231c998=0D Author: nia =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: Loosen GCC requirement from 7.5.0 to 7.4.0=0D =0D As discussed in issue 614, we're shipping GCC 7.4.0 as the=0D system compiler in NetBSD 9, the most recent stable branch,=0D and are still actively interested in QEMU on this platform.=0D =0D The differences between GCC 7.5.0 and 7.4.0 are trivial.=0D =0D Signed-off-by: Nia Alarie =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 75b98cb9f6456ccf194211beffcbf93b0a995fa4=0D https://github.com/qemu/qemu/commit/75b98cb9f6456ccf194211beffcbf93= b0a995fa4=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-mem-pci.c=0D =0D Log Message:=0D -----------=0D virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE= event=0D =0D Apparently, we don't have to duplicate the string.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: David Hildenbrand =0D Reviewed-by: Markus Armbruster =0D Message-Id: <20210929162445.64060-2-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: d89dd28f0e29c9eae997b0cd645208454a2f3374=0D https://github.com/qemu/qemu/commit/d89dd28f0e29c9eae997b0cd6452084= 54a2f3374=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-mem-pci.c=0D M qapi/machine.json=0D =0D Log Message:=0D -----------=0D qapi: Include qom-path in MEMORY_DEVICE_SIZE_CHANGE qapi events=0D =0D As we might not always have a device id, it is impossible to always=0D match MEMORY_DEVICE_SIZE_CHANGE events to an actual device. Let's=0D include the qom-path in the event, which allows for reliable mapping of=0D= events to devices.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210929162445.64060-3-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 77ae2302ae167aa840d5a3aa489f7958db7c1426=0D https://github.com/qemu/qemu/commit/77ae2302ae167aa840d5a3aa489f795= 8db7c1426=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M monitor/monitor.c=0D =0D Log Message:=0D -----------=0D monitor: Rate-limit MEMORY_DEVICE_SIZE_CHANGE qapi events per device=0D= =0D We want to rate-limit MEMORY_DEVICE_SIZE_CHANGE events per device,=0D otherwise we can lose some events for devices. We can now use the=0D qom-path to reliably map an event to a device and make rate-limiting=0D device-aware.=0D =0D This was noticed by starting a VM with two virtio-mem devices that each=0D= have a requested size > 0. The Linux guest will initialize both devices=0D= in parallel, resulting in losing MEMORY_DEVICE_SIZE_CHANGE events for=0D one of the devices.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210929162445.64060-4-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 45e576c74533c70b38ba00f0c298dcdbc1635163=0D https://github.com/qemu/qemu/commit/45e576c74533c70b38ba00f0c298dcd= bc1635163=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/tpm/tpm_ppi.c=0D =0D Log Message:=0D -----------=0D tpm: mark correct memory region range dirty when clearing RAM=0D =0D We might not start at the beginning of the memory region. Let's=0D calculate the offset into the memory region via the difference in the=0D host addresses.=0D =0D Acked-by: Stefan Berger =0D Fixes: ffab1be70692 ("tpm: clear RAM when "memory overwrite" requested")=0D= Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Reviewed-by: Peter Xu =0D Message-Id: <20210727082545.17934-2-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 602f8ea79ce39b7bd6d2e22c686ef05227e1876b=0D https://github.com/qemu/qemu/commit/602f8ea79ce39b7bd6d2e22c686ef05= 227e1876b=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: never merge ranges accross memory regions=0D =0D Let's make sure to not merge when different memory regions are involved.=0D= Unlikely, but theoretically possible.=0D =0D Acked-by: Stefan Berger =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-3-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3513bb1be1f025e011a69bafd02b6f59fa1d8383=0D https://github.com/qemu/qemu/commit/3513bb1be1f025e011a69bafd02b6f5= 9fa1d8383=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: factor out adding physical memory ranges=0D =0D Let's factor out adding a MemoryRegionSection to the list, to be reused i= n=0D RamDiscardManager context next.=0D =0D Reviewed-by: Stefan Berger =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-4-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cb83ba8c1ab856b4327e7e869c410bbfd4152c2c=0D https://github.com/qemu/qemu/commit/cb83ba8c1ab856b4327e7e869c410bb= fd4152c2c=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: optimize for RamDiscardManager sections=0D =0D virtio-mem logically plugs/unplugs memory within a sparse memory region=0D= and notifies via the RamDiscardManager interface when parts become=0D plugged (populated) or unplugged (discarded).=0D =0D Currently, we end up (via the two users)=0D 1) zeroing all logically unplugged/discarded memory during TPM resets.=0D= 2) reading all logically unplugged/discarded memory when dumping, to=0D figure out the content is zero.=0D =0D 1) is always bad, because we assume unplugged memory stays discarded=0D (and is already implicitly zero).=0D 2) isn't that bad with anonymous memory, we end up reading the zero=0D page (slow and unnecessary, though). However, once we use some=0D file-backed memory (future use case), even reading will populate memor= y.=0D =0D Let's cut out all parts marked as not-populated (discarded) via the=0D RamDiscardManager. As virtio-mem is the single user, this now means that=0D= logically unplugged memory ranges will no longer be included in the=0D dump, which results in smaller dump files and faster dumping.=0D =0D virtio-mem has a minimum granularity of 1 MiB (and the default is usually= =0D 2 MiB). Theoretically, we can see quite some fragmentation, in practice=0D= we won't have it completely fragmented in 1 MiB pieces. Still, we might=0D= end up with many physical ranges.=0D =0D Both, the ELF format and kdump seem to be ready to support many=0D individual ranges (e.g., for ELF it seems to be UINT32_MAX, kdump has a=0D= linear bitmap).=0D =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-5-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 30bd1db58b09c12b68c35f041f919014b885482d=0D https://github.com/qemu/qemu/commit/30bd1db58b09c12b68c35f041f91901= 4b885482d=0D Author: Richard Henderson =0D Date: 2021-10-03 (Sun, 03 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M hw/tpm/tpm_ppi.c=0D M hw/virtio/virtio-mem-pci.c=0D M monitor/monitor.c=0D M qapi/machine.json=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * -smp cleanpus (Yanan)=0D * Hyper-V enlightenment functionality (Vitaly)=0D * virtio-mem support in dump, tpm and QMP (David)=0D * NetBSD GCC 7.4 compiler support (Nia)=0D =0D # gpg: Signature made Sun 03 Oct 2021 03:41:30 AM EDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream:=0D softmmu/memory_mapping: optimize for RamDiscardManager sections=0D softmmu/memory_mapping: factor out adding physical memory ranges=0D softmmu/memory_mapping: never merge ranges accross memory regions=0D tpm: mark correct memory region range dirty when clearing RAM=0D monitor: Rate-limit MEMORY_DEVICE_SIZE_CHANGE qapi events per device=0D= qapi: Include qom-path in MEMORY_DEVICE_SIZE_CHANGE qapi events=0D virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE= event=0D configure: Loosen GCC requirement from 7.5.0 to 7.4.0=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/f50ecf548c73...30bd1db58b09= =0D From MAILER-DAEMON Sun Oct 03 11:12:32 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mX3AG-0008Nx-Oq for mharc-qemu-commits@gnu.org; Sun, 03 Oct 2021 11:12:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mX3AF-0008NQ-Mo for qemu-commits@nongnu.org; Sun, 03 Oct 2021 11:12:31 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:38813 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mX3AD-0002Hp-Bl for qemu-commits@nongnu.org; Sun, 03 Oct 2021 11:12:31 -0400 Received: from github.com (hubbernetes-node-bf8cd6b.va3-iad.github.net [10.48.124.26]) by smtp.github.com (Postfix) with ESMTPA id 85DAC5C00A4 for ; Sun, 3 Oct 2021 08:12:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633273948; bh=5YhjL36VKRW5tUPYrkkDb+Rvau/syEmkHJsFOmDFAno=; h=Date:From:To:Subject:From; b=lw5gSoHimuErZKH3IsLeTEbKau6bi05gA9tW4WtaOrW1SUdQfox1dODT1veP2EEjF TaWZPGjacg6qUGjYim+ebGj8xkS3kcSUi3cgGe6TWIOptfLzF7dksf/tcHY9Pu9flD UBmqJtPOWbbz3qJdV6lgmAwCvI838EER+4dIn0ps= Date: Sun, 03 Oct 2021 08:12:28 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.055, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 3830df: configure: Loosen GCC requirement from 7.5.0 to 7.4.0 X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Oct 2021 15:12:31 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 3830df5f83b9b52d9496763ce1a50afb9231c998=0D https://github.com/qemu/qemu/commit/3830df5f83b9b52d9496763ce1a50af= b9231c998=0D Author: nia =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: Loosen GCC requirement from 7.5.0 to 7.4.0=0D =0D As discussed in issue 614, we're shipping GCC 7.4.0 as the=0D system compiler in NetBSD 9, the most recent stable branch,=0D and are still actively interested in QEMU on this platform.=0D =0D The differences between GCC 7.5.0 and 7.4.0 are trivial.=0D =0D Signed-off-by: Nia Alarie =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 75b98cb9f6456ccf194211beffcbf93b0a995fa4=0D https://github.com/qemu/qemu/commit/75b98cb9f6456ccf194211beffcbf93= b0a995fa4=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-mem-pci.c=0D =0D Log Message:=0D -----------=0D virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE= event=0D =0D Apparently, we don't have to duplicate the string.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: David Hildenbrand =0D Reviewed-by: Markus Armbruster =0D Message-Id: <20210929162445.64060-2-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: d89dd28f0e29c9eae997b0cd645208454a2f3374=0D https://github.com/qemu/qemu/commit/d89dd28f0e29c9eae997b0cd6452084= 54a2f3374=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-mem-pci.c=0D M qapi/machine.json=0D =0D Log Message:=0D -----------=0D qapi: Include qom-path in MEMORY_DEVICE_SIZE_CHANGE qapi events=0D =0D As we might not always have a device id, it is impossible to always=0D match MEMORY_DEVICE_SIZE_CHANGE events to an actual device. Let's=0D include the qom-path in the event, which allows for reliable mapping of=0D= events to devices.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210929162445.64060-3-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 77ae2302ae167aa840d5a3aa489f7958db7c1426=0D https://github.com/qemu/qemu/commit/77ae2302ae167aa840d5a3aa489f795= 8db7c1426=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M monitor/monitor.c=0D =0D Log Message:=0D -----------=0D monitor: Rate-limit MEMORY_DEVICE_SIZE_CHANGE qapi events per device=0D= =0D We want to rate-limit MEMORY_DEVICE_SIZE_CHANGE events per device,=0D otherwise we can lose some events for devices. We can now use the=0D qom-path to reliably map an event to a device and make rate-limiting=0D device-aware.=0D =0D This was noticed by starting a VM with two virtio-mem devices that each=0D= have a requested size > 0. The Linux guest will initialize both devices=0D= in parallel, resulting in losing MEMORY_DEVICE_SIZE_CHANGE events for=0D one of the devices.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210929162445.64060-4-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 45e576c74533c70b38ba00f0c298dcdbc1635163=0D https://github.com/qemu/qemu/commit/45e576c74533c70b38ba00f0c298dcd= bc1635163=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M hw/tpm/tpm_ppi.c=0D =0D Log Message:=0D -----------=0D tpm: mark correct memory region range dirty when clearing RAM=0D =0D We might not start at the beginning of the memory region. Let's=0D calculate the offset into the memory region via the difference in the=0D host addresses.=0D =0D Acked-by: Stefan Berger =0D Fixes: ffab1be70692 ("tpm: clear RAM when "memory overwrite" requested")=0D= Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Reviewed-by: Peter Xu =0D Message-Id: <20210727082545.17934-2-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 602f8ea79ce39b7bd6d2e22c686ef05227e1876b=0D https://github.com/qemu/qemu/commit/602f8ea79ce39b7bd6d2e22c686ef05= 227e1876b=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: never merge ranges accross memory regions=0D =0D Let's make sure to not merge when different memory regions are involved.=0D= Unlikely, but theoretically possible.=0D =0D Acked-by: Stefan Berger =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-3-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3513bb1be1f025e011a69bafd02b6f59fa1d8383=0D https://github.com/qemu/qemu/commit/3513bb1be1f025e011a69bafd02b6f5= 9fa1d8383=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: factor out adding physical memory ranges=0D =0D Let's factor out adding a MemoryRegionSection to the list, to be reused i= n=0D RamDiscardManager context next.=0D =0D Reviewed-by: Stefan Berger =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-4-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cb83ba8c1ab856b4327e7e869c410bbfd4152c2c=0D https://github.com/qemu/qemu/commit/cb83ba8c1ab856b4327e7e869c410bb= fd4152c2c=0D Author: David Hildenbrand =0D Date: 2021-10-02 (Sat, 02 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D softmmu/memory_mapping: optimize for RamDiscardManager sections=0D =0D virtio-mem logically plugs/unplugs memory within a sparse memory region=0D= and notifies via the RamDiscardManager interface when parts become=0D plugged (populated) or unplugged (discarded).=0D =0D Currently, we end up (via the two users)=0D 1) zeroing all logically unplugged/discarded memory during TPM resets.=0D= 2) reading all logically unplugged/discarded memory when dumping, to=0D figure out the content is zero.=0D =0D 1) is always bad, because we assume unplugged memory stays discarded=0D (and is already implicitly zero).=0D 2) isn't that bad with anonymous memory, we end up reading the zero=0D page (slow and unnecessary, though). However, once we use some=0D file-backed memory (future use case), even reading will populate memor= y.=0D =0D Let's cut out all parts marked as not-populated (discarded) via the=0D RamDiscardManager. As virtio-mem is the single user, this now means that=0D= logically unplugged memory ranges will no longer be included in the=0D dump, which results in smaller dump files and faster dumping.=0D =0D virtio-mem has a minimum granularity of 1 MiB (and the default is usually= =0D 2 MiB). Theoretically, we can see quite some fragmentation, in practice=0D= we won't have it completely fragmented in 1 MiB pieces. Still, we might=0D= end up with many physical ranges.=0D =0D Both, the ELF format and kdump seem to be ready to support many=0D individual ranges (e.g., for ELF it seems to be UINT32_MAX, kdump has a=0D= linear bitmap).=0D =0D Reviewed-by: Peter Xu =0D Cc: Marc-Andr=C3=A9 Lureau =0D Cc: Paolo Bonzini =0D Cc: "Michael S. Tsirkin" =0D Cc: Eduardo Habkost =0D Cc: Alex Williamson =0D Cc: Dr. David Alan Gilbert =0D Cc: Igor Mammedov =0D Cc: Claudio Fontana =0D Cc: Thomas Huth =0D Cc: "Alex Benn=C3=A9e" =0D Cc: Peter Xu =0D Cc: Laurent Vivier =0D Cc: Stefan Berger =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210727082545.17934-5-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 30bd1db58b09c12b68c35f041f919014b885482d=0D https://github.com/qemu/qemu/commit/30bd1db58b09c12b68c35f041f91901= 4b885482d=0D Author: Richard Henderson =0D Date: 2021-10-03 (Sun, 03 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M hw/tpm/tpm_ppi.c=0D M hw/virtio/virtio-mem-pci.c=0D M monitor/monitor.c=0D M qapi/machine.json=0D M softmmu/memory_mapping.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * -smp cleanpus (Yanan)=0D * Hyper-V enlightenment functionality (Vitaly)=0D * virtio-mem support in dump, tpm and QMP (David)=0D * NetBSD GCC 7.4 compiler support (Nia)=0D =0D # gpg: Signature made Sun 03 Oct 2021 03:41:30 AM EDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream:=0D softmmu/memory_mapping: optimize for RamDiscardManager sections=0D softmmu/memory_mapping: factor out adding physical memory ranges=0D softmmu/memory_mapping: never merge ranges accross memory regions=0D tpm: mark correct memory region range dirty when clearing RAM=0D monitor: Rate-limit MEMORY_DEVICE_SIZE_CHANGE qapi events per device=0D= qapi: Include qom-path in MEMORY_DEVICE_SIZE_CHANGE qapi events=0D virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE= event=0D configure: Loosen GCC requirement from 7.5.0 to 7.4.0=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/f50ecf548c73...30bd1db58b09= =0D From MAILER-DAEMON Mon Oct 04 17:23:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXVQl-0006jq-Ip for mharc-qemu-commits@gnu.org; Mon, 04 Oct 2021 17:23:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXVQi-0006iL-5A for qemu-commits@nongnu.org; Mon, 04 Oct 2021 17:23:25 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:49161 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXVQd-0007nr-7m for qemu-commits@nongnu.org; Mon, 04 Oct 2021 17:23:23 -0400 Received: from github.com (hubbernetes-node-ac14c71.ash1-iad.github.net [10.56.120.41]) by smtp.github.com (Postfix) with ESMTPA id 7A7E25E0DB3 for ; Mon, 4 Oct 2021 14:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633382597; bh=5dmsz2rY12q/RaOea716sBaN9fcISgj91jbcM7FWc9M=; h=Date:From:To:Subject:From; b=1TWJH/SLlf9vLaCwhf3jL1RW3BLohqWYLozZwfsraKDjG8qcwja9LC4tWo22mGo2d q/TGmvdo8YSlKcoq4DnxXmI6rgQ4OCZa2jQqhPi+BcmnNgtKpr5gsnIuOEFZkR62K+ rx/ASr0rb576pWgkm3zqDqyIge+bDh8YXBWU+K1o= Date: Mon, 04 Oct 2021 14:23:17 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] db2af6: linux-user: Add infrastructure for a signal trampo... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Oct 2021 21:23:25 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: db2af69d6ba836a264878dbf2cf676d3c1fc46b4=0D https://github.com/qemu/qemu/commit/db2af69d6ba836a264878dbf2cf676d= 3c1fc46b4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M linux-user/signal-common.h=0D M linux-user/signal.c=0D =0D Log Message:=0D -----------=0D linux-user: Add infrastructure for a signal trampoline page=0D =0D Allocate a page to hold the signal trampoline(s).=0D Invoke a guest-specific hook to fill in the contents=0D of the page before marking it read-execute again.=0D =0D Reviewed-by: Max Filippov =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-2-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c70887a38212fd8ba0141d61502a33cda0a38d2d=0D https://github.com/qemu/qemu/commit/c70887a38212fd8ba0141d61502a33c= da0a38d2d=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/aarch64/signal.c=0D M linux-user/aarch64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/aarch64: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D Use it when the guest does not use SA_RESTORER.=0D =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-3-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: eef9790007e4282b808558f93089ad0b204487f0=0D https://github.com/qemu/qemu/commit/eef9790007e4282b808558f93089ad0= b204487f0=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/arm: Drop v1 signal frames=0D =0D Version 2 signal frames are used from 2.6.12 and since cbc14e6f286,=0D we have set UNAME_MINIMUM_RELEASE to 2.6.32.=0D =0D Suggested-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-4-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b807a1087ed864f6c37ccbf6ea416387f00a8b3c=0D https://github.com/qemu/qemu/commit/b807a1087ed864f6c37ccbf6ea41638= 7f00a8b3c=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/arm: Drop "_v2" from symbols in signal.c=0D =0D Since we no longer support "v1", there's no need to distinguish "v2".=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-5-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b5d66e0dd8dda3d58e58dafa425372d158bed3e8=0D https://github.com/qemu/qemu/commit/b5d66e0dd8dda3d58e58dafa425372d= 158bed3e8=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D M linux-user/arm/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/arm: Implement setup_sigtramp=0D =0D Mirror what the kernel does in arch/arm/kernel/signal.h,=0D using the old sigframe struct in the rt sigframe struct.=0D =0D Update the trampoline code to match the kernel: this uses=0D sp-relative accesses rather than pc-relative.=0D =0D Copy the code into frame->retcode from the trampoline page.=0D This minimises the different cases wrt arm vs thumb vs fdpic.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Peter Maydell =0D Message-Id: <20210929130553.121567-6-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: dd55f1c8b217e14293f42d8531371b7c626c61dd=0D https://github.com/qemu/qemu/commit/dd55f1c8b217e14293f42d8531371b7= c626c61dd=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/alpha/signal.c=0D M linux-user/alpha/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/alpha: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use ka_restorer.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-7-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e281c2bafe22135c47caf7e1fa9db19647e49c3d=0D https://github.com/qemu/qemu/commit/e281c2bafe22135c47caf7e1fa9db19= 647e49c3d=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/cris/signal.c=0D M linux-user/cris/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/cris: Implement setup_sigtramp=0D =0D Split out setup_sigreturn so that we can continue to=0D initialize the words on the stack, as documented.=0D However, use the off-stack trampoline.=0D =0D Cc: Edgar E. Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-8-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c8ef02b1acf0d78e909c6cbd38ed60ecc5ce52ff=0D https://github.com/qemu/qemu/commit/c8ef02b1acf0d78e909c6cbd38ed60e= cc5ce52ff=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/hexagon/signal.c=0D M linux-user/hexagon/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/hexagon: Implement setup_sigtramp=0D =0D Continue to initialize the words on the stack, as documented.=0D However, use the off-stack trampoline.=0D =0D Reviewed-by: Taylor Simpson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-9-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: a22fccd8b7de9e21fc31cc048e2bf9c15947f4a4=0D https://github.com/qemu/qemu/commit/a22fccd8b7de9e21fc31cc048e2bf9c= 15947f4a4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/hppa/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/hppa: Document non-use of setup_sigtramp=0D =0D We cannot use a raw sigtramp page for hppa,=0D but must wait for full vdso support.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-10-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 8ee8a104807f67595c1a1963dbee208a52cc513b=0D https://github.com/qemu/qemu/commit/8ee8a104807f67595c1a1963dbee208= a52cc513b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/i386/signal.c=0D M linux-user/i386/target_signal.h=0D M linux-user/x86_64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/i386: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D Note that x86_64 does not use this code.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-11-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: db2055415959bcc81cd6c2f0aa2c23e5f12c1eb6=0D https://github.com/qemu/qemu/commit/db2055415959bcc81cd6c2f0aa2c23e= 5f12c1eb6=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/i386/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/x86_64: Raise SIGSEGV if SA_RESTORER not set=0D =0D This has been a fixme for some time. The effect of=0D returning -EFAULT from the kernel code is to raise SIGSEGV.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-12-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 5125aced7cd291ba232944bf980612f905e524a0=0D https://github.com/qemu/qemu/commit/5125aced7cd291ba232944bf980612f= 905e524a0=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/m68k/signal.c=0D M linux-user/m68k/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/m68k: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-13-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 8004316d81c15681143c3b8d5e77f911b08cfc8b=0D https://github.com/qemu/qemu/commit/8004316d81c15681143c3b8d5e77f91= 1b08cfc8b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/microblaze/signal.c=0D M linux-user/microblaze/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/microblaze: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D Cc: Edgar E. Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-14-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4f7a0a4c866fde385e65395f870d042c217d3c8b=0D https://github.com/qemu/qemu/commit/4f7a0a4c866fde385e65395f870d042= c217d3c8b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/mips/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/mips: Tidy install_sigtramp=0D =0D The return value is constant 0, and unused as well -- change to void.=0D Drop inline marker. Change tramp type to uint32_t* for clarity.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-15-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 317a33b6ebad8a9e94109b4421804f7945eb8935=0D https://github.com/qemu/qemu/commit/317a33b6ebad8a9e94109b4421804f7= 945eb8935=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/mips/signal.c=0D M linux-user/mips/target_signal.h=0D M linux-user/mips64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/mips: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-16-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f32d3b67938a42e320016fd15f5c34afa0fb105a=0D https://github.com/qemu/qemu/commit/f32d3b67938a42e320016fd15f5c34a= fa0fb105a=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/nios2/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/nios2: Document non-use of setup_sigtramp=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-17-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 9ce3ad4452539723d9204dbfc137f57124eb8e36=0D https://github.com/qemu/qemu/commit/9ce3ad4452539723d9204dbfc137f57= 124eb8e36=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/openrisc/signal.c=0D M linux-user/openrisc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/openrisc: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D Reviewed-by: Stafford Horne =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-18-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 5d2fc70f57916abc6afbe739636dffed6a5009c7=0D https://github.com/qemu/qemu/commit/5d2fc70f57916abc6afbe739636dffe= d6a5009c7=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Simplify encode_trampoline=0D =0D The sigret parameter is never 0, and even if it was the encoding=0D of the LI instruction would still work.=0D =0D Reported-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-19-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c790e4ebfed8174f65d685f5a4f3262873c237a5=0D https://github.com/qemu/qemu/commit/c790e4ebfed8174f65d685f5a4f3262= 873c237a5=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D M linux-user/ppc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Cc: qemu-ppc@nongnu.org=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-20-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3c62b5d2015b8292d4453f8174abf5fadbc6cc0f=0D https://github.com/qemu/qemu/commit/3c62b5d2015b8292d4453f8174abf5f= adbc6cc0f=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/riscv/signal.c=0D M linux-user/riscv/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/riscv: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D This fixes a bug wrt libgcc fallback unwinding. It expects=0D the stack pointer to point to the siginfo_t, whereas we had=0D inexplicably placed our private signal trampoline at the start=0D of the signal frame instead of the end. Now moot because we=0D have removed it from the stack frame entirely.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-21-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 31330e6cecfdf2c4617ecb95c7e2804a8dae2488=0D https://github.com/qemu/qemu/commit/31330e6cecfdf2c4617ecb95c7e2804= a8dae2488=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/s390x/signal.c=0D M linux-user/s390x/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/s390x: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Cc: qemu-s390x@nongnu.org=0D Tested-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-22-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b9188f9ccc2af655666cfaac12ff9fb4db3c6009=0D https://github.com/qemu/qemu/commit/b9188f9ccc2af655666cfaac12ff9fb= 4db3c6009=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/sh4/signal.c=0D M linux-user/sh4/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/sh4: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Cc: Yoshinori Sato =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-23-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3f7685eaf90b36d0dc39d4719840e736c019a05c=0D https://github.com/qemu/qemu/commit/3f7685eaf90b36d0dc39d4719840e73= 6c019a05c=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/sparc/signal.c=0D M linux-user/sparc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/sparc: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Acked-by: Mark Cave-Ayland =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-24-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 55e83c200594b5c3ab412dec2646898571b08b40=0D https://github.com/qemu/qemu/commit/55e83c200594b5c3ab412dec2646898= 571b08b40=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/xtensa/signal.c=0D M linux-user/xtensa/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/xtensa: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D Use it when the guest does not use SA_RESTORER.=0D =0D Reviewed-by: Max Filippov =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-25-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 525c4670c5612336cc50fa4190bdc72c1e3ee270=0D https://github.com/qemu/qemu/commit/525c4670c5612336cc50fa4190bdc72= c1e3ee270=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D =0D Log Message:=0D -----------=0D linux-user: Remove default for TARGET_ARCH_HAS_SIGTRAMP_PAGE=0D =0D All targets now define TARGET_ARCH_HAS_SIGTRAMP_PAGE.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-26-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: efee71c8ca181d4f5b2211736b38a74a2a223375=0D https://github.com/qemu/qemu/commit/efee71c8ca181d4f5b2211736b38a74= a2a223375=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/hppa/Makefile.target=0D M tests/tcg/i386/Makefile.target=0D M tests/tcg/multiarch/Makefile.target=0D M tests/tcg/sh4/Makefile.target=0D =0D Log Message:=0D -----------=0D tests/tcg/multiarch: Re-enable signals test for most guests=0D =0D With signal trampolines safely off the stack for all=0D guests besides hppa, we can re-enable this test.=0D =0D It does show up a problem with sh4 (unrelated?),=0D so leave that test disabled for now.=0D =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-27-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e7ab6584784dbbd701f0ffe7b29918f44dcd98fd=0D https://github.com/qemu/qemu/commit/e7ab6584784dbbd701f0ffe7b29918f= 44dcd98fd=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M linux-user/aarch64/signal.c=0D M linux-user/aarch64/target_signal.h=0D M linux-user/alpha/signal.c=0D M linux-user/alpha/target_signal.h=0D M linux-user/arm/signal.c=0D M linux-user/arm/target_signal.h=0D M linux-user/cris/signal.c=0D M linux-user/cris/target_signal.h=0D M linux-user/elfload.c=0D M linux-user/hexagon/signal.c=0D M linux-user/hexagon/target_signal.h=0D M linux-user/hppa/target_signal.h=0D M linux-user/i386/signal.c=0D M linux-user/i386/target_signal.h=0D M linux-user/m68k/signal.c=0D M linux-user/m68k/target_signal.h=0D M linux-user/microblaze/signal.c=0D M linux-user/microblaze/target_signal.h=0D M linux-user/mips/signal.c=0D M linux-user/mips/target_signal.h=0D M linux-user/mips64/target_signal.h=0D M linux-user/nios2/target_signal.h=0D M linux-user/openrisc/signal.c=0D M linux-user/openrisc/target_signal.h=0D M linux-user/ppc/signal.c=0D M linux-user/ppc/target_signal.h=0D M linux-user/riscv/signal.c=0D M linux-user/riscv/target_signal.h=0D M linux-user/s390x/signal.c=0D M linux-user/s390x/target_signal.h=0D M linux-user/sh4/signal.c=0D M linux-user/sh4/target_signal.h=0D M linux-user/signal-common.h=0D M linux-user/signal.c=0D M linux-user/sparc/signal.c=0D M linux-user/sparc/target_signal.h=0D M linux-user/x86_64/target_signal.h=0D M linux-user/xtensa/signal.c=0D M linux-user/xtensa/target_signal.h=0D M tests/tcg/hppa/Makefile.target=0D M tests/tcg/i386/Makefile.target=0D M tests/tcg/multiarch/Makefile.target=0D M tests/tcg/sh4/Makefile.target=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/linux-user-for-6.2-pu= ll-request' into staging=0D =0D Pull request linux-user 20211004=0D =0D Move signal trampolines to new page=0D =0D # gpg: Signature made Mon 04 Oct 2021 12:43:53 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/linux-user-for-6.2-pull-request: (26 commits)=0D tests/tcg/multiarch: Re-enable signals test for most guests=0D linux-user: Remove default for TARGET_ARCH_HAS_SIGTRAMP_PAGE=0D linux-user/xtensa: Implement setup_sigtramp=0D linux-user/sparc: Implement setup_sigtramp=0D linux-user/sh4: Implement setup_sigtramp=0D linux-user/s390x: Implement setup_sigtramp=0D linux-user/riscv: Implement setup_sigtramp=0D linux-user/ppc: Implement setup_sigtramp=0D linux-user/ppc: Simplify encode_trampoline=0D linux-user/openrisc: Implement setup_sigtramp=0D linux-user/nios2: Document non-use of setup_sigtramp=0D linux-user/mips: Implement setup_sigtramp=0D linux-user/mips: Tidy install_sigtramp=0D linux-user/microblaze: Implement setup_sigtramp=0D linux-user/m68k: Implement setup_sigtramp=0D linux-user/x86_64: Raise SIGSEGV if SA_RESTORER not set=0D linux-user/i386: Implement setup_sigtramp=0D linux-user/hppa: Document non-use of setup_sigtramp=0D linux-user/hexagon: Implement setup_sigtramp=0D linux-user/cris: Implement setup_sigtramp=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/30bd1db58b09...e7ab6584784d= =0D From MAILER-DAEMON Mon Oct 04 19:26:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXXM7-0001Pf-05 for mharc-qemu-commits@gnu.org; Mon, 04 Oct 2021 19:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXXM5-0001PX-SF for qemu-commits@nongnu.org; Mon, 04 Oct 2021 19:26:45 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:49663 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXXM0-0004Ox-VD for qemu-commits@nongnu.org; Mon, 04 Oct 2021 19:26:45 -0400 Received: from github.com (hubbernetes-node-c306552.ash1-iad.github.net [10.56.118.49]) by smtp.github.com (Postfix) with ESMTPA id 2C3935E0701 for ; Mon, 4 Oct 2021 16:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633389999; bh=JJRCYFssVacqNz+ykBnh5n89sJAz62uEAH9ZhWfN58c=; h=Date:From:To:Subject:From; b=xkfhiCU7XVim/F8FmyrOAcp/CEQWjwJ4/uK3zbCpZma1GyFZ3A7jrnkuLNiOZ2yV6 Prqnp8DG4Zp6YMLk7hX9GU4xJLsiPmaPhIhh1p6acfTTlDNmsnDJbLwgA1WLe1hutL a3PEnkx7NEOEJHOinck0pQggt9QxdCUEbhEI5j8I= Date: Mon, 04 Oct 2021 16:26:39 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] db2af6: linux-user: Add infrastructure for a signal trampo... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Oct 2021 23:26:46 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: db2af69d6ba836a264878dbf2cf676d3c1fc46b4=0D https://github.com/qemu/qemu/commit/db2af69d6ba836a264878dbf2cf676d= 3c1fc46b4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M linux-user/signal-common.h=0D M linux-user/signal.c=0D =0D Log Message:=0D -----------=0D linux-user: Add infrastructure for a signal trampoline page=0D =0D Allocate a page to hold the signal trampoline(s).=0D Invoke a guest-specific hook to fill in the contents=0D of the page before marking it read-execute again.=0D =0D Reviewed-by: Max Filippov =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-2-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c70887a38212fd8ba0141d61502a33cda0a38d2d=0D https://github.com/qemu/qemu/commit/c70887a38212fd8ba0141d61502a33c= da0a38d2d=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/aarch64/signal.c=0D M linux-user/aarch64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/aarch64: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D Use it when the guest does not use SA_RESTORER.=0D =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-3-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: eef9790007e4282b808558f93089ad0b204487f0=0D https://github.com/qemu/qemu/commit/eef9790007e4282b808558f93089ad0= b204487f0=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/arm: Drop v1 signal frames=0D =0D Version 2 signal frames are used from 2.6.12 and since cbc14e6f286,=0D we have set UNAME_MINIMUM_RELEASE to 2.6.32.=0D =0D Suggested-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-4-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b807a1087ed864f6c37ccbf6ea416387f00a8b3c=0D https://github.com/qemu/qemu/commit/b807a1087ed864f6c37ccbf6ea41638= 7f00a8b3c=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/arm: Drop "_v2" from symbols in signal.c=0D =0D Since we no longer support "v1", there's no need to distinguish "v2".=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-5-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b5d66e0dd8dda3d58e58dafa425372d158bed3e8=0D https://github.com/qemu/qemu/commit/b5d66e0dd8dda3d58e58dafa425372d= 158bed3e8=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/arm/signal.c=0D M linux-user/arm/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/arm: Implement setup_sigtramp=0D =0D Mirror what the kernel does in arch/arm/kernel/signal.h,=0D using the old sigframe struct in the rt sigframe struct.=0D =0D Update the trampoline code to match the kernel: this uses=0D sp-relative accesses rather than pc-relative.=0D =0D Copy the code into frame->retcode from the trampoline page.=0D This minimises the different cases wrt arm vs thumb vs fdpic.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Peter Maydell =0D Message-Id: <20210929130553.121567-6-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: dd55f1c8b217e14293f42d8531371b7c626c61dd=0D https://github.com/qemu/qemu/commit/dd55f1c8b217e14293f42d8531371b7= c626c61dd=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/alpha/signal.c=0D M linux-user/alpha/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/alpha: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use ka_restorer.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-7-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e281c2bafe22135c47caf7e1fa9db19647e49c3d=0D https://github.com/qemu/qemu/commit/e281c2bafe22135c47caf7e1fa9db19= 647e49c3d=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/cris/signal.c=0D M linux-user/cris/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/cris: Implement setup_sigtramp=0D =0D Split out setup_sigreturn so that we can continue to=0D initialize the words on the stack, as documented.=0D However, use the off-stack trampoline.=0D =0D Cc: Edgar E. Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-8-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c8ef02b1acf0d78e909c6cbd38ed60ecc5ce52ff=0D https://github.com/qemu/qemu/commit/c8ef02b1acf0d78e909c6cbd38ed60e= cc5ce52ff=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/hexagon/signal.c=0D M linux-user/hexagon/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/hexagon: Implement setup_sigtramp=0D =0D Continue to initialize the words on the stack, as documented.=0D However, use the off-stack trampoline.=0D =0D Reviewed-by: Taylor Simpson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-9-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: a22fccd8b7de9e21fc31cc048e2bf9c15947f4a4=0D https://github.com/qemu/qemu/commit/a22fccd8b7de9e21fc31cc048e2bf9c= 15947f4a4=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/hppa/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/hppa: Document non-use of setup_sigtramp=0D =0D We cannot use a raw sigtramp page for hppa,=0D but must wait for full vdso support.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-10-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 8ee8a104807f67595c1a1963dbee208a52cc513b=0D https://github.com/qemu/qemu/commit/8ee8a104807f67595c1a1963dbee208= a52cc513b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/i386/signal.c=0D M linux-user/i386/target_signal.h=0D M linux-user/x86_64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/i386: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D Note that x86_64 does not use this code.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-11-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: db2055415959bcc81cd6c2f0aa2c23e5f12c1eb6=0D https://github.com/qemu/qemu/commit/db2055415959bcc81cd6c2f0aa2c23e= 5f12c1eb6=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/i386/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/x86_64: Raise SIGSEGV if SA_RESTORER not set=0D =0D This has been a fixme for some time. The effect of=0D returning -EFAULT from the kernel code is to raise SIGSEGV.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-12-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 5125aced7cd291ba232944bf980612f905e524a0=0D https://github.com/qemu/qemu/commit/5125aced7cd291ba232944bf980612f= 905e524a0=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/m68k/signal.c=0D M linux-user/m68k/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/m68k: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-13-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 8004316d81c15681143c3b8d5e77f911b08cfc8b=0D https://github.com/qemu/qemu/commit/8004316d81c15681143c3b8d5e77f91= 1b08cfc8b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/microblaze/signal.c=0D M linux-user/microblaze/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/microblaze: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D Cc: Edgar E. Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-14-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4f7a0a4c866fde385e65395f870d042c217d3c8b=0D https://github.com/qemu/qemu/commit/4f7a0a4c866fde385e65395f870d042= c217d3c8b=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/mips/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/mips: Tidy install_sigtramp=0D =0D The return value is constant 0, and unused as well -- change to void.=0D Drop inline marker. Change tramp type to uint32_t* for clarity.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-15-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 317a33b6ebad8a9e94109b4421804f7945eb8935=0D https://github.com/qemu/qemu/commit/317a33b6ebad8a9e94109b4421804f7= 945eb8935=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/mips/signal.c=0D M linux-user/mips/target_signal.h=0D M linux-user/mips64/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/mips: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-16-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f32d3b67938a42e320016fd15f5c34afa0fb105a=0D https://github.com/qemu/qemu/commit/f32d3b67938a42e320016fd15f5c34a= fa0fb105a=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/nios2/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/nios2: Document non-use of setup_sigtramp=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-17-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 9ce3ad4452539723d9204dbfc137f57124eb8e36=0D https://github.com/qemu/qemu/commit/9ce3ad4452539723d9204dbfc137f57= 124eb8e36=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/openrisc/signal.c=0D M linux-user/openrisc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/openrisc: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D Reviewed-by: Stafford Horne =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-18-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 5d2fc70f57916abc6afbe739636dffed6a5009c7=0D https://github.com/qemu/qemu/commit/5d2fc70f57916abc6afbe739636dffe= d6a5009c7=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Simplify encode_trampoline=0D =0D The sigret parameter is never 0, and even if it was the encoding=0D of the LI instruction would still work.=0D =0D Reported-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-19-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c790e4ebfed8174f65d685f5a4f3262873c237a5=0D https://github.com/qemu/qemu/commit/c790e4ebfed8174f65d685f5a4f3262= 873c237a5=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D M linux-user/ppc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D =0D Cc: qemu-ppc@nongnu.org=0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-20-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3c62b5d2015b8292d4453f8174abf5fadbc6cc0f=0D https://github.com/qemu/qemu/commit/3c62b5d2015b8292d4453f8174abf5f= adbc6cc0f=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/riscv/signal.c=0D M linux-user/riscv/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/riscv: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D =0D This fixes a bug wrt libgcc fallback unwinding. It expects=0D the stack pointer to point to the siginfo_t, whereas we had=0D inexplicably placed our private signal trampoline at the start=0D of the signal frame instead of the end. Now moot because we=0D have removed it from the stack frame entirely.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-21-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 31330e6cecfdf2c4617ecb95c7e2804a8dae2488=0D https://github.com/qemu/qemu/commit/31330e6cecfdf2c4617ecb95c7e2804= a8dae2488=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/s390x/signal.c=0D M linux-user/s390x/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/s390x: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Cc: qemu-s390x@nongnu.org=0D Tested-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-22-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: b9188f9ccc2af655666cfaac12ff9fb4db3c6009=0D https://github.com/qemu/qemu/commit/b9188f9ccc2af655666cfaac12ff9fb= 4db3c6009=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/sh4/signal.c=0D M linux-user/sh4/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/sh4: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Cc: Yoshinori Sato =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-23-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3f7685eaf90b36d0dc39d4719840e736c019a05c=0D https://github.com/qemu/qemu/commit/3f7685eaf90b36d0dc39d4719840e73= 6c019a05c=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/sparc/signal.c=0D M linux-user/sparc/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/sparc: Implement setup_sigtramp=0D =0D Create and record the two signal trampolines.=0D Use them when the guest does not use SA_RESTORER.=0D =0D Acked-by: Mark Cave-Ayland =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-24-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 55e83c200594b5c3ab412dec2646898571b08b40=0D https://github.com/qemu/qemu/commit/55e83c200594b5c3ab412dec2646898= 571b08b40=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/xtensa/signal.c=0D M linux-user/xtensa/target_signal.h=0D =0D Log Message:=0D -----------=0D linux-user/xtensa: Implement setup_sigtramp=0D =0D Create and record the rt signal trampoline.=0D Use it when the guest does not use SA_RESTORER.=0D =0D Reviewed-by: Max Filippov =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-25-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 525c4670c5612336cc50fa4190bdc72c1e3ee270=0D https://github.com/qemu/qemu/commit/525c4670c5612336cc50fa4190bdc72= c1e3ee270=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D =0D Log Message:=0D -----------=0D linux-user: Remove default for TARGET_ARCH_HAS_SIGTRAMP_PAGE=0D =0D All targets now define TARGET_ARCH_HAS_SIGTRAMP_PAGE.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-26-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: efee71c8ca181d4f5b2211736b38a74a2a223375=0D https://github.com/qemu/qemu/commit/efee71c8ca181d4f5b2211736b38a74= a2a223375=0D Author: Richard Henderson =0D Date: 2021-10-01 (Fri, 01 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/hppa/Makefile.target=0D M tests/tcg/i386/Makefile.target=0D M tests/tcg/multiarch/Makefile.target=0D M tests/tcg/sh4/Makefile.target=0D =0D Log Message:=0D -----------=0D tests/tcg/multiarch: Re-enable signals test for most guests=0D =0D With signal trampolines safely off the stack for all=0D guests besides hppa, we can re-enable this test.=0D =0D It does show up a problem with sh4 (unrelated?),=0D so leave that test disabled for now.=0D =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210929130553.121567-27-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e7ab6584784dbbd701f0ffe7b29918f44dcd98fd=0D https://github.com/qemu/qemu/commit/e7ab6584784dbbd701f0ffe7b29918f= 44dcd98fd=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M linux-user/aarch64/signal.c=0D M linux-user/aarch64/target_signal.h=0D M linux-user/alpha/signal.c=0D M linux-user/alpha/target_signal.h=0D M linux-user/arm/signal.c=0D M linux-user/arm/target_signal.h=0D M linux-user/cris/signal.c=0D M linux-user/cris/target_signal.h=0D M linux-user/elfload.c=0D M linux-user/hexagon/signal.c=0D M linux-user/hexagon/target_signal.h=0D M linux-user/hppa/target_signal.h=0D M linux-user/i386/signal.c=0D M linux-user/i386/target_signal.h=0D M linux-user/m68k/signal.c=0D M linux-user/m68k/target_signal.h=0D M linux-user/microblaze/signal.c=0D M linux-user/microblaze/target_signal.h=0D M linux-user/mips/signal.c=0D M linux-user/mips/target_signal.h=0D M linux-user/mips64/target_signal.h=0D M linux-user/nios2/target_signal.h=0D M linux-user/openrisc/signal.c=0D M linux-user/openrisc/target_signal.h=0D M linux-user/ppc/signal.c=0D M linux-user/ppc/target_signal.h=0D M linux-user/riscv/signal.c=0D M linux-user/riscv/target_signal.h=0D M linux-user/s390x/signal.c=0D M linux-user/s390x/target_signal.h=0D M linux-user/sh4/signal.c=0D M linux-user/sh4/target_signal.h=0D M linux-user/signal-common.h=0D M linux-user/signal.c=0D M linux-user/sparc/signal.c=0D M linux-user/sparc/target_signal.h=0D M linux-user/x86_64/target_signal.h=0D M linux-user/xtensa/signal.c=0D M linux-user/xtensa/target_signal.h=0D M tests/tcg/hppa/Makefile.target=0D M tests/tcg/i386/Makefile.target=0D M tests/tcg/multiarch/Makefile.target=0D M tests/tcg/sh4/Makefile.target=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/linux-user-for-6.2-pu= ll-request' into staging=0D =0D Pull request linux-user 20211004=0D =0D Move signal trampolines to new page=0D =0D # gpg: Signature made Mon 04 Oct 2021 12:43:53 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/linux-user-for-6.2-pull-request: (26 commits)=0D tests/tcg/multiarch: Re-enable signals test for most guests=0D linux-user: Remove default for TARGET_ARCH_HAS_SIGTRAMP_PAGE=0D linux-user/xtensa: Implement setup_sigtramp=0D linux-user/sparc: Implement setup_sigtramp=0D linux-user/sh4: Implement setup_sigtramp=0D linux-user/s390x: Implement setup_sigtramp=0D linux-user/riscv: Implement setup_sigtramp=0D linux-user/ppc: Implement setup_sigtramp=0D linux-user/ppc: Simplify encode_trampoline=0D linux-user/openrisc: Implement setup_sigtramp=0D linux-user/nios2: Document non-use of setup_sigtramp=0D linux-user/mips: Implement setup_sigtramp=0D linux-user/mips: Tidy install_sigtramp=0D linux-user/microblaze: Implement setup_sigtramp=0D linux-user/m68k: Implement setup_sigtramp=0D linux-user/x86_64: Raise SIGSEGV if SA_RESTORER not set=0D linux-user/i386: Implement setup_sigtramp=0D linux-user/hppa: Document non-use of setup_sigtramp=0D linux-user/hexagon: Implement setup_sigtramp=0D linux-user/cris: Implement setup_sigtramp=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/30bd1db58b09...e7ab6584784d= =0D From MAILER-DAEMON Mon Oct 04 19:33:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXXSQ-0003IC-SJ for mharc-qemu-commits@gnu.org; Mon, 04 Oct 2021 19:33:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXXSP-0003HC-9M for qemu-commits@nongnu.org; Mon, 04 Oct 2021 19:33:17 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:40451) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXXSN-0005LF-EE for qemu-commits@nongnu.org; Mon, 04 Oct 2021 19:33:17 -0400 Received: from github.com (hubbernetes-node-c88f106.ash1-iad.github.net [10.56.113.58]) by smtp.github.com (Postfix) with ESMTPA id 64BBC900908 for ; Mon, 4 Oct 2021 16:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633390394; bh=X2wfcxn6v7yQYPbkWrMZMxhR56DeJTOOg6/itVoU2Dk=; h=Date:From:To:Subject:From; b=PovtO8KzXRapsEpk9L8NEjV8PwQtuJWJEY3l2xLm06PqERImmtq7sUiSnX6EKJfG2 zkNwxAyXZRxu63KXzPJPymp3IfvrIAC1HT99HJdaLDuyZXtOSV2GZjXiuzbOHV70zG ALz3nhimQF3HVsjLkmmkqwTA9Ayqj1FvVvD8D9ik= Date: Mon, 04 Oct 2021 16:33:14 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ba858d: qemu-options: -chardev reconnect=seconds duplicate... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Oct 2021 23:33:17 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: ba858d1fadec417ab95c29938d2a0bb967d86114=0D https://github.com/qemu/qemu/commit/ba858d1fadec417ab95c29938d2a0bb= 967d86114=0D Author: Markus Armbruster =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: -chardev reconnect=3Dseconds duplicated in help, tidy up=0D= =0D Fixes: 5dd1f02b4bc2f2c2ef3a2adfd8a412c8c8769085=0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210928071449.1416022-1-armbru@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 553dc36b387d9c99740f5ae825465ffdd93685f2=0D https://github.com/qemu/qemu/commit/553dc36b387d9c99740f5ae825465ff= dd93685f2=0D Author: Yanan Wang =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: Tweak [, maxcpus=3Dcpus] to [, maxcpus=3Dmaxcpus]=0D =0D In qemu-option.hx, there is "-smp [[cpus=3D]n][,maxcpus=3Dcpus]..." in th= e=0D DEF part, and "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus]..." in the RST part.= =0D Obviously the later is right, let's fix the previous one.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Andrew Jones =0D Message-Id: <20210928121134.21064-2-wangyanan55@huawei.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 848dd26928e2f4ceb63d7de06dd0b5f5b55bbddd=0D https://github.com/qemu/qemu/commit/848dd26928e2f4ceb63d7de06dd0b5f= 5b55bbddd=0D Author: Yanan Wang =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: Add missing "sockets=3D2, maxcpus=3D2" to CLI "-smp 2"=0D= =0D There is one numa config example in qemu-options.hx currently=0D using "-smp 2" and assuming that there will be 2 sockets and=0D 2 cpus totally. However now the actual calculation logic of=0D missing sockets and cores is not immutable and is considered=0D liable to change. Although we will get maxcpus=3D2 finally based=0D on current parser, it's always stable to specify it explicitly.=0D =0D So "-smp 2,sockets=3D2,maxcpus=3D2" will be optimal when we expect=0D multiple sockets and 2 cpus totally.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Philippe Mathieu-Daude =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Andrew Jones =0D Message-Id: <20210928121134.21064-3-wangyanan55@huawei.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 196fb7ac7cb83f3b5547435f3b1d8b5bfaca35fb=0D https://github.com/qemu/qemu/commit/196fb7ac7cb83f3b5547435f3b1d8b5= bfaca35fb=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D target/sh4: Use lookup_symbol in sh4_tr_disas_log=0D =0D The correct thing to do has been present but commented=0D out since the initial commit of the sh4 translator.=0D =0D Fixes: fdf9b3e831e=0D Signed-off-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929130316.121330-1-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: daf0db06308b55c518312abc39a4bf74413ac007=0D https://github.com/qemu/qemu/commit/daf0db06308b55c518312abc39a4bf7= 4413ac007=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M hw/remote/proxy.c=0D =0D Log Message:=0D -----------=0D hw/remote/proxy: Categorize Wireless devices as 'Network' ones=0D =0D QEMU doesn't distinct network devices per link layer (Ethernet,=0D Wi-Fi, CAN, ...). Categorize PCI Wireless cards as Network=0D devices.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Jagannathan Raman =0D Message-Id: <20210926201926.1690896-1-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 9618c5badaa8eed25259cf095ff880efb939fbe7=0D https://github.com/qemu/qemu/commit/9618c5badaa8eed25259cf095ff880e= fb939fbe7=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M hw/remote/proxy.c=0D M qemu-options.hx=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.= 2-pull-request' into staging=0D =0D Pull request trivial-patches 2021104=0D =0D # gpg: Signature made Mon 04 Oct 2021 01:30:22 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/trivial-branch-for-6.2-pull-request:=0D hw/remote/proxy: Categorize Wireless devices as 'Network' ones=0D target/sh4: Use lookup_symbol in sh4_tr_disas_log=0D qemu-options: Add missing "sockets=3D2, maxcpus=3D2" to CLI "-smp 2"=0D= qemu-options: Tweak [, maxcpus=3Dcpus] to [, maxcpus=3Dmaxcpus]=0D qemu-options: -chardev reconnect=3Dseconds duplicated in help, tidy up=0D= =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e7ab6584784d...9618c5badaa8= =0D From MAILER-DAEMON Mon Oct 04 21:48:26 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXZZC-0003XO-1J for mharc-qemu-commits@gnu.org; Mon, 04 Oct 2021 21:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXZZ9-0003Sd-MB for qemu-commits@nongnu.org; Mon, 04 Oct 2021 21:48:23 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:36309 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXZZ7-0003wN-GI for qemu-commits@nongnu.org; Mon, 04 Oct 2021 21:48:23 -0400 Received: from github.com (hubbernetes-node-0570ca1.va3-iad.github.net [10.48.209.81]) by smtp.github.com (Postfix) with ESMTPA id BDC90340D11 for ; Mon, 4 Oct 2021 18:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633398500; bh=2/ACj6D12NbSyrSfZUVY9sYqu8UGUcr3hOIuWBW+gDs=; h=Date:From:To:Subject:From; b=L3q1h0JcFqtVWn0+JVuaAgyOW/G/bk5AS6EswfB18arudlWt1kJOSNiidSlaB50S5 cd/LNNE+Kmn94BgGI1hqeyi5Rki2F2J6c0OXC8diV46o8sro99TSD1QGlnyfUxexHK aqFGZS+QV750Vg6wHEB/+h0D3FMyVC8Nu/XmzGx4= Date: Mon, 04 Oct 2021 18:48:20 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ba858d: qemu-options: -chardev reconnect=seconds duplicate... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 01:48:23 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: ba858d1fadec417ab95c29938d2a0bb967d86114=0D https://github.com/qemu/qemu/commit/ba858d1fadec417ab95c29938d2a0bb= 967d86114=0D Author: Markus Armbruster =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: -chardev reconnect=3Dseconds duplicated in help, tidy up=0D= =0D Fixes: 5dd1f02b4bc2f2c2ef3a2adfd8a412c8c8769085=0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210928071449.1416022-1-armbru@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 553dc36b387d9c99740f5ae825465ffdd93685f2=0D https://github.com/qemu/qemu/commit/553dc36b387d9c99740f5ae825465ff= dd93685f2=0D Author: Yanan Wang =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: Tweak [, maxcpus=3Dcpus] to [, maxcpus=3Dmaxcpus]=0D =0D In qemu-option.hx, there is "-smp [[cpus=3D]n][,maxcpus=3Dcpus]..." in th= e=0D DEF part, and "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus]..." in the RST part.= =0D Obviously the later is right, let's fix the previous one.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Andrew Jones =0D Message-Id: <20210928121134.21064-2-wangyanan55@huawei.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 848dd26928e2f4ceb63d7de06dd0b5f5b55bbddd=0D https://github.com/qemu/qemu/commit/848dd26928e2f4ceb63d7de06dd0b5f= 5b55bbddd=0D Author: Yanan Wang =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M qemu-options.hx=0D =0D Log Message:=0D -----------=0D qemu-options: Add missing "sockets=3D2, maxcpus=3D2" to CLI "-smp 2"=0D= =0D There is one numa config example in qemu-options.hx currently=0D using "-smp 2" and assuming that there will be 2 sockets and=0D 2 cpus totally. However now the actual calculation logic of=0D missing sockets and cores is not immutable and is considered=0D liable to change. Although we will get maxcpus=3D2 finally based=0D on current parser, it's always stable to specify it explicitly.=0D =0D So "-smp 2,sockets=3D2,maxcpus=3D2" will be optimal when we expect=0D multiple sockets and 2 cpus totally.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Philippe Mathieu-Daude =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Andrew Jones =0D Message-Id: <20210928121134.21064-3-wangyanan55@huawei.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 196fb7ac7cb83f3b5547435f3b1d8b5bfaca35fb=0D https://github.com/qemu/qemu/commit/196fb7ac7cb83f3b5547435f3b1d8b5= bfaca35fb=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D target/sh4: Use lookup_symbol in sh4_tr_disas_log=0D =0D The correct thing to do has been present but commented=0D out since the initial commit of the sh4 translator.=0D =0D Fixes: fdf9b3e831e=0D Signed-off-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210929130316.121330-1-richard.henderson@linaro.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: daf0db06308b55c518312abc39a4bf74413ac007=0D https://github.com/qemu/qemu/commit/daf0db06308b55c518312abc39a4bf7= 4413ac007=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M hw/remote/proxy.c=0D =0D Log Message:=0D -----------=0D hw/remote/proxy: Categorize Wireless devices as 'Network' ones=0D =0D QEMU doesn't distinct network devices per link layer (Ethernet,=0D Wi-Fi, CAN, ...). Categorize PCI Wireless cards as Network=0D devices.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Jagannathan Raman =0D Message-Id: <20210926201926.1690896-1-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 9618c5badaa8eed25259cf095ff880efb939fbe7=0D https://github.com/qemu/qemu/commit/9618c5badaa8eed25259cf095ff880e= fb939fbe7=0D Author: Richard Henderson =0D Date: 2021-10-04 (Mon, 04 Oct 2021)=0D =0D Changed paths:=0D M hw/remote/proxy.c=0D M qemu-options.hx=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.= 2-pull-request' into staging=0D =0D Pull request trivial-patches 2021104=0D =0D # gpg: Signature made Mon 04 Oct 2021 01:30:22 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/trivial-branch-for-6.2-pull-request:=0D hw/remote/proxy: Categorize Wireless devices as 'Network' ones=0D target/sh4: Use lookup_symbol in sh4_tr_disas_log=0D qemu-options: Add missing "sockets=3D2, maxcpus=3D2" to CLI "-smp 2"=0D= qemu-options: Tweak [, maxcpus=3Dcpus] to [, maxcpus=3Dmaxcpus]=0D qemu-options: -chardev reconnect=3Dseconds duplicated in help, tidy up=0D= =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e7ab6584784d...9618c5badaa8= =0D From MAILER-DAEMON Tue Oct 05 13:17:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXo45-000647-3n for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 13:17:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXo3w-00061E-GN for qemu-commits@nongnu.org; Tue, 05 Oct 2021 13:17:09 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:32885) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXo3p-0008UV-HE for qemu-commits@nongnu.org; Tue, 05 Oct 2021 13:17:07 -0400 Received: from github.com (hubbernetes-node-9101aff.ac4-iad.github.net [10.52.205.13]) by smtp.github.com (Postfix) with ESMTPA id BAB7960015D for ; Tue, 5 Oct 2021 10:17:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633454220; bh=NH5L+RMnsBgKX8Qo6lDVE3Rqoq+BVkaAJAmRsTkDavY=; h=Date:From:To:Subject:From; b=U0S5X39ayYoVqsC7d2ysxJ4auvx/8AT9XEoDMKC7lpStHAfyTDQzb3FM2BYEomkhE YpFpkAWWxY5PV7h6bQV9NHa0a0J6qwvXOsCgpb9ggcvvFvAfdVMIs2hTYErETn5GKP M2cq/RxHL1TW7FMXJpdwYiaxntAXj1j2hIJx+QIE= Date: Tue, 05 Oct 2021 10:17:00 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ab4dd2: hw/virtio: Acquire RCU read lock in virtqueue_pack... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 17:17:09 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: ab4dd2746c234f038206b3ccfe6bec1f19f98c24=0D https://github.com/qemu/qemu/commit/ab4dd2746c234f038206b3ccfe6bec1= f19f98c24=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Acquire RCU read lock in virtqueue_packed_drop_all()=0D =0D vring_get_region_caches() must be called with the RCU read lock=0D acquired. virtqueue_packed_drop_all() does not, and uses the=0D 'caches' pointer. Fix that by using the RCU_READ_LOCK_GUARD()=0D macro.=0D =0D Reported-by: Stefano Garzarella =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-3-philmd@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: d6ed27bae717ceac9de0c53a31389143846b8465=0D https://github.com/qemu/qemu/commit/d6ed27bae717ceac9de0c53a3138914= 3846b8465=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Have virtqueue_get_avail_bytes() pass caches arg to callees=0D= =0D Both virtqueue_packed_get_avail_bytes() and=0D virtqueue_split_get_avail_bytes() access the region cache, but=0D their caller also does. Simplify by having virtqueue_get_avail_bytes=0D calling both with RCU lock held, and passing the caches as argument.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-4-philmd@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: e77b6374c0b8b6e410f0d74bcba0df98dfae4cce=0D https://github.com/qemu/qemu/commit/e77b6374c0b8b6e410f0d74bcba0df9= 8dfae4cce=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: open device fd in net_init_vhost_vdpa()=0D =0D This patch switches to open device fd in net_init_vhost_vpda(). This is=0D= used to prepare for the multiqueue support.=0D =0D Reviewed-by: Stefano Garzarella =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-2-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 67262edeb5c7bb99ed86304312bb7768e92f4cd7=0D https://github.com/qemu/qemu/commit/67262edeb5c7bb99ed86304312bb776= 8e92f4cd7=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vhost-vdpa: classify one time request=0D =0D Vhost-vdpa uses one device multiqueue queue (pairs) model. So we need=0D to classify the one time request (e.g SET_OWNER) and make sure those=0D request were only called once per device.=0D =0D This is used for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-3-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0f5bfa27e1c1df21b4c874cedf18d5ac812d81e2=0D https://github.com/qemu/qemu/commit/0f5bfa27e1c1df21b4c874cedf18d5a= c812d81e2=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: prepare for the multiqueue support=0D =0D Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue=0D model. So we need to simply use virtqueue index as the vhost virtqueue=0D= index. This is a must for multiqueue to work for vhost-vdpa.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-4-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7e91ad3cafee23b780d12fcd17786617b7dbc7b8=0D https://github.com/qemu/qemu/commit/7e91ad3cafee23b780d12fcd1778661= 7b7dbc7b8=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState *=0D =0D This patch switches to let net_vhost_vdpa_init() to return=0D NetClientState *. This is used for the callers to allocate multiqueue=0D NetClientState for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-5-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 14155bf5e07ec61d8d79763d420dd152b7bea3a4=0D https://github.com/qemu/qemu/commit/14155bf5e07ec61d8d79763d420dd15= 2b7bea3a4=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/net/net.h=0D M net/net.c=0D =0D Log Message:=0D -----------=0D net: introduce control client=0D =0D This patch introduces a boolean for the device has control queue which=0D= can accepts control command via network queue.=0D =0D The first user would be the control virtqueue support for vhost.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-6-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e8af39ea3390c00d04ad516e431c347876a0bc1=0D https://github.com/qemu/qemu/commit/0e8af39ea3390c00d04ad516e431c34= 7876a0bc1=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/net/vhost_net.h=0D =0D Log Message:=0D -----------=0D vhost-net: control virtqueue support=0D =0D We assume there's no cvq in the past, this is not true when we need=0D control virtqueue support for vhost-user backends. So this patch=0D implements the control virtqueue support for vhost-net. As datapath,=0D the control virtqueue is also required to be coupled with the=0D NetClientState. The vhost_net_start/stop() are tweaked to accept the=0D number of datapath queue pairs plus the the number of control=0D virtqueue for us to start and stop the vhost device.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-7-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2ee2a97db13812e8fcfc40d4a1be06d4144f9cb2=0D https://github.com/qemu/qemu/commit/2ee2a97db13812e8fcfc40d4a1be06d= 4144f9cb2=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: use "queue_pairs" instead of "queues" when possible=0D =0D Most of the time, "queues" really means queue pairs. So this patch=0D switch to use "queue_pairs" to avoid confusion.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-8-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 183b1abfdc4c479ad36772eb7b6a19599bdb06ef=0D https://github.com/qemu/qemu/commit/183b1abfdc4c479ad36772eb7b6a195= 99bdb06ef=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M include/hw/virtio/vhost.h=0D =0D Log Message:=0D -----------=0D vhost: record the last virtqueue index for the virtio device=0D =0D This patch introduces a new field in the vhost_dev structure to record=0D= the last virtqueue index for the virtio device. This will be useful=0D for the vhost backends with 1:N model to start or stop the device=0D after all the vhost_dev structures were started or stopped.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-9-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ed78ff806c761a03e16cae67a42ab0a65b949f9c=0D https://github.com/qemu/qemu/commit/ed78ff806c761a03e16cae67a42ab0a= 65b949f9c=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: vhost control virtqueue support=0D =0D This patch implements the control virtqueue support for vhost. This=0D requires virtio-net to figure out the datapath queue pairs and control=0D= virtqueue via is_datapath and pass the number of those two types=0D of virtqueues to vhost_net_start()/vhost_net_stop().=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-10-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 5f347bcfb556e5fd8a73161d392407bafc46e1b4=0D https://github.com/qemu/qemu/commit/5f347bcfb556e5fd8a73161d392407b= afc46e1b4=0D Author: Jason Wang =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: multiqueue support=0D =0D This patch implements the multiqueue support for vhost-vdpa. This is=0D done simply by reading the number of queue pairs from the config space=0D= and initialize the datapath and control path net client.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20210907090322.1756-11-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 88f62574685dcd2184d84031aa83d1f6b70466fa=0D https://github.com/qemu/qemu/commit/88f62574685dcd2184d84031aa83d1f= 6b70466fa=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: fix migration issue when seqpacket is supported=0D =0D Commit 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D enabled the SEQPACKET feature bit.=0D This commit is released with QEMU 6.1, so if we try to migrate a VM where= =0D the host kernel supports SEQPACKET but machine type version is less than=0D= 6.1, we get the following errors:=0D =0D Features 0x130000002 unsupported. Allowed features: 0x179000000=0D Failed to load virtio-vhost_vsock:virtio=0D error while loading state for instance 0x0 of device '0000:00:05.0/vi= rtio-vhost_vsock'=0D load of migration failed: Operation not permitted=0D =0D Let's disable the feature bit for machine types < 6.1.=0D We add a new OnOffAuto property for this, called `seqpacket`.=0D When it is `auto` (default), QEMU behaves as before, trying to enable the= =0D feature, when it is `on` QEMU will fail if the backend (vhost-vsock=0D kernel module) doesn't support it.=0D =0D Fixes: 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D Cc: qemu-stable@nongnu.org=0D Reported-by: Jiang Wang =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-2-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 32a574ee57fb0d002760e179581acce44a993989=0D https://github.com/qemu/qemu/commit/32a574ee57fb0d002760e179581acce= 44a993989=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock-common.h=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: handle common features in vhost-vsock-common=0D =0D virtio-vsock features, like VIRTIO_VSOCK_F_SEQPACKET, can be handled=0D by vhost-vsock-common parent class. In this way, we can reuse the=0D same code for all virtio-vsock backends (i.e. vhost-vsock,=0D vhost-user-vsock).=0D =0D Let's move `seqpacket` property to vhost-vsock-common class, add=0D vhost_vsock_common_get_features() used by children, and disable=0D `seqpacket` for vhost-user-vsock device for machine types < 6.2.=0D =0D The behavior of vhost-vsock device doesn't change; vhost-user-vsock=0D device now supports `seqpacket` property.=0D =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-3-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 09478d3363a9e739283534edbac36afba4c34ed8=0D https://github.com/qemu/qemu/commit/09478d3363a9e739283534edbac36af= ba4c34ed8=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: add helper routines to initialize ACPI tables=0D =0D Patch introduces acpi_table_begin()/ acpi_table_end() API=0D that hides pointer/offset arithmetic from user as opposed=0D to build_header(), to prevent errors caused by it [1].=0D =0D acpi_table_begin():=0D initializes table header and keeps track of=0D table data/offsets=0D acpi_table_end():=0D sets actual table length and tells bios loader=0D where table is for the later initialization on=0D guest side.=0D =0D 1) commits=0D bb9feea43179 x86: acpi: use offset instead of pointer when using build= _header()=0D 4d027afeb3a9 Virt: ACPI: fix qemu assert due to re-assigned table data= address=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Tested-by: Stefan Berger =0D Tested-by: Yanan Wang =0D =0D =0D Commit: e524a1529a4be211b5847ec6533d12fd97e27615=0D https://github.com/qemu/qemu/commit/e524a1529a4be211b5847ec6533d12f= d97e27615=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_rsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offests magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 1df1c911635352cc29c01b1713fb14d87988174d=0D https://github.com/qemu/qemu/commit/1df1c911635352cc29c01b1713fb14d= 87988174d=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_xsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0030c5c9363cd658c62c8d19ba8dad3f36492e14=0D https://github.com/qemu/qemu/commit/0030c5c9363cd658c62c8d19ba8dad3= f36492e14=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_slit: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2122081811cb36ef5512dc1c73684d345694f646=0D https://github.com/qemu/qemu/commit/2122081811cb36ef5512dc1c73684d3= 45694f646=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_fadt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7bd982cdce0b8c9f6b3a44a39e38d66735489b4e=0D https://github.com/qemu/qemu/commit/7bd982cdce0b8c9f6b3a44a39e38d66= 735489b4e=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_tpm2: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Tested-by: Stefan Berger =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e99b4c9ce485927214a1fe38fa9985ab56bd7502=0D https://github.com/qemu/qemu/commit/e99b4c9ce485927214a1fe38fa9985a= b56bd7502=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/ghes.c=0D =0D Log Message:=0D -----------=0D acpi: acpi_build_hest: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Dongjiu Geng =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: db871b847d8d2a10a348fe17eb31230d71459bce=0D https://github.com/qemu/qemu/commit/db871b847d8d2a10a348fe17eb31230= d71459bce=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/pci.c=0D =0D Log Message:=0D -----------=0D acpi: build_mcfg: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 26f05e855fc48324430599bbef659f5571430f26=0D https://github.com/qemu/qemu/commit/26f05e855fc48324430599bbef659f5= 571430f26=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/hmat.c=0D =0D Log Message:=0D -----------=0D acpi: build_hmat: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into hmat_build_table_structs()=0D which didn have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a3e6ddb358189aaaef3d64b7601805756707638f=0D https://github.com/qemu/qemu/commit/a3e6ddb358189aaaef3d64b76018057= 56707638f=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_nfit: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into nvdimm_build_nfit() which didn't=0D have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: d5b33547cb7df335ba4c9d7c9b2fac927e466c76=0D https://github.com/qemu/qemu/commit/d5b33547cb7df335ba4c9d7c9b2fac9= 27e466c76=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_ssdt: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 33c12707725a1155763fe653f0c4d5376b7a9001=0D https://github.com/qemu/qemu/commit/33c12707725a1155763fe653f0c4d53= 76b7a9001=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/vmgenid.c=0D =0D Log Message:=0D -----------=0D acpi: vmgenid_build_acpi: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 089ae6b31adbd13888067df944c36f5e6017a595=0D https://github.com/qemu/qemu/commit/089ae6b31adbd13888067df944c36f5= e6017a595=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: x86: build_dsdt: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: eda9da9f562ab865f07c90623345122f8dccb3af=0D https://github.com/qemu/qemu/commit/eda9da9f562ab865f07c90623345122= f8dccb3af=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_hpet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it convert build_hpet() to endian agnostic=0D build_append_FOO() API=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b5381e2c9a557e4b2489cbe779d027230bfb117f=0D https://github.com/qemu/qemu/commit/b5381e2c9a557e4b2489cbe779d0272= 30bfb117f=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_tpm_tcpa: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 53e214804ac9603271df7c4d4b5d6859e89e0de1=0D https://github.com/qemu/qemu/commit/53e214804ac9603271df7c4d4b5d685= 9e89e0de1=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/x86: build_srat: use acpi_table_begin()/acpi_table_end() inst= ead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations)=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-17-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 6a18841334ab592cff9cba454bd55bba24da54da=0D https://github.com/qemu/qemu/commit/6a18841334ab592cff9cba454bd55bb= a24da54da=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M hw/acpi/nvdimm.c=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: use build_append_int_noprefix() API to compose SRAT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building SRAT tables for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-18-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 03e3fab658f4463859da9f3e81d7bd44349e02cd=0D https://github.com/qemu/qemu/commit/03e3fab658f4463859da9f3e81d7bd4= 4349e02cd=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_dmar_q35: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries tables.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-19-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3a1b846d1544df75948dd731e285523042db7892=0D https://github.com/qemu/qemu/commit/3a1b846d1544df75948dd731e285523= 042db7892=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_waet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-20-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: f7bd41b9ee4d2625a5292826f9742b946dbb676c=0D https://github.com/qemu/qemu/commit/f7bd41b9ee4d2625a5292826f9742b9= 46dbb676c=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_amd_iommu: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-21-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ddc77c9e853f5a4f375f4f79cb15ec1e5067345a=0D https://github.com/qemu/qemu/commit/ddc77c9e853f5a4f375f4f79cb15ec1= e5067345a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: madt: arm/x86: use acpi_table_begin()/acpi_table_end() instead of= build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-22-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: fd2b640c7a94367f4f9771f1709d0a6578f2300a=0D https://github.com/qemu/qemu/commit/fd2b640c7a94367f4f9771f1709d0a6= 578f2300a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: remove dead code=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-23-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b7e5349cc3cf40efd5b76758f4f0b58f1a07a05d=0D https://github.com/qemu/qemu/commit/b7e5349cc3cf40efd5b76758f4f0b58= f1a07a05d=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/cpu.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/i386/pc.h=0D =0D Log Message:=0D -----------=0D acpi: x86: set enabled when composing _MAT entries=0D =0D Instead of composing disabled _MAT entry and then later on=0D patching it to enabled for hotpluggbale CPUs in DSDT,=0D set it to enabled at the time _MAT entry is built.=0D =0D It will allow to drop usage of packed structures in=0D following patches when build_madt() is switched to use=0D build_append_int_noprefix() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-24-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 9cd66b886c234fcf0daeccbea61fad5fcbd48570=0D https://github.com/qemu/qemu/commit/9cd66b886c234fcf0daeccbea61fad5= fcbd48570=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-25-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 32a25cc9a6699f6f8831bb2b485e329d322d18d9=0D https://github.com/qemu/qemu/commit/32a25cc9a6699f6f8831bb2b485e329= d322d18d9=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-26-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b6d6df246a62e8f23032f310540e6a6b8cf6703f=0D https://github.com/qemu/qemu/commit/b6d6df246a62e8f23032f310540e6a6= b8cf6703f=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-microvm.c=0D =0D Log Message:=0D -----------=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-27-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b3b1948d1bcad7e75eed0c52478a6b3b9dcd092b=0D https://github.com/qemu/qemu/commit/b3b1948d1bcad7e75eed0c52478a6b3= b9dcd092b=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-28-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 592c6b10a9092f0d8be29eca8b3804ab9dd738b1=0D https://github.com/qemu/qemu/commit/592c6b10a9092f0d8be29eca8b3804a= b9dd738b1=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D Message-Id: <20210924122802.1455362-29-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2161751abc9f236c9f7c2b9cfa300ec5cbbc7c05=0D https://github.com/qemu/qemu/commit/2161751abc9f236c9f7c2b9cfa300ec= 5cbbc7c05=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building IORT table use endian agnostic build_append_int_noprefix()=0D= API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-30-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D =0D =0D Commit: 819e3462d9b2ba26ce90a880ca501acedfdbfc1b=0D https://github.com/qemu/qemu/commit/819e3462d9b2ba26ce90a880ca501ac= edfdbfc1b=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: fix invalid cast=0D =0D implicit cast to structure uint8_t member didn't raise error when=0D assigning value from incorrect enum, but when using build_append_gas()=0D= (next patch) it will error out with (clang):=0D implicit conversion from enumeration type 'AmlRegionSpace'=0D to different enumeration type 'AmlAddressSpace'=0D fix cast error by using correct AML_AS_SYSTEM_MEMORY enum=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-31-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 204afab68cd6fc6f63b49f8a0cf61812be25ebbe=0D https://github.com/qemu/qemu/commit/204afab68cd6fc6f63b49f8a0cf6181= 2be25ebbe=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D PS:=0D Spec is Microsoft hosted, however 1.02 is no where to be found=0D (MS lists only the current revision) and the current revision is 1.07,=0D= so bring comments in line with 1.07 as this is the only available spec.=0D= There is no content change between originally implemented 1.02=0D (using QEMU code as reference) and 1.07. The only change is renaming=0D 'Reserved2' field to 'Language', with the same 0 value.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-32-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 003ebfbc9f1aa44628995fce74074db063cf53bf=0D https://github.com/qemu/qemu/commit/003ebfbc9f1aa44628995fce74074db= 063cf53bf=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-33-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: fed6b1c0fd5e34adc73f708c337931435f00944d=0D https://github.com/qemu/qemu/commit/fed6b1c0fd5e34adc73f708c3379314= 35f00944d=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= =0D Drop usage of packed structures and explicit endian=0D conversions when building table and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-34-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0bc04aaee992c815e4fc363369e14881d069b459=0D https://github.com/qemu/qemu/commit/0bc04aaee992c815e4fc363369e1488= 1d069b459=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: remove no longer used build_header()=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-35-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 97e06bd502c4449dc51dd75a8104d1c9420b1e7a=0D https://github.com/qemu/qemu/commit/97e06bd502c4449dc51dd75a8104d1c= 9420b1e7a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-36-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 381e17fc320c8d154a79e12d7418b8c8302b1b4c=0D https://github.com/qemu/qemu/commit/381e17fc320c8d154a79e12d7418b8c= 8302b1b4c=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D =0D We are going to commit a change to fix IO address range allocated for acp= i pci=0D hotplug in q35. This affects DSDT tables. This change allows DSDT table=0D= modification so that unit tests are not broken.=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: bd53d8b309f5f4c92c9c261c3c0d9a2a170542b0=0D https://github.com/qemu/qemu/commit/bd53d8b309f5f4c92c9c261c3c0d9a2= a170542b0=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/ich9.h=0D =0D Log Message:=0D -----------=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D =0D Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D selects an IO address range for acpi based PCI hotplug for q35 arbitraril= y. It=0D starts at address 0x0cc4 and ends at 0x0cdb. At the time when the patch w= as=0D written but the final version of the patch was not yet pushed upstream, t= his=0D address range was free and did not conflict with any other IO address ran= ges.=0D However, with the following change, this address range was no=0D longer conflict free as in this change, the IO address range=0D (value of ACPI_PCIHP_SIZE) was incremented by four bytes:=0D =0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D This can be seen from the output of QMP command 'info mtree' :=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc4-0000000000000cdb (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D It shows that there is a region of conflict between IO regions of acpi=0D= pci hotplug and acpi cpu hotplug.=0D =0D Unfortunately, the change caf108bc58790 did not update the IO address ran= ge=0D appropriately before it was pushed upstream to accommodate the increased=0D= length of the IO address space introduced in change b32bd763a1ca92.=0D =0D Due to this bug, windows guests complain 'This device cannot find=0D enough free resources it can use' in the device manager panel for extende= d=0D IO buses. This issue also breaks the correct functioning of pci hotplug a= s the=0D following shows that the IO space for pci hotplug has been truncated:=0D =0D (qemu) info mtree -f=0D FlatView #0=0D AS "I/O", root: io=0D Root memory region: io=0D 0000000000000cc4-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000cf7 (prio 0, i/o): acpi-cpu-hotplug=0D =0D Therefore, in this fix, we adjust the IO address range for the acpi pci=0D= hotplug so that it does not conflict with cpu hotplug and there is no=0D truncation of IO spaces. The starting IO address of PCI hotplug region=0D= has been decremented by four bytes in order to accommodate four byte=0D increment in the IO address space introduced by change=0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D After fixing, the following are the corrected IO ranges:=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc0-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D This change has been tested using a Windows Server 2019 guest VM. Windows= =0D no longer complains after this change.=0D =0D Fixes: caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/561=0D =0D Signed-off-by: Ani Sinha =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Julia Suvorova =0D Message-Id: <20210916132838.3469580-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 6cb1169b3fd6b22b309352c80989ae3248c1bc2b=0D https://github.com/qemu/qemu/commit/6cb1169b3fd6b22b309352c80989ae3= 248c1bc2b=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D =0D We have modified the IO address range for ACPI pci hotplug in q35. See ch= ange:=0D =0D 5adcc9e39e6a5 ("hw/i386/acpi: fix conflicting IO address range for acpi p= ci hotplug in q35")=0D =0D The ACPI DSDT table golden blobs must be regenrated in order to make the = unit tests=0D pass. This change updates the golden ACPI DSDT table blobs.=0D =0D Following is the ASL diff between the blobs:=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Tue Sep 14 09:04:06 2021=0D + * Disassembly of /tmp/aml-52DP90, Tue Sep 14 09:04:06 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D * Length 0x00002061 (8289)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xE5=0D + * Checksum 0xF9=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -226,46 +226,46 @@=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D 0x0070, // Range Minimum=0D 0x0070, // Range Maximum=0D 0x01, // Alignment=0D 0x08, // Length=0D )=0D IRQNoFlags ()=0D {8}=0D })=0D }=0D }=0D =0D Scope (_SB.PCI0)=0D {=0D - OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)=0D + OperationRegion (PCST, SystemIO, 0x0CC0, 0x08)=0D Field (PCST, DWordAcc, NoLock, WriteAsZeros)=0D {=0D PCIU, 32,=0D PCID, 32=0D }=0D =0D - OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04)=0D + OperationRegion (SEJ, SystemIO, 0x0CC8, 0x04)=0D Field (SEJ, DWordAcc, NoLock, WriteAsZeros)=0D {=0D B0EJ, 32=0D }=0D =0D - OperationRegion (BNMR, SystemIO, 0x0CD4, 0x08)=0D + OperationRegion (BNMR, SystemIO, 0x0CD0, 0x08)=0D Field (BNMR, DWordAcc, NoLock, WriteAsZeros)=0D {=0D BNUM, 32,=0D PIDX, 32=0D }=0D =0D Mutex (BLCK, 0x00)=0D Method (PCEJ, 2, NotSerialized)=0D {=0D Acquire (BLCK, 0xFFFF)=0D BNUM =3D Arg0=0D B0EJ =3D (One << Arg1)=0D Release (BLCK)=0D Return (Zero)=0D }=0D =0D @@ -3185,34 +3185,34 @@=0D 0x0620, // Range Minimum=0D 0x0620, // Range Maximum=0D 0x01, // Alignment=0D 0x10, // Length=0D )=0D })=0D }=0D =0D Device (PHPR)=0D {=0D Name (_HID, "PNP0A06" /* Generic Container Device */) // _H= ID: Hardware ID=0D Name (_UID, "PCI Hotplug resources") // _UID: Unique ID=0D Name (_STA, 0x0B) // _STA: Status=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D - 0x0CC4, // Range Minimum=0D - 0x0CC4, // Range Maximum=0D + 0x0CC0, // Range Minimum=0D + 0x0CC0, // Range Maximum=0D 0x01, // Alignment=0D 0x18, // Length=0D )=0D })=0D }=0D }=0D =0D Scope (\)=0D {=0D Name (_S3, Package (0x04) // _S3_: S3 System State=0D {=0D One,=0D One,=0D Zero,=0D Zero=0D })=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b6724f4e3b8266451317ab1406c299bf96be85e3=0D https://github.com/qemu/qemu/commit/b6724f4e3b8266451317ab1406c299b= f96be85e3=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-balloon.c=0D =0D Log Message:=0D -----------=0D virtio-balloon: Fix page-poison subsection name=0D =0D The subsection name for page-poison was typo'd as:=0D =0D vitio-balloon-device/page-poison=0D =0D Note the missing 'r' in virtio.=0D =0D When we have a machine type that enables page poison, and the guest=0D enables it (which needs a new kernel), things fail rather unpredictably.=0D= =0D The fallout from this is that most of the other subsections fail to=0D load, including things like the feature bits in the device, one=0D possible fallout is that the physical addresses of the queues=0D then get aligned differently and we fail with an error about=0D last_avail_idx being wrong.=0D It's not obvious to me why this doesn't produce a more obvious failure,=0D= but virtio's vmstate loading is a bit open-coded.=0D =0D Fixes: 7483cbbaf82 ("virtio-balloon: Implement support for page poison re= porting feature")=0D bz: https://bugzilla.redhat.com/show_bug.cgi?id=3D1984401=0D Signed-off-by: Dr. David Alan Gilbert =0D Message-Id: <20210914131716.102851-1-dgilbert@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: David Hildenbrand =0D =0D =0D Commit: 4d6e10f271300d5f0f60384a35dbfc38636647b1=0D https://github.com/qemu/qemu/commit/4d6e10f271300d5f0f60384a35dbfc3= 8636647b1=0D Author: Li Zhijian =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D nvdimm: release the correct device list=0D =0D Signed-off-by: Li Zhijian =0D Message-Id: <20210624110415.187164-1-lizhijian@cn.fujitsu.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: 0d1d97af593d15da038f97ba7a4c1020b7edcacc=0D https://github.com/qemu/qemu/commit/0d1d97af593d15da038f97ba7a4c102= 0b7edcacc=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D =0D Per 'QEMU Coding Style':=0D =0D Naming=0D =3D=3D=3D=3D=3D=3D=0D Variables are lower_case_with_underscores; easy to type and read.=0D =0D Rename amdviPCI variable as amdvi_pci.=0D =0D amdviPCI_register_types() register more than PCI types:=0D TYPE_AMD_IOMMU_DEVICE inherits TYPE_X86_IOMMU_DEVICE which=0D itself inherits TYPE_SYS_BUS_DEVICE.=0D =0D Rename it more generically as amdvi_register_types().=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-2-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ada929de88fe407980ef10f65ac300388489fe88=0D https://github.com/qemu/qemu/commit/ada929de88fe407980ef10f65ac3003= 88489fe88=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D =0D Various functions are SysBus specific. Rename them using the=0D consistent amdvi_sysbus_XXX() pattern, to differentiate them=0D from PCI specific functions (which we'll add in the next=0D commit).=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-3-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c7d2f59cf940b8c8c52c29d5fa25613fe662f7b6=0D https://github.com/qemu/qemu/commit/c7d2f59cf940b8c8c52c29d5fa25613= fe662f7b6=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D =0D TYPE_AMD_IOMMU_PCI is user-creatable but not well described.=0D Implement its class_init() handler to add it to the 'Misc=0D devices' category, and add a description.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-4-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: dfaac50f1e4f3e5c74b18b617d9ba5d264e0051b=0D https://github.com/qemu/qemu/commit/dfaac50f1e4f3e5c74b18b617d9ba5d= 264e0051b=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/aml-build.c=0D M hw/acpi/cpu.c=0D M hw/acpi/ghes.c=0D M hw/acpi/hmat.c=0D M hw/acpi/nvdimm.c=0D M hw/acpi/pci.c=0D M hw/acpi/vmgenid.c=0D M hw/arm/virt-acpi-build.c=0D M hw/core/machine.c=0D M hw/i386/acpi-build.c=0D M hw/i386/acpi-common.c=0D M hw/i386/acpi-microvm.c=0D M hw/i386/amd_iommu.c=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vdpa.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M hw/virtio/virtio-balloon.c=0D M hw/virtio/virtio.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/acpi/aml-build.h=0D M include/hw/acpi/ich9.h=0D M include/hw/i386/pc.h=0D M include/hw/virtio/vhost-vdpa.h=0D M include/hw/virtio/vhost-vsock-common.h=0D M include/hw/virtio/vhost.h=0D M include/hw/virtio/virtio-net.h=0D M include/net/net.h=0D M include/net/vhost_net.h=0D M net/net.c=0D M net/vhost-vdpa.c=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes=0D =0D VDPA multiqueue support.=0D A huge acpi refactoring.=0D Fixes, cleanups all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Tue 05 Oct 2021 08:59:13 AM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (57 commits)=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D nvdimm: release the correct device list=0D virtio-balloon: Fix page-poison subsection name=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D acpi: remove no longer used build_header()=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: fix invalid cast=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/9618c5badaa8...dfaac50f1e4f= =0D From MAILER-DAEMON Tue Oct 05 14:31:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXpDx-0001oi-2J for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 14:31:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXpDq-0001my-Fc for qemu-commits@nongnu.org; Tue, 05 Oct 2021 14:31:28 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:38525 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXpDn-0006mj-49 for qemu-commits@nongnu.org; Tue, 05 Oct 2021 14:31:25 -0400 Received: from github.com (hubbernetes-node-b070adf.ash1-iad.github.net [10.56.112.33]) by smtp.github.com (Postfix) with ESMTPA id 5E6D28407DD for ; Tue, 5 Oct 2021 11:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633458682; bh=Xd41TIZRaFcZfxMoftVSp2NFdbEfqVnl2kIs/dUODPI=; h=Date:From:To:Subject:From; b=isMySvZvGrp/IgsDlji49+om5YO9v6Bxv9ad+GxnpWO00upH+HDzImD6nxoKlK8qR PGnAmsBZWTwGeFfJod0Xx12gold7rx2ZsTrA1pSiwGHheHvd6XmP54n7ZMq5KHoM3k S7N4HywnLF20Soqjeou3WE3gxJ7uaD1M1oQZYJ/M= Date: Tue, 05 Oct 2021 11:31:22 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7f7c8d: i386: docs: Briefly describe KVM PV features X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 18:31:28 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 7f7c8d0ce3630849a4df3d627b11de354fcb3bb0=0D https://github.com/qemu/qemu/commit/7f7c8d0ce3630849a4df3d627b11de3= 54fcb3bb0=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A docs/system/i386/kvm-pv.rst=0D M docs/system/target-i386.rst=0D =0D Log Message:=0D -----------=0D i386: docs: Briefly describe KVM PV features=0D =0D KVM PV features don't seem to be documented anywhere, in particular, the=0D= fact that some of the features are enabled by default and some are not ca= n=0D only be figured out from the code.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20211004140445.624875-1-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cff03145ed3cec5c7bd542ea2e6b4458439e0bb0=0D https://github.com/qemu/qemu/commit/cff03145ed3cec5c7bd542ea2e6b445= 8439e0bb0=0D Author: Dov Murik =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D sev/i386: Introduce sev_add_kernel_loader_hashes for measured linux boo= t=0D =0D Add the sev_add_kernel_loader_hashes function to calculate the hashes of=0D= the kernel/initrd/cmdline and fill a designated OVMF encrypted hash=0D table area. For this to work, OVMF must support an encrypted area to=0D place the data which is advertised via a special GUID in the OVMF reset=0D= table.=0D =0D The hashes of each of the files is calculated (or the string in the case=0D= of the cmdline with trailing '\0' included). Each entry in the hashes=0D= table is GUID identified and since they're passed through the=0D sev_encrypt_flash interface, the hashes will be accumulated by the AMD=0D= PSP measurement (SEV_LAUNCH_MEASURE).=0D =0D Co-developed-by: James Bottomley =0D Signed-off-by: James Bottomley =0D Signed-off-by: Dov Murik =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930054915.13252-2-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: c0c2d319d6714517cc4e0332edf99f2fccaa9442=0D https://github.com/qemu/qemu/commit/c0c2d319d6714517cc4e0332edf99f2= fccaa9442=0D Author: Dov Murik =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/x86.c=0D =0D Log Message:=0D -----------=0D x86/sev: generate SEV kernel loader hashes in x86_load_linux=0D =0D If SEV is enabled and a kernel is passed via -kernel, pass the hashes of=0D= kernel/initrd/cmdline in an encrypted guest page to OVMF for SEV=0D measured boot.=0D =0D Co-developed-by: James Bottomley =0D Signed-off-by: James Bottomley =0D Signed-off-by: Dov Murik =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930054915.13252-3-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 93ddefbc3c909bb6c3b76086f1dfc8ad98dd3725=0D https://github.com/qemu/qemu/commit/93ddefbc3c909bb6c3b76086f1dfc8a= d98dd3725=0D Author: Pedro To=CC=82rres =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/misc/applesmc.c=0D =0D Log Message:=0D -----------=0D hw/misc: applesmc: use host osk as default on macs=0D =0D When running on a Mac, QEMU is able to get the host OSK and use it as=0D the default value for the AppleSMC device. The OSK query operation=0D doesn't require administrator privileges and can be executed by any user=0D= on the system. This patch is based on open-source code from Apple, just=0D= like the implementation from VirtualBox.=0D =0D Apple:=0D https://opensource.apple.com/source/IOKitUser/IOKitUser-647.6.13/pwr_mgt.= subproj/IOPMLibPrivate.c=0D https://opensource.apple.com/source/PowerManagement/PowerManagement-637.6= 0.1/pmconfigd/PrivateLib.c=0D =0D VirtualBox:=0D https://www.virtualbox.org/browser/vbox/trunk/src/VBox/Devices/EFI/DevSmc= .cpp#L516=0D =0D Signed-off-by: Pedro To=CC=82rres =0D =0D =0D Commit: 4dba27890844146d69e84916d024697947821655=0D https://github.com/qemu/qemu/commit/4dba27890844146d69e84916d024697= 947821655=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure, meson: move CPU_CFLAGS out of QEMU_CFLAGS=0D =0D Flags that choose the target architecture, such as -m32 on x86, affect=0D= all invocations of the compiler driver, for example including options=0D such as --print-search-dirs. To ensure that they are treated as such,=0D= place them in the cross file in the [binaries] section instead of=0D including them in QEMU_CFLAGS.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3c158eba1e11e52dbd0e14fc8fd40ec80abca436=0D https://github.com/qemu/qemu/commit/3c158eba1e11e52dbd0e14fc8fd40ec= 80abca436=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M migration/block-dirty-bitmap.c=0D =0D Log Message:=0D -----------=0D migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread=0D =0D init_dirty_bitmap_migration assumes the iothread lock (BQL)=0D to be held, but instead it isn't.=0D =0D Instead of adding the lock to qemu_savevm_state_setup(),=0D follow the same pattern as the other ->save_setup callbacks=0D and lock+unlock inside dirty_bitmap_save_setup().=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Reviewed-by: Stefan Hajnoczi =0D Message-Id: <20211005080751.3797161-2-eesposit@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 68b88468f6a4144bf0217624fbb0ff6b0fa1d694=0D https://github.com/qemu/qemu/commit/68b88468f6a4144bf0217624fbb0ff6= b0fa1d694=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D =0D Log Message:=0D -----------=0D migration: add missing qemu_mutex_lock_iothread in migration_completion= =0D =0D qemu_savevm_state_complete_postcopy assumes the iothread lock (BQL)=0D to be held, but instead it isn't.=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211005080751.3797161-3-eesposit@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69c4c5c1c47f5dac140eb6485c5281a9f145dcf3=0D https://github.com/qemu/qemu/commit/69c4c5c1c47f5dac140eb6485c5281a= 9f145dcf3=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson=0D =0D Log Message:=0D -----------=0D meson: bump submodule to 0.59.2=0D =0D The update to 0.57 has been delayed due to it causing warnings for=0D some actual issues, but it brings in important bugfixes and new=0D features. 0.58 also brings in a bugfix that is useful for modinfo.=0D =0D Important bugfixes:=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/7760, build: use PIE=0D objects for non-PIC static libraries if b_pie=3Dtrue=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/7900, thus avoiding=0D unnecessary rebuilds after running meson.=0D =0D - 0.58.2: https://github.com/mesonbuild/meson/pull/8900, fixes for=0D passing extract_objects() to custom_target (useful for modinfo)=0D =0D Features:=0D =0D - 0.57: the keyval module has now been stabilized=0D =0D - 0.57: env argument to custom_target (useful for hexagon)=0D =0D - 0.57: Feature parity between "meson test" and QEMU's TAP driver=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/8231, allows bringing=0D= back version numbers in the configuration summary=0D =0D - 0.59: Utility methods for feature objects=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 654d6b0453aa6eb19af0d75b0f087a97a5776da7=0D https://github.com/qemu/qemu/commit/654d6b0453aa6eb19af0d75b0f087a9= 7a5776da7=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D M meson.build=0D M plugins/meson.build=0D M scripts/mtest2make.py=0D M tests/qapi-schema/meson.build=0D M tests/qtest/meson.build=0D M tests/unit/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D meson: switch minimum meson version to 0.58.2, minimum recommended to 0= .59.2=0D =0D Meson 0.58.2 does not need b_staticpic=3D$pie anymore, and has=0D stabilized the keyval module. Remove the workaround and use a few=0D replacements for features deprecated in the 0.57.0 release cycle.=0D =0D One feature that we would like to use is passing dependencies to=0D summary. However, that was broken in 0.59.0 and 0.59.1. Therefore,=0D use the embedded Meson if the host has anything older than 0.59.2,=0D but allow --meson=3D to use 0.58.2.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0a11c44e891221a584bf06e75871dd1425555a65=0D https://github.com/qemu/qemu/commit/0a11c44e891221a584bf06e75871dd1= 425555a65=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/meson.build=0D =0D Log Message:=0D -----------=0D hexagon: use env keyword argument to pass PYTHONPATH=0D =0D This feature is new in meson 0.57 and allows getting rid of the "env" wra= pper.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2796032a51c635464481a9212e941da53b3b3a61=0D https://github.com/qemu/qemu/commit/2796032a51c635464481a9212e941da= 53b3b3a61=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A target/xtensa/cores.list=0D M target/xtensa/import_core.sh=0D M target/xtensa/meson.build=0D =0D Log Message:=0D -----------=0D target/xtensa: list cores in a text file=0D =0D Avoid that leftover files affect the build; instead, use the same=0D mechanism that was in place before the Meson transition of updating=0D a file from import_core.sh. Starting with Meson 0.57, the file=0D can be easily read from the filesystem module, so do that instead=0D of using run_command.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bb647c49b8f1f986d8171dd61db65e8a8d255be0=0D https://github.com/qemu/qemu/commit/bb647c49b8f1f986d8171dd61db65e8= a8d255be0=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: show library versions in the summary=0D =0D Meson 0.57 allows passing external programs and dependency objects=0D to summary(). Use this to show library versions and paths in the=0D summary.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 08a9b68dc033c9826da89f84202e547beadd92f0=0D https://github.com/qemu/qemu/commit/08a9b68dc033c9826da89f84202e547= beadd92f0=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D A docs/system/i386/kvm-pv.rst=0D M docs/system/target-i386.rst=0D M hw/i386/x86.c=0D M hw/misc/applesmc.c=0D M meson=0D M meson.build=0D M migration/block-dirty-bitmap.c=0D M migration/migration.c=0D M plugins/meson.build=0D M scripts/mtest2make.py=0D M target/hexagon/meson.build=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D A target/xtensa/cores.list=0D M target/xtensa/import_core.sh=0D M target/xtensa/meson.build=0D M tests/qapi-schema/meson.build=0D M tests/qtest/meson.build=0D M tests/unit/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * Meson version update=0D * fix search path when configuring with --cpu=0D * support for measured SEV boot with -kernel (Dov)=0D * fix missing BQL locks (Emanuele)=0D * retrieve applesmc key from the host (Pedro)=0D * KVM PV feature documentation (Vitaly)=0D =0D # gpg: Signature made Tue 05 Oct 2021 04:13:00 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream:=0D meson: show library versions in the summary=0D target/xtensa: list cores in a text file=0D hexagon: use env keyword argument to pass PYTHONPATH=0D meson: switch minimum meson version to 0.58.2, minimum recommended to 0= .59.2=0D meson: bump submodule to 0.59.2=0D migration: add missing qemu_mutex_lock_iothread in migration_completion= =0D migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread=0D configure, meson: move CPU_CFLAGS out of QEMU_CFLAGS=0D hw/misc: applesmc: use host osk as default on macs=0D x86/sev: generate SEV kernel loader hashes in x86_load_linux=0D sev/i386: Introduce sev_add_kernel_loader_hashes for measured linux boo= t=0D i386: docs: Briefly describe KVM PV features=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/dfaac50f1e4f...08a9b68dc033= =0D From MAILER-DAEMON Tue Oct 05 17:34:08 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXs4e-0004J0-Dl for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 17:34:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXs4O-0004IA-KN for qemu-commits@nongnu.org; Tue, 05 Oct 2021 17:33:54 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:40709 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXs4L-0004uN-3d for qemu-commits@nongnu.org; Tue, 05 Oct 2021 17:33:52 -0400 Received: from github.com (hubbernetes-node-1d96ffd.ash1-iad.github.net [10.56.112.39]) by smtp.github.com (Postfix) with ESMTPA id 3C4B5840849 for ; Tue, 5 Oct 2021 14:33:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633469628; bh=qUm255HfSYsH24X2f6eOo4V2KTAxrDCh4yaaUC3rDfc=; h=Date:From:To:Subject:From; b=HrqBSHUfraQ9DIQtj7gm3vEra1Ks4AlynTDfuJn//iy/giBbgQysi7KZiSVCAoBad iHx7yFrXptc7dCB5mvE4FfoN03ID69yp2/e89qzZvsCxiJD+Qc2OIcESRZ9XuBCPHn az5FoKsIAfiypGcgLynCce1Fl0QZgpMVAnByVflw= Date: Tue, 05 Oct 2021 14:33:48 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7f7c8d: i386: docs: Briefly describe KVM PV features X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 21:33:56 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 7f7c8d0ce3630849a4df3d627b11de354fcb3bb0=0D https://github.com/qemu/qemu/commit/7f7c8d0ce3630849a4df3d627b11de3= 54fcb3bb0=0D Author: Vitaly Kuznetsov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A docs/system/i386/kvm-pv.rst=0D M docs/system/target-i386.rst=0D =0D Log Message:=0D -----------=0D i386: docs: Briefly describe KVM PV features=0D =0D KVM PV features don't seem to be documented anywhere, in particular, the=0D= fact that some of the features are enabled by default and some are not ca= n=0D only be figured out from the code.=0D =0D Signed-off-by: Vitaly Kuznetsov =0D Message-Id: <20211004140445.624875-1-vkuznets@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cff03145ed3cec5c7bd542ea2e6b4458439e0bb0=0D https://github.com/qemu/qemu/commit/cff03145ed3cec5c7bd542ea2e6b445= 8439e0bb0=0D Author: Dov Murik =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D sev/i386: Introduce sev_add_kernel_loader_hashes for measured linux boo= t=0D =0D Add the sev_add_kernel_loader_hashes function to calculate the hashes of=0D= the kernel/initrd/cmdline and fill a designated OVMF encrypted hash=0D table area. For this to work, OVMF must support an encrypted area to=0D place the data which is advertised via a special GUID in the OVMF reset=0D= table.=0D =0D The hashes of each of the files is calculated (or the string in the case=0D= of the cmdline with trailing '\0' included). Each entry in the hashes=0D= table is GUID identified and since they're passed through the=0D sev_encrypt_flash interface, the hashes will be accumulated by the AMD=0D= PSP measurement (SEV_LAUNCH_MEASURE).=0D =0D Co-developed-by: James Bottomley =0D Signed-off-by: James Bottomley =0D Signed-off-by: Dov Murik =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930054915.13252-2-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: c0c2d319d6714517cc4e0332edf99f2fccaa9442=0D https://github.com/qemu/qemu/commit/c0c2d319d6714517cc4e0332edf99f2= fccaa9442=0D Author: Dov Murik =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/x86.c=0D =0D Log Message:=0D -----------=0D x86/sev: generate SEV kernel loader hashes in x86_load_linux=0D =0D If SEV is enabled and a kernel is passed via -kernel, pass the hashes of=0D= kernel/initrd/cmdline in an encrypted guest page to OVMF for SEV=0D measured boot.=0D =0D Co-developed-by: James Bottomley =0D Signed-off-by: James Bottomley =0D Signed-off-by: Dov Murik =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930054915.13252-3-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 93ddefbc3c909bb6c3b76086f1dfc8ad98dd3725=0D https://github.com/qemu/qemu/commit/93ddefbc3c909bb6c3b76086f1dfc8a= d98dd3725=0D Author: Pedro To=CC=82rres =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/misc/applesmc.c=0D =0D Log Message:=0D -----------=0D hw/misc: applesmc: use host osk as default on macs=0D =0D When running on a Mac, QEMU is able to get the host OSK and use it as=0D the default value for the AppleSMC device. The OSK query operation=0D doesn't require administrator privileges and can be executed by any user=0D= on the system. This patch is based on open-source code from Apple, just=0D= like the implementation from VirtualBox.=0D =0D Apple:=0D https://opensource.apple.com/source/IOKitUser/IOKitUser-647.6.13/pwr_mgt.= subproj/IOPMLibPrivate.c=0D https://opensource.apple.com/source/PowerManagement/PowerManagement-637.6= 0.1/pmconfigd/PrivateLib.c=0D =0D VirtualBox:=0D https://www.virtualbox.org/browser/vbox/trunk/src/VBox/Devices/EFI/DevSmc= .cpp#L516=0D =0D Signed-off-by: Pedro To=CC=82rres =0D =0D =0D Commit: 4dba27890844146d69e84916d024697947821655=0D https://github.com/qemu/qemu/commit/4dba27890844146d69e84916d024697= 947821655=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure, meson: move CPU_CFLAGS out of QEMU_CFLAGS=0D =0D Flags that choose the target architecture, such as -m32 on x86, affect=0D= all invocations of the compiler driver, for example including options=0D such as --print-search-dirs. To ensure that they are treated as such,=0D= place them in the cross file in the [binaries] section instead of=0D including them in QEMU_CFLAGS.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3c158eba1e11e52dbd0e14fc8fd40ec80abca436=0D https://github.com/qemu/qemu/commit/3c158eba1e11e52dbd0e14fc8fd40ec= 80abca436=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M migration/block-dirty-bitmap.c=0D =0D Log Message:=0D -----------=0D migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread=0D =0D init_dirty_bitmap_migration assumes the iothread lock (BQL)=0D to be held, but instead it isn't.=0D =0D Instead of adding the lock to qemu_savevm_state_setup(),=0D follow the same pattern as the other ->save_setup callbacks=0D and lock+unlock inside dirty_bitmap_save_setup().=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Reviewed-by: Stefan Hajnoczi =0D Message-Id: <20211005080751.3797161-2-eesposit@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 68b88468f6a4144bf0217624fbb0ff6b0fa1d694=0D https://github.com/qemu/qemu/commit/68b88468f6a4144bf0217624fbb0ff6= b0fa1d694=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D =0D Log Message:=0D -----------=0D migration: add missing qemu_mutex_lock_iothread in migration_completion= =0D =0D qemu_savevm_state_complete_postcopy assumes the iothread lock (BQL)=0D to be held, but instead it isn't.=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211005080751.3797161-3-eesposit@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69c4c5c1c47f5dac140eb6485c5281a9f145dcf3=0D https://github.com/qemu/qemu/commit/69c4c5c1c47f5dac140eb6485c5281a= 9f145dcf3=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson=0D =0D Log Message:=0D -----------=0D meson: bump submodule to 0.59.2=0D =0D The update to 0.57 has been delayed due to it causing warnings for=0D some actual issues, but it brings in important bugfixes and new=0D features. 0.58 also brings in a bugfix that is useful for modinfo.=0D =0D Important bugfixes:=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/7760, build: use PIE=0D objects for non-PIC static libraries if b_pie=3Dtrue=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/7900, thus avoiding=0D unnecessary rebuilds after running meson.=0D =0D - 0.58.2: https://github.com/mesonbuild/meson/pull/8900, fixes for=0D passing extract_objects() to custom_target (useful for modinfo)=0D =0D Features:=0D =0D - 0.57: the keyval module has now been stabilized=0D =0D - 0.57: env argument to custom_target (useful for hexagon)=0D =0D - 0.57: Feature parity between "meson test" and QEMU's TAP driver=0D =0D - 0.57: https://github.com/mesonbuild/meson/pull/8231, allows bringing=0D= back version numbers in the configuration summary=0D =0D - 0.59: Utility methods for feature objects=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 654d6b0453aa6eb19af0d75b0f087a97a5776da7=0D https://github.com/qemu/qemu/commit/654d6b0453aa6eb19af0d75b0f087a9= 7a5776da7=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D M meson.build=0D M plugins/meson.build=0D M scripts/mtest2make.py=0D M tests/qapi-schema/meson.build=0D M tests/qtest/meson.build=0D M tests/unit/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D meson: switch minimum meson version to 0.58.2, minimum recommended to 0= .59.2=0D =0D Meson 0.58.2 does not need b_staticpic=3D$pie anymore, and has=0D stabilized the keyval module. Remove the workaround and use a few=0D replacements for features deprecated in the 0.57.0 release cycle.=0D =0D One feature that we would like to use is passing dependencies to=0D summary. However, that was broken in 0.59.0 and 0.59.1. Therefore,=0D use the embedded Meson if the host has anything older than 0.59.2,=0D but allow --meson=3D to use 0.58.2.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0a11c44e891221a584bf06e75871dd1425555a65=0D https://github.com/qemu/qemu/commit/0a11c44e891221a584bf06e75871dd1= 425555a65=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/meson.build=0D =0D Log Message:=0D -----------=0D hexagon: use env keyword argument to pass PYTHONPATH=0D =0D This feature is new in meson 0.57 and allows getting rid of the "env" wra= pper.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2796032a51c635464481a9212e941da53b3b3a61=0D https://github.com/qemu/qemu/commit/2796032a51c635464481a9212e941da= 53b3b3a61=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A target/xtensa/cores.list=0D M target/xtensa/import_core.sh=0D M target/xtensa/meson.build=0D =0D Log Message:=0D -----------=0D target/xtensa: list cores in a text file=0D =0D Avoid that leftover files affect the build; instead, use the same=0D mechanism that was in place before the Meson transition of updating=0D a file from import_core.sh. Starting with Meson 0.57, the file=0D can be easily read from the filesystem module, so do that instead=0D of using run_command.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bb647c49b8f1f986d8171dd61db65e8a8d255be0=0D https://github.com/qemu/qemu/commit/bb647c49b8f1f986d8171dd61db65e8= a8d255be0=0D Author: Paolo Bonzini =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: show library versions in the summary=0D =0D Meson 0.57 allows passing external programs and dependency objects=0D to summary(). Use this to show library versions and paths in the=0D summary.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 08a9b68dc033c9826da89f84202e547beadd92f0=0D https://github.com/qemu/qemu/commit/08a9b68dc033c9826da89f84202e547= beadd92f0=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D A docs/system/i386/kvm-pv.rst=0D M docs/system/target-i386.rst=0D M hw/i386/x86.c=0D M hw/misc/applesmc.c=0D M meson=0D M meson.build=0D M migration/block-dirty-bitmap.c=0D M migration/migration.c=0D M plugins/meson.build=0D M scripts/mtest2make.py=0D M target/hexagon/meson.build=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D A target/xtensa/cores.list=0D M target/xtensa/import_core.sh=0D M target/xtensa/meson.build=0D M tests/qapi-schema/meson.build=0D M tests/qtest/meson.build=0D M tests/unit/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * Meson version update=0D * fix search path when configuring with --cpu=0D * support for measured SEV boot with -kernel (Dov)=0D * fix missing BQL locks (Emanuele)=0D * retrieve applesmc key from the host (Pedro)=0D * KVM PV feature documentation (Vitaly)=0D =0D # gpg: Signature made Tue 05 Oct 2021 04:13:00 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream:=0D meson: show library versions in the summary=0D target/xtensa: list cores in a text file=0D hexagon: use env keyword argument to pass PYTHONPATH=0D meson: switch minimum meson version to 0.58.2, minimum recommended to 0= .59.2=0D meson: bump submodule to 0.59.2=0D migration: add missing qemu_mutex_lock_iothread in migration_completion= =0D migration: block-dirty-bitmap: add missing qemu_mutex_lock_iothread=0D configure, meson: move CPU_CFLAGS out of QEMU_CFLAGS=0D hw/misc: applesmc: use host osk as default on macs=0D x86/sev: generate SEV kernel loader hashes in x86_load_linux=0D sev/i386: Introduce sev_add_kernel_loader_hashes for measured linux boo= t=0D i386: docs: Briefly describe KVM PV features=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/9618c5badaa8...08a9b68dc033= =0D From MAILER-DAEMON Tue Oct 05 17:42:21 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXsCb-0002zZ-Ip for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 17:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXsCa-0002zG-4i for qemu-commits@nongnu.org; Tue, 05 Oct 2021 17:42:20 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:45759 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXsCV-0005re-Fl for qemu-commits@nongnu.org; Tue, 05 Oct 2021 17:42:19 -0400 Received: from github.com (hubbernetes-node-48df57d.ash1-iad.github.net [10.56.116.38]) by smtp.github.com (Postfix) with ESMTPA id CAE6D840591 for ; Tue, 5 Oct 2021 14:42:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633470134; bh=fvV9UAWgEjcafmr1518I51ZagQ5Ke6j5SVpImIJl4sM=; h=Date:From:To:Subject:From; b=NZ3YlhmMLODbfSCpVJWYEEHSMvXFueo1gYK+Mvlb685E+uleFrmbwHVTGc7p/ojs2 6y/WrMXiaED3+rJtiBfi5/4PvIdHBLgfKe9VX6R+64hi92N6auVYnBVJ1acvZLOQQM 6KKghlWHi8b1QaOj0uAkRqoIe2TxftEqNaniHPCU= Date: Tue, 05 Oct 2021 14:42:14 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ab4dd2: hw/virtio: Acquire RCU read lock in virtqueue_pack... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 21:42:20 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: ab4dd2746c234f038206b3ccfe6bec1f19f98c24=0D https://github.com/qemu/qemu/commit/ab4dd2746c234f038206b3ccfe6bec1= f19f98c24=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Acquire RCU read lock in virtqueue_packed_drop_all()=0D =0D vring_get_region_caches() must be called with the RCU read lock=0D acquired. virtqueue_packed_drop_all() does not, and uses the=0D 'caches' pointer. Fix that by using the RCU_READ_LOCK_GUARD()=0D macro.=0D =0D Reported-by: Stefano Garzarella =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-3-philmd@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: d6ed27bae717ceac9de0c53a31389143846b8465=0D https://github.com/qemu/qemu/commit/d6ed27bae717ceac9de0c53a3138914= 3846b8465=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Have virtqueue_get_avail_bytes() pass caches arg to callees=0D= =0D Both virtqueue_packed_get_avail_bytes() and=0D virtqueue_split_get_avail_bytes() access the region cache, but=0D their caller also does. Simplify by having virtqueue_get_avail_bytes=0D calling both with RCU lock held, and passing the caches as argument.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-4-philmd@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: d6a9378f47515c6d70dbff4912c5740c98709880=0D https://github.com/qemu/qemu/commit/d6a9378f47515c6d70dbff4912c5740= c98709880=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: fix migration issue when seqpacket is supported=0D =0D Commit 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D enabled the SEQPACKET feature bit.=0D This commit is released with QEMU 6.1, so if we try to migrate a VM where= =0D the host kernel supports SEQPACKET but machine type version is less than=0D= 6.1, we get the following errors:=0D =0D Features 0x130000002 unsupported. Allowed features: 0x179000000=0D Failed to load virtio-vhost_vsock:virtio=0D error while loading state for instance 0x0 of device '0000:00:05.0/vi= rtio-vhost_vsock'=0D load of migration failed: Operation not permitted=0D =0D Let's disable the feature bit for machine types < 6.1.=0D We add a new OnOffAuto property for this, called `seqpacket`.=0D When it is `auto` (default), QEMU behaves as before, trying to enable the= =0D feature, when it is `on` QEMU will fail if the backend (vhost-vsock=0D kernel module) doesn't support it.=0D =0D Fixes: 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D Cc: qemu-stable@nongnu.org=0D Reported-by: Jiang Wang =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-2-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 46ce017167d800c5d96104a88cfaed9949c4a3b6=0D https://github.com/qemu/qemu/commit/46ce017167d800c5d96104a88cfaed9= 949c4a3b6=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock-common.h=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: handle common features in vhost-vsock-common=0D =0D virtio-vsock features, like VIRTIO_VSOCK_F_SEQPACKET, can be handled=0D by vhost-vsock-common parent class. In this way, we can reuse the=0D same code for all virtio-vsock backends (i.e. vhost-vsock,=0D vhost-user-vsock).=0D =0D Let's move `seqpacket` property to vhost-vsock-common class, add=0D vhost_vsock_common_get_features() used by children, and disable=0D `seqpacket` for vhost-user-vsock device for machine types < 6.2.=0D =0D The behavior of vhost-vsock device doesn't change; vhost-user-vsock=0D device now supports `seqpacket` property.=0D =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-3-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c151fd87102cbb4082ac5dbcd704196b0495d28a=0D https://github.com/qemu/qemu/commit/c151fd87102cbb4082ac5dbcd704196= b0495d28a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: add helper routines to initialize ACPI tables=0D =0D Patch introduces acpi_table_begin()/ acpi_table_end() API=0D that hides pointer/offset arithmetic from user as opposed=0D to build_header(), to prevent errors caused by it [1].=0D =0D acpi_table_begin():=0D initializes table header and keeps track of=0D table data/offsets=0D acpi_table_end():=0D sets actual table length and tells bios loader=0D where table is for the later initialization on=0D guest side.=0D =0D 1) commits=0D bb9feea43179 x86: acpi: use offset instead of pointer when using build= _header()=0D 4d027afeb3a9 Virt: ACPI: fix qemu assert due to re-assigned table data= address=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Tested-by: Stefan Berger =0D Tested-by: Yanan Wang =0D =0D =0D Commit: ea298e83a7fb435e57913dd755b53e6b2264feed=0D https://github.com/qemu/qemu/commit/ea298e83a7fb435e57913dd755b53e6= b2264feed=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_rsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offests magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: f497b7cae1cd052fdbc023f02d37921c4069f7e6=0D https://github.com/qemu/qemu/commit/f497b7cae1cd052fdbc023f02d37921= c4069f7e6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_xsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7469f1991dc5e061ff724070c65e3fef96602bca=0D https://github.com/qemu/qemu/commit/7469f1991dc5e061ff724070c65e3fe= f96602bca=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_slit: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 4b56e1e4eb08e923f68203f0f92a1d3053bceb33=0D https://github.com/qemu/qemu/commit/4b56e1e4eb08e923f68203f0f92a1d3= 053bceb33=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_fadt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3e39c1ed7b642a20b63afaeb3742e0917d25dbe0=0D https://github.com/qemu/qemu/commit/3e39c1ed7b642a20b63afaeb3742e09= 17d25dbe0=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_tpm2: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Tested-by: Stefan Berger =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 13229858cf76b9648ba20be93b70fca4429d7dcd=0D https://github.com/qemu/qemu/commit/13229858cf76b9648ba20be93b70fca= 4429d7dcd=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/ghes.c=0D =0D Log Message:=0D -----------=0D acpi: acpi_build_hest: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Dongjiu Geng =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 578bc7a06462fd71c66d1562c457b01da307a7b6=0D https://github.com/qemu/qemu/commit/578bc7a06462fd71c66d1562c457b01= da307a7b6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/pci.c=0D =0D Log Message:=0D -----------=0D acpi: build_mcfg: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 689ef4721a06dd724e447d8b8e2dc3622c866557=0D https://github.com/qemu/qemu/commit/689ef4721a06dd724e447d8b8e2dc36= 22c866557=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/hmat.c=0D =0D Log Message:=0D -----------=0D acpi: build_hmat: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into hmat_build_table_structs()=0D which didn have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7d1823beeffc43669aaf7c5bc274c30e1c16e6c2=0D https://github.com/qemu/qemu/commit/7d1823beeffc43669aaf7c5bc274c30= e1c16e6c2=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_nfit: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into nvdimm_build_nfit() which didn't=0D have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: de67dd1be0af2b7fb02af441254ea05cd9bc1007=0D https://github.com/qemu/qemu/commit/de67dd1be0af2b7fb02af441254ea05= cd9bc1007=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_ssdt: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b25681c358bccb8700d742acb742dc1c2374acb7=0D https://github.com/qemu/qemu/commit/b25681c358bccb8700d742acb742dc1= c2374acb7=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/vmgenid.c=0D =0D Log Message:=0D -----------=0D acpi: vmgenid_build_acpi: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 5c142bc48f973e348e6ae13495ce370b172abaa4=0D https://github.com/qemu/qemu/commit/5c142bc48f973e348e6ae13495ce370= b172abaa4=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: x86: build_dsdt: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 43dde1705c610710389491e5989ae6f5b5cf6fb9=0D https://github.com/qemu/qemu/commit/43dde1705c610710389491e5989ae6f= 5b5cf6fb9=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_hpet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it convert build_hpet() to endian agnostic=0D build_append_FOO() API=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 57cb8cfbf2cda59fe829fee54115f72dd7998645=0D https://github.com/qemu/qemu/commit/57cb8cfbf2cda59fe829fee54115f72= dd7998645=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_tpm_tcpa: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 255bf20f2e047be1068f90cf8eaf3fc07cbba7d5=0D https://github.com/qemu/qemu/commit/255bf20f2e047be1068f90cf8eaf3fc= 07cbba7d5=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/x86: build_srat: use acpi_table_begin()/acpi_table_end() inst= ead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations)=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-17-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e5b6d55a6e5e13002cf79a42a0b78b3188e88a1f=0D https://github.com/qemu/qemu/commit/e5b6d55a6e5e13002cf79a42a0b78b3= 188e88a1f=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M hw/acpi/nvdimm.c=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: use build_append_int_noprefix() API to compose SRAT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building SRAT tables for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-18-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 91a6b9756970f70d933ea3c01fb5306ea6e5b331=0D https://github.com/qemu/qemu/commit/91a6b9756970f70d933ea3c01fb5306= ea6e5b331=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_dmar_q35: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries tables.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-19-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: eaa507646d039556ee2a10514b0a0acfe8f8362d=0D https://github.com/qemu/qemu/commit/eaa507646d039556ee2a10514b0a0ac= fe8f8362d=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_waet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-20-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b0a45ff60e822c26fbf412d3b82bd5748e4f8fb0=0D https://github.com/qemu/qemu/commit/b0a45ff60e822c26fbf412d3b82bd57= 48e4f8fb0=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_amd_iommu: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-21-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 99a7545f92378765ca98eb1b54b1087c9d2567ec=0D https://github.com/qemu/qemu/commit/99a7545f92378765ca98eb1b54b1087= c9d2567ec=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: madt: arm/x86: use acpi_table_begin()/acpi_table_end() instead of= build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-22-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b10e7f4f8f05b3956eabf0661320c71f1e3bab10=0D https://github.com/qemu/qemu/commit/b10e7f4f8f05b3956eabf0661320c71= f1e3bab10=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: remove dead code=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-23-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: d0aa026a498cdd4e082f12618767f19a2532712a=0D https://github.com/qemu/qemu/commit/d0aa026a498cdd4e082f12618767f19= a2532712a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/cpu.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/i386/pc.h=0D =0D Log Message:=0D -----------=0D acpi: x86: set enabled when composing _MAT entries=0D =0D Instead of composing disabled _MAT entry and then later on=0D patching it to enabled for hotpluggbale CPUs in DSDT,=0D set it to enabled at the time _MAT entry is built.=0D =0D It will allow to drop usage of packed structures in=0D following patches when build_madt() is switched to use=0D build_append_int_noprefix() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-24-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: dd092b9c6008149785d7789c729f468fb762aa0b=0D https://github.com/qemu/qemu/commit/dd092b9c6008149785d7789c729f468= fb762aa0b=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-25-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 37f33084ed2eb0867e3a3f501c6279c7c5f666c6=0D https://github.com/qemu/qemu/commit/37f33084ed2eb0867e3a3f501c6279c= 7c5f666c6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-26-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 8f20f9a7364f5324416c33a7d0aeccbddd5affcc=0D https://github.com/qemu/qemu/commit/8f20f9a7364f5324416c33a7d0aeccb= ddd5affcc=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-microvm.c=0D =0D Log Message:=0D -----------=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-27-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: fc02b86982df0628926869551901b64d2ab777e5=0D https://github.com/qemu/qemu/commit/fc02b86982df0628926869551901b64= d2ab777e5=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-28-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3548494e49dacd33bbd610876d1ac38f8f8b94bc=0D https://github.com/qemu/qemu/commit/3548494e49dacd33bbd610876d1ac38= f8f8b94bc=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D Message-Id: <20210924122802.1455362-29-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 271cbb2f2bfecfbb31175645f4e3da7ec626b810=0D https://github.com/qemu/qemu/commit/271cbb2f2bfecfbb31175645f4e3da7= ec626b810=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building IORT table use endian agnostic build_append_int_noprefix()=0D= API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-30-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D =0D =0D Commit: 88b1045eadd699335ffab0c9235f096f3a8cf771=0D https://github.com/qemu/qemu/commit/88b1045eadd699335ffab0c9235f096= f3a8cf771=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: fix invalid cast=0D =0D implicit cast to structure uint8_t member didn't raise error when=0D assigning value from incorrect enum, but when using build_append_gas()=0D= (next patch) it will error out with (clang):=0D implicit conversion from enumeration type 'AmlRegionSpace'=0D to different enumeration type 'AmlAddressSpace'=0D fix cast error by using correct AML_AS_SYSTEM_MEMORY enum=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-31-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a86d86ac0ae39b7e8fcce08fffd2e0ab5aa287df=0D https://github.com/qemu/qemu/commit/a86d86ac0ae39b7e8fcce08fffd2e0a= b5aa287df=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D PS:=0D Spec is Microsoft hosted, however 1.02 is no where to be found=0D (MS lists only the current revision) and the current revision is 1.07,=0D= so bring comments in line with 1.07 as this is the only available spec.=0D= There is no content change between originally implemented 1.02=0D (using QEMU code as reference) and 1.07. The only change is renaming=0D 'Reserved2' field to 'Language', with the same 0 value.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-32-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 41041e57085a9454c45a6a751babfca70306f361=0D https://github.com/qemu/qemu/commit/41041e57085a9454c45a6a751babfca= 70306f361=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-33-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: cf68410bc98914ee9be5cb5a127a1212056ab83a=0D https://github.com/qemu/qemu/commit/cf68410bc98914ee9be5cb5a127a121= 2056ab83a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= =0D Drop usage of packed structures and explicit endian=0D conversions when building table and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-34-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 538c2ecf1ab73fb2ecc2d50ef23b116e634b5392=0D https://github.com/qemu/qemu/commit/538c2ecf1ab73fb2ecc2d50ef23b116= e634b5392=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: remove no longer used build_header()=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-35-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a8a5768786f4182cb4f4b08e830150dc93d51964=0D https://github.com/qemu/qemu/commit/a8a5768786f4182cb4f4b08e830150d= c93d51964=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-36-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 9f29e872d5b3973003701401cf659cfb71c95013=0D https://github.com/qemu/qemu/commit/9f29e872d5b3973003701401cf659cf= b71c95013=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D =0D We are going to commit a change to fix IO address range allocated for acp= i pci=0D hotplug in q35. This affects DSDT tables. This change allows DSDT table=0D= modification so that unit tests are not broken.=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e780da76a6fe283a20283856718bca3986c104f=0D https://github.com/qemu/qemu/commit/0e780da76a6fe283a20283856718bca= 3986c104f=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/ich9.h=0D =0D Log Message:=0D -----------=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D =0D Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D selects an IO address range for acpi based PCI hotplug for q35 arbitraril= y. It=0D starts at address 0x0cc4 and ends at 0x0cdb. At the time when the patch w= as=0D written but the final version of the patch was not yet pushed upstream, t= his=0D address range was free and did not conflict with any other IO address ran= ges.=0D However, with the following change, this address range was no=0D longer conflict free as in this change, the IO address range=0D (value of ACPI_PCIHP_SIZE) was incremented by four bytes:=0D =0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D This can be seen from the output of QMP command 'info mtree' :=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc4-0000000000000cdb (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D It shows that there is a region of conflict between IO regions of acpi=0D= pci hotplug and acpi cpu hotplug.=0D =0D Unfortunately, the change caf108bc58790 did not update the IO address ran= ge=0D appropriately before it was pushed upstream to accommodate the increased=0D= length of the IO address space introduced in change b32bd763a1ca92.=0D =0D Due to this bug, windows guests complain 'This device cannot find=0D enough free resources it can use' in the device manager panel for extende= d=0D IO buses. This issue also breaks the correct functioning of pci hotplug a= s the=0D following shows that the IO space for pci hotplug has been truncated:=0D =0D (qemu) info mtree -f=0D FlatView #0=0D AS "I/O", root: io=0D Root memory region: io=0D 0000000000000cc4-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000cf7 (prio 0, i/o): acpi-cpu-hotplug=0D =0D Therefore, in this fix, we adjust the IO address range for the acpi pci=0D= hotplug so that it does not conflict with cpu hotplug and there is no=0D truncation of IO spaces. The starting IO address of PCI hotplug region=0D= has been decremented by four bytes in order to accommodate four byte=0D increment in the IO address space introduced by change=0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D After fixing, the following are the corrected IO ranges:=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc0-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D This change has been tested using a Windows Server 2019 guest VM. Windows= =0D no longer complains after this change.=0D =0D Fixes: caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/561=0D =0D Signed-off-by: Ani Sinha =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Julia Suvorova =0D Message-Id: <20210916132838.3469580-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 500eb21cff08dfb0478db9b34f2fdba69eb31496=0D https://github.com/qemu/qemu/commit/500eb21cff08dfb0478db9b34f2fdba= 69eb31496=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D =0D We have modified the IO address range for ACPI pci hotplug in q35. See ch= ange:=0D =0D 5adcc9e39e6a5 ("hw/i386/acpi: fix conflicting IO address range for acpi p= ci hotplug in q35")=0D =0D The ACPI DSDT table golden blobs must be regenrated in order to make the = unit tests=0D pass. This change updates the golden ACPI DSDT table blobs.=0D =0D Following is the ASL diff between the blobs:=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Tue Sep 14 09:04:06 2021=0D + * Disassembly of /tmp/aml-52DP90, Tue Sep 14 09:04:06 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D * Length 0x00002061 (8289)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xE5=0D + * Checksum 0xF9=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -226,46 +226,46 @@=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D 0x0070, // Range Minimum=0D 0x0070, // Range Maximum=0D 0x01, // Alignment=0D 0x08, // Length=0D )=0D IRQNoFlags ()=0D {8}=0D })=0D }=0D }=0D =0D Scope (_SB.PCI0)=0D {=0D - OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)=0D + OperationRegion (PCST, SystemIO, 0x0CC0, 0x08)=0D Field (PCST, DWordAcc, NoLock, WriteAsZeros)=0D {=0D PCIU, 32,=0D PCID, 32=0D }=0D =0D - OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04)=0D + OperationRegion (SEJ, SystemIO, 0x0CC8, 0x04)=0D Field (SEJ, DWordAcc, NoLock, WriteAsZeros)=0D {=0D B0EJ, 32=0D }=0D =0D - OperationRegion (BNMR, SystemIO, 0x0CD4, 0x08)=0D + OperationRegion (BNMR, SystemIO, 0x0CD0, 0x08)=0D Field (BNMR, DWordAcc, NoLock, WriteAsZeros)=0D {=0D BNUM, 32,=0D PIDX, 32=0D }=0D =0D Mutex (BLCK, 0x00)=0D Method (PCEJ, 2, NotSerialized)=0D {=0D Acquire (BLCK, 0xFFFF)=0D BNUM =3D Arg0=0D B0EJ =3D (One << Arg1)=0D Release (BLCK)=0D Return (Zero)=0D }=0D =0D @@ -3185,34 +3185,34 @@=0D 0x0620, // Range Minimum=0D 0x0620, // Range Maximum=0D 0x01, // Alignment=0D 0x10, // Length=0D )=0D })=0D }=0D =0D Device (PHPR)=0D {=0D Name (_HID, "PNP0A06" /* Generic Container Device */) // _H= ID: Hardware ID=0D Name (_UID, "PCI Hotplug resources") // _UID: Unique ID=0D Name (_STA, 0x0B) // _STA: Status=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D - 0x0CC4, // Range Minimum=0D - 0x0CC4, // Range Maximum=0D + 0x0CC0, // Range Minimum=0D + 0x0CC0, // Range Maximum=0D 0x01, // Alignment=0D 0x18, // Length=0D )=0D })=0D }=0D }=0D =0D Scope (\)=0D {=0D Name (_S3, Package (0x04) // _S3_: S3 System State=0D {=0D One,=0D One,=0D Zero,=0D Zero=0D })=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 243a9284a989a38e32ceb3990eb795f5cf6f3be0=0D https://github.com/qemu/qemu/commit/243a9284a989a38e32ceb3990eb795f= 5cf6f3be0=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-balloon.c=0D =0D Log Message:=0D -----------=0D virtio-balloon: Fix page-poison subsection name=0D =0D The subsection name for page-poison was typo'd as:=0D =0D vitio-balloon-device/page-poison=0D =0D Note the missing 'r' in virtio.=0D =0D When we have a machine type that enables page poison, and the guest=0D enables it (which needs a new kernel), things fail rather unpredictably.=0D= =0D The fallout from this is that most of the other subsections fail to=0D load, including things like the feature bits in the device, one=0D possible fallout is that the physical addresses of the queues=0D then get aligned differently and we fail with an error about=0D last_avail_idx being wrong.=0D It's not obvious to me why this doesn't produce a more obvious failure,=0D= but virtio's vmstate loading is a bit open-coded.=0D =0D Fixes: 7483cbbaf82 ("virtio-balloon: Implement support for page poison re= porting feature")=0D bz: https://bugzilla.redhat.com/show_bug.cgi?id=3D1984401=0D Signed-off-by: Dr. David Alan Gilbert =0D Message-Id: <20210914131716.102851-1-dgilbert@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: David Hildenbrand =0D =0D =0D Commit: 5c243345236b058a3d84c8cbc62802f3fffb273c=0D https://github.com/qemu/qemu/commit/5c243345236b058a3d84c8cbc62802f= 3fffb273c=0D Author: Li Zhijian =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D nvdimm: release the correct device list=0D =0D Signed-off-by: Li Zhijian =0D Message-Id: <20210624110415.187164-1-lizhijian@cn.fujitsu.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: 64cba40c4480b4716da7d26fbedc97f43aa9f8f4=0D https://github.com/qemu/qemu/commit/64cba40c4480b4716da7d26fbedc97f= 43aa9f8f4=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D =0D Per 'QEMU Coding Style':=0D =0D Naming=0D =3D=3D=3D=3D=3D=3D=0D Variables are lower_case_with_underscores; easy to type and read.=0D =0D Rename amdviPCI variable as amdvi_pci.=0D =0D amdviPCI_register_types() register more than PCI types:=0D TYPE_AMD_IOMMU_DEVICE inherits TYPE_X86_IOMMU_DEVICE which=0D itself inherits TYPE_SYS_BUS_DEVICE.=0D =0D Rename it more generically as amdvi_register_types().=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-2-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 8f6b7309c423a876dbb26975fdb48f582ebcabcd=0D https://github.com/qemu/qemu/commit/8f6b7309c423a876dbb26975fdb48f5= 82ebcabcd=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D =0D Various functions are SysBus specific. Rename them using the=0D consistent amdvi_sysbus_XXX() pattern, to differentiate them=0D from PCI specific functions (which we'll add in the next=0D commit).=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-3-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 64bc656decc0fdf59e23753de8940c744b39b586=0D https://github.com/qemu/qemu/commit/64bc656decc0fdf59e23753de8940c7= 44b39b586=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D =0D TYPE_AMD_IOMMU_PCI is user-creatable but not well described.=0D Implement its class_init() handler to add it to the 'Misc=0D devices' category, and add a description.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-4-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 274f9a381cd334118e9c84afb3285fe1da97cf87=0D https://github.com/qemu/qemu/commit/274f9a381cd334118e9c84afb3285fe= 1da97cf87=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/aml-build.c=0D M hw/acpi/cpu.c=0D M hw/acpi/ghes.c=0D M hw/acpi/hmat.c=0D M hw/acpi/nvdimm.c=0D M hw/acpi/pci.c=0D M hw/acpi/vmgenid.c=0D M hw/arm/virt-acpi-build.c=0D M hw/core/machine.c=0D M hw/i386/acpi-build.c=0D M hw/i386/acpi-common.c=0D M hw/i386/acpi-microvm.c=0D M hw/i386/amd_iommu.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M hw/virtio/virtio-balloon.c=0D M hw/virtio/virtio.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/acpi/aml-build.h=0D M include/hw/acpi/ich9.h=0D M include/hw/i386/pc.h=0D M include/hw/virtio/vhost-vsock-common.h=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes=0D =0D A huge acpi refactoring.=0D Fixes, cleanups all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Tue 05 Oct 2021 02:31:11 PM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (47 commits)=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D nvdimm: release the correct device list=0D virtio-balloon: Fix page-poison subsection name=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D acpi: remove no longer used build_header()=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: fix invalid cast=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/08a9b68dc033...274f9a381cd3= =0D From MAILER-DAEMON Tue Oct 05 19:30:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXtte-0000o7-FG for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 19:30:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXtta-0000nu-Py for qemu-commits@nongnu.org; Tue, 05 Oct 2021 19:30:52 -0400 Received: from out-28.smtp.github.com ([192.30.252.211]:59619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXttT-0006LM-Oh for qemu-commits@nongnu.org; Tue, 05 Oct 2021 19:30:48 -0400 Received: from github.com (hubbernetes-node-7a1d7ea.ash1-iad.github.net [10.56.120.61]) by smtp.github.com (Postfix) with ESMTPA id 03D23900DF1 for ; Tue, 5 Oct 2021 16:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633476643; bh=p4+C9sF3YvYOjTPGDjfW4b832EnRcxGFOSiQ495d+kc=; h=Date:From:To:Subject:From; b=xocMwmzWY/P0FobBdmfd+o32nbi5OsUTWcZOGm4FcBFb3n2rmbsC8CzCIQT6KgyTq /ZlYaEMUJhOvrIAX3L55d/qQRPLTzyKMObjnA0inLBSmGc2i7vofzIldt/x55z97Y1 ap3Jm0OEQyUHz9zQtqy/lqMjw3CGu/srWy/TDS+A= Date: Tue, 05 Oct 2021 16:30:42 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.211; envelope-from=noreply@github.com; helo=out-28.smtp.github.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ab4dd2: hw/virtio: Acquire RCU read lock in virtqueue_pack... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 23:30:53 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: ab4dd2746c234f038206b3ccfe6bec1f19f98c24=0D https://github.com/qemu/qemu/commit/ab4dd2746c234f038206b3ccfe6bec1= f19f98c24=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Acquire RCU read lock in virtqueue_packed_drop_all()=0D =0D vring_get_region_caches() must be called with the RCU read lock=0D acquired. virtqueue_packed_drop_all() does not, and uses the=0D 'caches' pointer. Fix that by using the RCU_READ_LOCK_GUARD()=0D macro.=0D =0D Reported-by: Stefano Garzarella =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-3-philmd@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: d6ed27bae717ceac9de0c53a31389143846b8465=0D https://github.com/qemu/qemu/commit/d6ed27bae717ceac9de0c53a3138914= 3846b8465=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio.c=0D =0D Log Message:=0D -----------=0D hw/virtio: Have virtqueue_get_avail_bytes() pass caches arg to callees=0D= =0D Both virtqueue_packed_get_avail_bytes() and=0D virtqueue_split_get_avail_bytes() access the region cache, but=0D their caller also does. Simplify by having virtqueue_get_avail_bytes=0D calling both with RCU lock held, and passing the caches as argument.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210906104318.1569967-4-philmd@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: d6a9378f47515c6d70dbff4912c5740c98709880=0D https://github.com/qemu/qemu/commit/d6a9378f47515c6d70dbff4912c5740= c98709880=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: fix migration issue when seqpacket is supported=0D =0D Commit 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D enabled the SEQPACKET feature bit.=0D This commit is released with QEMU 6.1, so if we try to migrate a VM where= =0D the host kernel supports SEQPACKET but machine type version is less than=0D= 6.1, we get the following errors:=0D =0D Features 0x130000002 unsupported. Allowed features: 0x179000000=0D Failed to load virtio-vhost_vsock:virtio=0D error while loading state for instance 0x0 of device '0000:00:05.0/vi= rtio-vhost_vsock'=0D load of migration failed: Operation not permitted=0D =0D Let's disable the feature bit for machine types < 6.1.=0D We add a new OnOffAuto property for this, called `seqpacket`.=0D When it is `auto` (default), QEMU behaves as before, trying to enable the= =0D feature, when it is `on` QEMU will fail if the backend (vhost-vsock=0D kernel module) doesn't support it.=0D =0D Fixes: 1e08fd0a46 ("vhost-vsock: SOCK_SEQPACKET feature bit support")=0D Cc: qemu-stable@nongnu.org=0D Reported-by: Jiang Wang =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-2-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 46ce017167d800c5d96104a88cfaed9949c4a3b6=0D https://github.com/qemu/qemu/commit/46ce017167d800c5d96104a88cfaed9= 949c4a3b6=0D Author: Stefano Garzarella =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/core/machine.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M include/hw/virtio/vhost-vsock-common.h=0D M include/hw/virtio/vhost-vsock.h=0D =0D Log Message:=0D -----------=0D vhost-vsock: handle common features in vhost-vsock-common=0D =0D virtio-vsock features, like VIRTIO_VSOCK_F_SEQPACKET, can be handled=0D by vhost-vsock-common parent class. In this way, we can reuse the=0D same code for all virtio-vsock backends (i.e. vhost-vsock,=0D vhost-user-vsock).=0D =0D Let's move `seqpacket` property to vhost-vsock-common class, add=0D vhost_vsock_common_get_features() used by children, and disable=0D `seqpacket` for vhost-user-vsock device for machine types < 6.2.=0D =0D The behavior of vhost-vsock device doesn't change; vhost-user-vsock=0D device now supports `seqpacket` property.=0D =0D Signed-off-by: Stefano Garzarella =0D Message-Id: <20210921161642.206461-3-sgarzare@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c151fd87102cbb4082ac5dbcd704196b0495d28a=0D https://github.com/qemu/qemu/commit/c151fd87102cbb4082ac5dbcd704196= b0495d28a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: add helper routines to initialize ACPI tables=0D =0D Patch introduces acpi_table_begin()/ acpi_table_end() API=0D that hides pointer/offset arithmetic from user as opposed=0D to build_header(), to prevent errors caused by it [1].=0D =0D acpi_table_begin():=0D initializes table header and keeps track of=0D table data/offsets=0D acpi_table_end():=0D sets actual table length and tells bios loader=0D where table is for the later initialization on=0D guest side.=0D =0D 1) commits=0D bb9feea43179 x86: acpi: use offset instead of pointer when using build= _header()=0D 4d027afeb3a9 Virt: ACPI: fix qemu assert due to re-assigned table data= address=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Tested-by: Stefan Berger =0D Tested-by: Yanan Wang =0D =0D =0D Commit: ea298e83a7fb435e57913dd755b53e6b2264feed=0D https://github.com/qemu/qemu/commit/ea298e83a7fb435e57913dd755b53e6= b2264feed=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_rsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offests magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: f497b7cae1cd052fdbc023f02d37921c4069f7e6=0D https://github.com/qemu/qemu/commit/f497b7cae1cd052fdbc023f02d37921= c4069f7e6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_xsdt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D entries to other tables (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7469f1991dc5e061ff724070c65e3fef96602bca=0D https://github.com/qemu/qemu/commit/7469f1991dc5e061ff724070c65e3fe= f96602bca=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_slit: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 4b56e1e4eb08e923f68203f0f92a1d3053bceb33=0D https://github.com/qemu/qemu/commit/4b56e1e4eb08e923f68203f0f92a1d3= 053bceb33=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_fadt: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3e39c1ed7b642a20b63afaeb3742e0917d25dbe0=0D https://github.com/qemu/qemu/commit/3e39c1ed7b642a20b63afaeb3742e09= 17d25dbe0=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_tpm2: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Tested-by: Stefan Berger =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 13229858cf76b9648ba20be93b70fca4429d7dcd=0D https://github.com/qemu/qemu/commit/13229858cf76b9648ba20be93b70fca= 4429d7dcd=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/ghes.c=0D =0D Log Message:=0D -----------=0D acpi: acpi_build_hest: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Dongjiu Geng =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 578bc7a06462fd71c66d1562c457b01da307a7b6=0D https://github.com/qemu/qemu/commit/578bc7a06462fd71c66d1562c457b01= da307a7b6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/pci.c=0D =0D Log Message:=0D -----------=0D acpi: build_mcfg: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 689ef4721a06dd724e447d8b8e2dc3622c866557=0D https://github.com/qemu/qemu/commit/689ef4721a06dd724e447d8b8e2dc36= 22c866557=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/hmat.c=0D =0D Log Message:=0D -----------=0D acpi: build_hmat: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into hmat_build_table_structs()=0D which didn have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7d1823beeffc43669aaf7c5bc274c30e1c16e6c2=0D https://github.com/qemu/qemu/commit/7d1823beeffc43669aaf7c5bc274c30= e1c16e6c2=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_nfit: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Also since acpi_table_begin() reserves space only for standard header=0D while previous acpi_data_push() reserved the header + 4 bytes field,=0D add 4 bytes 'Reserved' field into nvdimm_build_nfit() which didn't=0D have it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: de67dd1be0af2b7fb02af441254ea05cd9bc1007=0D https://github.com/qemu/qemu/commit/de67dd1be0af2b7fb02af441254ea05= cd9bc1007=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D acpi: nvdimm_build_ssdt: use acpi_table_begin()/acpi_table_end() instea= d of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b25681c358bccb8700d742acb742dc1c2374acb7=0D https://github.com/qemu/qemu/commit/b25681c358bccb8700d742acb742dc1= c2374acb7=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/vmgenid.c=0D =0D Log Message:=0D -----------=0D acpi: vmgenid_build_acpi: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 5c142bc48f973e348e6ae13495ce370b172abaa4=0D https://github.com/qemu/qemu/commit/5c142bc48f973e348e6ae13495ce370= b172abaa4=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: x86: build_dsdt: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 43dde1705c610710389491e5989ae6f5b5cf6fb9=0D https://github.com/qemu/qemu/commit/43dde1705c610710389491e5989ae6f= 5b5cf6fb9=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_hpet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it convert build_hpet() to endian agnostic=0D build_append_FOO() API=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 57cb8cfbf2cda59fe829fee54115f72dd7998645=0D https://github.com/qemu/qemu/commit/57cb8cfbf2cda59fe829fee54115f72= dd7998645=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_tpm_tcpa: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations).=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 255bf20f2e047be1068f90cf8eaf3fc07cbba7d5=0D https://github.com/qemu/qemu/commit/255bf20f2e047be1068f90cf8eaf3fc= 07cbba7d5=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/x86: build_srat: use acpi_table_begin()/acpi_table_end() inst= ead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries (which also removes some manual offset=0D calculations)=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-17-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e5b6d55a6e5e13002cf79a42a0b78b3188e88a1f=0D https://github.com/qemu/qemu/commit/e5b6d55a6e5e13002cf79a42a0b78b3= 188e88a1f=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M hw/acpi/nvdimm.c=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: use build_append_int_noprefix() API to compose SRAT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building SRAT tables for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-18-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 91a6b9756970f70d933ea3c01fb5306ea6e5b331=0D https://github.com/qemu/qemu/commit/91a6b9756970f70d933ea3c01fb5306= ea6e5b331=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_dmar_q35: use acpi_table_begin()/acpi_table_end() instead o= f build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D While at it switch to build_append_int_noprefix() to build=0D table entries tables.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-19-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: eaa507646d039556ee2a10514b0a0acfe8f8362d=0D https://github.com/qemu/qemu/commit/eaa507646d039556ee2a10514b0a0ac= fe8f8362d=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_waet: use acpi_table_begin()/acpi_table_end() instead of bu= ild_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-20-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b0a45ff60e822c26fbf412d3b82bd5748e4f8fb0=0D https://github.com/qemu/qemu/commit/b0a45ff60e822c26fbf412d3b82bd57= 48e4f8fb0=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: build_amd_iommu: use acpi_table_begin()/acpi_table_end() instead = of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-21-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 99a7545f92378765ca98eb1b54b1087c9d2567ec=0D https://github.com/qemu/qemu/commit/99a7545f92378765ca98eb1b54b1087= c9d2567ec=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: madt: arm/x86: use acpi_table_begin()/acpi_table_end() instead of= build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-22-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b10e7f4f8f05b3956eabf0661320c71f1e3bab10=0D https://github.com/qemu/qemu/commit/b10e7f4f8f05b3956eabf0661320c71= f1e3bab10=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: remove dead code=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-23-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: d0aa026a498cdd4e082f12618767f19a2532712a=0D https://github.com/qemu/qemu/commit/d0aa026a498cdd4e082f12618767f19= a2532712a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/cpu.c=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/i386/pc.h=0D =0D Log Message:=0D -----------=0D acpi: x86: set enabled when composing _MAT entries=0D =0D Instead of composing disabled _MAT entry and then later on=0D patching it to enabled for hotpluggbale CPUs in DSDT,=0D set it to enabled at the time _MAT entry is built.=0D =0D It will allow to drop usage of packed structures in=0D following patches when build_madt() is switched to use=0D build_append_int_noprefix() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-24-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: dd092b9c6008149785d7789c729f468fb762aa0b=0D https://github.com/qemu/qemu/commit/dd092b9c6008149785d7789c729f468= fb762aa0b=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-common.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-25-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 37f33084ed2eb0867e3a3f501c6279c7c5f666c6=0D https://github.com/qemu/qemu/commit/37f33084ed2eb0867e3a3f501c6279c= 7c5f666c6=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building MADT table for arm/x86 and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-26-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 8f20f9a7364f5324416c33a7d0aeccbddd5affcc=0D https://github.com/qemu/qemu/commit/8f20f9a7364f5324416c33a7d0aeccb= ddd5affcc=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-microvm.c=0D =0D Log Message:=0D -----------=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-27-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: fc02b86982df0628926869551901b64d2ab777e5=0D https://github.com/qemu/qemu/commit/fc02b86982df0628926869551901b64= d2ab777e5=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-28-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3548494e49dacd33bbd610876d1ac38f8f8b94bc=0D https://github.com/qemu/qemu/commit/3548494e49dacd33bbd610876d1ac38= f8f8b94bc=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D Message-Id: <20210924122802.1455362-29-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 271cbb2f2bfecfbb31175645f4e3da7ec626b810=0D https://github.com/qemu/qemu/commit/271cbb2f2bfecfbb31175645f4e3da7= ec626b810=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D =0D Drop usage of packed structures and explicit endian conversions=0D when building IORT table use endian agnostic build_append_int_noprefix()=0D= API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210924122802.1455362-30-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Eric Auger =0D Tested-by: Eric Auger =0D =0D =0D Commit: 88b1045eadd699335ffab0c9235f096f3a8cf771=0D https://github.com/qemu/qemu/commit/88b1045eadd699335ffab0c9235f096= f3a8cf771=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: fix invalid cast=0D =0D implicit cast to structure uint8_t member didn't raise error when=0D assigning value from incorrect enum, but when using build_append_gas()=0D= (next patch) it will error out with (clang):=0D implicit conversion from enumeration type 'AmlRegionSpace'=0D to different enumeration type 'AmlAddressSpace'=0D fix cast error by using correct AML_AS_SYSTEM_MEMORY enum=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-31-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a86d86ac0ae39b7e8fcce08fffd2e0ab5aa287df=0D https://github.com/qemu/qemu/commit/a86d86ac0ae39b7e8fcce08fffd2e0a= b5aa287df=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D PS:=0D Spec is Microsoft hosted, however 1.02 is no where to be found=0D (MS lists only the current revision) and the current revision is 1.07,=0D= so bring comments in line with 1.07 as this is the only available spec.=0D= There is no content change between originally implemented 1.02=0D (using QEMU code as reference) and 1.07. The only change is renaming=0D 'Reserved2' field to 'Language', with the same 0 value.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-32-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 41041e57085a9454c45a6a751babfca70306f361=0D https://github.com/qemu/qemu/commit/41041e57085a9454c45a6a751babfca= 70306f361=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D =0D it replaces error-prone pointer arithmetic for build_header() API,=0D with 2 calls to start and finish table creation,=0D which hides offsets magic from API user.=0D =0D while at it, replace packed structure with endian agnostic=0D build_append_FOO() API.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-33-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: cf68410bc98914ee9be5cb5a127a1212056ab83a=0D https://github.com/qemu/qemu/commit/cf68410bc98914ee9be5cb5a127a121= 2056ab83a=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= =0D Drop usage of packed structures and explicit endian=0D conversions when building table and use endian agnostic=0D build_append_int_noprefix() API to build it.=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-34-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 538c2ecf1ab73fb2ecc2d50ef23b116e634b5392=0D https://github.com/qemu/qemu/commit/538c2ecf1ab73fb2ecc2d50ef23b116= e634b5392=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D acpi: remove no longer used build_header()=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-35-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a8a5768786f4182cb4f4b08e830150dc93d51964=0D https://github.com/qemu/qemu/commit/a8a5768786f4182cb4f4b08e830150d= c93d51964=0D Author: Igor Mammedov =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/acpi-defs.h=0D =0D Log Message:=0D -----------=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D =0D Signed-off-by: Igor Mammedov =0D Reviewed-by: Eric Auger =0D Message-Id: <20210924122802.1455362-36-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 9f29e872d5b3973003701401cf659cfb71c95013=0D https://github.com/qemu/qemu/commit/9f29e872d5b3973003701401cf659cf= b71c95013=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D =0D We are going to commit a change to fix IO address range allocated for acp= i pci=0D hotplug in q35. This affects DSDT tables. This change allows DSDT table=0D= modification so that unit tests are not broken.=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e780da76a6fe283a20283856718bca3986c104f=0D https://github.com/qemu/qemu/commit/0e780da76a6fe283a20283856718bca= 3986c104f=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/acpi/ich9.h=0D =0D Log Message:=0D -----------=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D =0D Change caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D selects an IO address range for acpi based PCI hotplug for q35 arbitraril= y. It=0D starts at address 0x0cc4 and ends at 0x0cdb. At the time when the patch w= as=0D written but the final version of the patch was not yet pushed upstream, t= his=0D address range was free and did not conflict with any other IO address ran= ges.=0D However, with the following change, this address range was no=0D longer conflict free as in this change, the IO address range=0D (value of ACPI_PCIHP_SIZE) was incremented by four bytes:=0D =0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D This can be seen from the output of QMP command 'info mtree' :=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc4-0000000000000cdb (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D It shows that there is a region of conflict between IO regions of acpi=0D= pci hotplug and acpi cpu hotplug.=0D =0D Unfortunately, the change caf108bc58790 did not update the IO address ran= ge=0D appropriately before it was pushed upstream to accommodate the increased=0D= length of the IO address space introduced in change b32bd763a1ca92.=0D =0D Due to this bug, windows guests complain 'This device cannot find=0D enough free resources it can use' in the device manager panel for extende= d=0D IO buses. This issue also breaks the correct functioning of pci hotplug a= s the=0D following shows that the IO space for pci hotplug has been truncated:=0D =0D (qemu) info mtree -f=0D FlatView #0=0D AS "I/O", root: io=0D Root memory region: io=0D 0000000000000cc4-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000cf7 (prio 0, i/o): acpi-cpu-hotplug=0D =0D Therefore, in this fix, we adjust the IO address range for the acpi pci=0D= hotplug so that it does not conflict with cpu hotplug and there is no=0D truncation of IO spaces. The starting IO address of PCI hotplug region=0D= has been decremented by four bytes in order to accommodate four byte=0D increment in the IO address space introduced by change=0D b32bd763a1ca92 ("pci: introduce acpi-index property for PCI device")=0D =0D After fixing, the following are the corrected IO ranges:=0D =0D 0000000000000600-0000000000000603 (prio 0, i/o): acpi-evt=0D 0000000000000604-0000000000000605 (prio 0, i/o): acpi-cnt=0D 0000000000000608-000000000000060b (prio 0, i/o): acpi-tmr=0D 0000000000000620-000000000000062f (prio 0, i/o): acpi-gpe0=0D 0000000000000630-0000000000000637 (prio 0, i/o): acpi-smi=0D 0000000000000cc0-0000000000000cd7 (prio 0, i/o): acpi-pci-hotplug=0D 0000000000000cd8-0000000000000ce3 (prio 0, i/o): acpi-cpu-hotplug=0D =0D This change has been tested using a Windows Server 2019 guest VM. Windows= =0D no longer complains after this change.=0D =0D Fixes: caf108bc58790 ("hw/i386/acpi-build: Add ACPI PCI hot-plug methods = to Q35")=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/561=0D =0D Signed-off-by: Ani Sinha =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Julia Suvorova =0D Message-Id: <20210916132838.3469580-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 500eb21cff08dfb0478db9b34f2fdba69eb31496=0D https://github.com/qemu/qemu/commit/500eb21cff08dfb0478db9b34f2fdba= 69eb31496=0D Author: Ani Sinha =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D =0D We have modified the IO address range for ACPI pci hotplug in q35. See ch= ange:=0D =0D 5adcc9e39e6a5 ("hw/i386/acpi: fix conflicting IO address range for acpi p= ci hotplug in q35")=0D =0D The ACPI DSDT table golden blobs must be regenrated in order to make the = unit tests=0D pass. This change updates the golden ACPI DSDT table blobs.=0D =0D Following is the ASL diff between the blobs:=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Tue Sep 14 09:04:06 2021=0D + * Disassembly of /tmp/aml-52DP90, Tue Sep 14 09:04:06 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D * Length 0x00002061 (8289)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xE5=0D + * Checksum 0xF9=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -226,46 +226,46 @@=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D 0x0070, // Range Minimum=0D 0x0070, // Range Maximum=0D 0x01, // Alignment=0D 0x08, // Length=0D )=0D IRQNoFlags ()=0D {8}=0D })=0D }=0D }=0D =0D Scope (_SB.PCI0)=0D {=0D - OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)=0D + OperationRegion (PCST, SystemIO, 0x0CC0, 0x08)=0D Field (PCST, DWordAcc, NoLock, WriteAsZeros)=0D {=0D PCIU, 32,=0D PCID, 32=0D }=0D =0D - OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04)=0D + OperationRegion (SEJ, SystemIO, 0x0CC8, 0x04)=0D Field (SEJ, DWordAcc, NoLock, WriteAsZeros)=0D {=0D B0EJ, 32=0D }=0D =0D - OperationRegion (BNMR, SystemIO, 0x0CD4, 0x08)=0D + OperationRegion (BNMR, SystemIO, 0x0CD0, 0x08)=0D Field (BNMR, DWordAcc, NoLock, WriteAsZeros)=0D {=0D BNUM, 32,=0D PIDX, 32=0D }=0D =0D Mutex (BLCK, 0x00)=0D Method (PCEJ, 2, NotSerialized)=0D {=0D Acquire (BLCK, 0xFFFF)=0D BNUM =3D Arg0=0D B0EJ =3D (One << Arg1)=0D Release (BLCK)=0D Return (Zero)=0D }=0D =0D @@ -3185,34 +3185,34 @@=0D 0x0620, // Range Minimum=0D 0x0620, // Range Maximum=0D 0x01, // Alignment=0D 0x10, // Length=0D )=0D })=0D }=0D =0D Device (PHPR)=0D {=0D Name (_HID, "PNP0A06" /* Generic Container Device */) // _H= ID: Hardware ID=0D Name (_UID, "PCI Hotplug resources") // _UID: Unique ID=0D Name (_STA, 0x0B) // _STA: Status=0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource S= ettings=0D {=0D IO (Decode16,=0D - 0x0CC4, // Range Minimum=0D - 0x0CC4, // Range Maximum=0D + 0x0CC0, // Range Minimum=0D + 0x0CC0, // Range Maximum=0D 0x01, // Alignment=0D 0x18, // Length=0D )=0D })=0D }=0D }=0D =0D Scope (\)=0D {=0D Name (_S3, Package (0x04) // _S3_: S3 System State=0D {=0D One,=0D One,=0D Zero,=0D Zero=0D })=0D =0D Signed-off-by: Ani Sinha =0D Acked-by: Igor Mammedov =0D Message-Id: <20210916132838.3469580-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 243a9284a989a38e32ceb3990eb795f5cf6f3be0=0D https://github.com/qemu/qemu/commit/243a9284a989a38e32ceb3990eb795f= 5cf6f3be0=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-balloon.c=0D =0D Log Message:=0D -----------=0D virtio-balloon: Fix page-poison subsection name=0D =0D The subsection name for page-poison was typo'd as:=0D =0D vitio-balloon-device/page-poison=0D =0D Note the missing 'r' in virtio.=0D =0D When we have a machine type that enables page poison, and the guest=0D enables it (which needs a new kernel), things fail rather unpredictably.=0D= =0D The fallout from this is that most of the other subsections fail to=0D load, including things like the feature bits in the device, one=0D possible fallout is that the physical addresses of the queues=0D then get aligned differently and we fail with an error about=0D last_avail_idx being wrong.=0D It's not obvious to me why this doesn't produce a more obvious failure,=0D= but virtio's vmstate loading is a bit open-coded.=0D =0D Fixes: 7483cbbaf82 ("virtio-balloon: Implement support for page poison re= porting feature")=0D bz: https://bugzilla.redhat.com/show_bug.cgi?id=3D1984401=0D Signed-off-by: Dr. David Alan Gilbert =0D Message-Id: <20210914131716.102851-1-dgilbert@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: David Hildenbrand =0D =0D =0D Commit: 5c243345236b058a3d84c8cbc62802f3fffb273c=0D https://github.com/qemu/qemu/commit/5c243345236b058a3d84c8cbc62802f= 3fffb273c=0D Author: Li Zhijian =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/nvdimm.c=0D =0D Log Message:=0D -----------=0D nvdimm: release the correct device list=0D =0D Signed-off-by: Li Zhijian =0D Message-Id: <20210624110415.187164-1-lizhijian@cn.fujitsu.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: 64cba40c4480b4716da7d26fbedc97f43aa9f8f4=0D https://github.com/qemu/qemu/commit/64cba40c4480b4716da7d26fbedc97f= 43aa9f8f4=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D =0D Per 'QEMU Coding Style':=0D =0D Naming=0D =3D=3D=3D=3D=3D=3D=0D Variables are lower_case_with_underscores; easy to type and read.=0D =0D Rename amdviPCI variable as amdvi_pci.=0D =0D amdviPCI_register_types() register more than PCI types:=0D TYPE_AMD_IOMMU_DEVICE inherits TYPE_X86_IOMMU_DEVICE which=0D itself inherits TYPE_SYS_BUS_DEVICE.=0D =0D Rename it more generically as amdvi_register_types().=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-2-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 8f6b7309c423a876dbb26975fdb48f582ebcabcd=0D https://github.com/qemu/qemu/commit/8f6b7309c423a876dbb26975fdb48f5= 82ebcabcd=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D =0D Various functions are SysBus specific. Rename them using the=0D consistent amdvi_sysbus_XXX() pattern, to differentiate them=0D from PCI specific functions (which we'll add in the next=0D commit).=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-3-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 64bc656decc0fdf59e23753de8940c744b39b586=0D https://github.com/qemu/qemu/commit/64bc656decc0fdf59e23753de8940c7= 44b39b586=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/amd_iommu.c=0D =0D Log Message:=0D -----------=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D =0D TYPE_AMD_IOMMU_PCI is user-creatable but not well described.=0D Implement its class_init() handler to add it to the 'Misc=0D devices' category, and add a description.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210926175648.1649075-4-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 274f9a381cd334118e9c84afb3285fe1da97cf87=0D https://github.com/qemu/qemu/commit/274f9a381cd334118e9c84afb3285fe= 1da97cf87=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/acpi-x86-stub.c=0D M hw/acpi/aml-build.c=0D M hw/acpi/cpu.c=0D M hw/acpi/ghes.c=0D M hw/acpi/hmat.c=0D M hw/acpi/nvdimm.c=0D M hw/acpi/pci.c=0D M hw/acpi/vmgenid.c=0D M hw/arm/virt-acpi-build.c=0D M hw/core/machine.c=0D M hw/i386/acpi-build.c=0D M hw/i386/acpi-common.c=0D M hw/i386/acpi-microvm.c=0D M hw/i386/amd_iommu.c=0D M hw/virtio/vhost-user-vsock.c=0D M hw/virtio/vhost-vsock-common.c=0D M hw/virtio/vhost-vsock.c=0D M hw/virtio/virtio-balloon.c=0D M hw/virtio/virtio.c=0D M include/hw/acpi/acpi-defs.h=0D M include/hw/acpi/acpi_dev_interface.h=0D M include/hw/acpi/aml-build.h=0D M include/hw/acpi/ich9.h=0D M include/hw/i386/pc.h=0D M include/hw/virtio/vhost-vsock-common.h=0D M tests/data/acpi/q35/DSDT=0D M tests/data/acpi/q35/DSDT.acpihmat=0D M tests/data/acpi/q35/DSDT.bridge=0D M tests/data/acpi/q35/DSDT.cphp=0D M tests/data/acpi/q35/DSDT.dimmpxm=0D M tests/data/acpi/q35/DSDT.ipmibt=0D M tests/data/acpi/q35/DSDT.memhp=0D M tests/data/acpi/q35/DSDT.mmio64=0D M tests/data/acpi/q35/DSDT.nohpet=0D M tests/data/acpi/q35/DSDT.numamem=0D M tests/data/acpi/q35/DSDT.tis.tpm12=0D M tests/data/acpi/q35/DSDT.tis.tpm2=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes=0D =0D A huge acpi refactoring.=0D Fixes, cleanups all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Tue 05 Oct 2021 02:31:11 PM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (47 commits)=0D hw/i386/amd_iommu: Add description/category to TYPE_AMD_IOMMU_PCI=0D hw/i386/amd_iommu: Rename SysBus specific functions as amdvi_sysbus_X()= =0D hw/i386/amd_iommu: Rename amdviPCI TypeInfo=0D nvdimm: release the correct device list=0D virtio-balloon: Fix page-poison subsection name=0D bios-tables-test: Update ACPI DSDT table golden blobs for q35=0D hw/i386/acpi: fix conflicting IO address range for acpi pci hotplug in = q35=0D bios-tables-test: allow changes in DSDT ACPI tables for q35=0D acpi: AcpiGenericAddress no longer used to map/access fields of MMIO, d= rop packed attribute=0D acpi: remove no longer used build_header()=0D acpi: build_facs: use build_append_int_noprefix() API to compose table=0D= acpi: arm/virt: build_gtdt: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: use acpi_table_begin()/acpi_table_end() ins= tead of build_header()=0D acpi: arm/virt: build_spcr: fix invalid cast=0D acpi: arm/virt: convert build_iort() to endian agnostic build_append_FO= O() API=0D acpi: arm: virt: build_iort: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: arm: virt: build_dsdt: use acpi_table_begin()/acpi_table_end() in= stead of build_header()=0D acpi: build_dsdt_microvm: use acpi_table_begin()/acpi_table_end() inste= ad of build_header()=0D acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MA= DT table=0D acpi: x86: madt: use build_append_int_noprefix() API to compose MADT ta= ble=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/08a9b68dc033...274f9a381cd3= =0D From MAILER-DAEMON Tue Oct 05 19:41:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXu46-0003iv-DF for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 19:41:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXu44-0003il-KT for qemu-commits@nongnu.org; Tue, 05 Oct 2021 19:41:40 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:50235 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXu42-0006aL-PV for qemu-commits@nongnu.org; Tue, 05 Oct 2021 19:41:40 -0400 Received: from github.com (hubbernetes-node-c6b11f2.va3-iad.github.net [10.48.207.58]) by smtp.github.com (Postfix) with ESMTPA id D7F575C0215 for ; Tue, 5 Oct 2021 16:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633477297; bh=FcS+FE3eAZWI1hP3V1MWgiCoPVKrWYaEPbaEKqBlHe0=; h=Date:From:To:Subject:From; b=nvIz/MDyPRCcauM5naH0lkkxhs4AMuWLQ9uUEJ7O9fsQvqwPiWEPo7LKUPe0KKn3L Hnl/LZfia89nQTNx0vQH1+E6viOGBSjSR5OLc/zOjYomVzOl6KvKsXSEo+e9x56CbJ bhTVC4P1vCUvpLJMw6WLxclrZ6el5sXHxK2s5XlA= Date: Tue, 05 Oct 2021 16:41:37 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e3acc2: tests/docker/dockerfiles: Bump fedora-i386-cross t... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 23:41:40 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3 https://github.com/qemu/qemu/commit/e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3 Author: Richard Henderson Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M tests/docker/dockerfiles/fedora-i386-cross.docker Log Message: ----------- tests/docker/dockerfiles: Bump fedora-i386-cross to fedora 34 For unknown and unrepeatable reasons, the cross-i386-tci test has started failing. "Fix" this by updating the container to use fedora 34. Add sysprof-capture-devel as a new dependency of glib2-devel that was not correctly spelled out in the rpm rules. Use dnf update Just In Case -- there are presently out-of-date packages in the upstream docker registry. Reviewed-by: Paolo Bonzini Message-Id: <20211005205846.153724-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson From MAILER-DAEMON Tue Oct 05 21:23:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mXven-0006o6-Ec for mharc-qemu-commits@gnu.org; Tue, 05 Oct 2021 21:23:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXvel-0006nl-VK for qemu-commits@nongnu.org; Tue, 05 Oct 2021 21:23:39 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:53365 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXvej-0000ok-FT for qemu-commits@nongnu.org; Tue, 05 Oct 2021 21:23:39 -0400 Received: from github.com (hubbernetes-node-caf0a88.ac4-iad.github.net [10.52.208.50]) by smtp.github.com (Postfix) with ESMTPA id 47E6A52007B for ; Tue, 5 Oct 2021 18:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633483416; bh=S6LBov5dmoUf1uEm0FDyWDUNWAiZCq6zPMBLCj6b56Y=; h=Date:From:To:Subject:From; b=DtQpuLyxVvP4cUnZUxHIrKvqXvX4MUrDez9YYFujkNigPtccuQpGB6kGapCogkpLo D4F7g+Mww3Kh5yHgsZ5P1YFn8s8PZHxfAMjwIuSkc1svuqd44nL0dW4jct1vmvjoaz ZZMR+njjS4KXg1x/Cytxedu/G8Vze3zE6IaYNj2A= Date: Tue, 05 Oct 2021 18:23:36 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e3acc2: tests/docker/dockerfiles: Bump fedora-i386-cross t... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 01:23:40 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3 https://github.com/qemu/qemu/commit/e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3 Author: Richard Henderson Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M tests/docker/dockerfiles/fedora-i386-cross.docker Log Message: ----------- tests/docker/dockerfiles: Bump fedora-i386-cross to fedora 34 For unknown and unrepeatable reasons, the cross-i386-tci test has started failing. "Fix" this by updating the container to use fedora 34. Add sysprof-capture-devel as a new dependency of glib2-devel that was not correctly spelled out in the rpm rules. Use dnf update Just In Case -- there are presently out-of-date packages in the upstream docker registry. Reviewed-by: Paolo Bonzini Message-Id: <20211005205846.153724-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson From MAILER-DAEMON Wed Oct 06 10:13:27 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mY7fi-0004c8-UR for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 10:13:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY7fh-0004bx-Fs for qemu-commits@nongnu.org; Wed, 06 Oct 2021 10:13:25 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:51437 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY7fY-0005DU-3d for qemu-commits@nongnu.org; Wed, 06 Oct 2021 10:13:25 -0400 Received: from github.com (hubbernetes-node-364c5f9.va3-iad.github.net [10.48.125.69]) by smtp.github.com (Postfix) with ESMTPA id 6F1AE340BF4 for ; Wed, 6 Oct 2021 07:13:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633529595; bh=wULfDQPvmqfoRF+97N1aFMxqCzzdsQNTKgClI0NNCfA=; h=Date:From:To:Subject:From; b=IQtouk8To0uGQpLuGATmOOkYkA80k4VQwPw6jcxLwBP2icya208k4VutIuUlXnDN7 YdEqazhRBeAUAaGGL7ntBjVFLGhempbXiyj3uB5uwOSJMcv2Ku38IgnRujXBzPFGcH np1oGFsuhRhIrLiN+ucSBX0N39R6kM8xQJH2N3cE= Date: Wed, 06 Oct 2021 07:13:15 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] a6297e: include/block.h: remove outdated comment X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 14:13:25 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: a6297e1ade6d9981c4a8d43eb426830b49a7913c=0D https://github.com/qemu/qemu/commit/a6297e1ade6d9981c4a8d43eb426830= b49a7913c=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M include/block/block.h=0D =0D Log Message:=0D -----------=0D include/block.h: remove outdated comment=0D =0D There are a couple of errors in bdrv_drained_begin header comment:=0D - block_job_pause does not exist anymore, it has been replaced=0D with job_pause in b15de82867=0D - job_pause is automatically invoked as a .drained_begin callback=0D (child_job_drained_begin) by the child_job BdrvChildClass struct=0D in blockjob.c. So no additional pause should be required.=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Message-Id: <20210903113800.59970-1-eesposit@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: d1bbd965bd96028b0f5a8e3dc01b37f1f8ae4456=0D https://github.com/qemu/qemu/commit/d1bbd965bd96028b0f5a8e3dc01b37f= 1f8ae4456=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M storage-daemon/qemu-storage-daemon.c=0D =0D Log Message:=0D -----------=0D qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D =0D When configuring QEMU with --disable-fuse, the qemu-storage-daemon=0D still reports FUSE command line options in its help:=0D =0D $ qemu-storage-daemon -h=0D Usage: qemu-storage-daemon [options]=0D QEMU storage daemon=0D =0D --export [type=3D]fuse,id=3D,node-name=3D,mountpoint=3D= =0D [,growable=3Don|off][,writable=3Don|off]=0D export the specified block node over FUSE=0D =0D Remove this help message when FUSE is disabled, to avoid:=0D =0D $ qemu-storage-daemon --export fuse=0D qemu-storage-daemon: --export fuse: Invalid parameter 'fuse'=0D =0D Reported-by: Qing Wang =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210816180442.2000642-1-philmd@redhat.com>=0D Reviewed-by: Eric Blake =0D Reviewed-by: Hanna Reitz =0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 621d17378a40509757d5e03eb1c2f5305ff76df3=0D https://github.com/qemu/qemu/commit/621d17378a40509757d5e03eb1c2f53= 05ff76df3=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D M include/block/block.h=0D =0D Log Message:=0D -----------=0D block: implement bdrv_new_open_driver_opts()=0D =0D Add version of bdrv_new_open_driver() that supports QDict options.=0D We'll use it in further commit.=0D =0D Simply add one more argument to bdrv_new_open_driver() is worse, as=0D there are too many invocations of bdrv_new_open_driver() to update=0D then.=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Suggested-by: Kevin Wolf =0D Message-Id: <20210920115538.264372-2-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: f053b7e8005d7f72c2a8e686c4779f75b0ae631f=0D https://github.com/qemu/qemu/commit/f053b7e8005d7f72c2a8e686c4779f7= 5b0ae631f=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): fix and improve error handling=0D =0D - use ERRP_GUARD(): function calls error_prepend(), so it must use=0D ERRP_GUARD(), otherwise error_prepend() would not be called when=0D passed errp is error_fatal=0D =0D - drop error propagation, handle return code instead=0D =0D - for symmetry, do error_prepend() for the second failure=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-3-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 96796fae6f22931d91223d086e9fa56d0f3e6720=0D https://github.com/qemu/qemu/commit/96796fae6f22931d91223d086e9fa56= d0f3e6720=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): doc and style=0D =0D - options & flags is common pair for open-like functions, let's use it=0D= - add a comment that specifies use of @options=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-4-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: b11c8739ae38166acac0669cee94b7e236ccb639=0D https://github.com/qemu/qemu/commit/b11c8739ae38166acac0669cee94b7e= 236ccb639=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): don't use bdrv_open()=0D =0D Use bdrv_new_open_driver_opts() instead of complicated bdrv_open().=0D =0D Among other extra things bdrv_open() also check for white-listed=0D formats, which we don't want for internal node creation: currently=0D backup doesn't work when copy-before-write filter is not white-listed.=0D= As well block-stream doesn't work when copy-on-read is not=0D white-listed.=0D =0D Fixes: 751cec7a261adaf1145dc7adf6de7c9c084e5a0b=0D Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=3D2004812=0D Reported-by: Yanan Fu=0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-5-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: d318fc20b2ecb785bfc74bd8ad9e0da9e47d2104=0D https://github.com/qemu/qemu/commit/d318fc20b2ecb785bfc74bd8ad9e0da= 9e47d2104=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/image-fleecing=0D =0D Log Message:=0D -----------=0D iotests/image-fleecing: declare requirement of copy-before-write=0D =0D Now test fails if copy-before-write is not white-listed.=0D Let's skip test instead.=0D =0D Fixes: c0605985696a19ef034fa25d04f53f3b3b383896=0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-6-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: cc071629539dc1f303175a7e2d4ab854c0a8b20f=0D https://github.com/qemu/qemu/commit/cc071629539dc1f303175a7e2d4ab85= 4c0a8b20f=0D Author: Paolo Bonzini =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block/block-backend.c=0D M block/file-posix.c=0D M block/io.c=0D M hw/scsi/scsi-generic.c=0D M include/block/block_int.h=0D M include/sysemu/block-backend.h=0D =0D Log Message:=0D -----------=0D block: introduce max_hw_iov for use in scsi-generic=0D =0D Linux limits the size of iovecs to 1024 (UIO_MAXIOV in the kernel=0D sources, IOV_MAX in POSIX). Because of this, on some host adapters=0D requests with many iovecs are rejected with -EINVAL by the=0D io_submit() or readv()/writev() system calls.=0D =0D In fact, the same limit applies to SG_IO as well. To fix both the=0D EINVAL and the possible performance issues from using fewer iovecs=0D than allowed by Linux (some HBAs have max_segments as low as 128),=0D introduce a separate entry in BlockLimits to hold the max_segments=0D value from sysfs. This new limit is used only for SG_IO and clamped=0D to bs->bl.max_iov anyway, just like max_hw_transfer is clamped to=0D bs->bl.max_transfer.=0D =0D Reported-by: Halil Pasic =0D Cc: Hanna Reitz =0D Cc: Kevin Wolf =0D Cc: qemu-block@nongnu.org=0D Cc: qemu-stable@nongnu.org=0D Fixes: 18473467d5 ("file-posix: try BLKSECTGET on block devices too, do n= ot round to power of 2", 2021-06-25)=0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20210923130436.1187591-1-pbonzini@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: af6d4c56e15a45fb4d0cdf8d0335275b5ed8fbf7=0D https://github.com/qemu/qemu/commit/af6d4c56e15a45fb4d0cdf8d0335275= b5ed8fbf7=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/235=0D M tests/qemu-iotests/297=0D M tests/qemu-iotests/300=0D M tests/qemu-iotests/iotests.py=0D M tests/qemu-iotests/testenv.py=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D iotests: add 'qemu' package location to PYTHONPATH in testenv=0D =0D We can drop the sys.path hacking in various places by doing=0D this. Additionally, by doing it in one place right up top, we can print=0D= interesting warnings in case the environment does not look correct. (See=0D= next commit.)=0D =0D If we ever decide to change how the environment is crafted, all of the=0D= "help me find my python packages" goop is all in one place, right in one=0D= function.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-2-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: f39decb583669e4335eaf2d1a5b8183254df51d6=0D https://github.com/qemu/qemu/commit/f39decb583669e4335eaf2d1a5b8183= 254df51d6=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/297=0D =0D Log Message:=0D -----------=0D iotests/linters: check mypy files all at once=0D =0D We can circumvent the '__main__' redefinition problem by passing=0D --scripts-are-modules. Take mypy out of the loop per-filename and check=0D= everything in one go: it's quite a bit faster.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-4-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: ac7424631943c0c015934a3c92dca87b70f8f8e9=0D https://github.com/qemu/qemu/commit/ac7424631943c0c015934a3c92dca87= b70f8f8e9=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D iotests/mirror-top-perms: Adjust imports=0D =0D We need to import subpackages from the qemu namespace package; importing=0D= the namespace package alone doesn't bring the subpackages with it --=0D unless someone else (like iotests.py) imports them too.=0D =0D Adjust the imports.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-5-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 22968996946d1a4eaca7396099ba40867bb58642=0D https://github.com/qemu/qemu/commit/22968996946d1a4eaca7396099ba408= 67bb58642=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/migrate-bitmaps-test=0D =0D Log Message:=0D -----------=0D iotests/migrate-bitmaps-test: delint=0D =0D Mostly uninteresting stuff. Move the test injections under a function=0D named main() so that the variables used during that process aren't in=0D the global scope.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-6-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 3765315d4c84f9c0799744f43a314169baaccc05=0D https://github.com/qemu/qemu/commit/3765315d4c84f9c0799744f43a31416= 9baaccc05=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/pylintrc=0D M tests/qemu-iotests/testrunner.py=0D =0D Log Message:=0D -----------=0D iotests: Update for pylint 2.11.1=0D =0D 1. Ignore the new f-strings warning, we're not interested in doing a=0D full conversion at this time.=0D =0D 2. Just mute the unbalanced-tuple-unpacking warning, it's not a real=0D error in this case and muting the dozens of callsites is just not=0D worth it.=0D =0D 3. Add encodings to read_text().=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-7-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 5564f068162d67584a8c35e1efcc051483b9077d=0D https://github.com/qemu/qemu/commit/5564f068162d67584a8c35e1efcc051= 483b9077d=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D M block/block-backend.c=0D M block/file-posix.c=0D M block/io.c=0D M hw/scsi/scsi-generic.c=0D M include/block/block.h=0D M include/block/block_int.h=0D M include/sysemu/block-backend.h=0D M storage-daemon/qemu-storage-daemon.c=0D M tests/qemu-iotests/235=0D M tests/qemu-iotests/297=0D M tests/qemu-iotests/300=0D M tests/qemu-iotests/iotests.py=0D M tests/qemu-iotests/pylintrc=0D M tests/qemu-iotests/testenv.py=0D M tests/qemu-iotests/testrunner.py=0D M tests/qemu-iotests/tests/image-fleecing=0D M tests/qemu-iotests/tests/migrate-bitmaps-test=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into sta= ging=0D =0D Block layer patches=0D =0D - Fix I/O errors because of incorrectly detected max_iov=0D - Fix not white-listed copy-before-write=0D - qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D - iotests: update environment and linting configuration=0D =0D # gpg: Signature made Wed 06 Oct 2021 03:58:10 AM PDT=0D # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2= FD6=0D # gpg: issuer "kwolf@redhat.com"=0D # gpg: Good signature from "Kevin Wolf " [full]=0D =0D * remotes/kwolf/tags/for-upstream:=0D iotests: Update for pylint 2.11.1=0D iotests/migrate-bitmaps-test: delint=0D iotests/mirror-top-perms: Adjust imports=0D iotests/linters: check mypy files all at once=0D iotests: add 'qemu' package location to PYTHONPATH in testenv=0D block: introduce max_hw_iov for use in scsi-generic=0D iotests/image-fleecing: declare requirement of copy-before-write=0D block: bdrv_insert_node(): don't use bdrv_open()=0D block: bdrv_insert_node(): doc and style=0D block: bdrv_insert_node(): fix and improve error handling=0D block: implement bdrv_new_open_driver_opts()=0D qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D include/block.h: remove outdated comment=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e3acc2c1961c...5564f068162d= =0D From MAILER-DAEMON Wed Oct 06 11:49:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mY9AQ-0001w8-2I for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 11:49:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY9AO-0001sH-2V for qemu-commits@nongnu.org; Wed, 06 Oct 2021 11:49:12 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:40369 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY9AK-0002tv-UB for qemu-commits@nongnu.org; Wed, 06 Oct 2021 11:49:11 -0400 Received: from github.com (hubbernetes-node-3386cc9.ash1-iad.github.net [10.56.110.67]) by smtp.github.com (Postfix) with ESMTPA id C488B5E0ED3 for ; Wed, 6 Oct 2021 08:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633535347; bh=dnbGhGsAy1URcniga8glk1V9wQgAYCSXV9Y5QHpoFus=; h=Date:From:To:Subject:From; b=UMBVZ5JozbW4LRMQ/JOo2wp4ZTfUsf/Jpb7uXmYEUAwwVXSgzAlfveHEYKClX08qI KL+IW4FQB5Nj7ThHZVdhh6NnXM5SkjiPAgEj3svUDZ8nENX46HeX7iO7nU3Q4EmlDI i9IxhZ6BKDdMJXkIsGbcpxL56Zbyd7VAVXOBBb5E= Date: Wed, 06 Oct 2021 08:49:07 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -52 X-Spam_score: -5.3 X-Spam_bar: ----- X-Spam_report: (-5.3 / 5.0 requ) DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] a6297e: include/block.h: remove outdated comment X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 15:49:12 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: a6297e1ade6d9981c4a8d43eb426830b49a7913c=0D https://github.com/qemu/qemu/commit/a6297e1ade6d9981c4a8d43eb426830= b49a7913c=0D Author: Emanuele Giuseppe Esposito =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M include/block/block.h=0D =0D Log Message:=0D -----------=0D include/block.h: remove outdated comment=0D =0D There are a couple of errors in bdrv_drained_begin header comment:=0D - block_job_pause does not exist anymore, it has been replaced=0D with job_pause in b15de82867=0D - job_pause is automatically invoked as a .drained_begin callback=0D (child_job_drained_begin) by the child_job BdrvChildClass struct=0D in blockjob.c. So no additional pause should be required.=0D =0D Signed-off-by: Emanuele Giuseppe Esposito =0D Message-Id: <20210903113800.59970-1-eesposit@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: d1bbd965bd96028b0f5a8e3dc01b37f1f8ae4456=0D https://github.com/qemu/qemu/commit/d1bbd965bd96028b0f5a8e3dc01b37f= 1f8ae4456=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M storage-daemon/qemu-storage-daemon.c=0D =0D Log Message:=0D -----------=0D qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D =0D When configuring QEMU with --disable-fuse, the qemu-storage-daemon=0D still reports FUSE command line options in its help:=0D =0D $ qemu-storage-daemon -h=0D Usage: qemu-storage-daemon [options]=0D QEMU storage daemon=0D =0D --export [type=3D]fuse,id=3D,node-name=3D,mountpoint=3D= =0D [,growable=3Don|off][,writable=3Don|off]=0D export the specified block node over FUSE=0D =0D Remove this help message when FUSE is disabled, to avoid:=0D =0D $ qemu-storage-daemon --export fuse=0D qemu-storage-daemon: --export fuse: Invalid parameter 'fuse'=0D =0D Reported-by: Qing Wang =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210816180442.2000642-1-philmd@redhat.com>=0D Reviewed-by: Eric Blake =0D Reviewed-by: Hanna Reitz =0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 621d17378a40509757d5e03eb1c2f5305ff76df3=0D https://github.com/qemu/qemu/commit/621d17378a40509757d5e03eb1c2f53= 05ff76df3=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D M include/block/block.h=0D =0D Log Message:=0D -----------=0D block: implement bdrv_new_open_driver_opts()=0D =0D Add version of bdrv_new_open_driver() that supports QDict options.=0D We'll use it in further commit.=0D =0D Simply add one more argument to bdrv_new_open_driver() is worse, as=0D there are too many invocations of bdrv_new_open_driver() to update=0D then.=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Suggested-by: Kevin Wolf =0D Message-Id: <20210920115538.264372-2-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: f053b7e8005d7f72c2a8e686c4779f75b0ae631f=0D https://github.com/qemu/qemu/commit/f053b7e8005d7f72c2a8e686c4779f7= 5b0ae631f=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): fix and improve error handling=0D =0D - use ERRP_GUARD(): function calls error_prepend(), so it must use=0D ERRP_GUARD(), otherwise error_prepend() would not be called when=0D passed errp is error_fatal=0D =0D - drop error propagation, handle return code instead=0D =0D - for symmetry, do error_prepend() for the second failure=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-3-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 96796fae6f22931d91223d086e9fa56d0f3e6720=0D https://github.com/qemu/qemu/commit/96796fae6f22931d91223d086e9fa56= d0f3e6720=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): doc and style=0D =0D - options & flags is common pair for open-like functions, let's use it=0D= - add a comment that specifies use of @options=0D =0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-4-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: b11c8739ae38166acac0669cee94b7e236ccb639=0D https://github.com/qemu/qemu/commit/b11c8739ae38166acac0669cee94b7e= 236ccb639=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D =0D Log Message:=0D -----------=0D block: bdrv_insert_node(): don't use bdrv_open()=0D =0D Use bdrv_new_open_driver_opts() instead of complicated bdrv_open().=0D =0D Among other extra things bdrv_open() also check for white-listed=0D formats, which we don't want for internal node creation: currently=0D backup doesn't work when copy-before-write filter is not white-listed.=0D= As well block-stream doesn't work when copy-on-read is not=0D white-listed.=0D =0D Fixes: 751cec7a261adaf1145dc7adf6de7c9c084e5a0b=0D Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=3D2004812=0D Reported-by: Yanan Fu=0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-5-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: d318fc20b2ecb785bfc74bd8ad9e0da9e47d2104=0D https://github.com/qemu/qemu/commit/d318fc20b2ecb785bfc74bd8ad9e0da= 9e47d2104=0D Author: Vladimir Sementsov-Ogievskiy =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/image-fleecing=0D =0D Log Message:=0D -----------=0D iotests/image-fleecing: declare requirement of copy-before-write=0D =0D Now test fails if copy-before-write is not white-listed.=0D Let's skip test instead.=0D =0D Fixes: c0605985696a19ef034fa25d04f53f3b3b383896=0D Signed-off-by: Vladimir Sementsov-Ogievskiy =0D= Message-Id: <20210920115538.264372-6-vsementsov@virtuozzo.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: cc071629539dc1f303175a7e2d4ab854c0a8b20f=0D https://github.com/qemu/qemu/commit/cc071629539dc1f303175a7e2d4ab85= 4c0a8b20f=0D Author: Paolo Bonzini =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block/block-backend.c=0D M block/file-posix.c=0D M block/io.c=0D M hw/scsi/scsi-generic.c=0D M include/block/block_int.h=0D M include/sysemu/block-backend.h=0D =0D Log Message:=0D -----------=0D block: introduce max_hw_iov for use in scsi-generic=0D =0D Linux limits the size of iovecs to 1024 (UIO_MAXIOV in the kernel=0D sources, IOV_MAX in POSIX). Because of this, on some host adapters=0D requests with many iovecs are rejected with -EINVAL by the=0D io_submit() or readv()/writev() system calls.=0D =0D In fact, the same limit applies to SG_IO as well. To fix both the=0D EINVAL and the possible performance issues from using fewer iovecs=0D than allowed by Linux (some HBAs have max_segments as low as 128),=0D introduce a separate entry in BlockLimits to hold the max_segments=0D value from sysfs. This new limit is used only for SG_IO and clamped=0D to bs->bl.max_iov anyway, just like max_hw_transfer is clamped to=0D bs->bl.max_transfer.=0D =0D Reported-by: Halil Pasic =0D Cc: Hanna Reitz =0D Cc: Kevin Wolf =0D Cc: qemu-block@nongnu.org=0D Cc: qemu-stable@nongnu.org=0D Fixes: 18473467d5 ("file-posix: try BLKSECTGET on block devices too, do n= ot round to power of 2", 2021-06-25)=0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20210923130436.1187591-1-pbonzini@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: af6d4c56e15a45fb4d0cdf8d0335275b5ed8fbf7=0D https://github.com/qemu/qemu/commit/af6d4c56e15a45fb4d0cdf8d0335275= b5ed8fbf7=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/235=0D M tests/qemu-iotests/297=0D M tests/qemu-iotests/300=0D M tests/qemu-iotests/iotests.py=0D M tests/qemu-iotests/testenv.py=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D iotests: add 'qemu' package location to PYTHONPATH in testenv=0D =0D We can drop the sys.path hacking in various places by doing=0D this. Additionally, by doing it in one place right up top, we can print=0D= interesting warnings in case the environment does not look correct. (See=0D= next commit.)=0D =0D If we ever decide to change how the environment is crafted, all of the=0D= "help me find my python packages" goop is all in one place, right in one=0D= function.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-2-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: f39decb583669e4335eaf2d1a5b8183254df51d6=0D https://github.com/qemu/qemu/commit/f39decb583669e4335eaf2d1a5b8183= 254df51d6=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/297=0D =0D Log Message:=0D -----------=0D iotests/linters: check mypy files all at once=0D =0D We can circumvent the '__main__' redefinition problem by passing=0D --scripts-are-modules. Take mypy out of the loop per-filename and check=0D= everything in one go: it's quite a bit faster.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-4-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: ac7424631943c0c015934a3c92dca87b70f8f8e9=0D https://github.com/qemu/qemu/commit/ac7424631943c0c015934a3c92dca87= b70f8f8e9=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D iotests/mirror-top-perms: Adjust imports=0D =0D We need to import subpackages from the qemu namespace package; importing=0D= the namespace package alone doesn't bring the subpackages with it --=0D unless someone else (like iotests.py) imports them too.=0D =0D Adjust the imports.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-5-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 22968996946d1a4eaca7396099ba40867bb58642=0D https://github.com/qemu/qemu/commit/22968996946d1a4eaca7396099ba408= 67bb58642=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/tests/migrate-bitmaps-test=0D =0D Log Message:=0D -----------=0D iotests/migrate-bitmaps-test: delint=0D =0D Mostly uninteresting stuff. Move the test injections under a function=0D named main() so that the variables used during that process aren't in=0D the global scope.=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Hanna Reitz =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-6-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 3765315d4c84f9c0799744f43a314169baaccc05=0D https://github.com/qemu/qemu/commit/3765315d4c84f9c0799744f43a31416= 9baaccc05=0D Author: John Snow =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/pylintrc=0D M tests/qemu-iotests/testrunner.py=0D =0D Log Message:=0D -----------=0D iotests: Update for pylint 2.11.1=0D =0D 1. Ignore the new f-strings warning, we're not interested in doing a=0D full conversion at this time.=0D =0D 2. Just mute the unbalanced-tuple-unpacking warning, it's not a real=0D error in this case and muting the dozens of callsites is just not=0D worth it.=0D =0D 3. Add encodings to read_text().=0D =0D Signed-off-by: John Snow =0D Reviewed-by: Vladimir Sementsov-Ogievskiy =0D Reviewed-by: Kevin Wolf =0D Message-Id: <20210923180715.4168522-7-jsnow@redhat.com>=0D Signed-off-by: Kevin Wolf =0D =0D =0D Commit: 5564f068162d67584a8c35e1efcc051483b9077d=0D https://github.com/qemu/qemu/commit/5564f068162d67584a8c35e1efcc051= 483b9077d=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M block.c=0D M block/block-backend.c=0D M block/file-posix.c=0D M block/io.c=0D M hw/scsi/scsi-generic.c=0D M include/block/block.h=0D M include/block/block_int.h=0D M include/sysemu/block-backend.h=0D M storage-daemon/qemu-storage-daemon.c=0D M tests/qemu-iotests/235=0D M tests/qemu-iotests/297=0D M tests/qemu-iotests/300=0D M tests/qemu-iotests/iotests.py=0D M tests/qemu-iotests/pylintrc=0D M tests/qemu-iotests/testenv.py=0D M tests/qemu-iotests/testrunner.py=0D M tests/qemu-iotests/tests/image-fleecing=0D M tests/qemu-iotests/tests/migrate-bitmaps-test=0D M tests/qemu-iotests/tests/mirror-top-perms=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into sta= ging=0D =0D Block layer patches=0D =0D - Fix I/O errors because of incorrectly detected max_iov=0D - Fix not white-listed copy-before-write=0D - qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D - iotests: update environment and linting configuration=0D =0D # gpg: Signature made Wed 06 Oct 2021 03:58:10 AM PDT=0D # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2= FD6=0D # gpg: issuer "kwolf@redhat.com"=0D # gpg: Good signature from "Kevin Wolf " [full]=0D =0D * remotes/kwolf/tags/for-upstream:=0D iotests: Update for pylint 2.11.1=0D iotests/migrate-bitmaps-test: delint=0D iotests/mirror-top-perms: Adjust imports=0D iotests/linters: check mypy files all at once=0D iotests: add 'qemu' package location to PYTHONPATH in testenv=0D block: introduce max_hw_iov for use in scsi-generic=0D iotests/image-fleecing: declare requirement of copy-before-write=0D block: bdrv_insert_node(): don't use bdrv_open()=0D block: bdrv_insert_node(): doc and style=0D block: bdrv_insert_node(): fix and improve error handling=0D block: implement bdrv_new_open_driver_opts()=0D qemu-storage-daemon: Only display FUSE help when FUSE is built-in=0D include/block.h: remove outdated comment=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e3acc2c1961c...5564f068162d= =0D From MAILER-DAEMON Wed Oct 06 11:56:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mY9Hb-0005Yv-P3 for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 11:56:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY9Ha-0005Ok-5I for qemu-commits@nongnu.org; Wed, 06 Oct 2021 11:56:38 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:35233) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY9HU-0000dh-29 for qemu-commits@nongnu.org; Wed, 06 Oct 2021 11:56:36 -0400 Received: from github.com (hubbernetes-node-1fbe417.ash1-iad.github.net [10.56.120.39]) by smtp.github.com (Postfix) with ESMTPA id 476F89008CC for ; Wed, 6 Oct 2021 08:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633535791; bh=KfQTiWhAmSI2jrW+FzXsTLt5FcxvpsnBQJMUvVsZuRY=; h=Date:From:To:Subject:From; b=OnWA1bDiFSqiWDwWUFHc3Y9glQsmKwfLm7d9PXMo236AhTiu6L2rzPPrtd8fgoOxA 8i4GDTuUky4xpJANTxB/qZArTnM/LCVImZ/IJ3PuQg2xKNNUb4yiqXtBc7ZhNmUZ3d AR6Y6Y1DIEUUbSgT3gyKHR9OBIVo94vFQoj95jGM= Date: Wed, 06 Oct 2021 08:56:31 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 6a2b0f: tests/docker: Remove fedora-i386-cross from DOCKER... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 15:56:38 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 6a2b0fd171082eae19f1da043cf53b5a5a7b9c6c=0D https://github.com/qemu/qemu/commit/6a2b0fd171082eae19f1da043cf53b5= a5a7b9c6c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/Makefile.include=0D =0D Log Message:=0D -----------=0D tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES=0D =0D The image was upgraded to a full image in ee381b7fe146.=0D This makes it possible to use docker-test@image syntax=0D with this container.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930163636.721311-2-richard.henderson@linaro.org>=0D =0D =0D Commit: 08a13c4b247338329951238a6c47b94f70c387d2=0D https://github.com/qemu/qemu/commit/08a13c4b247338329951238a6c47b94= f70c387d2=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/dockerfiles/fedora-i386-cross.docker=0D =0D Log Message:=0D -----------=0D tests/docker: Fix fedora-i386-cross cross-compilation=0D =0D By using PKG_CONFIG_PATH instead of PKG_CONFIG_LIBDIR,=0D we were still including the 64-bit packages. Install=0D pcre-devel.i686 to fill a missing glib2 dependency.=0D =0D By using --extra-cflags instead of --cpu, we incorrectly=0D use the wrong probing during meson.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Richard W.M. Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930163636.721311-3-richard.henderson@linaro.org>=0D =0D =0D Commit: db637f270b52f8c2a1c55e7e707532532295715c=0D https://github.com/qemu/qemu/commit/db637f270b52f8c2a1c55e7e7075325= 32295715c=0D Author: Philipp Tomsich =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D tcg: add dup_const_tl wrapper=0D =0D dup_const always generates a uint64_t, which may exceed the size of a=0D target_long (generating warnings with recent-enough compilers).=0D =0D To ensure that we can use dup_const both for 64bit and 32bit targets,=0D this adds dup_const_tl, which either maps back to dup_const (for 64bit=0D= targets) or provides a similar implementation using 32bit constants.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Philipp Tomsich =0D Message-Id: <20211003214243.3813425-1-philipp.tomsich@vrull.eu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c433e298d99228e41a78d480a505cfcc8c9ea067=0D https://github.com/qemu/qemu/commit/c433e298d99228e41a78d480a505cfc= c8c9ea067=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Drop signness in tracing in cputlb.c=0D =0D We are already inconsistent about whether or not=0D MO_SIGN is set in trace_mem_get_info. Dropping it=0D entirely allows some simplification.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4b473e0c60d802bb69accab3177d350fc580e2a4=0D https://github.com/qemu/qemu/commit/4b473e0c60d802bb69accab3177d350= fc580e2a4=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/exec/memop.h=0D M target/arm/translate-a64.c=0D M target/s390x/tcg/translate_vx.c.inc=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D M tcg/s390/tcg-target.c.inc=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D tcg: Expand MO_SIZE to 3 bits=0D =0D We have lacked expressive support for memory sizes larger=0D than 64-bits for a while. Fixing that requires adjustment=0D to several points where we used this for array indexing,=0D and two places that develop -Wswitch warnings after the change.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9002ffcb7264947d9a193567b457dea42f15c321=0D https://github.com/qemu/qemu/commit/9002ffcb7264947d9a193567b457dea= 42f15c321=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M include/tcg/tcg.h=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/s390x/tcg/mem_helper.c=0D M target/sparc/ldst_helper.c=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/optimize.c=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D M tcg/s390/tcg-target.c.inc=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-ldst.c.inc=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D tcg: Rename TCGMemOpIdx to MemOpIdx=0D =0D We're about to move this out of tcg.h, so rename it=0D as we did when moving MemOp.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: abe2e23eb703b7e2b0479b4672d087cc37b0e667=0D https://github.com/qemu/qemu/commit/abe2e23eb703b7e2b0479b4672d087c= c37b0e667=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A include/exec/memopidx.h=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D tcg: Split out MemOpIdx to exec/memopidx.h=0D =0D Move this code from tcg/tcg.h to its own header.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b0702c91c66a9a9d8831ecb3d08f511e7d167489=0D https://github.com/qemu/qemu/commit/b0702c91c66a9a9d8831ecb3d08f511= e7d167489=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M tcg/tcg-op.c=0D M trace/mem.h=0D =0D Log Message:=0D -----------=0D trace/mem: Pass MemOpIdx to trace_mem_get_info=0D =0D We (will) often have the complete MemOpIdx handy, so use that.=0D =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c3e83e376cf028fade97072d86f33e4a92ddf9a2=0D https://github.com/qemu/qemu/commit/c3e83e376cf028fade97072d86f33e4= a92ddf9a2=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D =0D Log Message:=0D -----------=0D accel/tcg: Pass MemOpIdx to atomic_trace_*_post=0D =0D We will shortly use the MemOpIdx directly, but in the meantime=0D re-compute the trace meminfo.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 37aff08726b533c5df6a5a8685cca8a0de5e6619=0D https://github.com/qemu/qemu/commit/37aff08726b533c5df6a5a8685cca8a= 0de5e6619=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/cputlb.c=0D M accel/tcg/plugin-gen.c=0D M accel/tcg/user-exec.c=0D M include/qemu/plugin.h=0D M plugins/api.c=0D M plugins/core.c=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb=0D =0D Use the MemOpIdx directly, rather than the rearrangement=0D of the same bits currently done by the trace infrastructure.=0D Pass in enum qemu_plugin_mem_rw so that we are able to treat=0D read-modify-write operations as a single operation.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0583f775d2740f64739febf6496d9207552399f6=0D https://github.com/qemu/qemu/commit/0583f775d2740f64739febf6496d920= 7552399f6=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M tcg/tcg-op.c=0D M trace-events=0D R trace/mem.h=0D =0D Log Message:=0D -----------=0D trace: Split guest_mem_before=0D =0D There is no point in encoding load/store within a bit of=0D the memory trace info operand. Represent atomic operations=0D as a single read-modify-write tracepoint. Use MemOpIdx=0D instead of inventing a form specifically for traces.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dc29f4746fc8c641fb1182495c2662381cc16e23=0D https://github.com/qemu/qemu/commit/dc29f4746fc8c641fb1182495c26623= 81cc16e23=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/core/cpu.h=0D =0D Log Message:=0D -----------=0D hw/core/cpu: Re-sort the non-pointers to the end of CPUClass=0D =0D Despite the comment, the members were not kept at the end.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2552d60ebd6c519027d74bd452db7580b90e5cbd=0D https://github.com/qemu/qemu/commit/2552d60ebd6c519027d74bd452db758= 0b90e5cbd=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg-op-vec.c=0D =0D Log Message:=0D -----------=0D tcg: Expand usadd/ussub with umin/umax=0D =0D For usadd, we only have to consider overflow. Since ~B + B =3D=3D -1,=0D= the maximum value for A that saturates is ~B.=0D =0D For ussub, we only have to consider underflow. The minimum value=0D that saturates to 0 from A - B is B.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3704993f545efbe7b5a9ede83525f0d9c07cb31f=0D https://github.com/qemu/qemu/commit/3704993f545efbe7b5a9ede83525f0d= 9c07cb31f=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D R tcg/s390/tcg-target-con-set.h=0D R tcg/s390/tcg-target-con-str.h=0D R tcg/s390/tcg-target.c.inc=0D R tcg/s390/tcg-target.h=0D A tcg/s390x/tcg-target-con-set.h=0D A tcg/s390x/tcg-target-con-str.h=0D A tcg/s390x/tcg-target.c.inc=0D A tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Rename from tcg/s390=0D =0D This emphasizes that we don't support s390, only 64-bit s390x hosts.=0D =0D Reviewed-by: Thomas Huth =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 748b7f3ef78654f0ed11c85ed0b34a02f97ea856=0D https://github.com/qemu/qemu/commit/748b7f3ef78654f0ed11c85ed0b34a0= 2f97ea856=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Change FACILITY representation=0D =0D We will shortly need to be able to check facilities beyond the=0D first 64. Instead of explicitly masking against s390_facilities,=0D create a HAVE_FACILITY macro that indexes an array.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D ---=0D v2: Change name to HAVE_FACILITY (david)=0D =0D =0D Commit: eee6251b48f4d65e10feaff3f015241585d89f49=0D https://github.com/qemu/qemu/commit/eee6251b48f4d65e10feaff3f015241= 585d89f49=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg=0D =0D They are rightly values in the same enumeration.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 34ef7676090e35ffb7f7d8b8d92a843a6ee94931=0D https://github.com/qemu/qemu/commit/34ef7676090e35ffb7f7d8b8d92a843= a6ee94931=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target-con-str.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D A tcg/s390x/tcg-target.opc.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Add host vector framework=0D =0D Add registers and function stubs. The functionality=0D is disabled via squashing s390_facilities[2] to 0.=0D =0D We must still include results for the mandatory opcodes in=0D tcg_target_op_def, as all opcodes are checked during tcg init.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2dabf74252e2b9b9f23b1991d69a8def61442a2c=0D https://github.com/qemu/qemu/commit/2dabf74252e2b9b9f23b1991d69a8de= f61442a2c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_ld/st for vector types=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b33ce7251c9591635ca0f93bf5e75e7dbb844b5c=0D https://github.com/qemu/qemu/commit/b33ce7251c9591635ca0f93bf5e75e7= dbb844b5c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_mov for vector types=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 79cada8693d3e32162e41323b4bfbeaa765cad35=0D https://github.com/qemu/qemu/commit/79cada8693d3e32162e41323b4bfbea= a765cad35=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_dup*_vec=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a429ee2978a1bb81cfb737e382a47c119a2c0886=0D https://github.com/qemu/qemu/commit/a429ee2978a1bb81cfb737e382a47c1= 19a2c0886=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement minimal vector operations=0D =0D Implementing add, sub, and, or, xor as the minimal set.=0D This allows us to actually enable vectors in query_s390_facilities.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ae77bbe5747dc655bed213006798f9b07e2f79bf=0D https://github.com/qemu/qemu/commit/ae77bbe5747dc655bed213006798f9b= 07e2f79bf=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement andc, orc, abs, neg, not vector operations=0D =0D These logical and arithmetic operations are optional but trivial.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 479b61cbfafba997b97aec2e4d323c86240c24b0=0D https://github.com/qemu/qemu/commit/479b61cbfafba997b97aec2e4d323c8= 6240c24b0=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_mul_vec=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 22cb37b41720c8bcd48941b29b7c6ac1f990ab94=0D https://github.com/qemu/qemu/commit/22cb37b41720c8bcd48941b29b7c6ac= 1f990ab94=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement vector shift operations=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 220db7a6c461d9e33a50134f72a2e0cb3c6c5e62=0D https://github.com/qemu/qemu/commit/220db7a6c461d9e33a50134f72a2e0c= b3c6c5e62=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4223c9c1c6358f65fb2df2708c86f95faf235e30=0D https://github.com/qemu/qemu/commit/4223c9c1c6358f65fb2df2708c86f95= faf235e30=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.opc.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_sat_vec=0D =0D The unsigned saturations are handled via generic code=0D using min/max. The signed saturations are expanded using=0D double-sized arithmetic and a saturating pack.=0D =0D Since all operations are done via expansion, do not=0D actually set TCG_TARGET_HAS_sat_vec.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9bca986df88b8ea46b100e3d21cc9e653c83e0b3=0D https://github.com/qemu/qemu/commit/9bca986df88b8ea46b100e3d21cc9e6= 53c83e0b3=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ea3f2af8f1b87d7bced9b75ef2e788b66ec49961=0D https://github.com/qemu/qemu/commit/ea3f2af8f1b87d7bced9b75ef2e788b= 66ec49961=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec=0D =0D This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6723ff639cace5c91a7e0508fe08ea58675442d6=0D https://github.com/qemu/qemu/commit/6723ff639cace5c91a7e0508fe08ea5= 8675442d6=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/plugin-gen.c=0D M accel/tcg/user-exec.c=0D M include/exec/memop.h=0D A include/exec/memopidx.h=0D M include/hw/core/cpu.h=0D M include/qemu/plugin.h=0D M include/tcg/tcg.h=0D M meson.build=0D M plugins/api.c=0D M plugins/core.c=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/arm/translate-a64.c=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/s390x/tcg/mem_helper.c=0D M target/s390x/tcg/translate_vx.c.inc=0D M target/sparc/ldst_helper.c=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/optimize.c=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D R tcg/s390/tcg-target-con-set.h=0D R tcg/s390/tcg-target-con-str.h=0D R tcg/s390/tcg-target.c.inc=0D R tcg/s390/tcg-target.h=0D A tcg/s390x/tcg-target-con-set.h=0D A tcg/s390x/tcg-target-con-str.h=0D A tcg/s390x/tcg-target.c.inc=0D A tcg/s390x/tcg-target.h=0D A tcg/s390x/tcg-target.opc.h=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-ldst.c.inc=0D M tcg/tcg-op-vec.c=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D M tests/docker/Makefile.include=0D M tests/docker/dockerfiles/fedora-i386-cross.docker=0D M trace-events=0D R trace/mem.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211006' into = staging=0D =0D More fixes for fedora-i386-cross=0D Add dup_const_tl=0D Expand MemOp MO_SIZE=0D Move MemOpIdx out of tcg.h=0D Vector support for tcg/s390x=0D =0D # gpg: Signature made Wed 06 Oct 2021 08:12:53 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211006: (28 commits)=0D tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_sat_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec=0D tcg/s390x: Implement vector shift operations=0D tcg/s390x: Implement TCG_TARGET_HAS_mul_vec=0D tcg/s390x: Implement andc, orc, abs, neg, not vector operations=0D tcg/s390x: Implement minimal vector operations=0D tcg/s390x: Implement tcg_out_dup*_vec=0D tcg/s390x: Implement tcg_out_mov for vector types=0D tcg/s390x: Implement tcg_out_ld/st for vector types=0D tcg/s390x: Add host vector framework=0D tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg=0D tcg/s390x: Change FACILITY representation=0D tcg/s390x: Rename from tcg/s390=0D tcg: Expand usadd/ussub with umin/umax=0D hw/core/cpu: Re-sort the non-pointers to the end of CPUClass=0D trace: Split guest_mem_before=0D plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb=0D accel/tcg: Pass MemOpIdx to atomic_trace_*_post=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/5564f068162d...6723ff639cac= =0D From MAILER-DAEMON Wed Oct 06 14:46:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYBwH-00007d-MT for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 14:46:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYBwF-00007P-6F for qemu-commits@nongnu.org; Wed, 06 Oct 2021 14:46:48 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:41039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYBwA-0008QU-P4 for qemu-commits@nongnu.org; Wed, 06 Oct 2021 14:46:46 -0400 Received: from github.com (hubbernetes-node-ceff565.ac4-iad.github.net [10.52.211.88]) by smtp.github.com (Postfix) with ESMTPA id 7403D60022B for ; Wed, 6 Oct 2021 11:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633546001; bh=tD/y92LKMwi5F6IWGl1w6mpz/7+FaIXEXKTrbQbHrsU=; h=Date:From:To:Subject:From; b=AG0uYCfSMUU/tZRuvx6fS2bMGeaiWV/qXPoGKtGFaGA2xJ51mSuP90DvmPcTRbrZn omYpvDd83mXCSsBqCsqSbaCARdi69G+Th5b5bJ28Euop95rbTVw77GQq8CWK5a6yS0 5rAYFbq8Xahhzs6mffqC2Mwq0DvpIzuHa5Dz1Oek= Date: Wed, 06 Oct 2021 11:46:41 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 6a2b0f: tests/docker: Remove fedora-i386-cross from DOCKER... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 18:46:48 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 6a2b0fd171082eae19f1da043cf53b5a5a7b9c6c=0D https://github.com/qemu/qemu/commit/6a2b0fd171082eae19f1da043cf53b5= a5a7b9c6c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/Makefile.include=0D =0D Log Message:=0D -----------=0D tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES=0D =0D The image was upgraded to a full image in ee381b7fe146.=0D This makes it possible to use docker-test@image syntax=0D with this container.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930163636.721311-2-richard.henderson@linaro.org>=0D =0D =0D Commit: 08a13c4b247338329951238a6c47b94f70c387d2=0D https://github.com/qemu/qemu/commit/08a13c4b247338329951238a6c47b94= f70c387d2=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/dockerfiles/fedora-i386-cross.docker=0D =0D Log Message:=0D -----------=0D tests/docker: Fix fedora-i386-cross cross-compilation=0D =0D By using PKG_CONFIG_PATH instead of PKG_CONFIG_LIBDIR,=0D we were still including the 64-bit packages. Install=0D pcre-devel.i686 to fill a missing glib2 dependency.=0D =0D By using --extra-cflags instead of --cpu, we incorrectly=0D use the wrong probing during meson.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Richard W.M. Jones =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210930163636.721311-3-richard.henderson@linaro.org>=0D =0D =0D Commit: db637f270b52f8c2a1c55e7e707532532295715c=0D https://github.com/qemu/qemu/commit/db637f270b52f8c2a1c55e7e7075325= 32295715c=0D Author: Philipp Tomsich =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D tcg: add dup_const_tl wrapper=0D =0D dup_const always generates a uint64_t, which may exceed the size of a=0D target_long (generating warnings with recent-enough compilers).=0D =0D To ensure that we can use dup_const both for 64bit and 32bit targets,=0D this adds dup_const_tl, which either maps back to dup_const (for 64bit=0D= targets) or provides a similar implementation using 32bit constants.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Philipp Tomsich =0D Message-Id: <20211003214243.3813425-1-philipp.tomsich@vrull.eu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c433e298d99228e41a78d480a505cfcc8c9ea067=0D https://github.com/qemu/qemu/commit/c433e298d99228e41a78d480a505cfc= c8c9ea067=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Drop signness in tracing in cputlb.c=0D =0D We are already inconsistent about whether or not=0D MO_SIGN is set in trace_mem_get_info. Dropping it=0D entirely allows some simplification.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4b473e0c60d802bb69accab3177d350fc580e2a4=0D https://github.com/qemu/qemu/commit/4b473e0c60d802bb69accab3177d350= fc580e2a4=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/exec/memop.h=0D M target/arm/translate-a64.c=0D M target/s390x/tcg/translate_vx.c.inc=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D M tcg/s390/tcg-target.c.inc=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D tcg: Expand MO_SIZE to 3 bits=0D =0D We have lacked expressive support for memory sizes larger=0D than 64-bits for a while. Fixing that requires adjustment=0D to several points where we used this for array indexing,=0D and two places that develop -Wswitch warnings after the change.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9002ffcb7264947d9a193567b457dea42f15c321=0D https://github.com/qemu/qemu/commit/9002ffcb7264947d9a193567b457dea= 42f15c321=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M include/tcg/tcg.h=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/s390x/tcg/mem_helper.c=0D M target/sparc/ldst_helper.c=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/optimize.c=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D M tcg/s390/tcg-target.c.inc=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-ldst.c.inc=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D tcg: Rename TCGMemOpIdx to MemOpIdx=0D =0D We're about to move this out of tcg.h, so rename it=0D as we did when moving MemOp.=0D =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: abe2e23eb703b7e2b0479b4672d087cc37b0e667=0D https://github.com/qemu/qemu/commit/abe2e23eb703b7e2b0479b4672d087c= c37b0e667=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D A include/exec/memopidx.h=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D tcg: Split out MemOpIdx to exec/memopidx.h=0D =0D Move this code from tcg/tcg.h to its own header.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b0702c91c66a9a9d8831ecb3d08f511e7d167489=0D https://github.com/qemu/qemu/commit/b0702c91c66a9a9d8831ecb3d08f511= e7d167489=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M tcg/tcg-op.c=0D M trace/mem.h=0D =0D Log Message:=0D -----------=0D trace/mem: Pass MemOpIdx to trace_mem_get_info=0D =0D We (will) often have the complete MemOpIdx handy, so use that.=0D =0D Reviewed-by: Peter Maydell =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c3e83e376cf028fade97072d86f33e4a92ddf9a2=0D https://github.com/qemu/qemu/commit/c3e83e376cf028fade97072d86f33e4= a92ddf9a2=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D =0D Log Message:=0D -----------=0D accel/tcg: Pass MemOpIdx to atomic_trace_*_post=0D =0D We will shortly use the MemOpIdx directly, but in the meantime=0D re-compute the trace meminfo.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 37aff08726b533c5df6a5a8685cca8a0de5e6619=0D https://github.com/qemu/qemu/commit/37aff08726b533c5df6a5a8685cca8a= 0de5e6619=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/cputlb.c=0D M accel/tcg/plugin-gen.c=0D M accel/tcg/user-exec.c=0D M include/qemu/plugin.h=0D M plugins/api.c=0D M plugins/core.c=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb=0D =0D Use the MemOpIdx directly, rather than the rearrangement=0D of the same bits currently done by the trace infrastructure.=0D Pass in enum qemu_plugin_mem_rw so that we are able to treat=0D read-modify-write operations as a single operation.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0583f775d2740f64739febf6496d9207552399f6=0D https://github.com/qemu/qemu/commit/0583f775d2740f64739febf6496d920= 7552399f6=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/user-exec.c=0D M tcg/tcg-op.c=0D M trace-events=0D R trace/mem.h=0D =0D Log Message:=0D -----------=0D trace: Split guest_mem_before=0D =0D There is no point in encoding load/store within a bit of=0D the memory trace info operand. Represent atomic operations=0D as a single read-modify-write tracepoint. Use MemOpIdx=0D instead of inventing a form specifically for traces.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dc29f4746fc8c641fb1182495c2662381cc16e23=0D https://github.com/qemu/qemu/commit/dc29f4746fc8c641fb1182495c26623= 81cc16e23=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M include/hw/core/cpu.h=0D =0D Log Message:=0D -----------=0D hw/core/cpu: Re-sort the non-pointers to the end of CPUClass=0D =0D Despite the comment, the members were not kept at the end.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2552d60ebd6c519027d74bd452db7580b90e5cbd=0D https://github.com/qemu/qemu/commit/2552d60ebd6c519027d74bd452db758= 0b90e5cbd=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg-op-vec.c=0D =0D Log Message:=0D -----------=0D tcg: Expand usadd/ussub with umin/umax=0D =0D For usadd, we only have to consider overflow. Since ~B + B =3D=3D -1,=0D= the maximum value for A that saturates is ~B.=0D =0D For ussub, we only have to consider underflow. The minimum value=0D that saturates to 0 from A - B is B.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3704993f545efbe7b5a9ede83525f0d9c07cb31f=0D https://github.com/qemu/qemu/commit/3704993f545efbe7b5a9ede83525f0d= 9c07cb31f=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D R tcg/s390/tcg-target-con-set.h=0D R tcg/s390/tcg-target-con-str.h=0D R tcg/s390/tcg-target.c.inc=0D R tcg/s390/tcg-target.h=0D A tcg/s390x/tcg-target-con-set.h=0D A tcg/s390x/tcg-target-con-str.h=0D A tcg/s390x/tcg-target.c.inc=0D A tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Rename from tcg/s390=0D =0D This emphasizes that we don't support s390, only 64-bit s390x hosts.=0D =0D Reviewed-by: Thomas Huth =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 748b7f3ef78654f0ed11c85ed0b34a02f97ea856=0D https://github.com/qemu/qemu/commit/748b7f3ef78654f0ed11c85ed0b34a0= 2f97ea856=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Change FACILITY representation=0D =0D We will shortly need to be able to check facilities beyond the=0D first 64. Instead of explicitly masking against s390_facilities,=0D create a HAVE_FACILITY macro that indexes an array.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D ---=0D v2: Change name to HAVE_FACILITY (david)=0D =0D =0D Commit: eee6251b48f4d65e10feaff3f015241585d89f49=0D https://github.com/qemu/qemu/commit/eee6251b48f4d65e10feaff3f015241= 585d89f49=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg=0D =0D They are rightly values in the same enumeration.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 34ef7676090e35ffb7f7d8b8d92a843a6ee94931=0D https://github.com/qemu/qemu/commit/34ef7676090e35ffb7f7d8b8d92a843= a6ee94931=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target-con-str.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D A tcg/s390x/tcg-target.opc.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Add host vector framework=0D =0D Add registers and function stubs. The functionality=0D is disabled via squashing s390_facilities[2] to 0.=0D =0D We must still include results for the mandatory opcodes in=0D tcg_target_op_def, as all opcodes are checked during tcg init.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2dabf74252e2b9b9f23b1991d69a8def61442a2c=0D https://github.com/qemu/qemu/commit/2dabf74252e2b9b9f23b1991d69a8de= f61442a2c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_ld/st for vector types=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b33ce7251c9591635ca0f93bf5e75e7dbb844b5c=0D https://github.com/qemu/qemu/commit/b33ce7251c9591635ca0f93bf5e75e7= dbb844b5c=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_mov for vector types=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 79cada8693d3e32162e41323b4bfbeaa765cad35=0D https://github.com/qemu/qemu/commit/79cada8693d3e32162e41323b4bfbea= a765cad35=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement tcg_out_dup*_vec=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a429ee2978a1bb81cfb737e382a47c119a2c0886=0D https://github.com/qemu/qemu/commit/a429ee2978a1bb81cfb737e382a47c1= 19a2c0886=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement minimal vector operations=0D =0D Implementing add, sub, and, or, xor as the minimal set.=0D This allows us to actually enable vectors in query_s390_facilities.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ae77bbe5747dc655bed213006798f9b07e2f79bf=0D https://github.com/qemu/qemu/commit/ae77bbe5747dc655bed213006798f9b= 07e2f79bf=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement andc, orc, abs, neg, not vector operations=0D =0D These logical and arithmetic operations are optional but trivial.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 479b61cbfafba997b97aec2e4d323c86240c24b0=0D https://github.com/qemu/qemu/commit/479b61cbfafba997b97aec2e4d323c8= 6240c24b0=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_mul_vec=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 22cb37b41720c8bcd48941b29b7c6ac1f990ab94=0D https://github.com/qemu/qemu/commit/22cb37b41720c8bcd48941b29b7c6ac= 1f990ab94=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement vector shift operations=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 220db7a6c461d9e33a50134f72a2e0cb3c6c5e62=0D https://github.com/qemu/qemu/commit/220db7a6c461d9e33a50134f72a2e0c= b3c6c5e62=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4223c9c1c6358f65fb2df2708c86f95faf235e30=0D https://github.com/qemu/qemu/commit/4223c9c1c6358f65fb2df2708c86f95= faf235e30=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.opc.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_sat_vec=0D =0D The unsigned saturations are handled via generic code=0D using min/max. The signed saturations are expanded using=0D double-sized arithmetic and a saturating pack.=0D =0D Since all operations are done via expansion, do not=0D actually set TCG_TARGET_HAS_sat_vec.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9bca986df88b8ea46b100e3d21cc9e653c83e0b3=0D https://github.com/qemu/qemu/commit/9bca986df88b8ea46b100e3d21cc9e6= 53c83e0b3=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target-con-set.h=0D M tcg/s390x/tcg-target.c.inc=0D M tcg/s390x/tcg-target.h=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ea3f2af8f1b87d7bced9b75ef2e788b66ec49961=0D https://github.com/qemu/qemu/commit/ea3f2af8f1b87d7bced9b75ef2e788b= 66ec49961=0D Author: Richard Henderson =0D Date: 2021-10-05 (Tue, 05 Oct 2021)=0D =0D Changed paths:=0D M tcg/s390x/tcg-target.c.inc=0D =0D Log Message:=0D -----------=0D tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec=0D =0D This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6723ff639cace5c91a7e0508fe08ea58675442d6=0D https://github.com/qemu/qemu/commit/6723ff639cace5c91a7e0508fe08ea5= 8675442d6=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/atomic_common.c.inc=0D M accel/tcg/atomic_template.h=0D M accel/tcg/cputlb.c=0D M accel/tcg/plugin-gen.c=0D M accel/tcg/user-exec.c=0D M include/exec/memop.h=0D A include/exec/memopidx.h=0D M include/hw/core/cpu.h=0D M include/qemu/plugin.h=0D M include/tcg/tcg.h=0D M meson.build=0D M plugins/api.c=0D M plugins/core.c=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/arm/translate-a64.c=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/s390x/tcg/mem_helper.c=0D M target/s390x/tcg/translate_vx.c.inc=0D M target/sparc/ldst_helper.c=0D M tcg/aarch64/tcg-target.c.inc=0D M tcg/arm/tcg-target.c.inc=0D M tcg/i386/tcg-target.c.inc=0D M tcg/mips/tcg-target.c.inc=0D M tcg/optimize.c=0D M tcg/ppc/tcg-target.c.inc=0D M tcg/riscv/tcg-target.c.inc=0D R tcg/s390/tcg-target-con-set.h=0D R tcg/s390/tcg-target-con-str.h=0D R tcg/s390/tcg-target.c.inc=0D R tcg/s390/tcg-target.h=0D A tcg/s390x/tcg-target-con-set.h=0D A tcg/s390x/tcg-target-con-str.h=0D A tcg/s390x/tcg-target.c.inc=0D A tcg/s390x/tcg-target.h=0D A tcg/s390x/tcg-target.opc.h=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg-ldst.c.inc=0D M tcg/tcg-op-vec.c=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D M tests/docker/Makefile.include=0D M tests/docker/dockerfiles/fedora-i386-cross.docker=0D M trace-events=0D R trace/mem.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211006' into = staging=0D =0D More fixes for fedora-i386-cross=0D Add dup_const_tl=0D Expand MemOp MO_SIZE=0D Move MemOpIdx out of tcg.h=0D Vector support for tcg/s390x=0D =0D # gpg: Signature made Wed 06 Oct 2021 08:12:53 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211006: (28 commits)=0D tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_sat_vec=0D tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec=0D tcg/s390x: Implement vector shift operations=0D tcg/s390x: Implement TCG_TARGET_HAS_mul_vec=0D tcg/s390x: Implement andc, orc, abs, neg, not vector operations=0D tcg/s390x: Implement minimal vector operations=0D tcg/s390x: Implement tcg_out_dup*_vec=0D tcg/s390x: Implement tcg_out_mov for vector types=0D tcg/s390x: Implement tcg_out_ld/st for vector types=0D tcg/s390x: Add host vector framework=0D tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg=0D tcg/s390x: Change FACILITY representation=0D tcg/s390x: Rename from tcg/s390=0D tcg: Expand usadd/ussub with umin/umax=0D hw/core/cpu: Re-sort the non-pointers to the end of CPUClass=0D trace: Split guest_mem_before=0D plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb=0D accel/tcg: Pass MemOpIdx to atomic_trace_*_post=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/5564f068162d...6723ff639cac= =0D From MAILER-DAEMON Wed Oct 06 15:14:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYCMq-0003UK-F8 for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 15:14:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYCMo-0003UB-IZ for qemu-commits@nongnu.org; Wed, 06 Oct 2021 15:14:15 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:51781 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYCMk-0005XQ-Bp for qemu-commits@nongnu.org; Wed, 06 Oct 2021 15:14:13 -0400 Received: from github.com (hubbernetes-node-cb32252.va3-iad.github.net [10.48.221.62]) by smtp.github.com (Postfix) with ESMTPA id 2B8645C0AE9 for ; Wed, 6 Oct 2021 12:14:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633547648; bh=XXcdEUTFlCRULAJ7Lk43NYBMnGzgjz4eo6GAtTCuOpU=; h=Date:From:To:Subject:From; b=Am6Yqm443gZFKHwZFtRP+4Mg5FsXssQ9GnBXDxliO+JUqgZvA4LOzZk6dhKraE6YB H20zTEK8OKzqjCE1ArxUm5+4afuX9Xx0zxg+DERtoTyYn1r2ddt//XqKi0Nvvc0INT iZDB+opb8jcskFEkSB1D8K4icEFtx+Nm440HFVB0= Date: Wed, 06 Oct 2021 12:14:08 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c23b57: Hexagon (target/hexagon) probe the stores in a pac... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 19:14:15 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: c23b5764e79f3951e98160faf6e97284453c4056=0D https://github.com/qemu/qemu/commit/c23b5764e79f3951e98160faf6e9728= 4453c4056=0D Author: Taylor Simpson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/helper.h=0D M target/hexagon/op_helper.c=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/hex_sigsegv.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) probe the stores in a packet at start of commi= t=0D =0D When a packet has 2 stores, either both commit or neither commit.=0D At the beginning of gen_commit_packet, we check for multiple stores.=0D If there are multiple stores, call a helper that will probe each of=0D them before proceeding with the commit.=0D =0D Note that we don't call the probe helper for packets with only one=0D store. Therefore, we call process_store_log before anything else=0D involved in committing the packet.=0D =0D We also fix a typo in the comment in process_store_log.=0D =0D Test case added in tests/tcg/hexagon/hex_sigsegv.c=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Taylor Simpson =0D Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>=0D =0D =0D Commit: f844f745a81a8b8dc7f85eaa3fe6a3bb880afaff=0D https://github.com/qemu/qemu/commit/f844f745a81a8b8dc7f85eaa3fe6a3b= b880afaff=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/macros.h=0D =0D Log Message:=0D -----------=0D target/hexagon: Remove unused TCG temporary from predicated loads=0D =0D The gen_pred_cancel() function, introduced in commit a646e99cb90=0D (Hexagon macros) doesn't use the 'one' TCG temporary; remove it.=0D =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Taylor Simpson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003004750.3608983-2-f4bug@amsat.org>=0D =0D =0D Commit: 23803bbe524c34d5725508f169a0a23f652e6584=0D https://github.com/qemu/qemu/commit/23803bbe524c34d5725508f169a0a23= f652e6584=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/genptr.c=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D target/hexagon: Use tcg_constant_*=0D =0D Replace uses of tcg_const_* with the allocate and free close together.=0D= =0D Inspired-by: Richard Henderson =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Taylor Simpson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003004750.3608983-3-f4bug@amsat.org>=0D =0D =0D Commit: ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def=0D https://github.com/qemu/qemu/commit/ca61fa4b803e5d0abaf6f1ceb690f23= bb78a4def=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/genptr.c=0D M target/hexagon/helper.h=0D M target/hexagon/macros.h=0D M target/hexagon/op_helper.c=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/hex_sigsegv.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into= staging=0D =0D Change from Philippe - Use tcg_constant_*=0D Change from Philippe - Remove unused TCG temp=0D Change from Taylor - Probe the stores in a packet at start of commit=0D =0D # gpg: Signature made Wed 06 Oct 2021 08:44:13 AM PDT=0D # gpg: using RSA key 7B0244FB12DE4422=0D # gpg: Good signature from "Taylor Simpson (Rock on) " [marginal]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE = 4422=0D =0D * remotes/quic/tags/pull-hex-20211006:=0D target/hexagon: Use tcg_constant_*=0D target/hexagon: Remove unused TCG temporary from predicated loads=0D Hexagon (target/hexagon) probe the stores in a packet at start of commi= t=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/6723ff639cac...ca61fa4b803e= =0D From MAILER-DAEMON Wed Oct 06 16:44:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYDmV-0005Yq-7f for mharc-qemu-commits@gnu.org; Wed, 06 Oct 2021 16:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYDmU-0005Yh-51 for qemu-commits@nongnu.org; Wed, 06 Oct 2021 16:44:50 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:42133) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYDmR-0002NX-Mv for qemu-commits@nongnu.org; Wed, 06 Oct 2021 16:44:49 -0400 Received: from github.com (hubbernetes-node-d558f35.ash1-iad.github.net [10.56.101.23]) by smtp.github.com (Postfix) with ESMTPA id 0C06D9008CC for ; Wed, 6 Oct 2021 13:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633553087; bh=HpWHLIrXLQl+vXGl9k069rqbhx4eRBwG2qiC3FZl9h0=; h=Date:From:To:Subject:From; b=wQjhNCMClAufCiLh1tWu8D3N/OEufIJw1amlqRR/cUw4beb4Gy+qm06w6aV5oAlJn dpvl7Coc9zhy2O7aCipkfYMWs6Bf7Rn54qzvIDYKbmE+h6gPsmMB+bfcRu6dkDcV++ W5ApeqAYJO4j/U7cDCH6F7geA3o9TFEYRWLTWXJ8= Date: Wed, 06 Oct 2021 13:44:47 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c23b57: Hexagon (target/hexagon) probe the stores in a pac... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Oct 2021 20:44:50 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: c23b5764e79f3951e98160faf6e97284453c4056=0D https://github.com/qemu/qemu/commit/c23b5764e79f3951e98160faf6e9728= 4453c4056=0D Author: Taylor Simpson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/helper.h=0D M target/hexagon/op_helper.c=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/hex_sigsegv.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) probe the stores in a packet at start of commi= t=0D =0D When a packet has 2 stores, either both commit or neither commit.=0D At the beginning of gen_commit_packet, we check for multiple stores.=0D If there are multiple stores, call a helper that will probe each of=0D them before proceeding with the commit.=0D =0D Note that we don't call the probe helper for packets with only one=0D store. Therefore, we call process_store_log before anything else=0D involved in committing the packet.=0D =0D We also fix a typo in the comment in process_store_log.=0D =0D Test case added in tests/tcg/hexagon/hex_sigsegv.c=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Taylor Simpson =0D Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>=0D =0D =0D Commit: f844f745a81a8b8dc7f85eaa3fe6a3bb880afaff=0D https://github.com/qemu/qemu/commit/f844f745a81a8b8dc7f85eaa3fe6a3b= b880afaff=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/macros.h=0D =0D Log Message:=0D -----------=0D target/hexagon: Remove unused TCG temporary from predicated loads=0D =0D The gen_pred_cancel() function, introduced in commit a646e99cb90=0D (Hexagon macros) doesn't use the 'one' TCG temporary; remove it.=0D =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Taylor Simpson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003004750.3608983-2-f4bug@amsat.org>=0D =0D =0D Commit: 23803bbe524c34d5725508f169a0a23f652e6584=0D https://github.com/qemu/qemu/commit/23803bbe524c34d5725508f169a0a23= f652e6584=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/genptr.c=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D target/hexagon: Use tcg_constant_*=0D =0D Replace uses of tcg_const_* with the allocate and free close together.=0D= =0D Inspired-by: Richard Henderson =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Taylor Simpson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003004750.3608983-3-f4bug@amsat.org>=0D =0D =0D Commit: ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def=0D https://github.com/qemu/qemu/commit/ca61fa4b803e5d0abaf6f1ceb690f23= bb78a4def=0D Author: Richard Henderson =0D Date: 2021-10-06 (Wed, 06 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/genptr.c=0D M target/hexagon/helper.h=0D M target/hexagon/macros.h=0D M target/hexagon/op_helper.c=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/hex_sigsegv.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into= staging=0D =0D Change from Philippe - Use tcg_constant_*=0D Change from Philippe - Remove unused TCG temp=0D Change from Taylor - Probe the stores in a packet at start of commit=0D =0D # gpg: Signature made Wed 06 Oct 2021 08:44:13 AM PDT=0D # gpg: using RSA key 7B0244FB12DE4422=0D # gpg: Good signature from "Taylor Simpson (Rock on) " [marginal]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE = 4422=0D =0D * remotes/quic/tags/pull-hex-20211006:=0D target/hexagon: Use tcg_constant_*=0D target/hexagon: Remove unused TCG temporary from predicated loads=0D Hexagon (target/hexagon) probe the stores in a packet at start of commi= t=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/6723ff639cac...ca61fa4b803e= =0D From MAILER-DAEMON Thu Oct 07 10:19:51 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYUFT-0007MC-6P for mharc-qemu-commits@gnu.org; Thu, 07 Oct 2021 10:19:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYUFQ-0007Lt-Ck for qemu-commits@nongnu.org; Thu, 07 Oct 2021 10:19:48 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:44293 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYUFM-000379-Ne for qemu-commits@nongnu.org; Thu, 07 Oct 2021 10:19:48 -0400 Received: from github.com (hubbernetes-node-2b0cb0b.ac4-iad.github.net [10.52.205.45]) by smtp.github.com (Postfix) with ESMTPA id E56C45602DD for ; Thu, 7 Oct 2021 07:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633616383; bh=mrvSssGEZfGl+Em13LnL6FAuNZ78ebmtkoJPZDTcPVA=; h=Date:From:To:Subject:From; b=F1DIky2mV3kxcNeRVFQcqL0dxV/WYptanEhZCPBjGM+RnS0HQ3g3hleEYnjM6smEB 6tBKq/OpaBtGLV+ahblvEWAPVCGTP6yU3zZftQwnlwaCJscHovjv9t6BZE2DsChFM4 GVYG3bmMAhEbysOnBrEW226S2aGtPuMZKP8+pL3o= Date: Thu, 07 Oct 2021 07:19:43 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c5b4ee: target/riscv: Introduce temporary in gen_add_uw() X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 14:19:49 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: c5b4ee5bb799685e1c5a4a30ab40013a984daded=0D https://github.com/qemu/qemu/commit/c5b4ee5bb799685e1c5a4a30ab40013= a984daded=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Introduce temporary in gen_add_uw()=0D =0D Following the recent changes in translate.c, gen_add_uw() causes=0D failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these=0D regressions by introducing a temporary.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu=0D Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e47fb6c1e96a4e50603c13b8408e0745a09cd867=0D https://github.com/qemu/qemu/commit/e47fb6c1e96a4e50603c13b8408e074= 5a09cd867=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: fix clzw implementation to operate on arg1=0D =0D The refactored gen_clzw() uses ret as its argument, instead of arg1.=0D Fix it.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu=0D Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 45d1749c1c32f7f44e02f267407cd6bca88fb84a=0D https://github.com/qemu/qemu/commit/45d1749c1c32f7f44e02f267407cd6b= ca88fb84a=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: clwz must ignore high bits (use shift-left & changed logi= c)=0D =0D Assume clzw being executed on a register that is not sign-extended, such=0D= as for the following sequence that uses (1ULL << 63) | 392 as the operand= =0D to clzw:=0D bseti a2, zero, 63=0D addi a2, a2, 392=0D clzw a3, a2=0D The correct result of clzw would be 23, but the current implementation=0D= returns -32 (as it performs a 64bit clz, which results in 0 leading zero=0D= bits, and then subtracts 32).=0D =0D Fix this by changing the implementation to:=0D 1. shift the original register up by 32=0D 2. performs a target-length (64bit) clz=0D 3. return 32 if no bits are set=0D =0D Marking this instruction as 'w-form' (i.e., setting ctx->w) would not=0D correctly model the behaviour, as the instruction should not perform=0D a zero-extensions on the input (after all, it is not a .uw instruction)=0D= and the result is always in the range 0..32 (so neither a sign-extension=0D= nor a zero-extension on the result will ever be needed). Consequently,=0D= we do not set ctx->w and mark the instruction as EXT_NONE.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: LIU Zhiwei=0D Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 878dd0e9ac18af657dcbdb598bb2eb1278606d3a=0D https://github.com/qemu/qemu/commit/878dd0e9ac18af657dcbdb598bb2eb1= 278606d3a=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties=0D =0D The bitmanipulation ISA extensions will be ratified as individual=0D small extension packages instead of a large B-extension. The first=0D new instructions through the door (these have completed public review)=0D= are Zb[abcs].=0D =0D This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for=0D these in target/riscv/cpu.[ch].=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: bb4dc158e084c3293b553c37f3ace99997aeff6f=0D https://github.com/qemu/qemu/commit/bb4dc158e084c3293b553c37f3ace99= 997aeff6f=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zba-extension=0D =0D The following instructions are part of Zba:=0D - add.uw (RV64 only)=0D - sh[123]add (RV32 and RV64)=0D - sh[123]add.uw (RV64-only)=0D - slli.uw (RV64-only)=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: dd98a74034a4ae6a80162f2db42e67260875eb5e=0D https://github.com/qemu/qemu/commit/dd98a74034a4ae6a80162f2db42e672= 60875eb5e=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove the W-form instructions from Zbs=0D =0D Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form=0D= instructions for Zbs (single-bit instructions). Remove them.=0D =0D Note that these instructions had already been removed for the 0.93=0D version of the draft-B extention and have not been present in the=0D binutils patches circulating in January 2021.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 628d8c88c14e6ee8eef0c6d3b7178dbfc7770f03=0D https://github.com/qemu/qemu/commit/628d8c88c14e6ee8eef0c6d3b7178db= fc7770f03=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 d= raft-B)=0D =0D The Zb[abcs] ratification package does not include the proposed=0D shift-one instructions. There currently is no clear plan to whether=0D these (or variants of them) will be ratified as Zbo (or a different=0D extension) or what the timeframe for such a decision could be.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: f36a4a89aad493990084a9b540ed511cb66701ce=0D https://github.com/qemu/qemu/commit/f36a4a89aad493990084a9b540ed511= cb66701ce=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zbs-extension=0D =0D The following instructions are part of Zbs:=0D - b{set,clr,ext,inv}=0D - b{set,clr,ext,inv}i=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fd4b81a304a5d50e719019d22eacca2d8ef4de69=0D https://github.com/qemu/qemu/commit/fd4b81a304a5d50e719019d22eacca2= d8ef4de69=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add instructions of the Zbc-extension=0D =0D The following instructions are part of Zbc:=0D - clmul=0D - clmulh=0D - clmulr=0D =0D Note that these instructions were already defined in the pre-0.93 and=0D the 0.93 draft-B proposals, but had not been omitted in the earlier=0D addition of draft-B to QEmu.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 16c38f36f5cb42bbfe7b9cd4bb29206a3ecab760=0D https://github.com/qemu/qemu/commit/16c38f36f5cb42bbfe7b9cd4bb29206= a3ecab760=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zbb-extension=0D =0D This reassigns the instructions that are part of Zbb into it, with the=0D= notable exceptions of the instructions (rev8, zext.w and orc.b) that=0D changed due to gorci, grevi and pack not being part of Zb[abcs].=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: d7a4fcb03433edefd19b7db3c4d20ed750b5833b=0D https://github.com/qemu/qemu/commit/d7a4fcb03433edefd19b7db3c4d20ed= 750b5833b=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci=0D =0D The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a=0D orc.b instruction (equivalent to the orc.b pseudo-instruction built on=0D= gorci from pre-0.93 draft-B) is available, mainly targeting=0D string-processing workloads.=0D =0D This commit adds the new orc.b instruction and removed gorc/gorci.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 7e68e6c79b9de5c923e478ea6794a5143610b765=0D https://github.com/qemu/qemu/commit/7e68e6c79b9de5c923e478ea6794a51= 43610b765=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add a REQUIRE_32BIT macro=0D =0D With the changes to Zb[abcs], there's some encodings that are=0D different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,=0D we'll need a helper macro allowing us to select on RV32, as well.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a1095bdcb050f0a17afb3fcb8a36543fb58f4ea9=0D https://github.com/qemu/qemu/commit/a1095bdcb050f0a17afb3fcb8a36543= fb58f4ea9=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add rev8 instruction, removing grev/grevi=0D =0D The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a=0D rev8 instruction (equivalent to the rev8 pseudo-instruction built on=0D grevi from pre-0.93 draft-B) is available.=0D =0D This commit adds the new rev8 instruction and removes grev/grevi.=0D =0D Note that there is no W-form of this instruction (both a=0D sign-extending and zero-extending 32-bit version can easily be=0D synthesized by following rev8 with either a srai or srli instruction=0D on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are=0D different.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 06dfa8a5c5e79c2be7672b0a56e08c7f6d350148=0D https://github.com/qemu/qemu/commit/06dfa8a5c5e79c2be7672b0a56e08c7= f6d350148=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh= =0D =0D The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a=0D= zext.h instruction is provided (built on pack/packh from pre-0.93=0D draft-B) is available.=0D =0D This commit adds zext.h and removes the pack* instructions.=0D =0D Note that the encodings for zext.h are different between RV32 and=0D RV64, which is handled through REQUIRE_32BIT.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 9916ea3c97f6cbd46d912ecc80dfe94baed5d288=0D https://github.com/qemu/qemu/commit/9916ea3c97f6cbd46d912ecc80dfe94= baed5d288=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/insn32.decode=0D =0D Log Message:=0D -----------=0D target/riscv: Remove RVB (replaced by Zb[abcs])=0D =0D With everything classified as Zb[abcs] and pre-0.93 draft-B=0D instructions that are not part of Zb[abcs] removed, we can remove the=0D remaining support code for RVB.=0D =0D Note that RVB has been retired for good and misa.B will neither mean=0D 'some' or 'all of' Zb*:=0D https://lists.riscv.org/g/tech-bitmanip/message/532=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 02c1b569a15b4b06a3c69b6cb1713830a29cb01f=0D https://github.com/qemu/qemu/commit/02c1b569a15b4b06a3c69b6cb171383= 0a29cb01f=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M disas/riscv.c=0D =0D Log Message:=0D -----------=0D disas/riscv: Add Zb[abcs] instructions=0D =0D With the addition of Zb[abcs], we also need to add disassembler=0D support for these new instructions.=0D =0D Signed-off-by: Philipp Tomsich =0D Acked-by: Alistair Francis =0D Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a88f0402391e9075df774affe5482d1286b9237e=0D https://github.com/qemu/qemu/commit/a88f0402391e9075df774affe5482d1= 286b9237e=0D Author: Frank Chang =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=3D1 in mark_fs= _dirty()=0D =0D When V=3D1, both vsstauts.FS and HS-level sstatus.FS are in effect.=0D Modifying the floating-point state when V=3D1 causes both fields to=0D be set to 3 (Dirty).=0D =0D However, it's possible that HS-level sstatus.FS is Clean and VS-level=0D vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=3D1.=0D= We can't early return for this case because we still need to set=0D sstatus.FS to Dirty according to spec.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Vincent Chen =0D Tested-by: Vincent Chen =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210921020234.123448-1-frank.chang@sifive.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 34229c46a721b2acf3cc1c1af3324f7468852330=0D https://github.com/qemu/qemu/commit/34229c46a721b2acf3cc1c1af3324f7= 468852330=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/ibex_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: ibex_uart: Register device in 'input' category=0D =0D The category of ibex_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 5515ff162e8c20bfe907e21b2a3b9bed12a8ef67=0D https://github.com/qemu/qemu/commit/5515ff162e8c20bfe907e21b2a3b9be= d12a8ef67=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/shakti_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: shakti_uart: Register device in 'input' category=0D =0D The category of shakti_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 6a03349007f84e514e2e3def25c3f85400fdb47a=0D https://github.com/qemu/qemu/commit/6a03349007f84e514e2e3def25c3f85= 400fdb47a=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sifive_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: sifive_uart: Register device in 'input' category=0D =0D The category of sifive_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 284a66a8f6ffc8a720071b3f3cbc10cff0637337=0D https://github.com/qemu/qemu/commit/284a66a8f6ffc8a720071b3f3cbc10c= ff0637337=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition=0D= =0D The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the=0D size occupied by all the registers. However all registers are=0D 32-bit wide, and the MemoryRegionOps handlers are restricted to=0D 32-bit:=0D =0D static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D {=0D .read =3D mchp_pfsoc_mmuart_read,=0D .write =3D mchp_pfsoc_mmuart_write,=0D .impl =3D {=0D .min_access_size =3D 4,=0D .max_access_size =3D 4,=0D },=0D =0D Avoid being triskaidekaphobic, simplify by using the number of=0D registers.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Message-id: 20210925133407.1259392-2-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 24ce762df7d10175db1f91962d4fb1355b2645d2=0D https://github.com/qemu/qemu/commit/24ce762df7d10175db1f91962d4fb13= 55b2645d2=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container=0D =0D Our device have 2 different I/O regions:=0D - a 16550 UART mapped for 32-bit accesses=0D - 13 extra registers=0D =0D Instead of mapping each region on the main bus, introduce=0D a container, map the 2 devices regions on the container,=0D and map the container on the main bus.=0D =0D Before:=0D =0D (qemu) info mtree=0D ...=0D 0000000020100000-000000002010001f (prio 0, i/o): serial=0D 0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020102000-000000002010201f (prio 0, i/o): serial=0D 0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020104000-000000002010401f (prio 0, i/o): serial=0D 0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020106000-000000002010601f (prio 0, i/o): serial=0D 0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart=0D= =0D After:=0D =0D (qemu) info mtree=0D ...=0D 0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020100000-000000002010001f (prio 0, i/o): serial=0D 0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020102000-000000002010201f (prio 0, i/o): serial=0D 0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020104000-000000002010401f (prio 0, i/o): serial=0D 0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020106000-000000002010601f (prio 0, i/o): serial=0D 0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Tested-by: Bin Meng =0D Message-id: 20210925133407.1259392-3-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 31ca70b5ff7c6ac600211f60e3ab024642fe5abb=0D https://github.com/qemu/qemu/commit/31ca70b5ff7c6ac600211f60e3ab024= 642fe5abb=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART=0D =0D - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it=0D - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART=0D - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()=0D - Add DeviceReset() method=0D - Add vmstate structure for migration=0D - Register device in 'input' category=0D - Keep mchp_pfsoc_mmuart_create() behavior=0D =0D Note, serial_mm_init() calls qdev_set_legacy_instance_id().=0D This call is only needed for backwards-compatibility of incoming=0D migration data with old versions of QEMU which implemented migration=0D of devices with hand-rolled code. Since this device didn't previously=0D handle migration at all, then it doesn't need to set the legacy=0D instance ID.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Message-id: 20210925133407.1259392-4-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5=0D https://github.com/qemu/qemu/commit/b7af62ae2ca4a5f36a36d98e37d59e9= 6fb3f8ef5=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/dma/sifive_pdma.c=0D =0D Log Message:=0D -----------=0D hw/dma: sifive_pdma: Fix Control.claim bit detection=0D =0D At present the codes detect whether the DMA channel is claimed by:=0D =0D claimed =3D !!s->chan[ch].control & CONTROL_CLAIM;=0D =0D As ! has higher precedence over & (bitwise and), this is essentially=0D =0D claimed =3D (!!s->chan[ch].control) & CONTROL_CLAIM;=0D =0D which is wrong, as any non-zero bit set in the control register will=0D produce a result of a claimed channel.=0D =0D Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Con= trol.claim is set")=0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 47b5fbf5a3f9c88936a0532ecb918f5e58ad348c=0D https://github.com/qemu/qemu/commit/47b5fbf5a3f9c88936a0532ecb918f5= e58ad348c=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/dma/sifive_pdma.c=0D =0D Log Message:=0D -----------=0D hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed=0D =0D If Control.run bit is set while not preserving the Control.claim=0D bit, the DMA transfer shall not be started.=0D =0D The following result is PDMA tested in U-Boot on Unleashed board:=0D =0D =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0=0D =3D> mw.l 0x3000000 0x1 <=3D Claim channel 0=0D =3D> mw.l 0x3000004 0x55000000 <=3D wsize =3D rsize =3D 5 (= 2^5 =3D 32 bytes)=0D =3D> mw.q 0x3000008 0x2 <=3D NextBytes =3D 2=0D =3D> mw.q 0x3000010 0x84000000 <=3D NextDestination =3D 0x8= 4000000=0D =3D> mw.q 0x3000018 0x84001000 <=3D NextSource =3D 0x840010= 00=0D =3D> mw.l 0x84000000 0x87654321 <=3D Fill test data to dst=0D= =3D> mw.l 0x84001000 0x12345678 <=3D Fill test data to src=0D= =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents=0D 84000000: 87654321 !Ce.=0D 84001000: 12345678 xV4.=0D =3D> md.l 0x3000000 8 <=3D Dump PDMA status=0D 03000000: 00000001 55000000 00000002 00000000 .......U........=0D 03000010: 84000000 00000000 84001000 00000000 ................=0D =3D> mw.l 0x3000000 0x2 <=3D Set channel 0 run bit o= nly=0D =3D> md.l 0x3000000 8 <=3D Dump PDMA status=0D 03000000: 00000000 55000000 00000002 00000000 .......U........=0D 03000010: 84000000 00000000 84001000 00000000 ................=0D =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents=0D 84000000: 87654321 !Ce.=0D 84001000: 12345678 xV4.=0D =0D Signed-off-by: Bin Meng =0D Acked-by: Alistair Francis =0D Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07=0D https://github.com/qemu/qemu/commit/9ae6ecd848dcd1b32003526ab65a0d4= c644dfb07=0D Author: Alistair Francis =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/shakti_c.c=0D =0D Log Message:=0D -----------=0D hw/riscv: shakti_c: Mark as not user creatable=0D =0D Mark the shakti_c machine as not user creatable.=0D =0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639=0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D =0D =0D Commit: 3c019339830affe7974b738e0c2b71bd28778ef0=0D https://github.com/qemu/qemu/commit/3c019339830affe7974b738e0c2b71b= d28778ef0=0D Author: Richard Henderson =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M disas/riscv.c=0D M hw/char/ibex_uart.c=0D M hw/char/mchp_pfsoc_mmuart.c=0D M hw/char/shakti_uart.c=0D M hw/char/sifive_uart.c=0D M hw/dma/sifive_pdma.c=0D M hw/riscv/shakti_c.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211007' into staging=0D =0D Third RISC-V PR for QEMU 6.2=0D =0D - Add Zb[abcs] instruction support=0D - Remove RVB support=0D - Bug fix of setting mstatus_hs.[SD|FS] bits=0D - Mark some UART devices as 'input'=0D - QOMify PolarFire MMUART=0D - Fixes for sifive PDMA=0D - Mark shakti_c as not user creatable=0D =0D # gpg: Signature made Wed 06 Oct 2021 11:42:53 PM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211007: (26 commits)=0D hw/riscv: shakti_c: Mark as not user creatable=0D hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed=0D hw/dma: sifive_pdma: Fix Control.claim bit detection=0D hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART=0D hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container=0D hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition=0D= hw/char: sifive_uart: Register device in 'input' category=0D hw/char: shakti_uart: Register device in 'input' category=0D hw/char: ibex_uart: Register device in 'input' category=0D target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=3D1 in mark_fs= _dirty()=0D disas/riscv: Add Zb[abcs] instructions=0D target/riscv: Remove RVB (replaced by Zb[abcs])=0D target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh= =0D target/riscv: Add rev8 instruction, removing grev/grevi=0D target/riscv: Add a REQUIRE_32BIT macro=0D target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci=0D target/riscv: Reassign instructions to the Zbb-extension=0D target/riscv: Add instructions of the Zbc-extension=0D target/riscv: Reassign instructions to the Zbs-extension=0D target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 d= raft-B)=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/ca61fa4b803e...3c019339830a= =0D From MAILER-DAEMON Thu Oct 07 13:25:47 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYX9N-0007cB-S3 for mharc-qemu-commits@gnu.org; Thu, 07 Oct 2021 13:25:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYX9E-0007ZN-8t for qemu-commits@nongnu.org; Thu, 07 Oct 2021 13:25:37 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:44745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYX97-0003TX-PS for qemu-commits@nongnu.org; Thu, 07 Oct 2021 13:25:35 -0400 Received: from github.com (hubbernetes-node-695fbdd.ash1-iad.github.net [10.56.113.37]) by smtp.github.com (Postfix) with ESMTPA id 2832C900F90 for ; Thu, 7 Oct 2021 10:25:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633627529; bh=WvIpOGQobCsmZPpyYNzESgv/4E6oJT4uoG0r4uw9NwA=; h=Date:From:To:Subject:From; b=eSImxWR9ImbsPB/ZAF6RblOalcRlt/UXP05hbssy36O+WRB51iwPI6rSV8aAXu6nk GdTrW8A5U0CRutopoXQpXNoOVCG0oEwAplw1gB5LvL+vthWOUgUMtmLvMhCEF9P8t8 Fh41fIURS0EsMUMlQSdO6B6F6Ijunil6mR+pnKm4= Date: Thu, 07 Oct 2021 10:25:29 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c5b4ee: target/riscv: Introduce temporary in gen_add_uw() X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 17:25:38 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: c5b4ee5bb799685e1c5a4a30ab40013a984daded=0D https://github.com/qemu/qemu/commit/c5b4ee5bb799685e1c5a4a30ab40013= a984daded=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Introduce temporary in gen_add_uw()=0D =0D Following the recent changes in translate.c, gen_add_uw() causes=0D failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these=0D regressions by introducing a temporary.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu=0D Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e47fb6c1e96a4e50603c13b8408e0745a09cd867=0D https://github.com/qemu/qemu/commit/e47fb6c1e96a4e50603c13b8408e074= 5a09cd867=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: fix clzw implementation to operate on arg1=0D =0D The refactored gen_clzw() uses ret as its argument, instead of arg1.=0D Fix it.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu=0D Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 45d1749c1c32f7f44e02f267407cd6bca88fb84a=0D https://github.com/qemu/qemu/commit/45d1749c1c32f7f44e02f267407cd6b= ca88fb84a=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: clwz must ignore high bits (use shift-left & changed logi= c)=0D =0D Assume clzw being executed on a register that is not sign-extended, such=0D= as for the following sequence that uses (1ULL << 63) | 392 as the operand= =0D to clzw:=0D bseti a2, zero, 63=0D addi a2, a2, 392=0D clzw a3, a2=0D The correct result of clzw would be 23, but the current implementation=0D= returns -32 (as it performs a 64bit clz, which results in 0 leading zero=0D= bits, and then subtracts 32).=0D =0D Fix this by changing the implementation to:=0D 1. shift the original register up by 32=0D 2. performs a target-length (64bit) clz=0D 3. return 32 if no bits are set=0D =0D Marking this instruction as 'w-form' (i.e., setting ctx->w) would not=0D correctly model the behaviour, as the instruction should not perform=0D a zero-extensions on the input (after all, it is not a .uw instruction)=0D= and the result is always in the range 0..32 (so neither a sign-extension=0D= nor a zero-extension on the result will ever be needed). Consequently,=0D= we do not set ctx->w and mark the instruction as EXT_NONE.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: LIU Zhiwei=0D Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 878dd0e9ac18af657dcbdb598bb2eb1278606d3a=0D https://github.com/qemu/qemu/commit/878dd0e9ac18af657dcbdb598bb2eb1= 278606d3a=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties=0D =0D The bitmanipulation ISA extensions will be ratified as individual=0D small extension packages instead of a large B-extension. The first=0D new instructions through the door (these have completed public review)=0D= are Zb[abcs].=0D =0D This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for=0D these in target/riscv/cpu.[ch].=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: bb4dc158e084c3293b553c37f3ace99997aeff6f=0D https://github.com/qemu/qemu/commit/bb4dc158e084c3293b553c37f3ace99= 997aeff6f=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zba-extension=0D =0D The following instructions are part of Zba:=0D - add.uw (RV64 only)=0D - sh[123]add (RV32 and RV64)=0D - sh[123]add.uw (RV64-only)=0D - slli.uw (RV64-only)=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: dd98a74034a4ae6a80162f2db42e67260875eb5e=0D https://github.com/qemu/qemu/commit/dd98a74034a4ae6a80162f2db42e672= 60875eb5e=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove the W-form instructions from Zbs=0D =0D Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form=0D= instructions for Zbs (single-bit instructions). Remove them.=0D =0D Note that these instructions had already been removed for the 0.93=0D version of the draft-B extention and have not been present in the=0D binutils patches circulating in January 2021.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 628d8c88c14e6ee8eef0c6d3b7178dbfc7770f03=0D https://github.com/qemu/qemu/commit/628d8c88c14e6ee8eef0c6d3b7178db= fc7770f03=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 d= raft-B)=0D =0D The Zb[abcs] ratification package does not include the proposed=0D shift-one instructions. There currently is no clear plan to whether=0D these (or variants of them) will be ratified as Zbo (or a different=0D extension) or what the timeframe for such a decision could be.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: f36a4a89aad493990084a9b540ed511cb66701ce=0D https://github.com/qemu/qemu/commit/f36a4a89aad493990084a9b540ed511= cb66701ce=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zbs-extension=0D =0D The following instructions are part of Zbs:=0D - b{set,clr,ext,inv}=0D - b{set,clr,ext,inv}i=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fd4b81a304a5d50e719019d22eacca2d8ef4de69=0D https://github.com/qemu/qemu/commit/fd4b81a304a5d50e719019d22eacca2= d8ef4de69=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add instructions of the Zbc-extension=0D =0D The following instructions are part of Zbc:=0D - clmul=0D - clmulh=0D - clmulr=0D =0D Note that these instructions were already defined in the pre-0.93 and=0D the 0.93 draft-B proposals, but had not been omitted in the earlier=0D addition of draft-B to QEmu.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 16c38f36f5cb42bbfe7b9cd4bb29206a3ecab760=0D https://github.com/qemu/qemu/commit/16c38f36f5cb42bbfe7b9cd4bb29206= a3ecab760=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Reassign instructions to the Zbb-extension=0D =0D This reassigns the instructions that are part of Zbb into it, with the=0D= notable exceptions of the instructions (rev8, zext.w and orc.b) that=0D changed due to gorci, grevi and pack not being part of Zb[abcs].=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Acked-by: Bin Meng =0D Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: d7a4fcb03433edefd19b7db3c4d20ed750b5833b=0D https://github.com/qemu/qemu/commit/d7a4fcb03433edefd19b7db3c4d20ed= 750b5833b=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci=0D =0D The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a=0D orc.b instruction (equivalent to the orc.b pseudo-instruction built on=0D= gorci from pre-0.93 draft-B) is available, mainly targeting=0D string-processing workloads.=0D =0D This commit adds the new orc.b instruction and removed gorc/gorci.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 7e68e6c79b9de5c923e478ea6794a5143610b765=0D https://github.com/qemu/qemu/commit/7e68e6c79b9de5c923e478ea6794a51= 43610b765=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add a REQUIRE_32BIT macro=0D =0D With the changes to Zb[abcs], there's some encodings that are=0D different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,=0D we'll need a helper macro allowing us to select on RV32, as well.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a1095bdcb050f0a17afb3fcb8a36543fb58f4ea9=0D https://github.com/qemu/qemu/commit/a1095bdcb050f0a17afb3fcb8a36543= fb58f4ea9=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add rev8 instruction, removing grev/grevi=0D =0D The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a=0D rev8 instruction (equivalent to the rev8 pseudo-instruction built on=0D grevi from pre-0.93 draft-B) is available.=0D =0D This commit adds the new rev8 instruction and removes grev/grevi.=0D =0D Note that there is no W-form of this instruction (both a=0D sign-extending and zero-extending 32-bit version can easily be=0D synthesized by following rev8 with either a srai or srli instruction=0D on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are=0D different.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 06dfa8a5c5e79c2be7672b0a56e08c7f6d350148=0D https://github.com/qemu/qemu/commit/06dfa8a5c5e79c2be7672b0a56e08c7= f6d350148=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh= =0D =0D The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a=0D= zext.h instruction is provided (built on pack/packh from pre-0.93=0D draft-B) is available.=0D =0D This commit adds zext.h and removes the pack* instructions.=0D =0D Note that the encodings for zext.h are different between RV32 and=0D RV64, which is handled through REQUIRE_32BIT.=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 9916ea3c97f6cbd46d912ecc80dfe94baed5d288=0D https://github.com/qemu/qemu/commit/9916ea3c97f6cbd46d912ecc80dfe94= baed5d288=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/insn32.decode=0D =0D Log Message:=0D -----------=0D target/riscv: Remove RVB (replaced by Zb[abcs])=0D =0D With everything classified as Zb[abcs] and pre-0.93 draft-B=0D instructions that are not part of Zb[abcs] removed, we can remove the=0D remaining support code for RVB.=0D =0D Note that RVB has been retired for good and misa.B will neither mean=0D 'some' or 'all of' Zb*:=0D https://lists.riscv.org/g/tech-bitmanip/message/532=0D =0D Signed-off-by: Philipp Tomsich =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 02c1b569a15b4b06a3c69b6cb1713830a29cb01f=0D https://github.com/qemu/qemu/commit/02c1b569a15b4b06a3c69b6cb171383= 0a29cb01f=0D Author: Philipp Tomsich =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M disas/riscv.c=0D =0D Log Message:=0D -----------=0D disas/riscv: Add Zb[abcs] instructions=0D =0D With the addition of Zb[abcs], we also need to add disassembler=0D support for these new instructions.=0D =0D Signed-off-by: Philipp Tomsich =0D Acked-by: Alistair Francis =0D Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a88f0402391e9075df774affe5482d1286b9237e=0D https://github.com/qemu/qemu/commit/a88f0402391e9075df774affe5482d1= 286b9237e=0D Author: Frank Chang =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=3D1 in mark_fs= _dirty()=0D =0D When V=3D1, both vsstauts.FS and HS-level sstatus.FS are in effect.=0D Modifying the floating-point state when V=3D1 causes both fields to=0D be set to 3 (Dirty).=0D =0D However, it's possible that HS-level sstatus.FS is Clean and VS-level=0D vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=3D1.=0D= We can't early return for this case because we still need to set=0D sstatus.FS to Dirty according to spec.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Vincent Chen =0D Tested-by: Vincent Chen =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20210921020234.123448-1-frank.chang@sifive.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 34229c46a721b2acf3cc1c1af3324f7468852330=0D https://github.com/qemu/qemu/commit/34229c46a721b2acf3cc1c1af3324f7= 468852330=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/ibex_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: ibex_uart: Register device in 'input' category=0D =0D The category of ibex_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 5515ff162e8c20bfe907e21b2a3b9bed12a8ef67=0D https://github.com/qemu/qemu/commit/5515ff162e8c20bfe907e21b2a3b9be= d12a8ef67=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/shakti_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: shakti_uart: Register device in 'input' category=0D =0D The category of shakti_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 6a03349007f84e514e2e3def25c3f85400fdb47a=0D https://github.com/qemu/qemu/commit/6a03349007f84e514e2e3def25c3f85= 400fdb47a=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sifive_uart.c=0D =0D Log Message:=0D -----------=0D hw/char: sifive_uart: Register device in 'input' category=0D =0D The category of sifive_uart device is not set. Put it into the=0D 'input' category.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 284a66a8f6ffc8a720071b3f3cbc10cff0637337=0D https://github.com/qemu/qemu/commit/284a66a8f6ffc8a720071b3f3cbc10c= ff0637337=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition=0D= =0D The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the=0D size occupied by all the registers. However all registers are=0D 32-bit wide, and the MemoryRegionOps handlers are restricted to=0D 32-bit:=0D =0D static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D {=0D .read =3D mchp_pfsoc_mmuart_read,=0D .write =3D mchp_pfsoc_mmuart_write,=0D .impl =3D {=0D .min_access_size =3D 4,=0D .max_access_size =3D 4,=0D },=0D =0D Avoid being triskaidekaphobic, simplify by using the number of=0D registers.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Message-id: 20210925133407.1259392-2-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 24ce762df7d10175db1f91962d4fb1355b2645d2=0D https://github.com/qemu/qemu/commit/24ce762df7d10175db1f91962d4fb13= 55b2645d2=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container=0D =0D Our device have 2 different I/O regions:=0D - a 16550 UART mapped for 32-bit accesses=0D - 13 extra registers=0D =0D Instead of mapping each region on the main bus, introduce=0D a container, map the 2 devices regions on the container,=0D and map the container on the main bus.=0D =0D Before:=0D =0D (qemu) info mtree=0D ...=0D 0000000020100000-000000002010001f (prio 0, i/o): serial=0D 0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020102000-000000002010201f (prio 0, i/o): serial=0D 0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020104000-000000002010401f (prio 0, i/o): serial=0D 0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020106000-000000002010601f (prio 0, i/o): serial=0D 0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart=0D= =0D After:=0D =0D (qemu) info mtree=0D ...=0D 0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020100000-000000002010001f (prio 0, i/o): serial=0D 0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020102000-000000002010201f (prio 0, i/o): serial=0D 0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020104000-000000002010401f (prio 0, i/o): serial=0D 0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D 0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart=0D= 0000000020106000-000000002010601f (prio 0, i/o): serial=0D 0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.= regs=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Tested-by: Bin Meng =0D Message-id: 20210925133407.1259392-3-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 31ca70b5ff7c6ac600211f60e3ab024642fe5abb=0D https://github.com/qemu/qemu/commit/31ca70b5ff7c6ac600211f60e3ab024= 642fe5abb=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/char/mchp_pfsoc_mmuart.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D =0D Log Message:=0D -----------=0D hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART=0D =0D - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it=0D - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART=0D - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()=0D - Add DeviceReset() method=0D - Add vmstate structure for migration=0D - Register device in 'input' category=0D - Keep mchp_pfsoc_mmuart_create() behavior=0D =0D Note, serial_mm_init() calls qdev_set_legacy_instance_id().=0D This call is only needed for backwards-compatibility of incoming=0D migration data with old versions of QEMU which implemented migration=0D of devices with hand-rolled code. Since this device didn't previously=0D handle migration at all, then it doesn't need to set the legacy=0D instance ID.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Message-id: 20210925133407.1259392-4-f4bug@amsat.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5=0D https://github.com/qemu/qemu/commit/b7af62ae2ca4a5f36a36d98e37d59e9= 6fb3f8ef5=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/dma/sifive_pdma.c=0D =0D Log Message:=0D -----------=0D hw/dma: sifive_pdma: Fix Control.claim bit detection=0D =0D At present the codes detect whether the DMA channel is claimed by:=0D =0D claimed =3D !!s->chan[ch].control & CONTROL_CLAIM;=0D =0D As ! has higher precedence over & (bitwise and), this is essentially=0D =0D claimed =3D (!!s->chan[ch].control) & CONTROL_CLAIM;=0D =0D which is wrong, as any non-zero bit set in the control register will=0D produce a result of a claimed channel.=0D =0D Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Con= trol.claim is set")=0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 47b5fbf5a3f9c88936a0532ecb918f5e58ad348c=0D https://github.com/qemu/qemu/commit/47b5fbf5a3f9c88936a0532ecb918f5= e58ad348c=0D Author: Bin Meng =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/dma/sifive_pdma.c=0D =0D Log Message:=0D -----------=0D hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed=0D =0D If Control.run bit is set while not preserving the Control.claim=0D bit, the DMA transfer shall not be started.=0D =0D The following result is PDMA tested in U-Boot on Unleashed board:=0D =0D =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0=0D =3D> mw.l 0x3000000 0x1 <=3D Claim channel 0=0D =3D> mw.l 0x3000004 0x55000000 <=3D wsize =3D rsize =3D 5 (= 2^5 =3D 32 bytes)=0D =3D> mw.q 0x3000008 0x2 <=3D NextBytes =3D 2=0D =3D> mw.q 0x3000010 0x84000000 <=3D NextDestination =3D 0x8= 4000000=0D =3D> mw.q 0x3000018 0x84001000 <=3D NextSource =3D 0x840010= 00=0D =3D> mw.l 0x84000000 0x87654321 <=3D Fill test data to dst=0D= =3D> mw.l 0x84001000 0x12345678 <=3D Fill test data to src=0D= =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents=0D 84000000: 87654321 !Ce.=0D 84001000: 12345678 xV4.=0D =3D> md.l 0x3000000 8 <=3D Dump PDMA status=0D 03000000: 00000001 55000000 00000002 00000000 .......U........=0D 03000010: 84000000 00000000 84001000 00000000 ................=0D =3D> mw.l 0x3000000 0x2 <=3D Set channel 0 run bit o= nly=0D =3D> md.l 0x3000000 8 <=3D Dump PDMA status=0D 03000000: 00000000 55000000 00000002 00000000 .......U........=0D 03000010: 84000000 00000000 84001000 00000000 ................=0D =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents=0D 84000000: 87654321 !Ce.=0D 84001000: 12345678 xV4.=0D =0D Signed-off-by: Bin Meng =0D Acked-by: Alistair Francis =0D Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07=0D https://github.com/qemu/qemu/commit/9ae6ecd848dcd1b32003526ab65a0d4= c644dfb07=0D Author: Alistair Francis =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/shakti_c.c=0D =0D Log Message:=0D -----------=0D hw/riscv: shakti_c: Mark as not user creatable=0D =0D Mark the shakti_c machine as not user creatable.=0D =0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639=0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D =0D =0D Commit: 3c019339830affe7974b738e0c2b71bd28778ef0=0D https://github.com/qemu/qemu/commit/3c019339830affe7974b738e0c2b71b= d28778ef0=0D Author: Richard Henderson =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M disas/riscv.c=0D M hw/char/ibex_uart.c=0D M hw/char/mchp_pfsoc_mmuart.c=0D M hw/char/shakti_uart.c=0D M hw/char/sifive_uart.c=0D M hw/dma/sifive_pdma.c=0D M hw/riscv/shakti_c.c=0D M include/hw/char/mchp_pfsoc_mmuart.h=0D M target/riscv/bitmanip_helper.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/helper.h=0D M target/riscv/insn32.decode=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211007' into staging=0D =0D Third RISC-V PR for QEMU 6.2=0D =0D - Add Zb[abcs] instruction support=0D - Remove RVB support=0D - Bug fix of setting mstatus_hs.[SD|FS] bits=0D - Mark some UART devices as 'input'=0D - QOMify PolarFire MMUART=0D - Fixes for sifive PDMA=0D - Mark shakti_c as not user creatable=0D =0D # gpg: Signature made Wed 06 Oct 2021 11:42:53 PM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211007: (26 commits)=0D hw/riscv: shakti_c: Mark as not user creatable=0D hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed=0D hw/dma: sifive_pdma: Fix Control.claim bit detection=0D hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART=0D hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container=0D hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition=0D= hw/char: sifive_uart: Register device in 'input' category=0D hw/char: shakti_uart: Register device in 'input' category=0D hw/char: ibex_uart: Register device in 'input' category=0D target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=3D1 in mark_fs= _dirty()=0D disas/riscv: Add Zb[abcs] instructions=0D target/riscv: Remove RVB (replaced by Zb[abcs])=0D target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh= =0D target/riscv: Add rev8 instruction, removing grev/grevi=0D target/riscv: Add a REQUIRE_32BIT macro=0D target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci=0D target/riscv: Reassign instructions to the Zbb-extension=0D target/riscv: Add instructions of the Zbc-extension=0D target/riscv: Reassign instructions to the Zbs-extension=0D target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 d= raft-B)=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/ca61fa4b803e...3c019339830a= =0D From MAILER-DAEMON Thu Oct 07 13:32:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYXGD-0004Sd-Ge for mharc-qemu-commits@gnu.org; Thu, 07 Oct 2021 13:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXGC-0004Mm-95 for qemu-commits@nongnu.org; Thu, 07 Oct 2021 13:32:48 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:59195) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXG8-0003Cz-E5 for qemu-commits@nongnu.org; Thu, 07 Oct 2021 13:32:47 -0400 Received: from github.com (hubbernetes-node-a4b35b2.ac4-iad.github.net [10.52.201.26]) by smtp.github.com (Postfix) with ESMTPA id 65A80600767 for ; Thu, 7 Oct 2021 10:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633627963; bh=E5BY4W0RVSPmhxdamsNKeCsjiUvQeysXM4kyqLpZqbM=; h=Date:From:To:Subject:From; b=k0jpmhz/8HvF4zjDcBcFZ9K8WYfEOdkrZBoOzYOa5790KG4SirunV0mGQSgn4zKEk 3ez0qXyzJB9VNrwKiArLlMbTcOk3YesDDtTOMYLtUyINocsFfqomzi9PXunIOjJMTQ Bij/qkwNPHi24aphB2jpP2SWHa2w2mjjJwXbb2Dw= Date: Thu, 07 Oct 2021 10:32:43 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 8fc898: block/backup: avoid integer overflow of `max-workers` X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 17:32:48 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 8fc898ce0b3e7fea8c7c2a8d8977f2a9b77ecebf https://github.com/qemu/qemu/commit/8fc898ce0b3e7fea8c7c2a8d8977f2a9b77ecebf Author: Stefano Garzarella Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M block/backup.c Log Message: ----------- block/backup: avoid integer overflow of `max-workers` QAPI generates `struct BackupPerf` where `max-workers` value is stored in an `int64_t` variable. But block_copy_async(), and the underlying code, uses an `int` parameter. At the end that variable is used to initialize `max_busy_tasks` in block/aio_task.c causing the following assertion failure if a value greater than INT_MAX(2147483647) is used: ../block/aio_task.c:63: aio_task_pool_wait_one: Assertion `pool->busy_tasks > 0' failed. Let's check that `max-workers` doesn't exceed INT_MAX and print an error in that case. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2009310 Signed-off-by: Stefano Garzarella Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211005161157.282396-2-sgarzare@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a9515df4d66da34cbc2938e4c1f46015fc74ff93 https://github.com/qemu/qemu/commit/a9515df4d66da34cbc2938e4c1f46015fc74ff93 Author: Stefano Garzarella Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M block/aio_task.c Log Message: ----------- block/aio_task: assert `max_busy_tasks` is greater than 0 All code in block/aio_task.c expects `max_busy_tasks` to always be greater than 0. Assert this condition during the AioTaskPool creation where `max_busy_tasks` is set. Signed-off-by: Stefano Garzarella Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211005161157.282396-3-sgarzare@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: d431131439f228626aedc6d211c73b2a3616d5e1 https://github.com/qemu/qemu/commit/d431131439f228626aedc6d211c73b2a3616d5e1 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Context changes in job_completed_txn_abort() Finalizing the job may cause its AioContext to change. This is noted by job_exit(), which points at job_txn_apply() to take this fact into account. However, job_completed() does not necessarily invoke job_txn_apply() (through job_completed_txn_success()), but potentially also job_completed_txn_abort(). The latter stores the context in a local variable, and so always acquires the same context at its end that it has released in the beginning -- which may be a different context from the one that job_exit() releases at its end. If it is different, qemu aborts ("qemu_mutex_unlock_impl: Operation not permitted"). Drop the local @outer_ctx variable from job_completed_txn_abort(), and instead re-acquire the actual job's context at the end of the function, so job_exit() will release the same. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-2-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a3810da5cff152a2a1b2d25a8b8080f640e491b6 https://github.com/qemu/qemu/commit/a3810da5cff152a2a1b2d25a8b8080f640e491b6 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Keep s->synced on error An error does not take us out of the READY phase, which is what s->synced signifies. It does of course mean that source and target are no longer in sync, but that is what s->actively_sync is for -- s->synced never meant that source and target are in sync, only that they were at some point (and at that point we transitioned into the READY phase). The tangible problem is that we transition to READY once we are in sync and s->synced is false. By resetting s->synced here, we will transition from READY to READY once the error is resolved (if the job keeps running), and that transition is not allowed. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-3-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 447162242803bdc38bb198312e1d0a0675948424 https://github.com/qemu/qemu/commit/447162242803bdc38bb198312e1d0a0675948424 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Drop s->synced As of HEAD^, there is no meaning to s->synced other than whether the job is READY or not. job_is_ready() gives us that information, too. Suggested-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-4-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 1d4a43e9464f8945bd8aa2ed9d95f184b011befe https://github.com/qemu/qemu/commit/1d4a43e9464f8945bd8aa2ed9d95f184b011befe Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Force-cancel jobs in a failed transaction When a transaction is aborted, no result matters, and so all jobs within should be force-cancelled. Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-5-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 4cfb3f05627ad82af473e7f7ae113c3884cd04e3 https://github.com/qemu/qemu/commit/4cfb3f05627ad82af473e7f7ae113c3884cd04e3 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/replication.c M blockdev.c M include/qemu/job.h M job.c M tests/qemu-iotests/109.out M tests/qemu-iotests/tests/qsd-jobs.out M tests/unit/test-blockjob.c Log Message: ----------- job: @force parameter for job_cancel_sync() Callers should be able to specify whether they want job_cancel_sync() to force-cancel the job or not. In fact, almost all invocations do not care about consistency of the result and just want the job to terminate as soon as possible, so they should pass force=true. The replication block driver is the exception, specifically the active commit job it runs. As for job_cancel_sync_all(), all callers want it to force-cancel all jobs, because that is the point of it: To cancel all remaining jobs as quickly as possible (generally on process termination). So make it invoke job_cancel_sync() with force=true. This changes some iotest outputs, because quitting qemu while a mirror job is active will now lead to it being cancelled instead of completed, which is what we want. (Cancelling a READY mirror job with force=false may take an indefinite amount of time, which we do not want when quitting. If users want consistent results, they must have all jobs be done before they quit qemu.) Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-6-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 73895f3838cd7fdaf185cf1dbc47be58844a966f https://github.com/qemu/qemu/commit/73895f3838cd7fdaf185cf1dbc47be58844a966f Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/backup.c M block/mirror.c M include/qemu/job.h M job.c Log Message: ----------- jobs: Give Job.force_cancel more meaning We largely have two cancel modes for jobs: First, there is actual cancelling. The job is terminated as soon as possible, without trying to reach a consistent result. Second, we have mirror in the READY state. Technically, the job is not really cancelled, but it just is a different completion mode. The job can still run for an indefinite amount of time while it tries to reach a consistent result. We want to be able to clearly distinguish which cancel mode a job is in (when it has been cancelled). We can use Job.force_cancel for this, but right now it only reflects cancel requests from the user with force=true, but clearly, jobs that do not even distinguish between force=false and force=true are effectively always force-cancelled. So this patch has Job.force_cancel signify whether the job will terminate as soon as possible (force_cancel=true) or whether it will effectively remain running despite being "cancelled" (force_cancel=false). To this end, we let jobs that provide JobDriver.cancel() tell the generic job code whether they will terminate as soon as possible or not, and for jobs that do not provide that method we assume they will. Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-7-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 401dd096ef9d19956977b371362107448575ef40 https://github.com/qemu/qemu/commit/401dd096ef9d19956977b371362107448575ef40 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Do not soft-cancel after a job is done The only job that supports a soft cancel mode is the mirror job, and in such a case it resets its .cancelled field before it leaves its .run() function, so it does not really count as cancelled. However, it is possible to cancel the job after .run() returns and before job_exit() (which is run in the main loop) is executed. Then, .cancelled would still be true and the job would count as cancelled. This does not seem to be in the interest of the mirror job, so adjust job_cancel_async() to not set .cancelled in such a case, and job_cancel() to not invoke job_completed_txn_abort(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-8-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 08b83bff2a77e082d0b29680a40f0aaf9996bd16 https://github.com/qemu/qemu/commit/08b83bff2a77e082d0b29680a40f0aaf9996bd16 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c M include/qemu/job.h M job.c Log Message: ----------- job: Add job_cancel_requested() Most callers of job_is_cancelled() actually want to know whether the job is on its way to immediate termination. For example, we refuse to pause jobs that are cancelled; but this only makes sense for jobs that are really actually cancelled. A mirror job that is cancelled during READY with force=false should absolutely be allowed to pause. This "cancellation" (which is actually a kind of completion) may take an indefinite amount of time, and so should behave like any job during normal operation. For example, with on-target-error=stop, the job should stop on write errors. (In contrast, force-cancelled jobs should not get write errors, as they should just terminate and not do further I/O.) Therefore, redefine job_is_cancelled() to only return true for jobs that are force-cancelled (which as of HEAD^ means any job that interprets the cancellation request as a request for immediate termination), and add job_cancel_requested() as the general variant, which returns true for any jobs which have been requested to be cancelled, whether it be immediately or after an arbitrarily long completion phase. Finally, here is a justification for how different job_is_cancelled() invocations are treated by this patch: - block/mirror.c (mirror_run()): - The first invocation is a while loop that should loop until the job has been cancelled or scheduled for completion. What kind of cancel does not matter, only the fact that the job is supposed to end. - The second invocation wants to know whether the job has been soft-cancelled. Calling job_cancel_requested() is a bit too broad, but if the job were force-cancelled, we should leave the main loop as soon as possible anyway, so this should not matter here. - The last two invocations already check force_cancel, so they should continue to use job_is_cancelled(). - block/backup.c, block/commit.c, block/stream.c, anything in tests/: These jobs know only force-cancel, so there is no difference between job_is_cancelled() and job_cancel_requested(). We can continue using job_is_cancelled(). - job.c: - job_pause_point(), job_yield(), job_sleep_ns(): Only force-cancelled jobs should be prevented from being paused. Continue using job_is_cancelled(). - job_update_rc(), job_finalize_single(), job_finish_sync(): These functions are all called after the job has left its main loop. The mirror job (the only job that can be soft-cancelled) will clear .cancelled before leaving the main loop if it has been soft-cancelled. Therefore, these functions will observe .cancelled to be true only if the job has been force-cancelled. We can continue to use job_is_cancelled(). (Furthermore, conceptually, a soft-cancelled mirror job should not report to have been cancelled. It should report completion (see also the block-job-cancel QAPI documentation). Therefore, it makes sense for these functions not to distinguish between a soft-cancelled mirror job and a job that has completed as normal.) - job_completed_txn_abort(): All jobs other than @job have been force-cancelled. job_is_cancelled() must be true for them. Regarding @job itself: job_completed_txn_abort() is mostly called when the job's return value is not 0. A soft-cancelled mirror has a return value of 0, and so will not end up here then. However, job_cancel() invokes job_completed_txn_abort() if the job has been deferred to the main loop, which is mostly the case for completed jobs (which skip the assertion), but not for sure. To be safe, use job_cancel_requested() in this assertion. - job_complete(): This is function eventually invoked by the user (through qmp_block_job_complete() or qmp_job_complete(), or job_complete_sync(), which comes from qemu-img). The intention here is to prevent a user from invoking job-complete after the job has been cancelled. This should also apply to soft cancelling: After a mirror job has been soft-cancelled, the user should not be able to decide otherwise and have it complete as normal (i.e. pivoting to the target). - job_cancel(): Both functions are equivalent (see comment there), but we want to use job_is_cancelled(), because this shows that we call job_completed_txn_abort() only for force-cancelled jobs. (As explained for job_update_rc(), soft-cancelled jobs should be treated as if they have completed as normal.) Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-9-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 20ad4d204accb27346b05b046ee8225c6725ef49 https://github.com/qemu/qemu/commit/20ad4d204accb27346b05b046ee8225c6725ef49 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Use job_is_cancelled() mirror_drained_poll() returns true whenever the job is cancelled, because "we [can] be sure that it won't issue more requests". However, this is only true for force-cancelled jobs, so use job_is_cancelled(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-10-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 4feeec7e23b4151c962cb1b9f1a0e403803dfaee https://github.com/qemu/qemu/commit/4feeec7e23b4151c962cb1b9f1a0e403803dfaee Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Check job_is_cancelled() earlier We must check whether the job is force-cancelled early in our main loop, most importantly before any `continue` statement. For example, we used to have `continue`s before our current checking location that are triggered by `mirror_flush()` failing. So, if `mirror_flush()` kept failing, force-cancelling the job would not terminate it. Jobs can be cancelled while they yield, and once they are (force-cancelled), they should not generate new I/O requests. Therefore, we should put the check after the last yield before mirror_iteration() is invoked. Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-11-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 9b230ef93e406dc46b82eebde996ef6a08b929d6 https://github.com/qemu/qemu/commit/9b230ef93e406dc46b82eebde996ef6a08b929d6 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Stop active mirroring after force-cancel Once the mirror job is force-cancelled (job_is_cancelled() is true), we should not generate new I/O requests. This applies to active mirroring, too, so stop it once the job is cancelled. (We must still forward all I/O requests to the source, though, of course, but those are not really I/O requests generated by the job, so this is fine.) Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-12-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a640fa0e381caf572266c6c07d026dd07cf66a49 https://github.com/qemu/qemu/commit/a640fa0e381caf572266c6c07d026dd07cf66a49 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c M job.c Log Message: ----------- mirror: Do not clear .cancelled Clearing .cancelled before leaving the main loop when the job has been soft-cancelled is no longer necessary since job_is_cancelled() only returns true for jobs that have been force-cancelled. Therefore, this only makes a differences in places that call job_cancel_requested(). In block/mirror.c, this is done only before .cancelled was cleared. In job.c, there are two callers: - job_completed_txn_abort() asserts that .cancelled is true, so keeping it true will not affect this place. - job_complete() refuses to let a job complete that has .cancelled set. It is correct to refuse to let the user invoke job-complete on mirror jobs that have already been soft-cancelled. With this change, there are no places that reset .cancelled to false and so we can be sure that .force_cancel can only be true if .cancelled is true as well. Assert this in job_is_cancelled(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-13-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 2451f72527d8760566a499b7513e17aaceb0f131 https://github.com/qemu/qemu/commit/2451f72527d8760566a499b7513e17aaceb0f131 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: A tests/qemu-iotests/tests/mirror-ready-cancel-error A tests/qemu-iotests/tests/mirror-ready-cancel-error.out Log Message: ----------- iotests: Add mirror-ready-cancel-error test Test what happens when there is an I/O error after a mirror job in the READY phase has been cancelled. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Tested-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-14-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 14f12119aa675e9e28207a48b0728a2daa5b88d6 https://github.com/qemu/qemu/commit/14f12119aa675e9e28207a48b0728a2daa5b88d6 Author: Richard Henderson Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/aio_task.c M block/backup.c M block/mirror.c M block/replication.c M blockdev.c M include/qemu/job.h M job.c M tests/qemu-iotests/109.out A tests/qemu-iotests/tests/mirror-ready-cancel-error A tests/qemu-iotests/tests/mirror-ready-cancel-error.out M tests/qemu-iotests/tests/qsd-jobs.out M tests/unit/test-blockjob.c Log Message: ----------- Merge remote-tracking branch 'remotes/vsementsov/tags/pull-jobs-2021-10-07-v2' into staging mirror: Handle errors after READY cancel v2: add small fix by Stefano, Hanna's series fixed # gpg: Signature made Thu 07 Oct 2021 08:25:07 AM PDT # gpg: using RSA key 8B9C26CDB2FD147C880E86A1561F24C1F19F79FB # gpg: Good signature from "Vladimir Sementsov-Ogievskiy " [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8B9C 26CD B2FD 147C 880E 86A1 561F 24C1 F19F 79FB * remotes/vsementsov/tags/pull-jobs-2021-10-07-v2: iotests: Add mirror-ready-cancel-error test mirror: Do not clear .cancelled mirror: Stop active mirroring after force-cancel mirror: Check job_is_cancelled() earlier mirror: Use job_is_cancelled() job: Add job_cancel_requested() job: Do not soft-cancel after a job is done jobs: Give Job.force_cancel more meaning job: @force parameter for job_cancel_sync() job: Force-cancel jobs in a failed transaction mirror: Drop s->synced mirror: Keep s->synced on error job: Context changes in job_completed_txn_abort() block/aio_task: assert `max_busy_tasks` is greater than 0 block/backup: avoid integer overflow of `max-workers` Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/3c019339830a...14f12119aa67 From MAILER-DAEMON Thu Oct 07 15:05:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYYhs-000370-4V for mharc-qemu-commits@gnu.org; Thu, 07 Oct 2021 15:05:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYYhk-00036D-8M for qemu-commits@nongnu.org; Thu, 07 Oct 2021 15:05:20 -0400 Received: from out-20.smtp.github.com ([192.30.252.203]:37355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYYhg-0005OU-W6 for qemu-commits@nongnu.org; Thu, 07 Oct 2021 15:05:19 -0400 Received: from github.com (hubbernetes-node-be7ccc8.va3-iad.github.net [10.48.204.60]) by smtp.github.com (Postfix) with ESMTPA id 13AE8E0525 for ; Thu, 7 Oct 2021 12:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633633516; bh=M7NRl5ceP1MlzxJ8xIWLHvJEGe/fb3gHcCeFq/9gjpc=; h=Date:From:To:Subject:From; b=oKKPEcevDh/0Qy/Ad6hErBCpMaOnc0oNJFrAkBpBwbxMhs42zWHs57AHH7qEf2Pxe LFhoGUoDRbTH310NXFdFX5Iw0r7+3NhAXhFBq38A2JO5ODGQ+dScQfk+A488WxAUZW 4iFDjG7KI4C0FPqBf2DfJD2t2cmMfY/jU0VpC2kI= Date: Thu, 07 Oct 2021 12:05:16 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.203; envelope-from=noreply@github.com; helo=out-20.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 8fc898: block/backup: avoid integer overflow of `max-workers` X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 19:05:20 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: 8fc898ce0b3e7fea8c7c2a8d8977f2a9b77ecebf https://github.com/qemu/qemu/commit/8fc898ce0b3e7fea8c7c2a8d8977f2a9b77ecebf Author: Stefano Garzarella Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M block/backup.c Log Message: ----------- block/backup: avoid integer overflow of `max-workers` QAPI generates `struct BackupPerf` where `max-workers` value is stored in an `int64_t` variable. But block_copy_async(), and the underlying code, uses an `int` parameter. At the end that variable is used to initialize `max_busy_tasks` in block/aio_task.c causing the following assertion failure if a value greater than INT_MAX(2147483647) is used: ../block/aio_task.c:63: aio_task_pool_wait_one: Assertion `pool->busy_tasks > 0' failed. Let's check that `max-workers` doesn't exceed INT_MAX and print an error in that case. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2009310 Signed-off-by: Stefano Garzarella Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211005161157.282396-2-sgarzare@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a9515df4d66da34cbc2938e4c1f46015fc74ff93 https://github.com/qemu/qemu/commit/a9515df4d66da34cbc2938e4c1f46015fc74ff93 Author: Stefano Garzarella Date: 2021-10-05 (Tue, 05 Oct 2021) Changed paths: M block/aio_task.c Log Message: ----------- block/aio_task: assert `max_busy_tasks` is greater than 0 All code in block/aio_task.c expects `max_busy_tasks` to always be greater than 0. Assert this condition during the AioTaskPool creation where `max_busy_tasks` is set. Signed-off-by: Stefano Garzarella Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211005161157.282396-3-sgarzare@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: d431131439f228626aedc6d211c73b2a3616d5e1 https://github.com/qemu/qemu/commit/d431131439f228626aedc6d211c73b2a3616d5e1 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Context changes in job_completed_txn_abort() Finalizing the job may cause its AioContext to change. This is noted by job_exit(), which points at job_txn_apply() to take this fact into account. However, job_completed() does not necessarily invoke job_txn_apply() (through job_completed_txn_success()), but potentially also job_completed_txn_abort(). The latter stores the context in a local variable, and so always acquires the same context at its end that it has released in the beginning -- which may be a different context from the one that job_exit() releases at its end. If it is different, qemu aborts ("qemu_mutex_unlock_impl: Operation not permitted"). Drop the local @outer_ctx variable from job_completed_txn_abort(), and instead re-acquire the actual job's context at the end of the function, so job_exit() will release the same. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-2-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a3810da5cff152a2a1b2d25a8b8080f640e491b6 https://github.com/qemu/qemu/commit/a3810da5cff152a2a1b2d25a8b8080f640e491b6 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Keep s->synced on error An error does not take us out of the READY phase, which is what s->synced signifies. It does of course mean that source and target are no longer in sync, but that is what s->actively_sync is for -- s->synced never meant that source and target are in sync, only that they were at some point (and at that point we transitioned into the READY phase). The tangible problem is that we transition to READY once we are in sync and s->synced is false. By resetting s->synced here, we will transition from READY to READY once the error is resolved (if the job keeps running), and that transition is not allowed. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-3-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 447162242803bdc38bb198312e1d0a0675948424 https://github.com/qemu/qemu/commit/447162242803bdc38bb198312e1d0a0675948424 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Drop s->synced As of HEAD^, there is no meaning to s->synced other than whether the job is READY or not. job_is_ready() gives us that information, too. Suggested-by: Vladimir Sementsov-Ogievskiy Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-4-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 1d4a43e9464f8945bd8aa2ed9d95f184b011befe https://github.com/qemu/qemu/commit/1d4a43e9464f8945bd8aa2ed9d95f184b011befe Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Force-cancel jobs in a failed transaction When a transaction is aborted, no result matters, and so all jobs within should be force-cancelled. Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-5-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 4cfb3f05627ad82af473e7f7ae113c3884cd04e3 https://github.com/qemu/qemu/commit/4cfb3f05627ad82af473e7f7ae113c3884cd04e3 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/replication.c M blockdev.c M include/qemu/job.h M job.c M tests/qemu-iotests/109.out M tests/qemu-iotests/tests/qsd-jobs.out M tests/unit/test-blockjob.c Log Message: ----------- job: @force parameter for job_cancel_sync() Callers should be able to specify whether they want job_cancel_sync() to force-cancel the job or not. In fact, almost all invocations do not care about consistency of the result and just want the job to terminate as soon as possible, so they should pass force=true. The replication block driver is the exception, specifically the active commit job it runs. As for job_cancel_sync_all(), all callers want it to force-cancel all jobs, because that is the point of it: To cancel all remaining jobs as quickly as possible (generally on process termination). So make it invoke job_cancel_sync() with force=true. This changes some iotest outputs, because quitting qemu while a mirror job is active will now lead to it being cancelled instead of completed, which is what we want. (Cancelling a READY mirror job with force=false may take an indefinite amount of time, which we do not want when quitting. If users want consistent results, they must have all jobs be done before they quit qemu.) Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-6-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 73895f3838cd7fdaf185cf1dbc47be58844a966f https://github.com/qemu/qemu/commit/73895f3838cd7fdaf185cf1dbc47be58844a966f Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/backup.c M block/mirror.c M include/qemu/job.h M job.c Log Message: ----------- jobs: Give Job.force_cancel more meaning We largely have two cancel modes for jobs: First, there is actual cancelling. The job is terminated as soon as possible, without trying to reach a consistent result. Second, we have mirror in the READY state. Technically, the job is not really cancelled, but it just is a different completion mode. The job can still run for an indefinite amount of time while it tries to reach a consistent result. We want to be able to clearly distinguish which cancel mode a job is in (when it has been cancelled). We can use Job.force_cancel for this, but right now it only reflects cancel requests from the user with force=true, but clearly, jobs that do not even distinguish between force=false and force=true are effectively always force-cancelled. So this patch has Job.force_cancel signify whether the job will terminate as soon as possible (force_cancel=true) or whether it will effectively remain running despite being "cancelled" (force_cancel=false). To this end, we let jobs that provide JobDriver.cancel() tell the generic job code whether they will terminate as soon as possible or not, and for jobs that do not provide that method we assume they will. Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Kevin Wolf Message-Id: <20211006151940.214590-7-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 401dd096ef9d19956977b371362107448575ef40 https://github.com/qemu/qemu/commit/401dd096ef9d19956977b371362107448575ef40 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M job.c Log Message: ----------- job: Do not soft-cancel after a job is done The only job that supports a soft cancel mode is the mirror job, and in such a case it resets its .cancelled field before it leaves its .run() function, so it does not really count as cancelled. However, it is possible to cancel the job after .run() returns and before job_exit() (which is run in the main loop) is executed. Then, .cancelled would still be true and the job would count as cancelled. This does not seem to be in the interest of the mirror job, so adjust job_cancel_async() to not set .cancelled in such a case, and job_cancel() to not invoke job_completed_txn_abort(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-8-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 08b83bff2a77e082d0b29680a40f0aaf9996bd16 https://github.com/qemu/qemu/commit/08b83bff2a77e082d0b29680a40f0aaf9996bd16 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c M include/qemu/job.h M job.c Log Message: ----------- job: Add job_cancel_requested() Most callers of job_is_cancelled() actually want to know whether the job is on its way to immediate termination. For example, we refuse to pause jobs that are cancelled; but this only makes sense for jobs that are really actually cancelled. A mirror job that is cancelled during READY with force=false should absolutely be allowed to pause. This "cancellation" (which is actually a kind of completion) may take an indefinite amount of time, and so should behave like any job during normal operation. For example, with on-target-error=stop, the job should stop on write errors. (In contrast, force-cancelled jobs should not get write errors, as they should just terminate and not do further I/O.) Therefore, redefine job_is_cancelled() to only return true for jobs that are force-cancelled (which as of HEAD^ means any job that interprets the cancellation request as a request for immediate termination), and add job_cancel_requested() as the general variant, which returns true for any jobs which have been requested to be cancelled, whether it be immediately or after an arbitrarily long completion phase. Finally, here is a justification for how different job_is_cancelled() invocations are treated by this patch: - block/mirror.c (mirror_run()): - The first invocation is a while loop that should loop until the job has been cancelled or scheduled for completion. What kind of cancel does not matter, only the fact that the job is supposed to end. - The second invocation wants to know whether the job has been soft-cancelled. Calling job_cancel_requested() is a bit too broad, but if the job were force-cancelled, we should leave the main loop as soon as possible anyway, so this should not matter here. - The last two invocations already check force_cancel, so they should continue to use job_is_cancelled(). - block/backup.c, block/commit.c, block/stream.c, anything in tests/: These jobs know only force-cancel, so there is no difference between job_is_cancelled() and job_cancel_requested(). We can continue using job_is_cancelled(). - job.c: - job_pause_point(), job_yield(), job_sleep_ns(): Only force-cancelled jobs should be prevented from being paused. Continue using job_is_cancelled(). - job_update_rc(), job_finalize_single(), job_finish_sync(): These functions are all called after the job has left its main loop. The mirror job (the only job that can be soft-cancelled) will clear .cancelled before leaving the main loop if it has been soft-cancelled. Therefore, these functions will observe .cancelled to be true only if the job has been force-cancelled. We can continue to use job_is_cancelled(). (Furthermore, conceptually, a soft-cancelled mirror job should not report to have been cancelled. It should report completion (see also the block-job-cancel QAPI documentation). Therefore, it makes sense for these functions not to distinguish between a soft-cancelled mirror job and a job that has completed as normal.) - job_completed_txn_abort(): All jobs other than @job have been force-cancelled. job_is_cancelled() must be true for them. Regarding @job itself: job_completed_txn_abort() is mostly called when the job's return value is not 0. A soft-cancelled mirror has a return value of 0, and so will not end up here then. However, job_cancel() invokes job_completed_txn_abort() if the job has been deferred to the main loop, which is mostly the case for completed jobs (which skip the assertion), but not for sure. To be safe, use job_cancel_requested() in this assertion. - job_complete(): This is function eventually invoked by the user (through qmp_block_job_complete() or qmp_job_complete(), or job_complete_sync(), which comes from qemu-img). The intention here is to prevent a user from invoking job-complete after the job has been cancelled. This should also apply to soft cancelling: After a mirror job has been soft-cancelled, the user should not be able to decide otherwise and have it complete as normal (i.e. pivoting to the target). - job_cancel(): Both functions are equivalent (see comment there), but we want to use job_is_cancelled(), because this shows that we call job_completed_txn_abort() only for force-cancelled jobs. (As explained for job_update_rc(), soft-cancelled jobs should be treated as if they have completed as normal.) Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-9-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 20ad4d204accb27346b05b046ee8225c6725ef49 https://github.com/qemu/qemu/commit/20ad4d204accb27346b05b046ee8225c6725ef49 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Use job_is_cancelled() mirror_drained_poll() returns true whenever the job is cancelled, because "we [can] be sure that it won't issue more requests". However, this is only true for force-cancelled jobs, so use job_is_cancelled(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-10-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 4feeec7e23b4151c962cb1b9f1a0e403803dfaee https://github.com/qemu/qemu/commit/4feeec7e23b4151c962cb1b9f1a0e403803dfaee Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Check job_is_cancelled() earlier We must check whether the job is force-cancelled early in our main loop, most importantly before any `continue` statement. For example, we used to have `continue`s before our current checking location that are triggered by `mirror_flush()` failing. So, if `mirror_flush()` kept failing, force-cancelling the job would not terminate it. Jobs can be cancelled while they yield, and once they are (force-cancelled), they should not generate new I/O requests. Therefore, we should put the check after the last yield before mirror_iteration() is invoked. Buglink: https://gitlab.com/qemu-project/qemu/-/issues/462 Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-11-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 9b230ef93e406dc46b82eebde996ef6a08b929d6 https://github.com/qemu/qemu/commit/9b230ef93e406dc46b82eebde996ef6a08b929d6 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c Log Message: ----------- mirror: Stop active mirroring after force-cancel Once the mirror job is force-cancelled (job_is_cancelled() is true), we should not generate new I/O requests. This applies to active mirroring, too, so stop it once the job is cancelled. (We must still forward all I/O requests to the source, though, of course, but those are not really I/O requests generated by the job, so this is fine.) Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-12-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: a640fa0e381caf572266c6c07d026dd07cf66a49 https://github.com/qemu/qemu/commit/a640fa0e381caf572266c6c07d026dd07cf66a49 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/mirror.c M job.c Log Message: ----------- mirror: Do not clear .cancelled Clearing .cancelled before leaving the main loop when the job has been soft-cancelled is no longer necessary since job_is_cancelled() only returns true for jobs that have been force-cancelled. Therefore, this only makes a differences in places that call job_cancel_requested(). In block/mirror.c, this is done only before .cancelled was cleared. In job.c, there are two callers: - job_completed_txn_abort() asserts that .cancelled is true, so keeping it true will not affect this place. - job_complete() refuses to let a job complete that has .cancelled set. It is correct to refuse to let the user invoke job-complete on mirror jobs that have already been soft-cancelled. With this change, there are no places that reset .cancelled to false and so we can be sure that .force_cancel can only be true if .cancelled is true as well. Assert this in job_is_cancelled(). Signed-off-by: Hanna Reitz Reviewed-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-13-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 2451f72527d8760566a499b7513e17aaceb0f131 https://github.com/qemu/qemu/commit/2451f72527d8760566a499b7513e17aaceb0f131 Author: Hanna Reitz Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: A tests/qemu-iotests/tests/mirror-ready-cancel-error A tests/qemu-iotests/tests/mirror-ready-cancel-error.out Log Message: ----------- iotests: Add mirror-ready-cancel-error test Test what happens when there is an I/O error after a mirror job in the READY phase has been cancelled. Signed-off-by: Hanna Reitz Reviewed-by: Vladimir Sementsov-Ogievskiy Tested-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006151940.214590-14-hreitz@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy Commit: 14f12119aa675e9e28207a48b0728a2daa5b88d6 https://github.com/qemu/qemu/commit/14f12119aa675e9e28207a48b0728a2daa5b88d6 Author: Richard Henderson Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M block/aio_task.c M block/backup.c M block/mirror.c M block/replication.c M blockdev.c M include/qemu/job.h M job.c M tests/qemu-iotests/109.out A tests/qemu-iotests/tests/mirror-ready-cancel-error A tests/qemu-iotests/tests/mirror-ready-cancel-error.out M tests/qemu-iotests/tests/qsd-jobs.out M tests/unit/test-blockjob.c Log Message: ----------- Merge remote-tracking branch 'remotes/vsementsov/tags/pull-jobs-2021-10-07-v2' into staging mirror: Handle errors after READY cancel v2: add small fix by Stefano, Hanna's series fixed # gpg: Signature made Thu 07 Oct 2021 08:25:07 AM PDT # gpg: using RSA key 8B9C26CDB2FD147C880E86A1561F24C1F19F79FB # gpg: Good signature from "Vladimir Sementsov-Ogievskiy " [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8B9C 26CD B2FD 147C 880E 86A1 561F 24C1 F19F 79FB * remotes/vsementsov/tags/pull-jobs-2021-10-07-v2: iotests: Add mirror-ready-cancel-error test mirror: Do not clear .cancelled mirror: Stop active mirroring after force-cancel mirror: Check job_is_cancelled() earlier mirror: Use job_is_cancelled() job: Add job_cancel_requested() job: Do not soft-cancel after a job is done jobs: Give Job.force_cancel more meaning job: @force parameter for job_cancel_sync() job: Force-cancel jobs in a failed transaction mirror: Drop s->synced mirror: Keep s->synced on error job: Context changes in job_completed_txn_abort() block/aio_task: assert `max_busy_tasks` is greater than 0 block/backup: avoid integer overflow of `max-workers` Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/3c019339830a...14f12119aa67 From MAILER-DAEMON Fri Oct 08 08:03:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYobF-0006HQ-0j for mharc-qemu-commits@gnu.org; Fri, 08 Oct 2021 08:03:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYobC-0006FO-24 for qemu-commits@nongnu.org; Fri, 08 Oct 2021 08:03:39 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:52097 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYob8-00057f-Vn for qemu-commits@nongnu.org; Fri, 08 Oct 2021 08:03:37 -0400 Received: from github.com (hubbernetes-node-338fd2c.ash1-iad.github.net [10.56.121.25]) by smtp.github.com (Postfix) with ESMTPA id 4E93C5E0104 for ; Fri, 8 Oct 2021 05:03:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633694614; bh=stjdk2EFMUndZQ8omnG+kgNBozqROj5rfpE6mNZ2jhA=; h=Date:From:To:Subject:From; b=oEe2bhqN27FCdoq9v9yIsu7ePWhHl8tIhB1RzbGJWcPPm0iKT11PEih0mP6p8rorY v5xxBSYLvx5vQZvge14M9Kwwc4cxjyQyAG0BEcryhFi+aj5KEW8n/Ks/W7JXf14R89 bi/SErPuSJnKcKvoWM9Nm1hVcrJcALvzafhS7ClE= Date: Fri, 08 Oct 2021 05:03:34 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7437b1: macfb: handle errors that occur during realize X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Oct 2021 12:03:39 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 7437b13eacfd05ed6817c2f05c4712ed618544e1=0D https://github.com/qemu/qemu/commit/7437b13eacfd05ed6817c2f05c4712e= d618544e1=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: handle errors that occur during realize=0D =0D Make sure any errors that occur within the macfb realize chain are detect= ed=0D and handled correctly to prevent crashes and to ensure that error message= s are=0D reported back to the user.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-2-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c047862acd502c305fbdc66a4a3fd717c04fa6d2=0D https://github.com/qemu/qemu/commit/c047862acd502c305fbdc66a4a3fd71= 7c04fa6d2=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: update macfb.c to use the Error API best practices=0D =0D As per the current Error API best practices, change macfb_commom_realize(= ) to return=0D a boolean indicating success to reduce errp boiler-plate handling code. N= ote that=0D memory_region_init_ram_nomigrate() is also updated to use &error_abort to= indicate=0D a non-recoverable error, matching the behaviour recommended after similar= =0D discussions on memory API failures for the recent nubus changes.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-3-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 906c2323f1edf41b1851e7e36231023ee930aa3c=0D https://github.com/qemu/qemu/commit/906c2323f1edf41b1851e7e36231023= ee930aa3c=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix invalid object reference in macfb_common_realize()=0D =0D During realize memory_region_init_ram_nomigrate() is used to initialise t= he RAM=0D memory region used for the framebuffer but the owner object reference is=0D= incorrect since MacFbState is a typedef and not a QOM type.=0D =0D Change the memory region owner to be the corresponding DeviceState to fix= the=0D issue and prevent random crashes during macfb_common_realize().=0D =0D Signed-off-by: Mark Cave-Ayland =0D Fixes: 8ac919a0654 ("hw/m68k: add Nubus macfb video card")=0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-4-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 14d0ddfce781374b7ce40062c0afc2ed00419267=0D https://github.com/qemu/qemu/commit/14d0ddfce781374b7ce40062c0afc2e= d00419267=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix overflow of color_palette array=0D =0D The palette_current index counter has a maximum size of 256 * 3 to cover = a full=0D color palette of 256 RGB entries. Linux assumes that the palette_current = index=0D wraps back around to zero after writing 256 RGB entries so ensure that=0D= palette_current is reset at this point to prevent data corruption within=0D= MacfbState.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-5-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3b10b5673c902981129d1817fcc235e467648200=0D https://github.com/qemu/qemu/commit/3b10b5673c902981129d1817fcc235e= 467648200=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: use memory_region_init_ram() in macfb_common_realize() for the f= ramebuffer=0D =0D Currently macfb_common_realize() defines the framebuffer RAM memory regio= n as=0D being non-migrateable but then immediately registers it for migration. Re= place=0D memory_region_init_ram_nomigrate() with memory_region_init_ram() which is= clearer=0D and does exactly the same thing.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-6-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4ec27073fd0e5a82a87b1122dfdca7a820cb1561=0D https://github.com/qemu/qemu/commit/4ec27073fd0e5a82a87b1122dfdca7a= 820cb1561=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D =0D Log Message:=0D -----------=0D macfb: add trace events for reading and writing the control registers=0D= =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-7-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e6108b96363bda0704ca69e5dfdb4b07dc589336=0D https://github.com/qemu/qemu/commit/e6108b96363bda0704ca69e5dfdb4b0= 7dc589336=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: implement mode sense to allow display type to be detected=0D =0D The MacOS toolbox ROM uses the monitor sense to detect the display type a= nd then=0D offer a fixed set of resolutions and colour depths accordingly. Implement= the=0D monitor sense using information found in Apple Technical Note HW26: "Maci= ntosh=0D Quadra Built-In Video" along with some local experiments.=0D =0D Since the default configuration is 640 x 480 with 8-bit colour then hardc= ode=0D the sense register to return MACFB_DISPLAY_VGA for now.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-8-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4317c518618adcd5d41637c849be17e94cecf003=0D https://github.com/qemu/qemu/commit/4317c518618adcd5d41637c849be17e= 94cecf003=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add qdev property to specify display type=0D =0D Since the available resolutions and colour depths are determined by the a= ttached=0D display type, add a qdev property to allow the display type to be specifi= ed.=0D =0D The main resolutions of interest are high resolution 1152x870 with 8-bit = colour=0D and SVGA resolution up to 800x600 with 24-bit colour so update the q800 m= achine=0D to allow high resolution mode if specified and otherwise fall back to SVG= A.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-9-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: df8abbbadf743bef6be5543b26f51231285b8923=0D https://github.com/qemu/qemu/commit/df8abbbadf743bef6be5543b26f5123= 1285b8923=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add common monitor modes supported by the MacOS toolbox ROM=0D =0D The monitor modes table is found by experimenting with the Monitors Contr= ol=0D Panel in MacOS and analysing the reads/writes. From this it can be found = that=0D the mode is controlled by writes to the DAFB_MODE_CTRL1 and DAFB_MODE_CTR= L2=0D registers.=0D =0D Implement the first block of DAFB registers as a register array including= the=0D existing sense register, the newly discovered control registers above, an= d also=0D the DAFB_MODE_VADDR1 and DAFB_MODE_VADDR2 registers which are used by Net= BSD to=0D determine the current video mode.=0D =0D These experiments also show that the offset of the start of video RAM and= the=0D stride can change depending upon the monitor mode, so update macfb_draw_g= raphic()=0D and both the BI_MAC_VADDR and BI_MAC_VROW bootinfo for the q800 machine=0D= accordingly.=0D =0D Finally update macfb_common_realize() so that only the resolution and dep= th=0D supported by the display type can be specified on the command line, and a= dd an=0D error hint showing the list of supported resolutions and depths if the us= er tries=0D to specify an invalid display mode.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-10-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 57eeaf44ce6964e6e86275318f5fc35610c1dc68=0D https://github.com/qemu/qemu/commit/57eeaf44ce6964e6e86275318f5fc35= 610c1dc68=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix up 1-bit pixel encoding=0D =0D The MacOS driver expects the RGB values for the pixel to be in entries 0 = and 1=0D of the colour palette.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-11-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 432d59c56ef8a8eaefd847a40a01439e32317bff=0D https://github.com/qemu/qemu/commit/432d59c56ef8a8eaefd847a40a01439= e32317bff=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix 24-bit RGB pixel encoding=0D =0D According to Apple Technical Note HW26: "Macintosh Quadra Built-In Video"= the=0D in-built framebuffer encodes each 24-bit pixel into 4 bytes. Adjust the 2= 4-bit=0D RGB pixel encoding accordingly which agrees with the encoding expected by= MacOS=0D when changing into 24-bit colour mode.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-12-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c7a2f7ba0c736a119d7b530693de0e1b691cdd5a=0D https://github.com/qemu/qemu/commit/c7a2f7ba0c736a119d7b530693de0e1= b691cdd5a=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add vertical blank interrupt=0D =0D The MacOS driver expects a 60.15Hz vertical blank interrupt to be generat= ed by=0D the framebuffer which in turn schedules the mouse driver via the Vertical= Retrace=0D Manager.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-13-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: efd0c37edc8efe7dccc2356f4a07f33581bc9e67=0D https://github.com/qemu/qemu/commit/efd0c37edc8efe7dccc2356f4a07f33= 581bc9e67=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/m68k/q800.c=0D =0D Log Message:=0D -----------=0D q800: wire macfb IRQ to separate video interrupt on VIA2=0D =0D Whilst the in-built Quadra 800 framebuffer exists within the Nubus addres= s=0D space for slot 9, it has its own dedicated interrupt on VIA2. Force the=0D= macfb device to occupy slot 9 in the q800 machine and wire its IRQ to the= =0D separate video interrupt since this is what is expected by the MacOS=0D interrupt handler.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-14-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 15a0578903dc0d612e63f542d159fe1f3fb8a17a=0D https://github.com/qemu/qemu/commit/15a0578903dc0d612e63f542d159fe1= f3fb8a17a=0D Author: Richard Henderson =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier-m68k/tags/m68k-next-pull-r= equest' into staging=0D =0D Pull request q800 20211008=0D =0D macfb: fixes for booting MacOS=0D =0D # gpg: Signature made Fri 08 Oct 2021 04:44:44 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier-m68k/tags/m68k-next-pull-request:=0D q800: wire macfb IRQ to separate video interrupt on VIA2=0D macfb: add vertical blank interrupt=0D macfb: fix 24-bit RGB pixel encoding=0D macfb: fix up 1-bit pixel encoding=0D macfb: add common monitor modes supported by the MacOS toolbox ROM=0D macfb: add qdev property to specify display type=0D macfb: implement mode sense to allow display type to be detected=0D macfb: add trace events for reading and writing the control registers=0D= macfb: use memory_region_init_ram() in macfb_common_realize() for the f= ramebuffer=0D macfb: fix overflow of color_palette array=0D macfb: fix invalid object reference in macfb_common_realize()=0D macfb: update macfb.c to use the Error API best practices=0D macfb: handle errors that occur during realize=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/14f12119aa67...15a0578903dc= =0D From MAILER-DAEMON Fri Oct 08 09:29:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYpvu-0005s1-5w for mharc-qemu-commits@gnu.org; Fri, 08 Oct 2021 09:29:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYpvt-0005rk-3Z for qemu-commits@nongnu.org; Fri, 08 Oct 2021 09:29:05 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:42627) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYpvq-0002l8-46 for qemu-commits@nongnu.org; Fri, 08 Oct 2021 09:29:04 -0400 Received: from github.com (hubbernetes-node-60d898d.ash1-iad.github.net [10.56.113.35]) by smtp.github.com (Postfix) with ESMTPA id 46BF8900FBA for ; Fri, 8 Oct 2021 06:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633699741; bh=CUHzI/d0TB2ZD/IqMAOEr2G6hdBLuvTYDnqwAuiMZpg=; h=Date:From:To:Subject:From; b=GKkAqTOujJbeK9ap3OWyVpmF5IRK0cAcBhWs2135eQ5FVMfqdYuY2GqTDTinR64dH Fb5Dkp/u7gMR0vMCOSfmXF8q7avKV+fwPQJ062OOU9knDx4espyo0YCMlg3wZ12+MD +PAJ0eB/uBWNqpYb4u/U5YNwG0GoF0mEuAtBddbY= Date: Fri, 08 Oct 2021 06:29:01 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7437b1: macfb: handle errors that occur during realize X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Oct 2021 13:29:05 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 7437b13eacfd05ed6817c2f05c4712ed618544e1=0D https://github.com/qemu/qemu/commit/7437b13eacfd05ed6817c2f05c4712e= d618544e1=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: handle errors that occur during realize=0D =0D Make sure any errors that occur within the macfb realize chain are detect= ed=0D and handled correctly to prevent crashes and to ensure that error message= s are=0D reported back to the user.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-2-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c047862acd502c305fbdc66a4a3fd717c04fa6d2=0D https://github.com/qemu/qemu/commit/c047862acd502c305fbdc66a4a3fd71= 7c04fa6d2=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: update macfb.c to use the Error API best practices=0D =0D As per the current Error API best practices, change macfb_commom_realize(= ) to return=0D a boolean indicating success to reduce errp boiler-plate handling code. N= ote that=0D memory_region_init_ram_nomigrate() is also updated to use &error_abort to= indicate=0D a non-recoverable error, matching the behaviour recommended after similar= =0D discussions on memory API failures for the recent nubus changes.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-3-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 906c2323f1edf41b1851e7e36231023ee930aa3c=0D https://github.com/qemu/qemu/commit/906c2323f1edf41b1851e7e36231023= ee930aa3c=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix invalid object reference in macfb_common_realize()=0D =0D During realize memory_region_init_ram_nomigrate() is used to initialise t= he RAM=0D memory region used for the framebuffer but the owner object reference is=0D= incorrect since MacFbState is a typedef and not a QOM type.=0D =0D Change the memory region owner to be the corresponding DeviceState to fix= the=0D issue and prevent random crashes during macfb_common_realize().=0D =0D Signed-off-by: Mark Cave-Ayland =0D Fixes: 8ac919a0654 ("hw/m68k: add Nubus macfb video card")=0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-4-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 14d0ddfce781374b7ce40062c0afc2ed00419267=0D https://github.com/qemu/qemu/commit/14d0ddfce781374b7ce40062c0afc2e= d00419267=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix overflow of color_palette array=0D =0D The palette_current index counter has a maximum size of 256 * 3 to cover = a full=0D color palette of 256 RGB entries. Linux assumes that the palette_current = index=0D wraps back around to zero after writing 256 RGB entries so ensure that=0D= palette_current is reset at this point to prevent data corruption within=0D= MacfbState.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-5-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3b10b5673c902981129d1817fcc235e467648200=0D https://github.com/qemu/qemu/commit/3b10b5673c902981129d1817fcc235e= 467648200=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: use memory_region_init_ram() in macfb_common_realize() for the f= ramebuffer=0D =0D Currently macfb_common_realize() defines the framebuffer RAM memory regio= n as=0D being non-migrateable but then immediately registers it for migration. Re= place=0D memory_region_init_ram_nomigrate() with memory_region_init_ram() which is= clearer=0D and does exactly the same thing.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-6-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4ec27073fd0e5a82a87b1122dfdca7a820cb1561=0D https://github.com/qemu/qemu/commit/4ec27073fd0e5a82a87b1122dfdca7a= 820cb1561=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D =0D Log Message:=0D -----------=0D macfb: add trace events for reading and writing the control registers=0D= =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-7-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e6108b96363bda0704ca69e5dfdb4b07dc589336=0D https://github.com/qemu/qemu/commit/e6108b96363bda0704ca69e5dfdb4b0= 7dc589336=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: implement mode sense to allow display type to be detected=0D =0D The MacOS toolbox ROM uses the monitor sense to detect the display type a= nd then=0D offer a fixed set of resolutions and colour depths accordingly. Implement= the=0D monitor sense using information found in Apple Technical Note HW26: "Maci= ntosh=0D Quadra Built-In Video" along with some local experiments.=0D =0D Since the default configuration is 640 x 480 with 8-bit colour then hardc= ode=0D the sense register to return MACFB_DISPLAY_VGA for now.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-8-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 4317c518618adcd5d41637c849be17e94cecf003=0D https://github.com/qemu/qemu/commit/4317c518618adcd5d41637c849be17e= 94cecf003=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add qdev property to specify display type=0D =0D Since the available resolutions and colour depths are determined by the a= ttached=0D display type, add a qdev property to allow the display type to be specifi= ed.=0D =0D The main resolutions of interest are high resolution 1152x870 with 8-bit = colour=0D and SVGA resolution up to 800x600 with 24-bit colour so update the q800 m= achine=0D to allow high resolution mode if specified and otherwise fall back to SVG= A.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-9-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: df8abbbadf743bef6be5543b26f51231285b8923=0D https://github.com/qemu/qemu/commit/df8abbbadf743bef6be5543b26f5123= 1285b8923=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add common monitor modes supported by the MacOS toolbox ROM=0D =0D The monitor modes table is found by experimenting with the Monitors Contr= ol=0D Panel in MacOS and analysing the reads/writes. From this it can be found = that=0D the mode is controlled by writes to the DAFB_MODE_CTRL1 and DAFB_MODE_CTR= L2=0D registers.=0D =0D Implement the first block of DAFB registers as a register array including= the=0D existing sense register, the newly discovered control registers above, an= d also=0D the DAFB_MODE_VADDR1 and DAFB_MODE_VADDR2 registers which are used by Net= BSD to=0D determine the current video mode.=0D =0D These experiments also show that the offset of the start of video RAM and= the=0D stride can change depending upon the monitor mode, so update macfb_draw_g= raphic()=0D and both the BI_MAC_VADDR and BI_MAC_VROW bootinfo for the q800 machine=0D= accordingly.=0D =0D Finally update macfb_common_realize() so that only the resolution and dep= th=0D supported by the display type can be specified on the command line, and a= dd an=0D error hint showing the list of supported resolutions and depths if the us= er tries=0D to specify an invalid display mode.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-10-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 57eeaf44ce6964e6e86275318f5fc35610c1dc68=0D https://github.com/qemu/qemu/commit/57eeaf44ce6964e6e86275318f5fc35= 610c1dc68=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix up 1-bit pixel encoding=0D =0D The MacOS driver expects the RGB values for the pixel to be in entries 0 = and 1=0D of the colour palette.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-11-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 432d59c56ef8a8eaefd847a40a01439e32317bff=0D https://github.com/qemu/qemu/commit/432d59c56ef8a8eaefd847a40a01439= e32317bff=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D =0D Log Message:=0D -----------=0D macfb: fix 24-bit RGB pixel encoding=0D =0D According to Apple Technical Note HW26: "Macintosh Quadra Built-In Video"= the=0D in-built framebuffer encodes each 24-bit pixel into 4 bytes. Adjust the 2= 4-bit=0D RGB pixel encoding accordingly which agrees with the encoding expected by= MacOS=0D when changing into 24-bit colour mode.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-12-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c7a2f7ba0c736a119d7b530693de0e1b691cdd5a=0D https://github.com/qemu/qemu/commit/c7a2f7ba0c736a119d7b530693de0e1= b691cdd5a=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D macfb: add vertical blank interrupt=0D =0D The MacOS driver expects a 60.15Hz vertical blank interrupt to be generat= ed by=0D the framebuffer which in turn schedules the mouse driver via the Vertical= Retrace=0D Manager.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-13-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: efd0c37edc8efe7dccc2356f4a07f33581bc9e67=0D https://github.com/qemu/qemu/commit/efd0c37edc8efe7dccc2356f4a07f33= 581bc9e67=0D Author: Mark Cave-Ayland =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/m68k/q800.c=0D =0D Log Message:=0D -----------=0D q800: wire macfb IRQ to separate video interrupt on VIA2=0D =0D Whilst the in-built Quadra 800 framebuffer exists within the Nubus addres= s=0D space for slot 9, it has its own dedicated interrupt on VIA2. Force the=0D= macfb device to occupy slot 9 in the q800 machine and wire its IRQ to the= =0D separate video interrupt since this is what is expected by the MacOS=0D interrupt handler.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Message-Id: <20211007221253.29024-14-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 15a0578903dc0d612e63f542d159fe1f3fb8a17a=0D https://github.com/qemu/qemu/commit/15a0578903dc0d612e63f542d159fe1= f3fb8a17a=0D Author: Richard Henderson =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M hw/display/macfb.c=0D M hw/display/trace-events=0D M hw/m68k/q800.c=0D M include/hw/display/macfb.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier-m68k/tags/m68k-next-pull-r= equest' into staging=0D =0D Pull request q800 20211008=0D =0D macfb: fixes for booting MacOS=0D =0D # gpg: Signature made Fri 08 Oct 2021 04:44:44 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier-m68k/tags/m68k-next-pull-request:=0D q800: wire macfb IRQ to separate video interrupt on VIA2=0D macfb: add vertical blank interrupt=0D macfb: fix 24-bit RGB pixel encoding=0D macfb: fix up 1-bit pixel encoding=0D macfb: add common monitor modes supported by the MacOS toolbox ROM=0D macfb: add qdev property to specify display type=0D macfb: implement mode sense to allow display type to be detected=0D macfb: add trace events for reading and writing the control registers=0D= macfb: use memory_region_init_ram() in macfb_common_realize() for the f= ramebuffer=0D macfb: fix overflow of color_palette array=0D macfb: fix invalid object reference in macfb_common_realize()=0D macfb: update macfb.c to use the Error API best practices=0D macfb: handle errors that occur during realize=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/14f12119aa67...15a0578903dc= =0D From MAILER-DAEMON Fri Oct 08 09:38:50 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mYq5K-0005yX-1z for mharc-qemu-commits@gnu.org; Fri, 08 Oct 2021 09:38:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYq5E-0005wG-U2 for qemu-commits@nongnu.org; Fri, 08 Oct 2021 09:38:46 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:58447 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYq5C-00087Z-Aa for qemu-commits@nongnu.org; Fri, 08 Oct 2021 09:38:44 -0400 Received: from github.com (hubbernetes-node-c0d1613.va3-iad.github.net [10.48.205.47]) by smtp.github.com (Postfix) with ESMTPA id 48D6E5C0849 for ; Fri, 8 Oct 2021 06:38:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633700321; bh=pP119VTAjH9KKM3WFGRtvjpdo8kn/Dju9MGl04KHqBo=; h=Date:From:To:Subject:From; b=HzvwzUARnKPHK1ozu06T9f15kEOZTNLKiefCy+53CsMsSyYqopkAArv1UU1p1i/zu MRVNGmZIuBiVwW+OYtC1wYSf+lJLWLq0u8CGGPZXkusiB3RmEbAxwd7UPwE/raPNHy PZ6fz5+GkzlFfq69aCOFc3nek3uji5st51tkuq3U= Date: Fri, 08 Oct 2021 06:38:41 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 52012b: configure: don't override the selected host test c... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Oct 2021 13:38:48 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 52012b0809cfb5e7be7ed8434b519c3a2e85c25f=0D https://github.com/qemu/qemu/commit/52012b0809cfb5e7be7ed8434b519c3= a2e85c25f=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: don't override the selected host test compiler if defined=0D= =0D There are not many cases you would want to do this but one is if you=0D want to use a test friendly compiler like gcc instead of a system=0D compiler like clang. Either way we should honour the users choice if=0D they have made it.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-2-alex.bennee@linaro.org>=0D =0D =0D Commit: 4e5a2fc0b2d5e6b31035e41edac7467716874a57=0D https://github.com/qemu/qemu/commit/4e5a2fc0b2d5e6b31035e41edac7467= 716874a57=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/sha1.c=0D =0D Log Message:=0D -----------=0D tests/tcg/sha1: remove endian include=0D =0D This doesn't exist in BSD world and doesn't seem to be needed by=0D either.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-3-alex.bennee@linaro.org>=0D =0D =0D Commit: 99bc9f19b3ccfc7ca74a503c679fca629a115d41=0D https://github.com/qemu/qemu/commit/99bc9f19b3ccfc7ca74a503c679fca6= 29a115d41=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D tests/tcg: move some multiarch files and make conditional=0D =0D We had some messy code to filter out stuff we can't build. Lets junk=0D that and simplify the logic by pushing some stuff into subdirs. In=0D particular we move:=0D =0D float_helpers into libs - not a standalone test=0D linux-test into linux - so we only build on Linux hosts=0D =0D This allows for at least some of the tests to be nominally usable=0D by *BSD user builds.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-4-alex.bennee@linaro.org>=0D =0D =0D Commit: ffa3dd5159b4e878218b28af59976e91740e6a5f=0D https://github.com/qemu/qemu/commit/ffa3dd5159b4e878218b28af59976e9= 1740e6a5f=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/container-cross.yml=0D M tests/docker/Makefile.include=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D =0D Log Message:=0D -----------=0D tests/docker: promote debian-riscv64-cross to a full image=0D =0D To be able to cross build QEMU itself we need to include a few more=0D libraries. These are only available in Debian's unstable ports repo=0D for now so we need to base the riscv64 image on sid with the the=0D minimal libs needed to build QEMU (glib/pixman).=0D =0D The result works but is not as clean as using build-dep to bring in=0D more dependencies. However sid is by definition a shifting pile of=0D sand and by keeping the list of libs minimal we reduce the chance of=0D having an image we can't build. It's good enough for a basic cross=0D build testing of TCG.=0D =0D Cc: "Daniel P. Berrang=C3=A9" =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-2-richard.henderson@linaro.org>=0D [AJB: tweak allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-5-alex.bennee@linaro.org>=0D =0D =0D Commit: cb64ff0bb63cd2812e37ef49c2831ca1b70107bc=0D https://github.com/qemu/qemu/commit/cb64ff0bb63cd2812e37ef49c2831ca= 1b70107bc=0D Author: Richard Henderson =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/crossbuilds.yml=0D =0D Log Message:=0D -----------=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-3-richard.henderson@linaro.org>=0D [AJB: add allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20210917162332.3511179-6-alex.bennee@linaro.org>=0D =0D =0D Commit: 2c8d6e5c6aea0ef993c93aa929aee0b19f569d33=0D https://github.com/qemu/qemu/commit/2c8d6e5c6aea0ef993c93aa929aee0b= 19f569d33=0D Author: Thomas Huth =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M .travis.yml=0D =0D Log Message:=0D -----------=0D travis.yml: Remove the "Release tarball" job=0D =0D This is a leftover from the days when we were using Travis excessively,=0D= but since x86 jobs are not really usable there anymore, this job has=0D likely never been used since many months. Let's simply remove it now.=0D =0D Signed-off-by: Thomas Huth =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210917094826.466047-1-thuth@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-8-alex.bennee@linaro.org>=0D =0D =0D Commit: cbd7a203a9e2fb35b80984b798a681cda2af8310=0D https://github.com/qemu/qemu/commit/cbd7a203a9e2fb35b80984b798a681c= da2af8310=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/static_checks.yml=0D =0D Log Message:=0D -----------=0D gitlab: skip the check-patch job on the upstream repo=0D =0D The check-patch job is intended to be used by contributors or=0D subsystem maintainers to see if there are style mistakes. The=0D false positive rate is too high to be used in a gating scenario=0D so should not run it on the upstream repo ever.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-2-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-9-alex.bennee@linaro.org>=0D =0D =0D Commit: 74372eadeb41d1ffb7616260ba3bd5371dc80114=0D https://github.com/qemu/qemu/commit/74372eadeb41d1ffb7616260ba3bd53= 71dc80114=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D =0D Log Message:=0D -----------=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D =0D A typo meant the substitution would not work, and the placeholder in the=0D= target file didn't even exist.=0D =0D The result was that tests were never run on the FreeBSD and macOS jobs,=0D= only a basic build.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Willian Rampazzo =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-3-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-10-alex.bennee@linaro.org>=0D =0D =0D Commit: 8fb6dbd927c82b57fee5ddf38108cfa58246fdcb=0D https://github.com/qemu/qemu/commit/8fb6dbd927c82b57fee5ddf38108cfa= 58246fdcb=0D Author: Lukas J=C3=BCnger =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M plugins/qemu-plugins.symbols=0D =0D Log Message:=0D -----------=0D plugins/: Add missing functions to symbol list=0D =0D Some functions of the plugin API were missing in=0D the symbol list. However, they are all used by=0D the contributed example plugins. QEMU fails to=0D load the plugin if the function symbol is not=0D exported.=0D =0D Signed-off-by: Lukas J=C3=BCnger =0D Message-Id: <20210905140939.638928-2-lukas.junger@greensocs.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-11-alex.bennee@linaro.org>=0D =0D =0D Commit: 1d43009f88e8c9f88b6e58e66e091610543f65fc=0D https://github.com/qemu/qemu/commit/1d43009f88e8c9f88b6e58e66e09161= 0543f65fc=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/plugin-gen.c=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D =0D Coverity doesn't know enough about how we have arranged our plugin TCG=0D= ops to know we will always have incremented insn_idx before injecting=0D the callback. Let us assert it for the benefit of Coverity and protect=0D= ourselves from accidentally breaking the assumption and triggering=0D harder to grok errors deeper in the code if we attempt a negative=0D indexed array lookup.=0D =0D However to get to this point we re-factor the code and remove the=0D second hand instruction boundary detection in favour of scanning the=0D full set of ops and using the existing INDEX_op_insn_start to cleanly=0D detect when the instruction has started. As we no longer need the=0D plugin specific list of ops we delete that.=0D =0D My initial benchmarks shows no discernible impact of dropping the=0D plugin specific ops list.=0D =0D Fixes: Coverity 1459509=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Richard Henderson =0D Cc: Peter Maydell =0D Message-Id: <20210917162332.3511179-12-alex.bennee@linaro.org>=0D =0D =0D Commit: 2859c323deacff8d667860ab97c0f6456a2b9192=0D https://github.com/qemu/qemu/commit/2859c323deacff8d667860ab97c0f64= 56a2b9192=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D =0D Log Message:=0D -----------=0D .github: move repo lockdown to the v2 configuration=0D =0D I was getting prompted by GitHub for new permissions but it turns out=0D per https://github.com/dessant/repo-lockdown/issues/6:=0D =0D Repo Lockdown has been rewritten for GitHub Actions, offering new=0D features and better control over your automation presets. The legacy=0D= GitHub App has been deprecated, and the public instance of the app=0D has been shut down.=0D =0D So this is what I've done. As the issues tab is disabled I've removed=0D the handling for issues from the new version.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20211004154308.2114870-1-alex.bennee@linaro.org>=0D =0D =0D Commit: 755c4aefd86f8b8eda1eb37f20024765c70ebbcb=0D https://github.com/qemu/qemu/commit/755c4aefd86f8b8eda1eb37f2002476= 5c70ebbcb=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D =0D Log Message:=0D -----------=0D tests/docker: add a debian-native image and make available=0D =0D This image is intended for building whatever the native versions of=0D QEMU are for the host architecture. This will hopefully be an aid for=0D 3rd parties who want to be able to build QEMU themselves without=0D redoing all the dependencies themselves.=0D =0D We disable the registry because we currently don't have multi-arch=0D support there.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Anders Roxell =0D Acked-by: Willian Rampazzo =0D Message-Id: <20210922151528.2192966-1-alex.bennee@linaro.org>=0D =0D =0D Commit: 3a76e8a42d86830e7d771a323b0c7a4a5734fedb=0D https://github.com/qemu/qemu/commit/3a76e8a42d86830e7d771a323b0c7a4= a5734fedb=0D Author: Richard Henderson =0D Date: 2021-10-08 (Fri, 08 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D M .gitlab-ci.d/container-cross.yml=0D M .gitlab-ci.d/crossbuilds.yml=0D M .gitlab-ci.d/static_checks.yml=0D M .travis.yml=0D M accel/tcg/plugin-gen.c=0D M configure=0D M include/tcg/tcg.h=0D M plugins/qemu-plugins.symbols=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/multiarch/sha1.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-081021-= 1' into staging=0D =0D Some testing and plugin updates:=0D =0D - don't override the test compiler when specified=0D - split some multiarch tests by guest OS=0D - add riscv64 docker image and cross-compile tests=0D - drop release tarball test from Travis=0D - skip check-patch on master repo=0D - fix passing of TEST_TARGETS to cirrus=0D - fix missing symbols in plugins=0D - refactor plugin instruction boundary detection=0D - update github repo lockdown=0D - add a debian-native test image for multi-arch builds=0D =0D # gpg: Signature made Fri 08 Oct 2021 05:00:58 AM PDT=0D # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2= A44=0D # gpg: Good signature from "Alex Benn=C3=A9e (Master Work Key) " [full]=0D =0D * remotes/stsquad/tags/pull-for-6.2-081021-1:=0D tests/docker: add a debian-native image and make available=0D .github: move repo lockdown to the v2 configuration=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D plugins/: Add missing functions to symbol list=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D gitlab: skip the check-patch job on the upstream repo=0D travis.yml: Remove the "Release tarball" job=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D tests/docker: promote debian-riscv64-cross to a full image=0D tests/tcg: move some multiarch files and make conditional=0D tests/tcg/sha1: remove endian include=0D configure: don't override the selected host test compiler if defined=0D= =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/15a0578903dc...3a76e8a42d86= =0D From MAILER-DAEMON Mon Oct 11 11:16:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mZx2m-0003Ab-0l for mharc-qemu-commits@gnu.org; Mon, 11 Oct 2021 11:16:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZx2k-00038W-IH for qemu-commits@nongnu.org; Mon, 11 Oct 2021 11:16:46 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:47079 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZx2i-0006pW-4L for qemu-commits@nongnu.org; Mon, 11 Oct 2021 11:16:46 -0400 Received: from github.com (hubbernetes-node-5c7a69b.ac4-iad.github.net [10.52.207.80]) by smtp.github.com (Postfix) with ESMTPA id 7007456089E for ; Mon, 11 Oct 2021 08:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633965402; bh=gCII4Md6bNXpoa6Flsno8q0q4u8DMxYJvBQpIoMR34o=; h=Date:From:To:Subject:From; b=HrUwkmYTHeCHtGVBlyR0ZrdHoU4DzeagFPhjUu84IuwylNN/p1+GZ2WC+srObsw8c dLyv89o3VIohAxqRVvXKRP35rvOJt/3rwHmcXhjf4gJ/EwZdCeaAFx5kQZNd2pBwbl ss0PLtQloG0npgHrPrF7Og01nbQQQ/JNVOohJkbQ= Date: Mon, 11 Oct 2021 08:16:42 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f0ed36: iothread: rename PollParamInfo to IOThreadParamInfo X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Oct 2021 15:16:46 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: f0ed36a64f1750a0ebc5d2a5437f4740985461d7=0D https://github.com/qemu/qemu/commit/f0ed36a64f1750a0ebc5d2a5437f474= 0985461d7=0D Author: Stefano Garzarella =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D iothread: rename PollParamInfo to IOThreadParamInfo=0D =0D Commit 1793ad0247 ("iothread: add aio-max-batch parameter") added=0D a new parameter (aio-max-batch) to IOThread and used PollParamInfo=0D structure to handle it.=0D =0D Since it is not a parameter of the polling mechanism, we rename the=0D structure to a more generic IOThreadParamInfo.=0D =0D Suggested-by: Kevin Wolf =0D Signed-off-by: Stefano Garzarella =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210727145936.147032-2-sgarzare@redhat.com=0D Signed-off-by: Stefan Hajnoczi =0D =0D =0D Commit: 1cc7eada97914f090125e588497986f6f7900514=0D https://github.com/qemu/qemu/commit/1cc7eada97914f090125e588497986f= 6f7900514=0D Author: Stefano Garzarella =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D iothread: use IOThreadParamInfo in iothread_[set|get]_param()=0D =0D Commit 0445409d74 ("iothread: generalize=0D iothread_set_param/iothread_get_param") moved common code to set and=0D get IOThread parameters in two new functions.=0D =0D These functions are called inside callbacks, so we don't need to use an=0D= opaque pointer. Let's replace `void *opaque` parameter with=0D `IOThreadParamInfo *info`.=0D =0D Suggested-by: Kevin Wolf =0D Signed-off-by: Stefano Garzarella =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210727145936.147032-3-sgarzare@redhat.com=0D Signed-off-by: Stefan Hajnoczi =0D =0D =0D Commit: c09124dcb8401a0d635b4a52b295e9b3fc12392a=0D https://github.com/qemu/qemu/commit/c09124dcb8401a0d635b4a52b295e9b= 3fc12392a=0D Author: Richard Henderson =0D Date: 2021-10-11 (Mon, 11 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'= into staging=0D =0D Pull request=0D =0D # gpg: Signature made Mon 11 Oct 2021 05:40:35 AM PDT=0D # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB7= 3C8=0D # gpg: Good signature from "Stefan Hajnoczi " [full]= =0D # gpg: aka "Stefan Hajnoczi " [full]=0D= =0D * remotes/stefanha/tags/block-pull-request:=0D iothread: use IOThreadParamInfo in iothread_[set|get]_param()=0D iothread: rename PollParamInfo to IOThreadParamInfo=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/3a76e8a42d86...c09124dcb840= =0D From MAILER-DAEMON Mon Oct 11 14:24:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mZzxy-0001BT-Hf for mharc-qemu-commits@gnu.org; Mon, 11 Oct 2021 14:24:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZzxv-00017S-Dc for qemu-commits@nongnu.org; Mon, 11 Oct 2021 14:23:59 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:38221 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mZzxt-0001Q0-8o for qemu-commits@nongnu.org; Mon, 11 Oct 2021 14:23:58 -0400 Received: from github.com (hubbernetes-node-04bb3d6.ash1-iad.github.net [10.56.112.75]) by smtp.github.com (Postfix) with ESMTPA id 92A4B5E0B6D for ; Mon, 11 Oct 2021 11:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1633976636; bh=EPgRGu6iAbv5qOs6j0XjFOwHbkD/waJAopQxr6YSYCE=; h=Date:From:To:Subject:From; b=hAohkB3eYqpMRU6Yiv1B1zei6/q+AJpXSyHu/Uwjgp5sDhB6Wjz2Vo9iaqCkSBuhL jiFDpNS3rqu4cyvSrXkAUvu5g//K0A6P/0zRrCm/HWVTWmLh4qKPFB3bi5xJjiCae2 U675gSo4DoW4OIUtWRiaAAfXNL+aK2wO1Qnxo1Cc= Date: Mon, 11 Oct 2021 11:23:56 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f0ed36: iothread: rename PollParamInfo to IOThreadParamInfo X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Oct 2021 18:23:59 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: f0ed36a64f1750a0ebc5d2a5437f4740985461d7=0D https://github.com/qemu/qemu/commit/f0ed36a64f1750a0ebc5d2a5437f474= 0985461d7=0D Author: Stefano Garzarella =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D iothread: rename PollParamInfo to IOThreadParamInfo=0D =0D Commit 1793ad0247 ("iothread: add aio-max-batch parameter") added=0D a new parameter (aio-max-batch) to IOThread and used PollParamInfo=0D structure to handle it.=0D =0D Since it is not a parameter of the polling mechanism, we rename the=0D structure to a more generic IOThreadParamInfo.=0D =0D Suggested-by: Kevin Wolf =0D Signed-off-by: Stefano Garzarella =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210727145936.147032-2-sgarzare@redhat.com=0D Signed-off-by: Stefan Hajnoczi =0D =0D =0D Commit: 1cc7eada97914f090125e588497986f6f7900514=0D https://github.com/qemu/qemu/commit/1cc7eada97914f090125e588497986f= 6f7900514=0D Author: Stefano Garzarella =0D Date: 2021-10-07 (Thu, 07 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D iothread: use IOThreadParamInfo in iothread_[set|get]_param()=0D =0D Commit 0445409d74 ("iothread: generalize=0D iothread_set_param/iothread_get_param") moved common code to set and=0D get IOThread parameters in two new functions.=0D =0D These functions are called inside callbacks, so we don't need to use an=0D= opaque pointer. Let's replace `void *opaque` parameter with=0D `IOThreadParamInfo *info`.=0D =0D Suggested-by: Kevin Wolf =0D Signed-off-by: Stefano Garzarella =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210727145936.147032-3-sgarzare@redhat.com=0D Signed-off-by: Stefan Hajnoczi =0D =0D =0D Commit: c09124dcb8401a0d635b4a52b295e9b3fc12392a=0D https://github.com/qemu/qemu/commit/c09124dcb8401a0d635b4a52b295e9b= 3fc12392a=0D Author: Richard Henderson =0D Date: 2021-10-11 (Mon, 11 Oct 2021)=0D =0D Changed paths:=0D M iothread.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'= into staging=0D =0D Pull request=0D =0D # gpg: Signature made Mon 11 Oct 2021 05:40:35 AM PDT=0D # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB7= 3C8=0D # gpg: Good signature from "Stefan Hajnoczi " [full]= =0D # gpg: aka "Stefan Hajnoczi " [full]=0D= =0D * remotes/stefanha/tags/block-pull-request:=0D iothread: use IOThreadParamInfo in iothread_[set|get]_param()=0D iothread: rename PollParamInfo to IOThreadParamInfo=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/15a0578903dc...c09124dcb840= =0D From MAILER-DAEMON Tue Oct 12 07:43:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maGBa-0005Vi-UK for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 07:43:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maGBS-0005SS-Mk for qemu-commits@nongnu.org; Tue, 12 Oct 2021 07:43:02 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:38243) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maGBP-0001jY-Dr for qemu-commits@nongnu.org; Tue, 12 Oct 2021 07:43:01 -0400 Received: from github.com (hubbernetes-node-f55450f.ac4-iad.github.net [10.52.207.38]) by smtp.github.com (Postfix) with ESMTPA id 03205600349 for ; Tue, 12 Oct 2021 04:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634038977; bh=aFBRKB/fEafjrYXu83NJ2ABFgDvhbLnceNztUNV++Ak=; h=Date:From:To:Subject:From; b=Y1EL32J0r4pIB3VOlItmprDlzDRgvo97BUS8qpETM//jP4bQbDXOEJOOT54/Pdd6A 2eS/nfGb95ifddrzOB42pHrMjznB55yZtcPF7c1E3ioOphJsunHaWwUPbV2N1bg6F3 JaUQVeqIgYAlmm4sOmHSSIjjYPUieEPR+UbBr298= Date: Tue, 12 Oct 2021 04:42:57 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 45a904: aspeed/smc: Add watchdog Control/Status Registers X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 11:43:04 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 45a904af3861b5457050e55271e1386a7040f04f=0D https://github.com/qemu/qemu/commit/45a904af3861b5457050e55271e1386= a7040f04f=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Add watchdog Control/Status Registers=0D =0D The Aspeed SoCs have a dual boot function for firmware fail-over=0D recovery. The system auto-reboots from the second flash if the main=0D flash does not boot successfully within a certain amount of time. This=0D= function is called alternate boot (ABR) in the FMC controllers.=0D =0D On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to=0D enable the 2nd watchdog timer, on AST2600, through register SCU510.=0D If the boot on the the main flash succeeds, the firmware should=0D disable the 2nd watchdog timer. If not, the BMC is reset and the CE0=0D and CE1 mappings are swapped to restart the BMC from the 2nd flash.=0D =0D On the AST2600, the ABR registers controlling the 2nd watchdog timer=0D were moved from the watchdog register to the FMC controller and the=0D FMC model should be able to control WDT2 through its own register set.=0D= This requires more work. For now, add dummy read/write handlers to let=0D= the FW disable the 2nd watchdog without error.=0D =0D Reviewed-by: Peter Delevoryas =0D Reported-by: Peter Delevoryas =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 32c54bd0ed622bbd1614ca9d1f5f108823f5cc11=0D https://github.com/qemu/qemu/commit/32c54bd0ed622bbd1614ca9d1f5f108= 823f5cc11=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Introduce aspeed_smc_error() helper=0D =0D It unifies the errors reported by the Aspeed SMC model and also=0D removes some use of ctrl->name which will help us for the next=0D patches.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: d0180a3ae48f71d4cb5b9cea89b49451e2dc9a47=0D https://github.com/qemu/qemu/commit/d0180a3ae48f71d4cb5b9cea89b4945= 1e2dc9a47=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Stop using the model name for the memory regions=0D =0D There is no real reason to use this name. It's simply nice to have in=0D the monitor output but it's a burden for the following patch which=0D removes the AspeedSMCController structure describing the controller.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 30b6852ce4c3398c54fc6f6c7ff5ccbf8c15cf4f=0D https://github.com/qemu/qemu/commit/30b6852ce4c3398c54fc6f6c7ff5ccb= f8c15cf4f=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Drop AspeedSMCController structure=0D =0D The characteristics of the Aspeed controllers are described in a=0D AspeedSMCController structure which is redundant with the=0D AspeedSMCClass. Move all attributes under the class and adapt the code=0D= to use class attributes instead.=0D =0D This is a large change but it is functionally equivalent.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a7d78beff46f8e5c4343edca4b76675e6e55172e=0D https://github.com/qemu/qemu/commit/a7d78beff46f8e5c4343edca4b76675= e6e55172e=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash=0D =0D There is no need to keep a reference of the flash qdev in the AspeedSMCFl= ash=0D state: the SPI bus takes ownership and will release its resources. Remove= =0D AspeedSMCFlash::flash.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 6bb55e796740a0b685831faa784efb0c38dd151c=0D https://github.com/qemu/qemu/commit/6bb55e796740a0b685831faa784efb0= c38dd151c=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash=0D =0D AspeedSMCFlash::size is only used to compute the initial size of the=0D boot_rom region. Not very useful, so directly call memory_region_size()=0D= instead.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 10f915e4caefeacedf092eb90bfcce56e23e102e=0D https://github.com/qemu/qemu/commit/10f915e4caefeacedf092eb90bfcce5= 6e23e102e=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'=0D =0D 'cs' is a more appropriate name to index SPI flash devices.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: f75b5331178b6771f2a96e92ce140dd2786c8282=0D https://github.com/qemu/qemu/commit/f75b5331178b6771f2a96e92ce140dd= 2786c8282=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: QOMify AspeedSMCFlash=0D =0D AspeedSMCFlash is a small structure representing the AHB memory window=0D= through which the contents of a flash device can be accessed with MMIOs.=0D= =0D Introduce an AspeedSMCFlash SysBusDevice model and attach the associated=0D= memory region to the newly instantiated objects.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 71255c48e7b902483b94862f4882ddd050fe8ad8=0D https://github.com/qemu/qemu/commit/71255c48e7b902483b94862f4882ddd= 050fe8ad8=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Add default reset values=0D =0D This simplifies the reset handler and has the benefit to remove some=0D "bad" use of the segments array as an identifier of the controller model.= =0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a779e37c681f17f83e1d31a68c030731ebc8c998=0D https://github.com/qemu/qemu/commit/a779e37c681f17f83e1d31a68c03073= 1ebc8c998=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Introduce a new addr_width() class handler=0D =0D The AST2400 SPI controller has a transitional HW interface and it=0D stores the address width currently in use in a different register than=0D= all the other SMC controllers. It needs special handling when working=0D in 4B mode.=0D =0D Make it clear through a class handler. This also removes another use=0D of the segments array.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 33456a8870f761ae4aba223a65082985d870bfc7=0D https://github.com/qemu/qemu/commit/33456a8870f761ae4aba223a6508298= 5d870bfc7=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove unused attribute 'irqline'=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 602610383f1be927830b903275ee02fcd368d6e8=0D https://github.com/qemu/qemu/commit/602610383f1be927830b903275ee02f= cd368d6e8=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/i2c/aspeed_i2c.c=0D M include/hw/i2c/aspeed_i2c.h=0D =0D Log Message:=0D -----------=0D aspeed/i2c: QOMify AspeedI2CBus=0D =0D Introduce an AspeedI2CBus SysBusDevice model and attach the associated=0D= memory region and IRQ to the newly instantiated objects.=0D =0D Before this change, the I2C bus IRQs were all attached to the=0D SysBusDevice model of the I2C controller. Adapt the AST2600 SoC=0D realize routine to take into account this change.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 9fffe140a9424e80af5f30a149c9f0d67424434f=0D https://github.com/qemu/qemu/commit/9fffe140a9424e80af5f30a149c9f0d= 67424434f=0D Author: Peter Delevoryas =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/gpio/aspeed_gpio.c=0D =0D Log Message:=0D -----------=0D hw: aspeed_gpio: Fix pin I/O type declarations=0D =0D Some of the pin declarations in the Aspeed GPIO module were incorrect,=0D= probably because of confusion over which bits in the input and output=0D uint32_t's correspond to which groups in the label array. Since the=0D uint32_t literals are in big endian, it's sort of the opposite of what=0D= would be intuitive. The least significant bit in ast2500_set_props[6]=0D corresponds to GPIOY0, not GPIOAB7.=0D =0D GPIOxx indicates input and output capabilities, GPIxx indicates only=0D input, GPOxx indicates only output.=0D =0D AST2500:=0D - Previously had GPIW0..GPIW7 and GPIX0..GPIX7, that's correct.=0D - Previously had GPIOY0..GPIOY3, should have been GPIOY0..GPIOY7.=0D - Previously had GPIOAB0..GPIOAB3 and GPIAB4..GPIAB7, should only have=0D= been GPIOAB0..GPIOAB3.=0D =0D AST2600:=0D - GPIOT0..GPIOT7 should have been GPIT0..GPIT7.=0D - GPIOU0..GPIOU7 should have been GPIU0..GPIU7.=0D - GPIW0..GPIW7 should have been GPIOW0..GPIOW7.=0D - GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled.=0D =0D Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST= 2400 and AST2500")=0D Fixes: 36d737ee82b2972167e ("hw/gpio: Add in AST2600 specific implementat= ion")=0D Signed-off-by: Peter Delevoryas =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Rashmica Gupta =0D Message-Id: <20210928032456.3192603-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 87bd33e8b0d2e08a6030ffced9433e5927360de5=0D https://github.com/qemu/qemu/commit/87bd33e8b0d2e08a6030ffced9433e5= 927360de5=0D Author: Peter Delevoryas =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/gpio/aspeed_gpio.c=0D M include/hw/gpio/aspeed_gpio.h=0D =0D Log Message:=0D -----------=0D hw: aspeed_gpio: Fix GPIO array indexing=0D =0D The gpio array is declared as a dense array:=0D =0D qemu_irq gpios[ASPEED_GPIO_NR_PINS];=0D =0D (AST2500 has 228, AST2400 has 216, AST2600 has 208)=0D =0D However, this array is used like a matrix of GPIO sets=0D (e.g. gpio[NR_SETS][NR_PINS_PER_SET] =3D gpio[8][32])=0D =0D size_t offset =3D set * GPIOS_PER_SET + gpio;=0D qemu_set_irq(s->gpios[offset], !!(new & mask));=0D =0D This can result in an out-of-bounds access to "s->gpios" because the=0D gpio sets do _not_ have the same length. Some of the groups (e.g.=0D GPIOAB) only have 4 pins. 228 !=3D 8 * 32 =3D=3D 256.=0D =0D To fix this, I converted the gpio array from dense to sparse, to that=0D match both the hardware layout and this existing indexing code.=0D =0D Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST= 2400 and AST2500")=0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211008033501.934729-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 5857974d5d1133455e3c33e7c740786722418588=0D https://github.com/qemu/qemu/commit/5857974d5d1133455e3c33e7c740786= 722418588=0D Author: Andrew Jeffery =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D A hw/adc/aspeed_adc.c=0D M hw/adc/meson.build=0D M hw/adc/trace-events=0D A include/hw/adc/aspeed_adc.h=0D =0D Log Message:=0D -----------=0D hw/adc: Add basic Aspeed ADC model=0D =0D This model implements enough behaviour to do basic functionality tests=0D= such as device initialisation and read out of dummy sample values. The=0D= sample value generation strategy is similar to the STM ADC already in=0D the tree.=0D =0D Signed-off-by: Andrew Jeffery =0D [clg : support for multiple engines (AST2600) ]=0D Signed-off-by: C=C3=A9dric Le Goater =0D [pdel : refactored engine register struct fields to regs[] array field]=0D= [pdel : added guest-error checking for upper-8 channel regs in AST2600]=0D= [pdel : allow 16-bit reads of the channel data registers]=0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211005052604.1674891-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 199fd6230cf9e774991b60e1ee8a0ab35b6c5f9a=0D https://github.com/qemu/qemu/commit/199fd6230cf9e774991b60e1ee8a0ab= 35b6c5f9a=0D Author: Andrew Jeffery =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M include/hw/arm/aspeed_soc.h=0D =0D Log Message:=0D -----------=0D hw/arm: Integrate ADC model into Aspeed SoC=0D =0D Signed-off-by: Andrew Jeffery =0D Signed-off-by: C=C3=A9dric Le Goater =0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211005052604.1674891-3-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a8eb9a43337b3243204c0a5d270165ca2ac03910=0D https://github.com/qemu/qemu/commit/a8eb9a43337b3243204c0a5d270165c= a2ac03910=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/watchdog/trace-events=0D M hw/watchdog/wdt_aspeed.c=0D =0D Log Message:=0D -----------=0D aspeed/wdt: Add trace events=0D =0D Reviewed-by: Francisco Iglesias =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: e2804a1ec97ceede14b69a2a6e9a8b5dfa0b15c2=0D https://github.com/qemu/qemu/commit/e2804a1ec97ceede14b69a2a6e9a8b5= dfa0b15c2=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Dump address offset in trace events=0D =0D The register index is currently printed and this is confusing.=0D =0D Reviewed-by: Francisco Iglesias =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 81d8537cb297d57b0897797f1329e4d755a0eaf4=0D https://github.com/qemu/qemu/commit/81d8537cb297d57b0897797f1329e4d= 755a0eaf4=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D A hw/adc/aspeed_adc.c=0D M hw/adc/meson.build=0D M hw/adc/trace-events=0D M hw/arm/aspeed.c=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M hw/gpio/aspeed_gpio.c=0D M hw/i2c/aspeed_i2c.c=0D M hw/ssi/aspeed_smc.c=0D M hw/watchdog/trace-events=0D M hw/watchdog/wdt_aspeed.c=0D A include/hw/adc/aspeed_adc.h=0D M include/hw/arm/aspeed_soc.h=0D M include/hw/gpio/aspeed_gpio.h=0D M include/hw/i2c/aspeed_i2c.h=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211012' in= to staging=0D =0D Aspeed patches :=0D =0D * I2C QOMify (Cedric)=0D * SMC model cleanup and QOMify (Cedric)=0D * ADC model (Peter and Andrew)=0D * GPIO fixes (Peter)=0D =0D # gpg: Signature made Tue 12 Oct 2021 12:36:22 AM PDT=0D # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBE= CA1=0D # gpg: Good signature from "C=C3=A9dric Le Goater " [margin= al]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB = ECA1=0D =0D * remotes/clg/tags/pull-aspeed-20211012:=0D aspeed/smc: Dump address offset in trace events=0D aspeed/wdt: Add trace events=0D hw/arm: Integrate ADC model into Aspeed SoC=0D hw/adc: Add basic Aspeed ADC model=0D hw: aspeed_gpio: Fix GPIO array indexing=0D hw: aspeed_gpio: Fix pin I/O type declarations=0D aspeed/i2c: QOMify AspeedI2CBus=0D aspeed/smc: Remove unused attribute 'irqline'=0D aspeed/smc: Introduce a new addr_width() class handler=0D aspeed/smc: Add default reset values=0D aspeed/smc: QOMify AspeedSMCFlash=0D aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'=0D aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash=0D aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash=0D aspeed/smc: Drop AspeedSMCController structure=0D aspeed/smc: Stop using the model name for the memory regions=0D aspeed/smc: Introduce aspeed_smc_error() helper=0D aspeed/smc: Add watchdog Control/Status Registers=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c09124dcb840...81d8537cb297= =0D From MAILER-DAEMON Tue Oct 12 09:15:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maHd6-0002Sc-9Q for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 09:15:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maHd4-0002OA-Op for qemu-commits@nongnu.org; Tue, 12 Oct 2021 09:15:38 -0400 Received: from out-19.smtp.github.com ([192.30.252.202]:50929) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maHcz-0006vC-HA for qemu-commits@nongnu.org; Tue, 12 Oct 2021 09:15:37 -0400 Received: from github.com (hubbernetes-node-f2595ab.va3-iad.github.net [10.48.206.60]) by smtp.github.com (Postfix) with ESMTPA id B7684E155D for ; Tue, 12 Oct 2021 06:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634044532; bh=8d0O5mvLo9l7+Z5aJQVKo3p5Pe4eIH6zFx1SSCTiLPw=; h=Date:From:To:Subject:From; b=KHRR911jghNNJqyJlHLdeSmjkF4i+au65hV87+NKbiL+2D1OMaDy+zMKj2T2rDpSV gHLVeemfsO8Y3OO0/a6j6QsjqVwhW44wjI8seNZn0dY1BAhgnttMRuLvkW+pyXXgCd iA+Kik8yXuxJsMJZRGY+Gze9adTK1tueO+6b+eCE= Date: Tue, 12 Oct 2021 06:15:32 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.202; envelope-from=noreply@github.com; helo=out-19.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 45a904: aspeed/smc: Add watchdog Control/Status Registers X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 13:15:39 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 45a904af3861b5457050e55271e1386a7040f04f=0D https://github.com/qemu/qemu/commit/45a904af3861b5457050e55271e1386= a7040f04f=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Add watchdog Control/Status Registers=0D =0D The Aspeed SoCs have a dual boot function for firmware fail-over=0D recovery. The system auto-reboots from the second flash if the main=0D flash does not boot successfully within a certain amount of time. This=0D= function is called alternate boot (ABR) in the FMC controllers.=0D =0D On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to=0D enable the 2nd watchdog timer, on AST2600, through register SCU510.=0D If the boot on the the main flash succeeds, the firmware should=0D disable the 2nd watchdog timer. If not, the BMC is reset and the CE0=0D and CE1 mappings are swapped to restart the BMC from the 2nd flash.=0D =0D On the AST2600, the ABR registers controlling the 2nd watchdog timer=0D were moved from the watchdog register to the FMC controller and the=0D FMC model should be able to control WDT2 through its own register set.=0D= This requires more work. For now, add dummy read/write handlers to let=0D= the FW disable the 2nd watchdog without error.=0D =0D Reviewed-by: Peter Delevoryas =0D Reported-by: Peter Delevoryas =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 32c54bd0ed622bbd1614ca9d1f5f108823f5cc11=0D https://github.com/qemu/qemu/commit/32c54bd0ed622bbd1614ca9d1f5f108= 823f5cc11=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Introduce aspeed_smc_error() helper=0D =0D It unifies the errors reported by the Aspeed SMC model and also=0D removes some use of ctrl->name which will help us for the next=0D patches.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: d0180a3ae48f71d4cb5b9cea89b49451e2dc9a47=0D https://github.com/qemu/qemu/commit/d0180a3ae48f71d4cb5b9cea89b4945= 1e2dc9a47=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Stop using the model name for the memory regions=0D =0D There is no real reason to use this name. It's simply nice to have in=0D the monitor output but it's a burden for the following patch which=0D removes the AspeedSMCController structure describing the controller.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 30b6852ce4c3398c54fc6f6c7ff5ccbf8c15cf4f=0D https://github.com/qemu/qemu/commit/30b6852ce4c3398c54fc6f6c7ff5ccb= f8c15cf4f=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Drop AspeedSMCController structure=0D =0D The characteristics of the Aspeed controllers are described in a=0D AspeedSMCController structure which is redundant with the=0D AspeedSMCClass. Move all attributes under the class and adapt the code=0D= to use class attributes instead.=0D =0D This is a large change but it is functionally equivalent.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a7d78beff46f8e5c4343edca4b76675e6e55172e=0D https://github.com/qemu/qemu/commit/a7d78beff46f8e5c4343edca4b76675= e6e55172e=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash=0D =0D There is no need to keep a reference of the flash qdev in the AspeedSMCFl= ash=0D state: the SPI bus takes ownership and will release its resources. Remove= =0D AspeedSMCFlash::flash.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 6bb55e796740a0b685831faa784efb0c38dd151c=0D https://github.com/qemu/qemu/commit/6bb55e796740a0b685831faa784efb0= c38dd151c=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash=0D =0D AspeedSMCFlash::size is only used to compute the initial size of the=0D boot_rom region. Not very useful, so directly call memory_region_size()=0D= instead.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 10f915e4caefeacedf092eb90bfcce56e23e102e=0D https://github.com/qemu/qemu/commit/10f915e4caefeacedf092eb90bfcce5= 6e23e102e=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'=0D =0D 'cs' is a more appropriate name to index SPI flash devices.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: f75b5331178b6771f2a96e92ce140dd2786c8282=0D https://github.com/qemu/qemu/commit/f75b5331178b6771f2a96e92ce140dd= 2786c8282=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: QOMify AspeedSMCFlash=0D =0D AspeedSMCFlash is a small structure representing the AHB memory window=0D= through which the contents of a flash device can be accessed with MMIOs.=0D= =0D Introduce an AspeedSMCFlash SysBusDevice model and attach the associated=0D= memory region to the newly instantiated objects.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 71255c48e7b902483b94862f4882ddd050fe8ad8=0D https://github.com/qemu/qemu/commit/71255c48e7b902483b94862f4882ddd= 050fe8ad8=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Add default reset values=0D =0D This simplifies the reset handler and has the benefit to remove some=0D "bad" use of the segments array as an identifier of the controller model.= =0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a779e37c681f17f83e1d31a68c030731ebc8c998=0D https://github.com/qemu/qemu/commit/a779e37c681f17f83e1d31a68c03073= 1ebc8c998=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Introduce a new addr_width() class handler=0D =0D The AST2400 SPI controller has a transitional HW interface and it=0D stores the address width currently in use in a different register than=0D= all the other SMC controllers. It needs special handling when working=0D in 4B mode.=0D =0D Make it clear through a class handler. This also removes another use=0D of the segments array.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 33456a8870f761ae4aba223a65082985d870bfc7=0D https://github.com/qemu/qemu/commit/33456a8870f761ae4aba223a6508298= 5d870bfc7=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Remove unused attribute 'irqline'=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 602610383f1be927830b903275ee02fcd368d6e8=0D https://github.com/qemu/qemu/commit/602610383f1be927830b903275ee02f= cd368d6e8=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/i2c/aspeed_i2c.c=0D M include/hw/i2c/aspeed_i2c.h=0D =0D Log Message:=0D -----------=0D aspeed/i2c: QOMify AspeedI2CBus=0D =0D Introduce an AspeedI2CBus SysBusDevice model and attach the associated=0D= memory region and IRQ to the newly instantiated objects.=0D =0D Before this change, the I2C bus IRQs were all attached to the=0D SysBusDevice model of the I2C controller. Adapt the AST2600 SoC=0D realize routine to take into account this change.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 9fffe140a9424e80af5f30a149c9f0d67424434f=0D https://github.com/qemu/qemu/commit/9fffe140a9424e80af5f30a149c9f0d= 67424434f=0D Author: Peter Delevoryas =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/gpio/aspeed_gpio.c=0D =0D Log Message:=0D -----------=0D hw: aspeed_gpio: Fix pin I/O type declarations=0D =0D Some of the pin declarations in the Aspeed GPIO module were incorrect,=0D= probably because of confusion over which bits in the input and output=0D uint32_t's correspond to which groups in the label array. Since the=0D uint32_t literals are in big endian, it's sort of the opposite of what=0D= would be intuitive. The least significant bit in ast2500_set_props[6]=0D corresponds to GPIOY0, not GPIOAB7.=0D =0D GPIOxx indicates input and output capabilities, GPIxx indicates only=0D input, GPOxx indicates only output.=0D =0D AST2500:=0D - Previously had GPIW0..GPIW7 and GPIX0..GPIX7, that's correct.=0D - Previously had GPIOY0..GPIOY3, should have been GPIOY0..GPIOY7.=0D - Previously had GPIOAB0..GPIOAB3 and GPIAB4..GPIAB7, should only have=0D= been GPIOAB0..GPIOAB3.=0D =0D AST2600:=0D - GPIOT0..GPIOT7 should have been GPIT0..GPIT7.=0D - GPIOU0..GPIOU7 should have been GPIU0..GPIU7.=0D - GPIW0..GPIW7 should have been GPIOW0..GPIOW7.=0D - GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled.=0D =0D Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST= 2400 and AST2500")=0D Fixes: 36d737ee82b2972167e ("hw/gpio: Add in AST2600 specific implementat= ion")=0D Signed-off-by: Peter Delevoryas =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Rashmica Gupta =0D Message-Id: <20210928032456.3192603-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 87bd33e8b0d2e08a6030ffced9433e5927360de5=0D https://github.com/qemu/qemu/commit/87bd33e8b0d2e08a6030ffced9433e5= 927360de5=0D Author: Peter Delevoryas =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/gpio/aspeed_gpio.c=0D M include/hw/gpio/aspeed_gpio.h=0D =0D Log Message:=0D -----------=0D hw: aspeed_gpio: Fix GPIO array indexing=0D =0D The gpio array is declared as a dense array:=0D =0D qemu_irq gpios[ASPEED_GPIO_NR_PINS];=0D =0D (AST2500 has 228, AST2400 has 216, AST2600 has 208)=0D =0D However, this array is used like a matrix of GPIO sets=0D (e.g. gpio[NR_SETS][NR_PINS_PER_SET] =3D gpio[8][32])=0D =0D size_t offset =3D set * GPIOS_PER_SET + gpio;=0D qemu_set_irq(s->gpios[offset], !!(new & mask));=0D =0D This can result in an out-of-bounds access to "s->gpios" because the=0D gpio sets do _not_ have the same length. Some of the groups (e.g.=0D GPIOAB) only have 4 pins. 228 !=3D 8 * 32 =3D=3D 256.=0D =0D To fix this, I converted the gpio array from dense to sparse, to that=0D match both the hardware layout and this existing indexing code.=0D =0D Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST= 2400 and AST2500")=0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211008033501.934729-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 5857974d5d1133455e3c33e7c740786722418588=0D https://github.com/qemu/qemu/commit/5857974d5d1133455e3c33e7c740786= 722418588=0D Author: Andrew Jeffery =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D A hw/adc/aspeed_adc.c=0D M hw/adc/meson.build=0D M hw/adc/trace-events=0D A include/hw/adc/aspeed_adc.h=0D =0D Log Message:=0D -----------=0D hw/adc: Add basic Aspeed ADC model=0D =0D This model implements enough behaviour to do basic functionality tests=0D= such as device initialisation and read out of dummy sample values. The=0D= sample value generation strategy is similar to the STM ADC already in=0D the tree.=0D =0D Signed-off-by: Andrew Jeffery =0D [clg : support for multiple engines (AST2600) ]=0D Signed-off-by: C=C3=A9dric Le Goater =0D [pdel : refactored engine register struct fields to regs[] array field]=0D= [pdel : added guest-error checking for upper-8 channel regs in AST2600]=0D= [pdel : allow 16-bit reads of the channel data registers]=0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211005052604.1674891-2-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 199fd6230cf9e774991b60e1ee8a0ab35b6c5f9a=0D https://github.com/qemu/qemu/commit/199fd6230cf9e774991b60e1ee8a0ab= 35b6c5f9a=0D Author: Andrew Jeffery =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M include/hw/arm/aspeed_soc.h=0D =0D Log Message:=0D -----------=0D hw/arm: Integrate ADC model into Aspeed SoC=0D =0D Signed-off-by: Andrew Jeffery =0D Signed-off-by: C=C3=A9dric Le Goater =0D Signed-off-by: Peter Delevoryas =0D Message-Id: <20211005052604.1674891-3-pdel@fb.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: a8eb9a43337b3243204c0a5d270165ca2ac03910=0D https://github.com/qemu/qemu/commit/a8eb9a43337b3243204c0a5d270165c= a2ac03910=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/watchdog/trace-events=0D M hw/watchdog/wdt_aspeed.c=0D =0D Log Message:=0D -----------=0D aspeed/wdt: Add trace events=0D =0D Reviewed-by: Francisco Iglesias =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: e2804a1ec97ceede14b69a2a6e9a8b5dfa0b15c2=0D https://github.com/qemu/qemu/commit/e2804a1ec97ceede14b69a2a6e9a8b5= dfa0b15c2=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D =0D Log Message:=0D -----------=0D aspeed/smc: Dump address offset in trace events=0D =0D The register index is currently printed and this is confusing.=0D =0D Reviewed-by: Francisco Iglesias =0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: 81d8537cb297d57b0897797f1329e4d755a0eaf4=0D https://github.com/qemu/qemu/commit/81d8537cb297d57b0897797f1329e4d= 755a0eaf4=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D A hw/adc/aspeed_adc.c=0D M hw/adc/meson.build=0D M hw/adc/trace-events=0D M hw/arm/aspeed.c=0D M hw/arm/aspeed_ast2600.c=0D M hw/arm/aspeed_soc.c=0D M hw/gpio/aspeed_gpio.c=0D M hw/i2c/aspeed_i2c.c=0D M hw/ssi/aspeed_smc.c=0D M hw/watchdog/trace-events=0D M hw/watchdog/wdt_aspeed.c=0D A include/hw/adc/aspeed_adc.h=0D M include/hw/arm/aspeed_soc.h=0D M include/hw/gpio/aspeed_gpio.h=0D M include/hw/i2c/aspeed_i2c.h=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211012' in= to staging=0D =0D Aspeed patches :=0D =0D * I2C QOMify (Cedric)=0D * SMC model cleanup and QOMify (Cedric)=0D * ADC model (Peter and Andrew)=0D * GPIO fixes (Peter)=0D =0D # gpg: Signature made Tue 12 Oct 2021 12:36:22 AM PDT=0D # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBE= CA1=0D # gpg: Good signature from "C=C3=A9dric Le Goater " [margin= al]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB = ECA1=0D =0D * remotes/clg/tags/pull-aspeed-20211012:=0D aspeed/smc: Dump address offset in trace events=0D aspeed/wdt: Add trace events=0D hw/arm: Integrate ADC model into Aspeed SoC=0D hw/adc: Add basic Aspeed ADC model=0D hw: aspeed_gpio: Fix GPIO array indexing=0D hw: aspeed_gpio: Fix pin I/O type declarations=0D aspeed/i2c: QOMify AspeedI2CBus=0D aspeed/smc: Remove unused attribute 'irqline'=0D aspeed/smc: Introduce a new addr_width() class handler=0D aspeed/smc: Add default reset values=0D aspeed/smc: QOMify AspeedSMCFlash=0D aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'=0D aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash=0D aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash=0D aspeed/smc: Drop AspeedSMCController structure=0D aspeed/smc: Stop using the model name for the memory regions=0D aspeed/smc: Introduce aspeed_smc_error() helper=0D aspeed/smc: Add watchdog Control/Status Registers=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c09124dcb840...81d8537cb297= =0D From MAILER-DAEMON Tue Oct 12 09:22:34 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maHjm-0004Xp-KZ for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 09:22:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maHjk-0004Tz-8D for qemu-commits@nongnu.org; Tue, 12 Oct 2021 09:22:32 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:45743 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maHjh-00028Q-CD for qemu-commits@nongnu.org; Tue, 12 Oct 2021 09:22:31 -0400 Received: from github.com (hubbernetes-node-a4a0adb.ac4-iad.github.net [10.52.205.38]) by smtp.github.com (Postfix) with ESMTPA id AECDD5202E1 for ; Tue, 12 Oct 2021 06:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634044948; bh=rXjVxqZyzzqN0Ex+NHdsVvwJCJdDQjICWtDONeIq9Vw=; h=Date:From:To:Subject:From; b=GjuG7jWUIfudsHy+q7d+ovAnoYdj1/p5sRA8vzXMgCQZr/CB20VWZ0MOJtRcXNjWD 2AGvePNrjfkurnJY+tscKpoMBAou8D/BlhJGUFBdCTbFtd/ELC71bMA5fnGp4xJqfx UIx9vqftxTXTEYa1H1aBmao/gs6XRsqhsVJvCN38= Date: Tue, 12 Oct 2021 06:22:28 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 9557af: configure: don't override the selected host test c... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 13:22:32 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 9557af9ce94d434440d6397fb0d80748e4714e94=0D https://github.com/qemu/qemu/commit/9557af9ce94d434440d6397fb0d8074= 8e4714e94=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: don't override the selected host test compiler if defined=0D= =0D There are not many cases you would want to do this but one is if you=0D want to use a test friendly compiler like gcc instead of a system=0D compiler like clang. Either way we should honour the users choice if=0D they have made it.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-2-alex.bennee@linaro.org>=0D =0D =0D Commit: 4f0ebed41809531e4e84658b8ac1742c4ba6966a=0D https://github.com/qemu/qemu/commit/4f0ebed41809531e4e84658b8ac1742= c4ba6966a=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/sha1.c=0D =0D Log Message:=0D -----------=0D tests/tcg/sha1: remove endian include=0D =0D This doesn't exist in BSD world and doesn't seem to be needed by=0D either.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-3-alex.bennee@linaro.org>=0D =0D =0D Commit: 5343a837cdb0e10db05310e0da5a89843539b400=0D https://github.com/qemu/qemu/commit/5343a837cdb0e10db05310e0da5a898= 43539b400=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D tests/tcg: move some multiarch files and make conditional=0D =0D We had some messy code to filter out stuff we can't build. Lets junk=0D that and simplify the logic by pushing some stuff into subdirs. In=0D particular we move:=0D =0D float_helpers into libs - not a standalone test=0D linux-test into linux - so we only build on Linux hosts=0D =0D This allows for at least some of the tests to be nominally usable=0D by *BSD user builds.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-4-alex.bennee@linaro.org>=0D =0D =0D Commit: 5c24acf320a0ac259447788162a3b17505ad4fb9=0D https://github.com/qemu/qemu/commit/5c24acf320a0ac259447788162a3b17= 505ad4fb9=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/container-cross.yml=0D M tests/docker/Makefile.include=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D =0D Log Message:=0D -----------=0D tests/docker: promote debian-riscv64-cross to a full image=0D =0D To be able to cross build QEMU itself we need to include a few more=0D libraries. These are only available in Debian's unstable ports repo=0D for now so we need to base the riscv64 image on sid with the the=0D minimal libs needed to build QEMU (glib/pixman).=0D =0D The result works but is not as clean as using build-dep to bring in=0D more dependencies. However sid is by definition a shifting pile of=0D sand and by keeping the list of libs minimal we reduce the chance of=0D having an image we can't build. It's good enough for a basic cross=0D build testing of TCG.=0D =0D Cc: "Daniel P. Berrang=C3=A9" =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-2-richard.henderson@linaro.org>=0D [AJB: tweak allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-5-alex.bennee@linaro.org>=0D =0D =0D Commit: 9f62025141c67c5dbe5c5a04becb12add2de12cf=0D https://github.com/qemu/qemu/commit/9f62025141c67c5dbe5c5a04becb12a= dd2de12cf=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/crossbuilds.yml=0D =0D Log Message:=0D -----------=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-3-richard.henderson@linaro.org>=0D [AJB: add allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20210917162332.3511179-6-alex.bennee@linaro.org>=0D =0D =0D Commit: 9d03f5abede84a7b05877f7adeeea967d55566a0=0D https://github.com/qemu/qemu/commit/9d03f5abede84a7b05877f7adeeea96= 7d55566a0=0D Author: Thomas Huth =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .travis.yml=0D =0D Log Message:=0D -----------=0D travis.yml: Remove the "Release tarball" job=0D =0D This is a leftover from the days when we were using Travis excessively,=0D= but since x86 jobs are not really usable there anymore, this job has=0D likely never been used since many months. Let's simply remove it now.=0D =0D Signed-off-by: Thomas Huth =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210917094826.466047-1-thuth@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-8-alex.bennee@linaro.org>=0D =0D =0D Commit: dcbad7a6ed57f2885307b1c2236ca51796e638ad=0D https://github.com/qemu/qemu/commit/dcbad7a6ed57f2885307b1c2236ca51= 796e638ad=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/static_checks.yml=0D =0D Log Message:=0D -----------=0D gitlab: skip the check-patch job on the upstream repo=0D =0D The check-patch job is intended to be used by contributors or=0D subsystem maintainers to see if there are style mistakes. The=0D false positive rate is too high to be used in a gating scenario=0D so should not run it on the upstream repo ever.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-2-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-9-alex.bennee@linaro.org>=0D =0D =0D Commit: f13abca0a3c55e2da35d2a0e6d6e0a75bb012885=0D https://github.com/qemu/qemu/commit/f13abca0a3c55e2da35d2a0e6d6e0a7= 5bb012885=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D =0D Log Message:=0D -----------=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D =0D A typo meant the substitution would not work, and the placeholder in the=0D= target file didn't even exist.=0D =0D The result was that tests were never run on the FreeBSD and macOS jobs,=0D= only a basic build.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Willian Rampazzo =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-3-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-10-alex.bennee@linaro.org>=0D =0D =0D Commit: 6a78a987c6826d44c9e70eddb63613e455f691e5=0D https://github.com/qemu/qemu/commit/6a78a987c6826d44c9e70eddb63613e= 455f691e5=0D Author: Lukas J=C3=BCnger =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M plugins/qemu-plugins.symbols=0D =0D Log Message:=0D -----------=0D plugins/: Add missing functions to symbol list=0D =0D Some functions of the plugin API were missing in=0D the symbol list. However, they are all used by=0D the contributed example plugins. QEMU fails to=0D load the plugin if the function symbol is not=0D exported.=0D =0D Signed-off-by: Lukas J=C3=BCnger =0D Message-Id: <20210905140939.638928-2-lukas.junger@greensocs.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-11-alex.bennee@linaro.org>=0D =0D =0D Commit: 5d23d530235eaf352b1067854ad22681b1ab5584=0D https://github.com/qemu/qemu/commit/5d23d530235eaf352b1067854ad2268= 1b1ab5584=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start=0D =0D We use INDEX_op_insn_start to make the start of instruction boundaries.=0D= If we don't do it in the .insn_start hook things get confused especially=0D= now plugins want to use that marking to identify the start of instruction= s=0D and will bomb out if it sees instrumented ops before the first instructio= n=0D boundary.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Alex Benn=C3=A9e =0D Message-Id: <20211011185332.166763-1-richard.henderson@linaro.org>=0D Signed-off-by: Alex Benn=C3=A9e =0D =0D =0D Commit: 453d50ce75b16d1b00a0783279779471e079f489=0D https://github.com/qemu/qemu/commit/453d50ce75b16d1b00a078327977947= 1e079f489=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/plugin-gen.c=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D =0D Coverity doesn't know enough about how we have arranged our plugin TCG=0D= ops to know we will always have incremented insn_idx before injecting=0D the callback. Let us assert it for the benefit of Coverity and protect=0D= ourselves from accidentally breaking the assumption and triggering=0D harder to grok errors deeper in the code if we attempt a negative=0D indexed array lookup.=0D =0D However to get to this point we re-factor the code and remove the=0D second hand instruction boundary detection in favour of scanning the=0D full set of ops and using the existing INDEX_op_insn_start to cleanly=0D detect when the instruction has started. As we no longer need the=0D plugin specific list of ops we delete that.=0D =0D My initial benchmarks shows no discernible impact of dropping the=0D plugin specific ops list.=0D =0D Fixes: Coverity 1459509=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Richard Henderson =0D Cc: Peter Maydell =0D Message-Id: <20210917162332.3511179-12-alex.bennee@linaro.org>=0D =0D =0D Commit: 9b89cdb2a5064a87b8a7172fa1748d46aa37a9df=0D https://github.com/qemu/qemu/commit/9b89cdb2a5064a87b8a7172fa1748d4= 6aa37a9df=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D =0D Log Message:=0D -----------=0D .github: move repo lockdown to the v2 configuration=0D =0D I was getting prompted by GitHub for new permissions but it turns out=0D per https://github.com/dessant/repo-lockdown/issues/6:=0D =0D Repo Lockdown has been rewritten for GitHub Actions, offering new=0D features and better control over your automation presets. The legacy=0D= GitHub App has been deprecated, and the public instance of the app=0D has been shut down.=0D =0D So this is what I've done. As the issues tab is disabled I've removed=0D the handling for issues from the new version.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20211004154308.2114870-1-alex.bennee@linaro.org>=0D =0D =0D Commit: 17888749ba0fb06694de5efe0b941f16a0fba6fa=0D https://github.com/qemu/qemu/commit/17888749ba0fb06694de5efe0b941f1= 6a0fba6fa=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D =0D Log Message:=0D -----------=0D tests/docker: add a debian-native image and make available=0D =0D This image is intended for building whatever the native versions of=0D QEMU are for the host architecture. This will hopefully be an aid for=0D 3rd parties who want to be able to build QEMU themselves without=0D redoing all the dependencies themselves.=0D =0D We disable the registry because we currently don't have multi-arch=0D support there.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Anders Roxell =0D Acked-by: Willian Rampazzo =0D Message-Id: <20210922151528.2192966-1-alex.bennee@linaro.org>=0D =0D =0D Commit: bfd9a76f9c143d450ab5545dedfa74364b39fc56=0D https://github.com/qemu/qemu/commit/bfd9a76f9c143d450ab5545dedfa743= 64b39fc56=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D M .gitlab-ci.d/container-cross.yml=0D M .gitlab-ci.d/crossbuilds.yml=0D M .gitlab-ci.d/static_checks.yml=0D M .travis.yml=0D M accel/tcg/plugin-gen.c=0D M configure=0D M include/tcg/tcg.h=0D M plugins/qemu-plugins.symbols=0D M target/s390x/tcg/translate.c=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/multiarch/sha1.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-= 2' into staging=0D =0D Some testing and plugin updates:=0D =0D - don't override the test compiler when specified=0D - split some multiarch tests by guest OS=0D - add riscv64 docker image and cross-compile tests=0D - drop release tarball test from Travis=0D - skip check-patch on master repo=0D - fix passing of TEST_TARGETS to cirrus=0D - fix missing symbols in plugins=0D - ensure s390x insn start ops precede plugin instrumentation=0D - refactor plugin instruction boundary detection=0D - update github repo lockdown=0D - add a debian-native test image for multi-arch builds=0D =0D # gpg: Signature made Tue 12 Oct 2021 02:35:00 AM PDT=0D # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2= A44=0D # gpg: Good signature from "Alex Benn=C3=A9e (Master Work Key) " [full]=0D =0D * remotes/stsquad/tags/pull-for-6.2-121021-2:=0D tests/docker: add a debian-native image and make available=0D .github: move repo lockdown to the v2 configuration=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start=0D plugins/: Add missing functions to symbol list=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D gitlab: skip the check-patch job on the upstream repo=0D travis.yml: Remove the "Release tarball" job=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D tests/docker: promote debian-riscv64-cross to a full image=0D tests/tcg: move some multiarch files and make conditional=0D tests/tcg/sha1: remove endian include=0D configure: don't override the selected host test compiler if defined=0D= =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/81d8537cb297...bfd9a76f9c14= =0D From MAILER-DAEMON Tue Oct 12 11:47:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maK0E-0000uD-AV for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 11:47:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maK0B-0000sU-0Z for qemu-commits@nongnu.org; Tue, 12 Oct 2021 11:47:40 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:59881 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maK08-0007lk-5q for qemu-commits@nongnu.org; Tue, 12 Oct 2021 11:47:38 -0400 Received: from github.com (hubbernetes-node-67eaa45.va3-iad.github.net [10.48.207.100]) by smtp.github.com (Postfix) with ESMTPA id 757175C000F for ; Tue, 12 Oct 2021 08:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634053655; bh=x4q6XADbzdaWguXtXm6s5c7xW9ptiYffhRmm2r5iRVw=; h=Date:From:To:Subject:From; b=bCs9Ru3jn0iQNm8ffJ+P5yHX6VMyiCaVD6yxN/q/dwoeRBsTPC4ovhKD7JY+lUTEW ibyW025C0oNp6/RMpaoOQcuGOTheFcnzIwJ4SEimZctRJr7bawopWnIMTFtUCBYqBl BP/Bgi+iXWYXiF1IiWF6yXPU3oNzbIPgxXopthWw= Date: Tue, 12 Oct 2021 08:47:35 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 9557af: configure: don't override the selected host test c... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 15:47:40 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 9557af9ce94d434440d6397fb0d80748e4714e94=0D https://github.com/qemu/qemu/commit/9557af9ce94d434440d6397fb0d8074= 8e4714e94=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: don't override the selected host test compiler if defined=0D= =0D There are not many cases you would want to do this but one is if you=0D want to use a test friendly compiler like gcc instead of a system=0D compiler like clang. Either way we should honour the users choice if=0D they have made it.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-2-alex.bennee@linaro.org>=0D =0D =0D Commit: 4f0ebed41809531e4e84658b8ac1742c4ba6966a=0D https://github.com/qemu/qemu/commit/4f0ebed41809531e4e84658b8ac1742= c4ba6966a=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/sha1.c=0D =0D Log Message:=0D -----------=0D tests/tcg/sha1: remove endian include=0D =0D This doesn't exist in BSD world and doesn't seem to be needed by=0D either.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-3-alex.bennee@linaro.org>=0D =0D =0D Commit: 5343a837cdb0e10db05310e0da5a89843539b400=0D https://github.com/qemu/qemu/commit/5343a837cdb0e10db05310e0da5a898= 43539b400=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D tests/tcg: move some multiarch files and make conditional=0D =0D We had some messy code to filter out stuff we can't build. Lets junk=0D that and simplify the logic by pushing some stuff into subdirs. In=0D particular we move:=0D =0D float_helpers into libs - not a standalone test=0D linux-test into linux - so we only build on Linux hosts=0D =0D This allows for at least some of the tests to be nominally usable=0D by *BSD user builds.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Cc: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Warner Losh =0D Message-Id: <20210917162332.3511179-4-alex.bennee@linaro.org>=0D =0D =0D Commit: 5c24acf320a0ac259447788162a3b17505ad4fb9=0D https://github.com/qemu/qemu/commit/5c24acf320a0ac259447788162a3b17= 505ad4fb9=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/container-cross.yml=0D M tests/docker/Makefile.include=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D =0D Log Message:=0D -----------=0D tests/docker: promote debian-riscv64-cross to a full image=0D =0D To be able to cross build QEMU itself we need to include a few more=0D libraries. These are only available in Debian's unstable ports repo=0D for now so we need to base the riscv64 image on sid with the the=0D minimal libs needed to build QEMU (glib/pixman).=0D =0D The result works but is not as clean as using build-dep to bring in=0D more dependencies. However sid is by definition a shifting pile of=0D sand and by keeping the list of libs minimal we reduce the chance of=0D having an image we can't build. It's good enough for a basic cross=0D build testing of TCG.=0D =0D Cc: "Daniel P. Berrang=C3=A9" =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-2-richard.henderson@linaro.org>=0D [AJB: tweak allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-5-alex.bennee@linaro.org>=0D =0D =0D Commit: 9f62025141c67c5dbe5c5a04becb12add2de12cf=0D https://github.com/qemu/qemu/commit/9f62025141c67c5dbe5c5a04becb12a= dd2de12cf=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/crossbuilds.yml=0D =0D Log Message:=0D -----------=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D =0D Signed-off-by: Richard Henderson =0D Message-Id: <20210914185830.1378771-3-richard.henderson@linaro.org>=0D [AJB: add allow_failure]=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20210917162332.3511179-6-alex.bennee@linaro.org>=0D =0D =0D Commit: 9d03f5abede84a7b05877f7adeeea967d55566a0=0D https://github.com/qemu/qemu/commit/9d03f5abede84a7b05877f7adeeea96= 7d55566a0=0D Author: Thomas Huth =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .travis.yml=0D =0D Log Message:=0D -----------=0D travis.yml: Remove the "Release tarball" job=0D =0D This is a leftover from the days when we were using Travis excessively,=0D= but since x86 jobs are not really usable there anymore, this job has=0D likely never been used since many months. Let's simply remove it now.=0D =0D Signed-off-by: Thomas Huth =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210917094826.466047-1-thuth@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-8-alex.bennee@linaro.org>=0D =0D =0D Commit: dcbad7a6ed57f2885307b1c2236ca51796e638ad=0D https://github.com/qemu/qemu/commit/dcbad7a6ed57f2885307b1c2236ca51= 796e638ad=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/static_checks.yml=0D =0D Log Message:=0D -----------=0D gitlab: skip the check-patch job on the upstream repo=0D =0D The check-patch job is intended to be used by contributors or=0D subsystem maintainers to see if there are style mistakes. The=0D false positive rate is too high to be used in a gating scenario=0D so should not run it on the upstream repo ever.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-2-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-9-alex.bennee@linaro.org>=0D =0D =0D Commit: f13abca0a3c55e2da35d2a0e6d6e0a75bb012885=0D https://github.com/qemu/qemu/commit/f13abca0a3c55e2da35d2a0e6d6e0a7= 5bb012885=0D Author: Daniel P. Berrang=C3=A9 =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D =0D Log Message:=0D -----------=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D =0D A typo meant the substitution would not work, and the placeholder in the=0D= target file didn't even exist.=0D =0D The result was that tests were never run on the FreeBSD and macOS jobs,=0D= only a basic build.=0D =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D Acked-by: Thomas Huth =0D Reviewed-by: Willian Rampazzo =0D Reviewed-by: Richard Henderson =0D Message-Id: <20210915125452.1704899-3-berrange@redhat.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-10-alex.bennee@linaro.org>=0D =0D =0D Commit: 6a78a987c6826d44c9e70eddb63613e455f691e5=0D https://github.com/qemu/qemu/commit/6a78a987c6826d44c9e70eddb63613e= 455f691e5=0D Author: Lukas J=C3=BCnger =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M plugins/qemu-plugins.symbols=0D =0D Log Message:=0D -----------=0D plugins/: Add missing functions to symbol list=0D =0D Some functions of the plugin API were missing in=0D the symbol list. However, they are all used by=0D the contributed example plugins. QEMU fails to=0D load the plugin if the function symbol is not=0D exported.=0D =0D Signed-off-by: Lukas J=C3=BCnger =0D Message-Id: <20210905140939.638928-2-lukas.junger@greensocs.com>=0D Signed-off-by: Alex Benn=C3=A9e =0D Message-Id: <20210917162332.3511179-11-alex.bennee@linaro.org>=0D =0D =0D Commit: 5d23d530235eaf352b1067854ad22681b1ab5584=0D https://github.com/qemu/qemu/commit/5d23d530235eaf352b1067854ad2268= 1b1ab5584=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start=0D =0D We use INDEX_op_insn_start to make the start of instruction boundaries.=0D= If we don't do it in the .insn_start hook things get confused especially=0D= now plugins want to use that marking to identify the start of instruction= s=0D and will bomb out if it sees instrumented ops before the first instructio= n=0D boundary.=0D =0D Signed-off-by: Richard Henderson =0D Reviewed-by: Alex Benn=C3=A9e =0D Message-Id: <20211011185332.166763-1-richard.henderson@linaro.org>=0D Signed-off-by: Alex Benn=C3=A9e =0D =0D =0D Commit: 453d50ce75b16d1b00a0783279779471e079f489=0D https://github.com/qemu/qemu/commit/453d50ce75b16d1b00a078327977947= 1e079f489=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/plugin-gen.c=0D M include/tcg/tcg.h=0D =0D Log Message:=0D -----------=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D =0D Coverity doesn't know enough about how we have arranged our plugin TCG=0D= ops to know we will always have incremented insn_idx before injecting=0D the callback. Let us assert it for the benefit of Coverity and protect=0D= ourselves from accidentally breaking the assumption and triggering=0D harder to grok errors deeper in the code if we attempt a negative=0D indexed array lookup.=0D =0D However to get to this point we re-factor the code and remove the=0D second hand instruction boundary detection in favour of scanning the=0D full set of ops and using the existing INDEX_op_insn_start to cleanly=0D detect when the instruction has started. As we no longer need the=0D plugin specific list of ops we delete that.=0D =0D My initial benchmarks shows no discernible impact of dropping the=0D plugin specific ops list.=0D =0D Fixes: Coverity 1459509=0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Richard Henderson =0D Cc: Peter Maydell =0D Message-Id: <20210917162332.3511179-12-alex.bennee@linaro.org>=0D =0D =0D Commit: 9b89cdb2a5064a87b8a7172fa1748d46aa37a9df=0D https://github.com/qemu/qemu/commit/9b89cdb2a5064a87b8a7172fa1748d4= 6aa37a9df=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D =0D Log Message:=0D -----------=0D .github: move repo lockdown to the v2 configuration=0D =0D I was getting prompted by GitHub for new permissions but it turns out=0D per https://github.com/dessant/repo-lockdown/issues/6:=0D =0D Repo Lockdown has been rewritten for GitHub Actions, offering new=0D features and better control over your automation presets. The legacy=0D= GitHub App has been deprecated, and the public instance of the app=0D has been shut down.=0D =0D So this is what I've done. As the issues tab is disabled I've removed=0D the handling for issues from the new version.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Willian Rampazzo =0D Message-Id: <20211004154308.2114870-1-alex.bennee@linaro.org>=0D =0D =0D Commit: 17888749ba0fb06694de5efe0b941f16a0fba6fa=0D https://github.com/qemu/qemu/commit/17888749ba0fb06694de5efe0b941f1= 6a0fba6fa=0D Author: Alex Benn=C3=A9e =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D =0D Log Message:=0D -----------=0D tests/docker: add a debian-native image and make available=0D =0D This image is intended for building whatever the native versions of=0D QEMU are for the host architecture. This will hopefully be an aid for=0D 3rd parties who want to be able to build QEMU themselves without=0D redoing all the dependencies themselves.=0D =0D We disable the registry because we currently don't have multi-arch=0D support there.=0D =0D Signed-off-by: Alex Benn=C3=A9e =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Anders Roxell =0D Acked-by: Willian Rampazzo =0D Message-Id: <20210922151528.2192966-1-alex.bennee@linaro.org>=0D =0D =0D Commit: bfd9a76f9c143d450ab5545dedfa74364b39fc56=0D https://github.com/qemu/qemu/commit/bfd9a76f9c143d450ab5545dedfa743= 64b39fc56=0D Author: Richard Henderson =0D Date: 2021-10-12 (Tue, 12 Oct 2021)=0D =0D Changed paths:=0D R .github/lockdown.yml=0D A .github/workflows/lockdown.yml=0D M .gitlab-ci.d/cirrus.yml=0D M .gitlab-ci.d/cirrus/build.yml=0D M .gitlab-ci.d/container-cross.yml=0D M .gitlab-ci.d/crossbuilds.yml=0D M .gitlab-ci.d/static_checks.yml=0D M .travis.yml=0D M accel/tcg/plugin-gen.c=0D M configure=0D M include/tcg/tcg.h=0D M plugins/qemu-plugins.symbols=0D M target/s390x/tcg/translate.c=0D M tests/docker/Makefile.include=0D M tests/docker/common.rc=0D A tests/docker/dockerfiles/debian-native.docker=0D M tests/docker/dockerfiles/debian-riscv64-cross.docker=0D M tests/tcg/multiarch/Makefile.target=0D R tests/tcg/multiarch/float_helpers.c=0D A tests/tcg/multiarch/libs/float_helpers.c=0D R tests/tcg/multiarch/linux-test.c=0D A tests/tcg/multiarch/linux/linux-test.c=0D M tests/tcg/multiarch/sha1.c=0D M tests/tcg/x86_64/Makefile.target=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-= 2' into staging=0D =0D Some testing and plugin updates:=0D =0D - don't override the test compiler when specified=0D - split some multiarch tests by guest OS=0D - add riscv64 docker image and cross-compile tests=0D - drop release tarball test from Travis=0D - skip check-patch on master repo=0D - fix passing of TEST_TARGETS to cirrus=0D - fix missing symbols in plugins=0D - ensure s390x insn start ops precede plugin instrumentation=0D - refactor plugin instruction boundary detection=0D - update github repo lockdown=0D - add a debian-native test image for multi-arch builds=0D =0D # gpg: Signature made Tue 12 Oct 2021 02:35:00 AM PDT=0D # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2= A44=0D # gpg: Good signature from "Alex Benn=C3=A9e (Master Work Key) " [full]=0D =0D * remotes/stsquad/tags/pull-for-6.2-121021-2:=0D tests/docker: add a debian-native image and make available=0D .github: move repo lockdown to the v2 configuration=0D accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is vali= d=0D target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start=0D plugins/: Add missing functions to symbol list=0D gitlab: fix passing of TEST_TARGETS env to cirrus=0D gitlab: skip the check-patch job on the upstream repo=0D travis.yml: Remove the "Release tarball" job=0D gitlab: Add cross-riscv64-system, cross-riscv64-user=0D tests/docker: promote debian-riscv64-cross to a full image=0D tests/tcg: move some multiarch files and make conditional=0D tests/tcg/sha1: remove endian include=0D configure: don't override the selected host test compiler if defined=0D= =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/81d8537cb297...bfd9a76f9c14= =0D From MAILER-DAEMON Tue Oct 12 12:38:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maKnW-0002ZT-Ul for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 12:38:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maKnV-0002VV-Pa for qemu-commits@nongnu.org; Tue, 12 Oct 2021 12:38:37 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:56895 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maKnS-0005ok-GB for qemu-commits@nongnu.org; Tue, 12 Oct 2021 12:38:37 -0400 Received: from github.com (hubbernetes-node-8e6ce34.ash1-iad.github.net [10.56.102.69]) by smtp.github.com (Postfix) with ESMTPA id CB1315E06BF for ; Tue, 12 Oct 2021 09:38:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634056713; bh=Pi1pFwHu1R2U9RFCjxb3la8JU7uvw1xB+t8GiuUEops=; h=Date:From:To:Subject:From; b=0sWVvYZoA5bwnxEDkXQ+jAumXN9qNtey8X1h0odFpWj+3klQIlUVCDKH9r+W+0KZl BCeNTV8tRzsMZsMEtSqUzHMRoclRDzpvZ2+eqPQEJlY8mfbkaViV+YjeXz9/ZXoeQQ jzNb9BLQ1hQy3caK9VIe3FFuyXW+K7ZnWiCM2Ybk= Date: Tue, 12 Oct 2021 09:38:33 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e770b8: pc-bios: Update hppa-firmware.img X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 16:38:38 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: e770b8cf76083cc51497b854e73f0a9bb92d1bc7 https://github.com/qemu/qemu/commit/e770b8cf76083cc51497b854e73f0a9bb92d1bc7 Author: Helge Deller Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M pc-bios/hppa-firmware.img M roms/seabios-hppa Log Message: ----------- pc-bios: Update hppa-firmware.img Update SeaBIOS to seabios-hppa-v2 Changes in seabios-hppa: * Include all latest upstream SeaBIOS patches * add support for the qemu "bootindex" parameter * add support for the qemu "-boot order=g-m" parameter to choose SCSI ID Signed-off-by: Helge Deller Message-Id: Signed-off-by: Richard Henderson Commit: 8be1d4ed9838f807c63695753b30865f6edc4a5c https://github.com/qemu/qemu/commit/8be1d4ed9838f807c63695753b30865f6edc4a5c Author: Richard Henderson Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M pc-bios/hppa-firmware.img M roms/seabios-hppa Log Message: ----------- Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20211012' into staging seabios-hppa update # gpg: Signature made Tue 12 Oct 2021 09:28:12 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson " [ultimate] * remotes/rth/tags/pull-hppa-20211012: pc-bios: Update hppa-firmware.img Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/bfd9a76f9c14...8be1d4ed9838 From MAILER-DAEMON Tue Oct 12 14:39:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maMgr-0000TG-N3 for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 14:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maMgo-0000Rd-BP for qemu-commits@nongnu.org; Tue, 12 Oct 2021 14:39:51 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:33019 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maMgm-00057G-M3 for qemu-commits@nongnu.org; Tue, 12 Oct 2021 14:39:49 -0400 Received: from github.com (hubbernetes-node-1804551.va3-iad.github.net [10.48.200.34]) by smtp.github.com (Postfix) with ESMTPA id 012A15C03EE for ; Tue, 12 Oct 2021 11:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634063988; bh=avCzoR2fMkSyAw5ue5p/1bh4+oiVtWuRm/V05KpOuKs=; h=Date:From:To:Subject:From; b=e8/+iw6LwlDv4lPfnWUtPdnyY8nb8zmn2wDgigt7sTqnmcYc+4F5i2STSdzLyBhbE Aob76bA4WFFSF1uKu27+9dPo+IgFnF5BS04WSg0sVaptn3+tTiNldjGxTVSTyCcc6i D/+5ouNtDYj6+GqkP+ilQ4sW5wwAbCEJpG8aIOhM= Date: Tue, 12 Oct 2021 11:39:47 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e770b8: pc-bios: Update hppa-firmware.img X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 18:39:51 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: e770b8cf76083cc51497b854e73f0a9bb92d1bc7 https://github.com/qemu/qemu/commit/e770b8cf76083cc51497b854e73f0a9bb92d1bc7 Author: Helge Deller Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M pc-bios/hppa-firmware.img M roms/seabios-hppa Log Message: ----------- pc-bios: Update hppa-firmware.img Update SeaBIOS to seabios-hppa-v2 Changes in seabios-hppa: * Include all latest upstream SeaBIOS patches * add support for the qemu "bootindex" parameter * add support for the qemu "-boot order=g-m" parameter to choose SCSI ID Signed-off-by: Helge Deller Message-Id: Signed-off-by: Richard Henderson Commit: 8be1d4ed9838f807c63695753b30865f6edc4a5c https://github.com/qemu/qemu/commit/8be1d4ed9838f807c63695753b30865f6edc4a5c Author: Richard Henderson Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M pc-bios/hppa-firmware.img M roms/seabios-hppa Log Message: ----------- Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20211012' into staging seabios-hppa update # gpg: Signature made Tue 12 Oct 2021 09:28:12 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson " [ultimate] * remotes/rth/tags/pull-hppa-20211012: pc-bios: Update hppa-firmware.img Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/bfd9a76f9c14...8be1d4ed9838 From MAILER-DAEMON Tue Oct 12 19:09:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maQtu-0008Dg-KF for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 19:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maQtn-0008CA-VU for qemu-commits@nongnu.org; Tue, 12 Oct 2021 19:09:32 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:53405) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maQtj-0005qR-0i for qemu-commits@nongnu.org; Tue, 12 Oct 2021 19:09:31 -0400 Received: from github.com (hubbernetes-node-0faa5d3.ac4-iad.github.net [10.52.210.19]) by smtp.github.com (Postfix) with ESMTPA id 520B7600684 for ; Tue, 12 Oct 2021 16:09:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634080166; bh=mFKb7rHZkuVSEKR+2Ewxi1hYjSSeV6f97D62rJvEq7I=; h=Date:From:To:Subject:From; b=I6EsGJr9EHZOMvb18DXY2KmsFRGDLpY02+qPbjal2DGzwxR0eBWEJFW+2if5o0f6G SGpjShy0R//2K+kYWuc5B7Ur0IBLUMy2cSO72l384XnS+op+Jc/hQFAAeYMy4KTSBd KQXZD9x01Ktgsc7wIik7MdJ2Lc7KEy/zf0ChoGXM= Date: Tue, 12 Oct 2021 16:09:26 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 025720: python/aqmp: add greeting property to QMPClient X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 23:09:34 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 0257209a09793bfaf1b662faad5558e7011e748a https://github.com/qemu/qemu/commit/0257209a09793bfaf1b662faad5558e7011e748a Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/qmp_client.py Log Message: ----------- python/aqmp: add greeting property to QMPClient Expose the greeting as a read-only property of QMPClient so it can be retrieved at-will. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-2-jsnow@redhat.com Signed-off-by: John Snow Commit: 16cce725ed87e3ed5901c93e61514840c989216a https://github.com/qemu/qemu/commit/16cce725ed87e3ed5901c93e61514840c989216a Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/events.py Log Message: ----------- python/aqmp: add .empty() method to EventListener Synchronous clients may want to know if they're about to block waiting for an event or not. A method such as this is necessary to implement a compatible interface for the old QEMUMonitorProtocol using the new async internals. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-3-jsnow@redhat.com Signed-off-by: John Snow Commit: 6bfebc7306e42910cd33553d9ed385ef475d8196 https://github.com/qemu/qemu/commit/6bfebc7306e42910cd33553d9ed385ef475d8196 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/events.py Log Message: ----------- python/aqmp: Return cleared events from EventListener.clear() This serves two purposes: (1) It is now possible to discern whether or not clear() removed any event(s) from the queue with absolute certainty, and (2) It is now very easy to get a List of all pending events in one chunk, which is useful for the sync bridge. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-4-jsnow@redhat.com Signed-off-by: John Snow Commit: 6e2f6ec5615f50c38e21542bb66bb690a289cbfc https://github.com/qemu/qemu/commit/6e2f6ec5615f50c38e21542bb66bb690a289cbfc Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/qmp_client.py Log Message: ----------- python/aqmp: add send_fd_scm Add an implementation for send_fd_scm to the async QMP implementation. Like socket_scm_helper mentions, a non-empty payload is required for QEMU to process the ancillary data. A space is most useful because it does not disturb the parsing of subsequent JSON objects. A note on "voiding the warranty": Python 3.11 removes support for calling sendmsg directly from a transport's socket. There is no other interface for doing this, our use case is, I suspect, "quite unique". As far as I can tell, this is safe to do -- send_fd_scm is a synchronous function and we can be guaranteed that the async coroutines will *not* be running when it is invoked. In testing, it works correctly. I investigated quite thoroughly the possibility of creating my own asyncio Transport (The class that ultimately manages the raw socket object) so that I could manage the socket myself, but this is so wildly invasive and unportable I scrapped the idea. It would involve a lot of copy-pasting of various python utilities and classes just to re-create the same infrastructure, and for extremely little benefit. Nah. Just boldly void the warranty instead, while I try to follow up on https://bugs.python.org/issue43232 Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-5-jsnow@redhat.com Signed-off-by: John Snow Commit: 58026b11f36f9a19fd35fdfbfa50be7bd78e70a5 https://github.com/qemu/qemu/commit/58026b11f36f9a19fd35fdfbfa50be7bd78e70a5 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/models.py Log Message: ----------- python/aqmp: Add dict conversion method to Greeting object The iotests interface expects to return the greeting as a dict; AQMP offers it as a rich object. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-6-jsnow@redhat.com Signed-off-by: John Snow Commit: 3e55dc35b8ed8cea53ef2604874d2fe882fbadc1 https://github.com/qemu/qemu/commit/3e55dc35b8ed8cea53ef2604874d2fe882fbadc1 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/protocol.py Log Message: ----------- python/aqmp: Reduce severity of EOFError-caused loop terminations When we encounter an EOFError, we don't know if it's an "error" in the perspective of the user of the library yet. Therefore, we should not log it as an error. Reduce the severity of this logging message to "INFO" to indicate that it's something that we expect to occur during the normal operation of the library. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-7-jsnow@redhat.com Signed-off-by: John Snow Commit: 3a3d84f5ec0bca2586a1a83691182576a9447130 https://github.com/qemu/qemu/commit/3a3d84f5ec0bca2586a1a83691182576a9447130 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/__init__.py Log Message: ----------- python/aqmp: Disable logging messages by default AQMP is a library, and ideally it should not print error diagnostics unless a user opts into seeing them. By default, Python will print all WARNING, ERROR or CRITICAL messages to screen if no logging configuration has been created by a client application. In AQMP's case, ERROR logging statements are used to report additional detail about runtime failures that will also eventually be reported to the client library via an Exception, so these messages should not be rendered by default. (Why bother to have them at all, then? In async contexts, there may be multiple Exceptions and we are only able to report one of them back to the client application. It is not reasonably easy to predict ahead of time if one or more of these Exceptions will be squelched. Therefore, it's useful to log intermediate failures to help make sense of the ultimate, resulting failure.) Add a NullHandler that will suppress these messages until a client application opts into logging via logging.basicConfig or similar. Note that upon calling basicConfig(), this handler will *not* suppress these messages from being displayed by the client's configuration. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-8-jsnow@redhat.com Signed-off-by: John Snow Commit: d911accf0a88070120f7cc71c065fb797484d9b7 https://github.com/qemu/qemu/commit/d911accf0a88070120f7cc71c065fb797484d9b7 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/qmp/__init__.py M python/qemu/qmp/qmp_shell.py Log Message: ----------- python/qmp: clear events on get_events() call All callers in the tree *already* clear the events after a call to get_events(). Do it automatically instead and update callsites to remove the manual clear call. These semantics are quite a bit easier to emulate with async QMP, and nobody appears to be abusing some emergent properties of what happens if you decide not to clear them, so let's dial down to the dumber, simpler thing. Specifically: callers of clear() right after a call to get_events() are more likely expressing their desire to not see any events they just retrieved, whereas callers of clear_events() not in relation to a recent call to pull_event/get_events are likely expressing their desire to simply drop *all* pending events straight onto the floor. In the sync world, this is safe enough; in the async world it's nearly impossible to promise that nothing happens between getting and clearing the events. Making the retrieval also clear the queue is vastly simpler. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-9-jsnow@redhat.com Signed-off-by: John Snow Commit: 514d00df5f44f220d0b97cc71323275067d3e60e https://github.com/qemu/qemu/commit/514d00df5f44f220d0b97cc71323275067d3e60e Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/qmp/__init__.py Log Message: ----------- python/qmp: add send_fd_scm directly to QEMUMonitorProtocol It turns out you can do this directly from Python ... and because of this, you don't need to worry about setting the inheritability of the fds or spawning another process. Doing this is helpful because it allows QEMUMonitorProtocol to keep its file descriptor and socket object as private implementation details. /that/ is helpful in turn because it allows me to write a compatible, alternative implementation. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-10-jsnow@redhat.com Signed-off-by: John Snow Commit: c163c723ef92d0f629d015902396f2c67328b2e5 https://github.com/qemu/qemu/commit/c163c723ef92d0f629d015902396f2c67328b2e5 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/machine/qtest.py M tests/Makefile.include M tests/meson.build M tests/qemu-iotests/iotests.py R tests/qemu-iotests/meson.build R tests/qemu-iotests/socket_scm_helper.c M tests/qemu-iotests/testenv.py Log Message: ----------- python, iotests: remove socket_scm_helper It's not used anymore, now. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-11-jsnow@redhat.com Signed-off-by: John Snow Commit: ee26ce674a93c824713542cec3b6a9ca85459165 https://github.com/qemu/qemu/commit/ee26ce674a93c824713542cec3b6a9ca85459165 Author: Richard Henderson Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/__init__.py M python/qemu/aqmp/events.py M python/qemu/aqmp/models.py M python/qemu/aqmp/protocol.py M python/qemu/aqmp/qmp_client.py M python/qemu/machine/machine.py M python/qemu/machine/qtest.py M python/qemu/qmp/__init__.py M python/qemu/qmp/qmp_shell.py M tests/Makefile.include M tests/meson.build M tests/qemu-iotests/iotests.py R tests/qemu-iotests/meson.build R tests/qemu-iotests/socket_scm_helper.c M tests/qemu-iotests/testenv.py Log Message: ----------- Merge remote-tracking branch 'remotes/jsnow/tags/python-pull-request' into staging Pull request # gpg: Signature made Tue 12 Oct 2021 02:36:07 PM PDT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) " [full] * remotes/jsnow/tags/python-pull-request: python, iotests: remove socket_scm_helper python/qmp: add send_fd_scm directly to QEMUMonitorProtocol python/qmp: clear events on get_events() call python/aqmp: Disable logging messages by default python/aqmp: Reduce severity of EOFError-caused loop terminations python/aqmp: Add dict conversion method to Greeting object python/aqmp: add send_fd_scm python/aqmp: Return cleared events from EventListener.clear() python/aqmp: add .empty() method to EventListener python/aqmp: add greeting property to QMPClient Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/8be1d4ed9838...ee26ce674a93 From MAILER-DAEMON Tue Oct 12 21:06:28 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maSiy-00068X-Ix for mharc-qemu-commits@gnu.org; Tue, 12 Oct 2021 21:06:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSir-00065N-KY for qemu-commits@nongnu.org; Tue, 12 Oct 2021 21:06:22 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:50837 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSin-00079e-VG for qemu-commits@nongnu.org; Tue, 12 Oct 2021 21:06:21 -0400 Received: from github.com (hubbernetes-node-87c3d84.va3-iad.github.net [10.48.221.15]) by smtp.github.com (Postfix) with ESMTPA id 552683401FD for ; Tue, 12 Oct 2021 18:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634087177; bh=VeYluBu5fwNg5eM5Df4LSqBQ0nmrMwuTnPkIC+CSunk=; h=Date:From:To:Subject:From; b=XCefkdL93+ib4yHLWBguDCb5eD2aApfSTx+MnXvBAhame/iEj7PIjIly3HqMHw2KX dE1MBNN5V6Sl3Sxaa7nz6iVZsfZiqYqB4gR0tH+CSVIavtiWb45MujgwoWKg4BhPs3 Z1UE8t4mkqBJfcH381lwWQ+ofIszzBv/XXIJWK8o= Date: Tue, 12 Oct 2021 18:06:17 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 025720: python/aqmp: add greeting property to QMPClient X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 01:06:22 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: 0257209a09793bfaf1b662faad5558e7011e748a https://github.com/qemu/qemu/commit/0257209a09793bfaf1b662faad5558e7011e748a Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/qmp_client.py Log Message: ----------- python/aqmp: add greeting property to QMPClient Expose the greeting as a read-only property of QMPClient so it can be retrieved at-will. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-2-jsnow@redhat.com Signed-off-by: John Snow Commit: 16cce725ed87e3ed5901c93e61514840c989216a https://github.com/qemu/qemu/commit/16cce725ed87e3ed5901c93e61514840c989216a Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/events.py Log Message: ----------- python/aqmp: add .empty() method to EventListener Synchronous clients may want to know if they're about to block waiting for an event or not. A method such as this is necessary to implement a compatible interface for the old QEMUMonitorProtocol using the new async internals. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-3-jsnow@redhat.com Signed-off-by: John Snow Commit: 6bfebc7306e42910cd33553d9ed385ef475d8196 https://github.com/qemu/qemu/commit/6bfebc7306e42910cd33553d9ed385ef475d8196 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/events.py Log Message: ----------- python/aqmp: Return cleared events from EventListener.clear() This serves two purposes: (1) It is now possible to discern whether or not clear() removed any event(s) from the queue with absolute certainty, and (2) It is now very easy to get a List of all pending events in one chunk, which is useful for the sync bridge. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-4-jsnow@redhat.com Signed-off-by: John Snow Commit: 6e2f6ec5615f50c38e21542bb66bb690a289cbfc https://github.com/qemu/qemu/commit/6e2f6ec5615f50c38e21542bb66bb690a289cbfc Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/qmp_client.py Log Message: ----------- python/aqmp: add send_fd_scm Add an implementation for send_fd_scm to the async QMP implementation. Like socket_scm_helper mentions, a non-empty payload is required for QEMU to process the ancillary data. A space is most useful because it does not disturb the parsing of subsequent JSON objects. A note on "voiding the warranty": Python 3.11 removes support for calling sendmsg directly from a transport's socket. There is no other interface for doing this, our use case is, I suspect, "quite unique". As far as I can tell, this is safe to do -- send_fd_scm is a synchronous function and we can be guaranteed that the async coroutines will *not* be running when it is invoked. In testing, it works correctly. I investigated quite thoroughly the possibility of creating my own asyncio Transport (The class that ultimately manages the raw socket object) so that I could manage the socket myself, but this is so wildly invasive and unportable I scrapped the idea. It would involve a lot of copy-pasting of various python utilities and classes just to re-create the same infrastructure, and for extremely little benefit. Nah. Just boldly void the warranty instead, while I try to follow up on https://bugs.python.org/issue43232 Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-5-jsnow@redhat.com Signed-off-by: John Snow Commit: 58026b11f36f9a19fd35fdfbfa50be7bd78e70a5 https://github.com/qemu/qemu/commit/58026b11f36f9a19fd35fdfbfa50be7bd78e70a5 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/models.py Log Message: ----------- python/aqmp: Add dict conversion method to Greeting object The iotests interface expects to return the greeting as a dict; AQMP offers it as a rich object. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-6-jsnow@redhat.com Signed-off-by: John Snow Commit: 3e55dc35b8ed8cea53ef2604874d2fe882fbadc1 https://github.com/qemu/qemu/commit/3e55dc35b8ed8cea53ef2604874d2fe882fbadc1 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/protocol.py Log Message: ----------- python/aqmp: Reduce severity of EOFError-caused loop terminations When we encounter an EOFError, we don't know if it's an "error" in the perspective of the user of the library yet. Therefore, we should not log it as an error. Reduce the severity of this logging message to "INFO" to indicate that it's something that we expect to occur during the normal operation of the library. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-7-jsnow@redhat.com Signed-off-by: John Snow Commit: 3a3d84f5ec0bca2586a1a83691182576a9447130 https://github.com/qemu/qemu/commit/3a3d84f5ec0bca2586a1a83691182576a9447130 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/__init__.py Log Message: ----------- python/aqmp: Disable logging messages by default AQMP is a library, and ideally it should not print error diagnostics unless a user opts into seeing them. By default, Python will print all WARNING, ERROR or CRITICAL messages to screen if no logging configuration has been created by a client application. In AQMP's case, ERROR logging statements are used to report additional detail about runtime failures that will also eventually be reported to the client library via an Exception, so these messages should not be rendered by default. (Why bother to have them at all, then? In async contexts, there may be multiple Exceptions and we are only able to report one of them back to the client application. It is not reasonably easy to predict ahead of time if one or more of these Exceptions will be squelched. Therefore, it's useful to log intermediate failures to help make sense of the ultimate, resulting failure.) Add a NullHandler that will suppress these messages until a client application opts into logging via logging.basicConfig or similar. Note that upon calling basicConfig(), this handler will *not* suppress these messages from being displayed by the client's configuration. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Reviewed-by: Eric Blake Message-id: 20210923004938.3999963-8-jsnow@redhat.com Signed-off-by: John Snow Commit: d911accf0a88070120f7cc71c065fb797484d9b7 https://github.com/qemu/qemu/commit/d911accf0a88070120f7cc71c065fb797484d9b7 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/qmp/__init__.py M python/qemu/qmp/qmp_shell.py Log Message: ----------- python/qmp: clear events on get_events() call All callers in the tree *already* clear the events after a call to get_events(). Do it automatically instead and update callsites to remove the manual clear call. These semantics are quite a bit easier to emulate with async QMP, and nobody appears to be abusing some emergent properties of what happens if you decide not to clear them, so let's dial down to the dumber, simpler thing. Specifically: callers of clear() right after a call to get_events() are more likely expressing their desire to not see any events they just retrieved, whereas callers of clear_events() not in relation to a recent call to pull_event/get_events are likely expressing their desire to simply drop *all* pending events straight onto the floor. In the sync world, this is safe enough; in the async world it's nearly impossible to promise that nothing happens between getting and clearing the events. Making the retrieval also clear the queue is vastly simpler. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-9-jsnow@redhat.com Signed-off-by: John Snow Commit: 514d00df5f44f220d0b97cc71323275067d3e60e https://github.com/qemu/qemu/commit/514d00df5f44f220d0b97cc71323275067d3e60e Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/qmp/__init__.py Log Message: ----------- python/qmp: add send_fd_scm directly to QEMUMonitorProtocol It turns out you can do this directly from Python ... and because of this, you don't need to worry about setting the inheritability of the fds or spawning another process. Doing this is helpful because it allows QEMUMonitorProtocol to keep its file descriptor and socket object as private implementation details. /that/ is helpful in turn because it allows me to write a compatible, alternative implementation. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-10-jsnow@redhat.com Signed-off-by: John Snow Commit: c163c723ef92d0f629d015902396f2c67328b2e5 https://github.com/qemu/qemu/commit/c163c723ef92d0f629d015902396f2c67328b2e5 Author: John Snow Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/machine/machine.py M python/qemu/machine/qtest.py M tests/Makefile.include M tests/meson.build M tests/qemu-iotests/iotests.py R tests/qemu-iotests/meson.build R tests/qemu-iotests/socket_scm_helper.c M tests/qemu-iotests/testenv.py Log Message: ----------- python, iotests: remove socket_scm_helper It's not used anymore, now. Signed-off-by: John Snow Reviewed-by: Hanna Reitz Reviewed-by: Paolo Bonzini Message-id: 20210923004938.3999963-11-jsnow@redhat.com Signed-off-by: John Snow Commit: ee26ce674a93c824713542cec3b6a9ca85459165 https://github.com/qemu/qemu/commit/ee26ce674a93c824713542cec3b6a9ca85459165 Author: Richard Henderson Date: 2021-10-12 (Tue, 12 Oct 2021) Changed paths: M python/qemu/aqmp/__init__.py M python/qemu/aqmp/events.py M python/qemu/aqmp/models.py M python/qemu/aqmp/protocol.py M python/qemu/aqmp/qmp_client.py M python/qemu/machine/machine.py M python/qemu/machine/qtest.py M python/qemu/qmp/__init__.py M python/qemu/qmp/qmp_shell.py M tests/Makefile.include M tests/meson.build M tests/qemu-iotests/iotests.py R tests/qemu-iotests/meson.build R tests/qemu-iotests/socket_scm_helper.c M tests/qemu-iotests/testenv.py Log Message: ----------- Merge remote-tracking branch 'remotes/jsnow/tags/python-pull-request' into staging Pull request # gpg: Signature made Tue 12 Oct 2021 02:36:07 PM PDT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) " [full] * remotes/jsnow/tags/python-pull-request: python, iotests: remove socket_scm_helper python/qmp: add send_fd_scm directly to QEMUMonitorProtocol python/qmp: clear events on get_events() call python/aqmp: Disable logging messages by default python/aqmp: Reduce severity of EOFError-caused loop terminations python/aqmp: Add dict conversion method to Greeting object python/aqmp: add send_fd_scm python/aqmp: Return cleared events from EventListener.clear() python/aqmp: add .empty() method to EventListener python/aqmp: add greeting property to QMPClient Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/8be1d4ed9838...ee26ce674a93 From MAILER-DAEMON Wed Oct 13 09:58:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maemJ-000349-Rk for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 09:58:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maemG-00031V-Nz for qemu-commits@nongnu.org; Wed, 13 Oct 2021 09:58:40 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:60811) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maemC-00020K-5h for qemu-commits@nongnu.org; Wed, 13 Oct 2021 09:58:39 -0400 Received: from github.com (hubbernetes-node-941d807.ac4-iad.github.net [10.52.207.84]) by smtp.github.com (Postfix) with ESMTPA id 16BB360075B for ; Wed, 13 Oct 2021 06:58:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634133509; bh=ufb02wjWgxLoet0m0wxCoJKgfwzf2L3+u4nFMA32TXQ=; h=Date:From:To:Subject:From; b=jn6q12BFxuUeBpzPsvBxz0c7J00nvxMOf1LRH67/nauF5FZaWhOan6kpji3TQ4Tob kVHw65G6OVIhsPocu8UflF0ZQh9COuxSKvgAU7T37/aiTrTjnxrGWkBxBb/afClYrv jcRRYZESWLkLeoMKPPLKoLqKx4UkaLsEww+P1IB0= Date: Wed, 13 Oct 2021 06:58:29 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 601454: MAINTAINERS: Add myself as reviewer of the 'Memory... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 13:58:41 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 60145485232cf1c4f3e9314ddb8a99d0473d785a=0D https://github.com/qemu/qemu/commit/60145485232cf1c4f3e9314ddb8a99d= 0473d785a=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Add myself as reviewer of the 'Memory API'=0D =0D Having developed interest with the Memory API,=0D volunteer to review the patches.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: David Hildenbrand =0D Message-Id: <20211007091949.319404-1-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8009806ec81ff2caa711c99e87ca394f9ba50565=0D https://github.com/qemu/qemu/commit/8009806ec81ff2caa711c99e87ca394= f9ba50565=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/Makefile.include=0D =0D Log Message:=0D -----------=0D tests: add missing dependency for check-block=0D =0D qemu-iotests run qemu-storage-daemon, make sure it is up to date.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 097a5f19a357b6bc699a05ccd119bfa89ea409cc=0D https://github.com/qemu/qemu/commit/097a5f19a357b6bc699a05ccd119bfa= 89ea409cc=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/Makefile.include=0D =0D Log Message:=0D -----------=0D build: fix "make check" without earlier "make"=0D =0D "make check", if not preceded by "make", will not build the tools=0D needed by qemu-iotests. This happens because qemu-iotests, aka=0D "make check-block", is not yet part of meson.build.=0D =0D While at it, remove the reference to the now-dead QEMU_IOTESTS_HELPERS-y=0D= variable.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ecc00666a020368ec2c3712c40386dc7ea75a8a9=0D https://github.com/qemu/qemu/commit/ecc00666a020368ec2c3712c40386dc= 7ea75a8a9=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/testrunner.py=0D =0D Log Message:=0D -----------=0D qemu-iotests: flush after every test=0D =0D This makes it possible to see what is happening, even if the output of=0D= "make check-block" is not sent to a tty (for example if it is sent to=0D grep or tee).=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 6bd17dccb63e152266cf7a7399931c9fe11bc8cf=0D https://github.com/qemu/qemu/commit/6bd17dccb63e152266cf7a7399931c9= fe11bc8cf=0D Author: Kacper S=C5=82omi=C5=84ski =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M util/compatfd.c=0D =0D Log Message:=0D -----------=0D util/compatfd.c: use libc signalfd wrapper instead of raw syscall=0D =0D This allows the use of native signalfd instead of the sigtimedwait=0D based emulation on systems other than Linux.=0D =0D Signed-off-by: Kacper S=C5=82omi=C5=84ski =0D= Message-Id: <20210905011621.200785-1-kacper.slominski72@gmail.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b50f6dc174cf391d725fca895d74c441b23e2e47=0D https://github.com/qemu/qemu/commit/b50f6dc174cf391d725fca895d74c44= 1b23e2e47=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/misc-target.json=0D =0D Log Message:=0D -----------=0D qapi/misc-target: Wrap long 'SEV Attestation Report' long lines=0D =0D Wrap long lines before 70 characters for legibility.=0D =0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-2-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 993e26058d10756f5e206742c20b0cd03a9cb973=0D https://github.com/qemu/qemu/commit/993e26058d10756f5e206742c20b0cd= 03a9cb973=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/misc-target.json=0D =0D Log Message:=0D -----------=0D qapi/misc-target: Group SEV QAPI definitions=0D =0D There is already a section with various SEV commands / types,=0D so move the SEV guest attestation together.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-3-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 02310f3a91470575a103857222d3a6e8acea338e=0D https://github.com/qemu/qemu/commit/02310f3a91470575a103857222d3a6e= 8acea338e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/kvm/meson.build=0D =0D Log Message:=0D -----------=0D target/i386/kvm: Introduce i386_softmmu_kvm Meson source set=0D =0D Introduce the i386_softmmu_kvm Meson source set to be able to=0D add features dependent on CONFIG_KVM.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-4-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 773ab6cb16b34272dc7eb8171824924c38dbeb90=0D https://github.com/qemu/qemu/commit/773ab6cb16b34272dc7eb8171824924= c38dbeb90=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/kvm/meson.build=0D R accel/kvm/sev-stub.c=0D M target/i386/kvm/meson.build=0D A target/i386/kvm/sev-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/kvm: Restrict SEV stubs to x86 architecture=0D =0D SEV is x86-specific, no need to add its stub to other=0D architectures. Move the stub file to target/i386/kvm/.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-5-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2c7233eb103adbf567778270b69950dd7a776c72=0D https://github.com/qemu/qemu/commit/2c7233eb103adbf567778270b69950d= d7a776c72=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Prefix QMP errors with 'SEV'=0D =0D Multiple errors might be reported to the monitor,=0D better to prefix the SEV ones so we can distinct them.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211007161716.453984-6-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9f885cac701325ebcbf7e4393aa9b21b32ec3c12=0D https://github.com/qemu/qemu/commit/9f885cac701325ebcbf7e4393aa9b21= b32ec3c12=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D target/i386/monitor: Return QMP error when SEV is not enabled for guest= =0D =0D If the management layer tries to inject a secret, it gets an empty=0D response in case the guest doesn't have SEV enabled, or the binary=0D is built without SEV:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "return": {=0D }=0D }=0D =0D Make it clearer by returning an error:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "error": {=0D "class": "GenericError",=0D "desc": "SEV not enabled for guest"=0D }=0D }=0D =0D Note: we will remove the sev_inject_launch_secret() stub in few commits,=0D= so we don't bother to add error_setg() there.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-7-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f83aeeaeba1cf3e25d6292d9cc12064bfe2e78ab=0D https://github.com/qemu/qemu/commit/f83aeeaeba1cf3e25d6292d9cc12064= bfe2e78ab=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D =0D Log Message:=0D -----------=0D target/i386/cpu: Add missing 'qapi/error.h' header=0D =0D Commit 00b81053244 ("target-i386: Remove assert_no_error usage")=0D forgot to add the "qapi/error.h" for &error_abort, add it now.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-8-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 40cbafe05bb8f463d9dc096985ceff5d2535dc56=0D https://github.com/qemu/qemu/commit/40cbafe05bb8f463d9dc096985ceff5= d2535dc56=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev_i386.h: Remove unused headers=0D =0D Declarations don't require these headers, remove them.=0D =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-9-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4e7189e112966ac3a7bc884273a8b07291c3012e=0D https://github.com/qemu/qemu/commit/4e7189e112966ac3a7bc884273a8b07= 291c3012e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Remove sev_get_me_mask()=0D =0D Unused dead code makes review harder, so remove it.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-10-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: d58d9f55a78a69730b4f1641f1c969d8585b970b=0D https://github.com/qemu/qemu/commit/d58d9f55a78a69730b4f1641f1c969d= 8585b970b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Mark unreachable code with g_assert_not_reached()=0D =0D The unique sev_encrypt_flash() invocation (in pc_system_flash_map)=0D is protected by the "if (sev_enabled())" check, so is not=0D reacheable.=0D Replace the abort() call in sev_es_save_reset_vector() by=0D g_assert_not_reached() which meaning is clearer.=0D =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-11-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ed84ae720d0b28c50906412a903e598f75ee1d7c=0D https://github.com/qemu/qemu/commit/ed84ae720d0b28c50906412a903e598= f75ee1d7c=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: sev_get_attestation_report use g_autofree=0D =0D Removes a whole bunch of g_free's and a goto.=0D =0D Signed-off-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Brijesh Singh =0D Message-Id: <20210603113017.34922-1-dgilbert@redhat.com>=0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-12-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2f573c415e8c84ec79aa6deb1d04fa9fccdebca7=0D https://github.com/qemu/qemu/commit/2f573c415e8c84ec79aa6deb1d04fa9= fccdebca7=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use g_autofree in sev_launch_get_measure()=0D =0D Use g_autofree to remove a pair of g_free/goto.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-13-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e24b3332042b7372f4817694aec48650dcfa68a0=0D https://github.com/qemu/qemu/commit/e24b3332042b7372f4817694aec4865= 0dcfa68a0=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/meson.build=0D M target/i386/sev-stub.c=0D A target/i386/sev-sysemu-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Restrict SEV to system emulation=0D =0D SEV is irrelevant on user emulation, so restrict it to sysemu.=0D Some stubs are still required because used in cpu.c by=0D x86_register_cpudef_types(), so move the sysemu specific stubs=0D to sev-sysemu-stub.c instead. This will allow us to simplify=0D monitor.c (which is not available in user emulation) in the=0D next commit.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-14-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 93777de3650e7db4b0434d63dd461505b85519f7=0D https://github.com/qemu/qemu/commit/93777de3650e7db4b0434d63dd46150= 5b85519f7=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/x86.c=0D M target/i386/cpu.c=0D M target/i386/kvm/kvm.c=0D M target/i386/monitor.c=0D M target/i386/sev-stub.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D A target/i386/sev.h=0D R target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Rename sev_i386.h -> sev.h=0D =0D SEV is a x86 specific feature, and the "sev_i386.h" header=0D is already in target/i386/. Rename it as "sev.h" to simplify.=0D =0D Patch created mechanically using:=0D =0D $ git mv target/i386/sev_i386.h target/i386/sev.h=0D $ sed -i s/sev_i386.h/sev.h/ $(git grep -l sev_i386.h)=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211007161716.453984-15-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: deae846f944a330e69109af8c807d6f2e66c95e6=0D https://github.com/qemu/qemu/commit/deae846f944a330e69109af8c807d6f= 2e66c95e6=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/pc_sysfw.c=0D R include/sysemu/sev.h=0D M target/i386/kvm/kvm.c=0D M target/i386/kvm/sev-stub.c=0D M target/i386/monitor.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Declare system-specific functions in 'sev.h'=0D =0D "sysemu/sev.h" is only used from x86-specific files. Let's move it=0D to include/hw/i386, and merge it with target/i386/sev.h.=0D =0D Suggested-by: Paolo Bonzini =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-16-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 02eacf31374152e6fb44554a4632f477d82dd9fc=0D https://github.com/qemu/qemu/commit/02eacf31374152e6fb44554a4632f47= 7d82dd9fc=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D M target/i386/meson.build=0D R target/i386/sev-stub.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Remove stubs by using code elision=0D =0D Only declare sev_enabled() and sev_es_enabled() when CONFIG_SEV is=0D set, to allow the compiler to elide unused code. Remove unnecessary=0D stubs.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Eric Blake =0D Message-Id: <20211007161716.453984-17-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3208de1cd23937254a456b95ef16658b68821a13=0D https://github.com/qemu/qemu/commit/3208de1cd23937254a456b95ef16658= b68821a13=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_attestation_report() to sev.c=0D =0D Move qmp_query_sev_attestation_report() from monitor.c to sev.c=0D and make sev_get_attestation_report() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-18-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 11a6ed0e77e8dd37ccea07575791b70c0410efea=0D https://github.com/qemu/qemu/commit/11a6ed0e77e8dd37ccea07575791b70= c0410efea=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_sev_inject_launch_secret() to sev.c=0D =0D Move qmp_sev_inject_launch_secret() from monitor.c to sev.c=0D and make sev_inject_launch_secret() static. We don't need the=0D stub anymore, remove it.=0D =0D Previously with binaries built without SEV, management layer=0D was getting an empty response:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "return": {=0D }=0D }=0D =0D Now the response is explicit, mentioning the feature is disabled:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "g= pa": 4294959104 }=0D }=0D {=0D "error": {=0D "class": "GenericError",=0D "desc": "this feature or command is not currently supported"=0D= }=0D }=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-19-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8371df29021241b43a7a9df6369fc70f649551a2=0D https://github.com/qemu/qemu/commit/8371df29021241b43a7a9df6369fc70= f649551a2=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_capabilities() to sev.c=0D =0D Move qmp_query_sev_capabilities() from monitor.c to sev.c=0D and make sev_get_capabilities() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-20-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0875a7038b8de0d79479a7d4662f0a9cdfa61940=0D https://github.com/qemu/qemu/commit/0875a7038b8de0d79479a7d4662f0a9= cdfa61940=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_launch_measure() to sev.c=0D =0D Move qmp_query_sev_launch_measure() from monitor.c to sev.c=0D and make sev_get_launch_measurement() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-21-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: aa3950182f902a48f60d7040069b092eb5aaae21=0D https://github.com/qemu/qemu/commit/aa3950182f902a48f60d7040069b092= eb5aaae21=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev() & hmp_info_sev() to sev.c=0D =0D Move qmp_query_sev() & hmp_info_sev()() from monitor.c to sev.c=0D and make sev_get_info() static. We don't need the stub anymore,=0D remove it. Add a stub for hmp_info_sev().=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-22-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cd35beb488c655a86da60d85949c026387187171=0D https://github.com/qemu/qemu/commit/cd35beb488c655a86da60d85949c026= 387187171=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M include/monitor/hmp-target.h=0D M include/monitor/hmp.h=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D monitor: Reduce hmp_info_sev() declaration=0D =0D While being conditionally used for TARGET_I386 in hmp-commands-info.hx,=0D= hmp_info_sev() is declared for all targets. Reduce its declaration=0D to target including "monitor/hmp-target.h". This is a minor cleanup.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-23-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8c9e7f8c8a6de68be1e31a645f7d76855fc219ba=0D https://github.com/qemu/qemu/commit/8c9e7f8c8a6de68be1e31a645f7d768= 55fc219ba=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Cover SEV-related files with X86/KVM section=0D =0D Complete the x86/KVM section with SEV-related files.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-24-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f1279fc15bf4315fb8e103e6eabaee014ce1f914=0D https://github.com/qemu/qemu/commit/f1279fc15bf4315fb8e103e6eabaee0= 14ce1f914=0D Author: Thomas Huth =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/qom.json=0D =0D Log Message:=0D -----------=0D qapi: Make some ObjectTypes depend on the build settings=0D =0D Some of the ObjectType entries already depend on CONFIG_* switches.=0D Some others also only make sense with certain configurations, but=0D are currently always listed in the ObjectType enum. Let's make them=0D depend on the correpsonding CONFIG_* switches, too, so that upper=0D layers (like libvirt) have a better way to determine which features=0D are available in QEMU.=0D =0D Signed-off-by: Thomas Huth =0D Reviewed-by: Markus Armbruster =0D Message-Id: <20210928160232.432980-1-thuth@redhat.com>=0D [Do the same for MemoryBackendEpcProperties. - Paolo]=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8e751e9c38e324737fd3d3aa0562f886313bba3c=0D https://github.com/qemu/qemu/commit/8e751e9c38e324737fd3d3aa0562f88= 6313bba3c=0D Author: Cole Robinson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/x86_64/system/kernel.ld=0D =0D Log Message:=0D -----------=0D tests: tcg: Fix PVH test with binutils 2.36+=0D =0D binutils started adding a .note.gnu.property ELF section which=0D makes the PVH test fail:=0D =0D TEST hello on x86_64=0D qemu-system-x86_64: Error loading uncompressed kernel without PVH ELF Not= e=0D =0D Discard .note.gnu* while keeping the PVH .note bits intact.=0D =0D This also strips the build-id note, so drop the related comment.=0D =0D Signed-off-by: Cole Robinson =0D Message-Id: <5ab2a54c262c61f64c22dbb49ade3e2db8a740bb.1633708346.git.crob= inso@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: dec490db8b5c98d60814d07c23ddf70708a56d6e=0D https://github.com/qemu/qemu/commit/dec490db8b5c98d60814d07c23ddf70= 708a56d6e=0D Author: Alexander Graf =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/hvf/hvf-accel-ops.c=0D =0D Log Message:=0D -----------=0D hvf: Determine slot count from struct layout=0D =0D We can handle up to a static amount of memory slots, capped by the size o= f=0D an internal array.=0D =0D Let's make sure that array size is the only source of truth for the numbe= r=0D of elements in that array.=0D =0D Signed-off-by: Alexander Graf =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211008054616.43828-1-agraf@csgraf.de>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a821186ec02ecf5ac4949ed42410bf2095bcea66=0D https://github.com/qemu/qemu/commit/a821186ec02ecf5ac4949ed42410bf2= 095bcea66=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Cover SGX documentation file with X86/KVM section=0D =0D Cc: Yang Zhong =0D Cc: Paolo Bonzini =0D Cc: Marcelo Tosatti =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-2-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 05fc8db720a2effad2fe523ab45c1ce5f8f32379=0D https://github.com/qemu/qemu/commit/05fc8db720a2effad2fe523ab45c1ce= 5f8f32379=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M include/hw/i386/sgx-epc.h=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Have sgx_epc_get_section() return a boolean=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-3-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 021658566b71e138db46434849f0556bab3fc30b=0D https://github.com/qemu/qemu/commit/021658566b71e138db46434849f0556= bab3fc30b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M include/hw/i386/sgx.h=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Move qmp_query_sgx_capabilities() to hw/i386/sgx.c=0D =0D Move qmp_query_sgx_capabilities() from target/i386/monitor.c to=0D hw/i386/sgx.c, removing the sgx_get_capabilities() indirection.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-4-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 6e81733e27a250af7507c3dd5ae945c473ab0d6b=0D https://github.com/qemu/qemu/commit/6e81733e27a250af7507c3dd5ae945c= 473ab0d6b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D R include/hw/i386/sgx.h=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Move qmp_query_sgx() and hmp_info_sgx() to hw/i386/sgx.c=0D= =0D Move qmp_query_sgx() and hmp_info_sgx() from target/i386/monitor.c=0D to hw/i386/sgx.c, removing the sgx_get_info() indirection and the=0D "hw/i386/sgx.h" header.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-5-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b71803a74612cc73eee82681f942a083038642ba=0D https://github.com/qemu/qemu/commit/b71803a74612cc73eee82681f942a08= 3038642ba=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/misc/applesmc.c=0D =0D Log Message:=0D -----------=0D Revert "hw/misc: applesmc: use host osk as default on macs"=0D =0D This reverts commit 93ddefbc3c909bb6c3b76086f1dfc8ad98dd3725.=0D The commit included code under the APSL 2.0, which is incompatible=0D with the GPL v2.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69520261204b9a1769134ed24b92cc0fa8445951=0D https://github.com/qemu/qemu/commit/69520261204b9a1769134ed24b92cc0= fa8445951=0D Author: Markus Armbruster =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M softmmu/qdev-monitor.c=0D =0D Log Message:=0D -----------=0D monitor: Tidy up find_device_state()=0D =0D Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"=0D extended find_device_state() to accept QOM paths in addition to qdev=0D IDs. This added a checked conversion to TYPE_DEVICE at the end, which=0D= duplicates the check done for the qdev ID case earlier, except it sets=0D= a *different* error: GenericError "ID is not a hotpluggable device"=0D when passed a QOM path, and DeviceNotFound "Device 'ID' not found"=0D when passed a qdev ID. Fortunately, the latter won't happen as long=0D as we add only devices to /machine/peripheral/.=0D =0D Earlier, commit b6cc36abb2 "qdev: device_del: Search for to be=0D unplugged device in 'peripheral' container" rewrote the lookup by qdev=0D= ID to use QOM instead of qdev_find_recursive(), so it can handle=0D buss-less devices. It does so by constructing an absolute QOM path.=0D Works, but object_resolve_path_component() is easier. Switching to it=0D= also gets rid of the unclean duplication described above.=0D =0D While there, avoid converting to TYPE_DEVICE twice, first to check=0D whether it's possible, and then for real.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210916111707.84999-1-armbru@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: eb8257a261325988873e047872975b5eda03efb4=0D https://github.com/qemu/qemu/commit/eb8257a261325988873e047872975b5= eda03efb4=0D Author: Dov Murik =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use local variable for kvm_sev_launch_start=0D =0D The struct kvm_sev_launch_start has a constant and small size, and=0D therefore we can use a regular local variable for it instead of=0D allocating and freeing heap memory for it.=0D =0D Signed-off-by: Dov Murik =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211011173026.2454294-2-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 59e42d88b6851b238927cbe48505b1cef547ce3b=0D https://github.com/qemu/qemu/commit/59e42d88b6851b238927cbe48505b1c= ef547ce3b=0D Author: Dov Murik =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use local variable for kvm_sev_launch_measure=0D =0D The struct kvm_sev_launch_measure has a constant and small size, and=0D therefore we can use a regular local variable for it instead of=0D allocating and freeing heap memory for it.=0D =0D Signed-off-by: Dov Murik =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211011173026.2454294-3-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: eeecc2ede44b2a5f2551dfcebd561a3945d4c132=0D https://github.com/qemu/qemu/commit/eeecc2ede44b2a5f2551dfcebd561a3= 945d4c132=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D ebpf: really include it only in system emulators=0D =0D eBPF libraries are being included in user emulators, which is useless and= =0D also breaks --static compilation if a shared library for libbpf is=0D present in the system.=0D =0D Reported-by: Alex Benn=C3=A9e =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 946de558354c99e1989621abe053f2ab87dc8de9=0D https://github.com/qemu/qemu/commit/946de558354c99e1989621abe053f2a= b87dc8de9=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M accel/hvf/hvf-accel-ops.c=0D M accel/kvm/meson.build=0D R accel/kvm/sev-stub.c=0D M hw/i386/pc_sysfw.c=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M hw/i386/x86.c=0D M hw/misc/applesmc.c=0D M include/hw/i386/sgx-epc.h=0D R include/hw/i386/sgx.h=0D M include/monitor/hmp-target.h=0D M include/monitor/hmp.h=0D R include/sysemu/sev.h=0D M meson.build=0D M qapi/misc-target.json=0D M qapi/qom.json=0D M softmmu/qdev-monitor.c=0D M target/i386/cpu.c=0D M target/i386/kvm/kvm.c=0D M target/i386/kvm/meson.build=0D A target/i386/kvm/sev-stub.c=0D M target/i386/meson.build=0D M target/i386/monitor.c=0D R target/i386/sev-stub.c=0D A target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D A target/i386/sev.h=0D R target/i386/sev_i386.h=0D M tests/Makefile.include=0D M tests/qemu-iotests/testrunner.py=0D M tests/tcg/x86_64/system/kernel.ld=0D M util/compatfd.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * SEV and SGX cleanups (Philippe, Dov)=0D * bugfixes for "check-block"=0D * bugfix for static build=0D * ObjectOptions cleanups (Thomas)=0D * binutils fix for PVH (Cole)=0D * HVF cleanup (Alex)=0D =0D # gpg: Signature made Wed 13 Oct 2021 01:47:56 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (40 commits)=0D ebpf: really include it only in system emulators=0D target/i386/sev: Use local variable for kvm_sev_launch_measure=0D target/i386/sev: Use local variable for kvm_sev_launch_start=0D monitor: Tidy up find_device_state()=0D Revert "hw/misc: applesmc: use host osk as default on macs"=0D hw/i386/sgx: Move qmp_query_sgx() and hmp_info_sgx() to hw/i386/sgx.c=0D= hw/i386/sgx: Move qmp_query_sgx_capabilities() to hw/i386/sgx.c=0D hw/i386/sgx: Have sgx_epc_get_section() return a boolean=0D MAINTAINERS: Cover SGX documentation file with X86/KVM section=0D hvf: Determine slot count from struct layout=0D tests: tcg: Fix PVH test with binutils 2.36+=0D qapi: Make some ObjectTypes depend on the build settings=0D MAINTAINERS: Cover SEV-related files with X86/KVM section=0D monitor: Reduce hmp_info_sev() declaration=0D target/i386/sev: Move qmp_query_sev() & hmp_info_sev() to sev.c=0D target/i386/sev: Move qmp_query_sev_launch_measure() to sev.c=0D target/i386/sev: Move qmp_query_sev_capabilities() to sev.c=0D target/i386/sev: Move qmp_sev_inject_launch_secret() to sev.c=0D target/i386/sev: Move qmp_query_sev_attestation_report() to sev.c=0D target/i386/sev: Remove stubs by using code elision=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/ee26ce674a93...946de558354c= =0D From MAILER-DAEMON Wed Oct 13 13:28:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mai3O-0005q5-UD for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 13:28:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mai3M-0005pA-HM for qemu-commits@nongnu.org; Wed, 13 Oct 2021 13:28:32 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:45819 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mai3G-00005U-UA for qemu-commits@nongnu.org; Wed, 13 Oct 2021 13:28:31 -0400 Received: from github.com (hubbernetes-node-17d1078.ac4-iad.github.net [10.52.125.37]) by smtp.github.com (Postfix) with ESMTPA id E95545607F3 for ; Wed, 13 Oct 2021 10:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634146106; bh=7MkGUBB26tH1a//ZUtogtNFZPQuvN8bNNhfoUuNxkzU=; h=Date:From:To:Subject:From; b=SNVIBTNVOsIS8e70RSADdmOca/u5WA2BP+icwfbPZ0F38cGd1rMa84thDVt9IbT/o Ah7zLhBfNU1ORKyDNCHnF4xgOJ2mohmJkOpL8sBU04gVHbBP9b5fwFKPCt2+2DeGMV MqzET3gPobDMPfQVr6UYb7iiSQ0QBLzbVo/p/uGQ= Date: Wed, 13 Oct 2021 10:28:25 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 601454: MAINTAINERS: Add myself as reviewer of the 'Memory... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 17:28:32 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 60145485232cf1c4f3e9314ddb8a99d0473d785a=0D https://github.com/qemu/qemu/commit/60145485232cf1c4f3e9314ddb8a99d= 0473d785a=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Add myself as reviewer of the 'Memory API'=0D =0D Having developed interest with the Memory API,=0D volunteer to review the patches.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: David Hildenbrand =0D Message-Id: <20211007091949.319404-1-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8009806ec81ff2caa711c99e87ca394f9ba50565=0D https://github.com/qemu/qemu/commit/8009806ec81ff2caa711c99e87ca394= f9ba50565=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/Makefile.include=0D =0D Log Message:=0D -----------=0D tests: add missing dependency for check-block=0D =0D qemu-iotests run qemu-storage-daemon, make sure it is up to date.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 097a5f19a357b6bc699a05ccd119bfa89ea409cc=0D https://github.com/qemu/qemu/commit/097a5f19a357b6bc699a05ccd119bfa= 89ea409cc=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/Makefile.include=0D =0D Log Message:=0D -----------=0D build: fix "make check" without earlier "make"=0D =0D "make check", if not preceded by "make", will not build the tools=0D needed by qemu-iotests. This happens because qemu-iotests, aka=0D "make check-block", is not yet part of meson.build.=0D =0D While at it, remove the reference to the now-dead QEMU_IOTESTS_HELPERS-y=0D= variable.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ecc00666a020368ec2c3712c40386dc7ea75a8a9=0D https://github.com/qemu/qemu/commit/ecc00666a020368ec2c3712c40386dc= 7ea75a8a9=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/qemu-iotests/testrunner.py=0D =0D Log Message:=0D -----------=0D qemu-iotests: flush after every test=0D =0D This makes it possible to see what is happening, even if the output of=0D= "make check-block" is not sent to a tty (for example if it is sent to=0D grep or tee).=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 6bd17dccb63e152266cf7a7399931c9fe11bc8cf=0D https://github.com/qemu/qemu/commit/6bd17dccb63e152266cf7a7399931c9= fe11bc8cf=0D Author: Kacper S=C5=82omi=C5=84ski =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M util/compatfd.c=0D =0D Log Message:=0D -----------=0D util/compatfd.c: use libc signalfd wrapper instead of raw syscall=0D =0D This allows the use of native signalfd instead of the sigtimedwait=0D based emulation on systems other than Linux.=0D =0D Signed-off-by: Kacper S=C5=82omi=C5=84ski =0D= Message-Id: <20210905011621.200785-1-kacper.slominski72@gmail.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b50f6dc174cf391d725fca895d74c441b23e2e47=0D https://github.com/qemu/qemu/commit/b50f6dc174cf391d725fca895d74c44= 1b23e2e47=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/misc-target.json=0D =0D Log Message:=0D -----------=0D qapi/misc-target: Wrap long 'SEV Attestation Report' long lines=0D =0D Wrap long lines before 70 characters for legibility.=0D =0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-2-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 993e26058d10756f5e206742c20b0cd03a9cb973=0D https://github.com/qemu/qemu/commit/993e26058d10756f5e206742c20b0cd= 03a9cb973=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/misc-target.json=0D =0D Log Message:=0D -----------=0D qapi/misc-target: Group SEV QAPI definitions=0D =0D There is already a section with various SEV commands / types,=0D so move the SEV guest attestation together.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-3-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 02310f3a91470575a103857222d3a6e8acea338e=0D https://github.com/qemu/qemu/commit/02310f3a91470575a103857222d3a6e= 8acea338e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/kvm/meson.build=0D =0D Log Message:=0D -----------=0D target/i386/kvm: Introduce i386_softmmu_kvm Meson source set=0D =0D Introduce the i386_softmmu_kvm Meson source set to be able to=0D add features dependent on CONFIG_KVM.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-4-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 773ab6cb16b34272dc7eb8171824924c38dbeb90=0D https://github.com/qemu/qemu/commit/773ab6cb16b34272dc7eb8171824924= c38dbeb90=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/kvm/meson.build=0D R accel/kvm/sev-stub.c=0D M target/i386/kvm/meson.build=0D A target/i386/kvm/sev-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/kvm: Restrict SEV stubs to x86 architecture=0D =0D SEV is x86-specific, no need to add its stub to other=0D architectures. Move the stub file to target/i386/kvm/.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-5-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2c7233eb103adbf567778270b69950dd7a776c72=0D https://github.com/qemu/qemu/commit/2c7233eb103adbf567778270b69950d= d7a776c72=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Prefix QMP errors with 'SEV'=0D =0D Multiple errors might be reported to the monitor,=0D better to prefix the SEV ones so we can distinct them.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211007161716.453984-6-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9f885cac701325ebcbf7e4393aa9b21b32ec3c12=0D https://github.com/qemu/qemu/commit/9f885cac701325ebcbf7e4393aa9b21= b32ec3c12=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D target/i386/monitor: Return QMP error when SEV is not enabled for guest= =0D =0D If the management layer tries to inject a secret, it gets an empty=0D response in case the guest doesn't have SEV enabled, or the binary=0D is built without SEV:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "return": {=0D }=0D }=0D =0D Make it clearer by returning an error:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "error": {=0D "class": "GenericError",=0D "desc": "SEV not enabled for guest"=0D }=0D }=0D =0D Note: we will remove the sev_inject_launch_secret() stub in few commits,=0D= so we don't bother to add error_setg() there.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-7-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f83aeeaeba1cf3e25d6292d9cc12064bfe2e78ab=0D https://github.com/qemu/qemu/commit/f83aeeaeba1cf3e25d6292d9cc12064= bfe2e78ab=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D =0D Log Message:=0D -----------=0D target/i386/cpu: Add missing 'qapi/error.h' header=0D =0D Commit 00b81053244 ("target-i386: Remove assert_no_error usage")=0D forgot to add the "qapi/error.h" for &error_abort, add it now.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-8-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 40cbafe05bb8f463d9dc096985ceff5d2535dc56=0D https://github.com/qemu/qemu/commit/40cbafe05bb8f463d9dc096985ceff5= d2535dc56=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev_i386.h: Remove unused headers=0D =0D Declarations don't require these headers, remove them.=0D =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-9-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4e7189e112966ac3a7bc884273a8b07291c3012e=0D https://github.com/qemu/qemu/commit/4e7189e112966ac3a7bc884273a8b07= 291c3012e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D M target/i386/sev.c=0D M target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Remove sev_get_me_mask()=0D =0D Unused dead code makes review harder, so remove it.=0D =0D Reviewed-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-10-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: d58d9f55a78a69730b4f1641f1c969d8585b970b=0D https://github.com/qemu/qemu/commit/d58d9f55a78a69730b4f1641f1c969d= 8585b970b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Mark unreachable code with g_assert_not_reached()=0D =0D The unique sev_encrypt_flash() invocation (in pc_system_flash_map)=0D is protected by the "if (sev_enabled())" check, so is not=0D reacheable.=0D Replace the abort() call in sev_es_save_reset_vector() by=0D g_assert_not_reached() which meaning is clearer.=0D =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-11-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ed84ae720d0b28c50906412a903e598f75ee1d7c=0D https://github.com/qemu/qemu/commit/ed84ae720d0b28c50906412a903e598= f75ee1d7c=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: sev_get_attestation_report use g_autofree=0D =0D Removes a whole bunch of g_free's and a goto.=0D =0D Signed-off-by: Dr. David Alan Gilbert =0D Reviewed-by: Connor Kuehl =0D Reviewed-by: Brijesh Singh =0D Message-Id: <20210603113017.34922-1-dgilbert@redhat.com>=0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-12-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 2f573c415e8c84ec79aa6deb1d04fa9fccdebca7=0D https://github.com/qemu/qemu/commit/2f573c415e8c84ec79aa6deb1d04fa9= fccdebca7=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use g_autofree in sev_launch_get_measure()=0D =0D Use g_autofree to remove a pair of g_free/goto.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-13-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e24b3332042b7372f4817694aec48650dcfa68a0=0D https://github.com/qemu/qemu/commit/e24b3332042b7372f4817694aec4865= 0dcfa68a0=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/meson.build=0D M target/i386/sev-stub.c=0D A target/i386/sev-sysemu-stub.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Restrict SEV to system emulation=0D =0D SEV is irrelevant on user emulation, so restrict it to sysemu.=0D Some stubs are still required because used in cpu.c by=0D x86_register_cpudef_types(), so move the sysemu specific stubs=0D to sev-sysemu-stub.c instead. This will allow us to simplify=0D monitor.c (which is not available in user emulation) in the=0D next commit.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-14-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 93777de3650e7db4b0434d63dd461505b85519f7=0D https://github.com/qemu/qemu/commit/93777de3650e7db4b0434d63dd46150= 5b85519f7=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/x86.c=0D M target/i386/cpu.c=0D M target/i386/kvm/kvm.c=0D M target/i386/monitor.c=0D M target/i386/sev-stub.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D A target/i386/sev.h=0D R target/i386/sev_i386.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Rename sev_i386.h -> sev.h=0D =0D SEV is a x86 specific feature, and the "sev_i386.h" header=0D is already in target/i386/. Rename it as "sev.h" to simplify.=0D =0D Patch created mechanically using:=0D =0D $ git mv target/i386/sev_i386.h target/i386/sev.h=0D $ sed -i s/sev_i386.h/sev.h/ $(git grep -l sev_i386.h)=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211007161716.453984-15-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: deae846f944a330e69109af8c807d6f2e66c95e6=0D https://github.com/qemu/qemu/commit/deae846f944a330e69109af8c807d6f= 2e66c95e6=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/pc_sysfw.c=0D R include/sysemu/sev.h=0D M target/i386/kvm/kvm.c=0D M target/i386/kvm/sev-stub.c=0D M target/i386/monitor.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Declare system-specific functions in 'sev.h'=0D =0D "sysemu/sev.h" is only used from x86-specific files. Let's move it=0D to include/hw/i386, and merge it with target/i386/sev.h.=0D =0D Suggested-by: Paolo Bonzini =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-16-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 02eacf31374152e6fb44554a4632f477d82dd9fc=0D https://github.com/qemu/qemu/commit/02eacf31374152e6fb44554a4632f47= 7d82dd9fc=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/cpu.c=0D M target/i386/meson.build=0D R target/i386/sev-stub.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Remove stubs by using code elision=0D =0D Only declare sev_enabled() and sev_es_enabled() when CONFIG_SEV is=0D set, to allow the compiler to elide unused code. Remove unnecessary=0D stubs.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Eric Blake =0D Message-Id: <20211007161716.453984-17-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3208de1cd23937254a456b95ef16658b68821a13=0D https://github.com/qemu/qemu/commit/3208de1cd23937254a456b95ef16658= b68821a13=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_attestation_report() to sev.c=0D =0D Move qmp_query_sev_attestation_report() from monitor.c to sev.c=0D and make sev_get_attestation_report() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-18-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 11a6ed0e77e8dd37ccea07575791b70c0410efea=0D https://github.com/qemu/qemu/commit/11a6ed0e77e8dd37ccea07575791b70= c0410efea=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_sev_inject_launch_secret() to sev.c=0D =0D Move qmp_sev_inject_launch_secret() from monitor.c to sev.c=0D and make sev_inject_launch_secret() static. We don't need the=0D stub anymore, remove it.=0D =0D Previously with binaries built without SEV, management layer=0D was getting an empty response:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "gpa": 4= 294959104 }=0D }=0D {=0D "return": {=0D }=0D }=0D =0D Now the response is explicit, mentioning the feature is disabled:=0D =0D { "execute": "sev-inject-launch-secret",=0D "arguments": { "packet-header": "mypkt", "secret": "mypass", "g= pa": 4294959104 }=0D }=0D {=0D "error": {=0D "class": "GenericError",=0D "desc": "this feature or command is not currently supported"=0D= }=0D }=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-19-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8371df29021241b43a7a9df6369fc70f649551a2=0D https://github.com/qemu/qemu/commit/8371df29021241b43a7a9df6369fc70= f649551a2=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_capabilities() to sev.c=0D =0D Move qmp_query_sev_capabilities() from monitor.c to sev.c=0D and make sev_get_capabilities() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-20-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0875a7038b8de0d79479a7d4662f0a9cdfa61940=0D https://github.com/qemu/qemu/commit/0875a7038b8de0d79479a7d4662f0a9= cdfa61940=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev_launch_measure() to sev.c=0D =0D Move qmp_query_sev_launch_measure() from monitor.c to sev.c=0D and make sev_get_launch_measurement() static. We don't need the=0D stub anymore, remove it.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-21-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: aa3950182f902a48f60d7040069b092eb5aaae21=0D https://github.com/qemu/qemu/commit/aa3950182f902a48f60d7040069b092= eb5aaae21=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/monitor.c=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D M target/i386/sev.h=0D =0D Log Message:=0D -----------=0D target/i386/sev: Move qmp_query_sev() & hmp_info_sev() to sev.c=0D =0D Move qmp_query_sev() & hmp_info_sev()() from monitor.c to sev.c=0D and make sev_get_info() static. We don't need the stub anymore,=0D remove it. Add a stub for hmp_info_sev().=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-22-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: cd35beb488c655a86da60d85949c026387187171=0D https://github.com/qemu/qemu/commit/cd35beb488c655a86da60d85949c026= 387187171=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M include/monitor/hmp-target.h=0D M include/monitor/hmp.h=0D M target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D monitor: Reduce hmp_info_sev() declaration=0D =0D While being conditionally used for TARGET_I386 in hmp-commands-info.hx,=0D= hmp_info_sev() is declared for all targets. Reduce its declaration=0D to target including "monitor/hmp-target.h". This is a minor cleanup.=0D =0D Reviewed-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-23-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8c9e7f8c8a6de68be1e31a645f7d76855fc219ba=0D https://github.com/qemu/qemu/commit/8c9e7f8c8a6de68be1e31a645f7d768= 55fc219ba=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Cover SEV-related files with X86/KVM section=0D =0D Complete the x86/KVM section with SEV-related files.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007161716.453984-24-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: f1279fc15bf4315fb8e103e6eabaee014ce1f914=0D https://github.com/qemu/qemu/commit/f1279fc15bf4315fb8e103e6eabaee0= 14ce1f914=0D Author: Thomas Huth =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M qapi/qom.json=0D =0D Log Message:=0D -----------=0D qapi: Make some ObjectTypes depend on the build settings=0D =0D Some of the ObjectType entries already depend on CONFIG_* switches.=0D Some others also only make sense with certain configurations, but=0D are currently always listed in the ObjectType enum. Let's make them=0D depend on the correpsonding CONFIG_* switches, too, so that upper=0D layers (like libvirt) have a better way to determine which features=0D are available in QEMU.=0D =0D Signed-off-by: Thomas Huth =0D Reviewed-by: Markus Armbruster =0D Message-Id: <20210928160232.432980-1-thuth@redhat.com>=0D [Do the same for MemoryBackendEpcProperties. - Paolo]=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8e751e9c38e324737fd3d3aa0562f886313bba3c=0D https://github.com/qemu/qemu/commit/8e751e9c38e324737fd3d3aa0562f88= 6313bba3c=0D Author: Cole Robinson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tests/tcg/x86_64/system/kernel.ld=0D =0D Log Message:=0D -----------=0D tests: tcg: Fix PVH test with binutils 2.36+=0D =0D binutils started adding a .note.gnu.property ELF section which=0D makes the PVH test fail:=0D =0D TEST hello on x86_64=0D qemu-system-x86_64: Error loading uncompressed kernel without PVH ELF Not= e=0D =0D Discard .note.gnu* while keeping the PVH .note bits intact.=0D =0D This also strips the build-id note, so drop the related comment.=0D =0D Signed-off-by: Cole Robinson =0D Message-Id: <5ab2a54c262c61f64c22dbb49ade3e2db8a740bb.1633708346.git.crob= inso@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: dec490db8b5c98d60814d07c23ddf70708a56d6e=0D https://github.com/qemu/qemu/commit/dec490db8b5c98d60814d07c23ddf70= 708a56d6e=0D Author: Alexander Graf =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/hvf/hvf-accel-ops.c=0D =0D Log Message:=0D -----------=0D hvf: Determine slot count from struct layout=0D =0D We can handle up to a static amount of memory slots, capped by the size o= f=0D an internal array.=0D =0D Let's make sure that array size is the only source of truth for the numbe= r=0D of elements in that array.=0D =0D Signed-off-by: Alexander Graf =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211008054616.43828-1-agraf@csgraf.de>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a821186ec02ecf5ac4949ed42410bf2095bcea66=0D https://github.com/qemu/qemu/commit/a821186ec02ecf5ac4949ed42410bf2= 095bcea66=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Cover SGX documentation file with X86/KVM section=0D =0D Cc: Yang Zhong =0D Cc: Paolo Bonzini =0D Cc: Marcelo Tosatti =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-2-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 05fc8db720a2effad2fe523ab45c1ce5f8f32379=0D https://github.com/qemu/qemu/commit/05fc8db720a2effad2fe523ab45c1ce= 5f8f32379=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M include/hw/i386/sgx-epc.h=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Have sgx_epc_get_section() return a boolean=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-3-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 021658566b71e138db46434849f0556bab3fc30b=0D https://github.com/qemu/qemu/commit/021658566b71e138db46434849f0556= bab3fc30b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M include/hw/i386/sgx.h=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Move qmp_query_sgx_capabilities() to hw/i386/sgx.c=0D =0D Move qmp_query_sgx_capabilities() from target/i386/monitor.c to=0D hw/i386/sgx.c, removing the sgx_get_capabilities() indirection.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-4-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 6e81733e27a250af7507c3dd5ae945c473ab0d6b=0D https://github.com/qemu/qemu/commit/6e81733e27a250af7507c3dd5ae945c= 473ab0d6b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D R include/hw/i386/sgx.h=0D M target/i386/monitor.c=0D =0D Log Message:=0D -----------=0D hw/i386/sgx: Move qmp_query_sgx() and hmp_info_sgx() to hw/i386/sgx.c=0D= =0D Move qmp_query_sgx() and hmp_info_sgx() from target/i386/monitor.c=0D to hw/i386/sgx.c, removing the sgx_get_info() indirection and the=0D "hw/i386/sgx.h" header.=0D =0D Suggested-by: Paolo Bonzini =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007175612.496366-5-philmd@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b71803a74612cc73eee82681f942a083038642ba=0D https://github.com/qemu/qemu/commit/b71803a74612cc73eee82681f942a08= 3038642ba=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/misc/applesmc.c=0D =0D Log Message:=0D -----------=0D Revert "hw/misc: applesmc: use host osk as default on macs"=0D =0D This reverts commit 93ddefbc3c909bb6c3b76086f1dfc8ad98dd3725.=0D The commit included code under the APSL 2.0, which is incompatible=0D with the GPL v2.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 69520261204b9a1769134ed24b92cc0fa8445951=0D https://github.com/qemu/qemu/commit/69520261204b9a1769134ed24b92cc0= fa8445951=0D Author: Markus Armbruster =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M softmmu/qdev-monitor.c=0D =0D Log Message:=0D -----------=0D monitor: Tidy up find_device_state()=0D =0D Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"=0D extended find_device_state() to accept QOM paths in addition to qdev=0D IDs. This added a checked conversion to TYPE_DEVICE at the end, which=0D= duplicates the check done for the qdev ID case earlier, except it sets=0D= a *different* error: GenericError "ID is not a hotpluggable device"=0D when passed a QOM path, and DeviceNotFound "Device 'ID' not found"=0D when passed a qdev ID. Fortunately, the latter won't happen as long=0D as we add only devices to /machine/peripheral/.=0D =0D Earlier, commit b6cc36abb2 "qdev: device_del: Search for to be=0D unplugged device in 'peripheral' container" rewrote the lookup by qdev=0D= ID to use QOM instead of qdev_find_recursive(), so it can handle=0D buss-less devices. It does so by constructing an absolute QOM path.=0D Works, but object_resolve_path_component() is easier. Switching to it=0D= also gets rid of the unclean duplication described above.=0D =0D While there, avoid converting to TYPE_DEVICE twice, first to check=0D whether it's possible, and then for real.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Damien Hedde =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210916111707.84999-1-armbru@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: eb8257a261325988873e047872975b5eda03efb4=0D https://github.com/qemu/qemu/commit/eb8257a261325988873e047872975b5= eda03efb4=0D Author: Dov Murik =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use local variable for kvm_sev_launch_start=0D =0D The struct kvm_sev_launch_start has a constant and small size, and=0D therefore we can use a regular local variable for it instead of=0D allocating and freeing heap memory for it.=0D =0D Signed-off-by: Dov Murik =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211011173026.2454294-2-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 59e42d88b6851b238927cbe48505b1cef547ce3b=0D https://github.com/qemu/qemu/commit/59e42d88b6851b238927cbe48505b1c= ef547ce3b=0D Author: Dov Murik =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/sev.c=0D =0D Log Message:=0D -----------=0D target/i386/sev: Use local variable for kvm_sev_launch_measure=0D =0D The struct kvm_sev_launch_measure has a constant and small size, and=0D therefore we can use a regular local variable for it instead of=0D allocating and freeing heap memory for it.=0D =0D Signed-off-by: Dov Murik =0D Reviewed-by: Dr. David Alan Gilbert =0D Message-Id: <20211011173026.2454294-3-dovmurik@linux.ibm.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: eeecc2ede44b2a5f2551dfcebd561a3945d4c132=0D https://github.com/qemu/qemu/commit/eeecc2ede44b2a5f2551dfcebd561a3= 945d4c132=0D Author: Paolo Bonzini =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D ebpf: really include it only in system emulators=0D =0D eBPF libraries are being included in user emulators, which is useless and= =0D also breaks --static compilation if a shared library for libbpf is=0D present in the system.=0D =0D Reported-by: Alex Benn=C3=A9e =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 946de558354c99e1989621abe053f2ab87dc8de9=0D https://github.com/qemu/qemu/commit/946de558354c99e1989621abe053f2a= b87dc8de9=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M accel/hvf/hvf-accel-ops.c=0D M accel/kvm/meson.build=0D R accel/kvm/sev-stub.c=0D M hw/i386/pc_sysfw.c=0D M hw/i386/sgx-stub.c=0D M hw/i386/sgx.c=0D M hw/i386/x86.c=0D M hw/misc/applesmc.c=0D M include/hw/i386/sgx-epc.h=0D R include/hw/i386/sgx.h=0D M include/monitor/hmp-target.h=0D M include/monitor/hmp.h=0D R include/sysemu/sev.h=0D M meson.build=0D M qapi/misc-target.json=0D M qapi/qom.json=0D M softmmu/qdev-monitor.c=0D M target/i386/cpu.c=0D M target/i386/kvm/kvm.c=0D M target/i386/kvm/meson.build=0D A target/i386/kvm/sev-stub.c=0D M target/i386/meson.build=0D M target/i386/monitor.c=0D R target/i386/sev-stub.c=0D A target/i386/sev-sysemu-stub.c=0D M target/i386/sev.c=0D A target/i386/sev.h=0D R target/i386/sev_i386.h=0D M tests/Makefile.include=0D M tests/qemu-iotests/testrunner.py=0D M tests/tcg/x86_64/system/kernel.ld=0D M util/compatfd.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * SEV and SGX cleanups (Philippe, Dov)=0D * bugfixes for "check-block"=0D * bugfix for static build=0D * ObjectOptions cleanups (Thomas)=0D * binutils fix for PVH (Cole)=0D * HVF cleanup (Alex)=0D =0D # gpg: Signature made Wed 13 Oct 2021 01:47:56 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (40 commits)=0D ebpf: really include it only in system emulators=0D target/i386/sev: Use local variable for kvm_sev_launch_measure=0D target/i386/sev: Use local variable for kvm_sev_launch_start=0D monitor: Tidy up find_device_state()=0D Revert "hw/misc: applesmc: use host osk as default on macs"=0D hw/i386/sgx: Move qmp_query_sgx() and hmp_info_sgx() to hw/i386/sgx.c=0D= hw/i386/sgx: Move qmp_query_sgx_capabilities() to hw/i386/sgx.c=0D hw/i386/sgx: Have sgx_epc_get_section() return a boolean=0D MAINTAINERS: Cover SGX documentation file with X86/KVM section=0D hvf: Determine slot count from struct layout=0D tests: tcg: Fix PVH test with binutils 2.36+=0D qapi: Make some ObjectTypes depend on the build settings=0D MAINTAINERS: Cover SEV-related files with X86/KVM section=0D monitor: Reduce hmp_info_sev() declaration=0D target/i386/sev: Move qmp_query_sev() & hmp_info_sev() to sev.c=0D target/i386/sev: Move qmp_query_sev_launch_measure() to sev.c=0D target/i386/sev: Move qmp_query_sev_capabilities() to sev.c=0D target/i386/sev: Move qmp_sev_inject_launch_secret() to sev.c=0D target/i386/sev: Move qmp_query_sev_attestation_report() to sev.c=0D target/i386/sev: Remove stubs by using code elision=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/ee26ce674a93...946de558354c= =0D From MAILER-DAEMON Wed Oct 13 13:38:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1maiDF-0001Gp-Et for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 13:38:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maiDD-0001Em-Ac for qemu-commits@nongnu.org; Wed, 13 Oct 2021 13:38:44 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:44531 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maiDB-0005ix-3d for qemu-commits@nongnu.org; Wed, 13 Oct 2021 13:38:42 -0400 Received: from github.com (hubbernetes-node-17d2c13.ac4-iad.github.net [10.52.211.39]) by smtp.github.com (Postfix) with ESMTPA id 52411560A39 for ; Wed, 13 Oct 2021 10:38:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634146720; bh=X+1YcpYabAUTxFocRr3E4ykSnUq5+YKHQsY0hLgBH7g=; h=Date:From:To:Subject:From; b=eA43rW88lHVNGVCt6VBPhv/qfxJPBarNdlKzCjGp9aStiJeGToJ0r0bRtJigUuhVT cre/1EJqHZvUPdHphIgHMKLzYUzb0xAZ9U0AHsf1Wd4aAWe1Z38JHK2EG0IlhleQmg /32tdbvHCbphPeEwZDidp0LS52ofNTI3dLBGcLy4= Date: Wed, 13 Oct 2021 10:38:40 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 452635: target/alpha: Reorg fp memory operations X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 17:38:44 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 452635318b78b98f0ef2586463334565674cb9e6=0D https://github.com/qemu/qemu/commit/452635318b78b98f0ef258646333456= 5674cb9e6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Reorg fp memory operations=0D =0D Pass in the context to each mini-helper, instead of an=0D incorrectly named "flags". Separate gen_load_fp and=0D gen_store_fp, away from the integer helpers.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5ffcb33426aaa2906daea2eee7a5195662a6580f=0D https://github.com/qemu/qemu/commit/5ffcb33426aaa2906daea2eee7a5195= 662a6580f=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Reorg integer memory operations=0D =0D Pass in the MemOp instead of a callback.=0D Drop the fp argument; add a locked argument.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 984b2b504942d9adb31d7743f02138fb79a73c12=0D https://github.com/qemu/qemu/commit/984b2b504942d9adb31d7743f02138f= b79a73c12=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20211013' into = staging=0D =0D Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN=0D =0D # gpg: Signature made Wed 13 Oct 2021 10:34:10 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-axp-20211013:=0D target/alpha: Reorg integer memory operations=0D target/alpha: Reorg fp memory operations=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/946de558354c...984b2b504942= =0D From MAILER-DAEMON Wed Oct 13 14:42:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1majCT-0004Dq-F9 for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 14:42:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1majCS-0004A7-3T for qemu-commits@nongnu.org; Wed, 13 Oct 2021 14:42:00 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:39557 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1majCP-000113-2R for qemu-commits@nongnu.org; Wed, 13 Oct 2021 14:41:59 -0400 Received: from github.com (hubbernetes-node-61aff55.va3-iad.github.net [10.48.210.47]) by smtp.github.com (Postfix) with ESMTPA id 578FC340B5B for ; Wed, 13 Oct 2021 11:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634150516; bh=2vnrHR6NKkzCIl09YiitOIAUII5Z0WMWNe2mJHq/1fc=; h=Date:From:To:Subject:From; b=QA0z4JIFEcf8sJmTo+bD4OBbvHJ++5Nf2Qk3NHN2YrdErcMYBZZhGQj82tTD3gDxk rXjYhQT0ebexQK6BwZf8sVAfT59aiJowAtenoECRigLzjuIr+OWe3IPjpvkNUdUEF4 imwXmNXBTbVZbLqix4fbSv0Sc5vUGjsxZ9igsJEk= Date: Wed, 13 Oct 2021 11:41:56 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 452635: target/alpha: Reorg fp memory operations X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 18:42:00 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 452635318b78b98f0ef2586463334565674cb9e6=0D https://github.com/qemu/qemu/commit/452635318b78b98f0ef258646333456= 5674cb9e6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Reorg fp memory operations=0D =0D Pass in the context to each mini-helper, instead of an=0D incorrectly named "flags". Separate gen_load_fp and=0D gen_store_fp, away from the integer helpers.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5ffcb33426aaa2906daea2eee7a5195662a6580f=0D https://github.com/qemu/qemu/commit/5ffcb33426aaa2906daea2eee7a5195= 662a6580f=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Reorg integer memory operations=0D =0D Pass in the MemOp instead of a callback.=0D Drop the fp argument; add a locked argument.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 984b2b504942d9adb31d7743f02138fb79a73c12=0D https://github.com/qemu/qemu/commit/984b2b504942d9adb31d7743f02138f= b79a73c12=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20211013' into = staging=0D =0D Cleanup alpha memory ops prior to prctl PR_SET_UNALIGN=0D =0D # gpg: Signature made Wed 13 Oct 2021 10:34:10 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-axp-20211013:=0D target/alpha: Reorg integer memory operations=0D target/alpha: Reorg fp memory operations=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/946de558354c...984b2b504942= =0D From MAILER-DAEMON Wed Oct 13 14:49:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1majJt-0004kO-Kp for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 14:49:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1majJr-0004io-Mw for qemu-commits@nongnu.org; Wed, 13 Oct 2021 14:49:39 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:53587 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1majJo-0007cr-3p for qemu-commits@nongnu.org; Wed, 13 Oct 2021 14:49:39 -0400 Received: from github.com (hubbernetes-node-e2c965e.va3-iad.github.net [10.48.209.58]) by smtp.github.com (Postfix) with ESMTPA id 2F4725C0517 for ; Wed, 13 Oct 2021 11:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634150975; bh=srti7NU2fvWKqp3h89bs0cYs/D4IkcWYZNCqqf1Yug0=; h=Date:From:To:Subject:From; b=y6LYQbR4WyuwQZ2LHo310mR4o3M224SOXuMzly3TphImliwgRQhyktX50zoP+cvhu 46gZ6Bg1Bo9YI7cDVxUtNtdi8s+6WyOBezj/PaOZ2jqiyERYQf692I5t5H9anhxo3L wntRN1dUGigO4jPNdvaiLEcaxmKTmUF7/lYEnqY4= Date: Wed, 13 Oct 2021 11:49:35 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7a7142: memory: Log access direction for invalid accesses X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 18:49:40 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 7a7142f0254464d16f0ddefd61237b40bfa97a47=0D https://github.com/qemu/qemu/commit/7a7142f0254464d16f0ddefd61237b4= 0bfa97a47=0D Author: BALATON Zoltan =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory.c=0D =0D Log Message:=0D -----------=0D memory: Log access direction for invalid accesses=0D =0D In memory_region_access_valid() invalid accesses are logged to help=0D debugging but the log message does not say if it was a read or write.=0D Log that too to better identify the access causing the problem.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <20211011173616.F1DE0756022@zero.eik.bme.hu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c21751f394591f2444c62bfcb1124300849ab46a=0D https://github.com/qemu/qemu/commit/c21751f394591f2444c62bfcb112430= 0849ab46a=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/arm/helper-a64.c=0D =0D Log Message:=0D -----------=0D target/arm: Use MO_128 for 16 byte atomics=0D =0D Cc: qemu-arm@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 26b14640d933d703c175a314479bdd0b8c26fedd=0D https://github.com/qemu/qemu/commit/26b14640d933d703c175a314479bdd0= b8c26fedd=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/i386: Use MO_128 for 16 byte atomics=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 68e33d869d2be9a765644782a0834fd87eec98f0=0D https://github.com/qemu/qemu/commit/68e33d869d2be9a765644782a0834fd= 87eec98f0=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use MO_128 for 16 byte atomics=0D =0D Cc: qemu-ppc@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 35c65de02998d23a26964c61b8c2e3b4235dcceb=0D https://github.com/qemu/qemu/commit/35c65de02998d23a26964c61b8c2e3b= 4235dcceb=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/s390x: Use MO_128 for 16 byte atomics=0D =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f79e80899dbcd306ae2e8a43bc5e139b051f30f4=0D https://github.com/qemu/qemu/commit/f79e80899dbcd306ae2e8a43bc5e139= b051f30f4=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/cpu.h=0D =0D Log Message:=0D -----------=0D target/hexagon: Implement cpu_mmu_index=0D =0D The function is trivial for user-only, but still must be present.=0D =0D Reviewed-by: Taylor Simpson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f83bcecb1ffe25a18367409eaf4ba1453c835c48=0D https://github.com/qemu/qemu/commit/f83bcecb1ffe25a18367409eaf4ba14= 53c835c48=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A accel/tcg/ldst_common.c.inc=0D M accel/tcg/user-exec.c=0D M docs/devel/loads-stores.rst=0D M include/exec/cpu_ldst.h=0D =0D Log Message:=0D -----------=0D accel/tcg: Add cpu_{ld,st}*_mmu interfaces=0D =0D These functions are much closer to the softmmu helper=0D functions, in that they take the complete MemOpIdx,=0D and from that they may enforce required alignment.=0D =0D The previous cpu_ldst.h functions did not have alignment info,=0D and so did not enforce it. Retain this by adding MO_UNALN to=0D the MemOp that we create in calling the new functions.=0D =0D Note that we are not yet enforcing alignment for user-only,=0D but we now have the information with which to do so.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b4c8f3d4dddcb6e547e1ba318f60ae9566743db1=0D https://github.com/qemu/qemu/commit/b4c8f3d4dddcb6e547e1ba318f60ae9= 566743db1=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M include/exec/cpu_ldst.h=0D M include/tcg/tcg.h=0D M target/arm/helper-a64.c=0D M target/m68k/op_helper.c=0D M target/ppc/mem_helper.c=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h=0D =0D The previous placement in tcg/tcg.h was not logical.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 948f88661c68307162dc4241144d87dc7772ca8d=0D https://github.com/qemu/qemu/commit/948f88661c68307162dc4241144d87d= c7772ca8d=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_helper.c=0D =0D Log Message:=0D -----------=0D target/mips: Use cpu_*_data_ra for msa load/store=0D =0D We should not have been using the helper_ret_* set of=0D functions, as they are supposed to be private to tcg.=0D Nor should we have been using the plain cpu_*_data set=0D of functions, as they do not handle unwinding properly.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 68ad9260e099da7c6345140d1da1811285e05757=0D https://github.com/qemu/qemu/commit/68ad9260e099da7c6345140d1da1811= 285e05757=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_helper.c=0D =0D Log Message:=0D -----------=0D target/mips: Use 8-byte memory ops for msa load/store=0D =0D Rather than use 4-16 separate operations, use 2 operations=0D plus some byte reordering as necessary.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bfe5b847af66be76c325f974017412f42e1dd62c=0D https://github.com/qemu/qemu/commit/bfe5b847af66be76c325f974017412f= 42e1dd62c=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/s390x: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a8f84958d09bfca0a775d8000bf81b0b66ca8066=0D https://github.com/qemu/qemu/commit/a8f84958d09bfca0a775d8000bf81b0= b66ca8066=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/sparc/ldst_helper.c=0D =0D Log Message:=0D -----------=0D target/sparc: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Reviewed-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1a2eaf9e3897b0c51ef65e676c9bbd125506dafd=0D https://github.com/qemu/qemu/commit/1a2eaf9e3897b0c51ef65e676c9bbd1= 25506dafd=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D =0D Log Message:=0D -----------=0D target/arm: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Cc: qemu-arm@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: d2ba80265739d1699dd33b93ed7db8d46e875ab6=0D https://github.com/qemu/qemu/commit/d2ba80265739d1699dd33b93ed7db8d= 46e875ab6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A include/tcg/tcg-ldst.h=0D M include/tcg/tcg.h=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h=0D =0D These functions have been replaced by cpu_*_mmu as the=0D most proper interface to use from target code.=0D =0D Hide these declarations from code that should not use them.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 76e366e728549b3324cc2dee6745d6a4f1af18e6=0D https://github.com/qemu/qemu/commit/76e366e728549b3324cc2dee6745d6a= 4f1af18e6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D tcg: Canonicalize alignment flags in MemOp=0D =0D Having observed e.g. al8+leq in dumps, canonicalize to al+leq.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e5b2333f24ff207f08cf96e73d2e11438c985801=0D https://github.com/qemu/qemu/commit/e5b2333f24ff207f08cf96e73d2e114= 38c985801=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A accel/tcg/ldst_common.c.inc=0D M accel/tcg/user-exec.c=0D M docs/devel/loads-stores.rst=0D M include/exec/cpu_ldst.h=0D A include/tcg/tcg-ldst.h=0D M include/tcg/tcg.h=0D M softmmu/memory.c=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/hexagon/cpu.h=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/ppc/mem_helper.c=0D M target/ppc/translate.c=0D M target/s390x/tcg/mem_helper.c=0D M target/sparc/ldst_helper.c=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211013' into = staging=0D =0D Use MO_128 for 16-byte atomic memory operations.=0D Add cpu_ld/st_mmu memory primitives.=0D Move helper_ld/st memory helpers out of tcg.h.=0D Canonicalize alignment flags in MemOp.=0D =0D # gpg: Signature made Wed 13 Oct 2021 10:48:45 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211013:=0D tcg: Canonicalize alignment flags in MemOp=0D tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h=0D target/arm: Use cpu_*_mmu instead of helper_*_mmu=0D target/sparc: Use cpu_*_mmu instead of helper_*_mmu=0D target/s390x: Use cpu_*_mmu instead of helper_*_mmu=0D target/mips: Use 8-byte memory ops for msa load/store=0D target/mips: Use cpu_*_data_ra for msa load/store=0D accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h=0D accel/tcg: Add cpu_{ld,st}*_mmu interfaces=0D target/hexagon: Implement cpu_mmu_index=0D target/s390x: Use MO_128 for 16 byte atomics=0D target/ppc: Use MO_128 for 16 byte atomics=0D target/i386: Use MO_128 for 16 byte atomics=0D target/arm: Use MO_128 for 16 byte atomics=0D memory: Log access direction for invalid accesses=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/984b2b504942...e5b2333f24ff= =0D From MAILER-DAEMON Wed Oct 13 15:55:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1makLb-0004aH-FY for mharc-qemu-commits@gnu.org; Wed, 13 Oct 2021 15:55:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1makLZ-0004ZZ-JY for qemu-commits@nongnu.org; Wed, 13 Oct 2021 15:55:29 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:47323 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1makLX-0003jG-AA for qemu-commits@nongnu.org; Wed, 13 Oct 2021 15:55:29 -0400 Received: from github.com (hubbernetes-node-d72f507.ash1-iad.github.net [10.56.113.30]) by smtp.github.com (Postfix) with ESMTPA id 72640840CE7 for ; Wed, 13 Oct 2021 12:55:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634154926; bh=yD/kc6lueknDEwEr8tfaWkTbK5B9WJs23SWxWTfV6R8=; h=Date:From:To:Subject:From; b=fZ7B4US8DJEj+YPNFEAFwodfFkP/8I6neVU79z4jrge+BCbQukQ3wn+GdgbKWLRm3 9TaBOTtTS3v2nO3uegkiuAKZ/0OPGKGcvNQd60/z8cNFXiGEBhdP1qeqf0+4rb89oW kS+vw9ibQFbXdHTIbmKDrypqhJNeheAihsMIKVBg= Date: Wed, 13 Oct 2021 12:55:26 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 7a7142: memory: Log access direction for invalid accesses X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Oct 2021 19:55:29 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 7a7142f0254464d16f0ddefd61237b40bfa97a47=0D https://github.com/qemu/qemu/commit/7a7142f0254464d16f0ddefd61237b4= 0bfa97a47=0D Author: BALATON Zoltan =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M softmmu/memory.c=0D =0D Log Message:=0D -----------=0D memory: Log access direction for invalid accesses=0D =0D In memory_region_access_valid() invalid accesses are logged to help=0D debugging but the log message does not say if it was a read or write.=0D Log that too to better identify the access causing the problem.=0D =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <20211011173616.F1DE0756022@zero.eik.bme.hu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c21751f394591f2444c62bfcb1124300849ab46a=0D https://github.com/qemu/qemu/commit/c21751f394591f2444c62bfcb112430= 0849ab46a=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/arm/helper-a64.c=0D =0D Log Message:=0D -----------=0D target/arm: Use MO_128 for 16 byte atomics=0D =0D Cc: qemu-arm@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 26b14640d933d703c175a314479bdd0b8c26fedd=0D https://github.com/qemu/qemu/commit/26b14640d933d703c175a314479bdd0= b8c26fedd=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/i386/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/i386: Use MO_128 for 16 byte atomics=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 68e33d869d2be9a765644782a0834fd87eec98f0=0D https://github.com/qemu/qemu/commit/68e33d869d2be9a765644782a0834fd= 87eec98f0=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use MO_128 for 16 byte atomics=0D =0D Cc: qemu-ppc@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 35c65de02998d23a26964c61b8c2e3b4235dcceb=0D https://github.com/qemu/qemu/commit/35c65de02998d23a26964c61b8c2e3b= 4235dcceb=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/s390x: Use MO_128 for 16 byte atomics=0D =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f79e80899dbcd306ae2e8a43bc5e139b051f30f4=0D https://github.com/qemu/qemu/commit/f79e80899dbcd306ae2e8a43bc5e139= b051f30f4=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/cpu.h=0D =0D Log Message:=0D -----------=0D target/hexagon: Implement cpu_mmu_index=0D =0D The function is trivial for user-only, but still must be present.=0D =0D Reviewed-by: Taylor Simpson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f83bcecb1ffe25a18367409eaf4ba1453c835c48=0D https://github.com/qemu/qemu/commit/f83bcecb1ffe25a18367409eaf4ba14= 53c835c48=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A accel/tcg/ldst_common.c.inc=0D M accel/tcg/user-exec.c=0D M docs/devel/loads-stores.rst=0D M include/exec/cpu_ldst.h=0D =0D Log Message:=0D -----------=0D accel/tcg: Add cpu_{ld,st}*_mmu interfaces=0D =0D These functions are much closer to the softmmu helper=0D functions, in that they take the complete MemOpIdx,=0D and from that they may enforce required alignment.=0D =0D The previous cpu_ldst.h functions did not have alignment info,=0D and so did not enforce it. Retain this by adding MO_UNALN to=0D the MemOp that we create in calling the new functions.=0D =0D Note that we are not yet enforcing alignment for user-only,=0D but we now have the information with which to do so.=0D =0D Reviewed-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b4c8f3d4dddcb6e547e1ba318f60ae9566743db1=0D https://github.com/qemu/qemu/commit/b4c8f3d4dddcb6e547e1ba318f60ae9= 566743db1=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M include/exec/cpu_ldst.h=0D M include/tcg/tcg.h=0D M target/arm/helper-a64.c=0D M target/m68k/op_helper.c=0D M target/ppc/mem_helper.c=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h=0D =0D The previous placement in tcg/tcg.h was not logical.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 948f88661c68307162dc4241144d87dc7772ca8d=0D https://github.com/qemu/qemu/commit/948f88661c68307162dc4241144d87d= c7772ca8d=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_helper.c=0D =0D Log Message:=0D -----------=0D target/mips: Use cpu_*_data_ra for msa load/store=0D =0D We should not have been using the helper_ret_* set of=0D functions, as they are supposed to be private to tcg.=0D Nor should we have been using the plain cpu_*_data set=0D of functions, as they do not handle unwinding properly.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 68ad9260e099da7c6345140d1da1811285e05757=0D https://github.com/qemu/qemu/commit/68ad9260e099da7c6345140d1da1811= 285e05757=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_helper.c=0D =0D Log Message:=0D -----------=0D target/mips: Use 8-byte memory ops for msa load/store=0D =0D Rather than use 4-16 separate operations, use 2 operations=0D plus some byte reordering as necessary.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bfe5b847af66be76c325f974017412f42e1dd62c=0D https://github.com/qemu/qemu/commit/bfe5b847af66be76c325f974017412f= 42e1dd62c=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/mem_helper.c=0D =0D Log Message:=0D -----------=0D target/s390x: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a8f84958d09bfca0a775d8000bf81b0b66ca8066=0D https://github.com/qemu/qemu/commit/a8f84958d09bfca0a775d8000bf81b0= b66ca8066=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/sparc/ldst_helper.c=0D =0D Log Message:=0D -----------=0D target/sparc: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Reviewed-by: Mark Cave-Ayland =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1a2eaf9e3897b0c51ef65e676c9bbd125506dafd=0D https://github.com/qemu/qemu/commit/1a2eaf9e3897b0c51ef65e676c9bbd1= 25506dafd=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D =0D Log Message:=0D -----------=0D target/arm: Use cpu_*_mmu instead of helper_*_mmu=0D =0D The helper_*_mmu functions were the only thing available=0D when this code was written. This could have been adjusted=0D when we added cpu_*_mmuidx_ra, but now we can most easily=0D use the newest set of interfaces.=0D =0D Cc: qemu-arm@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: d2ba80265739d1699dd33b93ed7db8d46e875ab6=0D https://github.com/qemu/qemu/commit/d2ba80265739d1699dd33b93ed7db8d= 46e875ab6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A include/tcg/tcg-ldst.h=0D M include/tcg/tcg.h=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h=0D =0D These functions have been replaced by cpu_*_mmu as the=0D most proper interface to use from target code.=0D =0D Hide these declarations from code that should not use them.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 76e366e728549b3324cc2dee6745d6a4f1af18e6=0D https://github.com/qemu/qemu/commit/76e366e728549b3324cc2dee6745d6a= 4f1af18e6=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg-op.c=0D =0D Log Message:=0D -----------=0D tcg: Canonicalize alignment flags in MemOp=0D =0D Having observed e.g. al8+leq in dumps, canonicalize to al+leq.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e5b2333f24ff207f08cf96e73d2e11438c985801=0D https://github.com/qemu/qemu/commit/e5b2333f24ff207f08cf96e73d2e114= 38c985801=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cputlb.c=0D A accel/tcg/ldst_common.c.inc=0D M accel/tcg/user-exec.c=0D M docs/devel/loads-stores.rst=0D M include/exec/cpu_ldst.h=0D A include/tcg/tcg-ldst.h=0D M include/tcg/tcg.h=0D M softmmu/memory.c=0D M target/arm/helper-a64.c=0D M target/arm/m_helper.c=0D M target/hexagon/cpu.h=0D M target/i386/tcg/mem_helper.c=0D M target/m68k/op_helper.c=0D M target/mips/tcg/msa_helper.c=0D M target/ppc/mem_helper.c=0D M target/ppc/translate.c=0D M target/s390x/tcg/mem_helper.c=0D M target/sparc/ldst_helper.c=0D M tcg/tcg-op.c=0D M tcg/tcg.c=0D M tcg/tci.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211013' into = staging=0D =0D Use MO_128 for 16-byte atomic memory operations.=0D Add cpu_ld/st_mmu memory primitives.=0D Move helper_ld/st memory helpers out of tcg.h.=0D Canonicalize alignment flags in MemOp.=0D =0D # gpg: Signature made Wed 13 Oct 2021 10:48:45 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211013:=0D tcg: Canonicalize alignment flags in MemOp=0D tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h=0D target/arm: Use cpu_*_mmu instead of helper_*_mmu=0D target/sparc: Use cpu_*_mmu instead of helper_*_mmu=0D target/s390x: Use cpu_*_mmu instead of helper_*_mmu=0D target/mips: Use 8-byte memory ops for msa load/store=0D target/mips: Use cpu_*_data_ra for msa load/store=0D accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h=0D accel/tcg: Add cpu_{ld,st}*_mmu interfaces=0D target/hexagon: Implement cpu_mmu_index=0D target/s390x: Use MO_128 for 16 byte atomics=0D target/ppc: Use MO_128 for 16 byte atomics=0D target/i386: Use MO_128 for 16 byte atomics=0D target/arm: Use MO_128 for 16 byte atomics=0D memory: Log access direction for invalid accesses=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/984b2b504942...e5b2333f24ff= =0D From MAILER-DAEMON Thu Oct 14 13:50:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mb4sP-0004Hv-0V for mharc-qemu-commits@gnu.org; Thu, 14 Oct 2021 13:50:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mb4sJ-0004Ff-3U for qemu-commits@nongnu.org; Thu, 14 Oct 2021 13:50:39 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:57611 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mb4sA-000273-JS for qemu-commits@nongnu.org; Thu, 14 Oct 2021 13:50:38 -0400 Received: from github.com (hubbernetes-node-c8f8bf8.va3-iad.github.net [10.48.201.89]) by smtp.github.com (Postfix) with ESMTPA id 1B05D340900 for ; Thu, 14 Oct 2021 10:50:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634233827; bh=yRC1qYA9TvSVRaDOTPSQdKqhHXh4Ad4c5h2sLuRURaU=; h=Date:From:To:Subject:From; b=eOq3c5Ub+SJs4QCfy1BP+P/97hZALh2tmdEfpqX4b0FsJ+kzbl6Y/1xt8Koo2NFDq +ARWqMuKitjsyTwk3g/XZ/840g92uJ3pZhW9cwimpyXUM0de3Q+TMPIqPtlbNPsuBE xtA726zA5JwK2iHtV6iHm+oqkKqiJQnQcCMs9D74= Date: Thu, 14 Oct 2021 10:50:27 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 381123: configure: remove --oss-lib X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Oct 2021 17:50:41 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 381123ddae754b68d55cd872e719a2ba69fe7f4a=0D https://github.com/qemu/qemu/commit/381123ddae754b68d55cd872e719a2b= a69fe7f4a=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove --oss-lib=0D =0D OSS is a kernel API, so the option should not be needed. The library=0D is used on NetBSD, where OSS is emulated, so keep the variable.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Thomas Huth =0D Message-Id: <20211007130630.632028-2-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7e1fbe7963f2b9bb44d6aa5c1ef793894212190a=0D https://github.com/qemu/qemu/commit/7e1fbe7963f2b9bb44d6aa5c1ef7938= 94212190a=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M audio/meson.build=0D M configure=0D =0D Log Message:=0D -----------=0D audio: remove CONFIG_AUDIO_WIN_INT=0D =0D Ever since winwaveaudio was removed in 2015, CONFIG_AUDIO_WIN_INT=0D is only set if dsound is in use, so use CONFIG_AUDIO_DSOUND directly.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-3-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 87430d5b13fdef0768cdb55352652ff78095e761=0D https://github.com/qemu/qemu/commit/87430d5b13fdef0768cdb55352652ff= 78095e761=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M audio/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D =0D Log Message:=0D -----------=0D configure, meson: move audio driver detection to Meson=0D =0D This brings a change that makes audio drivers more similar to all=0D other modules. All drivers are built by default, while=0D --audio-drv-list only governs the default choice of the audio driver.=0D =0D Meson options are added to disable the drivers, and the next patches=0D will fix the help messages and command line options, and especially=0D make the non-default drivers available via -audiodev.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-4-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e5424a2997bd5c6d480e80d3aa106bd4fba5fa7c=0D https://github.com/qemu/qemu/commit/e5424a2997bd5c6d480e80d3aa106bd= 4fba5fa7c=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: define symbols for all available audio drivers=0D =0D All drivers are now built by default if the corresponding libraries=0D are available, similar to how all other modules behave;=0D --audio-drv-list only governs the default choice of the audio driver.=0D =0D Adjust the CONFIG_AUDIO_* preprocessor symbols so that they are=0D based on library availability rather than --audio-drv-list, so that=0D the tests and -audiodev help follow the new logic.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Message-Id: <20211007130630.632028-5-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ca50e5231cfc120e90d264890bff59330257c361=0D https://github.com/qemu/qemu/commit/ca50e5231cfc120e90d264890bff593= 30257c361=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: add command line options for audio drivers=0D =0D Handle the choice of audio drivers the same as all other dependencies.=0D= =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-6-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 65ce87d47669168593398a4a3a0c0b0494858c0d=0D https://github.com/qemu/qemu/commit/65ce87d47669168593398a4a3a0c0b0= 494858c0d=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Kconfig.host=0D M hw/mem/Kconfig=0D M hw/mem/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D kconfig: split CONFIG_SPARSE_MEM from fuzzing=0D =0D Pass CONFIG_FUZZ via host_kconfig, and use it to select the=0D sparse-mem device.=0D =0D Cc: Alexander Oleinik =0D Reviewed-by: Alexander Bulekov =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Alexander Bulekov =0D Message-Id: <20211007130829.632254-1-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 537b7248991b85d1fb92cce78ecf1056f40bb750=0D https://github.com/qemu/qemu/commit/537b7248991b85d1fb92cce78ecf105= 6f40bb750=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M tests/qtest/fuzz/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move fuzzing configuration to Meson=0D =0D Cc: Alexander Oleinik =0D Reviewed-by: Alexander Bulekov =0D Tested-by: Alexander Bulekov =0D Message-Id: <20211007130829.632254-2-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0955d66e65e68580021a99960581422e93c127d4=0D https://github.com/qemu/qemu/commit/0955d66e65e68580021a99960581422= e93c127d4=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M trace/simple.c=0D =0D Log Message:=0D -----------=0D trace: simple: pass trace_file unmodified to config-host.h=0D =0D Add the suffix directly in trace/simple.c, so that quoting is done=0D properly by Meson.=0D =0D Cc: Stefan Hajnoczi =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-3-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9c29b74100e565c448b74a2f0e4051f4e656d18c=0D https://github.com/qemu/qemu/commit/9c29b74100e565c448b74a2f0e4051f= 4e656d18c=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D M meson.build=0D M meson_options.txt=0D M scripts/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D trace: move configuration from configure to Meson=0D =0D Cc: Stefan Hajnoczi =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-4-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a630508112aebad0da19384ff42642312d9d164f=0D https://github.com/qemu/qemu/commit/a630508112aebad0da19384ff426423= 12d9d164f=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move CONFIG_HOST_DSOSUF to Meson=0D =0D This is just a constant string, there is no need to pass it in config-hos= t.mak.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007130829.632254-5-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 269506d228d1aa48743a74d7a37d41d85ed9da59=0D https://github.com/qemu/qemu/commit/269506d228d1aa48743a74d7a37d41d= 85ed9da59=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: get HOST_WORDS_BIGENDIAN via the machine object=0D =0D No need to pass it in config-host.mak.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007130829.632254-6-pbonzini@redhat.com>=0D Reviewed-by: Thomas Huth =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: af2bb99bc122ecce3f1193aaf880f31b18cf6bd9=0D https://github.com/qemu/qemu/commit/af2bb99bc122ecce3f1193aaf880f31= b18cf6bd9=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: remove CONFIG_GCOV from config-host.mak=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-7-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a76a1f6b764bf9076440eb1a70e8c7636793d7fe=0D https://github.com/qemu/qemu/commit/a76a1f6b764bf9076440eb1a70e8c76= 36793d7fe=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: HAVE_GDB_BIN is not used by C code=0D =0D It is only used by the TCG tests, remove it from config-host.h.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 96a63aeb3d6658b837523fee0df25300622e1dd0=0D https://github.com/qemu/qemu/commit/96a63aeb3d6658b837523fee0df2530= 0622e1dd0=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move remaining HAVE_* compiler tests to Meson=0D =0D Remove some special cases by moving them to Meson.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-8-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 10f6b231879c94f34d3e6549c7b81b494d3cd1c2=0D https://github.com/qemu/qemu/commit/10f6b231879c94f34d3e6549c7b81b4= 94d3cd1c2=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M util/qemu-thread-posix.c=0D =0D Log Message:=0D -----------=0D configure, meson: move pthread_setname_np checks to Meson=0D =0D This makes the pthreads check dead in configure, so remove it=0D as well.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-9-pbonzini@redhat.com>=0D Reviewed-by: Thomas Huth =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ff66f3e55b5a8d95f0af1b7573bbcad5212b0ce7=0D https://github.com/qemu/qemu/commit/ff66f3e55b5a8d95f0af1b7573bbcad= 5212b0ce7=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M block/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D M stubs/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move libaio check to meson.build=0D =0D Message-Id: <20211007130829.632254-10-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e17239993d0f55c6b67a0318f177ab1168817e01=0D https://github.com/qemu/qemu/commit/e17239993d0f55c6b67a0318f177ab1= 168817e01=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move vde detection to meson=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-11-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 837b84b1c078bf3e909017ca11be7182a5df2ed0=0D https://github.com/qemu/qemu/commit/837b84b1c078bf3e909017ca11be718= 2a5df2ed0=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move netmap detection to meson=0D =0D Message-Id: <20211007130829.632254-12-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3f0a5d55ae1cd47149bf11bd984e54fc03ad6cfb=0D https://github.com/qemu/qemu/commit/3f0a5d55ae1cd47149bf11bd984e54f= c03ad6cfb=0D Author: Marc-Andr=C3=A9 Lureau =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M chardev/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D M ui/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move Spice configure handling to meson=0D =0D Add meson feature options for Spice and Spice protocol, and move=0D detection logic out of configure.=0D =0D Signed-off-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007102453.978041-1-marcandre.lureau@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20211007130829.632254-13-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b524e44fa4a6c0aeeb537fc704856002723c8d54=0D https://github.com/qemu/qemu/commit/b524e44fa4a6c0aeeb537fc70485600= 2723c8d54=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove obsolete Solaris ar check=0D =0D Meson already has its own logic to find the "ar" binary, so remove the=0D= Solaris specific check.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Thomas Huth =0D Message-Id: <20211007130829.632254-14-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bd87a36709096034bb8e9d12d2bf6ee1d003b6d7=0D https://github.com/qemu/qemu/commit/bd87a36709096034bb8e9d12d2bf6ee= 1d003b6d7=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M util/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move more compiler checks to Meson=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-15-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7bdf1f5a19132b1765482d73ee6e0782ffd374f3=0D https://github.com/qemu/qemu/commit/7bdf1f5a19132b1765482d73ee6e078= 2ffd374f3=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove deprecated --{enable, disable}-git-update=0D =0D The options were deprecated in 6.0. That said, we do not really have a=0D= formal deprecation cycle for build-time changes, since they do not affect= =0D users.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-16-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 03a3c0b3c59e93beeb7ca72cba632f78eb060253=0D https://github.com/qemu/qemu/commit/03a3c0b3c59e93beeb7ca72cba632f7= 8eb060253=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: accept "internal" for --enable-capstone/slirp/fdt=0D =0D Options such as "--enable-capstone=3Dgit" do not make much sense when bui= lding=0D from a tarball. Accept "internal" for consistency with the meson options= .=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-17-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 61d63097bec3a11f64e14a05a81401f9af7cea11=0D https://github.com/qemu/qemu/commit/61d63097bec3a11f64e14a05a81401f= 9af7cea11=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Makefile=0D M configure=0D A scripts/meson-buildoptions.py=0D A scripts/meson-buildoptions.sh=0D =0D Log Message:=0D -----------=0D configure: prepare for auto-generated option parsing=0D =0D Prepare the configure script and Makefile for automatically generated=0D help and parsing.=0D =0D Because we need to run the script to generate the full help, we=0D cannot rely on the user supplying the path to a Python interpreter=0D with --python; therefore, the introspection output is parsed into=0D shell functions and stored in scripts/. The converter is written=0D in Python as standard for QEMU, and this commit contains a stub.=0D =0D Tested-by: Thomas Huth =0D Message-Id: <20211007130829.632254-18-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8b5fb29842fdb586485dcfc4f24a9997c07cc9de=0D https://github.com/qemu/qemu/commit/8b5fb29842fdb586485dcfc4f24a999= 7c07cc9de=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M scripts/meson-buildoptions.py=0D =0D Log Message:=0D -----------=0D meson-buildoptions: include list of tracing backends=0D =0D Manually patch the introspection data to include the tracing backends.=0D= This works around a deficiency in Meson that will be fixed by=0D https://github.com/mesonbuild/meson/pull/9395.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3b4da13293482134b81d71be656ec76beff73a76=0D https://github.com/qemu/qemu/commit/3b4da13293482134b81d71be656ec76= beff73a76=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/devel/build-system.rst=0D M meson_options.txt=0D M scripts/meson-buildoptions.py=0D M scripts/meson-buildoptions.sh=0D =0D Log Message:=0D -----------=0D configure: automatically parse command line for meson -D options=0D =0D Right now meson_options.txt lists about 90 options. Each option=0D needs code in configure to parse it and pass the option down to Meson as=0D= a -D command-line argument; in addition the default must be duplicated=0D= between configure and meson_options.txt. This series tries to remove=0D the code duplication by generating the case statement for those --enable=0D= and --disable options, as well as the corresponding help text.=0D =0D About 80% of the options can be handled completely by the new mechanism.=0D= Eight meson options are not of the --enable/--disable kind. Six more nee= d=0D to be parsed in configure for various reasons documented in the patch,=0D= but they still have their help automatically generated.=0D =0D The advantages are:=0D =0D - less code in configure=0D =0D - parsing and help is more consistent (for example --enable-blobs was=0D not supported)=0D =0D - options are described entirely in one place, meson_options.txt.=0D This make it more attractive to use Meson options instead of=0D hand-crafted configure options and config-host.mak=0D =0D A few options change name: --enable-tcmalloc and --enable-jemalloc=0D become --enable-malloc=3D{tcmalloc,jemalloc}; --disable-blobs becomes=0D --disable-install-blobs; --enable-trace-backend becomes=0D --enable-trace-backends. However, the old names are allowed=0D for backwards compatibility.=0D =0D Message-Id: <20211007130829.632254-19-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4d1a525dfafe995a98bb486e702da09e31b68b9c=0D https://github.com/qemu/qemu/commit/4d1a525dfafe995a98bb486e702da09= e31b68b9c=0D Author: Richard Henderson =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Kconfig.host=0D M Makefile=0D M audio/meson.build=0D M block/meson.build=0D M chardev/meson.build=0D M configure=0D M docs/devel/build-system.rst=0D M docs/meson.build=0D M hw/mem/Kconfig=0D M hw/mem/meson.build=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D A scripts/meson-buildoptions.py=0D A scripts/meson-buildoptions.sh=0D M scripts/meson.build=0D M stubs/meson.build=0D M tests/qtest/fuzz/meson.build=0D M trace/meson.build=0D M trace/simple.c=0D M ui/meson.build=0D M util/meson.build=0D M util/qemu-thread-posix.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * Meson conversions + introspection-based command line parser=0D =0D # gpg: Signature made Thu 14 Oct 2021 12:51:54 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (26 commits)=0D configure: automatically parse command line for meson -D options=0D meson-buildoptions: include list of tracing backends=0D configure: prepare for auto-generated option parsing=0D configure: accept "internal" for --enable-capstone/slirp/fdt=0D configure: remove deprecated --{enable, disable}-git-update=0D configure, meson: move more compiler checks to Meson=0D configure: remove obsolete Solaris ar check=0D configure, meson: move Spice configure handling to meson=0D configure, meson: move netmap detection to meson=0D configure, meson: move vde detection to meson=0D configure, meson: move libaio check to meson.build=0D configure, meson: move pthread_setname_np checks to Meson=0D configure, meson: move remaining HAVE_* compiler tests to Meson=0D meson: HAVE_GDB_BIN is not used by C code=0D configure, meson: remove CONFIG_GCOV from config-host.mak=0D configure, meson: get HOST_WORDS_BIGENDIAN via the machine object=0D configure, meson: move CONFIG_HOST_DSOSUF to Meson=0D trace: move configuration from configure to Meson=0D trace: simple: pass trace_file unmodified to config-host.h=0D configure, meson: move fuzzing configuration to Meson=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e5b2333f24ff...4d1a525dfafe= =0D From MAILER-DAEMON Thu Oct 14 15:15:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mb6Cr-00051p-NL for mharc-qemu-commits@gnu.org; Thu, 14 Oct 2021 15:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mb6Cj-0004x5-67 for qemu-commits@nongnu.org; Thu, 14 Oct 2021 15:15:50 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:51303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mb6Cd-0000p4-PZ for qemu-commits@nongnu.org; Thu, 14 Oct 2021 15:15:46 -0400 Received: from github.com (hubbernetes-node-72d8ae7.ash1-iad.github.net [10.56.112.60]) by smtp.github.com (Postfix) with ESMTPA id 1FCFB9004A6 for ; Thu, 14 Oct 2021 12:15:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634238943; bh=MeNPrUi070P9BeLSefpdv9B31g40AzZkfAetClvtKl8=; h=Date:From:To:Subject:From; b=YKwr58amfS0gtiloJBHGfYgXgvDnnb4B/5yjwbvvAHBgs58YE5EJdbdz0cWQ9AKJy kOuhSAQsqS5KPRAezsy4lzEiNwfIBVLdKhhZmYenVNkeotQenxKH+Vm9UUOyLu8vW1 vVwRA/FRDFjhpTcSjeWkhYJzIWkoVk7Akz7+Wz3M= Date: Thu, 14 Oct 2021 12:15:43 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 381123: configure: remove --oss-lib X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Oct 2021 19:15:52 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 381123ddae754b68d55cd872e719a2ba69fe7f4a=0D https://github.com/qemu/qemu/commit/381123ddae754b68d55cd872e719a2b= a69fe7f4a=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove --oss-lib=0D =0D OSS is a kernel API, so the option should not be needed. The library=0D is used on NetBSD, where OSS is emulated, so keep the variable.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Thomas Huth =0D Message-Id: <20211007130630.632028-2-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7e1fbe7963f2b9bb44d6aa5c1ef793894212190a=0D https://github.com/qemu/qemu/commit/7e1fbe7963f2b9bb44d6aa5c1ef7938= 94212190a=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M audio/meson.build=0D M configure=0D =0D Log Message:=0D -----------=0D audio: remove CONFIG_AUDIO_WIN_INT=0D =0D Ever since winwaveaudio was removed in 2015, CONFIG_AUDIO_WIN_INT=0D is only set if dsound is in use, so use CONFIG_AUDIO_DSOUND directly.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-3-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 87430d5b13fdef0768cdb55352652ff78095e761=0D https://github.com/qemu/qemu/commit/87430d5b13fdef0768cdb55352652ff= 78095e761=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M audio/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D =0D Log Message:=0D -----------=0D configure, meson: move audio driver detection to Meson=0D =0D This brings a change that makes audio drivers more similar to all=0D other modules. All drivers are built by default, while=0D --audio-drv-list only governs the default choice of the audio driver.=0D =0D Meson options are added to disable the drivers, and the next patches=0D will fix the help messages and command line options, and especially=0D make the non-default drivers available via -audiodev.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-4-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e5424a2997bd5c6d480e80d3aa106bd4fba5fa7c=0D https://github.com/qemu/qemu/commit/e5424a2997bd5c6d480e80d3aa106bd= 4fba5fa7c=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: define symbols for all available audio drivers=0D =0D All drivers are now built by default if the corresponding libraries=0D are available, similar to how all other modules behave;=0D --audio-drv-list only governs the default choice of the audio driver.=0D =0D Adjust the CONFIG_AUDIO_* preprocessor symbols so that they are=0D based on library availability rather than --audio-drv-list, so that=0D the tests and -audiodev help follow the new logic.=0D =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Message-Id: <20211007130630.632028-5-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ca50e5231cfc120e90d264890bff59330257c361=0D https://github.com/qemu/qemu/commit/ca50e5231cfc120e90d264890bff593= 30257c361=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: add command line options for audio drivers=0D =0D Handle the choice of audio drivers the same as all other dependencies.=0D= =0D Cc: Gerd Hoffman =0D Cc: Volker R=C3=BCmelin =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130630.632028-6-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 65ce87d47669168593398a4a3a0c0b0494858c0d=0D https://github.com/qemu/qemu/commit/65ce87d47669168593398a4a3a0c0b0= 494858c0d=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Kconfig.host=0D M hw/mem/Kconfig=0D M hw/mem/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D kconfig: split CONFIG_SPARSE_MEM from fuzzing=0D =0D Pass CONFIG_FUZZ via host_kconfig, and use it to select the=0D sparse-mem device.=0D =0D Cc: Alexander Oleinik =0D Reviewed-by: Alexander Bulekov =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Alexander Bulekov =0D Message-Id: <20211007130829.632254-1-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 537b7248991b85d1fb92cce78ecf1056f40bb750=0D https://github.com/qemu/qemu/commit/537b7248991b85d1fb92cce78ecf105= 6f40bb750=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M tests/qtest/fuzz/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move fuzzing configuration to Meson=0D =0D Cc: Alexander Oleinik =0D Reviewed-by: Alexander Bulekov =0D Tested-by: Alexander Bulekov =0D Message-Id: <20211007130829.632254-2-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 0955d66e65e68580021a99960581422e93c127d4=0D https://github.com/qemu/qemu/commit/0955d66e65e68580021a99960581422= e93c127d4=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M trace/simple.c=0D =0D Log Message:=0D -----------=0D trace: simple: pass trace_file unmodified to config-host.h=0D =0D Add the suffix directly in trace/simple.c, so that quoting is done=0D properly by Meson.=0D =0D Cc: Stefan Hajnoczi =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-3-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 9c29b74100e565c448b74a2f0e4051f4e656d18c=0D https://github.com/qemu/qemu/commit/9c29b74100e565c448b74a2f0e4051f= 4e656d18c=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/meson.build=0D M meson.build=0D M meson_options.txt=0D M scripts/meson.build=0D M trace/meson.build=0D =0D Log Message:=0D -----------=0D trace: move configuration from configure to Meson=0D =0D Cc: Stefan Hajnoczi =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-4-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a630508112aebad0da19384ff42642312d9d164f=0D https://github.com/qemu/qemu/commit/a630508112aebad0da19384ff426423= 12d9d164f=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move CONFIG_HOST_DSOSUF to Meson=0D =0D This is just a constant string, there is no need to pass it in config-hos= t.mak.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007130829.632254-5-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 269506d228d1aa48743a74d7a37d41d85ed9da59=0D https://github.com/qemu/qemu/commit/269506d228d1aa48743a74d7a37d41d= 85ed9da59=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: get HOST_WORDS_BIGENDIAN via the machine object=0D =0D No need to pass it in config-host.mak.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211007130829.632254-6-pbonzini@redhat.com>=0D Reviewed-by: Thomas Huth =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: af2bb99bc122ecce3f1193aaf880f31b18cf6bd9=0D https://github.com/qemu/qemu/commit/af2bb99bc122ecce3f1193aaf880f31= b18cf6bd9=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: remove CONFIG_GCOV from config-host.mak=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-7-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: a76a1f6b764bf9076440eb1a70e8c7636793d7fe=0D https://github.com/qemu/qemu/commit/a76a1f6b764bf9076440eb1a70e8c76= 36793d7fe=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: HAVE_GDB_BIN is not used by C code=0D =0D It is only used by the TCG tests, remove it from config-host.h.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 96a63aeb3d6658b837523fee0df25300622e1dd0=0D https://github.com/qemu/qemu/commit/96a63aeb3d6658b837523fee0df2530= 0622e1dd0=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move remaining HAVE_* compiler tests to Meson=0D =0D Remove some special cases by moving them to Meson.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-8-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 10f6b231879c94f34d3e6549c7b81b494d3cd1c2=0D https://github.com/qemu/qemu/commit/10f6b231879c94f34d3e6549c7b81b4= 94d3cd1c2=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M util/qemu-thread-posix.c=0D =0D Log Message:=0D -----------=0D configure, meson: move pthread_setname_np checks to Meson=0D =0D This makes the pthreads check dead in configure, so remove it=0D as well.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-9-pbonzini@redhat.com>=0D Reviewed-by: Thomas Huth =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: ff66f3e55b5a8d95f0af1b7573bbcad5212b0ce7=0D https://github.com/qemu/qemu/commit/ff66f3e55b5a8d95f0af1b7573bbcad= 5212b0ce7=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M block/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D M stubs/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move libaio check to meson.build=0D =0D Message-Id: <20211007130829.632254-10-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: e17239993d0f55c6b67a0318f177ab1168817e01=0D https://github.com/qemu/qemu/commit/e17239993d0f55c6b67a0318f177ab1= 168817e01=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move vde detection to meson=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-11-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 837b84b1c078bf3e909017ca11be7182a5df2ed0=0D https://github.com/qemu/qemu/commit/837b84b1c078bf3e909017ca11be718= 2a5df2ed0=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move netmap detection to meson=0D =0D Message-Id: <20211007130829.632254-12-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3f0a5d55ae1cd47149bf11bd984e54fc03ad6cfb=0D https://github.com/qemu/qemu/commit/3f0a5d55ae1cd47149bf11bd984e54f= c03ad6cfb=0D Author: Marc-Andr=C3=A9 Lureau =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M chardev/meson.build=0D M configure=0D M meson.build=0D M meson_options.txt=0D M ui/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move Spice configure handling to meson=0D =0D Add meson feature options for Spice and Spice protocol, and move=0D detection logic out of configure.=0D =0D Signed-off-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007102453.978041-1-marcandre.lureau@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20211007130829.632254-13-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: b524e44fa4a6c0aeeb537fc704856002723c8d54=0D https://github.com/qemu/qemu/commit/b524e44fa4a6c0aeeb537fc70485600= 2723c8d54=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove obsolete Solaris ar check=0D =0D Meson already has its own logic to find the "ar" binary, so remove the=0D= Solaris specific check.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Reviewed-by: Thomas Huth =0D Message-Id: <20211007130829.632254-14-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: bd87a36709096034bb8e9d12d2bf6ee1d003b6d7=0D https://github.com/qemu/qemu/commit/bd87a36709096034bb8e9d12d2bf6ee= 1d003b6d7=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M meson.build=0D M util/meson.build=0D =0D Log Message:=0D -----------=0D configure, meson: move more compiler checks to Meson=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-15-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 7bdf1f5a19132b1765482d73ee6e0782ffd374f3=0D https://github.com/qemu/qemu/commit/7bdf1f5a19132b1765482d73ee6e078= 2ffd374f3=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: remove deprecated --{enable, disable}-git-update=0D =0D The options were deprecated in 6.0. That said, we do not really have a=0D= formal deprecation cycle for build-time changes, since they do not affect= =0D users.=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-16-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 03a3c0b3c59e93beeb7ca72cba632f78eb060253=0D https://github.com/qemu/qemu/commit/03a3c0b3c59e93beeb7ca72cba632f7= 8eb060253=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: accept "internal" for --enable-capstone/slirp/fdt=0D =0D Options such as "--enable-capstone=3Dgit" do not make much sense when bui= lding=0D from a tarball. Accept "internal" for consistency with the meson options= .=0D =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20211007130829.632254-17-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 61d63097bec3a11f64e14a05a81401f9af7cea11=0D https://github.com/qemu/qemu/commit/61d63097bec3a11f64e14a05a81401f= 9af7cea11=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Makefile=0D M configure=0D A scripts/meson-buildoptions.py=0D A scripts/meson-buildoptions.sh=0D =0D Log Message:=0D -----------=0D configure: prepare for auto-generated option parsing=0D =0D Prepare the configure script and Makefile for automatically generated=0D help and parsing.=0D =0D Because we need to run the script to generate the full help, we=0D cannot rely on the user supplying the path to a Python interpreter=0D with --python; therefore, the introspection output is parsed into=0D shell functions and stored in scripts/. The converter is written=0D in Python as standard for QEMU, and this commit contains a stub.=0D =0D Tested-by: Thomas Huth =0D Message-Id: <20211007130829.632254-18-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 8b5fb29842fdb586485dcfc4f24a9997c07cc9de=0D https://github.com/qemu/qemu/commit/8b5fb29842fdb586485dcfc4f24a999= 7c07cc9de=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M scripts/meson-buildoptions.py=0D =0D Log Message:=0D -----------=0D meson-buildoptions: include list of tracing backends=0D =0D Manually patch the introspection data to include the tracing backends.=0D= This works around a deficiency in Meson that will be fixed by=0D https://github.com/mesonbuild/meson/pull/9395.=0D =0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 3b4da13293482134b81d71be656ec76beff73a76=0D https://github.com/qemu/qemu/commit/3b4da13293482134b81d71be656ec76= beff73a76=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D M docs/devel/build-system.rst=0D M meson_options.txt=0D M scripts/meson-buildoptions.py=0D M scripts/meson-buildoptions.sh=0D =0D Log Message:=0D -----------=0D configure: automatically parse command line for meson -D options=0D =0D Right now meson_options.txt lists about 90 options. Each option=0D needs code in configure to parse it and pass the option down to Meson as=0D= a -D command-line argument; in addition the default must be duplicated=0D= between configure and meson_options.txt. This series tries to remove=0D the code duplication by generating the case statement for those --enable=0D= and --disable options, as well as the corresponding help text.=0D =0D About 80% of the options can be handled completely by the new mechanism.=0D= Eight meson options are not of the --enable/--disable kind. Six more nee= d=0D to be parsed in configure for various reasons documented in the patch,=0D= but they still have their help automatically generated.=0D =0D The advantages are:=0D =0D - less code in configure=0D =0D - parsing and help is more consistent (for example --enable-blobs was=0D not supported)=0D =0D - options are described entirely in one place, meson_options.txt.=0D This make it more attractive to use Meson options instead of=0D hand-crafted configure options and config-host.mak=0D =0D A few options change name: --enable-tcmalloc and --enable-jemalloc=0D become --enable-malloc=3D{tcmalloc,jemalloc}; --disable-blobs becomes=0D --disable-install-blobs; --enable-trace-backend becomes=0D --enable-trace-backends. However, the old names are allowed=0D for backwards compatibility.=0D =0D Message-Id: <20211007130829.632254-19-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D =0D =0D Commit: 4d1a525dfafe995a98bb486e702da09e31b68b9c=0D https://github.com/qemu/qemu/commit/4d1a525dfafe995a98bb486e702da09= e31b68b9c=0D Author: Richard Henderson =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M Kconfig.host=0D M Makefile=0D M audio/meson.build=0D M block/meson.build=0D M chardev/meson.build=0D M configure=0D M docs/devel/build-system.rst=0D M docs/meson.build=0D M hw/mem/Kconfig=0D M hw/mem/meson.build=0D M meson.build=0D M meson_options.txt=0D M net/meson.build=0D A scripts/meson-buildoptions.py=0D A scripts/meson-buildoptions.sh=0D M scripts/meson.build=0D M stubs/meson.build=0D M tests/qtest/fuzz/meson.build=0D M trace/meson.build=0D M trace/simple.c=0D M ui/meson.build=0D M util/meson.build=0D M util/qemu-thread-posix.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into s= taging=0D =0D * Meson conversions + introspection-based command line parser=0D =0D # gpg: Signature made Thu 14 Oct 2021 12:51:54 AM PDT=0D # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7A= E83=0D # gpg: issuer "pbonzini@redhat.com"=0D # gpg: Good signature from "Paolo Bonzini " [full]=0D # gpg: aka "Paolo Bonzini " [full]=0D= =0D * remotes/bonzini/tags/for-upstream: (26 commits)=0D configure: automatically parse command line for meson -D options=0D meson-buildoptions: include list of tracing backends=0D configure: prepare for auto-generated option parsing=0D configure: accept "internal" for --enable-capstone/slirp/fdt=0D configure: remove deprecated --{enable, disable}-git-update=0D configure, meson: move more compiler checks to Meson=0D configure: remove obsolete Solaris ar check=0D configure, meson: move Spice configure handling to meson=0D configure, meson: move netmap detection to meson=0D configure, meson: move vde detection to meson=0D configure, meson: move libaio check to meson.build=0D configure, meson: move pthread_setname_np checks to Meson=0D configure, meson: move remaining HAVE_* compiler tests to Meson=0D meson: HAVE_GDB_BIN is not used by C code=0D configure, meson: remove CONFIG_GCOV from config-host.mak=0D configure, meson: get HOST_WORDS_BIGENDIAN via the machine object=0D configure, meson: move CONFIG_HOST_DSOSUF to Meson=0D trace: move configuration from configure to Meson=0D trace: simple: pass trace_file unmodified to config-host.h=0D configure, meson: move fuzzing configuration to Meson=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e5b2333f24ff...4d1a525dfafe= =0D From MAILER-DAEMON Fri Oct 15 12:20:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbPwo-0003kW-GN for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 12:20:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbPwm-0003k5-14 for qemu-commits@nongnu.org; Fri, 15 Oct 2021 12:20:40 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:59437 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbPwi-0005Na-Rc for qemu-commits@nongnu.org; Fri, 15 Oct 2021 12:20:39 -0400 Received: from github.com (hubbernetes-node-47d496c.ash1-iad.github.net [10.56.111.33]) by smtp.github.com (Postfix) with ESMTPA id 074598407EE for ; Fri, 15 Oct 2021 09:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634314835; bh=bbFbPT5ogKA57snhF3HumZoDegZhWXQUrRf0vl4/DO4=; h=Date:From:To:Subject:From; b=akHUKISPj3jbPiV0SFTzLZHbi/N7q1WTv/bqrl5U94wwoeRiUolVPJMVk+CeSnfA9 nQcbW453vRRwFwg0Ljmb1ndGvcvyWK569JblptvY+FEV/5zDNk2s9+PJYIoih5Q2sC vIeOsmBhE7FRsbwu2N2r1/2a9GFNcUagNC2xyXgg= Date: Fri, 15 Oct 2021 09:20:35 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f14201: s390x/ipl: check kernel command line size X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 16:20:40 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: f1420101023c7d170d802efc8daab686189ed1bf=0D https://github.com/qemu/qemu/commit/f1420101023c7d170d802efc8daab68= 6189ed1bf=0D Author: Marc Hartmayer =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/s390x/ipl.c=0D =0D Log Message:=0D -----------=0D s390x/ipl: check kernel command line size=0D =0D Check if the provided kernel command line exceeds the maximum size of the= s390x=0D Linux kernel command line size, which is 896 bytes.=0D =0D Reported-by: Sven Schnelle =0D Signed-off-by: Marc Hartmayer =0D Message-Id: <20211006092631.20732-1-mhartmay@linux.ibm.com>=0D Reviewed-by: Christian Borntraeger =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [thuth: Adjusted format specifier for size_t]=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 998eb7448c75b432a13257d019f6866e604ce43c=0D https://github.com/qemu/qemu/commit/998eb7448c75b432a13257d019f6866= e604ce43c=0D Author: Eric Farman =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/sigp.c=0D =0D Log Message:=0D -----------=0D s390x: sigp: Force Set Architecture to return Invalid Parameter=0D =0D According to the Principles of Operation, the SIGP Set Architecture=0D order will return Incorrect State if some CPUs are not stopped, but=0D only if the CZAM facility is not present. If it is, the order will=0D return Invalid Parameter because the architecture mode cannot be=0D changed.=0D =0D Since CZAM always exists when S390_FEAT_ZARCH exists, which in turn=0D exists for every defined CPU model, we can simplify this code.=0D =0D Fixes: 075e52b81664 ("s390x/cpumodel: we are always in zarchitecture mode= ")=0D Signed-off-by: Eric Farman =0D Reviewed-by: Christian Borntraeger =0D Reviewed-by: Janosch Frank =0D Message-Id: <20211008203811.1980478-2-farman@linux.ibm.com>=0D Reviewed-by: Thomas Huth =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: ebbc6034dcfe772473d1d29724b36ce7a9a49ad2=0D https://github.com/qemu/qemu/commit/ebbc6034dcfe772473d1d29724b36ce= 7a9a49ad2=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D vfio-ccw: step down as maintainer=0D =0D I currently don't have time to act as vfio-ccw maintainer anymore,=0D so remove myself there.=0D =0D Signed-off-by: Cornelia Huck =0D Message-Id: <20211012144040.360887-2-cohuck@redhat.com>=0D Acked-by: Matthew Rosato =0D Acked-by: Eric Farman =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 373b2ab35635537c67bb6fe9aa36367f28a067a2=0D https://github.com/qemu/qemu/commit/373b2ab35635537c67bb6fe9aa36367= f28a067a2=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D s390x/kvm: step down as maintainer=0D =0D I'm no longer involved with KVM/s390 on the kernel side, and I don't=0D have enough resources to work on the s390 KVM cpus support, so I'll=0D step down.=0D =0D Signed-off-by: Cornelia Huck =0D Acked-by: Halil Pasic =0D Message-Id: <20211012144040.360887-3-cohuck@redhat.com>=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: afe5c8c5c14aff25fab6ae83957e87c717415be3=0D https://github.com/qemu/qemu/commit/afe5c8c5c14aff25fab6ae83957e87c= 717415be3=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D s390x virtio-ccw machine: step down as maintainer=0D =0D I currently don't have time to work on the s390x virtio-ccw machine=0D anymore, so let's step down. (I will, however, continue as a=0D maintainer for the virtio-ccw *transport*.)=0D =0D Signed-off-by: Cornelia Huck =0D Acked-by: Halil Pasic =0D Message-Id: <20211012144040.360887-4-cohuck@redhat.com>=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 962fde57b7d573281619cb2b7068d570470ef833=0D https://github.com/qemu/qemu/commit/962fde57b7d573281619cb2b7068d57= 0470ef833=0D Author: Thomas Huth =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M dtc=0D =0D Log Message:=0D -----------=0D dtc: Update to version 1.6.1=0D =0D The dtc submodule is currently pointing to non-release commit. It's nicer= =0D if submodules point to release versions instead and since dtc 1.6.1 is=0D= available now, let's update to that version.=0D =0D Message-Id: <20210827120901.150276-4-thuth@redhat.com>=0D Acked-by: Greg Kurz =0D Acked-by: David Gibson =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 82d88f834c8f7d33ad9529fca80924bc496fcb70=0D https://github.com/qemu/qemu/commit/82d88f834c8f7d33ad9529fca80924b= c496fcb70=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M dtc=0D M hw/s390x/ipl.c=0D M target/s390x/sigp.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/thuth/tags/pull-request-2021-10-1= 5' into staging=0D =0D * Check kernel command line size on s390x=0D * Simplification of one of the SIGP instructions on s390x=0D * Cornelia stepping down as maintainer in some subsystems=0D * Update the dtc submodule to a proper release version=0D =0D # gpg: Signature made Fri 15 Oct 2021 02:11:13 AM PDT=0D # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702= DB5=0D # gpg: issuer "thuth@redhat.com"=0D # gpg: Good signature from "Thomas Huth " [full]=0D # gpg: aka "Thomas Huth " [full]=0D # gpg: aka "Thomas Huth " [unknown]=0D= # gpg: aka "Thomas Huth " [full]=0D =0D * remotes/thuth/tags/pull-request-2021-10-15:=0D dtc: Update to version 1.6.1=0D s390x virtio-ccw machine: step down as maintainer=0D s390x/kvm: step down as maintainer=0D vfio-ccw: step down as maintainer=0D s390x: sigp: Force Set Architecture to return Invalid Parameter=0D s390x/ipl: check kernel command line size=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/4d1a525dfafe...82d88f834c8f= =0D From MAILER-DAEMON Fri Oct 15 15:08:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbSYm-0001R3-6f for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 15:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbSYk-0001OO-Qm for qemu-commits@nongnu.org; Fri, 15 Oct 2021 15:08:03 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:57509 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbSYi-0001Ye-3f for qemu-commits@nongnu.org; Fri, 15 Oct 2021 15:08:02 -0400 Received: from github.com (hubbernetes-node-1ec0b10.ash1-iad.github.net [10.56.22.72]) by smtp.github.com (Postfix) with ESMTPA id 5715E840057 for ; Fri, 15 Oct 2021 12:07:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634324879; bh=vh0jMoDCf5i/zi7LeoWErXU2idCN5G8m/txnIUCb3Ws=; h=Date:From:To:Subject:From; b=HrPPdb7j/zR5FAnxwh4MX+uHTWjgXSOd9bk6xs9ONfb/ShWOLUwD71m9/70OjQ3q7 IJb3LOQz/cNiIiJip9UkPvGSk19bQjvnyG2mCNJhq7BYUMTW0t5D3Fg+L5WvWc5O8j L+qnjXyKda1S5g5865x2moVi181Pk40niPo4SJNI= Date: Fri, 15 Oct 2021 12:07:59 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f14201: s390x/ipl: check kernel command line size X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 19:08:03 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: f1420101023c7d170d802efc8daab686189ed1bf=0D https://github.com/qemu/qemu/commit/f1420101023c7d170d802efc8daab68= 6189ed1bf=0D Author: Marc Hartmayer =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/s390x/ipl.c=0D =0D Log Message:=0D -----------=0D s390x/ipl: check kernel command line size=0D =0D Check if the provided kernel command line exceeds the maximum size of the= s390x=0D Linux kernel command line size, which is 896 bytes.=0D =0D Reported-by: Sven Schnelle =0D Signed-off-by: Marc Hartmayer =0D Message-Id: <20211006092631.20732-1-mhartmay@linux.ibm.com>=0D Reviewed-by: Christian Borntraeger =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [thuth: Adjusted format specifier for size_t]=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 998eb7448c75b432a13257d019f6866e604ce43c=0D https://github.com/qemu/qemu/commit/998eb7448c75b432a13257d019f6866= e604ce43c=0D Author: Eric Farman =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/sigp.c=0D =0D Log Message:=0D -----------=0D s390x: sigp: Force Set Architecture to return Invalid Parameter=0D =0D According to the Principles of Operation, the SIGP Set Architecture=0D order will return Incorrect State if some CPUs are not stopped, but=0D only if the CZAM facility is not present. If it is, the order will=0D return Invalid Parameter because the architecture mode cannot be=0D changed.=0D =0D Since CZAM always exists when S390_FEAT_ZARCH exists, which in turn=0D exists for every defined CPU model, we can simplify this code.=0D =0D Fixes: 075e52b81664 ("s390x/cpumodel: we are always in zarchitecture mode= ")=0D Signed-off-by: Eric Farman =0D Reviewed-by: Christian Borntraeger =0D Reviewed-by: Janosch Frank =0D Message-Id: <20211008203811.1980478-2-farman@linux.ibm.com>=0D Reviewed-by: Thomas Huth =0D Reviewed-by: David Hildenbrand =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: ebbc6034dcfe772473d1d29724b36ce7a9a49ad2=0D https://github.com/qemu/qemu/commit/ebbc6034dcfe772473d1d29724b36ce= 7a9a49ad2=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D vfio-ccw: step down as maintainer=0D =0D I currently don't have time to act as vfio-ccw maintainer anymore,=0D so remove myself there.=0D =0D Signed-off-by: Cornelia Huck =0D Message-Id: <20211012144040.360887-2-cohuck@redhat.com>=0D Acked-by: Matthew Rosato =0D Acked-by: Eric Farman =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 373b2ab35635537c67bb6fe9aa36367f28a067a2=0D https://github.com/qemu/qemu/commit/373b2ab35635537c67bb6fe9aa36367= f28a067a2=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D s390x/kvm: step down as maintainer=0D =0D I'm no longer involved with KVM/s390 on the kernel side, and I don't=0D have enough resources to work on the s390 KVM cpus support, so I'll=0D step down.=0D =0D Signed-off-by: Cornelia Huck =0D Acked-by: Halil Pasic =0D Message-Id: <20211012144040.360887-3-cohuck@redhat.com>=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: afe5c8c5c14aff25fab6ae83957e87c717415be3=0D https://github.com/qemu/qemu/commit/afe5c8c5c14aff25fab6ae83957e87c= 717415be3=0D Author: Cornelia Huck =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D s390x virtio-ccw machine: step down as maintainer=0D =0D I currently don't have time to work on the s390x virtio-ccw machine=0D anymore, so let's step down. (I will, however, continue as a=0D maintainer for the virtio-ccw *transport*.)=0D =0D Signed-off-by: Cornelia Huck =0D Acked-by: Halil Pasic =0D Message-Id: <20211012144040.360887-4-cohuck@redhat.com>=0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 962fde57b7d573281619cb2b7068d570470ef833=0D https://github.com/qemu/qemu/commit/962fde57b7d573281619cb2b7068d57= 0470ef833=0D Author: Thomas Huth =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M dtc=0D =0D Log Message:=0D -----------=0D dtc: Update to version 1.6.1=0D =0D The dtc submodule is currently pointing to non-release commit. It's nicer= =0D if submodules point to release versions instead and since dtc 1.6.1 is=0D= available now, let's update to that version.=0D =0D Message-Id: <20210827120901.150276-4-thuth@redhat.com>=0D Acked-by: Greg Kurz =0D Acked-by: David Gibson =0D Signed-off-by: Thomas Huth =0D =0D =0D Commit: 82d88f834c8f7d33ad9529fca80924bc496fcb70=0D https://github.com/qemu/qemu/commit/82d88f834c8f7d33ad9529fca80924b= c496fcb70=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M dtc=0D M hw/s390x/ipl.c=0D M target/s390x/sigp.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/thuth/tags/pull-request-2021-10-1= 5' into staging=0D =0D * Check kernel command line size on s390x=0D * Simplification of one of the SIGP instructions on s390x=0D * Cornelia stepping down as maintainer in some subsystems=0D * Update the dtc submodule to a proper release version=0D =0D # gpg: Signature made Fri 15 Oct 2021 02:11:13 AM PDT=0D # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702= DB5=0D # gpg: issuer "thuth@redhat.com"=0D # gpg: Good signature from "Thomas Huth " [full]=0D # gpg: aka "Thomas Huth " [full]=0D # gpg: aka "Thomas Huth " [unknown]=0D= # gpg: aka "Thomas Huth " [full]=0D =0D * remotes/thuth/tags/pull-request-2021-10-15:=0D dtc: Update to version 1.6.1=0D s390x virtio-ccw machine: step down as maintainer=0D s390x/kvm: step down as maintainer=0D vfio-ccw: step down as maintainer=0D s390x: sigp: Force Set Architecture to return Invalid Parameter=0D s390x/ipl: check kernel command line size=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/4d1a525dfafe...82d88f834c8f= =0D From MAILER-DAEMON Fri Oct 15 15:15:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbSff-0007VI-I7 for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 15:15:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbSfd-0007Ql-0O for qemu-commits@nongnu.org; Fri, 15 Oct 2021 15:15:09 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:55885 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbSfZ-000407-6R for qemu-commits@nongnu.org; Fri, 15 Oct 2021 15:15:08 -0400 Received: from github.com (hubbernetes-node-042ba19.ac4-iad.github.net [10.52.125.69]) by smtp.github.com (Postfix) with ESMTPA id 30C9C5606F7 for ; Fri, 15 Oct 2021 12:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634325304; bh=O/G4xNpvn/uucO0GJUfp/GK3pI1N9W45rKD9T7USZmM=; h=Date:From:To:Subject:From; b=YMtNhYxBli1qi6WQanVurKpHNXw/9LunJ6C/iOEalMxckcrure8lUS0JtnObQrEwq vIInh1pXLmJut2kNvLr1Mup20V4h5j+aU/wiTK8mpAMZBwUbxT4m+V4y2LAoHF6fiS 12OXguBmObQa4rsWpGxeS7xGOD6p8hQ8kYE1qabA= Date: Fri, 15 Oct 2021 12:15:04 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e287bf: net: Introduce NetClientInfo.check_peer_type() X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 19:15:09 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: e287bf7bb15ffd3728c000d9c5b52460ea17d713 https://github.com/qemu/qemu/commit/e287bf7bb15ffd3728c000d9c5b52460ea17d713 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev-properties-system.c M include/net/net.h Log Message: ----------- net: Introduce NetClientInfo.check_peer_type() Some network backends (vhost-user and vhost-vdpa) work only with specific devices. At startup, they second guess what the command line option handling will do and error out if they think a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Add a callback where backends can check compatibility with a device when it actually tries to attach, even on hotplug. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-2-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 5c485d51c4e2e8b3c78110a1a3f31f789c900d9d https://github.com/qemu/qemu/commit/5c485d51c4e2e8b3c78110a1a3f31f789c900d9d Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M net/vhost-user.c Log Message: ----------- net/vhost-user: Fix device compatibility check vhost-user works only with specific devices. At startup, it second guesses what the command line option handling will do and error out if it thinks a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Drop the old checks and implement .check_peer_type() instead to fix this. As a nice side effect, it also removes one more dependency on the legacy QemuOpts infrastructure and even reduces the code size. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-3-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: ee8a1c63d337a893fa915dd263dfdaa272e1a76a https://github.com/qemu/qemu/commit/ee8a1c63d337a893fa915dd263dfdaa272e1a76a Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M net/vhost-vdpa.c Log Message: ----------- net/vhost-vdpa: Fix device compatibility check vhost-vdpa works only with specific devices. At startup, it second guesses what the command line option handling will do and error out if it thinks a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Drop the old checks and implement .check_peer_type() instead to fix this. As a nice side effect, it also removes one more dependency on the legacy QemuOpts infrastructure and even reduces the code size. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-4-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: dbc8221f8cf3a3004fb6b4d0675f5852758b0388 https://github.com/qemu/qemu/commit/dbc8221f8cf3a3004fb6b4d0675f5852758b0388 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M qom/object.c M qom/object_interfaces.c Log Message: ----------- qom: Reduce use of error_propagate() ERRP_GUARD() makes debugging easier by making sure that &error_abort still fails at the real origin of the error instead of error_propagate(). Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-5-kwolf@redhat.com> Reviewed-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: e2c8eb1454b6aee79077d6d9710ec92d66554e56 https://github.com/qemu/qemu/commit/e2c8eb1454b6aee79077d6d9710ec92d66554e56 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M tests/qemu-iotests/245 Log Message: ----------- iotests/245: Fix type for iothread property iothread is a string property, so None (= JSON null) is not a valid value for it. Pass the empty string instead to get the default iothread. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-6-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: af6400afb89f5eb3f66f841c8ee8c2f6754c8394 https://github.com/qemu/qemu/commit/af6400afb89f5eb3f66f841c8ee8c2f6754c8394 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M tests/qemu-iotests/051 M tests/qemu-iotests/051.pc.out Log Message: ----------- iotests/051: Fix typo The iothread isn't called 'iothread0', but 'thread0'. Depending on the order that properties are parsed, the error message may change from the expected one to another one saying that the iothread doesn't exist. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-7-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: c34efecedd0552ee8b830402241e19daebb22aec https://github.com/qemu/qemu/commit/c34efecedd0552ee8b830402241e19daebb22aec Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M softmmu/qdev-monitor.c Log Message: ----------- qdev: Avoid using string visitor for properties The only thing the string visitor adds compared to a keyval visitor is list support. git grep for 'visit_start_list' and 'visit.*List' shows that devices don't make use of this. In a world with a QAPIfied command line interface, the keyval visitor is used to parse the command line. In order to make sure that no devices start using this feature that would make backwards compatibility harder, just switch away from object_property_parse(), which internally uses the string visitor, to a keyval visitor and object_property_set(). Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Message-Id: <20211008133442.141332-8-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 163f384752dd9125ce7eb1b2edf00b23f0a54557 https://github.com/qemu/qemu/commit/163f384752dd9125ce7eb1b2edf00b23f0a54557 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/arm/virt.c M hw/core/qdev.c M hw/pci-bridge/pci_expander_bridge.c M hw/ppc/e500.c M include/hw/qdev-core.h M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Make DeviceState.id independent of QemuOpts DeviceState.id is a pointer to a string that is stored in the QemuOpts object DeviceState.opts and freed together with it. We want to create devices without going through QemuOpts in the future, so make this a separately allocated string. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-9-kwolf@redhat.com> Reviewed-by: Damien Hedde Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 4a1d937796de0fecd8b22d7dbebf87f38e8282fd https://github.com/qemu/qemu/commit/4a1d937796de0fecd8b22d7dbebf87f38e8282fd Author: Damien Hedde Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/xen/xen-legacy-backend.c M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- softmmu/qdev-monitor: add error handling in qdev_set_id qdev_set_id() is mostly used when the user adds a device (using -device cli option or device_add qmp command). This commit adds an error parameter to handle the case where the given id is already taken. Also document the function and add a return value in order to be able to capture success/failure: the function now returns the id in case of success, or NULL in case of failure. The commit modifies the 2 calling places (qdev-monitor and xen-legacy-backend) to add the error object parameter. Note that the id is, right now, guaranteed to be unique because all ids came from the "device" QemuOptsList where the id is used as key. This addition is a preparation for a future commit which will relax the uniqueness. Signed-off-by: Damien Hedde Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-10-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 30648dd5d609d111e635112d7e6014ca63f7ba13 https://github.com/qemu/qemu/commit/30648dd5d609d111e635112d7e6014ca63f7ba13 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M util/qemu-option.c Log Message: ----------- qemu-option: Allow deleting opts during qemu_opts_foreach() Use QTAILQ_FOREACH_SAFE() so that the current QemuOpts can be deleted while iterating through the whole list. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-11-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 7d61808206cc651ae42024ab6def827afa2f807b https://github.com/qemu/qemu/commit/7d61808206cc651ae42024ab6def827afa2f807b Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev.c M hw/net/virtio-net.c M include/hw/qdev-core.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Add Error parameter to hide_device() callbacks hide_device() is used for virtio-net failover, where the standby virtio device delays creation of the primary device. It only makes sense to have a single primary device for each standby device. Adding a second one should result in an error instead of hiding it and never using it afterwards. Prepare for this by adding an Error parameter to the hide_device() callback where virtio-net is informed about adding a primary device. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-12-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 259a10dbcb4f36a3489fb52f9f7a654761589448 https://github.com/qemu/qemu/commit/259a10dbcb4f36a3489fb52f9f7a654761589448 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/net/virtio-net.c M include/hw/virtio/virtio-net.h Log Message: ----------- virtio-net: Store failover primary opts pointer locally Instead of accessing the global QemuOptsList, which really belong to the command line parser and shouldn't be accessed from devices, store a pointer to the QemuOpts in a new VirtIONet field. This is not the final state, but just an intermediate step to get rid of QemuOpts in devices. It will later be replaced with an options QDict. Before this patch, two "primary" devices could be hidden for the same standby device, but only one of them would actually be enabled and the other one would be kept hidden forever, so this doesn't make sense. After this patch, configuring a second primary device is an error. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-13-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 12b2fad7dcc8d08b6a59d1b14caa392ea614c6d9 https://github.com/qemu/qemu/commit/12b2fad7dcc8d08b6a59d1b14caa392ea614c6d9 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/net/virtio-net.c Log Message: ----------- virtio-net: Avoid QemuOpts in failover_find_primary_device() Don't go through the global QemuOptsList, it is state of the legacy command line parser and we will create devices that are not contained in it. It is also just the command line configuration and not necessarily the current runtime state. Instead, look at the qdev device tree which has the current state of all existing devices. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-14-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: f3558b1b763683bb877f7dd5b282469cdadc65c3 https://github.com/qemu/qemu/commit/f3558b1b763683bb877f7dd5b282469cdadc65c3 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev.c M hw/net/virtio-net.c M hw/vfio/pci.c M include/hw/qdev-core.h M include/hw/virtio/virtio-net.h M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Base object creation on QDict rather than QemuOpts QDicts are both what QMP natively uses and what the keyval parser produces. Going through QemuOpts isn't useful for either one, so switch the main device creation function to QDicts. By sharing more code with the -object/object-add code path, we can even reduce the code size a bit. This commit doesn't remove the detour through QemuOpts from any code path yet, but it allows the following commits to do so. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-15-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 5dacda5167560b3af8eadbce5814f60ba44b467e https://github.com/qemu/qemu/commit/5dacda5167560b3af8eadbce5814f60ba44b467e Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M qapi/qdev.json M softmmu/vl.c Log Message: ----------- vl: Enable JSON syntax for -device Like we already do for -object, introduce support for JSON syntax in -device, which can be kept stable in the long term and guarantees that a single code path with identical behaviour is used for both QMP and the command line. Compared to the QemuOpts based code, the parser contains less surprises and has support for non-scalar options (lists and structs). Switching management tools to JSON means that we can more easily change the "human" CLI syntax from QemuOpts to the keyval parser later. In the QAPI schema, a feature flag is added to the device-add command to allow management tools to detect support for this. Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Message-Id: <20211008133442.141332-16-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 253e399bab7c83b3411f8eac01840283a9304cb3 https://github.com/qemu/qemu/commit/253e399bab7c83b3411f8eac01840283a9304cb3 Author: Richard Henderson Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/arm/virt.c M hw/core/qdev-properties-system.c M hw/core/qdev.c M hw/net/virtio-net.c M hw/pci-bridge/pci_expander_bridge.c M hw/ppc/e500.c M hw/vfio/pci.c M hw/xen/xen-legacy-backend.c M include/hw/qdev-core.h M include/hw/virtio/virtio-net.h M include/monitor/qdev.h M include/net/net.h M net/vhost-user.c M net/vhost-vdpa.c M qapi/qdev.json M qom/object.c M qom/object_interfaces.c M softmmu/qdev-monitor.c M softmmu/vl.c M tests/qemu-iotests/051 M tests/qemu-iotests/051.pc.out M tests/qemu-iotests/245 M util/qemu-option.c Log Message: ----------- Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging qdev: Add JSON -device - Add a JSON mode to the -device command line option - net/vhost-{user,vdpa}: Fix device compatibility check - Minor iotests fixes # gpg: Signature made Fri 15 Oct 2021 07:41:22 AM PDT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf " [full] * remotes/kwolf/tags/for-upstream: vl: Enable JSON syntax for -device qdev: Base object creation on QDict rather than QemuOpts virtio-net: Avoid QemuOpts in failover_find_primary_device() virtio-net: Store failover primary opts pointer locally qdev: Add Error parameter to hide_device() callbacks qemu-option: Allow deleting opts during qemu_opts_foreach() softmmu/qdev-monitor: add error handling in qdev_set_id qdev: Make DeviceState.id independent of QemuOpts qdev: Avoid using string visitor for properties iotests/051: Fix typo iotests/245: Fix type for iothread property qom: Reduce use of error_propagate() net/vhost-vdpa: Fix device compatibility check net/vhost-user: Fix device compatibility check net: Introduce NetClientInfo.check_peer_type() Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/82d88f834c8f...253e399bab7c From MAILER-DAEMON Fri Oct 15 16:26:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbTmQ-00034E-Dn for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 16:26:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbTmP-00033k-5g for qemu-commits@nongnu.org; Fri, 15 Oct 2021 16:26:13 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:51005 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbTmM-0000xj-6t for qemu-commits@nongnu.org; Fri, 15 Oct 2021 16:26:12 -0400 Received: from github.com (hubbernetes-node-d46ae33.ash1-iad.github.net [10.56.113.33]) by smtp.github.com (Postfix) with ESMTPA id 767EF8404F1 for ; Fri, 15 Oct 2021 13:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634329569; bh=N1w72H+tSBolPXz6AdwQWF4YO8xiwAya+ZNzmNFJ/eA=; h=Date:From:To:Subject:From; b=GIvOoMZHlV52GWkh4pnkbUgmneuCiY+ivSsBtdNUMbmrnAeoHlMWeIRBIrH9VqNLE gikJAaibm5sKGctD/6O9npaKlMSxOWwZGDVE4sY2fakM400uhYlTOoka2Fg6zBwBlk I5HJUzkMEN8j1MSY9Kf5W7imLE220EJnRUfiMOHE= Date: Fri, 15 Oct 2021 13:26:09 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e287bf: net: Introduce NetClientInfo.check_peer_type() X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 20:26:13 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: e287bf7bb15ffd3728c000d9c5b52460ea17d713 https://github.com/qemu/qemu/commit/e287bf7bb15ffd3728c000d9c5b52460ea17d713 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev-properties-system.c M include/net/net.h Log Message: ----------- net: Introduce NetClientInfo.check_peer_type() Some network backends (vhost-user and vhost-vdpa) work only with specific devices. At startup, they second guess what the command line option handling will do and error out if they think a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Add a callback where backends can check compatibility with a device when it actually tries to attach, even on hotplug. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-2-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 5c485d51c4e2e8b3c78110a1a3f31f789c900d9d https://github.com/qemu/qemu/commit/5c485d51c4e2e8b3c78110a1a3f31f789c900d9d Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M net/vhost-user.c Log Message: ----------- net/vhost-user: Fix device compatibility check vhost-user works only with specific devices. At startup, it second guesses what the command line option handling will do and error out if it thinks a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Drop the old checks and implement .check_peer_type() instead to fix this. As a nice side effect, it also removes one more dependency on the legacy QemuOpts infrastructure and even reduces the code size. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-3-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: ee8a1c63d337a893fa915dd263dfdaa272e1a76a https://github.com/qemu/qemu/commit/ee8a1c63d337a893fa915dd263dfdaa272e1a76a Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M net/vhost-vdpa.c Log Message: ----------- net/vhost-vdpa: Fix device compatibility check vhost-vdpa works only with specific devices. At startup, it second guesses what the command line option handling will do and error out if it thinks a non-virtio device will attach to them. This second guessing is not only ugly, it can lead to wrong error messages ('-device floppy,netdev=foo' should complain about an unknown property, not about the wrong kind of network device being attached) and completely ignores hotplugging. Drop the old checks and implement .check_peer_type() instead to fix this. As a nice side effect, it also removes one more dependency on the legacy QemuOpts infrastructure and even reduces the code size. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-4-kwolf@redhat.com> Reviewed-by: Damien Hedde Acked-by: Jason Wang Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: dbc8221f8cf3a3004fb6b4d0675f5852758b0388 https://github.com/qemu/qemu/commit/dbc8221f8cf3a3004fb6b4d0675f5852758b0388 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M qom/object.c M qom/object_interfaces.c Log Message: ----------- qom: Reduce use of error_propagate() ERRP_GUARD() makes debugging easier by making sure that &error_abort still fails at the real origin of the error instead of error_propagate(). Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-5-kwolf@redhat.com> Reviewed-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: e2c8eb1454b6aee79077d6d9710ec92d66554e56 https://github.com/qemu/qemu/commit/e2c8eb1454b6aee79077d6d9710ec92d66554e56 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M tests/qemu-iotests/245 Log Message: ----------- iotests/245: Fix type for iothread property iothread is a string property, so None (= JSON null) is not a valid value for it. Pass the empty string instead to get the default iothread. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-6-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: af6400afb89f5eb3f66f841c8ee8c2f6754c8394 https://github.com/qemu/qemu/commit/af6400afb89f5eb3f66f841c8ee8c2f6754c8394 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M tests/qemu-iotests/051 M tests/qemu-iotests/051.pc.out Log Message: ----------- iotests/051: Fix typo The iothread isn't called 'iothread0', but 'thread0'. Depending on the order that properties are parsed, the error message may change from the expected one to another one saying that the iothread doesn't exist. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-7-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: c34efecedd0552ee8b830402241e19daebb22aec https://github.com/qemu/qemu/commit/c34efecedd0552ee8b830402241e19daebb22aec Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M softmmu/qdev-monitor.c Log Message: ----------- qdev: Avoid using string visitor for properties The only thing the string visitor adds compared to a keyval visitor is list support. git grep for 'visit_start_list' and 'visit.*List' shows that devices don't make use of this. In a world with a QAPIfied command line interface, the keyval visitor is used to parse the command line. In order to make sure that no devices start using this feature that would make backwards compatibility harder, just switch away from object_property_parse(), which internally uses the string visitor, to a keyval visitor and object_property_set(). Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Message-Id: <20211008133442.141332-8-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 163f384752dd9125ce7eb1b2edf00b23f0a54557 https://github.com/qemu/qemu/commit/163f384752dd9125ce7eb1b2edf00b23f0a54557 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/arm/virt.c M hw/core/qdev.c M hw/pci-bridge/pci_expander_bridge.c M hw/ppc/e500.c M include/hw/qdev-core.h M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Make DeviceState.id independent of QemuOpts DeviceState.id is a pointer to a string that is stored in the QemuOpts object DeviceState.opts and freed together with it. We want to create devices without going through QemuOpts in the future, so make this a separately allocated string. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-9-kwolf@redhat.com> Reviewed-by: Damien Hedde Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 4a1d937796de0fecd8b22d7dbebf87f38e8282fd https://github.com/qemu/qemu/commit/4a1d937796de0fecd8b22d7dbebf87f38e8282fd Author: Damien Hedde Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/xen/xen-legacy-backend.c M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- softmmu/qdev-monitor: add error handling in qdev_set_id qdev_set_id() is mostly used when the user adds a device (using -device cli option or device_add qmp command). This commit adds an error parameter to handle the case where the given id is already taken. Also document the function and add a return value in order to be able to capture success/failure: the function now returns the id in case of success, or NULL in case of failure. The commit modifies the 2 calling places (qdev-monitor and xen-legacy-backend) to add the error object parameter. Note that the id is, right now, guaranteed to be unique because all ids came from the "device" QemuOptsList where the id is used as key. This addition is a preparation for a future commit which will relax the uniqueness. Signed-off-by: Damien Hedde Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-10-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 30648dd5d609d111e635112d7e6014ca63f7ba13 https://github.com/qemu/qemu/commit/30648dd5d609d111e635112d7e6014ca63f7ba13 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M util/qemu-option.c Log Message: ----------- qemu-option: Allow deleting opts during qemu_opts_foreach() Use QTAILQ_FOREACH_SAFE() so that the current QemuOpts can be deleted while iterating through the whole list. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211008133442.141332-11-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 7d61808206cc651ae42024ab6def827afa2f807b https://github.com/qemu/qemu/commit/7d61808206cc651ae42024ab6def827afa2f807b Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev.c M hw/net/virtio-net.c M include/hw/qdev-core.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Add Error parameter to hide_device() callbacks hide_device() is used for virtio-net failover, where the standby virtio device delays creation of the primary device. It only makes sense to have a single primary device for each standby device. Adding a second one should result in an error instead of hiding it and never using it afterwards. Prepare for this by adding an Error parameter to the hide_device() callback where virtio-net is informed about adding a primary device. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-12-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 259a10dbcb4f36a3489fb52f9f7a654761589448 https://github.com/qemu/qemu/commit/259a10dbcb4f36a3489fb52f9f7a654761589448 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/net/virtio-net.c M include/hw/virtio/virtio-net.h Log Message: ----------- virtio-net: Store failover primary opts pointer locally Instead of accessing the global QemuOptsList, which really belong to the command line parser and shouldn't be accessed from devices, store a pointer to the QemuOpts in a new VirtIONet field. This is not the final state, but just an intermediate step to get rid of QemuOpts in devices. It will later be replaced with an options QDict. Before this patch, two "primary" devices could be hidden for the same standby device, but only one of them would actually be enabled and the other one would be kept hidden forever, so this doesn't make sense. After this patch, configuring a second primary device is an error. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-13-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 12b2fad7dcc8d08b6a59d1b14caa392ea614c6d9 https://github.com/qemu/qemu/commit/12b2fad7dcc8d08b6a59d1b14caa392ea614c6d9 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/net/virtio-net.c Log Message: ----------- virtio-net: Avoid QemuOpts in failover_find_primary_device() Don't go through the global QemuOptsList, it is state of the legacy command line parser and we will create devices that are not contained in it. It is also just the command line configuration and not necessarily the current runtime state. Instead, look at the qdev device tree which has the current state of all existing devices. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-14-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: f3558b1b763683bb877f7dd5b282469cdadc65c3 https://github.com/qemu/qemu/commit/f3558b1b763683bb877f7dd5b282469cdadc65c3 Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/core/qdev.c M hw/net/virtio-net.c M hw/vfio/pci.c M include/hw/qdev-core.h M include/hw/virtio/virtio-net.h M include/monitor/qdev.h M softmmu/qdev-monitor.c Log Message: ----------- qdev: Base object creation on QDict rather than QemuOpts QDicts are both what QMP natively uses and what the keyval parser produces. Going through QemuOpts isn't useful for either one, so switch the main device creation function to QDicts. By sharing more code with the -object/object-add code path, we can even reduce the code size a bit. This commit doesn't remove the detour through QemuOpts from any code path yet, but it allows the following commits to do so. Signed-off-by: Kevin Wolf Message-Id: <20211008133442.141332-15-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 5dacda5167560b3af8eadbce5814f60ba44b467e https://github.com/qemu/qemu/commit/5dacda5167560b3af8eadbce5814f60ba44b467e Author: Kevin Wolf Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M qapi/qdev.json M softmmu/vl.c Log Message: ----------- vl: Enable JSON syntax for -device Like we already do for -object, introduce support for JSON syntax in -device, which can be kept stable in the long term and guarantees that a single code path with identical behaviour is used for both QMP and the command line. Compared to the QemuOpts based code, the parser contains less surprises and has support for non-scalar options (lists and structs). Switching management tools to JSON means that we can more easily change the "human" CLI syntax from QemuOpts to the keyval parser later. In the QAPI schema, a feature flag is added to the device-add command to allow management tools to detect support for this. Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Message-Id: <20211008133442.141332-16-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin Tested-by: Peter Krempa Signed-off-by: Kevin Wolf Commit: 253e399bab7c83b3411f8eac01840283a9304cb3 https://github.com/qemu/qemu/commit/253e399bab7c83b3411f8eac01840283a9304cb3 Author: Richard Henderson Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M hw/arm/virt.c M hw/core/qdev-properties-system.c M hw/core/qdev.c M hw/net/virtio-net.c M hw/pci-bridge/pci_expander_bridge.c M hw/ppc/e500.c M hw/vfio/pci.c M hw/xen/xen-legacy-backend.c M include/hw/qdev-core.h M include/hw/virtio/virtio-net.h M include/monitor/qdev.h M include/net/net.h M net/vhost-user.c M net/vhost-vdpa.c M qapi/qdev.json M qom/object.c M qom/object_interfaces.c M softmmu/qdev-monitor.c M softmmu/vl.c M tests/qemu-iotests/051 M tests/qemu-iotests/051.pc.out M tests/qemu-iotests/245 M util/qemu-option.c Log Message: ----------- Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging qdev: Add JSON -device - Add a JSON mode to the -device command line option - net/vhost-{user,vdpa}: Fix device compatibility check - Minor iotests fixes # gpg: Signature made Fri 15 Oct 2021 07:41:22 AM PDT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf " [full] * remotes/kwolf/tags/for-upstream: vl: Enable JSON syntax for -device qdev: Base object creation on QDict rather than QemuOpts virtio-net: Avoid QemuOpts in failover_find_primary_device() virtio-net: Store failover primary opts pointer locally qdev: Add Error parameter to hide_device() callbacks qemu-option: Allow deleting opts during qemu_opts_foreach() softmmu/qdev-monitor: add error handling in qdev_set_id qdev: Make DeviceState.id independent of QemuOpts qdev: Avoid using string visitor for properties iotests/051: Fix typo iotests/245: Fix type for iothread property qom: Reduce use of error_propagate() net/vhost-vdpa: Fix device compatibility check net/vhost-user: Fix device compatibility check net: Introduce NetClientInfo.check_peer_type() Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/82d88f834c8f...253e399bab7c From MAILER-DAEMON Fri Oct 15 17:18:35 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbUb2-0004d1-Kt for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 17:18:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbUb0-0004Wn-Ft for qemu-commits@nongnu.org; Fri, 15 Oct 2021 17:18:30 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:42317) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbUax-0004qI-Ms for qemu-commits@nongnu.org; Fri, 15 Oct 2021 17:18:30 -0400 Received: from github.com (hubbernetes-node-2b0cb0b.ac4-iad.github.net [10.52.205.45]) by smtp.github.com (Postfix) with ESMTPA id AE7AE600A4F for ; Fri, 15 Oct 2021 14:18:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634332706; bh=PhO8mgDmWeH/vkrqod+QK/a3afs4MXvnfWDxuMEY7UY=; h=Date:From:To:Subject:From; b=1L3VzvMT7c8AGG35/AVTPCB2rRkf6qktoNQFb/gUUCklr5QmrrbU7ji6E9fWFI8ch VgntUfIj184UjT/QXN/tsmVptiwyI7H2CD9cLns/rjJ+kX1U0KTekpfZdJhL8HCsX+ EEQZhbzKwyOXvhu2h1guOhscwiXHfnqYgZKay59o= Date: Fri, 15 Oct 2021 14:18:26 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e7e588: qcow2: Silence clang -m32 compiler warning X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 21:18:31 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: e7e588d432d31ecebc26358e47201dd108db964c https://github.com/qemu/qemu/commit/e7e588d432d31ecebc26358e47201dd108db964c Author: Hanna Reitz Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/qcow2-cluster.c Log Message: ----------- qcow2: Silence clang -m32 compiler warning With -m32, size_t is generally only a uint32_t. That makes clang complain that in the assertion assert(qiov->size <= INT64_MAX); the range of the type of qiov->size (size_t) is too small for any of its values to ever exceed INT64_MAX. Cast qiov->size to uint64_t to silence clang. Fixes: f7ef38dd1310d7d9db76d0aa16899cbc5744f36d ("block: use int64_t instead of uint64_t in driver read handlers") Signed-off-by: Hanna Reitz Message-Id: <20211011155031.149158-1-hreitz@redhat.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 7242db6389261cb936bd2240351b137843d49807 https://github.com/qemu/qemu/commit/7242db6389261cb936bd2240351b137843d49807 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: blk_check_byte_request(): int64_t bytes Rename size and make it int64_t to correspond to modern block layer, which always uses int64_t for offset and bytes (not in blk layer yet, which is a task for following commits). All callers pass int or unsigned int. So, for bytes in [0, INT_MAX] nothing is changed, for negative bytes we now fail on "bytes < 0" check instead of "bytes > INT_MAX" check. Note, that blk_check_byte_request() still doesn't allow requests exceeding INT_MAX. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 9547907705c94fa0415427ce12be418f8b68b56d https://github.com/qemu/qemu/commit/9547907705c94fa0415427ce12be418f8b68b56d Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/trace-events M include/sysemu/block-backend.h Log Message: ----------- block-backend: make blk_co_preadv() 64bit For both updated functions, the type of bytes becomes wider, so all callers should be OK with it. blk_co_preadv() only passes its arguments to blk_do_preadv(). blk_do_preadv() passes bytes to: - trace_blk_co_preadv, which is updated too - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_preadv, which are already int64_t. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-3-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 34460feb63230daad12b0e0f31754f7ef5bc2be9 https://github.com/qemu/qemu/commit/34460feb63230daad12b0e0f31754f7ef5bc2be9 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/trace-events M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_pwritev_part to int64_t bytes We convert blk_do_pwritev_part() and some wrappers: blk_co_pwritev_part(), blk_co_pwritev(), blk_co_pwrite_zeroes(). All functions are converted so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pwritev_part() body: bytes is passed to: - trace_blk_co_pwritev (we update it here) - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_pwritev_part - all already have int64_t argument. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-4-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 2800637a33b0ff68c40c94a1d3d13f92feaadbc6 https://github.com/qemu/qemu/commit/2800637a33b0ff68c40c94a1d3d13f92feaadbc6 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_pdiscard to int64_t bytes We updated blk_do_pdiscard() and its wrapper blk_co_pdiscard(). Both functions are updated so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pdiscard(): bytes is passed only to blk_check_byte_request() and bdrv_co_pdiscard(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-5-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 70e8775ed9e46cb4fab8013627df4dd835a1c24c https://github.com/qemu/qemu/commit/70e8775ed9e46cb4fab8013627df4dd835a1c24c Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: rename _do_ helper functions to _co_do_ This is a preparation to the following commit, to use automatic coroutine wrapper generation. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-6-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 7d55a3bbadc0b00ff6c2a4f37116db887caec7ab https://github.com/qemu/qemu/commit/7d55a3bbadc0b00ff6c2a4f37116db887caec7ab Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/coroutines.h M scripts/block-coroutine-wrapper.py Log Message: ----------- block-coroutine-wrapper.py: support BlockBackend first argument Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-7-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 16d36e299669145f3021f2912aefbc32d7f0593c https://github.com/qemu/qemu/commit/16d36e299669145f3021f2912aefbc32d7f0593c Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/coroutines.h Log Message: ----------- block-backend: drop blk_prw, use block-coroutine-wrapper Let's drop hand-made coroutine wrappers and use coroutine wrapper generation like in block/io.c. Now, blk_foo() functions are written in same way as blk_co_foo() ones, but wrap blk_do_foo() instead of blk_co_do_foo(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-8-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: spelling fix] Signed-off-by: Eric Blake Commit: 06f0325c5b62f80bab1c9eb50edc814158d6005e https://github.com/qemu/qemu/commit/06f0325c5b62f80bab1c9eb50edc814158d6005e Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_foo wrappers to use int64_t bytes parameter Convert blk_pdiscard, blk_pwrite_compressed, blk_pwrite_zeroes. These are just wrappers for functions with int64_t argument, so allow passing int64_t as well. Parameter type becomes wider so all callers should be OK with it. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Note also that we don't (and are not going to) convert blk_pwrite and blk_pread: these functions return number of bytes on success, so to update them, we should change return type to int64_t as well, which will lead to investigating and updating all callers which is too much. So, blk_pread and blk_pwrite remain unchanged. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-9-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: e192179bb2c080f0130a7ff427c2572909fc31ed https://github.com/qemu/qemu/commit/e192179bb2c080f0130a7ff427c2572909fc31ed Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_copy_range to int64_t bytes Function is updated so that parameter type becomes wider, so all callers should be OK with it. Look at blk_co_copy_range() itself: bytes is passed only to blk_check_byte_request() and bdrv_co_copy_range(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-10-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5 https://github.com/qemu/qemu/commit/a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_aio_ functions to int64_t bytes paramter 1. Convert bytes in BlkAioEmAIOCB: aio->bytes is only passed to already int64_t interfaces, and set in blk_aio_prwv, which is updated here. 2. For all updated functions the parameter type becomes wider so callers are safe. 3. In blk_aio_prwv we only store bytes to BlkAioEmAIOCB, which is updated here. 4. Other updated functions are wrappers on blk_aio_prwv. Note that blk_aio_preadv and blk_aio_pwritev become safer: before this commit, it's theoretically possible to pass qiov with size exceeding INT_MAX, which than converted to int argument of blk_aio_prwv. Now it's converted to int64_t which is a lot better. Still add assertions. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-11-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: tweak assertion and grammar] Signed-off-by: Eric Blake Commit: 14149710f98fcf7af13eeb6cf6040b33c01b9792 https://github.com/qemu/qemu/commit/14149710f98fcf7af13eeb6cf6040b33c01b9792 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: blk_pread, blk_pwrite: rename count parameter to bytes To be consistent with declarations in include/sysemu/block-backend.h. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-12-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: aa78b825162163d2c51903490d67c10a689eac6b https://github.com/qemu/qemu/commit/aa78b825162163d2c51903490d67c10a689eac6b Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: drop INT_MAX restriction from blk_check_byte_request() blk_check_bytes_request is called from blk_co_do_preadv, blk_co_do_pwritev_part, blk_co_do_pdiscard and blk_co_copy_range before (maybe) calling throttle_group_co_io_limits_intercept() (which has int64_t argument) and then calling corresponding bdrv_co_ function. bdrv_co_ functions are OK with int64_t bytes as well. So dropping the check for INT_MAX we just get same restrictions as in bdrv_ layer: discard and write-zeroes goes through bdrv_check_qiov_request() and are allowed to be 64bit. Other requests go through bdrv_check_request32() and still restricted by INT_MAX boundary. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-13-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 57768ec166493260494b76a2fa9fea980ca30e18 https://github.com/qemu/qemu/commit/57768ec166493260494b76a2fa9fea980ca30e18 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M include/sysemu/block-backend.h Log Message: ----------- block-backend: fix blk_co_flush prototype to mention coroutine_fn We already have this marker for the blk_co_flush function declaration in block/block-backend.c. Add it in the header too. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211007175243.642516-1-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: wording tweak] Signed-off-by: Eric Blake Commit: bec4042baefc1bfeae05b161aa17d2f57d526b60 https://github.com/qemu/qemu/commit/bec4042baefc1bfeae05b161aa17d2f57d526b60 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M include/sysemu/block-backend.h Log Message: ----------- block-backend: update blk_co_pwrite() and blk_co_pread() wrappers Make bytes argument int64_t to be consistent with modern block-layer. Callers should be OK with it as type becomes wider. What is inside functions? - Conversion from int64_t to size_t. Still, we can't have a buffer larger than SIZE_MAX, therefore bytes should not be larger than SIZE_MAX as well. Add an assertion. - Passing to blk_co_pwritev() / blk_co_preadv() which already has int64_t bytes argument. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211007175243.642516-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: spelling fix] Signed-off-by: Eric Blake Commit: 6587b0c1331d427b0939c37e763842550ed581db https://github.com/qemu/qemu/commit/6587b0c1331d427b0939c37e763842550ed581db Author: Richard Henderson Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/coroutines.h M block/qcow2-cluster.c M block/trace-events M include/sysemu/block-backend.h M scripts/block-coroutine-wrapper.py Log Message: ----------- Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging nbd patches for 2021-10-15 - Vladimir Sementsov-Ogievskiy: Consistent use of 64-bit parameters in block operations - Hanna Reitz: Silence 32-bit compiler warning # gpg: Signature made Fri 15 Oct 2021 02:08:10 PM PDT # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake " [full] # gpg: aka "Eric Blake (Free Software Programmer) " [full] # gpg: aka "[jpeg image of size 6874]" [full] * remotes/ericb/tags/pull-nbd-2021-10-15: block-backend: update blk_co_pwrite() and blk_co_pread() wrappers block-backend: fix blk_co_flush prototype to mention coroutine_fn block-backend: drop INT_MAX restriction from blk_check_byte_request() block-backend: blk_pread, blk_pwrite: rename count parameter to bytes block-backend: convert blk_aio_ functions to int64_t bytes paramter block-backend: convert blk_co_copy_range to int64_t bytes block-backend: convert blk_foo wrappers to use int64_t bytes parameter block-backend: drop blk_prw, use block-coroutine-wrapper block-coroutine-wrapper.py: support BlockBackend first argument block-backend: rename _do_ helper functions to _co_do_ block-backend: convert blk_co_pdiscard to int64_t bytes block-backend: convert blk_co_pwritev_part to int64_t bytes block-backend: make blk_co_preadv() 64bit block-backend: blk_check_byte_request(): int64_t bytes qcow2: Silence clang -m32 compiler warning Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/253e399bab7c...6587b0c1331d From MAILER-DAEMON Fri Oct 15 18:49:56 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbW1U-0004fO-Mf for mharc-qemu-commits@gnu.org; Fri, 15 Oct 2021 18:49:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbW1T-0004ew-EE for qemu-commits@nongnu.org; Fri, 15 Oct 2021 18:49:55 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:37459 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbW1Q-0007N8-AF for qemu-commits@nongnu.org; Fri, 15 Oct 2021 18:49:54 -0400 Received: from github.com (hubbernetes-node-e5c3a37.va3-iad.github.net [10.48.210.33]) by smtp.github.com (Postfix) with ESMTPA id 72EFF5C00A0 for ; Fri, 15 Oct 2021 15:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634338191; bh=88hVqBSpJOMLQib9nrjuk/XDoL760Cwkh+barS+qlVg=; h=Date:From:To:Subject:From; b=DjCsipEHunnpWqVx+EYCR1qn/BFaT9ol46ypCX79aUXnmEmZoPsfHRXhF7xhEiCoI 7ywKNGOzFEbkXqulG8VMk+xRF97c3pFl6qU2l5eBG7E+iIX4Gu4xVbMxexKTw4ihHM 5yzMLs6OmG4h41W0fTRdGaGeoEnMI2qI1FdbxSWs= Date: Fri, 15 Oct 2021 15:49:51 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e7e588: qcow2: Silence clang -m32 compiler warning X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 22:49:55 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: e7e588d432d31ecebc26358e47201dd108db964c https://github.com/qemu/qemu/commit/e7e588d432d31ecebc26358e47201dd108db964c Author: Hanna Reitz Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/qcow2-cluster.c Log Message: ----------- qcow2: Silence clang -m32 compiler warning With -m32, size_t is generally only a uint32_t. That makes clang complain that in the assertion assert(qiov->size <= INT64_MAX); the range of the type of qiov->size (size_t) is too small for any of its values to ever exceed INT64_MAX. Cast qiov->size to uint64_t to silence clang. Fixes: f7ef38dd1310d7d9db76d0aa16899cbc5744f36d ("block: use int64_t instead of uint64_t in driver read handlers") Signed-off-by: Hanna Reitz Message-Id: <20211011155031.149158-1-hreitz@redhat.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 7242db6389261cb936bd2240351b137843d49807 https://github.com/qemu/qemu/commit/7242db6389261cb936bd2240351b137843d49807 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: blk_check_byte_request(): int64_t bytes Rename size and make it int64_t to correspond to modern block layer, which always uses int64_t for offset and bytes (not in blk layer yet, which is a task for following commits). All callers pass int or unsigned int. So, for bytes in [0, INT_MAX] nothing is changed, for negative bytes we now fail on "bytes < 0" check instead of "bytes > INT_MAX" check. Note, that blk_check_byte_request() still doesn't allow requests exceeding INT_MAX. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 9547907705c94fa0415427ce12be418f8b68b56d https://github.com/qemu/qemu/commit/9547907705c94fa0415427ce12be418f8b68b56d Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/trace-events M include/sysemu/block-backend.h Log Message: ----------- block-backend: make blk_co_preadv() 64bit For both updated functions, the type of bytes becomes wider, so all callers should be OK with it. blk_co_preadv() only passes its arguments to blk_do_preadv(). blk_do_preadv() passes bytes to: - trace_blk_co_preadv, which is updated too - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_preadv, which are already int64_t. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-3-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 34460feb63230daad12b0e0f31754f7ef5bc2be9 https://github.com/qemu/qemu/commit/34460feb63230daad12b0e0f31754f7ef5bc2be9 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/trace-events M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_pwritev_part to int64_t bytes We convert blk_do_pwritev_part() and some wrappers: blk_co_pwritev_part(), blk_co_pwritev(), blk_co_pwrite_zeroes(). All functions are converted so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pwritev_part() body: bytes is passed to: - trace_blk_co_pwritev (we update it here) - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_pwritev_part - all already have int64_t argument. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-4-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 2800637a33b0ff68c40c94a1d3d13f92feaadbc6 https://github.com/qemu/qemu/commit/2800637a33b0ff68c40c94a1d3d13f92feaadbc6 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_pdiscard to int64_t bytes We updated blk_do_pdiscard() and its wrapper blk_co_pdiscard(). Both functions are updated so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pdiscard(): bytes is passed only to blk_check_byte_request() and bdrv_co_pdiscard(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-5-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: 70e8775ed9e46cb4fab8013627df4dd835a1c24c https://github.com/qemu/qemu/commit/70e8775ed9e46cb4fab8013627df4dd835a1c24c Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: rename _do_ helper functions to _co_do_ This is a preparation to the following commit, to use automatic coroutine wrapper generation. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-6-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 7d55a3bbadc0b00ff6c2a4f37116db887caec7ab https://github.com/qemu/qemu/commit/7d55a3bbadc0b00ff6c2a4f37116db887caec7ab Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/coroutines.h M scripts/block-coroutine-wrapper.py Log Message: ----------- block-coroutine-wrapper.py: support BlockBackend first argument Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-7-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 16d36e299669145f3021f2912aefbc32d7f0593c https://github.com/qemu/qemu/commit/16d36e299669145f3021f2912aefbc32d7f0593c Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/coroutines.h Log Message: ----------- block-backend: drop blk_prw, use block-coroutine-wrapper Let's drop hand-made coroutine wrappers and use coroutine wrapper generation like in block/io.c. Now, blk_foo() functions are written in same way as blk_co_foo() ones, but wrap blk_do_foo() instead of blk_co_do_foo(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-8-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: spelling fix] Signed-off-by: Eric Blake Commit: 06f0325c5b62f80bab1c9eb50edc814158d6005e https://github.com/qemu/qemu/commit/06f0325c5b62f80bab1c9eb50edc814158d6005e Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_foo wrappers to use int64_t bytes parameter Convert blk_pdiscard, blk_pwrite_compressed, blk_pwrite_zeroes. These are just wrappers for functions with int64_t argument, so allow passing int64_t as well. Parameter type becomes wider so all callers should be OK with it. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Note also that we don't (and are not going to) convert blk_pwrite and blk_pread: these functions return number of bytes on success, so to update them, we should change return type to int64_t as well, which will lead to investigating and updating all callers which is too much. So, blk_pread and blk_pwrite remain unchanged. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-9-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: e192179bb2c080f0130a7ff427c2572909fc31ed https://github.com/qemu/qemu/commit/e192179bb2c080f0130a7ff427c2572909fc31ed Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_co_copy_range to int64_t bytes Function is updated so that parameter type becomes wider, so all callers should be OK with it. Look at blk_co_copy_range() itself: bytes is passed only to blk_check_byte_request() and bdrv_co_copy_range(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-10-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: grammar tweaks] Signed-off-by: Eric Blake Commit: a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5 https://github.com/qemu/qemu/commit/a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M include/sysemu/block-backend.h Log Message: ----------- block-backend: convert blk_aio_ functions to int64_t bytes paramter 1. Convert bytes in BlkAioEmAIOCB: aio->bytes is only passed to already int64_t interfaces, and set in blk_aio_prwv, which is updated here. 2. For all updated functions the parameter type becomes wider so callers are safe. 3. In blk_aio_prwv we only store bytes to BlkAioEmAIOCB, which is updated here. 4. Other updated functions are wrappers on blk_aio_prwv. Note that blk_aio_preadv and blk_aio_pwritev become safer: before this commit, it's theoretically possible to pass qiov with size exceeding INT_MAX, which than converted to int argument of blk_aio_prwv. Now it's converted to int64_t which is a lot better. Still add assertions. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-11-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: tweak assertion and grammar] Signed-off-by: Eric Blake Commit: 14149710f98fcf7af13eeb6cf6040b33c01b9792 https://github.com/qemu/qemu/commit/14149710f98fcf7af13eeb6cf6040b33c01b9792 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: blk_pread, blk_pwrite: rename count parameter to bytes To be consistent with declarations in include/sysemu/block-backend.h. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-12-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: aa78b825162163d2c51903490d67c10a689eac6b https://github.com/qemu/qemu/commit/aa78b825162163d2c51903490d67c10a689eac6b Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c Log Message: ----------- block-backend: drop INT_MAX restriction from blk_check_byte_request() blk_check_bytes_request is called from blk_co_do_preadv, blk_co_do_pwritev_part, blk_co_do_pdiscard and blk_co_copy_range before (maybe) calling throttle_group_co_io_limits_intercept() (which has int64_t argument) and then calling corresponding bdrv_co_ function. bdrv_co_ functions are OK with int64_t bytes as well. So dropping the check for INT_MAX we just get same restrictions as in bdrv_ layer: discard and write-zeroes goes through bdrv_check_qiov_request() and are allowed to be 64bit. Other requests go through bdrv_check_request32() and still restricted by INT_MAX boundary. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211006131718.214235-13-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake Signed-off-by: Eric Blake Commit: 57768ec166493260494b76a2fa9fea980ca30e18 https://github.com/qemu/qemu/commit/57768ec166493260494b76a2fa9fea980ca30e18 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M include/sysemu/block-backend.h Log Message: ----------- block-backend: fix blk_co_flush prototype to mention coroutine_fn We already have this marker for the blk_co_flush function declaration in block/block-backend.c. Add it in the header too. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211007175243.642516-1-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: wording tweak] Signed-off-by: Eric Blake Commit: bec4042baefc1bfeae05b161aa17d2f57d526b60 https://github.com/qemu/qemu/commit/bec4042baefc1bfeae05b161aa17d2f57d526b60 Author: Vladimir Sementsov-Ogievskiy Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M include/sysemu/block-backend.h Log Message: ----------- block-backend: update blk_co_pwrite() and blk_co_pread() wrappers Make bytes argument int64_t to be consistent with modern block-layer. Callers should be OK with it as type becomes wider. What is inside functions? - Conversion from int64_t to size_t. Still, we can't have a buffer larger than SIZE_MAX, therefore bytes should not be larger than SIZE_MAX as well. Add an assertion. - Passing to blk_co_pwritev() / blk_co_preadv() which already has int64_t bytes argument. Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211007175243.642516-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake [eblake: spelling fix] Signed-off-by: Eric Blake Commit: 6587b0c1331d427b0939c37e763842550ed581db https://github.com/qemu/qemu/commit/6587b0c1331d427b0939c37e763842550ed581db Author: Richard Henderson Date: 2021-10-15 (Fri, 15 Oct 2021) Changed paths: M block/block-backend.c M block/coroutines.h M block/qcow2-cluster.c M block/trace-events M include/sysemu/block-backend.h M scripts/block-coroutine-wrapper.py Log Message: ----------- Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging nbd patches for 2021-10-15 - Vladimir Sementsov-Ogievskiy: Consistent use of 64-bit parameters in block operations - Hanna Reitz: Silence 32-bit compiler warning # gpg: Signature made Fri 15 Oct 2021 02:08:10 PM PDT # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake " [full] # gpg: aka "Eric Blake (Free Software Programmer) " [full] # gpg: aka "[jpeg image of size 6874]" [full] * remotes/ericb/tags/pull-nbd-2021-10-15: block-backend: update blk_co_pwrite() and blk_co_pread() wrappers block-backend: fix blk_co_flush prototype to mention coroutine_fn block-backend: drop INT_MAX restriction from blk_check_byte_request() block-backend: blk_pread, blk_pwrite: rename count parameter to bytes block-backend: convert blk_aio_ functions to int64_t bytes paramter block-backend: convert blk_co_copy_range to int64_t bytes block-backend: convert blk_foo wrappers to use int64_t bytes parameter block-backend: drop blk_prw, use block-coroutine-wrapper block-coroutine-wrapper.py: support BlockBackend first argument block-backend: rename _do_ helper functions to _co_do_ block-backend: convert blk_co_pdiscard to int64_t bytes block-backend: convert blk_co_pwritev_part to int64_t bytes block-backend: make blk_co_preadv() 64bit block-backend: blk_check_byte_request(): int64_t bytes qcow2: Silence clang -m32 compiler warning Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/253e399bab7c...6587b0c1331d From MAILER-DAEMON Sat Oct 16 14:17:42 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mboFa-0003D6-48 for mharc-qemu-commits@gnu.org; Sat, 16 Oct 2021 14:17:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mboFX-00039a-6C for qemu-commits@nongnu.org; Sat, 16 Oct 2021 14:17:40 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:42285 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mboFJ-0003e6-OS for qemu-commits@nongnu.org; Sat, 16 Oct 2021 14:17:38 -0400 Received: from github.com (hubbernetes-node-1f34ae5.va3-iad.github.net [10.48.204.47]) by smtp.github.com (Postfix) with ESMTPA id F09275C022F for ; Sat, 16 Oct 2021 11:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634408245; bh=ELn5Me2sWkepaRWdnt7W8UHJZfmtWj1GCRY3ypuuHqc=; h=Date:From:To:Subject:From; b=2Oik12a00ueTYHhmbyKXRGnMamHEOqfpbDf2b1QjI0NKQn+98JAi4CCiDmyQjPl3C X4XAw0p0bVa9+GH+jYuEsgRQufFYUzZL9wwvbOtRTnIZTqHWoYCeuHJgtqZw65CK/7 7Jzliyl0XviChCUr2qdDoZ5FdNhM6UheBMM77xpE= Date: Sat, 16 Oct 2021 11:17:24 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c9460d: accel/tcg: Handle gdb singlestep in cpu_tb_exec X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Oct 2021 18:17:40 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: c9460d75c59fc6b6f110156e4c1035e9ae9bd611=0D https://github.com/qemu/qemu/commit/c9460d75c59fc6b6f110156e4c1035e= 9ae9bd611=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cpu-exec.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Handle gdb singlestep in cpu_tb_exec=0D =0D Currently the change in cpu_tb_exec is masked by the debug exception=0D being raised by the translators. But this allows us to remove that code.= =0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1760e4abf11223535b92e25a7fbd928b29b57233=0D https://github.com/qemu/qemu/commit/1760e4abf11223535b92e25a7fbd928= b29b57233=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a893daa936161b8f45b2567875922343e388de9c=0D https://github.com/qemu/qemu/commit/a893daa936161b8f45b256787592234= 3e388de9c=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/avr/translate.c=0D =0D Log Message:=0D -----------=0D target/avr: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Tested-by: Michael Rolnik =0D Reviewed-by: Michael Rolnik =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e3774881b5b651da7b44e5e98c5c8cea610e35bc=0D https://github.com/qemu/qemu/commit/e3774881b5b651da7b44e5e98c5c8ce= a610e35bc=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/cris/translate.c=0D =0D Log Message:=0D -----------=0D target/cris: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: db07bd026ee6f5ea4fe32c503645813252bae2c6=0D https://github.com/qemu/qemu/commit/db07bd026ee6f5ea4fe32c503645813= 252bae2c6=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D target/hexagon: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 364caea70f965a4fc81395863a3bae6bc16ce240=0D https://github.com/qemu/qemu/commit/364caea70f965a4fc81395863a3bae6= bc16ce240=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/arm/translate-a64.c=0D M target/arm/translate.c=0D =0D Log Message:=0D -----------=0D target/arm: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8532a14e413b3395c3ee2f13285462259858f433=0D https://github.com/qemu/qemu/commit/8532a14e413b3395c3ee2f132854622= 59858f433=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/hppa/translate.c=0D =0D Log Message:=0D -----------=0D target/hppa: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9ef6c6ec08b8ecd89a797fa6819b0c1d121e24d7=0D https://github.com/qemu/qemu/commit/9ef6c6ec08b8ecd89a797fa6819b0c1= d121e24d7=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/i386/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt=0D =0D We were using singlestep_enabled as a proxy for whether=0D translator_use_goto_tb would always return false.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4bc4c3135be4b258ae8143b1f8982fe76cba460a=0D https://github.com/qemu/qemu/commit/4bc4c3135be4b258ae8143b1f8982fe= 76cba460a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/i386/helper.h=0D M target/i386/tcg/misc_helper.c=0D M target/i386/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/i386: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 661da0f63f973b84755423ae9e919582ff330a0c=0D https://github.com/qemu/qemu/commit/661da0f63f973b84755423ae9e91958= 2ff330a0c=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/m68k/translate.c=0D =0D Log Message:=0D -----------=0D target/m68k: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Acked-by: Laurent Vivier =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fbafb3a4d2fc90efdba05ec0d1f2ad7c4f68e9a5=0D https://github.com/qemu/qemu/commit/fbafb3a4d2fc90efdba05ec0d1f2ad7= c4f68e9a5=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/microblaze/translate.c=0D =0D Log Message:=0D -----------=0D target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP=0D =0D We were using singlestep_enabled as a proxy for whether=0D translator_use_goto_tb would always return false.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 66345580255f4a9f382cb9e8321a2590025eb1b4=0D https://github.com/qemu/qemu/commit/66345580255f4a9f382cb9e8321a259= 0025eb1b4=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/microblaze/translate.c=0D =0D Log Message:=0D -----------=0D target/microblaze: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ef00cd4a22701923583862c48448b43bbcdaca0f=0D https://github.com/qemu/qemu/commit/ef00cd4a22701923583862c48448b43= bbcdaca0f=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Fix single stepping=0D =0D As per an ancient comment in mips_tr_translate_insn about the=0D expectations of gdb, when restarting the insn in a delay slot=0D we also re-execute the branch. Which means that we are=0D expected to execute two insns in this case.=0D =0D This has been broken since 8b86d6d2580, where we forced max_insns=0D to 1 while single-stepping. This resulted in an exit from the=0D translator loop after the branch but before the delay slot is=0D translated.=0D =0D Increase the max_insns to 2 for this case. In addition, bypass=0D the end-of-page check, for when the branch itself ends the page.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1a79c413999e241bbc24487b4db08faec2493c9d=0D https://github.com/qemu/qemu/commit/1a79c413999e241bbc24487b4db08fa= ec2493c9d=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Drop exit checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b21fce536c5e673b1f3faab6db9bd7a7aec88cc1=0D https://github.com/qemu/qemu/commit/b21fce536c5e673b1f3faab6db9bd7a= 7aec88cc1=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/openrisc/translate.c=0D =0D Log Message:=0D -----------=0D target/openrisc: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9498d1032c107166ffb72939f99929a4dd3f600a=0D https://github.com/qemu/qemu/commit/9498d1032c107166ffb72939f99929a= 4dd3f600a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Drop exit checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D Reuse gen_debug_exception to handle architectural debug exceptions.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ea06a006525181826b1197a987d474bdaeb0acf7=0D https://github.com/qemu/qemu/commit/ea06a006525181826b1197a987d474b= daeb0acf7=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove dead code after exception=0D =0D We have already set DISAS_NORETURN in generate_exception,=0D which makes the exit_tb unreachable.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 273b68b10428117ffb1917d4081cf8ab4cc940ca=0D https://github.com/qemu/qemu/commit/273b68b10428117ffb1917d4081cf8a= b4cc940ca=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Remove exit_tb and lookup_and_goto_ptr=0D =0D GDB single-stepping is now handled generically, which means=0D we don't need to do anything in the wrappers.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6509e35b9e3a3fa90cdafcb8d53bf75306f427b=0D https://github.com/qemu/qemu/commit/b6509e35b9e3a3fa90cdafcb8d53bf7= 5306f427b=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/rx/helper.h=0D M target/rx/op_helper.c=0D M target/rx/translate.c=0D =0D Log Message:=0D -----------=0D target/rx: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2df7a3618aacaa0f057d7b05444a21974a157263=0D https://github.com/qemu/qemu/commit/2df7a3618aacaa0f057d7b05444a219= 74a157263=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/s390x: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 52df5adce9c028cec91cc0c10f7012b17212ea35=0D https://github.com/qemu/qemu/commit/52df5adce9c028cec91cc0c10f7012b= 17212ea35=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/sh4/helper.h=0D M target/sh4/op_helper.c=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D target/sh4: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1b55c52d607043210ed4579009191f99a5cf8f71=0D https://github.com/qemu/qemu/commit/1b55c52d607043210ed4579009191f9= 9a5cf8f71=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/tricore/helper.h=0D M target/tricore/op_helper.c=0D M target/tricore/translate.c=0D =0D Log Message:=0D -----------=0D target/tricore: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 02bf7fa022feae36b0f818b5ee30daccef8615fd=0D https://github.com/qemu/qemu/commit/02bf7fa022feae36b0f818b5ee30dac= cef8615fd=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/xtensa/translate.c=0D =0D Log Message:=0D -----------=0D target/xtensa: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 995b87dedc78b0467f5f18bbc3546072ba97516a=0D https://github.com/qemu/qemu/commit/995b87dedc78b0467f5f18bbc354607= 2ba97516a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M cpu.c=0D M hw/core/cpu-common.c=0D M include/hw/core/cpu.h=0D =0D Log Message:=0D -----------=0D Revert "cpu: Move cpu_common_props to hw/core/cpu.c"=0D =0D This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.=0D =0D Despite a comment saying why cpu_common_props cannot be placed in=0D a file that is compiled once, it was moved anyway. Revert that.=0D =0D Since then, Property is not defined in hw/core/cpu.h, so it is now=0D easier to declare a function to install the properties rather than=0D the Property array itself.=0D =0D Cc: Eduardo Habkost =0D Suggested-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c148a0572130ff485cd2249fbdd1a3260d5e10a4=0D https://github.com/qemu/qemu/commit/c148a0572130ff485cd2249fbdd1a32= 60d5e10a4=0D Author: Richard Henderson =0D Date: 2021-10-16 (Sat, 16 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cpu-exec.c=0D M cpu.c=0D M hw/core/cpu-common.c=0D M include/hw/core/cpu.h=0D M target/alpha/translate.c=0D M target/arm/translate-a64.c=0D M target/arm/translate.c=0D M target/avr/translate.c=0D M target/cris/translate.c=0D M target/hexagon/translate.c=0D M target/hppa/translate.c=0D M target/i386/helper.h=0D M target/i386/tcg/misc_helper.c=0D M target/i386/tcg/translate.c=0D M target/m68k/translate.c=0D M target/microblaze/translate.c=0D M target/mips/tcg/translate.c=0D M target/openrisc/translate.c=0D M target/ppc/translate.c=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/translate.c=0D M target/rx/helper.h=0D M target/rx/op_helper.c=0D M target/rx/translate.c=0D M target/s390x/tcg/translate.c=0D M target/sh4/helper.h=0D M target/sh4/op_helper.c=0D M target/sh4/translate.c=0D M target/tricore/helper.h=0D M target/tricore/op_helper.c=0D M target/tricore/translate.c=0D M target/xtensa/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into = staging=0D =0D Move gdb singlestep to generic code=0D Fix cpu_common_props=0D =0D # gpg: Signature made Sat 16 Oct 2021 11:13:54 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211016: (24 commits)=0D Revert "cpu: Move cpu_common_props to hw/core/cpu.c"=0D target/xtensa: Drop check for singlestep_enabled=0D target/tricore: Drop check for singlestep_enabled=0D target/sh4: Drop check for singlestep_enabled=0D target/s390x: Drop check for singlestep_enabled=0D target/rx: Drop checks for singlestep_enabled=0D target/riscv: Remove exit_tb and lookup_and_goto_ptr=0D target/riscv: Remove dead code after exception=0D target/ppc: Drop exit checks for singlestep_enabled=0D target/openrisc: Drop checks for singlestep_enabled=0D target/mips: Drop exit checks for singlestep_enabled=0D target/mips: Fix single stepping=0D target/microblaze: Drop checks for singlestep_enabled=0D target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP=0D target/m68k: Drop checks for singlestep_enabled=0D target/i386: Drop check for singlestep_enabled=0D target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt=0D target/hppa: Drop checks for singlestep_enabled=0D target/arm: Drop checks for singlestep_enabled=0D target/hexagon: Drop checks for singlestep_enabled=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/6587b0c1331d...c148a0572130= =0D From MAILER-DAEMON Sat Oct 16 19:49:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mbtQO-0000nZ-Kk for mharc-qemu-commits@gnu.org; Sat, 16 Oct 2021 19:49:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbtQN-0000nQ-7j for qemu-commits@nongnu.org; Sat, 16 Oct 2021 19:49:11 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:42505 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbtQK-0000LI-Ci for qemu-commits@nongnu.org; Sat, 16 Oct 2021 19:49:10 -0400 Received: from github.com (hubbernetes-node-c9b2c67.ac4-iad.github.net [10.52.201.31]) by smtp.github.com (Postfix) with ESMTPA id A351D56006E for ; Sat, 16 Oct 2021 16:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634428147; bh=uZzS5eQayTus2AELBeGz8tD7WKm1Zv9oh2g2fIP0GhI=; h=Date:From:To:Subject:From; b=PpEOfdHkOShj9FsLeOSLB4ZiALelAcz6IPvtqBo3X05FKhxbz3B+ZxpMbEzCgXz30 HbQor6iUGVMl507ApQbnWcz6kT3M9IyYiYv/n6LnoCRVXAGg6g747xWjceySMBC1mp xiHOGL2XYOktaEYlBQNmpEKwGdk9dM5eO98ONtwA= Date: Sat, 16 Oct 2021 16:49:07 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c9460d: accel/tcg: Handle gdb singlestep in cpu_tb_exec X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Oct 2021 23:49:11 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: c9460d75c59fc6b6f110156e4c1035e9ae9bd611=0D https://github.com/qemu/qemu/commit/c9460d75c59fc6b6f110156e4c1035e= 9ae9bd611=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cpu-exec.c=0D =0D Log Message:=0D -----------=0D accel/tcg: Handle gdb singlestep in cpu_tb_exec=0D =0D Currently the change in cpu_tb_exec is masked by the debug exception=0D being raised by the translators. But this allows us to remove that code.= =0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1760e4abf11223535b92e25a7fbd928b29b57233=0D https://github.com/qemu/qemu/commit/1760e4abf11223535b92e25a7fbd928= b29b57233=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/alpha/translate.c=0D =0D Log Message:=0D -----------=0D target/alpha: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a893daa936161b8f45b2567875922343e388de9c=0D https://github.com/qemu/qemu/commit/a893daa936161b8f45b256787592234= 3e388de9c=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/avr/translate.c=0D =0D Log Message:=0D -----------=0D target/avr: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Tested-by: Michael Rolnik =0D Reviewed-by: Michael Rolnik =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e3774881b5b651da7b44e5e98c5c8cea610e35bc=0D https://github.com/qemu/qemu/commit/e3774881b5b651da7b44e5e98c5c8ce= a610e35bc=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/cris/translate.c=0D =0D Log Message:=0D -----------=0D target/cris: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: db07bd026ee6f5ea4fe32c503645813252bae2c6=0D https://github.com/qemu/qemu/commit/db07bd026ee6f5ea4fe32c503645813= 252bae2c6=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D target/hexagon: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 364caea70f965a4fc81395863a3bae6bc16ce240=0D https://github.com/qemu/qemu/commit/364caea70f965a4fc81395863a3bae6= bc16ce240=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/arm/translate-a64.c=0D M target/arm/translate.c=0D =0D Log Message:=0D -----------=0D target/arm: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8532a14e413b3395c3ee2f13285462259858f433=0D https://github.com/qemu/qemu/commit/8532a14e413b3395c3ee2f132854622= 59858f433=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/hppa/translate.c=0D =0D Log Message:=0D -----------=0D target/hppa: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9ef6c6ec08b8ecd89a797fa6819b0c1d121e24d7=0D https://github.com/qemu/qemu/commit/9ef6c6ec08b8ecd89a797fa6819b0c1= d121e24d7=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/i386/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt=0D =0D We were using singlestep_enabled as a proxy for whether=0D translator_use_goto_tb would always return false.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4bc4c3135be4b258ae8143b1f8982fe76cba460a=0D https://github.com/qemu/qemu/commit/4bc4c3135be4b258ae8143b1f8982fe= 76cba460a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/i386/helper.h=0D M target/i386/tcg/misc_helper.c=0D M target/i386/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/i386: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 661da0f63f973b84755423ae9e919582ff330a0c=0D https://github.com/qemu/qemu/commit/661da0f63f973b84755423ae9e91958= 2ff330a0c=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/m68k/translate.c=0D =0D Log Message:=0D -----------=0D target/m68k: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Acked-by: Laurent Vivier =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fbafb3a4d2fc90efdba05ec0d1f2ad7c4f68e9a5=0D https://github.com/qemu/qemu/commit/fbafb3a4d2fc90efdba05ec0d1f2ad7= c4f68e9a5=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/microblaze/translate.c=0D =0D Log Message:=0D -----------=0D target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP=0D =0D We were using singlestep_enabled as a proxy for whether=0D translator_use_goto_tb would always return false.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 66345580255f4a9f382cb9e8321a2590025eb1b4=0D https://github.com/qemu/qemu/commit/66345580255f4a9f382cb9e8321a259= 0025eb1b4=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/microblaze/translate.c=0D =0D Log Message:=0D -----------=0D target/microblaze: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ef00cd4a22701923583862c48448b43bbcdaca0f=0D https://github.com/qemu/qemu/commit/ef00cd4a22701923583862c48448b43= bbcdaca0f=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Fix single stepping=0D =0D As per an ancient comment in mips_tr_translate_insn about the=0D expectations of gdb, when restarting the insn in a delay slot=0D we also re-execute the branch. Which means that we are=0D expected to execute two insns in this case.=0D =0D This has been broken since 8b86d6d2580, where we forced max_insns=0D to 1 while single-stepping. This resulted in an exit from the=0D translator loop after the branch but before the delay slot is=0D translated.=0D =0D Increase the max_insns to 2 for this case. In addition, bypass=0D the end-of-page check, for when the branch itself ends the page.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1a79c413999e241bbc24487b4db08faec2493c9d=0D https://github.com/qemu/qemu/commit/1a79c413999e241bbc24487b4db08fa= ec2493c9d=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Drop exit checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b21fce536c5e673b1f3faab6db9bd7a7aec88cc1=0D https://github.com/qemu/qemu/commit/b21fce536c5e673b1f3faab6db9bd7a= 7aec88cc1=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/openrisc/translate.c=0D =0D Log Message:=0D -----------=0D target/openrisc: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9498d1032c107166ffb72939f99929a4dd3f600a=0D https://github.com/qemu/qemu/commit/9498d1032c107166ffb72939f99929a= 4dd3f600a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Drop exit checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D Reuse gen_debug_exception to handle architectural debug exceptions.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ea06a006525181826b1197a987d474bdaeb0acf7=0D https://github.com/qemu/qemu/commit/ea06a006525181826b1197a987d474b= daeb0acf7=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Remove dead code after exception=0D =0D We have already set DISAS_NORETURN in generate_exception,=0D which makes the exit_tb unreachable.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 273b68b10428117ffb1917d4081cf8ab4cc940ca=0D https://github.com/qemu/qemu/commit/273b68b10428117ffb1917d4081cf8a= b4cc940ca=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Remove exit_tb and lookup_and_goto_ptr=0D =0D GDB single-stepping is now handled generically, which means=0D we don't need to do anything in the wrappers.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6509e35b9e3a3fa90cdafcb8d53bf75306f427b=0D https://github.com/qemu/qemu/commit/b6509e35b9e3a3fa90cdafcb8d53bf7= 5306f427b=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/rx/helper.h=0D M target/rx/op_helper.c=0D M target/rx/translate.c=0D =0D Log Message:=0D -----------=0D target/rx: Drop checks for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2df7a3618aacaa0f057d7b05444a21974a157263=0D https://github.com/qemu/qemu/commit/2df7a3618aacaa0f057d7b05444a219= 74a157263=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/s390x/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/s390x: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 52df5adce9c028cec91cc0c10f7012b17212ea35=0D https://github.com/qemu/qemu/commit/52df5adce9c028cec91cc0c10f7012b= 17212ea35=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/sh4/helper.h=0D M target/sh4/op_helper.c=0D M target/sh4/translate.c=0D =0D Log Message:=0D -----------=0D target/sh4: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1b55c52d607043210ed4579009191f99a5cf8f71=0D https://github.com/qemu/qemu/commit/1b55c52d607043210ed4579009191f9= 9a5cf8f71=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/tricore/helper.h=0D M target/tricore/op_helper.c=0D M target/tricore/translate.c=0D =0D Log Message:=0D -----------=0D target/tricore: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 02bf7fa022feae36b0f818b5ee30daccef8615fd=0D https://github.com/qemu/qemu/commit/02bf7fa022feae36b0f818b5ee30dac= cef8615fd=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/xtensa/translate.c=0D =0D Log Message:=0D -----------=0D target/xtensa: Drop check for singlestep_enabled=0D =0D GDB single-stepping is now handled generically.=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 995b87dedc78b0467f5f18bbc3546072ba97516a=0D https://github.com/qemu/qemu/commit/995b87dedc78b0467f5f18bbc354607= 2ba97516a=0D Author: Richard Henderson =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M cpu.c=0D M hw/core/cpu-common.c=0D M include/hw/core/cpu.h=0D =0D Log Message:=0D -----------=0D Revert "cpu: Move cpu_common_props to hw/core/cpu.c"=0D =0D This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.=0D =0D Despite a comment saying why cpu_common_props cannot be placed in=0D a file that is compiled once, it was moved anyway. Revert that.=0D =0D Since then, Property is not defined in hw/core/cpu.h, so it is now=0D easier to declare a function to install the properties rather than=0D the Property array itself.=0D =0D Cc: Eduardo Habkost =0D Suggested-by: Peter Maydell =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c148a0572130ff485cd2249fbdd1a3260d5e10a4=0D https://github.com/qemu/qemu/commit/c148a0572130ff485cd2249fbdd1a32= 60d5e10a4=0D Author: Richard Henderson =0D Date: 2021-10-16 (Sat, 16 Oct 2021)=0D =0D Changed paths:=0D M accel/tcg/cpu-exec.c=0D M cpu.c=0D M hw/core/cpu-common.c=0D M include/hw/core/cpu.h=0D M target/alpha/translate.c=0D M target/arm/translate-a64.c=0D M target/arm/translate.c=0D M target/avr/translate.c=0D M target/cris/translate.c=0D M target/hexagon/translate.c=0D M target/hppa/translate.c=0D M target/i386/helper.h=0D M target/i386/tcg/misc_helper.c=0D M target/i386/tcg/translate.c=0D M target/m68k/translate.c=0D M target/microblaze/translate.c=0D M target/mips/tcg/translate.c=0D M target/openrisc/translate.c=0D M target/ppc/translate.c=0D M target/riscv/insn_trans/trans_privileged.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/translate.c=0D M target/rx/helper.h=0D M target/rx/op_helper.c=0D M target/rx/translate.c=0D M target/s390x/tcg/translate.c=0D M target/sh4/helper.h=0D M target/sh4/op_helper.c=0D M target/sh4/translate.c=0D M target/tricore/helper.h=0D M target/tricore/op_helper.c=0D M target/tricore/translate.c=0D M target/xtensa/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into = staging=0D =0D Move gdb singlestep to generic code=0D Fix cpu_common_props=0D =0D # gpg: Signature made Sat 16 Oct 2021 11:13:54 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211016: (24 commits)=0D Revert "cpu: Move cpu_common_props to hw/core/cpu.c"=0D target/xtensa: Drop check for singlestep_enabled=0D target/tricore: Drop check for singlestep_enabled=0D target/sh4: Drop check for singlestep_enabled=0D target/s390x: Drop check for singlestep_enabled=0D target/rx: Drop checks for singlestep_enabled=0D target/riscv: Remove exit_tb and lookup_and_goto_ptr=0D target/riscv: Remove dead code after exception=0D target/ppc: Drop exit checks for singlestep_enabled=0D target/openrisc: Drop checks for singlestep_enabled=0D target/mips: Drop exit checks for singlestep_enabled=0D target/mips: Fix single stepping=0D target/microblaze: Drop checks for singlestep_enabled=0D target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP=0D target/m68k: Drop checks for singlestep_enabled=0D target/i386: Drop check for singlestep_enabled=0D target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt=0D target/hppa: Drop checks for singlestep_enabled=0D target/arm: Drop checks for singlestep_enabled=0D target/hexagon: Drop checks for singlestep_enabled=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/6587b0c1331d...c148a0572130= =0D From MAILER-DAEMON Mon Oct 18 11:09:29 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcUGW-0003uZ-QR for mharc-qemu-commits@gnu.org; Mon, 18 Oct 2021 11:09:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcUGS-0003tu-3f for qemu-commits@nongnu.org; Mon, 18 Oct 2021 11:09:25 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:36471 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcUGM-000845-WC for qemu-commits@nongnu.org; Mon, 18 Oct 2021 11:09:23 -0400 Received: from github.com (hubbernetes-node-6d0365b.ash1-iad.github.net [10.56.112.66]) by smtp.github.com (Postfix) with ESMTPA id 49462840D1E for ; Mon, 18 Oct 2021 08:09:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634569758; bh=bkuKj/+aYV5g8/nndG4Wwl9KQGo9HLbRWbFUW8zoK9U=; h=Date:From:To:Subject:From; b=S40GpfH+3Shz/pkeLsYCCgX79/nusyZYTOHHmi9C1kiiPUSLLD5JTYRyDsMf5FS08 moSj6nrCmrf9O4LfLNTVZJjMTSIWukgsan1fYeqY68ahIdSTf2TcK6b8sdGNI5imiY VmzhoJ39cFZ4NGPc8y/HA5bNNq2nVJZOTC2Zo9Oo= Date: Mon, 18 Oct 2021 08:09:18 -0700 From: Marcel Apfelbaum To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 151399: multi-process: Initialize variables declared with ... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 15:09:25 -0000 Branch: refs/heads/stable-6.0-staging=0D Home: https://github.com/qemu/qemu=0D Commit: 1513997aa2aac392d8a2e020feddd26f0f1fc4d3=0D https://github.com/qemu/qemu/commit/1513997aa2aac392d8a2e020feddd26= f0f1fc4d3=0D Author: Zenghui Yu =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M hw/remote/memory.c=0D M hw/remote/proxy.c=0D =0D Log Message:=0D -----------=0D multi-process: Initialize variables declared with g_auto*=0D =0D Quote docs/devel/style.rst (section "Automatic memory deallocation"):=0D =0D * Variables declared with g_auto* MUST always be initialized,=0D otherwise the cleanup function will use uninitialized stack memory=0D =0D Initialize @name properly to get rid of the compilation error (using=0D gcc-7.3.0 on CentOS):=0D =0D ../hw/remote/proxy.c: In function 'pci_proxy_dev_realize':=0D /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: error: 'name' may be= used uninitialized in this function [-Werror=3Dmaybe-uninitialized]=0D g_free (*pp);=0D ^~~~~~~~~~~~=0D ../hw/remote/proxy.c:350:30: note: 'name' was declared here=0D g_autofree char *name;=0D ^~~~=0D =0D Signed-off-by: Zenghui Yu =0D Reviewed-by: Jagannathan Raman =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Miroslav Rezanina =0D Message-id: 20210312112143.1369-1-yuzenghui@huawei.com=0D Signed-off-by: Stefan Hajnoczi =0D (cherry picked from commit d90226808b5b1b30b07968e94d8f74bf8804fc89)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 5d0c78455ebac78fba07949910434c040352facc=0D https://github.com/qemu/qemu/commit/5d0c78455ebac78fba07949910434c0= 40352facc=0D Author: Richard Henderson =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D =0D Log Message:=0D -----------=0D linux-user/aarch64: Enable hwcap for RND, BTI, and MTE=0D =0D These three features are already enabled by TCG, but are missing=0D their hwcap bits. Update HWCAP2 from linux v5.12.=0D =0D Cc: qemu-stable@nongnu.org (for 6.0.1)=0D Buglink: https://bugs.launchpad.net/bugs/1926044=0D Signed-off-by: Richard Henderson =0D Message-id: 20210427214108.88503-1-richard.henderson@linaro.org=0D Signed-off-by: Peter Maydell =0D (cherry picked from commit 68948d18224b93361e2880e2946ab268d0c650d7)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: c1d1c0b4c3a3a96b25b8dff091ae9874705e39b1=0D https://github.com/qemu/qemu/commit/c1d1c0b4c3a3a96b25b8dff091ae987= 4705e39b1=0D Author: Greg Kurz =0D Date: 2021-10-13 (Wed, 13 Oct 2021)=0D =0D Changed paths:=0D M docs/system/removed-features.rst=0D =0D Log Message:=0D -----------=0D docs/system: Document the removal of "compat" property for POWER CPUs=0D= =0D This is just an oversight.=0D =0D Fixes: f518be3aa35b ("target/ppc: Remove "compat" property of server clas= s POWER CPUs")=0D Cc: groug@kaod.org=0D Signed-off-by: Greg Kurz =0D Reviewed-by: Laurent Vivier =0D Message-Id: <161399328834.51902.14269239378658110394.stgit@bahia.lan>=0D Signed-off-by: Laurent Vivier =0D (cherry picked from commit a058b895079348d0854a027a42ce3396a4a00bb7)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 318b07635651ca284f0e3f60f1c117a5fda41463=0D https://github.com/qemu/qemu/commit/318b07635651ca284f0e3f60f1c117a= 5fda41463=0D Author: Stefan Reiter =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M monitor/qmp.c=0D =0D Log Message:=0D -----------=0D monitor/qmp: fix race on CHR_EVENT_CLOSED without OOB=0D =0D The QMP dispatcher coroutine holds the qmp_queue_lock over a yield=0D point, where it expects to be rescheduled from the main context. If a=0D CHR_EVENT_CLOSED event is received just then, it can race and block the=0D= main thread on the mutex in monitor_qmp_cleanup_queue_and_resume.=0D =0D monitor_resume does not need to be called from main context, so we can=0D= call it immediately after popping a request from the queue, which allows=0D= us to drop the qmp_queue_lock mutex before yielding.=0D =0D Suggested-by: Wolfgang Bumiller =0D Signed-off-by: Stefan Reiter =0D Message-Id: <20210322154024.15011-1-s.reiter@proxmox.com>=0D Reviewed-by: Kevin Wolf =0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Markus Armbruster =0D (cherry picked from commit a67b996e7894edfafbcd3fd007c9f58f26d25908)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: fdf58b451b4d419238b266f578d50fd693c36844=0D https://github.com/qemu/qemu/commit/fdf58b451b4d419238b266f578d50fd= 693c36844=0D Author: Li Zhijian =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M migration/rdma.c=0D =0D Log Message:=0D -----------=0D migration/rdma: Fix cm_event used before being initialized=0D =0D A segmentation fault was triggered when i try to abort a postcopy + rdma=0D= migration.=0D =0D since rdma_ack_cm_event releases a uninitialized cm_event in these case.=0D= =0D like below:=0D 2496 ret =3D rdma_get_cm_event(rdma->channel, &cm_event);=0D 2497 if (ret) {=0D 2498 perror("rdma_get_cm_event after rdma_connect");=0D 2499 ERROR(errp, "connecting to destination!");=0D 2500 rdma_ack_cm_event(cm_event); <<<< cause segmentation fault=0D= 2501 goto err_rdma_source_connect;=0D 2502 }=0D =0D Refer to the rdma_get_cm_event() code, cm_event will be=0D updated/changed only if rdma_get_cm_event() returns 0. So it's okey to=0D= remove the ack in error patch.=0D =0D Signed-off-by: Li Zhijian =0D =0D Message-Id: <20210519064740.10828-1-lizhijian@cn.fujitsu.com>=0D Reviewed-by: Dr. David Alan Gilbert =0D Signed-off-by: Dr. David Alan Gilbert =0D (cherry picked from commit efb208dc9c3f1e881aecff21fb1c7a7b6b869480)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: e2258e527950fff984f1be0a71dbbae2cb14ebfc=0D https://github.com/qemu/qemu/commit/e2258e527950fff984f1be0a71dbbae= 2cb14ebfc=0D Author: Richard Henderson =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M target/i386/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/i386: Exit tb after wrmsr=0D =0D At minimum, wrmsr can change efer, which affects HF_LMA.=0D =0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Richard Henderson =0D Reviewed-by: Paolo Bonzini =0D Message-Id: <20210514151342.384376-46-richard.henderson@linaro.org>=0D (cherry picked from commit 244843b757220c432e0e9ae8d2210218c034730d)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 59ac5e6d61fcf95d723c7191711ff9b7f6462320=0D https://github.com/qemu/qemu/commit/59ac5e6d61fcf95d723c7191711ff9b= 7f6462320=0D Author: Giuseppe Musacchio =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate/vsx-impl.c.inc=0D =0D Log Message:=0D -----------=0D target/ppc: Fix load endianness for lxvwsx/lxvdsx=0D =0D TARGET_WORDS_BIGENDIAN may not match the machine endianness if that's a=0D= runtime-configurable parameter.=0D =0D Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c=0D Fixes: afae37d98ae991c0792c867dbd9f32f988044318=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/212=0D =0D Signed-off-by: Giuseppe Musacchio =0D Message-Id: <20210518133020.58927-1-thatlemon@gmail.com>=0D Tested-by: Paul A. Clarke =0D Signed-off-by: David Gibson =0D (cherry picked from commit 861f10fd528263a507476b8c4dda93a9588dfa5c)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: b20eff3ba44576dad70b76969870837de7105ba3=0D https://github.com/qemu/qemu/commit/b20eff3ba44576dad70b76969870837= de7105ba3=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M softmmu/vl.c=0D =0D Log Message:=0D -----------=0D vl: allow not specifying size in -m when using -M memory-backend=0D =0D Starting in QEMU 6.0's commit f5c9fcb82d ("vl: separate=0D qemu_create_machine", 2020-12-10), a function have_custom_ram_size()=0D replaced the return value of set_memory_options().=0D =0D The purpose of the return value was to record the presence of=0D "-m size", and if it was not there, change the default RAM=0D size to the size of the memory backend passed with "-M=0D memory-backend".=0D =0D With that commit, however, have_custom_ram_size() is now queried only=0D after set_memory_options has stored the fixed-up RAM size in QemuOpts for= =0D "future use". This was actually the only future use of the fixed-up RAM=0D= size, so remove that code and fix the bug.=0D =0D Cc: qemu-stable@nongnu.org=0D Fixes: f5c9fcb82d ("vl: separate qemu_create_machine", 2020-12-10)=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit d349f92f78d26db2805ca39a7745cc70affea021)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: ab331881254228561c1045d4fa96cc5f66672a41=0D https://github.com/qemu/qemu/commit/ab331881254228561c1045d4fa96cc5= f66672a41=0D Author: Max Filippov =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M target/xtensa/translate.c=0D =0D Log Message:=0D -----------=0D target/xtensa: fix access ring in l32ex=0D =0D l32ex does memory access as all regular load/store operations at CRING=0D= level. Fix apparent pasto from l32e that caused it to use RING instead.=0D= =0D This is a correctness issue, not a security issue, because in the worst=0D= case the privilege level of memory access may be lowered, resulting in=0D= an exception when the correct implementation would've succeeded.=0D In no case it would allow memory access that would've raised an=0D exception in the correct implementation.=0D =0D Cc: qemu-stable@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Max Filippov =0D (cherry picked from commit 735aa900e4bf57b777ac620bed7c88234ec4b601)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 4e1eef86117da65c7e084e9e87df3f562682a84b=0D https://github.com/qemu/qemu/commit/4e1eef86117da65c7e084e9e87df3f5= 62682a84b=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M util/qemu-option.c=0D =0D Log Message:=0D -----------=0D qemu-option: support accept-any QemuOptsList in qemu_opts_absorb_qdict=0D= =0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 941a4736d2b465be1d6429415f8b1f26e2167585)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 701ff59cc42e5812c1cd024a07b4802f19e0fd2a=0D https://github.com/qemu/qemu/commit/701ff59cc42e5812c1cd024a07b4802= f19e0fd2a=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M include/qemu/config-file.h=0D M softmmu/vl.c=0D M stubs/meson.build=0D A stubs/module-opts.c=0D M util/qemu-config.c=0D =0D Log Message:=0D -----------=0D qemu-config: load modules when instantiating option groups=0D =0D Right now the SPICE module is special cased to be loaded when processing=0D= of the -spice command line option. However, the spice option group=0D can also be brought in via -readconfig, in which case the module is=0D not loaded.=0D =0D Add a generic hook to load modules that provide a QemuOpts group,=0D and use it for the "spice" and "iscsi" groups.=0D =0D Fixes: #194=0D Fixes: https://bugs.launchpad.net/qemu/+bug/1910696=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 632a8873500d27022c584256afc11e57e2418b94)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 203f0ba14434057d6ea1fef15a34694965771837=0D https://github.com/qemu/qemu/commit/203f0ba14434057d6ea1fef15a34694= 965771837=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M include/qemu/config-file.h=0D M softmmu/vl.c=0D M util/qemu-config.c=0D =0D Log Message:=0D -----------=0D qemu-config: parse configuration files to a QDict=0D =0D Change the parser to put the values into a QDict and pass them=0D to a callback. qemu_config_parse's QemuOpts creation is=0D itself turned into a callback function.=0D =0D This is useful for -readconfig to support keyval-based options;=0D getting a QDict from the parser removes a roundtrip from=0D QDict to QemuOpts and then back to QDict.=0D =0D Unfortunately there is a disadvantage in that semantic errors will=0D point to the last line of the group, because the entries of the QDict=0D do not have a location attached.=0D =0D Cc: Kevin Wolf =0D Cc: Markus Armbruster =0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20210524105752.3318299-2-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 37701411397c7b7d709ae92abd347cc593940ee5)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: c675ba821cc2369fe369b89efa09696a2b1afda1=0D https://github.com/qemu/qemu/commit/c675ba821cc2369fe369b89efa09696= a2b1afda1=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M include/block/qdict.h=0D M include/qapi/qmp/qdict.h=0D M softmmu/vl.c=0D =0D Log Message:=0D -----------=0D vl: plumb keyval-based options into -readconfig=0D =0D Let -readconfig support parsing command line options into QDict or=0D QemuOpts. This will be used to add back support for objects in=0D -readconfig.=0D =0D Cc: Markus Armbruster =0D Cc: qemu-stable@nongnu.org=0D Reviewed-by: Kevin Wolf =0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20210524105752.3318299-3-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit c0d4aa82f895af67cbf7772324e05605e22b4162)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 5b96b36a6162d24fd6a4d64c81e71b3a60e511a6=0D https://github.com/qemu/qemu/commit/5b96b36a6162d24fd6a4d64c81e71b3= a60e511a6=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M softmmu/vl.c=0D =0D Log Message:=0D -----------=0D vl: plug -object back into -readconfig=0D =0D Commit bc2f4fcb1d ("qom: move user_creatable_add_opts logic to vl.c=0D and QAPIfy it", 2021-03-19) switched the creation of objects from=0D qemu_opts_foreach to a bespoke QTAILQ in preparation for supporting JSON=0D= syntax in -object.=0D =0D Unfortunately in doing so it lost support for [object] stanzas in=0D configuration files and also for "-set object.ID.KEY=3DVAL". The latter=0D= is hard to re-establish and probably best solved by deprecating -set.=0D This patch uses the infrastructure introduced by the previous two=0D patches in order to parse QOM objects correctly from configuration=0D files.=0D =0D Cc: Markus Armbruster =0D Cc: qemu-stable@nongnu.org=0D Reviewed-by: Kevin Wolf =0D Signed-off-by: Paolo Bonzini =0D Message-Id: <20210524105752.3318299-4-pbonzini@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 49e987695a1873a769a823604f9065aa88e00c55)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 9b0ee423a1b5312f12e375eaacb6fcdd56e60d16=0D https://github.com/qemu/qemu/commit/9b0ee423a1b5312f12e375eaacb6fcd= d56e60d16=0D Author: Stefan Hajnoczi =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M util/qemu-sockets.c=0D =0D Log Message:=0D -----------=0D sockets: update SOCKET_ADDRESS_TYPE_FD listen(2) backlog=0D =0D socket_get_fd() fails with the error "socket_get_fd: too many=0D connections" if the given listen backlog value is not 1.=0D =0D Not all callers set the backlog to 1. For example, commit=0D 582d4210eb2f2ab5baac328fe4b479cd86da1647 ("qemu-nbd: Use SOMAXCONN for=0D= socket listen() backlog") uses SOMAXCONN. This will always fail with in=0D= socket_get_fd().=0D =0D This patch calls listen(2) on the fd to update the backlog value. The=0D socket may already be in the listen state. I have tested that this works=0D= on Linux 5.10 and macOS Catalina.=0D =0D As a bonus this allows us to detect when the fd cannot listen. Now we'll=0D= be able to catch unbound or connected fds in socket_listen().=0D =0D Drop the num argument from socket_get_fd() since this function is also=0D= called by socket_connect() where a listen backlog value does not make=0D sense.=0D =0D Fixes: e5b6353cf25c99c3f08bf51e29933352f7140e8f ("socket: Add backlog par= ameter to socket_listen")=0D Reported-by: Richard W.M. Jones =0D Cc: Juan Quintela =0D Cc: Eric Blake =0D Signed-off-by: Stefan Hajnoczi =0D Message-Id: <20210310173004.420190-1-stefanha@redhat.com>=0D Tested-by: Richard W.M. Jones =0D Reviewed-by: Eric Blake =0D Reviewed-by: Stefano Garzarella =0D Signed-off-by: Eric Blake =0D (cherry picked from commit 37179e9ea45d6428b29ae789209c119ac18c1d39)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: fcfe1509a1a622d85224a1e7003aba940897fe8d=0D https://github.com/qemu/qemu/commit/fcfe1509a1a622d85224a1e7003aba9= 40897fe8d=0D Author: Kevin Wolf =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M monitor/hmp-cmds.c=0D =0D Log Message:=0D -----------=0D hmp: Fix loadvm to resume the VM on success instead of failure=0D =0D Commit f61fe11aa6f broke hmp_loadvm() by adding an incorrect negation=0D when converting from 0/-errno return values to a bool value. The result=0D= is that loadvm resumes the VM now if it failed and keeps it stopped if=0D= it failed. Fix it to restore the old behaviour and do it the other way=0D= around.=0D =0D Fixes: f61fe11aa6f7f8f0ffe4ddaa56a8108f3ab57854=0D Cc: qemu-stable@nongnu.org=0D Reported-by: Yanhui Ma =0D Signed-off-by: Kevin Wolf =0D Message-Id: <20210511163151.45167-1-kwolf@redhat.com>=0D Reviewed-by: Dr. David Alan Gilbert =0D Signed-off-by: Dr. David Alan Gilbert =0D (cherry picked from commit c53cd04e70641fdf9410aac40c617d074047b3e1)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: ad8c49081aad03dbeab57717280326d3d98d659e=0D https://github.com/qemu/qemu/commit/ad8c49081aad03dbeab57717280326d= 3d98d659e=0D Author: Paolo Bonzini =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D configure: fix detection of gdbus-codegen=0D =0D "pkg-config --variable=3Dgdbus_codegen gio-2.0" returns "gdbus-codegen",=0D= and it does not pass test -x (which does not walk the path).=0D =0D Meson 0.58.0 notices that something is iffy, as the dbus_vmstate1=0D assignment in tests/qtest/meson.build uses an empty string as the=0D command, and fails very eloquently:=0D =0D ../tests/qtest/meson.build:92:2: ERROR: No program name specified.=0D =0D Use the "has" function instead of test -x, and fix the generation=0D of config-host.mak since meson.build expects that GDBUS_CODEGEN=0D is absent, rather than empty, if the tool is unavailable.=0D =0D Reported-by: Sebastian Mitterle =0D Fixes: #178=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 5ecfb76ccc056eb6127e44268e475827ae73b9e0)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 8d719825d93b219d3de046e3e41ccc6ff39bea11=0D https://github.com/qemu/qemu/commit/8d719825d93b219d3de046e3e41ccc6= ff39bea11=0D Author: Jason Wang =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: don't initialize backend_features=0D =0D We used to initialize backend_features during vhost_vdpa_init()=0D regardless whether or not it was supported by vhost. This will lead=0D the unsupported features like VIRTIO_F_IN_ORDER to be included and set=0D= to the vhost-vdpa during vhost_dev_start. Because the=0D VIRTIO_F_IN_ORDER is not supported by vhost-vdpa so it won't be=0D advertised to guest which will break the datapath.=0D =0D Fix this by not initializing the backend_features, so the=0D acked_features could be built only from guest features via=0D vhost_net_ack_features().=0D =0D Fixes: 108a64818e69b ("vhost-vdpa: introduce vhost-vdpa backend")=0D Cc: qemu-stable@nongnu.org=0D Cc: Gautam Dawar =0D Signed-off-by: Jason Wang =0D (cherry picked from commit c33f23a419f95da16ab4faaf08be635c89b96ff0)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 44e5878ce34d27dbebd4198766eb843833f4972e=0D https://github.com/qemu/qemu/commit/44e5878ce34d27dbebd4198766eb843= 833f4972e=0D Author: Mark Cave-Ayland =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/scsi/esp.c=0D =0D Log Message:=0D -----------=0D esp: only assert INTR_DC interrupt flag if selection fails=0D =0D The datasheet sequence tables confirm that when a target selection fails,= only=0D the INTR_DC interrupt flag should be asserted.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Fixes: cf47a41e05 ("esp: latch individual bits in ESP_RINTR register")=0D= Message-Id: <20210518212511.21688-2-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit cf1a7a9b3721544aaa3e43d111eb383c30d71a62)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: b6f5c02f5f757e0aec2869b336a3ea11ed5eec7c=0D https://github.com/qemu/qemu/commit/b6f5c02f5f757e0aec2869b336a3ea1= 1ed5eec7c=0D Author: Mark Cave-Ayland =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/scsi/esp.c=0D =0D Log Message:=0D -----------=0D esp: only set ESP_RSEQ at the start of the select sequence=0D =0D When processing a command to select a target and send a CDB, the ESP devi= ce=0D maintains a sequence step register so that if an error occurs the host ca= n=0D determine which part of the selection/CDB submission sequence failed.=0D =0D The old Linux 2.6 driver is really pedantic here: it checks the sequence = step=0D register even if a command succeeds and complains loudly on the console i= f the=0D sequence step register doesn't match the expected bus phase and interrupt= flags.=0D =0D This reason this mismatch occurs is because the ESP emulation currently d= oesn't=0D update the bus phase until the next TI (Transfer Information) command and= so the=0D cleared sequence step register is considered invalid for the stale bus ph= ase.=0D =0D Normally this isn't an issue as the host only checks the sequence step re= gister=0D if an error occurs but the old Linux 2.6 driver does this in several plac= es=0D causing a large stream of "esp0: STEP_ASEL for tgt 0" messages to appear = on the=0D console during the boot process.=0D =0D Fix this by not clearing the sequence step register when reading the inte= rrupt=0D register and clearing the DMA status, so the guest sees a valid sequence = step=0D and bus phase combination at the end of the command phase. No other chang= e is=0D required since the sequence step register is correctly updated throughout= the=0D selection/CDB submission sequence once one of the select commands is issu= ed.=0D =0D Signed-off-by: Mark Cave-Ayland =0D Fixes: 1b9e48a5bd ("esp: implement non-DMA transfers in PDMA mode")=0D Message-Id: <20210518212511.21688-3-mark.cave-ayland@ilande.co.uk>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit af947a3d853a235943681a00f07f3081f5143cc3)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: d1000ee07b02c3a6f87a39b45d1b8c5689a14aa9=0D https://github.com/qemu/qemu/commit/d1000ee07b02c3a6f87a39b45d1b8c5= 689a14aa9=0D Author: Peng Liang =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M softmmu/runstate.c=0D =0D Log Message:=0D -----------=0D runstate: Initialize Error * to NULL=0D =0D Based on the description of error_setg(), the local variable err in=0D qemu_init_subsystems() should be initialized to NULL.=0D =0D Fixes: efd7ab22fb ("vl: extract qemu_init_subsystems")=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Peng Liang =0D Message-Id: <20210610131729.3906565-1-liangpeng10@huawei.com>=0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 6e1da3d305499d3907f3c7f6638243e2e09b5085)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 5b55370e28e262fba0c95f5dc05e9551c875671a=0D https://github.com/qemu/qemu/commit/5b55370e28e262fba0c95f5dc05e955= 1c875671a=0D Author: Kunkun Jiang =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/vfio/migration.c=0D =0D Log Message:=0D -----------=0D vfio: Fix unregister SaveVMHandler in vfio_migration_finalize=0D =0D In the vfio_migration_init(), the SaveVMHandler is registered for=0D VFIO device. But it lacks the operation of 'unregister'. It will=0D lead to 'Segmentation fault (core dumped)' in=0D qemu_savevm_state_setup(), if performing live migration after a=0D VFIO device is hot deleted.=0D =0D Fixes: 7c2f5f75f94 (vfio: Register SaveVMHandlers for VFIO device)=0D Reported-by: Qixin Gan =0D Signed-off-by: Kunkun Jiang =0D Message-Id: <20210527123101.289-1-jiangkunkun@huawei.com>=0D Reviewed by: Kirti Wankhede =0D Signed-off-by: Alex Williamson =0D (cherry picked from commit 22fca190e25b10761925bb1eeadeda07aabf3c26)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: cdb8a71e2e4bcef3a7815d6a3d02bb8da2a1001d=0D https://github.com/qemu/qemu/commit/cdb8a71e2e4bcef3a7815d6a3d02bb8= da2a1001d=0D Author: Zhenzhong Duan =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M softmmu/vl.c=0D =0D Log Message:=0D -----------=0D vl: Fix an assert failure in error path=0D =0D Based on the description of error_setg(), the local variable err in=0D qemu_maybe_daemonize() should be initialized to NULL.=0D =0D Without fix, the uninitialized *errp triggers assert failure which=0D doesn't show much valuable information.=0D =0D Before the fix:=0D qemu-system-x86_64: ../util/error.c:59: error_setv: Assertion `*errp =3D=3D= NULL' failed.=0D =0D After fix:=0D qemu-system-x86_64: cannot create PID file: Cannot open pid file: Permiss= ion denied=0D =0D Signed-off-by: Zhenzhong Duan =0D Message-Id: <20210610084741.456260-1-zhenzhong.duan@intel.com>=0D Cc: qemu-stable@nongnu.org=0D Fixes: 0546c0609c ("vl: split various early command line options to a sep= arate function", 2020-12-10)=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 38f71349c7c4969bc14da4da1c70b8cc4078d596)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 1a0a1c49649f7e7b2116daa127337a003bb0dcfb=0D https://github.com/qemu/qemu/commit/1a0a1c49649f7e7b2116daa127337a0= 03bb0dcfb=0D Author: Richard Henderson =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M tcg/sparc/tcg-target.c.inc=0D M tcg/tcg.c=0D =0D Log Message:=0D -----------=0D tcg/sparc: Fix temp_allocate_frame vs sparc stack bias=0D =0D We should not be aligning the offset in temp_allocate_frame,=0D because the odd offset produces an aligned address in the end.=0D Instead, pass the logical offset into tcg_set_frame and add=0D the stack bias last.=0D =0D Cc: qemu-stable@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D (cherry picked from commit 9defd1bdfb0f2ddb3ca9863e39577f3a9929d58c)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 059ad82f38073afb5aaa2245aeeda7eee608fc79=0D https://github.com/qemu/qemu/commit/059ad82f38073afb5aaa2245aeeda7e= ee608fc79=0D Author: Richard Henderson =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg.c=0D =0D Log Message:=0D -----------=0D tcg: Allocate sufficient storage in temp_allocate_frame=0D =0D This function should have been updated for vector types=0D when they were introduced.=0D =0D Fixes: d2fd745fe8b=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367=0D Cc: qemu-stable@nongnu.org=0D Tested-by: Stefan Weil =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D (cherry picked from commit c1c091948ae4a73c1a80b5005f6204d0e665ce52)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 0a579d4389fb52bd139cec5457b2a27fc29b78f7=0D https://github.com/qemu/qemu/commit/0a579d4389fb52bd139cec5457b2a27= fc29b78f7=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/pci-host/q35.c=0D =0D Log Message:=0D -----------=0D hw/pci-host/q35: Ignore write of reserved PCIEXBAR LENGTH field=0D =0D libFuzzer triggered the following assertion:=0D =0D cat << EOF | qemu-system-i386 -M pc-q35-5.0 \=0D -nographic -monitor none -serial none \=0D -qtest stdio -d guest_errors -trace pci\*=0D outl 0xcf8 0xf2000060=0D outl 0xcfc 0x8400056e=0D EOF=0D pci_cfg_write mch 00:0 @0x60 <- 0x8400056e=0D Aborted (core dumped)=0D =0D This is because guest wrote MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD=0D (reserved value) to the PCIE XBAR register.=0D =0D There is no indication on the datasheet about what occurs when=0D this value is written. Simply ignore it on QEMU (and report an=0D guest error):=0D =0D pci_cfg_write mch 00:0 @0x60 <- 0x8400056e=0D Q35: Reserved PCIEXBAR LENGTH=0D pci_cfg_read mch 00:0 @0x0 -> 0x8086=0D pci_cfg_read mch 00:0 @0x0 -> 0x29c08086=0D ...=0D =0D Cc: qemu-stable@nongnu.org=0D Reported-by: Alexander Bulekov =0D BugLink: https://bugs.launchpad.net/qemu/+bug/1878641=0D Fixes: df2d8b3ed4 ("q35: Introduce q35 pc based chipset emulator")=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210526142438.281477-1-f4bug@amsat.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Alexander Bulekov =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D (cherry picked from commit 9b0ca75e0196a72523232063db1e07ae36a5077a)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 072a8d3693b40f46efcc7b05f6f4136760e57612=0D https://github.com/qemu/qemu/commit/072a8d3693b40f46efcc7b05f6f4136= 760e57612=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M block/nvme.c=0D =0D Log Message:=0D -----------=0D block/nvme: Fix VFIO_MAP_DMA failed: No space left on device=0D =0D When the NVMe block driver was introduced (see commit bdd6a90a9e5,=0D January 2018), Linux VFIO_IOMMU_MAP_DMA ioctl was only returning=0D -ENOMEM in case of error. The driver was correctly handling the=0D error path to recycle its volatile IOVA mappings.=0D =0D To fix CVE-2019-3882, Linux commit 492855939bdb ("vfio/type1: Limit=0D DMA mappings per container", April 2019) added the -ENOSPC error to=0D signal the user exhausted the DMA mappings available for a container.=0D =0D The block driver started to mis-behave:=0D =0D qemu-system-x86_64: VFIO_MAP_DMA failed: No space left on device=0D (qemu)=0D (qemu) info status=0D VM status: paused (io-error)=0D (qemu) c=0D VFIO_MAP_DMA failed: No space left on device=0D (qemu) c=0D VFIO_MAP_DMA failed: No space left on device=0D =0D (The VM is not resumable from here, hence stuck.)=0D =0D Fix by handling the new -ENOSPC error (when DMA mappings are=0D exhausted) without any distinction to the current -ENOMEM error,=0D so we don't change the behavior on old kernels where the CVE-2019-3882=0D= fix is not present.=0D =0D An easy way to reproduce this bug is to restrict the DMA mapping=0D limit (65535 by default) when loading the VFIO IOMMU module:=0D =0D # modprobe vfio_iommu_type1 dma_entry_limit=3D666=0D =0D Cc: qemu-stable@nongnu.org=0D Cc: Fam Zheng =0D Cc: Maxim Levitsky =0D Cc: Alex Williamson =0D Reported-by: Michal Pr=C3=ADvozn=C3=ADk =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20210723195843.1032825-1-philmd@redhat.com=0D Fixes: bdd6a90a9e5 ("block: Add VFIO based NVMe driver")=0D Buglink: https://bugs.launchpad.net/qemu/+bug/1863333=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/65=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Stefan Hajnoczi =0D (cherry picked from commit 15a730e7a3aaac180df72cd5730e0617bcf44a5a)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 7e84d58e8be9c8b64710982f947f63b95816d311=0D https://github.com/qemu/qemu/commit/7e84d58e8be9c8b64710982f947f63b= 95816d311=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M crypto/tlscreds.c=0D M include/crypto/tlscreds.h=0D =0D Log Message:=0D -----------=0D crypto/tlscreds: Introduce qcrypto_tls_creds_check_endpoint() helper=0D= =0D Introduce the qcrypto_tls_creds_check_endpoint() helper=0D to access QCryptoTLSCreds internal 'endpoint' field.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit e9ac68083f26759b85ef0d871ca2bbe897218f64)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 738ff4bf07304399d3d830afd4b5e3296fbb3cce=0D https://github.com/qemu/qemu/commit/738ff4bf07304399d3d830afd4b5e32= 96fbb3cce=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M block/nbd.c=0D M blockdev-nbd.c=0D =0D Log Message:=0D -----------=0D block/nbd: Use qcrypto_tls_creds_check_endpoint()=0D =0D Avoid accessing QCryptoTLSCreds internals by using=0D the qcrypto_tls_creds_check_endpoint() helper.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 7b3b616838c30830c004b746e7b1209297118318)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 8d5c255a2569b01c56b32783da93b1c2f15c7deb=0D https://github.com/qemu/qemu/commit/8d5c255a2569b01c56b32783da93b1c= 2f15c7deb=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M qemu-nbd.c=0D =0D Log Message:=0D -----------=0D qemu-nbd: Use qcrypto_tls_creds_check_endpoint()=0D =0D Avoid accessing QCryptoTLSCreds internals by using=0D the qcrypto_tls_creds_check_endpoint() helper.=0D =0D Tested-by: Akihiko Odaki =0D Reviewed-by: Eric Blake =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 0279cd9535283cf5711768ab6401b204e5697a81)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 0a7e2c99f9cbe6c64e0e7ba002d362d0e4b6dc5c=0D https://github.com/qemu/qemu/commit/0a7e2c99f9cbe6c64e0e7ba002d362d= 0e4b6dc5c=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M chardev/char-socket.c=0D =0D Log Message:=0D -----------=0D chardev/socket: Use qcrypto_tls_creds_check_endpoint()=0D =0D Avoid accessing QCryptoTLSCreds internals by using=0D the qcrypto_tls_creds_check_endpoint() helper.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 8612df2ebef9ff1f880fe76d223a3369b9c98db2)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: a1c966bdf4174f238077784016854231033034cf=0D https://github.com/qemu/qemu/commit/a1c966bdf4174f23807778401685423= 1033034cf=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M migration/tls.c=0D =0D Log Message:=0D -----------=0D migration/tls: Use qcrypto_tls_creds_check_endpoint()=0D =0D Avoid accessing QCryptoTLSCreds internals by using=0D the qcrypto_tls_creds_check_endpoint() helper.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 5590f65facc508fbc38575f19a0ab2fdcdcf18a4)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 43844c2fb2fffd0f710071259453714acb804c07=0D https://github.com/qemu/qemu/commit/43844c2fb2fffd0f710071259453714= acb804c07=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M ui/vnc.c=0D =0D Log Message:=0D -----------=0D ui/vnc: Use qcrypto_tls_creds_check_endpoint()=0D =0D Avoid accessing QCryptoTLSCreds internals by using=0D the qcrypto_tls_creds_check_endpoint() helper.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 3c52bf0c608419d7892fea95f2a0af8f2e99633e)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 747fd3cb1336e482c2da31036cb2706e9c45074d=0D https://github.com/qemu/qemu/commit/747fd3cb1336e482c2da31036cb2706= e9c45074d=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M crypto/tls-cipher-suites.c=0D M crypto/tlscredsanon.c=0D M crypto/tlscredspriv.h=0D M crypto/tlscredspsk.c=0D M crypto/tlscredsx509.c=0D M crypto/tlssession.c=0D M include/crypto/tls-cipher-suites.h=0D M include/crypto/tlscreds.h=0D M include/crypto/tlscredsanon.h=0D M include/crypto/tlscredspsk.h=0D M include/crypto/tlscredsx509.h=0D =0D Log Message:=0D -----------=0D crypto: Make QCryptoTLSCreds* structures private=0D =0D Code consuming the "crypto/tlscreds*.h" APIs doesn't need=0D to access its internals. Move the structure definitions to=0D the "tlscredspriv.h" private header (only accessible by=0D implementations). The public headers (in include/) still=0D forward-declare the structures typedef.=0D =0D Note, tlscreds.c and 3 of the 5 modified source files already=0D include "tlscredspriv.h", so only add it to tls-cipher-suites.c=0D and tlssession.c.=0D =0D Removing the internals from the public header solves a bug=0D introduced by commit 7de2e856533 ("yank: Unregister function=0D when using TLS migration") which made migration/qemu-file-channel.c=0D include "io/channel-tls.h", itself sometime depends on GNUTLS,=0D leading to a build failure on OSX:=0D =0D [2/35] Compiling C object libmigration.fa.p/migration_qemu-file-channel= .c.o=0D FAILED: libmigration.fa.p/migration_qemu-file-channel.c.o=0D cc -Ilibmigration.fa.p -I. -I.. -Iqapi [ ... ] -o libmigration.fa.p/mig= ration_qemu-file-channel.c.o -c ../migration/qemu-file-channel.c=0D In file included from ../migration/qemu-file-channel.c:29:=0D In file included from include/io/channel-tls.h:26:=0D In file included from include/crypto/tlssession.h:24:=0D include/crypto/tlscreds.h:28:10: fatal error: 'gnutls/gnutls.h' file no= t found=0D #include =0D ^~~~~~~~~~~~~~~~~=0D 1 error generated.=0D =0D Reported-by: Stefan Weil =0D Suggested-by: Daniel P. Berrang=C3=A9 =0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/407=0D Fixes: 7de2e856533 ("yank: Unregister function when using TLS migration")= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Daniel P. Berrang=C3=A9 =0D (cherry picked from commit 678bcc3c2cf22262d0a72b52da57737c4a40e040)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 22de6752c12383e0778177fda314566d1d54b54f=0D https://github.com/qemu/qemu/commit/22de6752c12383e0778177fda314566= d1d54b54f=0D Author: Leonardo Bras =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M migration/channel.c=0D M migration/multifd.c=0D M migration/qemu-file-channel.c=0D =0D Log Message:=0D -----------=0D yank: Unregister function when using TLS migration=0D =0D After yank feature was introduced in migration, whenever migration=0D is started using TLS, the following error happens in both source and=0D destination hosts:=0D =0D (qemu) qemu-kvm: ../util/yank.c:107: yank_unregister_instance:=0D Assertion `QLIST_EMPTY(&entry->yankfns)' failed.=0D =0D This happens because of a missing yank_unregister_function() when using=0D= qio-channel-tls.=0D =0D Fix this by also allowing TYPE_QIO_CHANNEL_TLS object type to perform=0D yank_unregister_function() in channel_close() and multifd_load_cleanup().= =0D =0D Also, inside migration_channel_connect() and=0D migration_channel_process_incoming() move yank_register_function() so=0D it only runs once on a TLS migration.=0D =0D Fixes: b5eea99ec2f ("migration: Add yank feature", 2021-01-13)=0D Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=3D1964326=0D Signed-off-by: Leonardo Bras =0D Reviewed-by: Lukas Straub =0D Reviewed-by: Peter Xu =0D =0D --=0D Changes since v2:=0D - Dropped all references to ioc->master=0D - yank_register_function() and yank_unregister_function() now only run=0D= once in a TLS migration.=0D =0D Changes since v1:=0D - Cast p->c to QIOChannelTLS into multifd_load_cleanup()=0D Message-Id: <20210601054030.1153249-1-leobras.c@gmail.com>=0D =0D Signed-off-by: Dr. David Alan Gilbert =0D (cherry picked from commit 7de2e8565335c13fb3516cddbe2e40e366cce273)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: e23fe27ed9fa45d44b2234309565e42284165e86=0D https://github.com/qemu/qemu/commit/e23fe27ed9fa45d44b2234309565e42= 284165e86=0D Author: Igor Mammedov =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: prepare for changing DSDT tables=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210624204229.998824-2-imammedo@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Tested-by: John Sucaet =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D (cherry picked from commit a4344574fd47336b6d8fc85ce1f66d4262e7dafd)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: b989641145f079d487edce798b7557e47ee080a9=0D https://github.com/qemu/qemu/commit/b989641145f079d487edce798b7557e= 47ee080a9=0D Author: Igor Mammedov =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/i386/acpi-build.c=0D =0D Log Message:=0D -----------=0D acpi: pc: revert back to v5.2 PCI slot enumeration=0D =0D Commit [1] moved _SUN variable from only hot-pluggable to=0D all devices. This made linux kernel enumerate extra slots=0D that weren't present before. If extra slot happens to be=0D be enumerated first and there is a device in th same slot=0D but on other bridge, linux kernel will add -N suffix to=0D slot name of the later, thus changing NIC name compared to=0D QEMU 5.2. This in some case confuses systemd, if it is=0D using SLOT NIC naming scheme and interface name becomes=0D not the same as it was under QEMU-5.2.=0D =0D Reproducer QEMU CLI:=0D -M pc-i440fx-5.2 -nodefaults \=0D -device pci-bridge,chassis_nr=3D1,id=3Dpci.1,bus=3Dpci.0,addr=3D0x3 \=0D= -device virtio-net-pci,id=3Dnic1,bus=3Dpci.1,addr=3D0x1 \=0D -device virtio-net-pci,id=3Dnic2,bus=3Dpci.1,addr=3D0x2 \=0D -device virtio-net-pci,id=3Dnic3,bus=3Dpci.1,addr=3D0x3=0D =0D with RHEL8 guest produces following results:=0D v5.2:=0D kernel: virtio_net virtio0 ens1: renamed from eth0=0D kernel: virtio_net virtio2 ens3: renamed from eth2=0D kernel: virtio_net virtio1 enp1s2: renamed from eth1=0D (slot 2 is assigned to empty bus 0 slot and virtio1=0D is assigned to 2-2 slot, and renaming falls back,=0D for some reason, to path based naming scheme)=0D =0D v6.0:=0D kernel: virtio_net virtio0 ens1: renamed from eth0=0D kernel: virtio_net virtio2 ens3: renamed from eth2=0D systemd-udevd[299]: Error changing net interface name 'eth1' to 'ens= 3': File exists=0D systemd-udevd[299]: could not rename interface '3' from 'eth1' to 'e= ns3': File exists=0D (with commit [1] kernel assigns virtio2 to 3-2 slot=0D since bridge advertises _SUN=3D0x3 and kernel assigns=0D slot 3 to bridge. Still it manages to rename virtio2=0D correctly to ens3, however systemd gets confused with virtio1=0D where slot allocation exactly the same (2-2) as in 5.2 case=0D and tries to rename it to ens3 which is rightfully taken by=0D virtio2)=0D =0D I'm not sure what breaks in systemd interface renaming (it probably=0D should be investigated), but on QEMU side we can safely revert=0D _SUN to 5.2 behavior (i.e. avoid cold-plugged bridges and non=0D hot-pluggable device classes), without breaking acpi-index, which uses=0D= slot numbers but it doesn't have to use _SUN, it could use an arbitrary=0D= variable name that has the same slot value).=0D It will help existing VMs to keep networking with non trivial=0D configs in working order since systemd will do its interface=0D renaming magic as it used to do.=0D =0D 1)=0D Fixes: b7f23f62e40 (pci: acpi: add _DSM method to PCI devices)=0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210624204229.998824-3-imammedo@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Tested-by: John Sucaet =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D (cherry picked from commit 7193d7cdd93e50f0e5f09803b98d27d3f9b147ac)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 765ed56e7606c0993e47619db38471d3210963c4=0D https://github.com/qemu/qemu/commit/765ed56e7606c0993e47619db38471d= 3210963c4=0D Author: Igor Mammedov =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/pc/DSDT=0D M tests/data/acpi/pc/DSDT.acpihmat=0D M tests/data/acpi/pc/DSDT.bridge=0D M tests/data/acpi/pc/DSDT.cphp=0D M tests/data/acpi/pc/DSDT.dimmpxm=0D M tests/data/acpi/pc/DSDT.hpbridge=0D M tests/data/acpi/pc/DSDT.ipmikcs=0D M tests/data/acpi/pc/DSDT.memhp=0D M tests/data/acpi/pc/DSDT.nohpet=0D M tests/data/acpi/pc/DSDT.numamem=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: pc: update expected DSDT blobs=0D =0D @@ -930,20 +930,20 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC = ", 0x00000001)=0D Device (S00)=0D {=0D Name (_ADR, Zero) // _ADR: Address=0D - Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (ASUN, Zero)=0D Method (_DSM, 4, Serialized) // _DSM: Device-Specific M= ethod=0D {=0D - Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))=0D= + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN))=0D= }=0D }=0D =0D Device (S10)=0D {=0D Name (_ADR, 0x00020000) // _ADR: Address=0D - Name (_SUN, 0x02) // _SUN: Slot User Number=0D + Name (ASUN, 0x02)=0D Method (_DSM, 4, Serialized) // _DSM: Device-Specific M= ethod=0D {=0D - Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))=0D= + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN))=0D= }=0D =0D Method (_S1D, 0, NotSerialized) // _S1D: S1 Device Stat= e=0D =0D with a hank per bridge:=0D =0D @@ -965,10 +965,10 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC = ", 0x00000001)=0D Device (S18)=0D {=0D Name (_ADR, 0x00030000) // _ADR: Address=0D - Name (_SUN, 0x03) // _SUN: Slot User Number=0D + Name (ASUN, 0x03)=0D Method (_DSM, 4, Serialized) // _DSM: Device-Specific M= ethod=0D {=0D - Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))=0D= + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN))=0D= }=0D }=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210624204229.998824-4-imammedo@redhat.com>=0D Reviewed-by: Stefan Hajnoczi =0D Tested-by: John Sucaet =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D (cherry picked from commit 40f23e4e52f6188036062abea432560e5cdd239a)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: aa99651295cf13aafa8db030c3cc1a0c1b64427d=0D https://github.com/qemu/qemu/commit/aa99651295cf13aafa8db030c3cc1a0= c1b64427d=0D Author: Gollu Appalanaidu =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/block/nvme-ns.c=0D M hw/block/nvme.c=0D M include/block/nvme.h=0D =0D Log Message:=0D -----------=0D hw/block/nvme: align with existing style=0D =0D While QEMU coding style prefers lowercase hexadecimals in constants, the=0D= NVMe subsystem uses the format from the NVMe specifications in comments,=0D= i.e. 'h' suffix instead of '0x' prefix.=0D =0D Fix this up across the code base.=0D =0D Signed-off-by: Gollu Appalanaidu =0D [k.jensen: updated message; added conversion in a couple of missing comme= nts]=0D Signed-off-by: Klaus Jensen =0D (cherry picked from commit 312c3531bba416e589f106db8c8241fc6e7e6332)=0D *context dependency for 2b02aabc9d=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: bef905cd8a3eb0753262703ecebf2fae0658154b=0D https://github.com/qemu/qemu/commit/bef905cd8a3eb0753262703ecebf2fa= e0658154b=0D Author: Klaus Jensen =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/block/nvme.c=0D =0D Log Message:=0D -----------=0D hw/nvme: fix missing check for PMR capability=0D =0D Qiang Liu reported that an access on an unknown address is triggered in=0D= memory_region_set_enabled because a check on CAP.PMRS is missing for the=0D= PMRCTL register write when no PMR is configured.=0D =0D Cc: qemu-stable@nongnu.org=0D Fixes: 75c3c9de961d ("hw/block/nvme: disable PMR at boot up")=0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/362=0D Signed-off-by: Klaus Jensen =0D Reviewed-by: Keith Busch =0D (cherry picked from commit 2b02aabc9d02f9e95946cf639f546bb61f1721b7)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 6576f6ab8726e52fbd9060224670683bc3e613d6=0D https://github.com/qemu/qemu/commit/6576f6ab8726e52fbd9060224670683= bc3e613d6=0D Author: Klaus Jensen =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/block/nvme.c=0D M hw/block/nvme.h=0D =0D Log Message:=0D -----------=0D hw/nvme: fix pin-based interrupt behavior (again)=0D =0D Jakub noticed[1] that, when using pin-based interrupts, the device will=0D= unconditionally deasssert when any CQEs are acknowledged. However, the=0D= pin should not be deasserted if other completion queues still holds=0D unacknowledged CQEs.=0D =0D The bug is an artifact of commit ca247d35098d ("hw/block/nvme: fix=0D pin-based interrupt behavior") which fixed one bug but introduced=0D another. This is the third time someone tries to fix pin-based=0D interrupts (see commit 5e9aa92eb1a5 ("hw/block: Fix pin-based interrupt=0D= behaviour of NVMe"))...=0D =0D Third time's the charm, so fix it, again, by keeping track of how many=0D= CQs have unacknowledged CQEs and only deassert when all are cleared.=0D =0D [1]: <20210610114624.304681-1-jakub.jermar@kernkonzept.com>=0D =0D Cc: qemu-stable@nongnu.org=0D Fixes: ca247d35098d ("hw/block/nvme: fix pin-based interrupt behavior")=0D= Reported-by: Jakub Jerm=C3=A1=C5=99 =0D Signed-off-by: Klaus Jensen =0D Reviewed-by: Keith Busch =0D (cherry picked from commit 83d7ed5c570d4c1d5163951b3057cac2ae7da4ff)=0D *avoid dependency on 88eea45c ("hw/nvme: move nvme emulation out of hw/bl= ock")=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 7999d5b12f336b4b2064361c163e06878e5d20e8=0D https://github.com/qemu/qemu/commit/7999d5b12f336b4b2064361c163e068= 78e5d20e8=0D Author: David Hildenbrand =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-balloon.c=0D =0D Log Message:=0D -----------=0D virtio-balloon: don't start free page hinting if postcopy is possible=0D= =0D Postcopy never worked properly with 'free-page-hint=3Don', as there are=0D= at least two issues:=0D =0D 1) With postcopy, the guest will never receive a VIRTIO_BALLOON_CMD_ID_DO= NE=0D and consequently won't release free pages back to the OS once=0D migration finishes.=0D =0D The issue is that for postcopy, we won't do a final bitmap sync while=0D= the guest is stopped on the source and=0D virtio_balloon_free_page_hint_notify() will only call=0D virtio_balloon_free_page_done() on the source during=0D PRECOPY_NOTIFY_CLEANUP, after the VM state was already migrated to=0D the destination.=0D =0D 2) Once the VM touches a page on the destination that has been excluded=0D= from migration on the source via qemu_guest_free_page_hint() while=0D postcopy is active, that thread will stall until postcopy finishes=0D and all threads are woken up. (with older Linux kernels that won't=0D retry faults when woken up via userfaultfd, we might actually get a=0D= SEGFAULT)=0D =0D The issue is that the source will refuse to migrate any pages that=0D are not marked as dirty in the dirty bmap -- for example, because the=0D= page might just have been sent. Consequently, the faulting thread will= =0D stall, waiting for the page to be migrated -- which could take quite=0D= a while and result in guest OS issues.=0D =0D While we could fix 1) comparatively easily, 2) is harder to get right and= =0D might require more involved RAM migration changes on source and destinati= on=0D [1].=0D =0D As it never worked properly, let's not start free page hinting in the=0D precopy notifier if the postcopy migration capability was enabled to fix=0D= it easily. Capabilities cannot be enabled once migration is already=0D running.=0D =0D Note 1: in the future we might either adjust migration code on the source= =0D to track pages that have actually been sent or adjust=0D migration code on source and destination to eventually send=0D pages multiple times from the source and and deal with pages=0D that are sent multiple times on the destination.=0D =0D Note 2: virtio-mem has similar issues, however, access to "unplugged"=0D memory by the guest is very rare and we would have to be very=0D lucky for it to happen during migration. The spec states=0D "The driver SHOULD NOT read from unplugged memory blocks ..."=0D and "The driver MUST NOT write to unplugged memory blocks".=0D virtio-mem will move away from virtio_balloon_free_page_done()=0D= soon and handle this case explicitly on the destination.=0D =0D [1] https://lkml.kernel.org/r/e79fd18c-aa62-c1d8-c7f3-ba3fc2c25fc8@redhat= .com=0D =0D Fixes: c13c4153f76d ("virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_HINT")=0D= Cc: qemu-stable@nongnu.org=0D Cc: Wei Wang =0D Cc: Michael S. Tsirkin =0D Cc: Philippe Mathieu-Daud=C3=A9 =0D Cc: Alexander Duyck =0D Cc: Juan Quintela =0D Cc: "Dr. David Alan Gilbert" =0D Cc: Peter Xu =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20210708095339.20274-2-david@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Peter Xu =0D (cherry picked from commit fd51e54fa10221e5a8add894c38cc1cf199f4bc4)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 4d3cfb2f6bb6afa07d0a9629136ae71eb6ab0268=0D https://github.com/qemu/qemu/commit/4d3cfb2f6bb6afa07d0a9629136ae71= eb6ab0268=0D Author: Pavel Pisa =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/net/can/can_sja1000.c=0D =0D Log Message:=0D -----------=0D hw/net/can: sja1000 fix buff2frame_bas and buff2frame_pel when dlc is o= ut of std CAN 8 bytes=0D =0D Problem reported by openEuler fuzz-sig group.=0D =0D The buff2frame_bas function (hw\net\can\can_sja1000.c)=0D infoleak(qemu5.x~qemu6.x) or stack-overflow(qemu 4.x).=0D =0D Reported-by: Qiang Ning =0D Cc: qemu-stable@nongnu.org=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Pavel Pisa =0D Signed-off-by: Jason Wang =0D (cherry picked from commit 11744862f27b9ba6488a247d2fd6bb83d9bc3c8d)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 21611dd0a5634946367137a30f52a7677ff75928=0D https://github.com/qemu/qemu/commit/21611dd0a5634946367137a30f52a76= 77ff75928=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/sd/sd.c=0D =0D Log Message:=0D -----------=0D hw/sd/sdcard: Document out-of-range addresses for SEND_WRITE_PROT=0D =0D Per the 'Physical Layer Simplified Specification Version 3.01',=0D Table 4-22: 'Block Oriented Write Protection Commands'=0D =0D SEND_WRITE_PROT (CMD30)=0D =0D If the card provides write protection features, this command asks=0D the card to send the status of the write protection bits [1].=0D =0D [1] 32 write protection bits (representing 32 write protect groups=0D starting at the specified address) [...]=0D The last (least significant) bit of the protection bits corresponds=0D to the first addressed group. If the addresses of the last groups=0D are outside the valid range, then the corresponding write protection=0D= bits shall be set to 0.=0D =0D Split the if() statement (without changing the behaviour of the code)=0D to better position the description comment.=0D =0D Reviewed-by: Alexander Bulekov =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210802235524.3417739-2-f4bug@amsat.org>=0D Reviewed-by: Peter Maydell =0D Tested-by: Alexander Bulekov =0D (cherry picked from commit 2a0396285daa9483459ec1d3791951300b595e85)=0D *context dependency for 4ac0b72bae ("hw/sd/sdcard: Fix assertion accessin= g out-of-range addresses with CMD30")=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 978c11b013bfd2a484c6b2ad0edb14bd754f23ac=0D https://github.com/qemu/qemu/commit/978c11b013bfd2a484c6b2ad0edb14b= d754f23ac=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M hw/sd/sd.c=0D =0D Log Message:=0D -----------=0D hw/sd/sdcard: Fix assertion accessing out-of-range addresses with CMD30= =0D =0D OSS-Fuzz found sending illegal addresses when querying the write=0D protection bits triggers the assertion added in commit 84816fb63e5=0D ("hw/sd/sdcard: Assert if accessing an illegal group"):=0D =0D qemu-fuzz-i386-target-generic-fuzz-sdhci-v3: ../hw/sd/sd.c:824: uint32_= t sd_wpbits(SDState *, uint64_t):=0D Assertion `wpnum < sd->wpgrps_size' failed.=0D #3 0x7f62a8b22c91 in __assert_fail=0D #4 0x5569adcec405 in sd_wpbits hw/sd/sd.c:824:9=0D #5 0x5569adce5f6d in sd_normal_command hw/sd/sd.c:1389:38=0D #6 0x5569adce3870 in sd_do_command hw/sd/sd.c:1737:17=0D #7 0x5569adcf1566 in sdbus_do_command hw/sd/core.c:100:16=0D #8 0x5569adcfc192 in sdhci_send_command hw/sd/sdhci.c:337:12=0D #9 0x5569adcfa3a3 in sdhci_write hw/sd/sdhci.c:1186:9=0D #10 0x5569adfb3447 in memory_region_write_accessor softmmu/memory.c:492= :5=0D =0D It is legal for the CMD30 to query for out-of-range addresses.=0D Such invalid addresses are simply ignored in the response (write=0D protection bits set to 0).=0D =0D In commit 84816fb63e5 ("hw/sd/sdcard: Assert if accessing an illegal=0D group") we misplaced the assertion *before* we test the address is=0D in range. Move it *after*.=0D =0D Include the qtest reproducer provided by Alexander Bulekov:=0D =0D $ make check-qtest-i386=0D ...=0D Running test qtest-i386/fuzz-sdcard-test=0D qemu-system-i386: ../hw/sd/sd.c:824: sd_wpbits: Assertion `wpnum < sd->= wpgrps_size' failed.=0D =0D Cc: qemu-stable@nongnu.org=0D Reported-by: OSS-Fuzz (Issue 29225)=0D Suggested-by: Peter Maydell =0D Fixes: 84816fb63e5 ("hw/sd/sdcard: Assert if accessing an illegal group")= =0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/495=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210802235524.3417739-3-f4bug@amsat.org>=0D Reviewed-by: Peter Maydell =0D Tested-by: Alexander Bulekov =0D (cherry picked from commit 4ac0b72bae85cf94ae0e5153b9c2c288c71667d4)=0D *drop fuzz test additions, since sdcard fuzz test has functional=0D dependency on guest-visible change not flagged for stable:=0D 59b63d78 ("hw/sd/sdcard: Check for valid address range in SEND_WRITE_PRO= T (CMD30)")=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 4fca33b4bec8afa8e902137c82a0f47a02134c13=0D https://github.com/qemu/qemu/commit/4fca33b4bec8afa8e902137c82a0f47= a02134c13=0D Author: Dr. David Alan Gilbert =0D Date: 2021-10-14 (Thu, 14 Oct 2021)=0D =0D Changed paths:=0D M audio/audio.c=0D =0D Log Message:=0D -----------=0D audio: Never send migration section=0D =0D The audio migration vmstate is empty, and always has been; we can't=0D just remove it though because an old qemu might send it us.=0D Changes with -audiodev now mean it's sometimes created when it didn't=0D used to be, and can confuse migration to old qemu.=0D =0D Change it so that vmstate_audio is never sent; if it's received it=0D should still be accepted, and old qemu's shouldn't be too upset if it's=0D= missing.=0D =0D Signed-off-by: Dr. David Alan Gilbert =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Tested-by: Daniel P. Berrang=C3=A9 =0D Message-Id: <20210809170956.78536-1-dgilbert@redhat.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit da77adbaf619c4d170cb42d769145ad1803fbad9)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 2ae61d81a575d22599fb22355acc995def2902fc=0D https://github.com/qemu/qemu/commit/2ae61d81a575d22599fb22355acc995= def2902fc=0D Author: Peter Maydell =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M target/arm/cpu.c=0D =0D Log Message:=0D -----------=0D target/arm: Don't skip M-profile reset entirely in user mode=0D =0D Currently all of the M-profile specific code in arm_cpu_reset() is=0D inside a !defined(CONFIG_USER_ONLY) ifdef block. This is=0D unintentional: it happened because originally the only=0D M-profile-specific handling was the setup of the initial SP and PC=0D from the vector table, which is system-emulation only. But then we=0D added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)"=0D code block without noticing that it was all inside a not-user-mode=0D ifdef. This has generally been harmless, but with the addition of=0D v8.1M low-overhead-loop support we ran into a problem: the reset of=0D FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so=0D if a user-mode guest tried to execute the LE instruction it would=0D incorrectly take a UsageFault.=0D =0D Adjust the ifdefs so only the really system-emulation specific parts=0D are covered. Because this means we now run some reset code that sets=0D up initial values in the FPCCR and similar FPU related registers,=0D explicitly set up the registers controlling FPU context handling in=0D user-emulation mode so that the FPU works by design and not by=0D chance.=0D =0D Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Peter Maydell =0D Reviewed-by: Richard Henderson =0D Message-id: 20210914120725.24992-2-peter.maydell@linaro.org=0D (cherry picked from commit b62ceeaf8096fdbbbfdc6087da0028bc4a4dd77e)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 5881d76ff41ab898751babdf26ea668cb8fb7a0e=0D https://github.com/qemu/qemu/commit/5881d76ff41ab898751babdf26ea668= cb8fb7a0e=0D Author: Jason Wang =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D =0D Log Message:=0D -----------=0D virtio-net: fix use after unmap/free for sg=0D =0D When mergeable buffer is enabled, we try to set the num_buffers after=0D the virtqueue elem has been unmapped. This will lead several issues,=0D E.g a use after free when the descriptor has an address which belongs=0D to the non direct access region. In this case we use bounce buffer=0D that is allocated during address_space_map() and freed during=0D address_space_unmap().=0D =0D Fixing this by storing the elems temporarily in an array and delay the=0D= unmap after we set the the num_buffers.=0D =0D This addresses CVE-2021-3748.=0D =0D Reported-by: Alexander Bulekov =0D Fixes: fbe78f4f55c6 ("virtio-net support")=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Jason Wang =0D (cherry picked from commit bedd7e93d01961fcb16a97ae45d93acf357e11f6)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 916372e48faf47ce0950d4cf2ae7d0b63c803227=0D https://github.com/qemu/qemu/commit/916372e48faf47ce0950d4cf2ae7d0b= 63c803227=0D Author: Nir Soffer =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M docs/tools/qemu-nbd.rst=0D M qemu-nbd.c=0D =0D Log Message:=0D -----------=0D qemu-nbd: Change default cache mode to writeback=0D =0D Both qemu and qemu-img use writeback cache mode by default, which is=0D already documented in qemu(1). qemu-nbd uses writethrough cache mode by=0D= default, and the default cache mode is not documented.=0D =0D According to the qemu-nbd(8):=0D =0D --cache=3DCACHE=0D The cache mode to be used with the file. See the=0D documentation of the emulator's -drive cache=3D... option for=0D= allowed values.=0D =0D qemu(1) says:=0D =0D The default mode is cache=3Dwriteback.=0D =0D So users have no reason to assume that qemu-nbd is using writethough=0D cache mode. The only hint is the painfully slow writing when using the=0D= defaults.=0D =0D Looking in git history, it seems that qemu used writethrough in the past=0D= to support broken guests that did not flush data properly, or could not=0D= flush due to limitations in qemu. But qemu-nbd clients can use=0D NBD_CMD_FLUSH to flush data, so using writethrough does not help anyone.=0D= =0D Change the default cache mode to writback, and document the default and=0D= available values properly in the online help and manual.=0D =0D With this change converting image via qemu-nbd is 3.5 times faster.=0D =0D $ qemu-img create dst.img 50g=0D $ qemu-nbd -t -f raw -k /tmp/nbd.sock dst.img=0D =0D Before this change:=0D =0D $ hyperfine -r3 "./qemu-img convert -p -f raw -O raw -T none -W fedor= a34.img nbd+unix:///?socket=3D/tmp/nbd.sock"=0D Benchmark #1: ./qemu-img convert -p -f raw -O raw -T none -W fedora34= .img nbd+unix:///?socket=3D/tmp/nbd.sock=0D Time (mean =C2=B1 =CF=83): 83.639 s =C2=B1 5.970 s [User: 2= .733 s, System: 6.112 s]=0D Range (min =E2=80=A6 max): 76.749 s =E2=80=A6 87.245 s 3 runs=0D= =0D After this change:=0D =0D $ hyperfine -r3 "./qemu-img convert -p -f raw -O raw -T none -W fedor= a34.img nbd+unix:///?socket=3D/tmp/nbd.sock"=0D Benchmark #1: ./qemu-img convert -p -f raw -O raw -T none -W fedora34= .img nbd+unix:///?socket=3D/tmp/nbd.sock=0D Time (mean =C2=B1 =CF=83): 23.522 s =C2=B1 0.433 s [User: 2= .083 s, System: 5.475 s]=0D Range (min =E2=80=A6 max): 23.234 s =E2=80=A6 24.019 s 3 runs=0D= =0D Users can avoid the issue by using --cache=3Dwriteback[1] but the default= s=0D should give good performance for the common use case.=0D =0D [1] https://bugzilla.redhat.com/1990656=0D =0D Signed-off-by: Nir Soffer =0D Message-Id: <20210813205519.50518-1-nsoffer@redhat.com>=0D Reviewed-by: Eric Blake =0D CC: qemu-stable@nongnu.org=0D Signed-off-by: Eric Blake =0D (cherry picked from commit 09615257058a0ae87b837bb041f56f7312d9ead8)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: f22c225e2359429508d65f581b9bdf457a0ac069=0D https://github.com/qemu/qemu/commit/f22c225e2359429508d65f581b9bdf4= 57a0ac069=0D Author: Markus Armbruster =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M monitor/hmp-cmds.c=0D =0D Log Message:=0D -----------=0D hmp: Unbreak "change vnc"=0D =0D HMP command "change vnc" can take the password as argument, or prompt=0D for it:=0D =0D (qemu) change vnc password 123=0D (qemu) change vnc password=0D Password: ***=0D (qemu)=0D =0D This regressed in commit cfb5387a1d "hmp: remove "change vnc TARGET"=0D command", v6.0.0.=0D =0D (qemu) change vnc passwd 123=0D Password: ***=0D (qemu) change vnc passwd=0D (qemu)=0D =0D The latter passes NULL to qmp_change_vnc_password(), which is a no-no.=0D= Looks like it puts the display into "password required, but none set"=0D state.=0D =0D The logic error is easy to miss in review, but testing should've=0D caught it.=0D =0D Fix the obvious way.=0D =0D Fixes: cfb5387a1de2acda23fb5c97d2378b9e7ddf8025=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Daniel P. Berrang=C3=A9 =0D Reviewed-by: Gerd Hoffmann =0D Message-Id: <20210909081219.308065-2-armbru@redhat.com>=0D Signed-off-by: Laurent Vivier =0D (cherry picked from commit 6193344f9337f8b76cd44ce94a32c9900d907d35)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 5a964fe8d93efd9c42c72a6244bd23039380eb59=0D https://github.com/qemu/qemu/commit/5a964fe8d93efd9c42c72a6244bd230= 39380eb59=0D Author: David Hildenbrand =0D Date: 2021-10-15 (Fri, 15 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-mem-pci.c=0D =0D Log Message:=0D -----------=0D virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE= event=0D =0D Apparently, we don't have to duplicate the string.=0D =0D Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem si= ze changes")=0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: David Hildenbrand =0D Reviewed-by: Markus Armbruster =0D Message-Id: <20210929162445.64060-2-david@redhat.com>=0D Signed-off-by: Paolo Bonzini =0D (cherry picked from commit 75b98cb9f6456ccf194211beffcbf93b0a995fa4)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 36403e8788a264dc96174f52584681ebcb4f54b1=0D https://github.com/qemu/qemu/commit/36403e8788a264dc96174f52584681e= bcb4f54b1=0D Author: Gerd Hoffmann =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/usb/dev-uas.c=0D =0D Log Message:=0D -----------=0D uas: add stream number sanity checks.=0D =0D The device uses the guest-supplied stream number unchecked, which can=0D lead to guest-triggered out-of-band access to the UASDevice->data3 and=0D= UASDevice->status3 fields. Add the missing checks.=0D =0D Fixes: CVE-2021-3713=0D Signed-off-by: Gerd Hoffmann =0D Reported-by: Chen Zhe =0D Reported-by: Tan Jingguo =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210818120505.1258262-2-kraxel@redhat.com>=0D (cherry picked from commit 13b250b12ad3c59114a6a17d59caf073ce45b33a)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 606f618b3c1d517edaf145cd8648a9b5ae3fc941=0D https://github.com/qemu/qemu/commit/606f618b3c1d517edaf145cd8648a9b= 5ae3fc941=0D Author: Gerd Hoffmann =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/usb/redirect.c=0D =0D Log Message:=0D -----------=0D usb/redir: avoid dynamic stack allocation (CVE-2021-3527)=0D =0D Use autofree heap allocation instead.=0D =0D Fixes: 4f4321c11ff ("usb: use iovecs in USBPacket")=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Gerd Hoffmann =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20210503132915.2335822-3-kraxel@redhat.com>=0D (cherry picked from commit 7ec54f9eb62b5d177e30eb8b1cad795a5f8d8986)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: e204dca909ed2fe5aa18f03c973e3ad6cff98595=0D https://github.com/qemu/qemu/commit/e204dca909ed2fe5aa18f03c973e3ad= 6cff98595=0D Author: Gerd Hoffmann =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/usb/combined-packet.c=0D =0D Log Message:=0D -----------=0D usb: limit combined packets to 1 MiB (CVE-2021-3527)=0D =0D usb-host and usb-redirect try to batch bulk transfers by combining many=0D= small usb packets into a single, large transfer request, to reduce the=0D= overhead and improve performance.=0D =0D This patch adds a size limit of 1 MiB for those combined packets to=0D restrict the host resources the guest can bind that way.=0D =0D Signed-off-by: Gerd Hoffmann =0D Message-Id: <20210503132915.2335822-6-kraxel@redhat.com>=0D (cherry picked from commit 05a40b172e4d691371534828078be47e7fff524c)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 168299eb7ddcee4b337d4e635ef98784ca9a5804=0D https://github.com/qemu/qemu/commit/168299eb7ddcee4b337d4e635ef9878= 4ca9a5804=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/virgl.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix memory disclosure in virgl_cmd_get_capset_info (CVE= -2021-3545)=0D =0D Otherwise some of the 'resp' will be leaked to guest.=0D =0D Fixes: CVE-2021-3545=0D Reported-by: Li Qiang =0D virtio-gpu fix: 42a8dadc74 ("virtio-gpu: fix information leak=0D in getting capset info dispatch")=0D =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-2-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit 121841b25d72d13f8cad554363138c360f1250ea)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: c5300b8a94105dee1c44ac49d2bb3b35412b5ae6=0D https://github.com/qemu/qemu/commit/c5300b8a94105dee1c44ac49d2bb3b3= 5412b5ae6=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/vhost-user-gpu.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix resource leak in 'vg_resource_create_2d' (CVE-2021-= 3544)=0D =0D Call 'vugbm_buffer_destroy' in error path to avoid resource leak.=0D =0D Fixes: CVE-2021-3544=0D Reported-by: Li Qiang =0D Reviewed-by: Prasad J Pandit =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-3-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit 86dd8fac2acc366930a5dc08d3fb1b1e816f4e1e)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 6ae68dfd10e53466e341f8330e0c8f9f10bd5d54=0D https://github.com/qemu/qemu/commit/6ae68dfd10e53466e341f8330e0c8f9= f10bd5d54=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/vhost-user-gpu.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix memory leak in vg_resource_attach_backing (CVE-2021= -3544)=0D =0D Check whether the 'res' has already been attach_backing to avoid=0D memory leak.=0D =0D Fixes: CVE-2021-3544=0D Reported-by: Li Qiang =0D virtio-gpu fix: 204f01b309 ("virtio-gpu: fix memory leak=0D in resource attach backing")=0D =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-4-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit b9f79858a614d95f5de875d0ca31096eaab72c3b)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 457053998df9ab77fa82360bbe3115263063e17a=0D https://github.com/qemu/qemu/commit/457053998df9ab77fa82360bbe31152= 63063e17a=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/vhost-user-gpu.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix memory leak while calling 'vg_resource_unref' (CVE-= 2021-3544)=0D =0D If the guest trigger following sequences, the attach_backing will be leak= ed:=0D =0D vg_resource_create_2d=0D vg_resource_attach_backing=0D vg_resource_unref=0D =0D This patch fix this by freeing 'res->iov' in vg_resource_destroy.=0D =0D Fixes: CVE-2021-3544=0D Reported-by: Li Qiang =0D virtio-gpu fix: 5e8e3c4c75 ("virtio-gpu: fix resource leak=0D in virgl_cmd_resource_unref")=0D =0D Reviewed-by: Prasad J Pandit =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-5-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit b7afebcf9e6ecf3cf9b5a9b9b731ed04bca6aa3e)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 4dda63d7edea4374dd3f5ec9982c255a6ec54d37=0D https://github.com/qemu/qemu/commit/4dda63d7edea4374dd3f5ec9982c255= a6ec54d37=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/virgl.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix memory leak in 'virgl_cmd_resource_unref' (CVE-2021= -3544)=0D =0D The 'res->iov' will be leaked if the guest trigger following sequences:=0D= =0D virgl_cmd_create_resource_2d=0D virgl_resource_attach_backing=0D virgl_cmd_resource_unref=0D =0D This patch fixes this.=0D =0D Fixes: CVE-2021-3544=0D Reported-by: Li Qiang =0D virtio-gpu fix: 5e8e3c4c75 ("virtio-gpu: fix resource leak=0D in virgl_cmd_resource_unref"=0D =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-6-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit f6091d86ba9ea05f4e111b9b42ee0005c37a6779)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 07daff4a9a5f9dd6e79e3aa4a9664aee3156bd7d=0D https://github.com/qemu/qemu/commit/07daff4a9a5f9dd6e79e3aa4a9664ae= e3156bd7d=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/virgl.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix memory leak in 'virgl_resource_attach_backing' (CVE= -2021-3544)=0D =0D If 'virgl_renderer_resource_attach_iov' failed, the 'res_iovs' will=0D be leaked.=0D =0D Fixes: CVE-2021-3544=0D Reported-by: Li Qiang =0D virtio-gpu fix: 33243031da ("virtio-gpu-3d: fix memory leak=0D in resource attach backing")=0D =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-7-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit 63736af5a6571d9def93769431e0d7e38c6677bf)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 4787501893f8b18e84f4d72ccbea4854ad9f5c9b=0D https://github.com/qemu/qemu/commit/4787501893f8b18e84f4d72ccbea485= 4ad9f5c9b=0D Author: Li Qiang =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M contrib/vhost-user-gpu/virgl.c=0D =0D Log Message:=0D -----------=0D vhost-user-gpu: fix OOB write in 'virgl_cmd_get_capset' (CVE-2021-3546)= =0D =0D If 'virgl_cmd_get_capset' set 'max_size' to 0,=0D the 'virgl_renderer_fill_caps' will write the data after the 'resp'.=0D This patch avoid this by checking the returned 'max_size'.=0D =0D virtio-gpu fix: abd7f08b23 ("display: virtio-gpu-3d: check=0D virgl capabilities max_size")=0D =0D Fixes: CVE-2021-3546=0D Reported-by: Li Qiang =0D Reviewed-by: Prasad J Pandit =0D Signed-off-by: Li Qiang =0D Reviewed-by: Marc-Andr=C3=A9 Lureau =0D Message-Id: <20210516030403.107723-8-liq3ea@163.com>=0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit 9f22893adcb02580aee5968f32baa2cd109b3ec2)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: d25db58213557663140afb57bf3416b93a93a3e6=0D https://github.com/qemu/qemu/commit/d25db58213557663140afb57bf3416b= 93a93a3e6=0D Author: Marcel Apfelbaum =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/rdma/vmw/pvrdma_cmd.c=0D =0D Log Message:=0D -----------=0D hw/rdma: Fix possible mremap overflow in the pvrdma device (CVE-2021-35= 82)=0D =0D Ensure mremap boundaries not trusting the guest kernel to=0D pass the correct buffer length.=0D =0D Fixes: CVE-2021-3582=0D Reported-by: VictorV (Kunlun Lab) =0D Tested-by: VictorV (Kunlun Lab) =0D Signed-off-by: Marcel Apfelbaum =0D Message-Id: <20210616110600.20889-1-marcel.apfelbaum@gmail.com>=0D Reviewed-by: Yuval Shaia =0D Tested-by: Yuval Shaia =0D Reviewed-by: Prasad J Pandit =0D Signed-off-by: Marcel Apfelbaum =0D (cherry picked from commit 284f191b4abad213aed04cb0458e1600fd18d7c4)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 46d3c9e9f5b067a784f24a40134ed9a97e145094=0D https://github.com/qemu/qemu/commit/46d3c9e9f5b067a784f24a40134ed9a= 97e145094=0D Author: Marcel Apfelbaum =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/rdma/vmw/pvrdma_main.c=0D =0D Log Message:=0D -----------=0D pvrdma: Ensure correct input on ring init (CVE-2021-3607)=0D =0D Check the guest passed a non zero page count=0D for pvrdma device ring buffers.=0D =0D Fixes: CVE-2021-3607=0D Reported-by: VictorV (Kunlun Lab) =0D Reviewed-by: VictorV (Kunlun Lab) =0D Signed-off-by: Marcel Apfelbaum =0D Message-Id: <20210630114634.2168872-1-marcel@redhat.com>=0D Reviewed-by: Yuval Shaia =0D Tested-by: Yuval Shaia =0D Signed-off-by: Marcel Apfelbaum =0D (cherry picked from commit 32e5703cfea07c91e6e84bcb0313f633bb146534)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 27c6f20d9d8725ddd4d0744022c4a66ec4878c6d=0D https://github.com/qemu/qemu/commit/27c6f20d9d8725ddd4d0744022c4a66= ec4878c6d=0D Author: Marcel Apfelbaum =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M hw/rdma/vmw/pvrdma_dev_ring.c=0D =0D Log Message:=0D -----------=0D pvrdma: Fix the ring init error flow (CVE-2021-3608)=0D =0D Do not unmap uninitialized dma addresses.=0D =0D Fixes: CVE-2021-3608=0D Reviewed-by: VictorV (Kunlun Lab) =0D Tested-by: VictorV (Kunlun Lab) =0D Signed-off-by: Marcel Apfelbaum =0D Message-Id: <20210630115246.2178219-1-marcel@redhat.com>=0D Tested-by: Yuval Shaia =0D Reviewed-by: Yuval Shaia =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Marcel Apfelbaum =0D (cherry picked from commit 66ae37d8cc313f89272e711174a846a229bcdbd3)=0D Signed-off-by: Michael Roth =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/1513997aa2aa%5E...27c6f20d9= d87=0D From MAILER-DAEMON Mon Oct 18 12:19:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcVLz-0002WT-H6 for mharc-qemu-commits@gnu.org; Mon, 18 Oct 2021 12:19:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcVLy-0002Sf-DI for qemu-commits@nongnu.org; Mon, 18 Oct 2021 12:19:10 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:45303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcVLv-0004Dc-Gc for qemu-commits@nongnu.org; Mon, 18 Oct 2021 12:19:09 -0400 Received: from github.com (hubbernetes-node-bfb71a0.ac4-iad.github.net [10.52.207.26]) by smtp.github.com (Postfix) with ESMTPA id 7D668600CEB for ; Mon, 18 Oct 2021 09:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634573946; bh=9NPwYgF9r6qdl+iDHOfJQnwEPJlLYR7ip9tOiWPjHSQ=; h=Date:From:To:Subject:From; b=bti0nZSr+/+ozThYbqrPP77nDcrzMtCpQEgOj1wMGd1dMoAA4ULl4fgPp9YUGR1pg tuvxKzSJ2HwcmMgUYhXAxwPgWeF9mHKKuwWkKM9DYSWN1Oz/MhWCiEPFBTTb641pQf FQEOqDQatj5I+fQ1p5KlyPIRH65hGdmxFjtrg9fY= Date: Mon, 18 Oct 2021 09:19:06 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 719f87: target/mips: Check nanoMIPS DSP MULT[U] accumulato... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 16:19:10 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 719f874b83792951faa3fe67378eca4034bec3dc=0D https://github.com/qemu/qemu/commit/719f874b83792951faa3fe67378eca4= 034bec3dc=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/nanomips_translate.c.inc=0D =0D Log Message:=0D -----------=0D target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6=0D =0D Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04,=0D MULT and MULTU opcodes:=0D =0D The value of ac selects an accumulator numbered from 0 to 3.=0D When ac=3D0, this refers to the original HI/LO register pair of the=0D MIPS32 architecture.=0D =0D In Release 6 of the MIPS Architecture, accumulators are eliminated=0D from MIPS32.=0D =0D Ensure pre-Release 6 is restricted to HI/LO registers pair.=0D =0D Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS -= part 4")=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: e07f3e265b90d078d69c1f305563f04f1371b7aa=0D https://github.com/qemu/qemu/commit/e07f3e265b90d078d69c1f305563f04= f1371b7aa=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Massage memory map information=0D =0D Use memmap array to uinfy address of memory map.=0D That would allow us reuse address information for FDT generation.=0D =0D Signed-off-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [PMD: Use local 'regaddr' in gen_firmware(), fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 10e3f30ff730624094a2fe6a81aaa72064853036=0D https://github.com/qemu/qemu/commit/10e3f30ff730624094a2fe6a81aaa72= 064853036=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Allow loading elf kernel and dtb=0D =0D ELF kernel allows us debugging much easier with DWARF symbols.=0D =0D Signed-off-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [PMD: Fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-3-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 723038999ef42fec4f845841d2d35a52f9ab1dbe=0D https://github.com/qemu/qemu/commit/723038999ef42fec4f845841d2d35a5= 2f9ab1dbe=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Add FDT generator=0D =0D Generate FDT on our own if no dtb argument supplied.=0D Avoid introducing unused device in FDT with user supplied dtb.=0D =0D Signed-off-by: Jiaxun Yang =0D [PMD: Fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-4-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 7da51cb391bc1100b941d04a0e9fec2cdc5b9632=0D https://github.com/qemu/qemu/commit/7da51cb391bc1100b941d04a0e9fec2= cdc5b9632=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Remove unused register from MSA 2R/2RF instruction format=0D= =0D Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")=0D= and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added=0D= the MSA 2R/2RF instructions. However these instructions don't use any=0D target vector register, so remove the unused TCG temporaries.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003175743.3738710-2-f4bug@amsat.org>=0D =0D =0D Commit: 2b537a3d856e2500acc321c9333f03b36a829f4e=0D https://github.com/qemu/qemu/commit/2b537a3d856e2500acc321c9333f03b= 36a829f4e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_elm_df()=0D =0D Data Format is a 2-bit constant value.=0D Avoid using a TCG temporary by moving it to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-3-f4bug@amsat.org>=0D =0D =0D Commit: e81a48b9e7fb3db72b7820b0342779227bf0510f=0D https://github.com/qemu/qemu/commit/e81a48b9e7fb3db72b7820b03427792= 27bf0510f=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_2rf()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-4-f4bug@amsat.org>=0D =0D =0D Commit: 74341af7d6c7093bba0893a7efd53d30aa50a200=0D https://github.com/qemu/qemu/commit/74341af7d6c7093bba0893a7efd53d3= 0aa50a200=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_2r()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-5-f4bug@amsat.org>=0D =0D =0D Commit: 1b5c0a11471cd0c3c2f206fd49e31972a2dc3bad=0D https://github.com/qemu/qemu/commit/1b5c0a11471cd0c3c2f206fd49e3197= 2a2dc3bad=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_3rf()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-6-f4bug@amsat.org>=0D =0D =0D Commit: 469a316dc42cd669ab502a385fdd3539fd45e36e=0D https://github.com/qemu/qemu/commit/469a316dc42cd669ab502a385fdd353= 9fd45e36e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use explicit extract32() calls in gen_msa_i5()=0D =0D We already use sextract32(), use extract32() for completeness=0D instead of open-coding it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-7-f4bug@amsat.org>=0D =0D =0D Commit: d2db0f729da6946873b1352bfb7c12c2c9f91fb0=0D https://github.com/qemu/qemu/commit/d2db0f729da6946873b1352bfb7c12c= 2c9f91fb0=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()=0D =0D The offset is constant and read-only: move it to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-9-f4bug@amsat.org>=0D =0D =0D Commit: 0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f=0D https://github.com/qemu/qemu/commit/0e235827de65b8a0a5fa403ad9ed15d= 04f8b1a4f=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Fix DEXTRV_S.H DSP opcode=0D =0D While for the DEXTR_S.H opcode:=0D =0D "The shift argument is provided in the instruction."=0D =0D For the DEXTRV_S.H opcode we have:=0D =0D "The five least-significant bits of register rs provide the=0D shift argument, interpreted as a five-bit unsigned integer;=0D the remaining bits in rs are ignored."=0D =0D While 't1' contains the 'rs' register content (the shift value=0D for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.=0D We can directly use the v1_t TCG register which already contains=0D this shift value.=0D =0D Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")=0D= Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>=0D =0D =0D Commit: cfddceba7f9f56a5564015962154dccd242f5c8b=0D https://github.com/qemu/qemu/commit/cfddceba7f9f56a5564015962154dcc= d242f5c8b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()=0D =0D Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4=0D ("target-mips: Add ASE DSP accumulator instructions"), the=0D 'v2_t' TCG temporary has never been used. Remove it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>=0D =0D =0D Commit: 7c8eae45c0c12c92055486184f779d57a7677948=0D https://github.com/qemu/qemu/commit/7c8eae45c0c12c92055486184f779d5= 7a7677948=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D =0D Log Message:=0D -----------=0D via-ide: Set user_creatable to false=0D =0D This model only works as a function of the via superio chip not as a=0D standalone PCI device.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015092159.3E863748F57@zero.eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3a2f166fe05ce4b00ca781d7abd08e6accd6e472=0D https://github.com/qemu/qemu/commit/3a2f166fe05ce4b00ca781d7abd08e6= accd6e472=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/isa/vt82c686.c=0D =0D Log Message:=0D -----------=0D vt82c686: Move common code to via_isa_realize=0D =0D The vt82c686b_realize and vt8231_realize methods are almost identical,=0D= factor out the common parts to a via_isa_realize function to avoid=0D code duplication.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <7cb7a16ff4daf8f48d576246255bea1fd355207c.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: a4d65b701ffce52b69b5b6c3f253519129af182e=0D https://github.com/qemu/qemu/commit/a4d65b701ffce52b69b5b6c3f253519= 129af182e=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/isa/vt82c686.c=0D M include/hw/isa/vt82c686.h=0D =0D Log Message:=0D -----------=0D vt82c686: Add a method to VIA_ISA to raise ISA interrupts=0D =0D Other functions in the VT82xx chips need to raise ISA interrupts. Keep=0D= a reference to them in the device state and add via_isa_set_irq() to=0D allow setting their state.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Jiaxun Yang =0D Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 2792cf20ca7eed0e354a0ed731422411faca4908=0D https://github.com/qemu/qemu/commit/2792cf20ca7eed0e354a0ed73142241= 1faca4908=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D =0D Log Message:=0D -----------=0D via-ide: Avoid using isa_get_irq()=0D =0D Use via_isa_set_irq() which better encapsulates irq handling in the=0D vt82xx model and avoids using isa_get_irq() that has a comment saying=0D it should not be used.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <26cb1848c9fc0360df7a57c2c9ba5e03c4a692b5.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 9c050b661d3a43dfe2fd44106e559b39706d1296=0D https://github.com/qemu/qemu/commit/9c050b661d3a43dfe2fd44106e559b3= 9706d1296=0D Author: Richard Henderson =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D M hw/isa/vt82c686.c=0D M hw/mips/boston.c=0D M include/hw/isa/vt82c686.h=0D M target/mips/tcg/msa_translate.c=0D M target/mips/tcg/nanomips_translate.c.inc=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into s= taging=0D =0D MIPS patches queue=0D =0D Hardware emulation:=0D - Generate FDT blob for Boston machine (Jiaxun)=0D - VIA chipset cleanups (Zoltan)=0D =0D TCG:=0D - Use tcg_constant() in Compact branch and MSA opcodes=0D - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6=0D - Fix DEXTRV_S.H DSP opcode=0D - Remove unused TCG temporary for some DSP opcodes=0D =0D # gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT=0D # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC= 0DE=0D # gpg: Good signature from "Philippe Mathieu-Daud=C3=A9 (F4BUG) " [full]=0D =0D * remotes/philmd/tags/mips-20211018:=0D via-ide: Avoid using isa_get_irq()=0D vt82c686: Add a method to VIA_ISA to raise ISA interrupts=0D vt82c686: Move common code to via_isa_realize=0D via-ide: Set user_creatable to false=0D target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()=0D target/mips: Fix DEXTRV_S.H DSP opcode=0D target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()=0D target/mips: Use explicit extract32() calls in gen_msa_i5()=0D target/mips: Use tcg_constant_i32() in gen_msa_3rf()=0D target/mips: Use tcg_constant_i32() in gen_msa_2r()=0D target/mips: Use tcg_constant_i32() in gen_msa_2rf()=0D target/mips: Use tcg_constant_i32() in gen_msa_elm_df()=0D target/mips: Remove unused register from MSA 2R/2RF instruction format=0D= hw/mips/boston: Add FDT generator=0D hw/mips/boston: Allow loading elf kernel and dtb=0D hw/mips/boston: Massage memory map information=0D target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c148a0572130...9c050b661d3a= =0D From MAILER-DAEMON Mon Oct 18 14:42:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcXaM-0002O7-DX for mharc-qemu-commits@gnu.org; Mon, 18 Oct 2021 14:42:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcXaK-0002Jl-1f for qemu-commits@nongnu.org; Mon, 18 Oct 2021 14:42:08 -0400 Received: from out-19.smtp.github.com ([192.30.252.202]:40527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcXaG-0002sa-9P for qemu-commits@nongnu.org; Mon, 18 Oct 2021 14:42:07 -0400 Received: from github.com (hubbernetes-node-355c978.va3-iad.github.net [10.48.200.57]) by smtp.github.com (Postfix) with ESMTPA id 6119AE04B1 for ; Mon, 18 Oct 2021 11:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634582523; bh=4+BgjEVdWGG/unVeAkXaP88hR6x+PgVKnU55LZJp3s8=; h=Date:From:To:Subject:From; b=r4b+Q7ygYJDMiR+vvblewsMK6tlB2+fgY6Bqf28lE6fCnFlYFrU6RR7Rp056w9E0b cUkh1HMIu+BnBZdDAvyuSZtEtQT0WQC1Vh+2yuJr1Q4MfAC5YuZQIBmuSN9x1TgHLX eIKhpUwe2H56ThjlMNnLy8WgBVrGviKKFvtszFvY= Date: Mon, 18 Oct 2021 11:42:03 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.202; envelope-from=noreply@github.com; helo=out-19.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 719f87: target/mips: Check nanoMIPS DSP MULT[U] accumulato... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 18:42:08 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 719f874b83792951faa3fe67378eca4034bec3dc=0D https://github.com/qemu/qemu/commit/719f874b83792951faa3fe67378eca4= 034bec3dc=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/nanomips_translate.c.inc=0D =0D Log Message:=0D -----------=0D target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6=0D =0D Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04,=0D MULT and MULTU opcodes:=0D =0D The value of ac selects an accumulator numbered from 0 to 3.=0D When ac=3D0, this refers to the original HI/LO register pair of the=0D MIPS32 architecture.=0D =0D In Release 6 of the MIPS Architecture, accumulators are eliminated=0D from MIPS32.=0D =0D Ensure pre-Release 6 is restricted to HI/LO registers pair.=0D =0D Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS -= part 4")=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: e07f3e265b90d078d69c1f305563f04f1371b7aa=0D https://github.com/qemu/qemu/commit/e07f3e265b90d078d69c1f305563f04= f1371b7aa=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Massage memory map information=0D =0D Use memmap array to uinfy address of memory map.=0D That would allow us reuse address information for FDT generation.=0D =0D Signed-off-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [PMD: Use local 'regaddr' in gen_firmware(), fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 10e3f30ff730624094a2fe6a81aaa72064853036=0D https://github.com/qemu/qemu/commit/10e3f30ff730624094a2fe6a81aaa72= 064853036=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Allow loading elf kernel and dtb=0D =0D ELF kernel allows us debugging much easier with DWARF symbols.=0D =0D Signed-off-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [PMD: Fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-3-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 723038999ef42fec4f845841d2d35a52f9ab1dbe=0D https://github.com/qemu/qemu/commit/723038999ef42fec4f845841d2d35a5= 2f9ab1dbe=0D Author: Jiaxun Yang =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/mips/boston.c=0D =0D Log Message:=0D -----------=0D hw/mips/boston: Add FDT generator=0D =0D Generate FDT on our own if no dtb argument supplied.=0D Avoid introducing unused device in FDT with user supplied dtb.=0D =0D Signed-off-by: Jiaxun Yang =0D [PMD: Fix coding style]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211002184539.169-4-jiaxun.yang@flygoat.com>=0D =0D =0D Commit: 7da51cb391bc1100b941d04a0e9fec2cdc5b9632=0D https://github.com/qemu/qemu/commit/7da51cb391bc1100b941d04a0e9fec2= cdc5b9632=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Remove unused register from MSA 2R/2RF instruction format=0D= =0D Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")=0D= and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added=0D= the MSA 2R/2RF instructions. However these instructions don't use any=0D target vector register, so remove the unused TCG temporaries.=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003175743.3738710-2-f4bug@amsat.org>=0D =0D =0D Commit: 2b537a3d856e2500acc321c9333f03b36a829f4e=0D https://github.com/qemu/qemu/commit/2b537a3d856e2500acc321c9333f03b= 36a829f4e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_elm_df()=0D =0D Data Format is a 2-bit constant value.=0D Avoid using a TCG temporary by moving it to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-3-f4bug@amsat.org>=0D =0D =0D Commit: e81a48b9e7fb3db72b7820b0342779227bf0510f=0D https://github.com/qemu/qemu/commit/e81a48b9e7fb3db72b7820b03427792= 27bf0510f=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_2rf()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-4-f4bug@amsat.org>=0D =0D =0D Commit: 74341af7d6c7093bba0893a7efd53d30aa50a200=0D https://github.com/qemu/qemu/commit/74341af7d6c7093bba0893a7efd53d3= 0aa50a200=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_2r()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-5-f4bug@amsat.org>=0D =0D =0D Commit: 1b5c0a11471cd0c3c2f206fd49e31972a2dc3bad=0D https://github.com/qemu/qemu/commit/1b5c0a11471cd0c3c2f206fd49e3197= 2a2dc3bad=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_i32() in gen_msa_3rf()=0D =0D Avoid using a TCG temporary by moving Data Format to the constant pool.=0D= =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-6-f4bug@amsat.org>=0D =0D =0D Commit: 469a316dc42cd669ab502a385fdd3539fd45e36e=0D https://github.com/qemu/qemu/commit/469a316dc42cd669ab502a385fdd353= 9fd45e36e=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/msa_translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use explicit extract32() calls in gen_msa_i5()=0D =0D We already use sextract32(), use extract32() for completeness=0D instead of open-coding it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-7-f4bug@amsat.org>=0D =0D =0D Commit: d2db0f729da6946873b1352bfb7c12c2c9f91fb0=0D https://github.com/qemu/qemu/commit/d2db0f729da6946873b1352bfb7c12c= 2c9f91fb0=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()=0D =0D The offset is constant and read-only: move it to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211003175743.3738710-9-f4bug@amsat.org>=0D =0D =0D Commit: 0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f=0D https://github.com/qemu/qemu/commit/0e235827de65b8a0a5fa403ad9ed15d= 04f8b1a4f=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Fix DEXTRV_S.H DSP opcode=0D =0D While for the DEXTR_S.H opcode:=0D =0D "The shift argument is provided in the instruction."=0D =0D For the DEXTRV_S.H opcode we have:=0D =0D "The five least-significant bits of register rs provide the=0D shift argument, interpreted as a five-bit unsigned integer;=0D the remaining bits in rs are ignored."=0D =0D While 't1' contains the 'rs' register content (the shift value=0D for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.=0D We can directly use the v1_t TCG register which already contains=0D this shift value.=0D =0D Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")=0D= Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>=0D =0D =0D Commit: cfddceba7f9f56a5564015962154dccd242f5c8b=0D https://github.com/qemu/qemu/commit/cfddceba7f9f56a5564015962154dcc= d242f5c8b=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()=0D =0D Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4=0D ("target-mips: Add ASE DSP accumulator instructions"), the=0D 'v2_t' TCG temporary has never been used. Remove it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>=0D =0D =0D Commit: 7c8eae45c0c12c92055486184f779d57a7677948=0D https://github.com/qemu/qemu/commit/7c8eae45c0c12c92055486184f779d5= 7a7677948=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D =0D Log Message:=0D -----------=0D via-ide: Set user_creatable to false=0D =0D This model only works as a function of the via superio chip not as a=0D standalone PCI device.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015092159.3E863748F57@zero.eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3a2f166fe05ce4b00ca781d7abd08e6accd6e472=0D https://github.com/qemu/qemu/commit/3a2f166fe05ce4b00ca781d7abd08e6= accd6e472=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/isa/vt82c686.c=0D =0D Log Message:=0D -----------=0D vt82c686: Move common code to via_isa_realize=0D =0D The vt82c686b_realize and vt8231_realize methods are almost identical,=0D= factor out the common parts to a via_isa_realize function to avoid=0D code duplication.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Jiaxun Yang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <7cb7a16ff4daf8f48d576246255bea1fd355207c.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: a4d65b701ffce52b69b5b6c3f253519129af182e=0D https://github.com/qemu/qemu/commit/a4d65b701ffce52b69b5b6c3f253519= 129af182e=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/isa/vt82c686.c=0D M include/hw/isa/vt82c686.h=0D =0D Log Message:=0D -----------=0D vt82c686: Add a method to VIA_ISA to raise ISA interrupts=0D =0D Other functions in the VT82xx chips need to raise ISA interrupts. Keep=0D= a reference to them in the device state and add via_isa_set_irq() to=0D allow setting their state.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Jiaxun Yang =0D Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 2792cf20ca7eed0e354a0ed731422411faca4908=0D https://github.com/qemu/qemu/commit/2792cf20ca7eed0e354a0ed73142241= 1faca4908=0D Author: BALATON Zoltan =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D =0D Log Message:=0D -----------=0D via-ide: Avoid using isa_get_irq()=0D =0D Use via_isa_set_irq() which better encapsulates irq handling in the=0D vt82xx model and avoids using isa_get_irq() that has a comment saying=0D it should not be used.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <26cb1848c9fc0360df7a57c2c9ba5e03c4a692b5.1634259980.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 9c050b661d3a43dfe2fd44106e559b39706d1296=0D https://github.com/qemu/qemu/commit/9c050b661d3a43dfe2fd44106e559b3= 9706d1296=0D Author: Richard Henderson =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/ide/via.c=0D M hw/isa/vt82c686.c=0D M hw/mips/boston.c=0D M include/hw/isa/vt82c686.h=0D M target/mips/tcg/msa_translate.c=0D M target/mips/tcg/nanomips_translate.c.inc=0D M target/mips/tcg/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into s= taging=0D =0D MIPS patches queue=0D =0D Hardware emulation:=0D - Generate FDT blob for Boston machine (Jiaxun)=0D - VIA chipset cleanups (Zoltan)=0D =0D TCG:=0D - Use tcg_constant() in Compact branch and MSA opcodes=0D - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6=0D - Fix DEXTRV_S.H DSP opcode=0D - Remove unused TCG temporary for some DSP opcodes=0D =0D # gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT=0D # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC= 0DE=0D # gpg: Good signature from "Philippe Mathieu-Daud=C3=A9 (F4BUG) " [full]=0D =0D * remotes/philmd/tags/mips-20211018:=0D via-ide: Avoid using isa_get_irq()=0D vt82c686: Add a method to VIA_ISA to raise ISA interrupts=0D vt82c686: Move common code to via_isa_realize=0D via-ide: Set user_creatable to false=0D target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()=0D target/mips: Fix DEXTRV_S.H DSP opcode=0D target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()=0D target/mips: Use explicit extract32() calls in gen_msa_i5()=0D target/mips: Use tcg_constant_i32() in gen_msa_3rf()=0D target/mips: Use tcg_constant_i32() in gen_msa_2r()=0D target/mips: Use tcg_constant_i32() in gen_msa_2rf()=0D target/mips: Use tcg_constant_i32() in gen_msa_elm_df()=0D target/mips: Remove unused register from MSA 2R/2RF instruction format=0D= hw/mips/boston: Add FDT generator=0D hw/mips/boston: Allow loading elf kernel and dtb=0D hw/mips/boston: Massage memory map information=0D target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c148a0572130...9c050b661d3a= =0D From MAILER-DAEMON Mon Oct 18 15:18:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcY9c-0001RX-Ml for mharc-qemu-commits@gnu.org; Mon, 18 Oct 2021 15:18:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcY9Z-0001PK-7J for qemu-commits@nongnu.org; Mon, 18 Oct 2021 15:18:34 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:58679 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcY9W-0003CV-2X for qemu-commits@nongnu.org; Mon, 18 Oct 2021 15:18:32 -0400 Received: from github.com (hubbernetes-node-a019c39.ac4-iad.github.net [10.52.202.72]) by smtp.github.com (Postfix) with ESMTPA id 5E727560CBA for ; Mon, 18 Oct 2021 12:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634584708; bh=wQTuCbA/lUMAGeQmFSJu2NnLF3HrhWki2Iw9dyX4clY=; h=Date:From:To:Subject:From; b=uC4vjYISTpg4cKUJ2qBRteBM8yOH91n+pM2qpFCYBK96eF2E2zDi22Zc7sBcjLnOV DirvF0M+0x2Iad47wBLY65VuTG84H+GAW1+Vz1g/Xb7Hv/2QndvMGBmdta10bvT3s7 3vpcXF4PCYo1B9K/XJDVxe4AD3WszS27gP56yxsE= Date: Mon, 18 Oct 2021 12:18:28 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 948516: bsd-user/mmap.c: Always zero MAP_ANONYMOUS memory ... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 19:18:34 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 948516a3fac0bdd47eb127fe1a86148ed86d5c65=0D https://github.com/qemu/qemu/commit/948516a3fac0bdd47eb127fe1a86148= ed86d5c65=0D Author: Mika=C3=ABl Urankar =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Always zero MAP_ANONYMOUS memory in mmap_frag()=0D =0D Similar to the equivalent linux-user commit e6deac9cf99=0D =0D When mapping MAP_ANONYMOUS memory fragments, still need notice about to=0D= set it zero, or it will cause issues.=0D =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 26778ac3da794f29c2c7c7d473f0a8d77b874392=0D https://github.com/qemu/qemu/commit/26778ac3da794f29c2c7c7d473f0a8d= 77b874392=0D Author: Mika=C3=ABl Urankar =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: check pread's return value to fix warnings with _FORTI= FY_SOURCE=0D =0D Simmilar to the equivalent linux-user: commit fb7e378cf9c, which added=0D= checking to pread's return value. Update to current qemu standards with=0D= {} around the if statement.=0D =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 36d5d891559f6b9f0bae4907669de9bfdf5d4d94=0D https://github.com/qemu/qemu/commit/36d5d891559f6b9f0bae4907669de9b= fdf5d4d94=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: MAP_ symbols are defined, so no need for ifdefs=0D =0D All these MAP_ symbols are always defined on supported FreeBSD versions=0D= (12.2 and newer), so remove the #ifdefs since they aren't needed.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 14837a3f7540f38ba78261238da3914a6529d882=0D https://github.com/qemu/qemu/commit/14837a3f7540f38ba78261238da3914= a6529d882=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: mmap return ENOMEM on overflow=0D =0D mmap should return ENOMEM on len overflow rather than EINVAL. Return=0D EINVAL when len =3D=3D 0 and ENOMEM when the rounded to a page length is = 0.=0D Found by make check-tcg.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 953b69cc06fe3ae5fa1c157f17f054fa95620f38=0D https://github.com/qemu/qemu/commit/953b69cc06fe3ae5fa1c157f17f054f= a95620f38=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: mmap prefer MAP_ANON for BSD=0D =0D MAP_ANON and MAP_ANONYMOUS are identical. Prefer MAP_ANON for BSD since=0D= the file is now a confusing mix of the two.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 45b8765e8f3001436c09cebcd9b8b281e6c55804=0D https://github.com/qemu/qemu/commit/45b8765e8f3001436c09cebcd9b8b28= 1e6c55804=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Convert to qemu_log logging for mmap debugging=0D =0D Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: a6b2d060667422d54e077c0a8e4c55bd083ef489=0D https://github.com/qemu/qemu/commit/a6b2d060667422d54e077c0a8e4c55b= d083ef489=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Don't mmap fd =3D=3D -1 independently from MAP_ANON fl= ag=0D =0D Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd !=3D -1.=0D= MAP_STACK and MAP_GUARD both require fd =3D=3D -1 and don't require mappi= ng=0D the fd either. Add analysis from Guy Yur detailing the different cases=0D= for MAP_GUARD and MAP_STACK.=0D =0D Signed-off-by: Guy Yur =0D [ partially merged before, finishing the job and documenting origin]=0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 0fc76b685989d30a32316b17a9c43ba017e114a1=0D https://github.com/qemu/qemu/commit/0fc76b685989d30a32316b17a9c43ba= 017e114a1=0D Author: Kyle Evans =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Implement MAP_EXCL, required by jemalloc in head=0D =0D jemalloc requires a working MAP_EXCL. Ensure that no page is double=0D mapped when specified. In addition, use guest_range_valid_untagged to=0D test for valid ranges of pages rather than an incomplete inlined version=0D= of the test that might be wrong.=0D =0D Signed-off-by: Kyle Evans =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D =0D =0D Commit: 91a5adda1583fa8a3166bc16d79c67f3c87e958b=0D https://github.com/qemu/qemu/commit/91a5adda1583fa8a3166bc16d79c67f= 3c87e958b=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: assert that target_mprotect cannot fail=0D =0D Similar to the equivalent linux-user change 86abac06c14. All error=0D conditions that target_mprotect checks are also checked by target_mmap.=0D= EACCESS cannot happen because we are just removing PROT_WRITE. ENOMEM=0D= should not happen because we are modifying a whole VMA (and we have=0D bigger problems anyway if it happens).=0D =0D Fixes a Coverity false positive, where Coverity complains about=0D target_mprotect's return value being passed to tb_invalidate_phys_range.=0D= =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: dda2da6c94484b85d28fe7c29f7fee562deaf177=0D https://github.com/qemu/qemu/commit/dda2da6c94484b85d28fe7c29f7fee5= 62deaf177=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/meson.build=0D M linux-user/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: *-user: only descend into *-user when configured=0D =0D To increase flexibility, only descend into *-user when that is=0D configured. This allows *-user to selectively include directories based=0D= on the host OS which may not exist on all hosts. Adopt Paolo's=0D suggestion of checking the configuration in the directories that know=0D about the configuration.=0D =0D Message-Id: <20210926220103.1721355-2-f4bug@amsat.org>=0D Message-Id: <20210926220103.1721355-3-f4bug@amsat.org>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Warner Losh =0D Acked-by: Paolo Bonzini =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 1fecb605f83f4a5db315cd183b6f4e30fc72518d=0D https://github.com/qemu/qemu/commit/1fecb605f83f4a5db315cd183b6f4e3= 0fc72518d=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_user.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os-user.h: Remove support for FreeBSD older than 12.0=0D= =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: b03c0bb27aa513869fbdbff941b92e5aa3604bd0=0D https://github.com/qemu/qemu/commit/b03c0bb27aa513869fbdbff941b92e5= aa3604bd0=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/strace.list=0D =0D Log Message:=0D -----------=0D bsd-user/strace.list: Remove support for FreeBSD versions older than 12= .0=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: fbbacc99821781f4d0faa0e714c4885d9570faf4=0D https://github.com/qemu/qemu/commit/fbbacc99821781f4d0faa0e714c4885= d9570faf4=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/i386/target_arch_cpu.h=0D M bsd-user/x86_64/target_arch_cpu.h=0D =0D Log Message:=0D -----------=0D bsd-user: TARGET_RESET define is unused, remove it=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: e5f674f01cdfbb7b98374a947aed84412f4c763f=0D https://github.com/qemu/qemu/commit/e5f674f01cdfbb7b98374a947aed844= 12f4c763f=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D M bsd-user/syscall.c=0D =0D Log Message:=0D -----------=0D bsd-user: export get_errno and is_error from syscall.c=0D =0D Make get_errno and is_error global so files other than syscall.c can use=0D= them.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 7cb4d7c917c2718f9fd5a075c2e4b4fca3be482a=0D https://github.com/qemu/qemu/commit/7cb4d7c917c2718f9fd5a075c2e4b4f= ca3be482a=0D Author: Stacey Son =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/errno_defs.h=0D =0D Log Message:=0D -----------=0D bsd-user/errno_defs.h: Add internal error numbers=0D =0D To emulate signals and interrupted system calls, we need to have the=0D same mechanisms we have in the kernel, including these errno values.=0D =0D Signed-off-by: Stacey Son =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: f4a29b6ed29360cf556851c82875a2b782adb5ed=0D https://github.com/qemu/qemu/commit/f4a29b6ed29360cf556851c82875a2b= 782adb5ed=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_signal.h=0D M bsd-user/i386/target_arch_signal.h=0D M bsd-user/x86_64/target_arch_signal.h=0D =0D Log Message:=0D -----------=0D bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h=0D =0D Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's=0D architecture agnostic on FreeBSD.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 11170cbdcc64e4207850eb886baeb6db436aaf46=0D https://github.com/qemu/qemu/commit/11170cbdcc64e4207850eb886baeb6d= b436aaf46=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_elf.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder=0D =0D All architectures have a ELF_HWCAP, so remove the fallback ifdef.=0D Place ELF_HWCAP in the same order as on native FreeBSD.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: f6f0706cc2081ebaf786603aaaf204ae5a39dda7=0D https://github.com/qemu/qemu/commit/f6f0706cc2081ebaf786603aaaf204a= e5a39dda7=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_elf.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os_elf: If ELF_HWCAP2 is defined, publish it=0D =0D Some architectures publish AT_HWCAP2 as well as AT_HWCAP. Those=0D architectures will define ELF_HWCAP2 in their target_arch_elf.h files=0D for the value for this process. If it is defined, then publish it.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 7aac7392346d1f5bb9fc31cb7e4f3f1f3fc2be05=0D https://github.com/qemu/qemu/commit/7aac7392346d1f5bb9fc31cb7e4f3f1= f3fc2be05=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/main.c=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Remove used from TaskState=0D =0D The 'used' field in TaskState is write only. Remove it from TaskState.=0D= =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 653ccec26dd3f9942ac258c43be0edb93e16dfba=0D https://github.com/qemu/qemu/commit/653ccec26dd3f9942ac258c43be0edb= 93e16dfba=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/main.c=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Add stop_all_tasks=0D =0D Similar to the same function in linux-user: this stops all the current ta= sks.=0D =0D Signed-off-by: Stacey Son =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: da07e6944fb0f1fe162246cbf31271f31ec9a5c0=0D https://github.com/qemu/qemu/commit/da07e6944fb0f1fe162246cbf31271f= 31ec9a5c0=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D A bsd-user/freebsd/meson.build=0D A bsd-user/freebsd/os-sys.c=0D M bsd-user/meson.build=0D M bsd-user/qemu.h=0D M bsd-user/syscall.c=0D =0D Log Message:=0D -----------=0D bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface=0D =0D do_freebsd_arch_sysarch() exists in $ARCH/target_arch_sysarch.h for x86.=0D= Call it from do_freebsd_sysarch() and remove the mostly duplicate=0D version in syscall.c. Future changes will move it to os-sys.c and=0D support other architectures.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 11c7b43faa1d19c94524984c878479d14a7194f6=0D https://github.com/qemu/qemu/commit/11c7b43faa1d19c94524984c878479d= 14a7194f6=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Rename sigqueue to qemu_sigqueue=0D =0D To avoid a name clash with FreeBSD's sigqueue data structure in=0D signalvar.h, rename sigqueue to qemu_sigqueue. This structure=0D is currently defined, but unused.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 5abfac277d25feb5f12332422c03ea1cb21c6aa1=0D https://github.com/qemu/qemu/commit/5abfac277d25feb5f12332422c03ea1= cb21c6aa1=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D M bsd-user/signal.c=0D =0D Log Message:=0D -----------=0D bsd-user/signal: Create a dummy signal queueing function=0D =0D Create dummy signal queueing function so we can start to integrate other=0D= architectures (at the cost of signals remaining broken) to tame the=0D dependency graph a bit and to bring in signals in a more controlled=0D fashion. Log unimplemented events to it in the mean time.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 362534a643b4a34bcb223996538ce9de5cdab946=0D https://github.com/qemu/qemu/commit/362534a643b4a34bcb223996538ce9d= e5cdab946=0D Author: Richard Henderson =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/errno_defs.h=0D A bsd-user/freebsd/meson.build=0D A bsd-user/freebsd/os-sys.c=0D M bsd-user/freebsd/strace.list=0D M bsd-user/freebsd/target_os_elf.h=0D M bsd-user/freebsd/target_os_signal.h=0D M bsd-user/freebsd/target_os_user.h=0D M bsd-user/i386/target_arch_cpu.h=0D M bsd-user/i386/target_arch_signal.h=0D M bsd-user/main.c=0D M bsd-user/meson.build=0D M bsd-user/mmap.c=0D M bsd-user/qemu.h=0D M bsd-user/signal.c=0D M bsd-user/syscall.c=0D M bsd-user/x86_64/target_arch_cpu.h=0D M bsd-user/x86_64/target_arch_signal.h=0D M linux-user/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-2021101= 8-pull-request' into staging=0D =0D bsd-user pull request: merge dependencies for next architectures=0D =0D Merge the dependencies for arm, aarch64, and riscv64 architectures. This = joins=0D together two patch series:=0D =0D [PATCH v2 00/15] bsd-user: misc cleanup for aarch64 import=0D =0D Prepare for aarch64 support (the next architecture to be upstreamed). As = the=0D aarch64 emulation is more complete, it relies on a number of different it= ems.=0D In some cases, I've pulled in the full support from bsd-user fork. In oth= er=0D cases I've created a simple stub (as is the case for signals, which have=0D= independent changes pending, so I wanted to be as minimal as possible. S= ince=0D all pre-12.2 support was purged from the bsd-user fork, go ahead and remo= ve it=0D here. FreeBSD 11.x goes ouft of support at the end of the month. Remove w= hat=0D little multi-version support that's in upstream.=0D =0D and=0D =0D [PATCH v3 0/9] bsd-user mmap fixes=0D This series synchronizes mmap.c with the bsd-user fork. This is a mix of = old bug=0D fixes pulled in from linux-user, as well as some newer fixes to adress bu= gs=0D found in check-tcg and recent FreeBSD developments. There are also a coup= le of=0D style commits. Updated to migrate debugging to qemu_log.=0D =0D as well as a couple of minor rebase tweaks. In addition, the next two=0D architectures I plan on upstreaming (arm and riscv64) also have their pre= reqs=0D satisfied with this request.=0D =0D v2: Remove accidental module regression in patch 7 and try again.=0D =0D # gpg: Signature made Mon 18 Oct 2021 12:00:28 PM PDT=0D # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01= 100=0D # gpg: Good signature from "Warner Losh " [unknown]=0D= # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: WARNING: This key is not certified with a trusted signature!=0D # gpg: There is no indication that the signature belongs to the = owner.=0D # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 = 1100=0D =0D * remotes/bsdimp/tags/pull-bsd-user-20211018-pull-request: (23 commits)=0D= bsd-user/signal: Create a dummy signal queueing function=0D bsd-user: Rename sigqueue to qemu_sigqueue=0D bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface=0D bsd-user: Add stop_all_tasks=0D bsd-user: Remove used from TaskState=0D bsd-user/target_os_elf: If ELF_HWCAP2 is defined, publish it=0D bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder=0D bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h=0D bsd-user/errno_defs.h: Add internal error numbers=0D bsd-user: export get_errno and is_error from syscall.c=0D bsd-user: TARGET_RESET define is unused, remove it=0D bsd-user/strace.list: Remove support for FreeBSD versions older than 12= .0=0D bsd-user/target_os-user.h: Remove support for FreeBSD older than 12.0=0D= meson: *-user: only descend into *-user when configured=0D bsd-user/mmap.c: assert that target_mprotect cannot fail=0D bsd-user/mmap.c: Implement MAP_EXCL, required by jemalloc in head=0D bsd-user/mmap.c: Don't mmap fd =3D=3D -1 independently from MAP_ANON fl= ag=0D bsd-user/mmap.c: Convert to qemu_log logging for mmap debugging=0D bsd-user/mmap.c: mmap prefer MAP_ANON for BSD=0D bsd-user/mmap.c: mmap return ENOMEM on overflow=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/9c050b661d3a...362534a643b4= =0D From MAILER-DAEMON Mon Oct 18 17:06:31 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcZq3-0003jN-Hf for mharc-qemu-commits@gnu.org; Mon, 18 Oct 2021 17:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcZq2-0003fQ-3Y for qemu-commits@nongnu.org; Mon, 18 Oct 2021 17:06:30 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:38431) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcZpy-0008C2-Qj for qemu-commits@nongnu.org; Mon, 18 Oct 2021 17:06:29 -0400 Received: from github.com (hubbernetes-node-9ba6275.ac4-iad.github.net [10.52.125.45]) by smtp.github.com (Postfix) with ESMTPA id 3315B6004D8 for ; Mon, 18 Oct 2021 14:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634591186; bh=ZxrSnIGotiQAGoDFArZB/POYLDcaKK9eEuU+UwVn1HI=; h=Date:From:To:Subject:From; b=1hxedZEmm4VnjEtxHCMNFvoKi5gyEJyTgUgcWw5P252ESIIsWTBlYiGgXkQkH/OPG qEZGHBmAYwvtBJkKX5+g/pGFmDkZTlAyomqakOHqtDgKktsOBVHwBF7EXUdiyD4wUP 2nIxNTT66mrHjpag/0YoRgyhAwGNpXwDzrkq6im0= Date: Mon, 18 Oct 2021 14:06:26 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 948516: bsd-user/mmap.c: Always zero MAP_ANONYMOUS memory ... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 21:06:30 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 948516a3fac0bdd47eb127fe1a86148ed86d5c65=0D https://github.com/qemu/qemu/commit/948516a3fac0bdd47eb127fe1a86148= ed86d5c65=0D Author: Mika=C3=ABl Urankar =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Always zero MAP_ANONYMOUS memory in mmap_frag()=0D =0D Similar to the equivalent linux-user commit e6deac9cf99=0D =0D When mapping MAP_ANONYMOUS memory fragments, still need notice about to=0D= set it zero, or it will cause issues.=0D =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 26778ac3da794f29c2c7c7d473f0a8d77b874392=0D https://github.com/qemu/qemu/commit/26778ac3da794f29c2c7c7d473f0a8d= 77b874392=0D Author: Mika=C3=ABl Urankar =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: check pread's return value to fix warnings with _FORTI= FY_SOURCE=0D =0D Simmilar to the equivalent linux-user: commit fb7e378cf9c, which added=0D= checking to pread's return value. Update to current qemu standards with=0D= {} around the if statement.=0D =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 36d5d891559f6b9f0bae4907669de9bfdf5d4d94=0D https://github.com/qemu/qemu/commit/36d5d891559f6b9f0bae4907669de9b= fdf5d4d94=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: MAP_ symbols are defined, so no need for ifdefs=0D =0D All these MAP_ symbols are always defined on supported FreeBSD versions=0D= (12.2 and newer), so remove the #ifdefs since they aren't needed.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 14837a3f7540f38ba78261238da3914a6529d882=0D https://github.com/qemu/qemu/commit/14837a3f7540f38ba78261238da3914= a6529d882=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: mmap return ENOMEM on overflow=0D =0D mmap should return ENOMEM on len overflow rather than EINVAL. Return=0D EINVAL when len =3D=3D 0 and ENOMEM when the rounded to a page length is = 0.=0D Found by make check-tcg.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 953b69cc06fe3ae5fa1c157f17f054fa95620f38=0D https://github.com/qemu/qemu/commit/953b69cc06fe3ae5fa1c157f17f054f= a95620f38=0D Author: Warner Losh =0D Date: 2021-10-17 (Sun, 17 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: mmap prefer MAP_ANON for BSD=0D =0D MAP_ANON and MAP_ANONYMOUS are identical. Prefer MAP_ANON for BSD since=0D= the file is now a confusing mix of the two.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 45b8765e8f3001436c09cebcd9b8b281e6c55804=0D https://github.com/qemu/qemu/commit/45b8765e8f3001436c09cebcd9b8b28= 1e6c55804=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Convert to qemu_log logging for mmap debugging=0D =0D Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: a6b2d060667422d54e077c0a8e4c55bd083ef489=0D https://github.com/qemu/qemu/commit/a6b2d060667422d54e077c0a8e4c55b= d083ef489=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Don't mmap fd =3D=3D -1 independently from MAP_ANON fl= ag=0D =0D Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd !=3D -1.=0D= MAP_STACK and MAP_GUARD both require fd =3D=3D -1 and don't require mappi= ng=0D the fd either. Add analysis from Guy Yur detailing the different cases=0D= for MAP_GUARD and MAP_STACK.=0D =0D Signed-off-by: Guy Yur =0D [ partially merged before, finishing the job and documenting origin]=0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 0fc76b685989d30a32316b17a9c43ba017e114a1=0D https://github.com/qemu/qemu/commit/0fc76b685989d30a32316b17a9c43ba= 017e114a1=0D Author: Kyle Evans =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: Implement MAP_EXCL, required by jemalloc in head=0D =0D jemalloc requires a working MAP_EXCL. Ensure that no page is double=0D mapped when specified. In addition, use guest_range_valid_untagged to=0D test for valid ranges of pages rather than an incomplete inlined version=0D= of the test that might be wrong.=0D =0D Signed-off-by: Kyle Evans =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D =0D =0D Commit: 91a5adda1583fa8a3166bc16d79c67f3c87e958b=0D https://github.com/qemu/qemu/commit/91a5adda1583fa8a3166bc16d79c67f= 3c87e958b=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/mmap.c=0D =0D Log Message:=0D -----------=0D bsd-user/mmap.c: assert that target_mprotect cannot fail=0D =0D Similar to the equivalent linux-user change 86abac06c14. All error=0D conditions that target_mprotect checks are also checked by target_mmap.=0D= EACCESS cannot happen because we are just removing PROT_WRITE. ENOMEM=0D= should not happen because we are modifying a whole VMA (and we have=0D bigger problems anyway if it happens).=0D =0D Fixes a Coverity false positive, where Coverity complains about=0D target_mprotect's return value being passed to tb_invalidate_phys_range.=0D= =0D Signed-off-by: Mika=C3=ABl Urankar =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: dda2da6c94484b85d28fe7c29f7fee562deaf177=0D https://github.com/qemu/qemu/commit/dda2da6c94484b85d28fe7c29f7fee5= 62deaf177=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/meson.build=0D M linux-user/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D meson: *-user: only descend into *-user when configured=0D =0D To increase flexibility, only descend into *-user when that is=0D configured. This allows *-user to selectively include directories based=0D= on the host OS which may not exist on all hosts. Adopt Paolo's=0D suggestion of checking the configuration in the directories that know=0D about the configuration.=0D =0D Message-Id: <20210926220103.1721355-2-f4bug@amsat.org>=0D Message-Id: <20210926220103.1721355-3-f4bug@amsat.org>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Warner Losh =0D Acked-by: Paolo Bonzini =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 1fecb605f83f4a5db315cd183b6f4e30fc72518d=0D https://github.com/qemu/qemu/commit/1fecb605f83f4a5db315cd183b6f4e3= 0fc72518d=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_user.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os-user.h: Remove support for FreeBSD older than 12.0=0D= =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: b03c0bb27aa513869fbdbff941b92e5aa3604bd0=0D https://github.com/qemu/qemu/commit/b03c0bb27aa513869fbdbff941b92e5= aa3604bd0=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/strace.list=0D =0D Log Message:=0D -----------=0D bsd-user/strace.list: Remove support for FreeBSD versions older than 12= .0=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: fbbacc99821781f4d0faa0e714c4885d9570faf4=0D https://github.com/qemu/qemu/commit/fbbacc99821781f4d0faa0e714c4885= d9570faf4=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/i386/target_arch_cpu.h=0D M bsd-user/x86_64/target_arch_cpu.h=0D =0D Log Message:=0D -----------=0D bsd-user: TARGET_RESET define is unused, remove it=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: e5f674f01cdfbb7b98374a947aed84412f4c763f=0D https://github.com/qemu/qemu/commit/e5f674f01cdfbb7b98374a947aed844= 12f4c763f=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D M bsd-user/syscall.c=0D =0D Log Message:=0D -----------=0D bsd-user: export get_errno and is_error from syscall.c=0D =0D Make get_errno and is_error global so files other than syscall.c can use=0D= them.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 7cb4d7c917c2718f9fd5a075c2e4b4fca3be482a=0D https://github.com/qemu/qemu/commit/7cb4d7c917c2718f9fd5a075c2e4b4f= ca3be482a=0D Author: Stacey Son =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/errno_defs.h=0D =0D Log Message:=0D -----------=0D bsd-user/errno_defs.h: Add internal error numbers=0D =0D To emulate signals and interrupted system calls, we need to have the=0D same mechanisms we have in the kernel, including these errno values.=0D =0D Signed-off-by: Stacey Son =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: f4a29b6ed29360cf556851c82875a2b782adb5ed=0D https://github.com/qemu/qemu/commit/f4a29b6ed29360cf556851c82875a2b= 782adb5ed=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_signal.h=0D M bsd-user/i386/target_arch_signal.h=0D M bsd-user/x86_64/target_arch_signal.h=0D =0D Log Message:=0D -----------=0D bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h=0D =0D Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's=0D architecture agnostic on FreeBSD.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 11170cbdcc64e4207850eb886baeb6db436aaf46=0D https://github.com/qemu/qemu/commit/11170cbdcc64e4207850eb886baeb6d= b436aaf46=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_elf.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder=0D =0D All architectures have a ELF_HWCAP, so remove the fallback ifdef.=0D Place ELF_HWCAP in the same order as on native FreeBSD.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: f6f0706cc2081ebaf786603aaaf204ae5a39dda7=0D https://github.com/qemu/qemu/commit/f6f0706cc2081ebaf786603aaaf204a= e5a39dda7=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/freebsd/target_os_elf.h=0D =0D Log Message:=0D -----------=0D bsd-user/target_os_elf: If ELF_HWCAP2 is defined, publish it=0D =0D Some architectures publish AT_HWCAP2 as well as AT_HWCAP. Those=0D architectures will define ELF_HWCAP2 in their target_arch_elf.h files=0D for the value for this process. If it is defined, then publish it.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 7aac7392346d1f5bb9fc31cb7e4f3f1f3fc2be05=0D https://github.com/qemu/qemu/commit/7aac7392346d1f5bb9fc31cb7e4f3f1= f3fc2be05=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/main.c=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Remove used from TaskState=0D =0D The 'used' field in TaskState is write only. Remove it from TaskState.=0D= =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 653ccec26dd3f9942ac258c43be0edb93e16dfba=0D https://github.com/qemu/qemu/commit/653ccec26dd3f9942ac258c43be0edb= 93e16dfba=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/main.c=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Add stop_all_tasks=0D =0D Similar to the same function in linux-user: this stops all the current ta= sks.=0D =0D Signed-off-by: Stacey Son =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: da07e6944fb0f1fe162246cbf31271f31ec9a5c0=0D https://github.com/qemu/qemu/commit/da07e6944fb0f1fe162246cbf31271f= 31ec9a5c0=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D A bsd-user/freebsd/meson.build=0D A bsd-user/freebsd/os-sys.c=0D M bsd-user/meson.build=0D M bsd-user/qemu.h=0D M bsd-user/syscall.c=0D =0D Log Message:=0D -----------=0D bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface=0D =0D do_freebsd_arch_sysarch() exists in $ARCH/target_arch_sysarch.h for x86.=0D= Call it from do_freebsd_sysarch() and remove the mostly duplicate=0D version in syscall.c. Future changes will move it to os-sys.c and=0D support other architectures.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 11c7b43faa1d19c94524984c878479d14a7194f6=0D https://github.com/qemu/qemu/commit/11c7b43faa1d19c94524984c878479d= 14a7194f6=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D =0D Log Message:=0D -----------=0D bsd-user: Rename sigqueue to qemu_sigqueue=0D =0D To avoid a name clash with FreeBSD's sigqueue data structure in=0D signalvar.h, rename sigqueue to qemu_sigqueue. This structure=0D is currently defined, but unused.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 5abfac277d25feb5f12332422c03ea1cb21c6aa1=0D https://github.com/qemu/qemu/commit/5abfac277d25feb5f12332422c03ea1= cb21c6aa1=0D Author: Warner Losh =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/qemu.h=0D M bsd-user/signal.c=0D =0D Log Message:=0D -----------=0D bsd-user/signal: Create a dummy signal queueing function=0D =0D Create dummy signal queueing function so we can start to integrate other=0D= architectures (at the cost of signals remaining broken) to tame the=0D dependency graph a bit and to bring in signals in a more controlled=0D fashion. Log unimplemented events to it in the mean time.=0D =0D Signed-off-by: Warner Losh =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Kyle Evans =0D =0D =0D Commit: 362534a643b4a34bcb223996538ce9de5cdab946=0D https://github.com/qemu/qemu/commit/362534a643b4a34bcb223996538ce9d= e5cdab946=0D Author: Richard Henderson =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M bsd-user/errno_defs.h=0D A bsd-user/freebsd/meson.build=0D A bsd-user/freebsd/os-sys.c=0D M bsd-user/freebsd/strace.list=0D M bsd-user/freebsd/target_os_elf.h=0D M bsd-user/freebsd/target_os_signal.h=0D M bsd-user/freebsd/target_os_user.h=0D M bsd-user/i386/target_arch_cpu.h=0D M bsd-user/i386/target_arch_signal.h=0D M bsd-user/main.c=0D M bsd-user/meson.build=0D M bsd-user/mmap.c=0D M bsd-user/qemu.h=0D M bsd-user/signal.c=0D M bsd-user/syscall.c=0D M bsd-user/x86_64/target_arch_cpu.h=0D M bsd-user/x86_64/target_arch_signal.h=0D M linux-user/meson.build=0D M meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-2021101= 8-pull-request' into staging=0D =0D bsd-user pull request: merge dependencies for next architectures=0D =0D Merge the dependencies for arm, aarch64, and riscv64 architectures. This = joins=0D together two patch series:=0D =0D [PATCH v2 00/15] bsd-user: misc cleanup for aarch64 import=0D =0D Prepare for aarch64 support (the next architecture to be upstreamed). As = the=0D aarch64 emulation is more complete, it relies on a number of different it= ems.=0D In some cases, I've pulled in the full support from bsd-user fork. In oth= er=0D cases I've created a simple stub (as is the case for signals, which have=0D= independent changes pending, so I wanted to be as minimal as possible. S= ince=0D all pre-12.2 support was purged from the bsd-user fork, go ahead and remo= ve it=0D here. FreeBSD 11.x goes ouft of support at the end of the month. Remove w= hat=0D little multi-version support that's in upstream.=0D =0D and=0D =0D [PATCH v3 0/9] bsd-user mmap fixes=0D This series synchronizes mmap.c with the bsd-user fork. This is a mix of = old bug=0D fixes pulled in from linux-user, as well as some newer fixes to adress bu= gs=0D found in check-tcg and recent FreeBSD developments. There are also a coup= le of=0D style commits. Updated to migrate debugging to qemu_log.=0D =0D as well as a couple of minor rebase tweaks. In addition, the next two=0D architectures I plan on upstreaming (arm and riscv64) also have their pre= reqs=0D satisfied with this request.=0D =0D v2: Remove accidental module regression in patch 7 and try again.=0D =0D # gpg: Signature made Mon 18 Oct 2021 12:00:28 PM PDT=0D # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01= 100=0D # gpg: Good signature from "Warner Losh " [unknown]=0D= # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: aka "Warner Losh " [unknown]=0D # gpg: WARNING: This key is not certified with a trusted signature!=0D # gpg: There is no indication that the signature belongs to the = owner.=0D # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 = 1100=0D =0D * remotes/bsdimp/tags/pull-bsd-user-20211018-pull-request: (23 commits)=0D= bsd-user/signal: Create a dummy signal queueing function=0D bsd-user: Rename sigqueue to qemu_sigqueue=0D bsd-user/sysarch: Move to using do_freebsd_arch_sysarch interface=0D bsd-user: Add stop_all_tasks=0D bsd-user: Remove used from TaskState=0D bsd-user/target_os_elf: If ELF_HWCAP2 is defined, publish it=0D bsd-user/target_os_elf.h: Remove fallback ELF_HWCAP and reorder=0D bsd-user: move TARGET_MC_GET_CLEAR_RET to target_os_signal.h=0D bsd-user/errno_defs.h: Add internal error numbers=0D bsd-user: export get_errno and is_error from syscall.c=0D bsd-user: TARGET_RESET define is unused, remove it=0D bsd-user/strace.list: Remove support for FreeBSD versions older than 12= .0=0D bsd-user/target_os-user.h: Remove support for FreeBSD older than 12.0=0D= meson: *-user: only descend into *-user when configured=0D bsd-user/mmap.c: assert that target_mprotect cannot fail=0D bsd-user/mmap.c: Implement MAP_EXCL, required by jemalloc in head=0D bsd-user/mmap.c: Don't mmap fd =3D=3D -1 independently from MAP_ANON fl= ag=0D bsd-user/mmap.c: Convert to qemu_log logging for mmap debugging=0D bsd-user/mmap.c: mmap prefer MAP_ANON for BSD=0D bsd-user/mmap.c: mmap return ENOMEM on overflow=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/9c050b661d3a...362534a643b4= =0D From MAILER-DAEMON Tue Oct 19 10:42:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcqJW-0000aM-0V for mharc-qemu-commits@gnu.org; Tue, 19 Oct 2021 10:42:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqJT-0000TI-KQ for qemu-commits@nongnu.org; Tue, 19 Oct 2021 10:41:59 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:37177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcqJN-0007go-Gu for qemu-commits@nongnu.org; Tue, 19 Oct 2021 10:41:59 -0400 Received: from github.com (hubbernetes-node-0229691.ac4-iad.github.net [10.52.200.19]) by smtp.github.com (Postfix) with ESMTPA id 61AF960005C for ; Tue, 19 Oct 2021 07:41:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634654512; bh=aKVl4/AJlG3opr9OhYovr131HCMLDr3yBmktKI67/bs=; h=Date:From:To:Subject:From; b=c59/W3+hFG4E4DeYD36U5CAbwS3P3OjVieSxphHyXPiv7cQCJCLBmctEmpUKq0frG YDKJuP1LoFSKBsiVOBOhWNnwi/2W5hM+aAjNhoOBwxOlF9YtJCcMmJwNgYo/Ej1yv6 SAZA3aL1dAEYVe2UlM7LsuyOrg8yNLK6bguZQkdQ= Date: Tue, 19 Oct 2021 07:41:52 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 20171e: multifd: Implement yank for multifd send side X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Oct 2021 14:41:59 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 20171ea8950c619f00dc5cfa6136fd489998ffc5=0D https://github.com/qemu/qemu/commit/20171ea8950c619f00dc5cfa6136fd4= 89998ffc5=0D Author: Lukas Straub =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/multifd.c=0D M migration/multifd.h=0D =0D Log Message:=0D -----------=0D multifd: Implement yank for multifd send side=0D =0D To: qemu-devel =0D Cc: "Dr. David Alan Gilbert" , Juan Quintela=0D , Peter Xu , Leonardo Bras Soare= s=0D Passos =0D Date: Wed, 1 Sep 2021 17:58:57 +0200 (1 week, 15 hours, 17 minutes ago)=0D= =0D [[PGP Signed Part:No public key for 35AB0B289C5DB258 created at 2021-09-0= 1T17:58:57+0200 using RSA]]=0D When introducing yank functionality in the migration code I forgot=0D to cover the multifd send side.=0D =0D Signed-off-by: Lukas Straub =0D Tested-by: Leonardo Bras =0D Reviewed-by: Leonardo Bras =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: e9ab82b858c14aa76dac5235a99d1723ec069407=0D https://github.com/qemu/qemu/commit/e9ab82b858c14aa76dac5235a99d172= 3ec069407=0D Author: Lukas Straub =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/multifd.c=0D =0D Log Message:=0D -----------=0D multifd: Unconditionally unregister yank function=0D =0D To: qemu-devel =0D Cc: "Dr. David Alan Gilbert" , Juan Quintela=0D , Peter Xu , Leonardo Bras Soare= s=0D Passos =0D Date: Wed, 4 Aug 2021 21:26:32 +0200 (5 weeks, 11 hours, 52 minutes ago)=0D= =0D [[PGP Signed Part:No public key for 35AB0B289C5DB258 created at 2021-08-0= 4T21:26:32+0200 using RSA]]=0D Unconditionally unregister yank function in multifd_load_cleanup().=0D If it is not unregistered here, it will leak and cause a crash=0D in yank_unregister_instance(). Now if the ioc is still in use=0D afterwards, it will only lead to qemu not being able to recover=0D from a hang related to that ioc.=0D =0D After checking the code, i am pretty sure that ref is always 1=0D when arriving here. So all this currently does is remove the=0D unneeded check.=0D =0D Signed-off-by: Lukas Straub =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 1230a25f6fa3048c56d0f7f4e70e451330f4d33c=0D https://github.com/qemu/qemu/commit/1230a25f6fa3048c56d0f7f4e70e451= 330f4d33c=0D Author: David Hildenbrand =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/ram.c=0D =0D Log Message:=0D -----------=0D migration/ram: Don't passs RAMState to migration_clear_memory_region_di= rty_bitmap_*()=0D =0D The parameter is unused, let's drop it.=0D =0D Reviewed-by: Peter Xu =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Juan Quintela =0D Signed-off-by: David Hildenbrand =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: b7acd65707623a8b728b622f4c9dd96c2085c05b=0D https://github.com/qemu/qemu/commit/b7acd65707623a8b728b622f4c9dd96= c2085c05b=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D M migration/multifd.c=0D M migration/multifd.h=0D =0D Log Message:=0D -----------=0D migration: allow multifd for socket protocol only=0D =0D To: , , = =0D CC: Li Zhijian =0D Date: Sat, 31 Jul 2021 22:05:51 +0800 (5 weeks, 4 days, 17 hours ago)=0D =0D multifd with unsupported protocol will cause a segment fault.=0D (gdb) bt=0D #0 0x0000563b4a93faf8 in socket_connect (addr=3D0x0, errp=3D0x7f7f02675= 410) at ../util/qemu-sockets.c:1190=0D #1 0x0000563b4a797a03 in qio_channel_socket_connect_sync=0D (ioc=3D0x563b4d16e8c0, addr=3D0x0, errp=3D0x7f7f02675410) at=0D ../io/channel-socket.c:145=0D #2 0x0000563b4a797abf in qio_channel_socket_connect_worker (task=3D0x56= 3b4cd86c30, opaque=3D0x0) at ../io/channel-socket.c:168=0D #3 0x0000563b4a792631 in qio_task_thread_worker (opaque=3D0x563b4cd86c3= 0) at ../io/task.c:124=0D #4 0x0000563b4a91da69 in qemu_thread_start (args=3D0x563b4c44bb80) at .= ./util/qemu-thread-posix.c:541=0D #5 0x00007f7fe9b5b3f9 in ?? ()=0D #6 0x0000000000000000 in ?? ()=0D =0D It's enough to check migrate_multifd_is_allowed() in multifd cleanup() an= d=0D multifd setup() though there are so many other places using migrate_use_m= ultifd().=0D =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 5ad15e8614b0877225af42aa28a7195ed2fb74e4=0D https://github.com/qemu/qemu/commit/5ad15e8614b0877225af42aa28a7195= ed2fb74e4=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D M migration/multifd.c=0D =0D Log Message:=0D -----------=0D migration: allow enabling mutilfd for specific protocol only=0D =0D To: , , = =0D CC: Li Zhijian =0D Date: Sat, 31 Jul 2021 22:05:52 +0800 (5 weeks, 4 days, 17 hours ago)=0D =0D And change the default to true so that in '-incoming defer' case, user is= able=0D to change multifd capability.=0D =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: e2daccb0d0375717efed80b772e9fd1e4c51ae5b=0D https://github.com/qemu/qemu/commit/e2daccb0d0375717efed80b772e9fd1= e4c51ae5b=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D migration/rdma: Try to register On-Demand Paging memory region=0D =0D Previously, for the fsdax mem-backend-file, it will register failed with=0D= Operation not supported. In this case, we can try to register it with=0D On-Demand Paging[1] like what rpma_mr_reg() does on rpma[2].=0D =0D [1]: https://community.mellanox.com/s/article/understanding-on-demand-pag= ing--odp-x=0D [2]: http://pmem.io/rpma/manpages/v0.9.0/rpma_mr_reg.3=0D =0D CC: Marcel Apfelbaum =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Marcel Apfelbaum =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 911965ace9386e35ca022a65bb45a32fd421af3e=0D https://github.com/qemu/qemu/commit/911965ace9386e35ca022a65bb45a32= fd421af3e=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D migration/rdma: advise prefetch write for ODP region=0D =0D The responder mr registering with ODP will sent RNR NAK back to=0D the requester in the face of the page fault.=0D ---------=0D ibv_poll_cq wc.status=3D13 RNR retry counter exceeded!=0D ibv_poll_cq wrid=3DWRITE RDMA!=0D ---------=0D ibv_advise_mr(3) helps to make pages present before the actual IO is=0D conducted so that the responder does page fault as little as possible.=0D= =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Marcel Apfelbaum =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 50352cce138ef3b30c1cda28a4df68fff5da3202=0D https://github.com/qemu/qemu/commit/50352cce138ef3b30c1cda28a4df68f= ff5da3202=0D Author: Richard Henderson =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M migration/migration.c=0D M migration/multifd.c=0D M migration/multifd.h=0D M migration/ram.c=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/juanquintela/tags/migration.next-= pull-request' into staging=0D =0D Migration Pull request (3rd try)=0D =0D Hi=0D =0D This should fix all the freebsd problems.=0D =0D Please apply,=0D =0D # gpg: Signature made Tue 19 Oct 2021 02:28:51 AM PDT=0D # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D= 723=0D # gpg: Good signature from "Juan Quintela " [full]=0D= # gpg: aka "Juan Quintela " [full]=0D= =0D * remotes/juanquintela/tags/migration.next-pull-request:=0D migration/rdma: advise prefetch write for ODP region=0D migration/rdma: Try to register On-Demand Paging memory region=0D migration: allow enabling mutilfd for specific protocol only=0D migration: allow multifd for socket protocol only=0D migration/ram: Don't passs RAMState to migration_clear_memory_region_di= rty_bitmap_*()=0D multifd: Unconditionally unregister yank function=0D multifd: Implement yank for multifd send side=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/362534a643b4...50352cce138e= =0D From MAILER-DAEMON Tue Oct 19 12:55:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcsOM-000270-G2 for mharc-qemu-commits@gnu.org; Tue, 19 Oct 2021 12:55:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcsOK-0001zw-Ik for qemu-commits@nongnu.org; Tue, 19 Oct 2021 12:55:08 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:35371 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcsOG-0008Ss-TE for qemu-commits@nongnu.org; Tue, 19 Oct 2021 12:55:08 -0400 Received: from github.com (hubbernetes-node-7cce387.ac4-iad.github.net [10.52.125.63]) by smtp.github.com (Postfix) with ESMTPA id 27A62560388 for ; Tue, 19 Oct 2021 09:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634662504; bh=nTAxL2QBjo3hOVfUPp/frESMxO0h2nPWEZf6cFyrPSI=; h=Date:From:To:Subject:From; b=NiiDvYGA7Bw9+Fp5RLkI7X3FnhDItwTgWUv+rWZo+uRMEitOlddlC1/S3QtWoQO9G SDUPp07IlBOSdIu4QBUJGOdzb0NtZzib+1+8aiDvFMLNPycQAmkobyc842dVCEFa1F kjISspJvXo/UqozRdv1RgIzlm5Qy/NK5XWkjhHyM= Date: Tue, 19 Oct 2021 09:55:04 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 20171e: multifd: Implement yank for multifd send side X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Oct 2021 16:55:09 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 20171ea8950c619f00dc5cfa6136fd489998ffc5=0D https://github.com/qemu/qemu/commit/20171ea8950c619f00dc5cfa6136fd4= 89998ffc5=0D Author: Lukas Straub =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/multifd.c=0D M migration/multifd.h=0D =0D Log Message:=0D -----------=0D multifd: Implement yank for multifd send side=0D =0D To: qemu-devel =0D Cc: "Dr. David Alan Gilbert" , Juan Quintela=0D , Peter Xu , Leonardo Bras Soare= s=0D Passos =0D Date: Wed, 1 Sep 2021 17:58:57 +0200 (1 week, 15 hours, 17 minutes ago)=0D= =0D [[PGP Signed Part:No public key for 35AB0B289C5DB258 created at 2021-09-0= 1T17:58:57+0200 using RSA]]=0D When introducing yank functionality in the migration code I forgot=0D to cover the multifd send side.=0D =0D Signed-off-by: Lukas Straub =0D Tested-by: Leonardo Bras =0D Reviewed-by: Leonardo Bras =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: e9ab82b858c14aa76dac5235a99d1723ec069407=0D https://github.com/qemu/qemu/commit/e9ab82b858c14aa76dac5235a99d172= 3ec069407=0D Author: Lukas Straub =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/multifd.c=0D =0D Log Message:=0D -----------=0D multifd: Unconditionally unregister yank function=0D =0D To: qemu-devel =0D Cc: "Dr. David Alan Gilbert" , Juan Quintela=0D , Peter Xu , Leonardo Bras Soare= s=0D Passos =0D Date: Wed, 4 Aug 2021 21:26:32 +0200 (5 weeks, 11 hours, 52 minutes ago)=0D= =0D [[PGP Signed Part:No public key for 35AB0B289C5DB258 created at 2021-08-0= 4T21:26:32+0200 using RSA]]=0D Unconditionally unregister yank function in multifd_load_cleanup().=0D If it is not unregistered here, it will leak and cause a crash=0D in yank_unregister_instance(). Now if the ioc is still in use=0D afterwards, it will only lead to qemu not being able to recover=0D from a hang related to that ioc.=0D =0D After checking the code, i am pretty sure that ref is always 1=0D when arriving here. So all this currently does is remove the=0D unneeded check.=0D =0D Signed-off-by: Lukas Straub =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 1230a25f6fa3048c56d0f7f4e70e451330f4d33c=0D https://github.com/qemu/qemu/commit/1230a25f6fa3048c56d0f7f4e70e451= 330f4d33c=0D Author: David Hildenbrand =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/ram.c=0D =0D Log Message:=0D -----------=0D migration/ram: Don't passs RAMState to migration_clear_memory_region_di= rty_bitmap_*()=0D =0D The parameter is unused, let's drop it.=0D =0D Reviewed-by: Peter Xu =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Juan Quintela =0D Signed-off-by: David Hildenbrand =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: b7acd65707623a8b728b622f4c9dd96c2085c05b=0D https://github.com/qemu/qemu/commit/b7acd65707623a8b728b622f4c9dd96= c2085c05b=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D M migration/multifd.c=0D M migration/multifd.h=0D =0D Log Message:=0D -----------=0D migration: allow multifd for socket protocol only=0D =0D To: , , = =0D CC: Li Zhijian =0D Date: Sat, 31 Jul 2021 22:05:51 +0800 (5 weeks, 4 days, 17 hours ago)=0D =0D multifd with unsupported protocol will cause a segment fault.=0D (gdb) bt=0D #0 0x0000563b4a93faf8 in socket_connect (addr=3D0x0, errp=3D0x7f7f02675= 410) at ../util/qemu-sockets.c:1190=0D #1 0x0000563b4a797a03 in qio_channel_socket_connect_sync=0D (ioc=3D0x563b4d16e8c0, addr=3D0x0, errp=3D0x7f7f02675410) at=0D ../io/channel-socket.c:145=0D #2 0x0000563b4a797abf in qio_channel_socket_connect_worker (task=3D0x56= 3b4cd86c30, opaque=3D0x0) at ../io/channel-socket.c:168=0D #3 0x0000563b4a792631 in qio_task_thread_worker (opaque=3D0x563b4cd86c3= 0) at ../io/task.c:124=0D #4 0x0000563b4a91da69 in qemu_thread_start (args=3D0x563b4c44bb80) at .= ./util/qemu-thread-posix.c:541=0D #5 0x00007f7fe9b5b3f9 in ?? ()=0D #6 0x0000000000000000 in ?? ()=0D =0D It's enough to check migrate_multifd_is_allowed() in multifd cleanup() an= d=0D multifd setup() though there are so many other places using migrate_use_m= ultifd().=0D =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 5ad15e8614b0877225af42aa28a7195ed2fb74e4=0D https://github.com/qemu/qemu/commit/5ad15e8614b0877225af42aa28a7195= ed2fb74e4=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/migration.c=0D M migration/multifd.c=0D =0D Log Message:=0D -----------=0D migration: allow enabling mutilfd for specific protocol only=0D =0D To: , , = =0D CC: Li Zhijian =0D Date: Sat, 31 Jul 2021 22:05:52 +0800 (5 weeks, 4 days, 17 hours ago)=0D =0D And change the default to true so that in '-incoming defer' case, user is= able=0D to change multifd capability.=0D =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: e2daccb0d0375717efed80b772e9fd1e4c51ae5b=0D https://github.com/qemu/qemu/commit/e2daccb0d0375717efed80b772e9fd1= e4c51ae5b=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D migration/rdma: Try to register On-Demand Paging memory region=0D =0D Previously, for the fsdax mem-backend-file, it will register failed with=0D= Operation not supported. In this case, we can try to register it with=0D On-Demand Paging[1] like what rpma_mr_reg() does on rpma[2].=0D =0D [1]: https://community.mellanox.com/s/article/understanding-on-demand-pag= ing--odp-x=0D [2]: http://pmem.io/rpma/manpages/v0.9.0/rpma_mr_reg.3=0D =0D CC: Marcel Apfelbaum =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Marcel Apfelbaum =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 911965ace9386e35ca022a65bb45a32fd421af3e=0D https://github.com/qemu/qemu/commit/911965ace9386e35ca022a65bb45a32= fd421af3e=0D Author: Li Zhijian =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D migration/rdma: advise prefetch write for ODP region=0D =0D The responder mr registering with ODP will sent RNR NAK back to=0D the requester in the face of the page fault.=0D ---------=0D ibv_poll_cq wc.status=3D13 RNR retry counter exceeded!=0D ibv_poll_cq wrid=3DWRITE RDMA!=0D ---------=0D ibv_advise_mr(3) helps to make pages present before the actual IO is=0D conducted so that the responder does page fault as little as possible.=0D= =0D Signed-off-by: Li Zhijian =0D Reviewed-by: Marcel Apfelbaum =0D Reviewed-by: Juan Quintela =0D Signed-off-by: Juan Quintela =0D =0D =0D Commit: 50352cce138ef3b30c1cda28a4df68fff5da3202=0D https://github.com/qemu/qemu/commit/50352cce138ef3b30c1cda28a4df68f= ff5da3202=0D Author: Richard Henderson =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M migration/migration.c=0D M migration/multifd.c=0D M migration/multifd.h=0D M migration/ram.c=0D M migration/rdma.c=0D M migration/trace-events=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/juanquintela/tags/migration.next-= pull-request' into staging=0D =0D Migration Pull request (3rd try)=0D =0D Hi=0D =0D This should fix all the freebsd problems.=0D =0D Please apply,=0D =0D # gpg: Signature made Tue 19 Oct 2021 02:28:51 AM PDT=0D # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D= 723=0D # gpg: Good signature from "Juan Quintela " [full]=0D= # gpg: aka "Juan Quintela " [full]=0D= =0D * remotes/juanquintela/tags/migration.next-pull-request:=0D migration/rdma: advise prefetch write for ODP region=0D migration/rdma: Try to register On-Demand Paging memory region=0D migration: allow enabling mutilfd for specific protocol only=0D migration: allow multifd for socket protocol only=0D migration/ram: Don't passs RAMState to migration_clear_memory_region_di= rty_bitmap_*()=0D multifd: Unconditionally unregister yank function=0D multifd: Implement yank for multifd send side=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/362534a643b4...50352cce138e= =0D From MAILER-DAEMON Tue Oct 19 13:01:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcsUw-0002gB-HJ for mharc-qemu-commits@gnu.org; Tue, 19 Oct 2021 13:01:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcsUu-0002Zg-QF for qemu-commits@nongnu.org; Tue, 19 Oct 2021 13:01:56 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:55337 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcsUc-0007Mj-S1 for qemu-commits@nongnu.org; Tue, 19 Oct 2021 13:01:50 -0400 Received: from github.com (hubbernetes-node-b035797.va3-iad.github.net [10.48.205.98]) by smtp.github.com (Postfix) with ESMTPA id 2FA373407F4 for ; Tue, 19 Oct 2021 10:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634662895; bh=jdeD03TGk8MB09/MLZISkgL2TYQtyNn8wZiux4LcHes=; h=Date:From:To:Subject:From; b=rlODmf46nH4GVr4kzW/jvmTV3ON0hVzpibodPspZjXDtvY9SdIjoUjf1V7PCQY91U 0y0ooDh15LveE55VP3QxiD4B20QSVPWZwzkI8uQcK3I4RmFaB948UXuGx2hXNlzx0R P3yAZ/rigMn5c3iSa8/+MH18am2yPGq2q9VNwk5k= Date: Tue, 19 Oct 2021 10:01:35 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 07a12e: tests: acpi: dump table with failed checksum X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Oct 2021 17:01:57 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 07a12e71f2f03ace3ea44365f787c7e9b1dd836d=0D https://github.com/qemu/qemu/commit/07a12e71f2f03ace3ea44365f787c7e= 9b1dd836d=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/acpi-utils.c=0D =0D Log Message:=0D -----------=0D tests: acpi: dump table with failed checksum=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 147478071977a42e9d951aeab38435249754c8b7=0D https://github.com/qemu/qemu/commit/147478071977a42e9d951aeab384352= 49754c8b7=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D =0D Log Message:=0D -----------=0D tests: qtest: add qtest_has_accel() to check if tested binary supports = accelerator=0D =0D Currently it is not possible to create tests that have KVM as a hard=0D requirement on a host that doesn't support KVM for tested target=0D binary (modulo going through the trouble of compiling out=0D the offending test case).=0D =0D Following scenario makes test fail when it's run on non x86 host:=0D qemu-system-x86_64 -enable-kvm -M q35,kernel-irqchip=3Don -smp 1,maxcpu= s=3D288=0D =0D This patch introduces qtest_has_accel() to let users check if accel is=0D= available in advance and avoid executing non run-able test-cases.=0D =0D It implements detection of TCG and KVM only, the rest could be=0D added later on, when we actually start testing them in qtest.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 9db5bf78ba6ace02b05667a1df8a63b10a46699a=0D https://github.com/qemu/qemu/commit/9db5bf78ba6ace02b05667a1df8a63b= 10a46699a=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected tables for acpi/q35/xapic testcase=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 59b98b1514737535cc46a2955d5ef7922836ac48=0D https://github.com/qemu/qemu/commit/59b98b1514737535cc46a2955d5ef79= 22836ac48=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: q35: test for x2APIC entries in SRAT=0D =0D Set -smp 1,maxcpus=3D288 to test for ACPI code that=0D deal with CPUs with large APIC ID (>255).=0D =0D PS:=0D Test requires KVM and in-kernel irqchip support,=0D so skip test if KVM is not available.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: d92f2410aa80b7cf022bda1d5e4d1116cd179afe=0D https://github.com/qemu/qemu/commit/d92f2410aa80b7cf022bda1d5e4d111= 6cd179afe=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/APIC.xapic=0D M tests/data/acpi/q35/DSDT.xapic=0D M tests/data/acpi/q35/FACP.xapic=0D M tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected tables blobs=0D =0D Update adds CPU entries to MADT/SRAT/FACP and DSDT to cover 288 CPUs.=0D Notable changes are that CPUs with APIC ID 255 and higher=0D use 'Processor Local x2APIC Affinity' structure in SRAT and=0D "Device" element in DSDT.=0D =0D FACP:=0D - Use APIC Cluster Model (V4) : 0=0D + Use APIC Cluster Model (V4) : 1=0D =0D SRAT:=0D ...=0D +[1010h 4112 1] Subtable Type : 00 [Processor Local APIC= /SAPIC Affinity]=0D +[1011h 4113 1] Length : 10=0D +=0D +[1012h 4114 1] Proximity Domain Low(8) : 00=0D +[1013h 4115 1] Apic ID : FE=0D +[1014h 4116 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1018h 4120 1] Local Sapic EID : 00=0D +[1019h 4121 3] Proximity Domain High(24) : 000000=0D +[101Ch 4124 4] Clock Domain : 00000000=0D +=0D +[1020h 4128 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1021h 4129 1] Length : 18=0D +=0D +[1022h 4130 2] Reserved1 : 0000=0D +[1024h 4132 4] Proximity Domain : 00000001=0D +[1028h 4136 4] Apic ID : 000000FF=0D +[102Ch 4140 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1030h 4144 4] Clock Domain : 00000000=0D +[1034h 4148 4] Reserved2 : 00000000=0D =0D ...=0D =0D +[1320h 4896 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1321h 4897 1] Length : 18=0D +=0D +[1322h 4898 2] Reserved1 : 0000=0D +[1324h 4900 4] Proximity Domain : 00000001=0D +[1328h 4904 4] Apic ID : 0000011F=0D +[132Ch 4908 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1330h 4912 4] Clock Domain : 00000000=0D +[1334h 4916 4] Reserved2 : 00000000=0D =0D DSDT:=0D =0D ...=0D + Processor (C0FE, 0xFE, 0x00000000, 0x00)=0D + {=0D ...=0D + }=0D +=0D + Device (C0FF)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0xFF) // _UID: Unique ID=0D ...=0D + }=0D =0D + Device (C11F)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0x011F) // _UID: Unique ID=0D ...=0D + }=0D =0D APIC:=0D +[034h 0052 1] Subtable Type : 00 [Processor Local APIC]= =0D +[035h 0053 1] Length : 08=0D +[036h 0054 1] Processor ID : 01=0D +[037h 0055 1] Local Apic ID : 01=0D +[038h 0056 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D =0D ...=0D =0D +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC]= =0D +[81Dh 2077 1] Length : 08=0D +[81Eh 2078 1] Processor ID : FE=0D +[81Fh 2079 1] Local Apic ID : FE=0D +[820h 2080 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +=0D +[824h 2084 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[825h 2085 1] Length : 10=0D +[826h 2086 2] Reserved : 0000=0D +[828h 2088 4] Processor x2Apic ID : 000000FF=0D +[82Ch 2092 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[830h 2096 4] Processor UID : 000000FF=0D =0D ...=0D =0D +[A24h 2596 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[A25h 2597 1] Length : 10=0D +[A26h 2598 2] Reserved : 0000=0D +[A28h 2600 4] Processor x2Apic ID : 0000011F=0D +[A2Ch 2604 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[A30h 2608 4] Processor UID : 0000011F=0D +=0D +[A34h 2612 1] Subtable Type : 01 [I/O APIC]=0D +[A35h 2613 1] Length : 0C=0D +[A36h 2614 1] I/O Apic ID : 00=0D +[A37h 2615 1] Reserved : 00=0D +[A38h 2616 4] Address : FEC00000=0D +[A3Ch 2620 4] Interrupt : 00000000=0D +=0D +[A40h 2624 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A41h 2625 1] Length : 0A=0D +[A42h 2626 1] Bus : 00=0D +[A43h 2627 1] Source : 00=0D +[A44h 2628 4] Interrupt : 00000002=0D +[A48h 2632 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D =0D -[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[04Bh 0075 1] Length : 0A=0D -[04Ch 0076 1] Bus : 00=0D -[04Dh 0077 1] Source : 05=0D -[04Eh 0078 4] Interrupt : 00000005=0D -[052h 0082 2] Flags (decoded below) : 000D=0D +[A4Ah 2634 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A4Bh 2635 1] Length : 0A=0D +[A4Ch 2636 1] Bus : 00=0D +[A4Dh 2637 1] Source : 05=0D +[A4Eh 2638 4] Interrupt : 00000005=0D +[A52h 2642 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[054h 0084 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[055h 0085 1] Length : 0A=0D -[056h 0086 1] Bus : 00=0D -[057h 0087 1] Source : 09=0D -[058h 0088 4] Interrupt : 00000009=0D -[05Ch 0092 2] Flags (decoded below) : 000D=0D +[A54h 2644 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A55h 2645 1] Length : 0A=0D +[A56h 2646 1] Bus : 00=0D +[A57h 2647 1] Source : 09=0D +[A58h 2648 4] Interrupt : 00000009=0D +[A5Ch 2652 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[05Fh 0095 1] Length : 0A=0D -[060h 0096 1] Bus : 00=0D -[061h 0097 1] Source : 0A=0D -[062h 0098 4] Interrupt : 0000000A=0D -[066h 0102 2] Flags (decoded below) : 000D=0D +[A5Eh 2654 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A5Fh 2655 1] Length : 0A=0D +[A60h 2656 1] Bus : 00=0D +[A61h 2657 1] Source : 0A=0D +[A62h 2658 4] Interrupt : 0000000A=0D +[A66h 2662 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[068h 0104 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[069h 0105 1] Length : 0A=0D -[06Ah 0106 1] Bus : 00=0D -[06Bh 0107 1] Source : 0B=0D -[06Ch 0108 4] Interrupt : 0000000B=0D -[070h 0112 2] Flags (decoded below) : 000D=0D +[A68h 2664 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A69h 2665 1] Length : 0A=0D +[A6Ah 2666 1] Bus : 00=0D +[A6Bh 2667 1] Source : 0B=0D +[A6Ch 2668 4] Interrupt : 0000000B=0D +[A70h 2672 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[072h 0114 1] Subtable Type : 04 [Local APIC NMI]=0D -[073h 0115 1] Length : 06=0D -[074h 0116 1] Processor ID : FF=0D -[075h 0117 2] Flags (decoded below) : 0000=0D +[A72h 2674 1] Subtable Type : 0A [Local x2APIC NMI]=0D +[A73h 2675 1] Length : 0C=0D +[A74h 2676 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D -[077h 0119 1] Interrupt Input LINT : 01=0D +[A76h 2678 4] Processor UID : FFFFFFFF=0D +[A7Ah 2682 1] Interrupt Input LINT : 01=0D +[A7Bh 2683 3] Reserved : 000000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ae1ce30470c7e64d5f20e2258d6ca49ae5a12048=0D https://github.com/qemu/qemu/commit/ae1ce30470c7e64d5f20e2258d6ca49= ae5a12048=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist new expected table tests/data/acpi/q35/DMAR.dmar= =0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e97bf39498561f107250b251d1ac00c30779814=0D https://github.com/qemu/qemu/commit/0e97bf39498561f107250b251d1ac00= c30779814=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for intel_iommu (DMAR table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: aeb4f8e38bf59fb17fb6313f0b65492fdfecc8cd=0D https://github.com/qemu/qemu/commit/aeb4f8e38bf59fb17fb6313f0b65492= fdfecc8cd=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: add expected blob for DMAR table=0D =0D [000h 0000 4] Signature : "DMAR" [DMA Remapping t= able]=0D [004h 0004 4] Table Length : 00000078=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 15=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 1] Host Address Width : 26=0D [025h 0037 1] Flags : 01=0D [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00= 00=0D =0D [030h 0048 2] Subtable Type : 0000 [Hardware Unit Defini= tion]=0D [032h 0050 2] Length : 0040=0D =0D [034h 0052 1] Flags : 00=0D [035h 0053 1] Reserved : 00=0D [036h 0054 2] PCI Segment Number : 0000=0D [038h 0056 8] Register Base Address : 00000000FED90000=0D =0D [040h 0064 1] Device Scope Type : 03 [IOAPIC Device]=0D [041h 0065 1] Entry Length : 08=0D [042h 0066 2] Reserved : 0000=0D [044h 0068 1] Enumeration ID : 00=0D [045h 0069 1] PCI Bus Number : FF=0D =0D [046h 0070 2] PCI Path : 00,00=0D =0D [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [049h 0073 1] Entry Length : 08=0D [04Ah 0074 2] Reserved : 0000=0D [04Ch 0076 1] Enumeration ID : 00=0D [04Dh 0077 1] PCI Bus Number : 00=0D =0D [04Eh 0078 2] PCI Path : 00,00=0D =0D [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [051h 0081 1] Entry Length : 08=0D [052h 0082 2] Reserved : 0000=0D [054h 0084 1] Enumeration ID : 00=0D [055h 0085 1] PCI Bus Number : 00=0D =0D [056h 0086 2] PCI Path : 01,00=0D =0D [058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [059h 0089 1] Entry Length : 08=0D [05Ah 0090 2] Reserved : 0000=0D [05Ch 0092 1] Enumeration ID : 00=0D [05Dh 0093 1] PCI Bus Number : 00=0D =0D [05Eh 0094 2] PCI Path : 1F,00=0D =0D [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [061h 0097 1] Entry Length : 08=0D [062h 0098 2] Reserved : 0000=0D [064h 0100 1] Enumeration ID : 00=0D [065h 0101 1] PCI Bus Number : 00=0D =0D [066h 0102 2] PCI Path : 1F,02=0D =0D [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [069h 0105 1] Entry Length : 08=0D [06Ah 0106 2] Reserved : 0000=0D [06Ch 0108 1] Enumeration ID : 00=0D [06Dh 0109 1] PCI Bus Number : 00=0D =0D [06Eh 0110 2] PCI Path : 1F,03=0D =0D [070h 0112 2] Subtable Type : 0002 [Root Port ATS Capabi= lity]=0D [072h 0114 2] Length : 0008=0D =0D [074h 0116 1] Flags : 01=0D [075h 0117 1] Reserved : 00=0D [076h 0118 2] PCI Segment Number : 0000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 5bd371958dbb5020243611ba0a9d35f7094c061e=0D https://github.com/qemu/qemu/commit/5bd371958dbb5020243611ba0a9d35f= 7094c061e=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected blobs for new acpi/q35/ivrs testcase=0D= =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 679a7c927e24a12419aee60132531c81650050d4=0D https://github.com/qemu/qemu/commit/679a7c927e24a12419aee60132531c8= 1650050d4=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for amd-iommu (IVRS table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a5cc6d49ffaddf0f78268f0661edf03bade0c729=0D https://github.com/qemu/qemu/commit/a5cc6d49ffaddf0f78268f0661edf03= bade0c729=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.ivrs=0D M tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected blobs=0D =0D DSDT:=0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + }=0D =0D New IVRS table:=0D =0D [000h 0000 4] Signature : "IVRS" [I/O Virtualizat= ion Reporting Structure]=0D [004h 0004 4] Table Length : 00000068=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 43=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 4] Virtualization Info : 00002800=0D [028h 0040 8] Reserved : 0000000000000000=0D =0D [030h 0048 1] Subtable Type : 10 [Hardware Definition Bl= ock]=0D [031h 0049 1] Flags : D1=0D [032h 0050 2] Length : 0038=0D [034h 0052 2] DeviceId : 0010=0D =0D [036h 0054 2] Capability Offset : 0040=0D [038h 0056 8] Base Address : 00000000FED80000=0D [040h 0064 2] PCI Segment Group : 0000=0D [042h 0066 2] Virtualization Info : 0000=0D [044h 0068 4] Reserved : 00000044=0D =0D [048h 0072 1] Entry Type : 02=0D [049h 0073 2] Device ID : 0000=0D [04Bh 0075 1] Data Setting : 00=0D =0D [04Ch 0076 1] Entry Type : 02=0D [04Dh 0077 2] Device ID : 0008=0D [04Fh 0079 1] Data Setting : 00=0D =0D [050h 0080 1] Entry Type : 02=0D [051h 0081 2] Device ID : 0010=0D [053h 0083 1] Data Setting : 00=0D =0D [054h 0084 1] Entry Type : 02=0D [055h 0085 2] Device ID : 00F8=0D [057h 0087 1] Data Setting : 00=0D =0D [058h 0088 1] Entry Type : 02=0D [059h 0089 2] Device ID : 00FA=0D [05Bh 0091 1] Data Setting : 00=0D =0D [05Ch 0092 1] Entry Type : 02=0D [05Dh 0093 2] Device ID : 00FB=0D [05Fh 0095 1] Data Setting : 00=0D =0D [060h 0096 1] Entry Type : 48=0D [061h 0097 2] Device ID : 0000=0D [063h 0099 1] Data Setting : 00=0D [064h 0100 1] Handle : 00=0D [065h 0101 2] Source Used Device ID : 00A0=0D [067h 0103 1] Variety : 01=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e1e07b453c6e00063ce91b59f5117c252f866d14=0D https://github.com/qemu/qemu/commit/e1e07b453c6e00063ce91b59f5117c2= 52f866d14=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: arm/virt: drop redundant test_acpi_one() in test_acpi_virt= _tcg()=0D =0D follow up call with smbios options generates the same ACPI tables,=0D so there is no need to run smbios-less variant at all.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a0f4653470d7aeedb4fc1e83070929a4bc050bf1=0D https://github.com/qemu/qemu/commit/a0f4653470d7aeedb4fc1e83070929a= 4bc050bf1=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/arm-cpu-features.c=0D =0D Log Message:=0D -----------=0D tests: arm-cpu-features: use qtest_has_kvm() API=0D =0D and drop custom function that were doing the job=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: eb3d80370381b782ede58f22eaa3a63bf97e7d3d=0D https://github.com/qemu/qemu/commit/eb3d80370381b782ede58f22eaa3a63= bf97e7d3d=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/migration-test.c=0D =0D Log Message:=0D -----------=0D tests: migration-test: use qtest_has_accel() API=0D =0D Signed-off-by: Igor Mammedov =0D Suggested-by: Thomas Huth =0D Message-Id: <20210902113551.461632-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 082e408cba90ad2a6ffb9caab4aaca39e33a899c=0D https://github.com/qemu/qemu/commit/082e408cba90ad2a6ffb9caab4aaca3= 9e33a899c=0D Author: Igor Mammedov =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: bios-tables-test: use qtest_has_accel() API to register TCG only= tests=0D =0D .. only if TCG is available=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: d13c473fe6439d32da7c975f6713b5b2b888ca1e=0D https://github.com/qemu/qemu/commit/d13c473fe6439d32da7c975f6713b5b= 2b888ca1e=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Skip protected ram IOMMU mappings=0D =0D Following the logic of commit 56918a126ae ("memory: Add RAM_PROTECTED=0D flag to skip IOMMU mappings") with VFIO, skip memory sections=0D inaccessible via normal mechanisms, including DMA.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-2-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 71339f6f1e105ee0338f2217641aaa7691d5b3b4=0D https://github.com/qemu/qemu/commit/71339f6f1e105ee0338f2217641aaa7= 691d5b3b4=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Add vhost_vdpa_section_end=0D =0D Abstract this operation, that will be reused when validating the region=0D= against the iova range that the device supports.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-3-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: ef4a0f868cecb1bbc8beccaf9d0a82a1a5539740=0D https://github.com/qemu/qemu/commit/ef4a0f868cecb1bbc8beccaf9d0a82a= 1a5539740=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-18 (Mon, 18 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/trace-events=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vdpa: Check for iova range at mappings changes=0D =0D Check vdpa device range before updating memory regions so we don't add=0D= any outside of it, and report the invalid change if any.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Message-Id: <20211014141236.923287-4-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Jason Wang =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: f1024cb41aa4c30605752bb0eb49994170536170=0D https://github.com/qemu/qemu/commit/f1024cb41aa4c30605752bb0eb49994= 170536170=0D Author: Eric Auger =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D =0D Log Message:=0D -----------=0D virtio-iommu: Remove the non transitional name=0D =0D Remove the non transitional name for virtio iommu. Like other=0D devices introduced after 1.0 spec, the virtio-iommu does=0D not need it.=0D =0D Signed-off-by: Eric Auger =0D Reported-by: Andrea Bolognani =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-2-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ec856d271e7454354d1c35c63a524e1f7b09fc74=0D https://github.com/qemu/qemu/commit/ec856d271e7454354d1c35c63a524e1= f7b09fc74=0D Author: Eric Auger =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D M include/hw/virtio/virtio-iommu.h=0D =0D Log Message:=0D -----------=0D virtio-iommu: Drop base_name and change generic_name=0D =0D Drop base_name and turn generic_name into=0D "virtio-iommu-pci". This is more in line with=0D other modern-only devices.=0D =0D Signed-off-by: Eric Auger =0D Suggested-by: Cornelia Huck =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-3-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2aa1d637a6ffaa71bebbdf8f202bb093bff0cdd0=0D https://github.com/qemu/qemu/commit/2aa1d637a6ffaa71bebbdf8f202bb09= 3bff0cdd0=0D Author: David Hildenbrand =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M subprojects/libvhost-user/libvhost-user.c=0D =0D Log Message:=0D -----------=0D libvhost-user: fix VHOST_USER_REM_MEM_REG skipping mmap_addr=0D =0D We end up not copying the mmap_addr of all existing regions, resulting=0D= in a SEGFAULT once we actually try to map/access anything within our=0D memory regions.=0D =0D Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user")=0D= Cc: qemu-stable@nongnu.org=0D Cc: Michael S. Tsirkin =0D Cc: Raphael Norwitz =0D Cc: "Marc-Andr=C3=A9 Lureau" =0D Cc: Stefan Hajnoczi =0D Cc: Paolo Bonzini =0D Cc: Coiby Xu =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20211011201047.62587-1-david@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Raphael Norwitz =0D Reviewed-by: Stefan Hajnoczi =0D =0D =0D Commit: 122585bf5dd9dde6f4c6a5a41f25bb38bbbe8dbd=0D https://github.com/qemu/qemu/commit/122585bf5dd9dde6f4c6a5a41f25bb3= 8bbbe8dbd=0D Author: Mathieu Poirier =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng.c=0D A include/hw/virtio/vhost-user-rng.h=0D =0D Log Message:=0D -----------=0D vhost-user-rng: Add vhost-user-rng implementation=0D =0D Introduce a random number generator (RNG) backend that communicates=0D with a vhost-user server to retrieve entropy. That way other VMM=0D that comply with the vhost user protocl can use the same vhost-user=0D daemon without having to write yet another RNG driver.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-2-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 8b784b61a51e14e277856c6d3e623d8531640ba6=0D https://github.com/qemu/qemu/commit/8b784b61a51e14e277856c6d3e623d8= 531640ba6=0D Author: Mathieu Poirier =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng-pci.c=0D =0D Log Message:=0D -----------=0D vhost-user-rng-pci: Add vhost-user-rng-pci implementation=0D =0D This patch provides a PCI bus interface to the vhost-user-rng backend.=0D= =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-3-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 63b63b7bb95c889d016331cc4e01796719d985c0=0D https://github.com/qemu/qemu/commit/63b63b7bb95c889d016331cc4e01796= 719d985c0=0D Author: Mathieu Poirier =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D =0D Log Message:=0D -----------=0D docs: Add documentation for vhost based RNG implementation=0D =0D Add description and example for the vhost-user based RNG implementation.=0D= =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-4-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ef390caecafe175852219986fb4f3b48a5872a09=0D https://github.com/qemu/qemu/commit/ef390caecafe175852219986fb4f3b4= 8a5872a09=0D Author: Xueming Li =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-user.c=0D =0D Log Message:=0D -----------=0D vhost-user: fix duplicated notifier MR init=0D =0D In case of device resume after suspend, VQ notifier MR still valid.=0D Duplicated registrations explode memory block list and slow down device=0D= resume.=0D =0D Fixes: 44866521bd6e ("vhost-user: support registering external host notif= iers")=0D Cc: tiwei.bie@intel.com=0D Cc: qemu-stable@nongnu.org=0D Cc: Yuwei Zhang =0D =0D Signed-off-by: Xueming Li =0D Message-Id: <20211008080215.590292-1-xuemingl@nvidia.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: fbe7fa5d00629fb9035230cf27e14e0bb27be70a=0D https://github.com/qemu/qemu/commit/fbe7fa5d00629fb9035230cf27e14e0= bb27be70a=0D Author: Ani Sinha =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D =0D We are adding a new unit test to cover the acpi hotplug support in q35 fo= r=0D multi-function bridges. This test uses a new table DSDT.multi-bridge.=0D We need to allow changes in DSDT acpi table for addition of this new=0D unit test.=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: 2853fd527e7157dd14e1e0926473fbaa279da88f=0D https://github.com/qemu/qemu/commit/2853fd527e7157dd14e1e0926473fba= a279da88f=0D Author: Ani Sinha =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D =0D commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunc= tion bridges")=0D added ACPI hotplug descriptions for cold plugged bridges for functions ot= her=0D than 0. For all other devices, the ACPI hotplug descriptions are limited = to=0D function 0 only. This change adds unit tests for this feature.=0D =0D This test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D The following diff compares the DSDT table AML with the new unit test bef= ore=0D and after the change d7346e614f4ec is introduced. In other words,=0D this diff reflects the changes that occurs in the DSDT table due to the c= hange=0D d7346e614f4ec .=0D =0D @@ -1,60 +1,38 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT.multi-bridge, Thu Oct 7 18:5= 6:05 2021=0D + * Disassembly of /tmp/aml-AN0DA1, Thu Oct 7 18:56:05 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x000020FE (8446)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xDE=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D - /*=0D - * iASL Warning: There was 1 external control method found during=0D= - * disassembly, but only 0 were resolved (1 unresolved). Additional=0D= - * ACPI tables may be required to properly disassemble the code. Thi= s=0D - * resulting disassembler output file may not compile because the=0D= - * disassembler did not know how many arguments to assign to the=0D - * unresolved methods. Note: SSDTs can be dynamically loaded at=0D - * runtime and may or may not be available via the host OS.=0D - *=0D - * In addition, the -fe option can be used to specify a file contain= ing=0D - * control method external declarations with the associated method=0D= - * argument counts. Each line of the file must be of the form:=0D - * External (, MethodObj, )=0D - * Invocation:=0D - * iasl -fe refs.txt -d dsdt.aml=0D - *=0D - * The following methods were unresolved and many not compile proper= ly=0D - * because the disassembler had to guess at the number of arguments=0D= - * required for each:=0D - */=0D - External (_SB_.PCI0.S19_.PCNT, MethodObj) // Warning: Unknown met= hod, guessing 1 arguments=0D -=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D Method (DBUG, 1, NotSerialized)=0D {=0D ToHexString (Arg0, Local0)=0D ToBuffer (Local0, Local0)=0D Local1 =3D (SizeOf (Local0) - One)=0D Local2 =3D Zero=0D While ((Local2 < Local1))=0D {=0D @@ -3322,24 +3300,60 @@=0D Method (DVNT, 2, NotSerialized)=0D {=0D If ((Arg0 & One))=0D {=0D Notify (S00, Arg1)=0D }=0D }=0D =0D Method (PCNT, 0, NotSerialized)=0D {=0D BNUM =3D One=0D DVNT (PCIU, One)=0D DVNT (PCID, 0x03)=0D }=0D }=0D =0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D - ^S19.PCNT (^S10.PCNT ())=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: 43c40f73299ff8e069b55cd9c01dbfa321a7c205=0D https://github.com/qemu/qemu/commit/43c40f73299ff8e069b55cd9c01dbfa= 321a7c205=0D Author: Ani Sinha =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D =0D We added a new unit test for testing acpi hotplug on multifunction bridge= s in=0D q35 machines. Here, we update the DSDT table gloden master blob for this = unit=0D test.=0D =0D The test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D Following is the ASL diff between the original DSDT table and the modifie= d DSDT=0D table due to the unit test. We see that multifunction bridge on bus 2 and= single=0D function bridge on bus 3 function 1 are described, not the non-bridge bal= loon=0D device on bus 4, function 2.=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Thu Oct 7 18:29:19 2021=0D + * Disassembly of /tmp/aml-C7JCA1, Thu Oct 7 18:29:19 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x00002061 (8289)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xF9=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -3265,23 +3265,95 @@=0D Method (_S1D, 0, NotSerialized) // _S1D: S1 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S2D, 0, NotSerialized) // _S2D: S2 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S3D, 0, NotSerialized) // _S3D: S3 Device Stat= e=0D {=0D Return (Zero)=0D }=0D }=0D =0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + Name (BSEL, One)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D One=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: bf2dd99b7d536cdba157fd6687810ce7b8340ccc=0D https://github.com/qemu/qemu/commit/bf2dd99b7d536cdba157fd6687810ce= 7b8340ccc=0D Author: Laurent Vivier =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D =0D Log Message:=0D -----------=0D failover: fix a regression introduced by JSON'ification of -device=0D =0D The hide_device helper can be called several times for the same=0D devices as it shouldn't change any state and should only return an=0D information.=0D =0D But not to rely anymore on QemuOpts we have introduced a new field=0D to store the parameters of the device and don't allow to update it=0D once it is done.=0D =0D And as the function is called several times, we ends with:=0D =0D warning: Cannot attach more than one primary device to 'virtio0'=0D =0D That is not only a warning as it prevents to hide the device and breaks=0D= failover.=0D =0D Fix that by checking the device id.=0D =0D Now, we fail only if the virtio-net device is really used by two differen= t=0D devices, for instance:=0D =0D -device virtio-net-pci,id=3Dvirtio0,failover=3Don,... \=0D -device vfio-pci,id=3Dhostdev0,failover_pair_id=3Dvirtio0,... \=0D -device e1000e,id=3De1000e0,failover_pair_id=3Dvirtio0,... \=0D =0D will exit with:=0D =0D Cannot attach more than one primary device to 'virtio0': 'hostdev0' and= 'e1000e0'=0D =0D Fixes: 259a10dbcb4f ("virtio-net: Store failover primary opts pointer loc= ally")=0D Cc: kwolf@redhat.com=0D Signed-off-by: Laurent Vivier =0D Message-Id: <20211019071532.682717-2-lvivier@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Kevin Wolf =0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 3b3d643d958051b7e7e23b23328f695b28be8138=0D https://github.com/qemu/qemu/commit/3b3d643d958051b7e7e23b23328f695= b28be8138=0D Author: Stefan Hajnoczi =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D =0D qemu-storage-daemon is launched with the vhost-user listen socket path.=0D= The path is first unlinked before opening the listen socket. This=0D prevents stale UNIX domain socket files from stopping socket=0D initialization.=0D =0D This behavior is undesirable in vhost-user-blk-test and the cause of a=0D= bug:=0D =0D There is a race condition in vhost-user-blk-test when QEMU launches=0D before QSD. It connects to the old socket that QSD unlinks and the=0D vhost-user connection is never serviced, resulting in a hang.=0D =0D Pass the listen socket fd to QSD to maintain listen socket continuity=0D and prevent the lost connection.=0D =0D Fixes: 806952026df41939680abe92b329715b9b4e01cc ("test: new qTest case to= test the vhost-user-blk-server")=0D Cc: Raphael Norwitz =0D Cc: Michael S. Tsirkin =0D Cc: Thomas Huth =0D Cc: Coiby Xu =0D Signed-off-by: Stefan Hajnoczi =0D Message-Id: <20211019135655.83067-1-stefanha@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 3f2755e24da81b605609818859aac00f7aac847e=0D https://github.com/qemu/qemu/commit/3f2755e24da81b605609818859aac00= f7aac847e=0D Author: Richard Henderson =0D Date: 2021-10-19 (Tue, 19 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D M hw/net/virtio-net.c=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D M hw/virtio/trace-events=0D A hw/virtio/vhost-user-rng-pci.c=0D A hw/virtio/vhost-user-rng.c=0D M hw/virtio/vhost-user.c=0D M hw/virtio/vhost-vdpa.c=0D M hw/virtio/virtio-iommu-pci.c=0D A include/hw/virtio/vhost-user-rng.h=0D M include/hw/virtio/vhost-vdpa.h=0D M include/hw/virtio/virtio-iommu.h=0D M meson.build=0D M subprojects/libvhost-user/libvhost-user.c=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DMAR.dmar=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/IVRS.ivrs=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/acpi-utils.c=0D M tests/qtest/arm-cpu-features.c=0D M tests/qtest/bios-tables-test.c=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D M tests/qtest/migration-test.c=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes=0D =0D vhost user rng=0D Fixes, cleanups all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Tue 19 Oct 2021 07:05:38 AM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (30 commits)=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D failover: fix a regression introduced by JSON'ification of -device=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D vhost-user: fix duplicated notifier MR init=0D docs: Add documentation for vhost based RNG implementation=0D vhost-user-rng-pci: Add vhost-user-rng-pci implementation=0D vhost-user-rng: Add vhost-user-rng implementation=0D libvhost-user: fix VHOST_USER_REM_MEM_REG skipping mmap_addr=0D virtio-iommu: Drop base_name and change generic_name=0D virtio-iommu: Remove the non transitional name=0D vdpa: Check for iova range at mappings changes=0D vdpa: Add vhost_vdpa_section_end=0D vdpa: Skip protected ram IOMMU mappings=0D tests: bios-tables-test: use qtest_has_accel() API to register TCG only= tests=0D tests: migration-test: use qtest_has_accel() API=0D tests: arm-cpu-features: use qtest_has_kvm() API=0D tests: acpi: arm/virt: drop redundant test_acpi_one() in test_acpi_virt= _tcg()=0D tests: acpi: update expected blobs=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/50352cce138e...3f2755e24da8= =0D From MAILER-DAEMON Wed Oct 20 09:12:22 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdBOG-0007xn-Vp for mharc-qemu-commits@gnu.org; Wed, 20 Oct 2021 09:12:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdBOA-0007wR-CN for qemu-commits@nongnu.org; Wed, 20 Oct 2021 09:12:14 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:51759 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdBO5-0005iU-4f for qemu-commits@nongnu.org; Wed, 20 Oct 2021 09:12:13 -0400 Received: from github.com (hubbernetes-node-b75a562.ash1-iad.github.net [10.56.115.19]) by smtp.github.com (Postfix) with ESMTPA id 7638D840083 for ; Wed, 20 Oct 2021 06:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634735528; bh=LU8MUesnV0mxVhUYRpPdSqiS+vNRm3Kmr83iMt+tmJA=; h=Date:From:To:Subject:From; b=jUmEE1cxaRv9HC1AsAh40/tSNe08AWSlSEWKoFfMv5Al+cVZIFe4sW+Vz55Cyr4by CJciG9plUqEVln3VP4J/KCAN9grVrMlhgPlhDQwO2wP/5dSO11x6HJfq65uWRZPXam JVT+QBewaViLDuBN9KLDI2jjIWuaKa991lAFv8sk= Date: Wed, 20 Oct 2021 06:12:08 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HEXHASH_WORD=1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 685db1: tests: acpi: dump table with failed checksum X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Oct 2021 13:12:14 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 685db13a38f7599fabd353382ff65d3c244ea641=0D https://github.com/qemu/qemu/commit/685db13a38f7599fabd353382ff65d3= c244ea641=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/acpi-utils.c=0D =0D Log Message:=0D -----------=0D tests: acpi: dump table with failed checksum=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e741aff0f43343d6d91242fee1072fee376d5cce=0D https://github.com/qemu/qemu/commit/e741aff0f43343d6d91242fee1072fe= e376d5cce=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D =0D Log Message:=0D -----------=0D tests: qtest: add qtest_has_accel() to check if tested binary supports = accelerator=0D =0D Currently it is not possible to create tests that have KVM as a hard=0D requirement on a host that doesn't support KVM for tested target=0D binary (modulo going through the trouble of compiling out=0D the offending test case).=0D =0D Following scenario makes test fail when it's run on non x86 host:=0D qemu-system-x86_64 -enable-kvm -M q35,kernel-irqchip=3Don -smp 1,maxcpu= s=3D288=0D =0D This patch introduces qtest_has_accel() to let users check if accel is=0D= available in advance and avoid executing non run-able test-cases.=0D =0D It implements detection of TCG and KVM only, the rest could be=0D added later on, when we actually start testing them in qtest.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c306cdb0cc5327f336fbf9a7411f319f0717ee75=0D https://github.com/qemu/qemu/commit/c306cdb0cc5327f336fbf9a7411f319= f0717ee75=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected tables for acpi/q35/xapic testcase=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 80a2f3387c239d06d4a4b6838b511a88838ddc0f=0D https://github.com/qemu/qemu/commit/80a2f3387c239d06d4a4b6838b511a8= 8838ddc0f=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: q35: test for x2APIC entries in SRAT=0D =0D Set -smp 1,maxcpus=3D288 to test for ACPI code that=0D deal with CPUs with large APIC ID (>255).=0D =0D PS:=0D Test requires KVM and in-kernel irqchip support,=0D so skip test if KVM is not available.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b59a898458aea328618521be7dc180d2396c0bf4=0D https://github.com/qemu/qemu/commit/b59a898458aea328618521be7dc180d= 2396c0bf4=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/APIC.xapic=0D M tests/data/acpi/q35/DSDT.xapic=0D M tests/data/acpi/q35/FACP.xapic=0D M tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected tables blobs=0D =0D Update adds CPU entries to MADT/SRAT/FACP and DSDT to cover 288 CPUs.=0D Notable changes are that CPUs with APIC ID 255 and higher=0D use 'Processor Local x2APIC Affinity' structure in SRAT and=0D "Device" element in DSDT.=0D =0D FACP:=0D - Use APIC Cluster Model (V4) : 0=0D + Use APIC Cluster Model (V4) : 1=0D =0D SRAT:=0D ...=0D +[1010h 4112 1] Subtable Type : 00 [Processor Local APIC= /SAPIC Affinity]=0D +[1011h 4113 1] Length : 10=0D +=0D +[1012h 4114 1] Proximity Domain Low(8) : 00=0D +[1013h 4115 1] Apic ID : FE=0D +[1014h 4116 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1018h 4120 1] Local Sapic EID : 00=0D +[1019h 4121 3] Proximity Domain High(24) : 000000=0D +[101Ch 4124 4] Clock Domain : 00000000=0D +=0D +[1020h 4128 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1021h 4129 1] Length : 18=0D +=0D +[1022h 4130 2] Reserved1 : 0000=0D +[1024h 4132 4] Proximity Domain : 00000001=0D +[1028h 4136 4] Apic ID : 000000FF=0D +[102Ch 4140 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1030h 4144 4] Clock Domain : 00000000=0D +[1034h 4148 4] Reserved2 : 00000000=0D =0D ...=0D =0D +[1320h 4896 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1321h 4897 1] Length : 18=0D +=0D +[1322h 4898 2] Reserved1 : 0000=0D +[1324h 4900 4] Proximity Domain : 00000001=0D +[1328h 4904 4] Apic ID : 0000011F=0D +[132Ch 4908 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1330h 4912 4] Clock Domain : 00000000=0D +[1334h 4916 4] Reserved2 : 00000000=0D =0D DSDT:=0D =0D ...=0D + Processor (C0FE, 0xFE, 0x00000000, 0x00)=0D + {=0D ...=0D + }=0D +=0D + Device (C0FF)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0xFF) // _UID: Unique ID=0D ...=0D + }=0D =0D + Device (C11F)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0x011F) // _UID: Unique ID=0D ...=0D + }=0D =0D APIC:=0D +[034h 0052 1] Subtable Type : 00 [Processor Local APIC]= =0D +[035h 0053 1] Length : 08=0D +[036h 0054 1] Processor ID : 01=0D +[037h 0055 1] Local Apic ID : 01=0D +[038h 0056 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D =0D ...=0D =0D +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC]= =0D +[81Dh 2077 1] Length : 08=0D +[81Eh 2078 1] Processor ID : FE=0D +[81Fh 2079 1] Local Apic ID : FE=0D +[820h 2080 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +=0D +[824h 2084 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[825h 2085 1] Length : 10=0D +[826h 2086 2] Reserved : 0000=0D +[828h 2088 4] Processor x2Apic ID : 000000FF=0D +[82Ch 2092 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[830h 2096 4] Processor UID : 000000FF=0D =0D ...=0D =0D +[A24h 2596 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[A25h 2597 1] Length : 10=0D +[A26h 2598 2] Reserved : 0000=0D +[A28h 2600 4] Processor x2Apic ID : 0000011F=0D +[A2Ch 2604 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[A30h 2608 4] Processor UID : 0000011F=0D +=0D +[A34h 2612 1] Subtable Type : 01 [I/O APIC]=0D +[A35h 2613 1] Length : 0C=0D +[A36h 2614 1] I/O Apic ID : 00=0D +[A37h 2615 1] Reserved : 00=0D +[A38h 2616 4] Address : FEC00000=0D +[A3Ch 2620 4] Interrupt : 00000000=0D +=0D +[A40h 2624 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A41h 2625 1] Length : 0A=0D +[A42h 2626 1] Bus : 00=0D +[A43h 2627 1] Source : 00=0D +[A44h 2628 4] Interrupt : 00000002=0D +[A48h 2632 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D =0D -[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[04Bh 0075 1] Length : 0A=0D -[04Ch 0076 1] Bus : 00=0D -[04Dh 0077 1] Source : 05=0D -[04Eh 0078 4] Interrupt : 00000005=0D -[052h 0082 2] Flags (decoded below) : 000D=0D +[A4Ah 2634 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A4Bh 2635 1] Length : 0A=0D +[A4Ch 2636 1] Bus : 00=0D +[A4Dh 2637 1] Source : 05=0D +[A4Eh 2638 4] Interrupt : 00000005=0D +[A52h 2642 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[054h 0084 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[055h 0085 1] Length : 0A=0D -[056h 0086 1] Bus : 00=0D -[057h 0087 1] Source : 09=0D -[058h 0088 4] Interrupt : 00000009=0D -[05Ch 0092 2] Flags (decoded below) : 000D=0D +[A54h 2644 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A55h 2645 1] Length : 0A=0D +[A56h 2646 1] Bus : 00=0D +[A57h 2647 1] Source : 09=0D +[A58h 2648 4] Interrupt : 00000009=0D +[A5Ch 2652 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[05Fh 0095 1] Length : 0A=0D -[060h 0096 1] Bus : 00=0D -[061h 0097 1] Source : 0A=0D -[062h 0098 4] Interrupt : 0000000A=0D -[066h 0102 2] Flags (decoded below) : 000D=0D +[A5Eh 2654 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A5Fh 2655 1] Length : 0A=0D +[A60h 2656 1] Bus : 00=0D +[A61h 2657 1] Source : 0A=0D +[A62h 2658 4] Interrupt : 0000000A=0D +[A66h 2662 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[068h 0104 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[069h 0105 1] Length : 0A=0D -[06Ah 0106 1] Bus : 00=0D -[06Bh 0107 1] Source : 0B=0D -[06Ch 0108 4] Interrupt : 0000000B=0D -[070h 0112 2] Flags (decoded below) : 000D=0D +[A68h 2664 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A69h 2665 1] Length : 0A=0D +[A6Ah 2666 1] Bus : 00=0D +[A6Bh 2667 1] Source : 0B=0D +[A6Ch 2668 4] Interrupt : 0000000B=0D +[A70h 2672 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[072h 0114 1] Subtable Type : 04 [Local APIC NMI]=0D -[073h 0115 1] Length : 06=0D -[074h 0116 1] Processor ID : FF=0D -[075h 0117 2] Flags (decoded below) : 0000=0D +[A72h 2674 1] Subtable Type : 0A [Local x2APIC NMI]=0D +[A73h 2675 1] Length : 0C=0D +[A74h 2676 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D -[077h 0119 1] Interrupt Input LINT : 01=0D +[A76h 2678 4] Processor UID : FFFFFFFF=0D +[A7Ah 2682 1] Interrupt Input LINT : 01=0D +[A7Bh 2683 3] Reserved : 000000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: f6826ac4ae2dea392a69fe1ca870a8a27e2bf0ac=0D https://github.com/qemu/qemu/commit/f6826ac4ae2dea392a69fe1ca870a8a= 27e2bf0ac=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist new expected table tests/data/acpi/q35/DMAR.dmar= =0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0ff92b6d99011c8de57321503c0eb655c461a217=0D https://github.com/qemu/qemu/commit/0ff92b6d99011c8de57321503c0eb65= 5c461a217=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for intel_iommu (DMAR table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 44d3bdd8a6f1ae2a5ca417251736a033900d4c08=0D https://github.com/qemu/qemu/commit/44d3bdd8a6f1ae2a5ca417251736a03= 3900d4c08=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: add expected blob for DMAR table=0D =0D [000h 0000 4] Signature : "DMAR" [DMA Remapping t= able]=0D [004h 0004 4] Table Length : 00000078=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 15=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 1] Host Address Width : 26=0D [025h 0037 1] Flags : 01=0D [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00= 00=0D =0D [030h 0048 2] Subtable Type : 0000 [Hardware Unit Defini= tion]=0D [032h 0050 2] Length : 0040=0D =0D [034h 0052 1] Flags : 00=0D [035h 0053 1] Reserved : 00=0D [036h 0054 2] PCI Segment Number : 0000=0D [038h 0056 8] Register Base Address : 00000000FED90000=0D =0D [040h 0064 1] Device Scope Type : 03 [IOAPIC Device]=0D [041h 0065 1] Entry Length : 08=0D [042h 0066 2] Reserved : 0000=0D [044h 0068 1] Enumeration ID : 00=0D [045h 0069 1] PCI Bus Number : FF=0D =0D [046h 0070 2] PCI Path : 00,00=0D =0D [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [049h 0073 1] Entry Length : 08=0D [04Ah 0074 2] Reserved : 0000=0D [04Ch 0076 1] Enumeration ID : 00=0D [04Dh 0077 1] PCI Bus Number : 00=0D =0D [04Eh 0078 2] PCI Path : 00,00=0D =0D [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [051h 0081 1] Entry Length : 08=0D [052h 0082 2] Reserved : 0000=0D [054h 0084 1] Enumeration ID : 00=0D [055h 0085 1] PCI Bus Number : 00=0D =0D [056h 0086 2] PCI Path : 01,00=0D =0D [058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [059h 0089 1] Entry Length : 08=0D [05Ah 0090 2] Reserved : 0000=0D [05Ch 0092 1] Enumeration ID : 00=0D [05Dh 0093 1] PCI Bus Number : 00=0D =0D [05Eh 0094 2] PCI Path : 1F,00=0D =0D [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [061h 0097 1] Entry Length : 08=0D [062h 0098 2] Reserved : 0000=0D [064h 0100 1] Enumeration ID : 00=0D [065h 0101 1] PCI Bus Number : 00=0D =0D [066h 0102 2] PCI Path : 1F,02=0D =0D [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [069h 0105 1] Entry Length : 08=0D [06Ah 0106 2] Reserved : 0000=0D [06Ch 0108 1] Enumeration ID : 00=0D [06Dh 0109 1] PCI Bus Number : 00=0D =0D [06Eh 0110 2] PCI Path : 1F,03=0D =0D [070h 0112 2] Subtable Type : 0002 [Root Port ATS Capabi= lity]=0D [072h 0114 2] Length : 0008=0D =0D [074h 0116 1] Flags : 01=0D [075h 0117 1] Reserved : 00=0D [076h 0118 2] PCI Segment Number : 0000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c5a7baad2997091c48ec40a2a8efa63f18f9b3b7=0D https://github.com/qemu/qemu/commit/c5a7baad2997091c48ec40a2a8efa63= f18f9b3b7=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected blobs for new acpi/q35/ivrs testcase=0D= =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a4c730cbb284479ec2f7799bbbd7521525553593=0D https://github.com/qemu/qemu/commit/a4c730cbb284479ec2f7799bbbd7521= 525553593=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for amd-iommu (IVRS table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ef422a14226fd0078bdf61657fdd63099cb49099=0D https://github.com/qemu/qemu/commit/ef422a14226fd0078bdf61657fdd630= 99cb49099=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.ivrs=0D M tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected blobs=0D =0D DSDT:=0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + }=0D =0D New IVRS table:=0D =0D [000h 0000 4] Signature : "IVRS" [I/O Virtualizat= ion Reporting Structure]=0D [004h 0004 4] Table Length : 00000068=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 43=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 4] Virtualization Info : 00002800=0D [028h 0040 8] Reserved : 0000000000000000=0D =0D [030h 0048 1] Subtable Type : 10 [Hardware Definition Bl= ock]=0D [031h 0049 1] Flags : D1=0D [032h 0050 2] Length : 0038=0D [034h 0052 2] DeviceId : 0010=0D =0D [036h 0054 2] Capability Offset : 0040=0D [038h 0056 8] Base Address : 00000000FED80000=0D [040h 0064 2] PCI Segment Group : 0000=0D [042h 0066 2] Virtualization Info : 0000=0D [044h 0068 4] Reserved : 00000044=0D =0D [048h 0072 1] Entry Type : 02=0D [049h 0073 2] Device ID : 0000=0D [04Bh 0075 1] Data Setting : 00=0D =0D [04Ch 0076 1] Entry Type : 02=0D [04Dh 0077 2] Device ID : 0008=0D [04Fh 0079 1] Data Setting : 00=0D =0D [050h 0080 1] Entry Type : 02=0D [051h 0081 2] Device ID : 0010=0D [053h 0083 1] Data Setting : 00=0D =0D [054h 0084 1] Entry Type : 02=0D [055h 0085 2] Device ID : 00F8=0D [057h 0087 1] Data Setting : 00=0D =0D [058h 0088 1] Entry Type : 02=0D [059h 0089 2] Device ID : 00FA=0D [05Bh 0091 1] Data Setting : 00=0D =0D [05Ch 0092 1] Entry Type : 02=0D [05Dh 0093 2] Device ID : 00FB=0D [05Fh 0095 1] Data Setting : 00=0D =0D [060h 0096 1] Entry Type : 48=0D [061h 0097 2] Device ID : 0000=0D [063h 0099 1] Data Setting : 00=0D [064h 0100 1] Handle : 00=0D [065h 0101 2] Source Used Device ID : 00A0=0D [067h 0103 1] Variety : 01=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 709611cb23cc677fa0c2d4de76a21c24baefe9a0=0D https://github.com/qemu/qemu/commit/709611cb23cc677fa0c2d4de76a21c2= 4baefe9a0=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: arm/virt: drop redundant test_acpi_one() in test_acpi_virt= _tcg()=0D =0D follow up call with smbios options generates the same ACPI tables,=0D so there is no need to run smbios-less variant at all.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 07e6ed2c79b311aad4d2c87740753752ad1503ba=0D https://github.com/qemu/qemu/commit/07e6ed2c79b311aad4d2c8774075375= 2ad1503ba=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/arm-cpu-features.c=0D =0D Log Message:=0D -----------=0D tests: arm-cpu-features: use qtest_has_kvm() API=0D =0D and drop custom function that were doing the job=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b72c76033de766d4ff891c582514caf12edbbfb4=0D https://github.com/qemu/qemu/commit/b72c76033de766d4ff891c582514caf= 12edbbfb4=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/migration-test.c=0D =0D Log Message:=0D -----------=0D tests: migration-test: use qtest_has_accel() API=0D =0D Signed-off-by: Igor Mammedov =0D Suggested-by: Thomas Huth =0D Message-Id: <20210902113551.461632-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 220ffd949bf2c157665905f7744bdbf201333e1f=0D https://github.com/qemu/qemu/commit/220ffd949bf2c157665905f7744bdbf= 201333e1f=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: bios-tables-test: use qtest_has_accel() API to register TCG only= tests=0D =0D .. only if TCG is available=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c64038c93e171697058d96871f87a4438b613662=0D https://github.com/qemu/qemu/commit/c64038c93e171697058d96871f87a44= 38b613662=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Skip protected ram IOMMU mappings=0D =0D Following the logic of commit 56918a126ae ("memory: Add RAM_PROTECTED=0D flag to skip IOMMU mappings") with VFIO, skip memory sections=0D inaccessible via normal mechanisms, including DMA.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-2-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 032e4d686e9c6f8ae3b9206c720ae3614e28d8a3=0D https://github.com/qemu/qemu/commit/032e4d686e9c6f8ae3b9206c720ae36= 14e28d8a3=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Add vhost_vdpa_section_end=0D =0D Abstract this operation, that will be reused when validating the region=0D= against the iova range that the device supports.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-3-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 013108b6e51e1c10b78859e2e091202364aa7a7d=0D https://github.com/qemu/qemu/commit/013108b6e51e1c10b78859e2e091202= 364aa7a7d=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/trace-events=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vdpa: Check for iova range at mappings changes=0D =0D Check vdpa device range before updating memory regions so we don't add=0D= any outside of it, and report the invalid change if any.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Message-Id: <20211014141236.923287-4-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Jason Wang =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 819bbda81fd6a08bea79d56a6ca27092ec29719b=0D https://github.com/qemu/qemu/commit/819bbda81fd6a08bea79d56a6ca2709= 2ec29719b=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D =0D Log Message:=0D -----------=0D virtio-iommu: Remove the non transitional name=0D =0D Remove the non transitional name for virtio iommu. Like other=0D devices introduced after 1.0 spec, the virtio-iommu does=0D not need it.=0D =0D Signed-off-by: Eric Auger =0D Reported-by: Andrea Bolognani =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-2-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 19d20e910a586f503994acf590d5f41c314fa4c3=0D https://github.com/qemu/qemu/commit/19d20e910a586f503994acf590d5f41= c314fa4c3=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D M include/hw/virtio/virtio-iommu.h=0D =0D Log Message:=0D -----------=0D virtio-iommu: Drop base_name and change generic_name=0D =0D Drop base_name and turn generic_name into=0D "virtio-iommu-pci". This is more in line with=0D other modern-only devices.=0D =0D Signed-off-by: Eric Auger =0D Suggested-by: Cornelia Huck =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-3-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 6889eb2d431ae962e3e083b57bff47cd573cb1c4=0D https://github.com/qemu/qemu/commit/6889eb2d431ae962e3e083b57bff47c= d573cb1c4=0D Author: David Hildenbrand =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M subprojects/libvhost-user/libvhost-user.c=0D =0D Log Message:=0D -----------=0D libvhost-user: fix VHOST_USER_REM_MEM_REG skipping mmap_addr=0D =0D We end up not copying the mmap_addr of all existing regions, resulting=0D= in a SEGFAULT once we actually try to map/access anything within our=0D memory regions.=0D =0D Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user")=0D= Cc: qemu-stable@nongnu.org=0D Cc: Michael S. Tsirkin =0D Cc: Raphael Norwitz =0D Cc: "Marc-Andr=C3=A9 Lureau" =0D Cc: Stefan Hajnoczi =0D Cc: Paolo Bonzini =0D Cc: Coiby Xu =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20211011201047.62587-1-david@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Raphael Norwitz =0D Reviewed-by: Stefan Hajnoczi =0D =0D =0D Commit: 821d28b88f850e5fbc66ee62bdd155eb2d474a29=0D https://github.com/qemu/qemu/commit/821d28b88f850e5fbc66ee62bdd155e= b2d474a29=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng.c=0D A include/hw/virtio/vhost-user-rng.h=0D =0D Log Message:=0D -----------=0D vhost-user-rng: Add vhost-user-rng implementation=0D =0D Introduce a random number generator (RNG) backend that communicates=0D with a vhost-user server to retrieve entropy. That way other VMM=0D that comply with the vhost user protocl can use the same vhost-user=0D daemon without having to write yet another RNG driver.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-2-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c7160fff7d48cead5d673ef2032b60c363c84e27=0D https://github.com/qemu/qemu/commit/c7160fff7d48cead5d673ef2032b60c= 363c84e27=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng-pci.c=0D =0D Log Message:=0D -----------=0D vhost-user-rng-pci: Add vhost-user-rng-pci implementation=0D =0D This patch provides a PCI bus interface to the vhost-user-rng backend.=0D= =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-3-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c47d4fa0c8f0a28614cc0ce849dc9bbaa5c6878f=0D https://github.com/qemu/qemu/commit/c47d4fa0c8f0a28614cc0ce849dc9bb= aa5c6878f=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D =0D Log Message:=0D -----------=0D docs: Add documentation for vhost based RNG implementation=0D =0D Add description and example for the vhost-user based RNG implementation.=0D= =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-4-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a1ed9ef1de87c3e86ff68589604298ec90875a14=0D https://github.com/qemu/qemu/commit/a1ed9ef1de87c3e86ff68589604298e= c90875a14=0D Author: Xueming Li =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-user.c=0D =0D Log Message:=0D -----------=0D vhost-user: fix duplicated notifier MR init=0D =0D In case of device resume after suspend, VQ notifier MR still valid.=0D Duplicated registrations explode memory block list and slow down device=0D= resume.=0D =0D Fixes: 44866521bd6e ("vhost-user: support registering external host notif= iers")=0D Cc: tiwei.bie@intel.com=0D Cc: qemu-stable@nongnu.org=0D Cc: Yuwei Zhang =0D =0D Signed-off-by: Xueming Li =0D Message-Id: <20211008080215.590292-1-xuemingl@nvidia.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7fe7791e3f652ac31ef98dcc94a8f2a317ab846b=0D https://github.com/qemu/qemu/commit/7fe7791e3f652ac31ef98dcc94a8f2a= 317ab846b=0D Author: Laurent Vivier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D =0D Log Message:=0D -----------=0D failover: fix a regression introduced by JSON'ification of -device=0D =0D The hide_device helper can be called several times for the same=0D devices as it shouldn't change any state and should only return an=0D information.=0D =0D But not to rely anymore on QemuOpts we have introduced a new field=0D to store the parameters of the device and don't allow to update it=0D once it is done.=0D =0D And as the function is called several times, we ends with:=0D =0D warning: Cannot attach more than one primary device to 'virtio0'=0D =0D That is not only a warning as it prevents to hide the device and breaks=0D= failover.=0D =0D Fix that by checking the device id.=0D =0D Now, we fail only if the virtio-net device is really used by two differen= t=0D devices, for instance:=0D =0D -device virtio-net-pci,id=3Dvirtio0,failover=3Don,... \=0D -device vfio-pci,id=3Dhostdev0,failover_pair_id=3Dvirtio0,... \=0D -device e1000e,id=3De1000e0,failover_pair_id=3Dvirtio0,... \=0D =0D will exit with:=0D =0D Cannot attach more than one primary device to 'virtio0': 'hostdev0' and= 'e1000e0'=0D =0D Fixes: 259a10dbcb4f ("virtio-net: Store failover primary opts pointer loc= ally")=0D Cc: kwolf@redhat.com=0D Signed-off-by: Laurent Vivier =0D Message-Id: <20211019071532.682717-2-lvivier@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Kevin Wolf =0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 515efffc2fd0928317a0a1ec47b28a972c40ddad=0D https://github.com/qemu/qemu/commit/515efffc2fd0928317a0a1ec47b28a9= 72c40ddad=0D Author: Stefan Hajnoczi =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D =0D qemu-storage-daemon is launched with the vhost-user listen socket path.=0D= The path is first unlinked before opening the listen socket. This=0D prevents stale UNIX domain socket files from stopping socket=0D initialization.=0D =0D This behavior is undesirable in vhost-user-blk-test and the cause of a=0D= bug:=0D =0D There is a race condition in vhost-user-blk-test when QEMU launches=0D before QSD. It connects to the old socket that QSD unlinks and the=0D vhost-user connection is never serviced, resulting in a hang.=0D =0D Pass the listen socket fd to QSD to maintain listen socket continuity=0D and prevent the lost connection.=0D =0D Fixes: 806952026df41939680abe92b329715b9b4e01cc ("test: new qTest case to= test the vhost-user-blk-server")=0D Cc: Raphael Norwitz =0D Cc: Michael S. Tsirkin =0D Cc: Thomas Huth =0D Cc: Coiby Xu =0D Signed-off-by: Stefan Hajnoczi =0D Message-Id: <20211019135655.83067-1-stefanha@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: bcfc906be47a88803307cd6b665dc4c26fdd6dd2=0D https://github.com/qemu/qemu/commit/bcfc906be47a88803307cd6b665dc4c= 26fdd6dd2=0D Author: Laurent Vivier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D M softmmu/qdev-monitor.c=0D =0D Log Message:=0D -----------=0D qdev/qbus: remove failover specific code=0D =0D Commit f3a850565693 ("qdev/qbus: add hidden device support") has=0D introduced a generic way to hide a device but it has modified=0D qdev_device_add() to check a specific option of the failover device,=0D "failover_pair_id", before calling the generic mechanism.=0D =0D It's not needed (and not generic) to do that in qdev_device_add() because= =0D this is also checked by the failover_hide_primary_device() function that=0D= uses the generic mechanism to hide the device.=0D =0D Cc: Jens Freimann =0D Signed-off-by: Laurent Vivier =0D Message-Id: <20211019071532.682717-3-lvivier@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 71352aa95bf49d7a0ddab4e685147974c32ebc2c=0D https://github.com/qemu/qemu/commit/71352aa95bf49d7a0ddab4e68514797= 4c32ebc2c=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/rebuild-expected-aml.sh=0D =0D Log Message:=0D -----------=0D rebuild-expected-aml.sh: allow partial target list=0D =0D Only rebuild AML for configured targets.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 81d7228647e0bd17d4f4f0434b8ed410fe5f7497=0D https://github.com/qemu/qemu/commit/81d7228647e0bd17d4f4f0434b8ed41= 0fe5f7497=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D bios-tables-test: don't disassemble empty files=0D =0D A recommended way to populate new tables is to have an=0D empty expected file. In this case, attempts to disassemble=0D will fail but it is useful to disassemble the actual files.=0D Detect and skip decompile step in this case.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7327813d17086fadabe3b27ba2d9737c8a33c5b0=0D https://github.com/qemu/qemu/commit/7327813d17086fadabe3b27ba2d9737= c8a33c5b0=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: open device fd in net_init_vhost_vdpa()=0D =0D This patch switches to open device fd in net_init_vhost_vpda(). This is=0D= used to prepare for the multiqueue support.=0D =0D Reviewed-by: Stefano Garzarella =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-2-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 4d191cfdc7de958d06f821173f721c56bc131620=0D https://github.com/qemu/qemu/commit/4d191cfdc7de958d06f821173f721c5= 6bc131620=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vhost-vdpa: classify one time request=0D =0D Vhost-vdpa uses one device multiqueue queue (pairs) model. So we need=0D to classify the one time request (e.g SET_OWNER) and make sure those=0D request were only called once per device.=0D =0D This is used for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-3-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 353244d8b96767659e6c95c0c87dfe4372fe8c12=0D https://github.com/qemu/qemu/commit/353244d8b96767659e6c95c0c87dfe4= 372fe8c12=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: prepare for the multiqueue support=0D =0D Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue=0D model. So we need to simply use virtqueue index as the vhost virtqueue=0D= index. This is a must for multiqueue to work for vhost-vdpa.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-4-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 654790b65b8435a7d409b1873b566e8db9e91b9b=0D https://github.com/qemu/qemu/commit/654790b65b8435a7d409b1873b566e8= db9e91b9b=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState *=0D =0D This patch switches to let net_vhost_vdpa_init() to return=0D NetClientState *. This is used for the callers to allocate multiqueue=0D NetClientState for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-5-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2f849dbdb2ab2c70715520a8129524f197b9a8ba=0D https://github.com/qemu/qemu/commit/2f849dbdb2ab2c70715520a8129524f= 197b9a8ba=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M include/net/net.h=0D M net/net.c=0D =0D Log Message:=0D -----------=0D net: introduce control client=0D =0D This patch introduces a boolean for the device has control queue which=0D= can accepts control command via network queue.=0D =0D The first user would be the control virtqueue support for vhost.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-6-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 05ba3f63d174a716b42aa31c9af5d0ef64fff515=0D https://github.com/qemu/qemu/commit/05ba3f63d174a716b42aa31c9af5d0e= f64fff515=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net-stub.c=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/net/vhost_net.h=0D =0D Log Message:=0D -----------=0D vhost-net: control virtqueue support=0D =0D We assume there's no cvq in the past, this is not true when we need=0D control virtqueue support for vhost-user backends. So this patch=0D implements the control virtqueue support for vhost-net. As datapath,=0D the control virtqueue is also required to be coupled with the=0D NetClientState. The vhost_net_start/stop() are tweaked to accept the=0D number of datapath queue pairs plus the the number of control=0D virtqueue for us to start and stop the vhost device.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-7-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 441537f1ce0153978b4c9ee1cc4d4152147aa16f=0D https://github.com/qemu/qemu/commit/441537f1ce0153978b4c9ee1cc4d415= 2147aa16f=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: use "queue_pairs" instead of "queues" when possible=0D =0D Most of the time, "queues" really means queue pairs. So this patch=0D switch to use "queue_pairs" to avoid confusion.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-8-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 049eb15b5fc9c54ae76254a196b695000127da7a=0D https://github.com/qemu/qemu/commit/049eb15b5fc9c54ae76254a196b6950= 00127da7a=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M include/hw/virtio/vhost.h=0D =0D Log Message:=0D -----------=0D vhost: record the last virtqueue index for the virtio device=0D =0D This patch introduces a new field in the vhost_dev structure to record=0D= the last virtqueue index for the virtio device. This will be useful=0D for the vhost backends with 1:N model to start or stop the device=0D after all the vhost_dev structures were started or stopped.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-9-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 22288fe5a3f2dc4cb5c8826646d466019ad67682=0D https://github.com/qemu/qemu/commit/22288fe5a3f2dc4cb5c8826646d4660= 19ad67682=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: vhost control virtqueue support=0D =0D This patch implements the control virtqueue support for vhost. This=0D requires virtio-net to figure out the datapath queue pairs and control=0D= virtqueue via is_datapath and pass the number of those two types=0D of virtqueues to vhost_net_start()/vhost_net_stop().=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-10-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 402378407dbdce79ce745a13f5c84815f929cfdd=0D https://github.com/qemu/qemu/commit/402378407dbdce79ce745a13f5c8481= 5f929cfdd=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: multiqueue support=0D =0D This patch implements the multiqueue support for vhost-vdpa. This is=0D done simply by reading the number of queue pairs from the config space=0D= and initialize the datapath and control path net client.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-11-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e464f7d993113119f0fd17b890831440734ce15=0D https://github.com/qemu/qemu/commit/0e464f7d993113119f0fd17b8908314= 40734ce15=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/pci/pci_bridge.c=0D =0D Log Message:=0D -----------=0D pci: fix PCI resource reserve capability on BE=0D =0D PCI resource reserve capability should use LE format as all other PCI=0D things. If we don't then seabios won't boot:=0D =0D =3D=3D=3D PCI new allocation pass #1 =3D=3D=3D=0D PCI: check devices=0D PCI: QEMU resource reserve cap: size 10000000000000 type io=0D PCI: secondary bus 1 size 10000000000000 type io=0D PCI: secondary bus 1 size 00200000 type mem=0D PCI: secondary bus 1 size 00200000 type prefmem=0D =3D=3D=3D PCI new allocation pass #2 =3D=3D=3D=0D PCI: out of I/O address space=0D =0D This became more important since we started reserving IO by default,=0D previously no one noticed.=0D =0D Fixes: e2a6290aab ("hw/pcie-root-port: Fix hotplug for PCI devices requir= ing IO")=0D Cc: marcel.apfelbaum@gmail.com=0D Fixes: 226263fb5c ("hw/pci: add QEMU-specific PCI capability to the Gener= ic PCI Express Root Port")=0D Cc: zuban32s@gmail.com=0D Fixes: 6755e618d0 ("hw/pci: add PCI resource reserve capability to legacy= PCI bridge")=0D Cc: jing2.liu@linux.intel.com=0D Tested-by: Thomas Huth =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 6dcb1cc9512c6b4cd8f85abc537abaf6f6c0738b=0D https://github.com/qemu/qemu/commit/6dcb1cc9512c6b4cd8f85abc537abaf= 6f6c0738b=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D =0D We are adding a new unit test to cover the acpi hotplug support in q35 fo= r=0D multi-function bridges. This test uses a new table DSDT.multi-bridge.=0D We need to allow changes in DSDT acpi table for addition of this new=0D unit test.=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: 04dd78b9e85720226a148eef54b45cb02b463034=0D https://github.com/qemu/qemu/commit/04dd78b9e85720226a148eef54b45cb= 02b463034=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D =0D commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunc= tion bridges")=0D added ACPI hotplug descriptions for cold plugged bridges for functions ot= her=0D than 0. For all other devices, the ACPI hotplug descriptions are limited = to=0D function 0 only. This change adds unit tests for this feature.=0D =0D This test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D The following diff compares the DSDT table AML with the new unit test bef= ore=0D and after the change d7346e614f4ec is introduced. In other words,=0D this diff reflects the changes that occurs in the DSDT table due to the c= hange=0D d7346e614f4ec .=0D =0D @@ -1,60 +1,38 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT.multi-bridge, Thu Oct 7 18:5= 6:05 2021=0D + * Disassembly of /tmp/aml-AN0DA1, Thu Oct 7 18:56:05 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x000020FE (8446)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xDE=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D - /*=0D - * iASL Warning: There was 1 external control method found during=0D= - * disassembly, but only 0 were resolved (1 unresolved). Additional=0D= - * ACPI tables may be required to properly disassemble the code. Thi= s=0D - * resulting disassembler output file may not compile because the=0D= - * disassembler did not know how many arguments to assign to the=0D - * unresolved methods. Note: SSDTs can be dynamically loaded at=0D - * runtime and may or may not be available via the host OS.=0D - *=0D - * In addition, the -fe option can be used to specify a file contain= ing=0D - * control method external declarations with the associated method=0D= - * argument counts. Each line of the file must be of the form:=0D - * External (, MethodObj, )=0D - * Invocation:=0D - * iasl -fe refs.txt -d dsdt.aml=0D - *=0D - * The following methods were unresolved and many not compile proper= ly=0D - * because the disassembler had to guess at the number of arguments=0D= - * required for each:=0D - */=0D - External (_SB_.PCI0.S19_.PCNT, MethodObj) // Warning: Unknown met= hod, guessing 1 arguments=0D -=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D Method (DBUG, 1, NotSerialized)=0D {=0D ToHexString (Arg0, Local0)=0D ToBuffer (Local0, Local0)=0D Local1 =3D (SizeOf (Local0) - One)=0D Local2 =3D Zero=0D While ((Local2 < Local1))=0D {=0D @@ -3322,24 +3300,60 @@=0D Method (DVNT, 2, NotSerialized)=0D {=0D If ((Arg0 & One))=0D {=0D Notify (S00, Arg1)=0D }=0D }=0D =0D Method (PCNT, 0, NotSerialized)=0D {=0D BNUM =3D One=0D DVNT (PCIU, One)=0D DVNT (PCID, 0x03)=0D }=0D }=0D =0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D - ^S19.PCNT (^S10.PCNT ())=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: a8339e07f94a47f99560baef59d65a9e039aaf45=0D https://github.com/qemu/qemu/commit/a8339e07f94a47f99560baef59d65a9= e039aaf45=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D =0D We added a new unit test for testing acpi hotplug on multifunction bridge= s in=0D q35 machines. Here, we update the DSDT table gloden master blob for this = unit=0D test.=0D =0D The test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D Following is the ASL diff between the original DSDT table and the modifie= d DSDT=0D table due to the unit test. We see that multifunction bridge on bus 2 and= single=0D function bridge on bus 3 function 1 are described, not the non-bridge bal= loon=0D device on bus 4, function 2.=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Thu Oct 7 18:29:19 2021=0D + * Disassembly of /tmp/aml-C7JCA1, Thu Oct 7 18:29:19 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x00002061 (8289)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xF9=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -3265,23 +3265,95 @@=0D Method (_S1D, 0, NotSerialized) // _S1D: S1 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S2D, 0, NotSerialized) // _S2D: S2 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S3D, 0, NotSerialized) // _S3D: S3 Device Stat= e=0D {=0D Return (Zero)=0D }=0D }=0D =0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + Name (BSEL, One)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D One=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: afc9fcde55296b83f659de9da3cdf044812a6eeb=0D https://github.com/qemu/qemu/commit/afc9fcde55296b83f659de9da3cdf04= 4812a6eeb=0D Author: Richard Henderson =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D M hw/net/vhost_net-stub.c=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M hw/pci/pci_bridge.c=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D M hw/virtio/trace-events=0D A hw/virtio/vhost-user-rng-pci.c=0D A hw/virtio/vhost-user-rng.c=0D M hw/virtio/vhost-user.c=0D M hw/virtio/vhost-vdpa.c=0D M hw/virtio/virtio-iommu-pci.c=0D A include/hw/virtio/vhost-user-rng.h=0D M include/hw/virtio/vhost-vdpa.h=0D M include/hw/virtio/vhost.h=0D M include/hw/virtio/virtio-iommu.h=0D M include/hw/virtio/virtio-net.h=0D M include/net/net.h=0D M include/net/vhost_net.h=0D M meson.build=0D M net/net.c=0D M net/vhost-vdpa.c=0D M softmmu/qdev-monitor.c=0D M subprojects/libvhost-user/libvhost-user.c=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DMAR.dmar=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/IVRS.ivrs=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/data/acpi/rebuild-expected-aml.sh=0D M tests/qtest/acpi-utils.c=0D M tests/qtest/arm-cpu-features.c=0D M tests/qtest/bios-tables-test.c=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D M tests/qtest/migration-test.c=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes, tests=0D =0D vhost user rng=0D vdpa multiqueue=0D Fixes, cleanups, new tests all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Wed 20 Oct 2021 03:18:24 AM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (44 commits)=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D pci: fix PCI resource reserve capability on BE=0D vhost-vdpa: multiqueue support=0D virtio-net: vhost control virtqueue support=0D vhost: record the last virtqueue index for the virtio device=0D virtio-net: use "queue_pairs" instead of "queues" when possible=0D vhost-net: control virtqueue support=0D net: introduce control client=0D vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState *=0D vhost-vdpa: prepare for the multiqueue support=0D vhost-vdpa: classify one time request=0D vhost-vdpa: open device fd in net_init_vhost_vdpa()=0D bios-tables-test: don't disassemble empty files=0D rebuild-expected-aml.sh: allow partial target list=0D qdev/qbus: remove failover specific code=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D failover: fix a regression introduced by JSON'ification of -device=0D vhost-user: fix duplicated notifier MR init=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/3f2755e24da8...afc9fcde5529= =0D From MAILER-DAEMON Wed Oct 20 13:56:11 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdFox-0004jH-EJ for mharc-qemu-commits@gnu.org; Wed, 20 Oct 2021 13:56:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdFoo-0004hN-G6 for qemu-commits@nongnu.org; Wed, 20 Oct 2021 13:56:03 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:49155 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdFog-0002Qv-AK for qemu-commits@nongnu.org; Wed, 20 Oct 2021 13:55:59 -0400 Received: from github.com (hubbernetes-node-24be4a4.va3-iad.github.net [10.48.206.55]) by smtp.github.com (Postfix) with ESMTPA id 8C66E5C0748 for ; Wed, 20 Oct 2021 10:55:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634752553; bh=q0sW3ddktdYpoyjBlAR0WRVzk+HbKxSL/n/E9PLqKgk=; h=Date:From:To:Subject:From; b=aVdVPrXV+xLoSPmF7iwHI1vl6Js2sQyQolLtxy27EP9B3KtpSkHK3fNEF4RryK0vl P7GedgjqeuTUsWjm+S/s03iEtEXRJZlu5liIdvbu5j2vCsStni7erwrwGnZ9gxMSG8 WdI77zeTJ4QxieD8phS7O+Q9/qx93vwO0ltg079I= Date: Wed, 20 Oct 2021 10:55:53 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HEXHASH_WORD=1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 685db1: tests: acpi: dump table with failed checksum X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Oct 2021 17:56:04 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 685db13a38f7599fabd353382ff65d3c244ea641=0D https://github.com/qemu/qemu/commit/685db13a38f7599fabd353382ff65d3= c244ea641=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/acpi-utils.c=0D =0D Log Message:=0D -----------=0D tests: acpi: dump table with failed checksum=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-2-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: e741aff0f43343d6d91242fee1072fee376d5cce=0D https://github.com/qemu/qemu/commit/e741aff0f43343d6d91242fee1072fe= e376d5cce=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M meson.build=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D =0D Log Message:=0D -----------=0D tests: qtest: add qtest_has_accel() to check if tested binary supports = accelerator=0D =0D Currently it is not possible to create tests that have KVM as a hard=0D requirement on a host that doesn't support KVM for tested target=0D binary (modulo going through the trouble of compiling out=0D the offending test case).=0D =0D Following scenario makes test fail when it's run on non x86 host:=0D qemu-system-x86_64 -enable-kvm -M q35,kernel-irqchip=3Don -smp 1,maxcpu= s=3D288=0D =0D This patch introduces qtest_has_accel() to let users check if accel is=0D= available in advance and avoid executing non run-able test-cases.=0D =0D It implements detection of TCG and KVM only, the rest could be=0D added later on, when we actually start testing them in qtest.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-3-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c306cdb0cc5327f336fbf9a7411f319f0717ee75=0D https://github.com/qemu/qemu/commit/c306cdb0cc5327f336fbf9a7411f319= f0717ee75=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected tables for acpi/q35/xapic testcase=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-4-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 80a2f3387c239d06d4a4b6838b511a88838ddc0f=0D https://github.com/qemu/qemu/commit/80a2f3387c239d06d4a4b6838b511a8= 8838ddc0f=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: q35: test for x2APIC entries in SRAT=0D =0D Set -smp 1,maxcpus=3D288 to test for ACPI code that=0D deal with CPUs with large APIC ID (>255).=0D =0D PS:=0D Test requires KVM and in-kernel irqchip support,=0D so skip test if KVM is not available.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-5-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b59a898458aea328618521be7dc180d2396c0bf4=0D https://github.com/qemu/qemu/commit/b59a898458aea328618521be7dc180d= 2396c0bf4=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/APIC.xapic=0D M tests/data/acpi/q35/DSDT.xapic=0D M tests/data/acpi/q35/FACP.xapic=0D M tests/data/acpi/q35/SRAT.xapic=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected tables blobs=0D =0D Update adds CPU entries to MADT/SRAT/FACP and DSDT to cover 288 CPUs.=0D Notable changes are that CPUs with APIC ID 255 and higher=0D use 'Processor Local x2APIC Affinity' structure in SRAT and=0D "Device" element in DSDT.=0D =0D FACP:=0D - Use APIC Cluster Model (V4) : 0=0D + Use APIC Cluster Model (V4) : 1=0D =0D SRAT:=0D ...=0D +[1010h 4112 1] Subtable Type : 00 [Processor Local APIC= /SAPIC Affinity]=0D +[1011h 4113 1] Length : 10=0D +=0D +[1012h 4114 1] Proximity Domain Low(8) : 00=0D +[1013h 4115 1] Apic ID : FE=0D +[1014h 4116 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1018h 4120 1] Local Sapic EID : 00=0D +[1019h 4121 3] Proximity Domain High(24) : 000000=0D +[101Ch 4124 4] Clock Domain : 00000000=0D +=0D +[1020h 4128 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1021h 4129 1] Length : 18=0D +=0D +[1022h 4130 2] Reserved1 : 0000=0D +[1024h 4132 4] Proximity Domain : 00000001=0D +[1028h 4136 4] Apic ID : 000000FF=0D +[102Ch 4140 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1030h 4144 4] Clock Domain : 00000000=0D +[1034h 4148 4] Reserved2 : 00000000=0D =0D ...=0D =0D +[1320h 4896 1] Subtable Type : 02 [Processor Local x2AP= IC Affinity]=0D +[1321h 4897 1] Length : 18=0D +=0D +[1322h 4898 2] Reserved1 : 0000=0D +[1324h 4900 4] Proximity Domain : 00000001=0D +[1328h 4904 4] Apic ID : 0000011F=0D +[132Ch 4908 4] Flags (decoded below) : 00000001=0D + Enabled : 1=0D +[1330h 4912 4] Clock Domain : 00000000=0D +[1334h 4916 4] Reserved2 : 00000000=0D =0D DSDT:=0D =0D ...=0D + Processor (C0FE, 0xFE, 0x00000000, 0x00)=0D + {=0D ...=0D + }=0D +=0D + Device (C0FF)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0xFF) // _UID: Unique ID=0D ...=0D + }=0D =0D + Device (C11F)=0D + {=0D + Name (_HID, "ACPI0007" /* Processor Device */) // _HID:= Hardware ID=0D + Name (_UID, 0x011F) // _UID: Unique ID=0D ...=0D + }=0D =0D APIC:=0D +[034h 0052 1] Subtable Type : 00 [Processor Local APIC]= =0D +[035h 0053 1] Length : 08=0D +[036h 0054 1] Processor ID : 01=0D +[037h 0055 1] Local Apic ID : 01=0D +[038h 0056 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D =0D ...=0D =0D +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC]= =0D +[81Dh 2077 1] Length : 08=0D +[81Eh 2078 1] Processor ID : FE=0D +[81Fh 2079 1] Local Apic ID : FE=0D +[820h 2080 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +=0D +[824h 2084 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[825h 2085 1] Length : 10=0D +[826h 2086 2] Reserved : 0000=0D +[828h 2088 4] Processor x2Apic ID : 000000FF=0D +[82Ch 2092 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[830h 2096 4] Processor UID : 000000FF=0D =0D ...=0D =0D +[A24h 2596 1] Subtable Type : 09 [Processor Local x2API= C]=0D +[A25h 2597 1] Length : 10=0D +[A26h 2598 2] Reserved : 0000=0D +[A28h 2600 4] Processor x2Apic ID : 0000011F=0D +[A2Ch 2604 4] Flags (decoded below) : 00000000=0D + Processor Enabled : 0=0D +[A30h 2608 4] Processor UID : 0000011F=0D +=0D +[A34h 2612 1] Subtable Type : 01 [I/O APIC]=0D +[A35h 2613 1] Length : 0C=0D +[A36h 2614 1] I/O Apic ID : 00=0D +[A37h 2615 1] Reserved : 00=0D +[A38h 2616 4] Address : FEC00000=0D +[A3Ch 2620 4] Interrupt : 00000000=0D +=0D +[A40h 2624 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A41h 2625 1] Length : 0A=0D +[A42h 2626 1] Bus : 00=0D +[A43h 2627 1] Source : 00=0D +[A44h 2628 4] Interrupt : 00000002=0D +[A48h 2632 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D =0D -[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[04Bh 0075 1] Length : 0A=0D -[04Ch 0076 1] Bus : 00=0D -[04Dh 0077 1] Source : 05=0D -[04Eh 0078 4] Interrupt : 00000005=0D -[052h 0082 2] Flags (decoded below) : 000D=0D +[A4Ah 2634 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A4Bh 2635 1] Length : 0A=0D +[A4Ch 2636 1] Bus : 00=0D +[A4Dh 2637 1] Source : 05=0D +[A4Eh 2638 4] Interrupt : 00000005=0D +[A52h 2642 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[054h 0084 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[055h 0085 1] Length : 0A=0D -[056h 0086 1] Bus : 00=0D -[057h 0087 1] Source : 09=0D -[058h 0088 4] Interrupt : 00000009=0D -[05Ch 0092 2] Flags (decoded below) : 000D=0D +[A54h 2644 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A55h 2645 1] Length : 0A=0D +[A56h 2646 1] Bus : 00=0D +[A57h 2647 1] Source : 09=0D +[A58h 2648 4] Interrupt : 00000009=0D +[A5Ch 2652 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[05Fh 0095 1] Length : 0A=0D -[060h 0096 1] Bus : 00=0D -[061h 0097 1] Source : 0A=0D -[062h 0098 4] Interrupt : 0000000A=0D -[066h 0102 2] Flags (decoded below) : 000D=0D +[A5Eh 2654 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A5Fh 2655 1] Length : 0A=0D +[A60h 2656 1] Bus : 00=0D +[A61h 2657 1] Source : 0A=0D +[A62h 2658 4] Interrupt : 0000000A=0D +[A66h 2662 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[068h 0104 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D -[069h 0105 1] Length : 0A=0D -[06Ah 0106 1] Bus : 00=0D -[06Bh 0107 1] Source : 0B=0D -[06Ch 0108 4] Interrupt : 0000000B=0D -[070h 0112 2] Flags (decoded below) : 000D=0D +[A68h 2664 1] Subtable Type : 02 [Interrupt Source Over= ride]=0D +[A69h 2665 1] Length : 0A=0D +[A6Ah 2666 1] Bus : 00=0D +[A6Bh 2667 1] Source : 0B=0D +[A6Ch 2668 4] Interrupt : 0000000B=0D +[A70h 2672 2] Flags (decoded below) : 000D=0D Polarity : 1=0D Trigger Mode : 3=0D =0D -[072h 0114 1] Subtable Type : 04 [Local APIC NMI]=0D -[073h 0115 1] Length : 06=0D -[074h 0116 1] Processor ID : FF=0D -[075h 0117 2] Flags (decoded below) : 0000=0D +[A72h 2674 1] Subtable Type : 0A [Local x2APIC NMI]=0D +[A73h 2675 1] Length : 0C=0D +[A74h 2676 2] Flags (decoded below) : 0000=0D Polarity : 0=0D Trigger Mode : 0=0D -[077h 0119 1] Interrupt Input LINT : 01=0D +[A76h 2678 4] Processor UID : FFFFFFFF=0D +[A7Ah 2682 1] Interrupt Input LINT : 01=0D +[A7Bh 2683 3] Reserved : 000000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-6-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: f6826ac4ae2dea392a69fe1ca870a8a27e2bf0ac=0D https://github.com/qemu/qemu/commit/f6826ac4ae2dea392a69fe1ca870a8a= 27e2bf0ac=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist new expected table tests/data/acpi/q35/DMAR.dmar= =0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-7-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0ff92b6d99011c8de57321503c0eb655c461a217=0D https://github.com/qemu/qemu/commit/0ff92b6d99011c8de57321503c0eb65= 5c461a217=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for intel_iommu (DMAR table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-8-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 44d3bdd8a6f1ae2a5ca417251736a033900d4c08=0D https://github.com/qemu/qemu/commit/44d3bdd8a6f1ae2a5ca417251736a03= 3900d4c08=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DMAR.dmar=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: add expected blob for DMAR table=0D =0D [000h 0000 4] Signature : "DMAR" [DMA Remapping t= able]=0D [004h 0004 4] Table Length : 00000078=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 15=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 1] Host Address Width : 26=0D [025h 0037 1] Flags : 01=0D [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00= 00=0D =0D [030h 0048 2] Subtable Type : 0000 [Hardware Unit Defini= tion]=0D [032h 0050 2] Length : 0040=0D =0D [034h 0052 1] Flags : 00=0D [035h 0053 1] Reserved : 00=0D [036h 0054 2] PCI Segment Number : 0000=0D [038h 0056 8] Register Base Address : 00000000FED90000=0D =0D [040h 0064 1] Device Scope Type : 03 [IOAPIC Device]=0D [041h 0065 1] Entry Length : 08=0D [042h 0066 2] Reserved : 0000=0D [044h 0068 1] Enumeration ID : 00=0D [045h 0069 1] PCI Bus Number : FF=0D =0D [046h 0070 2] PCI Path : 00,00=0D =0D [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [049h 0073 1] Entry Length : 08=0D [04Ah 0074 2] Reserved : 0000=0D [04Ch 0076 1] Enumeration ID : 00=0D [04Dh 0077 1] PCI Bus Number : 00=0D =0D [04Eh 0078 2] PCI Path : 00,00=0D =0D [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [051h 0081 1] Entry Length : 08=0D [052h 0082 2] Reserved : 0000=0D [054h 0084 1] Enumeration ID : 00=0D [055h 0085 1] PCI Bus Number : 00=0D =0D [056h 0086 2] PCI Path : 01,00=0D =0D [058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [059h 0089 1] Entry Length : 08=0D [05Ah 0090 2] Reserved : 0000=0D [05Ch 0092 1] Enumeration ID : 00=0D [05Dh 0093 1] PCI Bus Number : 00=0D =0D [05Eh 0094 2] PCI Path : 1F,00=0D =0D [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [061h 0097 1] Entry Length : 08=0D [062h 0098 2] Reserved : 0000=0D [064h 0100 1] Enumeration ID : 00=0D [065h 0101 1] PCI Bus Number : 00=0D =0D [066h 0102 2] PCI Path : 1F,02=0D =0D [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device]=0D= [069h 0105 1] Entry Length : 08=0D [06Ah 0106 2] Reserved : 0000=0D [06Ch 0108 1] Enumeration ID : 00=0D [06Dh 0109 1] PCI Bus Number : 00=0D =0D [06Eh 0110 2] PCI Path : 1F,03=0D =0D [070h 0112 2] Subtable Type : 0002 [Root Port ATS Capabi= lity]=0D [072h 0114 2] Length : 0008=0D =0D [074h 0116 1] Flags : 01=0D [075h 0117 1] Reserved : 00=0D [076h 0118 2] PCI Segment Number : 0000=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-9-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c5a7baad2997091c48ec40a2a8efa63f18f9b3b7=0D https://github.com/qemu/qemu/commit/c5a7baad2997091c48ec40a2a8efa63= f18f9b3b7=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: whitelist expected blobs for new acpi/q35/ivrs testcase=0D= =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-10-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a4c730cbb284479ec2f7799bbbd7521525553593=0D https://github.com/qemu/qemu/commit/a4c730cbb284479ec2f7799bbbd7521= 525553593=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: add testcase for amd-iommu (IVRS table)=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-11-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: ef422a14226fd0078bdf61657fdd63099cb49099=0D https://github.com/qemu/qemu/commit/ef422a14226fd0078bdf61657fdd630= 99cb49099=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.ivrs=0D M tests/data/acpi/q35/IVRS.ivrs=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests: acpi: update expected blobs=0D =0D DSDT:=0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + }=0D =0D New IVRS table:=0D =0D [000h 0000 4] Signature : "IVRS" [I/O Virtualizat= ion Reporting Structure]=0D [004h 0004 4] Table Length : 00000068=0D [008h 0008 1] Revision : 01=0D [009h 0009 1] Checksum : 43=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 4] Virtualization Info : 00002800=0D [028h 0040 8] Reserved : 0000000000000000=0D =0D [030h 0048 1] Subtable Type : 10 [Hardware Definition Bl= ock]=0D [031h 0049 1] Flags : D1=0D [032h 0050 2] Length : 0038=0D [034h 0052 2] DeviceId : 0010=0D =0D [036h 0054 2] Capability Offset : 0040=0D [038h 0056 8] Base Address : 00000000FED80000=0D [040h 0064 2] PCI Segment Group : 0000=0D [042h 0066 2] Virtualization Info : 0000=0D [044h 0068 4] Reserved : 00000044=0D =0D [048h 0072 1] Entry Type : 02=0D [049h 0073 2] Device ID : 0000=0D [04Bh 0075 1] Data Setting : 00=0D =0D [04Ch 0076 1] Entry Type : 02=0D [04Dh 0077 2] Device ID : 0008=0D [04Fh 0079 1] Data Setting : 00=0D =0D [050h 0080 1] Entry Type : 02=0D [051h 0081 2] Device ID : 0010=0D [053h 0083 1] Data Setting : 00=0D =0D [054h 0084 1] Entry Type : 02=0D [055h 0085 2] Device ID : 00F8=0D [057h 0087 1] Data Setting : 00=0D =0D [058h 0088 1] Entry Type : 02=0D [059h 0089 2] Device ID : 00FA=0D [05Bh 0091 1] Data Setting : 00=0D =0D [05Ch 0092 1] Entry Type : 02=0D [05Dh 0093 2] Device ID : 00FB=0D [05Fh 0095 1] Data Setting : 00=0D =0D [060h 0096 1] Entry Type : 48=0D [061h 0097 2] Device ID : 0000=0D [063h 0099 1] Data Setting : 00=0D [064h 0100 1] Handle : 00=0D [065h 0101 2] Source Used Device ID : 00A0=0D [067h 0103 1] Variety : 01=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-12-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 709611cb23cc677fa0c2d4de76a21c24baefe9a0=0D https://github.com/qemu/qemu/commit/709611cb23cc677fa0c2d4de76a21c2= 4baefe9a0=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: acpi: arm/virt: drop redundant test_acpi_one() in test_acpi_virt= _tcg()=0D =0D follow up call with smbios options generates the same ACPI tables,=0D so there is no need to run smbios-less variant at all.=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-13-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 07e6ed2c79b311aad4d2c87740753752ad1503ba=0D https://github.com/qemu/qemu/commit/07e6ed2c79b311aad4d2c8774075375= 2ad1503ba=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/arm-cpu-features.c=0D =0D Log Message:=0D -----------=0D tests: arm-cpu-features: use qtest_has_kvm() API=0D =0D and drop custom function that were doing the job=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-14-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: b72c76033de766d4ff891c582514caf12edbbfb4=0D https://github.com/qemu/qemu/commit/b72c76033de766d4ff891c582514caf= 12edbbfb4=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/migration-test.c=0D =0D Log Message:=0D -----------=0D tests: migration-test: use qtest_has_accel() API=0D =0D Signed-off-by: Igor Mammedov =0D Suggested-by: Thomas Huth =0D Message-Id: <20210902113551.461632-15-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 220ffd949bf2c157665905f7744bdbf201333e1f=0D https://github.com/qemu/qemu/commit/220ffd949bf2c157665905f7744bdbf= 201333e1f=0D Author: Igor Mammedov =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests: bios-tables-test: use qtest_has_accel() API to register TCG only= tests=0D =0D .. only if TCG is available=0D =0D Signed-off-by: Igor Mammedov =0D Message-Id: <20210902113551.461632-16-imammedo@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c64038c93e171697058d96871f87a4438b613662=0D https://github.com/qemu/qemu/commit/c64038c93e171697058d96871f87a44= 38b613662=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Skip protected ram IOMMU mappings=0D =0D Following the logic of commit 56918a126ae ("memory: Add RAM_PROTECTED=0D flag to skip IOMMU mappings") with VFIO, skip memory sections=0D inaccessible via normal mechanisms, including DMA.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-2-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 032e4d686e9c6f8ae3b9206c720ae3614e28d8a3=0D https://github.com/qemu/qemu/commit/032e4d686e9c6f8ae3b9206c720ae36= 14e28d8a3=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vdpa: Add vhost_vdpa_section_end=0D =0D Abstract this operation, that will be reused when validating the region=0D= against the iova range that the device supports.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Acked-by: Jason Wang =0D Message-Id: <20211014141236.923287-3-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 013108b6e51e1c10b78859e2e091202364aa7a7d=0D https://github.com/qemu/qemu/commit/013108b6e51e1c10b78859e2e091202= 364aa7a7d=0D Author: Eugenio P=C3=A9rez =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/trace-events=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vdpa: Check for iova range at mappings changes=0D =0D Check vdpa device range before updating memory regions so we don't add=0D= any outside of it, and report the invalid change if any.=0D =0D Signed-off-by: Eugenio P=C3=A9rez =0D Message-Id: <20211014141236.923287-4-eperezma@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Jason Wang =0D Reviewed-by: Stefano Garzarella =0D =0D =0D Commit: 819bbda81fd6a08bea79d56a6ca27092ec29719b=0D https://github.com/qemu/qemu/commit/819bbda81fd6a08bea79d56a6ca2709= 2ec29719b=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D =0D Log Message:=0D -----------=0D virtio-iommu: Remove the non transitional name=0D =0D Remove the non transitional name for virtio iommu. Like other=0D devices introduced after 1.0 spec, the virtio-iommu does=0D not need it.=0D =0D Signed-off-by: Eric Auger =0D Reported-by: Andrea Bolognani =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-2-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 19d20e910a586f503994acf590d5f41c314fa4c3=0D https://github.com/qemu/qemu/commit/19d20e910a586f503994acf590d5f41= c314fa4c3=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/virtio-iommu-pci.c=0D M include/hw/virtio/virtio-iommu.h=0D =0D Log Message:=0D -----------=0D virtio-iommu: Drop base_name and change generic_name=0D =0D Drop base_name and turn generic_name into=0D "virtio-iommu-pci". This is more in line with=0D other modern-only devices.=0D =0D Signed-off-by: Eric Auger =0D Suggested-by: Cornelia Huck =0D Reviewed-by: Cornelia Huck =0D Message-Id: <20211013191755.767468-3-eric.auger@redhat.com>=0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 6889eb2d431ae962e3e083b57bff47cd573cb1c4=0D https://github.com/qemu/qemu/commit/6889eb2d431ae962e3e083b57bff47c= d573cb1c4=0D Author: David Hildenbrand =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M subprojects/libvhost-user/libvhost-user.c=0D =0D Log Message:=0D -----------=0D libvhost-user: fix VHOST_USER_REM_MEM_REG skipping mmap_addr=0D =0D We end up not copying the mmap_addr of all existing regions, resulting=0D= in a SEGFAULT once we actually try to map/access anything within our=0D memory regions.=0D =0D Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user")=0D= Cc: qemu-stable@nongnu.org=0D Cc: Michael S. Tsirkin =0D Cc: Raphael Norwitz =0D Cc: "Marc-Andr=C3=A9 Lureau" =0D Cc: Stefan Hajnoczi =0D Cc: Paolo Bonzini =0D Cc: Coiby Xu =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20211011201047.62587-1-david@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Raphael Norwitz =0D Reviewed-by: Stefan Hajnoczi =0D =0D =0D Commit: 821d28b88f850e5fbc66ee62bdd155eb2d474a29=0D https://github.com/qemu/qemu/commit/821d28b88f850e5fbc66ee62bdd155e= b2d474a29=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng.c=0D A include/hw/virtio/vhost-user-rng.h=0D =0D Log Message:=0D -----------=0D vhost-user-rng: Add vhost-user-rng implementation=0D =0D Introduce a random number generator (RNG) backend that communicates=0D with a vhost-user server to retrieve entropy. That way other VMM=0D that comply with the vhost user protocl can use the same vhost-user=0D daemon without having to write yet another RNG driver.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-2-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c7160fff7d48cead5d673ef2032b60c363c84e27=0D https://github.com/qemu/qemu/commit/c7160fff7d48cead5d673ef2032b60c= 363c84e27=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/meson.build=0D A hw/virtio/vhost-user-rng-pci.c=0D =0D Log Message:=0D -----------=0D vhost-user-rng-pci: Add vhost-user-rng-pci implementation=0D =0D This patch provides a PCI bus interface to the vhost-user-rng backend.=0D= =0D Reviewed-by: Alex Benn=C3=A9e =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-3-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: c47d4fa0c8f0a28614cc0ce849dc9bbaa5c6878f=0D https://github.com/qemu/qemu/commit/c47d4fa0c8f0a28614cc0ce849dc9bb= aa5c6878f=0D Author: Mathieu Poirier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D =0D Log Message:=0D -----------=0D docs: Add documentation for vhost based RNG implementation=0D =0D Add description and example for the vhost-user based RNG implementation.=0D= =0D Signed-off-by: Mathieu Poirier =0D Message-Id: <20211012205904.4106769-4-mathieu.poirier@linaro.org>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: a1ed9ef1de87c3e86ff68589604298ec90875a14=0D https://github.com/qemu/qemu/commit/a1ed9ef1de87c3e86ff68589604298e= c90875a14=0D Author: Xueming Li =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-user.c=0D =0D Log Message:=0D -----------=0D vhost-user: fix duplicated notifier MR init=0D =0D In case of device resume after suspend, VQ notifier MR still valid.=0D Duplicated registrations explode memory block list and slow down device=0D= resume.=0D =0D Fixes: 44866521bd6e ("vhost-user: support registering external host notif= iers")=0D Cc: tiwei.bie@intel.com=0D Cc: qemu-stable@nongnu.org=0D Cc: Yuwei Zhang =0D =0D Signed-off-by: Xueming Li =0D Message-Id: <20211008080215.590292-1-xuemingl@nvidia.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7fe7791e3f652ac31ef98dcc94a8f2a317ab846b=0D https://github.com/qemu/qemu/commit/7fe7791e3f652ac31ef98dcc94a8f2a= 317ab846b=0D Author: Laurent Vivier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D =0D Log Message:=0D -----------=0D failover: fix a regression introduced by JSON'ification of -device=0D =0D The hide_device helper can be called several times for the same=0D devices as it shouldn't change any state and should only return an=0D information.=0D =0D But not to rely anymore on QemuOpts we have introduced a new field=0D to store the parameters of the device and don't allow to update it=0D once it is done.=0D =0D And as the function is called several times, we ends with:=0D =0D warning: Cannot attach more than one primary device to 'virtio0'=0D =0D That is not only a warning as it prevents to hide the device and breaks=0D= failover.=0D =0D Fix that by checking the device id.=0D =0D Now, we fail only if the virtio-net device is really used by two differen= t=0D devices, for instance:=0D =0D -device virtio-net-pci,id=3Dvirtio0,failover=3Don,... \=0D -device vfio-pci,id=3Dhostdev0,failover_pair_id=3Dvirtio0,... \=0D -device e1000e,id=3De1000e0,failover_pair_id=3Dvirtio0,... \=0D =0D will exit with:=0D =0D Cannot attach more than one primary device to 'virtio0': 'hostdev0' and= 'e1000e0'=0D =0D Fixes: 259a10dbcb4f ("virtio-net: Store failover primary opts pointer loc= ally")=0D Cc: kwolf@redhat.com=0D Signed-off-by: Laurent Vivier =0D Message-Id: <20211019071532.682717-2-lvivier@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Kevin Wolf =0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 515efffc2fd0928317a0a1ec47b28a972c40ddad=0D https://github.com/qemu/qemu/commit/515efffc2fd0928317a0a1ec47b28a9= 72c40ddad=0D Author: Stefan Hajnoczi =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D =0D qemu-storage-daemon is launched with the vhost-user listen socket path.=0D= The path is first unlinked before opening the listen socket. This=0D prevents stale UNIX domain socket files from stopping socket=0D initialization.=0D =0D This behavior is undesirable in vhost-user-blk-test and the cause of a=0D= bug:=0D =0D There is a race condition in vhost-user-blk-test when QEMU launches=0D before QSD. It connects to the old socket that QSD unlinks and the=0D vhost-user connection is never serviced, resulting in a hang.=0D =0D Pass the listen socket fd to QSD to maintain listen socket continuity=0D and prevent the lost connection.=0D =0D Fixes: 806952026df41939680abe92b329715b9b4e01cc ("test: new qTest case to= test the vhost-user-blk-server")=0D Cc: Raphael Norwitz =0D Cc: Michael S. Tsirkin =0D Cc: Thomas Huth =0D Cc: Coiby Xu =0D Signed-off-by: Stefan Hajnoczi =0D Message-Id: <20211019135655.83067-1-stefanha@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: bcfc906be47a88803307cd6b665dc4c26fdd6dd2=0D https://github.com/qemu/qemu/commit/bcfc906be47a88803307cd6b665dc4c= 26fdd6dd2=0D Author: Laurent Vivier =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/virtio-net.c=0D M softmmu/qdev-monitor.c=0D =0D Log Message:=0D -----------=0D qdev/qbus: remove failover specific code=0D =0D Commit f3a850565693 ("qdev/qbus: add hidden device support") has=0D introduced a generic way to hide a device but it has modified=0D qdev_device_add() to check a specific option of the failover device,=0D "failover_pair_id", before calling the generic mechanism.=0D =0D It's not needed (and not generic) to do that in qdev_device_add() because= =0D this is also checked by the failover_hide_primary_device() function that=0D= uses the generic mechanism to hide the device.=0D =0D Cc: Jens Freimann =0D Signed-off-by: Laurent Vivier =0D Message-Id: <20211019071532.682717-3-lvivier@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 71352aa95bf49d7a0ddab4e685147974c32ebc2c=0D https://github.com/qemu/qemu/commit/71352aa95bf49d7a0ddab4e68514797= 4c32ebc2c=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/rebuild-expected-aml.sh=0D =0D Log Message:=0D -----------=0D rebuild-expected-aml.sh: allow partial target list=0D =0D Only rebuild AML for configured targets.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 81d7228647e0bd17d4f4f0434b8ed410fe5f7497=0D https://github.com/qemu/qemu/commit/81d7228647e0bd17d4f4f0434b8ed41= 0fe5f7497=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D bios-tables-test: don't disassemble empty files=0D =0D A recommended way to populate new tables is to have an=0D empty expected file. In this case, attempts to disassemble=0D will fail but it is useful to disassemble the actual files.=0D Detect and skip decompile step in this case.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 7327813d17086fadabe3b27ba2d9737c8a33c5b0=0D https://github.com/qemu/qemu/commit/7327813d17086fadabe3b27ba2d9737= c8a33c5b0=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: open device fd in net_init_vhost_vdpa()=0D =0D This patch switches to open device fd in net_init_vhost_vpda(). This is=0D= used to prepare for the multiqueue support.=0D =0D Reviewed-by: Stefano Garzarella =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-2-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 4d191cfdc7de958d06f821173f721c56bc131620=0D https://github.com/qemu/qemu/commit/4d191cfdc7de958d06f821173f721c5= 6bc131620=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M include/hw/virtio/vhost-vdpa.h=0D =0D Log Message:=0D -----------=0D vhost-vdpa: classify one time request=0D =0D Vhost-vdpa uses one device multiqueue queue (pairs) model. So we need=0D to classify the one time request (e.g SET_OWNER) and make sure those=0D request were only called once per device.=0D =0D This is used for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-3-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 353244d8b96767659e6c95c0c87dfe4372fe8c12=0D https://github.com/qemu/qemu/commit/353244d8b96767659e6c95c0c87dfe4= 372fe8c12=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: prepare for the multiqueue support=0D =0D Unlike vhost-kernel, vhost-vdpa adapts a single device multiqueue=0D model. So we need to simply use virtqueue index as the vhost virtqueue=0D= index. This is a must for multiqueue to work for vhost-vdpa.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-4-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 654790b65b8435a7d409b1873b566e8db9e91b9b=0D https://github.com/qemu/qemu/commit/654790b65b8435a7d409b1873b566e8= db9e91b9b=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState *=0D =0D This patch switches to let net_vhost_vdpa_init() to return=0D NetClientState *. This is used for the callers to allocate multiqueue=0D NetClientState for multiqueue support.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-5-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 2f849dbdb2ab2c70715520a8129524f197b9a8ba=0D https://github.com/qemu/qemu/commit/2f849dbdb2ab2c70715520a8129524f= 197b9a8ba=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M include/net/net.h=0D M net/net.c=0D =0D Log Message:=0D -----------=0D net: introduce control client=0D =0D This patch introduces a boolean for the device has control queue which=0D= can accepts control command via network queue.=0D =0D The first user would be the control virtqueue support for vhost.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-6-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 05ba3f63d174a716b42aa31c9af5d0ef64fff515=0D https://github.com/qemu/qemu/commit/05ba3f63d174a716b42aa31c9af5d0e= f64fff515=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net-stub.c=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/net/vhost_net.h=0D =0D Log Message:=0D -----------=0D vhost-net: control virtqueue support=0D =0D We assume there's no cvq in the past, this is not true when we need=0D control virtqueue support for vhost-user backends. So this patch=0D implements the control virtqueue support for vhost-net. As datapath,=0D the control virtqueue is also required to be coupled with the=0D NetClientState. The vhost_net_start/stop() are tweaked to accept the=0D number of datapath queue pairs plus the the number of control=0D virtqueue for us to start and stop the vhost device.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-7-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 441537f1ce0153978b4c9ee1cc4d4152147aa16f=0D https://github.com/qemu/qemu/commit/441537f1ce0153978b4c9ee1cc4d415= 2147aa16f=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: use "queue_pairs" instead of "queues" when possible=0D =0D Most of the time, "queues" really means queue pairs. So this patch=0D switch to use "queue_pairs" to avoid confusion.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-8-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 049eb15b5fc9c54ae76254a196b695000127da7a=0D https://github.com/qemu/qemu/commit/049eb15b5fc9c54ae76254a196b6950= 00127da7a=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M include/hw/virtio/vhost.h=0D =0D Log Message:=0D -----------=0D vhost: record the last virtqueue index for the virtio device=0D =0D This patch introduces a new field in the vhost_dev structure to record=0D= the last virtqueue index for the virtio device. This will be useful=0D for the vhost backends with 1:N model to start or stop the device=0D after all the vhost_dev structures were started or stopped.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-9-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 22288fe5a3f2dc4cb5c8826646d466019ad67682=0D https://github.com/qemu/qemu/commit/22288fe5a3f2dc4cb5c8826646d4660= 19ad67682=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M include/hw/virtio/virtio-net.h=0D =0D Log Message:=0D -----------=0D virtio-net: vhost control virtqueue support=0D =0D This patch implements the control virtqueue support for vhost. This=0D requires virtio-net to figure out the datapath queue pairs and control=0D= virtqueue via is_datapath and pass the number of those two types=0D of virtqueues to vhost_net_start()/vhost_net_stop().=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-10-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 402378407dbdce79ce745a13f5c84815f929cfdd=0D https://github.com/qemu/qemu/commit/402378407dbdce79ce745a13f5c8481= 5f929cfdd=0D Author: Jason Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-vdpa.c=0D M net/vhost-vdpa.c=0D =0D Log Message:=0D -----------=0D vhost-vdpa: multiqueue support=0D =0D This patch implements the multiqueue support for vhost-vdpa. This is=0D done simply by reading the number of queue pairs from the config space=0D= and initialize the datapath and control path net client.=0D =0D Signed-off-by: Jason Wang =0D Message-Id: <20211020045600.16082-11-jasowang@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D =0D =0D Commit: 0e464f7d993113119f0fd17b890831440734ce15=0D https://github.com/qemu/qemu/commit/0e464f7d993113119f0fd17b8908314= 40734ce15=0D Author: Michael S. Tsirkin =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/pci/pci_bridge.c=0D =0D Log Message:=0D -----------=0D pci: fix PCI resource reserve capability on BE=0D =0D PCI resource reserve capability should use LE format as all other PCI=0D things. If we don't then seabios won't boot:=0D =0D =3D=3D=3D PCI new allocation pass #1 =3D=3D=3D=0D PCI: check devices=0D PCI: QEMU resource reserve cap: size 10000000000000 type io=0D PCI: secondary bus 1 size 10000000000000 type io=0D PCI: secondary bus 1 size 00200000 type mem=0D PCI: secondary bus 1 size 00200000 type prefmem=0D =3D=3D=3D PCI new allocation pass #2 =3D=3D=3D=0D PCI: out of I/O address space=0D =0D This became more important since we started reserving IO by default,=0D previously no one noticed.=0D =0D Fixes: e2a6290aab ("hw/pcie-root-port: Fix hotplug for PCI devices requir= ing IO")=0D Cc: marcel.apfelbaum@gmail.com=0D Fixes: 226263fb5c ("hw/pci: add QEMU-specific PCI capability to the Gener= ic PCI Express Root Port")=0D Cc: zuban32s@gmail.com=0D Fixes: 6755e618d0 ("hw/pci: add PCI resource reserve capability to legacy= PCI bridge")=0D Cc: jing2.liu@linux.intel.com=0D Tested-by: Thomas Huth =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 6dcb1cc9512c6b4cd8f85abc537abaf6f6c0738b=0D https://github.com/qemu/qemu/commit/6dcb1cc9512c6b4cd8f85abc537abaf= 6f6c0738b=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D =0D We are adding a new unit test to cover the acpi hotplug support in q35 fo= r=0D multi-function bridges. This test uses a new table DSDT.multi-bridge.=0D We need to allow changes in DSDT acpi table for addition of this new=0D unit test.=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-2-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: 04dd78b9e85720226a148eef54b45cb02b463034=0D https://github.com/qemu/qemu/commit/04dd78b9e85720226a148eef54b45cb= 02b463034=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test.c=0D =0D Log Message:=0D -----------=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D =0D commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunc= tion bridges")=0D added ACPI hotplug descriptions for cold plugged bridges for functions ot= her=0D than 0. For all other devices, the ACPI hotplug descriptions are limited = to=0D function 0 only. This change adds unit tests for this feature.=0D =0D This test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D The following diff compares the DSDT table AML with the new unit test bef= ore=0D and after the change d7346e614f4ec is introduced. In other words,=0D this diff reflects the changes that occurs in the DSDT table due to the c= hange=0D d7346e614f4ec .=0D =0D @@ -1,60 +1,38 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT.multi-bridge, Thu Oct 7 18:5= 6:05 2021=0D + * Disassembly of /tmp/aml-AN0DA1, Thu Oct 7 18:56:05 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x000020FE (8446)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xDE=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D - /*=0D - * iASL Warning: There was 1 external control method found during=0D= - * disassembly, but only 0 were resolved (1 unresolved). Additional=0D= - * ACPI tables may be required to properly disassemble the code. Thi= s=0D - * resulting disassembler output file may not compile because the=0D= - * disassembler did not know how many arguments to assign to the=0D - * unresolved methods. Note: SSDTs can be dynamically loaded at=0D - * runtime and may or may not be available via the host OS.=0D - *=0D - * In addition, the -fe option can be used to specify a file contain= ing=0D - * control method external declarations with the associated method=0D= - * argument counts. Each line of the file must be of the form:=0D - * External (, MethodObj, )=0D - * Invocation:=0D - * iasl -fe refs.txt -d dsdt.aml=0D - *=0D - * The following methods were unresolved and many not compile proper= ly=0D - * because the disassembler had to guess at the number of arguments=0D= - * required for each:=0D - */=0D - External (_SB_.PCI0.S19_.PCNT, MethodObj) // Warning: Unknown met= hod, guessing 1 arguments=0D -=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D Method (DBUG, 1, NotSerialized)=0D {=0D ToHexString (Arg0, Local0)=0D ToBuffer (Local0, Local0)=0D Local1 =3D (SizeOf (Local0) - One)=0D Local2 =3D Zero=0D While ((Local2 < Local1))=0D {=0D @@ -3322,24 +3300,60 @@=0D Method (DVNT, 2, NotSerialized)=0D {=0D If ((Arg0 & One))=0D {=0D Notify (S00, Arg1)=0D }=0D }=0D =0D Method (PCNT, 0, NotSerialized)=0D {=0D BNUM =3D One=0D DVNT (PCIU, One)=0D DVNT (PCID, 0x03)=0D }=0D }=0D =0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D - ^S19.PCNT (^S10.PCNT ())=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-3-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Igor Mammedov =0D =0D =0D Commit: a8339e07f94a47f99560baef59d65a9e039aaf45=0D https://github.com/qemu/qemu/commit/a8339e07f94a47f99560baef59d65a9= e039aaf45=0D Author: Ani Sinha =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/q35/DSDT.multi-bridge=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D =0D We added a new unit test for testing acpi hotplug on multifunction bridge= s in=0D q35 machines. Here, we update the DSDT table gloden master blob for this = unit=0D test.=0D =0D The test adds the following devices to qemu and then checks the changes=0D= introduced in the DSDT table due to the addition of the following devices= :=0D =0D (a) a multifunction bridge device=0D (b) a bridge device with function 1=0D (c) a non-bridge device with function 2=0D =0D In the DSDT table, we should see AML hotplug descriptions for (a) and (b)= .=0D For (a) we should find a hotplug AML description for function 0.=0D =0D Following is the ASL diff between the original DSDT table and the modifie= d DSDT=0D table due to the unit test. We see that multifunction bridge on bus 2 and= single=0D function bridge on bus 3 function 1 are described, not the non-bridge bal= loon=0D device on bus 4, function 2.=0D =0D @@ -1,30 +1,30 @@=0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20190509 (64-bit version)=0D * Copyright (c) 2000 - 2019 Intel Corporation=0D *=0D * Disassembling to symbolic ASL+ operators=0D *=0D - * Disassembly of tests/data/acpi/q35/DSDT, Thu Oct 7 18:29:19 2021=0D + * Disassembly of /tmp/aml-C7JCA1, Thu Oct 7 18:29:19 2021=0D *=0D * Original Table Header:=0D * Signature "DSDT"=0D - * Length 0x00002061 (8289)=0D + * Length 0x00002187 (8583)=0D * Revision 0x01 **** 32-bit table (V1), no 64-bit math supp= ort=0D - * Checksum 0xF9=0D + * Checksum 0x8D=0D * OEM ID "BOCHS "=0D * OEM Table ID "BXPC "=0D * OEM Revision 0x00000001 (1)=0D * Compiler ID "BXPC"=0D * Compiler Version 0x00000001 (1)=0D */=0D DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)=0D {=0D Scope (\)=0D {=0D OperationRegion (DBG, SystemIO, 0x0402, One)=0D Field (DBG, ByteAcc, NoLock, Preserve)=0D {=0D DBGB, 8=0D }=0D =0D @@ -3265,23 +3265,95 @@=0D Method (_S1D, 0, NotSerialized) // _S1D: S1 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S2D, 0, NotSerialized) // _S2D: S2 Device Stat= e=0D {=0D Return (Zero)=0D }=0D =0D Method (_S3D, 0, NotSerialized) // _S3D: S3 Device Stat= e=0D {=0D Return (Zero)=0D }=0D }=0D =0D + Device (S10)=0D + {=0D + Name (_ADR, 0x00020000) // _ADR: Address=0D + Name (BSEL, One)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D One=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D + Device (S19)=0D + {=0D + Name (_ADR, 0x00030001) // _ADR: Address=0D + Name (BSEL, Zero)=0D + Device (S00)=0D + {=0D + Name (_SUN, Zero) // _SUN: Slot User Number=0D + Name (_ADR, Zero) // _ADR: Address=0D + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Devi= ce, x=3D0-9=0D + {=0D + PCEJ (BSEL, _SUN)=0D + }=0D +=0D + Method (_DSM, 4, Serialized) // _DSM: Device-Specif= ic Method=0D + {=0D + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN= ))=0D + }=0D + }=0D +=0D + Method (DVNT, 2, NotSerialized)=0D + {=0D + If ((Arg0 & One))=0D + {=0D + Notify (S00, Arg1)=0D + }=0D + }=0D +=0D + Method (PCNT, 0, NotSerialized)=0D + {=0D + BNUM =3D Zero=0D + DVNT (PCIU, One)=0D + DVNT (PCID, 0x03)=0D + }=0D + }=0D +=0D Method (PCNT, 0, NotSerialized)=0D {=0D + ^S19.PCNT ()=0D + ^S10.PCNT ()=0D }=0D }=0D }=0D }=0D =0D Signed-off-by: Ani Sinha =0D Message-Id: <20211007135750.1277213-4-ani@anisinha.ca>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Acked-by: Igor Mammedov =0D =0D =0D Commit: afc9fcde55296b83f659de9da3cdf044812a6eeb=0D https://github.com/qemu/qemu/commit/afc9fcde55296b83f659de9da3cdf04= 4812a6eeb=0D Author: Richard Henderson =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M docs/system/device-emulation.rst=0D A docs/system/devices/vhost-user-rng.rst=0D M hw/net/vhost_net-stub.c=0D M hw/net/vhost_net.c=0D M hw/net/virtio-net.c=0D M hw/pci/pci_bridge.c=0D M hw/virtio/Kconfig=0D M hw/virtio/meson.build=0D M hw/virtio/trace-events=0D A hw/virtio/vhost-user-rng-pci.c=0D A hw/virtio/vhost-user-rng.c=0D M hw/virtio/vhost-user.c=0D M hw/virtio/vhost-vdpa.c=0D M hw/virtio/virtio-iommu-pci.c=0D A include/hw/virtio/vhost-user-rng.h=0D M include/hw/virtio/vhost-vdpa.h=0D M include/hw/virtio/vhost.h=0D M include/hw/virtio/virtio-iommu.h=0D M include/hw/virtio/virtio-net.h=0D M include/net/net.h=0D M include/net/vhost_net.h=0D M meson.build=0D M net/net.c=0D M net/vhost-vdpa.c=0D M softmmu/qdev-monitor.c=0D M subprojects/libvhost-user/libvhost-user.c=0D A tests/data/acpi/q35/APIC.xapic=0D A tests/data/acpi/q35/DMAR.dmar=0D A tests/data/acpi/q35/DSDT.ivrs=0D A tests/data/acpi/q35/DSDT.multi-bridge=0D A tests/data/acpi/q35/DSDT.xapic=0D A tests/data/acpi/q35/FACP.xapic=0D A tests/data/acpi/q35/IVRS.ivrs=0D A tests/data/acpi/q35/SRAT.xapic=0D M tests/data/acpi/rebuild-expected-aml.sh=0D M tests/qtest/acpi-utils.c=0D M tests/qtest/arm-cpu-features.c=0D M tests/qtest/bios-tables-test.c=0D M tests/qtest/libqos/libqtest.h=0D M tests/qtest/libqtest.c=0D M tests/qtest/migration-test.c=0D M tests/qtest/vhost-user-blk-test.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagi= ng=0D =0D pc,pci,virtio: features, fixes, tests=0D =0D vhost user rng=0D vdpa multiqueue=0D Fixes, cleanups, new tests all over the place.=0D =0D Signed-off-by: Michael S. Tsirkin =0D =0D # gpg: Signature made Wed 20 Oct 2021 03:18:24 AM PDT=0D # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5= 469=0D # gpg: issuer "mst@redhat.com"=0D # gpg: Good signature from "Michael S. Tsirkin " [full]=0D= # gpg: aka "Michael S. Tsirkin " [full]=0D= =0D * remotes/mst/tags/for_upstream: (44 commits)=0D tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge = test=0D tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges f= or q35=0D tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT ta= ble blob=0D pci: fix PCI resource reserve capability on BE=0D vhost-vdpa: multiqueue support=0D virtio-net: vhost control virtqueue support=0D vhost: record the last virtqueue index for the virtio device=0D virtio-net: use "queue_pairs" instead of "queues" when possible=0D vhost-net: control virtqueue support=0D net: introduce control client=0D vhost-vdpa: let net_vhost_vdpa_init() returns NetClientState *=0D vhost-vdpa: prepare for the multiqueue support=0D vhost-vdpa: classify one time request=0D vhost-vdpa: open device fd in net_init_vhost_vdpa()=0D bios-tables-test: don't disassemble empty files=0D rebuild-expected-aml.sh: allow partial target list=0D qdev/qbus: remove failover specific code=0D vhost-user-blk-test: pass vhost-user socket fds to QSD=0D failover: fix a regression introduced by JSON'ification of -device=0D vhost-user: fix duplicated notifier MR init=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/50352cce138e...afc9fcde5529= =0D From MAILER-DAEMON Thu Oct 21 11:29:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mda0J-00069c-TY for mharc-qemu-commits@gnu.org; Thu, 21 Oct 2021 11:29:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mda0I-00064N-MX for qemu-commits@nongnu.org; Thu, 21 Oct 2021 11:29:14 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:34121 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mda0E-0007pY-UG for qemu-commits@nongnu.org; Thu, 21 Oct 2021 11:29:14 -0400 Received: from github.com (hubbernetes-node-82063ad.ac4-iad.github.net [10.52.208.67]) by smtp.github.com (Postfix) with ESMTPA id 1A261560155 for ; Thu, 21 Oct 2021 08:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634830150; bh=oheKiA59Pam5jnG/4is/3rHD4TVo2SP76lBrqQuug7E=; h=Date:From:To:Subject:From; b=T8VIEVU62cwn+cb84h1mgIdMqUvIjPnzF/HAHU0wybqadzdA23j9xQtqvWH5w8koa Q97j8nLNpQTELQWO/RRpdDhhxDwjPVkVgqnfZMTcBkWtz0iUvlgmXZzHnKou+Sg/bG XRyelYH+8I31BeVxPhGWTAFmUdgBb3sNJ82qkrJQ= Date: Thu, 21 Oct 2021 08:29:10 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 621f70: spapr/xive: Add source status helpers X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 15:29:15 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 621f70d21027a914eda1446134193a24e7a662d5=0D https://github.com/qemu/qemu/commit/621f70d21027a914eda1446134193a2= 4e7a662d5=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/spapr_xive.c=0D M hw/intc/spapr_xive_kvm.c=0D M hw/intc/xive.c=0D M include/hw/ppc/xive.h=0D =0D Log Message:=0D -----------=0D spapr/xive: Add source status helpers=0D =0D and use them to set and test the ASSERTED bit of LSI sources.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211004212141.432954-1-clg@kaod.org>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6f4912a4160f157217730b0affdcb6c92c24ca76=0D https://github.com/qemu/qemu/commit/6f4912a4160f157217730b0affdcb6c= 92c24ca76=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use tcg_constant_i32() in gen_setb()=0D =0D Avoid using TCG temporaries for the -1 and 8 constant values.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003141711.3673181-2-f4bug@amsat.org>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 491b3cca3653bf36db67f91be0e3db64682bef91=0D https://github.com/qemu/qemu/commit/491b3cca3653bf36db67f91be0e3db6= 4682bef91=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use tcg_constant_i64() in gen_brh()=0D =0D The mask of the Byte-Reverse Halfword opcode is a read-only=0D constant. We can avoid using a TCG temporary by moving the=0D mask to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003141711.3673181-3-f4bug@amsat.org>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: a8dcb8da8a95edde3d6d8bb6a0502d50ed632557=0D https://github.com/qemu/qemu/commit/a8dcb8da8a95edde3d6d8bb6a0502d5= 0ed632557=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix the test raising the decrementer exception=0D =0D Commit 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") introduced=0D new int64t variables and broke the test triggering the decrementer=0D exception. Revert partially the change to evaluate both clause of the=0D if statement.=0D =0D Reported-by: Coverity CID 1464061=0D Fixes: 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer")=0D Suggested-by: Peter Maydell =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211005053324.441132-1-clg@kaod.org>=0D Reviewed-by: Greg Kurz =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 3c706d02522fb031e79823fd14b121878dccbcc6=0D https://github.com/qemu/qemu/commit/3c706d02522fb031e79823fd14b1218= 78dccbcc6=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/spapr_softmmu.c=0D =0D Log Message:=0D -----------=0D hw/ppc/spapr_softmmu: Reduce include list=0D =0D Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu")=0D introduced a lot of unnecessary #include directives. Remove them.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211006170801.178023-1-philmd@redhat.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 644c68696e8335f80d4a9295db0445505e24d8e2=0D https://github.com/qemu/qemu/commit/644c68696e8335f80d4a9295db04455= 05e24d8e2=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/spapr_xive_kvm.c=0D =0D Log Message:=0D -----------=0D spapr/xive: Use xive_esb_rw() to trigger interrupts=0D =0D xive_esb_rw() is the common routine used for memory accesses on ESB=0D page. Use it for triggers also.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211006210546.641102-1-clg@kaod.org>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 5ae3d2e8ba37def4b3ca38f220200bf5721317e0=0D https://github.com/qemu/qemu/commit/5ae3d2e8ba37def4b3ca38f220200bf= 5721317e0=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc.c=0D =0D Log Message:=0D -----------=0D hw/ppc: Fix iothread locking in the 405 code=0D =0D When using u-boot as firmware with the taihu board, QEMU aborts with=0D this assertion:=0D =0D ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion fa= iled:=0D (qemu_mutex_iothread_locked())=0D =0D Running QEMU with "-d in_asm" shows that the crash happens when writing=0D= to SPR 0x3f2, so we are missing to lock the iothread in the code path=0D here.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211006071140.565952-1-thuth@redhat.com>=0D Reviewed-by: C=C3=A9dric Le Goater =0D Tested-by: C=C3=A9dric Le Goater =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 252fcf36bba483493365e91c2f98569de29a43fd=0D https://github.com/qemu/qemu/commit/252fcf36bba483493365e91c2f98569= de29a43fd=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D A tests/acceptance/ppc_405.py=0D =0D Log Message:=0D -----------=0D tests/acceptance: Add tests for the ppc405 boards=0D =0D Using the U-Boot firmware, we can check that at least the serial console=0D= of the ppc405 boards is still usable.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211011125930.750217-1-thuth@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D [dwg: Added an extra tag at Philippe's suggestion]=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 66c6b40aba13807506f20c7522f4930c9ffc76ce=0D https://github.com/qemu/qemu/commit/66c6b40aba13807506f20c7522f4930= c9ffc76ce=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D M tests/tcg/ppc64/Makefile.target=0D M tests/tcg/ppc64le/Makefile.target=0D A tests/tcg/ppc64le/signal_save_restore_xer.c=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Fix XER access in save/restore_user_regs=0D =0D We should use cpu_read_xer/cpu_write_xer to save/restore the complete=0D register since some of its bits are in other fields of CPUPPCState. A=0D test is added to prevent future regressions.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-2-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 7974dc5900f7c128232782b0b39ccd40001bdb08=0D https://github.com/qemu/qemu/commit/7974dc5900f7c128232782b0b39ccd4= 0001bdb08=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/gdbstub.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix XER access in gdbstub=0D =0D The value of XER is split in multiple fields of CPUPPCState, like=0D env->xer and env->so. To get/set the whole register from gdb, we should=0D= use cpu_read_xer/cpu_write_xer.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-3-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 10de0521889d36633450e35b22f6a45ef856226d=0D https://github.com/qemu/qemu/commit/10de0521889d36633450e35b22f6a45= ef856226d=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M target/ppc/cpu.c=0D M target/ppc/cpu.h=0D =0D Log Message:=0D -----------=0D linux-user: Fix XER access in ppc version of elf_core_copy_regs=0D =0D env->xer doesn't hold some bits of XER, like OV and CA. To write the=0D complete register in the core dump we should read XER value with=0D cpu_read_xer.=0D =0D Reported-by: Lucas Mateus Castro (alqotel) = =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-4-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 3938cacdb2367c203fd796af3f8c70cdb70c5007=0D https://github.com/qemu/qemu/commit/3938cacdb2367c203fd796af3f8c70c= db70c5007=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/monitor.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix XER access in monitor=0D =0D We can't read env->xer directly, as it does not contain some bits of=0D XER. Instead, we should have a callback that uses cpu_read_xer to read=0D= the complete register.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-5-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 239fec2497907f2adf7e6b9fdda4138e81bac619=0D https://github.com/qemu/qemu/commit/239fec2497907f2adf7e6b9fdda4138= e81bac619=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Restrict memory to 2 gigabytes=0D =0D The CHRP spec this board confirms to only allows 2 GiB of system=0D memory below 4 GiB as the high 2 GiB is allocated to IO and system=0D resources. To avoid problems with memory overlapping these areas=0D restrict RAM to 2 GiB similar to mac_newworld.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <54f58229a69c9c1cca21bcecad700b3d7052edd5.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 99173b679a346d6a92dbb685adecf5c419288c0c=0D https://github.com/qemu/qemu/commit/99173b679a346d6a92dbb685adecf5c= 419288c0c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Warn when using VOF but no kernel is specified=0D =0D Issue a warning when using VOF (which is the default) but no -kernel=0D option given to let users know that it will likely fail as the guest=0D has nothing to run. It is not a hard error because it may still be=0D useful to start the machine without further options for testing or=0D inspecting it from monitor without actually booting it.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 94cd1ffbe1a8b7f08df76e14d9226804cc21b56c=0D https://github.com/qemu/qemu/commit/94cd1ffbe1a8b7f08df76e14d922680= 4cc21b56c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Implement get-time-of-day RTAS function with VOF=0D =0D This is needed for Linux to access RTC time.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <6233eb07c680d6c74427e11b9641958f98d53378.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: bd20cde50bb1a3b47fcba02432edc6141d9fb1d0=0D https://github.com/qemu/qemu/commit/bd20cde50bb1a3b47fcba02432edc61= 41d9fb1d0=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/pci-host/mv64361.c=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Access MV64361 registers via their memory region=0D =0D Instead of relying on the mapped address of the MV64361 registers=0D access them via their memory region. This is not a problem at reset=0D time when these registers are mapped at the default address but the=0D guest could change this later and then the RTAS calls accessing PCI=0D config registers could fail. None of the guests actually do this so=0D this only avoids a theoretical problem not seen in practice.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: =0D Signed-off-by: David Gibson =0D =0D =0D Commit: d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d=0D https://github.com/qemu/qemu/commit/d200ea14b7ec5b9f0eaf1eee6e8fc47= c359ee40d=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Add constants for PCI config addresses=0D =0D Define a constant for PCI config addresses to make it clearer what=0D these numbers are.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 284c0486e7872243458b956b9a91bc757b59a44c=0D https://github.com/qemu/qemu/commit/284c0486e7872243458b956b9a91bc7= 57b59a44c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Implement power-off RTAS function with VOF=0D =0D This only helps Linux guests as only that seems to use it.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <1c1e030f2bbc86e950b3310fb5922facdc21ef86.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 5ff1dfdf66f99c5208187cc2716a3a974f22b7c7=0D https://github.com/qemu/qemu/commit/5ff1dfdf66f99c5208187cc2716a3a9= 74f22b7c7=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D A tests/acceptance/ppc_bamboo.py=0D =0D Log Message:=0D -----------=0D tests/acceptance: Add a test for the bamboo ppc board=0D =0D The kernel and initrd from the "Aboriginal Linux" project can be=0D used to run some tests on the bamboo ppc machine.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211015090008.1299609-1-thuth@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6fa5726be6a52b246335cb86a3c118cdfd40c677=0D https://github.com/qemu/qemu/commit/6fa5726be6a52b246335cb86a3c118c= dfd40c677=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Filter mtmsr[d] input before setting MSR=0D =0D PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or=0D= MSR[LE]", but the current code only filters the GPR-provided value if=0D L=3D1. This behavior caused some problems in FreeBSD, and a build option=0D= was added to work around the issue [1], but it seems that the bug was=0D not reported in launchpad/gitlab. This patch address the issue in qemu,=0D= so the option on FreeBSD should no longer be required.=0D =0D [1] https://cgit.freebsd.org/src/commit/?id=3D4efb1ca7d2a44cfb33d7f9e18bd= 92f8d68dcfee0=0D =0D Signed-off-by: Matheus Ferst =0D Message-Id: <20211015181940.197982-1-matheus.ferst@eldorado.org.br>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: f7460df27162d1643f74677d53fad4328142c6a9=0D https://github.com/qemu/qemu/commit/f7460df27162d1643f74677d53fad43= 28142c6a9=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/helper_regs.c=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: add MMCR0 PMCC bits to hflags=0D =0D We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+=0D= emulation and following PowerISA v3.1. This requires several PMU related=0D= registers to be exposed to userspace (problem state). PowerISA v3.1=0D dictates that the PMCC bits of the MMCR0 register controls the level of=0D= access of the PMU registers to problem state.=0D =0D This patch start things off by exposing both PMCC bits to hflags,=0D allowing us to access them via DisasContext in the read/write callbacks=0D= that we're going to add next.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-2-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 565cb1096733dae6d388244e03d60d680f6eca84=0D https://github.com/qemu/qemu/commit/565cb1096733dae6d388244e03d60d6= 80f6eca84=0D Author: Gustavo Romero =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D A target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: add user read/write functions for MMCR0=0D =0D Userspace need access to PMU SPRs to be able to operate the PMU. One of=0D= such SPRs is MMCR0.=0D =0D MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU=0D register. This class of registers has common read/write rules that are=0D= governed by MMCR0 PMCC bits. MMCR0 is also not fully exposed to problem=0D= state: only MMCR0_FC, MMCR0_PMAO and MMCR0_PMAE bits are=0D readable/writable in this case.=0D =0D This patch exposes MMCR0 to userspace by doing the following:=0D =0D - two new callbacks, spr_read_MMCR0_ureg() and spr_write_MMCR0_ureg(),=0D= are added to be used as problem state read/write callbacks of UMMCR0.=0D Both callbacks filters the amount of bits userspace is able to=0D read/write by using a MMCR0_UREG_MASK;=0D =0D - problem state access control is done by the spr_groupA_read_allowed()=0D= and spr_groupA_write_allowed() helpers. These helpers will read the=0D current PMCC bits from DisasContext and check whether the read/write=0D MMCR0 operation is valid or noti;=0D =0D - to avoid putting exclusive PMU logic into the already loaded=0D translate.c file, let's create a new 'power8-pmu-regs.c.inc' file that=0D= will hold all the spr_read/spr_write functions of PMU registers.=0D =0D The 'power8' name of this new file intends to hint about the proven=0D support of the PMU logic to be added. The code has been tested with the=0D= IBM POWER chip family, POWER8 being the oldest version tested. This=0D doesn't mean that the PMU logic will break with any other PPC64 chip=0D that implements Book3s, but rather that we can't assert that it works=0D properly with any Book3s compliant chip.=0D =0D CC: Gustavo Romero =0D Signed-off-by: Gustavo Romero =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-3-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 7b3ecf16c81c16eb3cf171b0bd63c08f1a5dd942=0D https://github.com/qemu/qemu/commit/7b3ecf16c81c16eb3cf171b0bd63c08= f1a5dd942=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D M target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D =0D Log Message:=0D -----------=0D target/ppc: add user read/write functions for MMCR2=0D =0D Similar to the previous patch, let's add problem state read/write access = to=0D the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered=0D= to be read/written by userspace.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-4-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: cedf706956e7440653b18ac2c2a9452b8d710577=0D https://github.com/qemu/qemu/commit/cedf706956e7440653b18ac2c2a9452= b8d710577=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu_init.c=0D M target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D =0D Log Message:=0D -----------=0D target/ppc: adding user read/write functions for PMCs=0D =0D Problem state needs to be able to read and write the PMU counters,=0D otherwise it won't be aware of any sampling result that the PMU produces=0D= after a Perf run.=0D =0D This patch does that in a similar fashion as already done in the=0D previous patches. PMCs 5 and 6 have a special condition, aside from the=0D= constraints that are common with PMCs 1-4, where they are not part of the= =0D PMU if MMCR0_PMCC is 0b11.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-5-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6f9e8515c106650fbba7222c8f66234c8546c025=0D https://github.com/qemu/qemu/commit/6f9e8515c106650fbba7222c8f66234= c8546c025=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc4xx_pci.c=0D =0D Log Message:=0D -----------=0D hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels=0D= =0D Recent Linux kernels are accessing the PCI device in slot 0 that=0D represents the PCI host bridge. This causes ppc4xx_pci_map_irq()=0D to return -1 which causes an assert() later:=0D =0D hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >=3D 0' f= ailed.=0D =0D Thus we should allocate an IRQ line for the device in slot 0, too.=0D To avoid changes to the outside of ppc4xx_pci.c, we map it to=0D the internal IRQ number 4 which will then happily be ignored since=0D ppc440_bamboo.c does not wire it up.=0D =0D With these changes it is now possible again to use recent Linux=0D kernels for the bamboo board.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211019091817.469003-1-thuth@redhat.com>=0D Reviewed-by: C=C3=A9dric Le Goater =0D Tested-by: C=C3=A9dric Le Goater =0D Signed-off-by: David Gibson =0D =0D =0D Commit: e016b58f6ed2e07bde45da7d6792b6c93879a3cf=0D https://github.com/qemu/qemu/commit/e016b58f6ed2e07bde45da7d6792b6c= 93879a3cf=0D Author: Richard Henderson =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M hw/intc/spapr_xive.c=0D M hw/intc/spapr_xive_kvm.c=0D M hw/intc/xive.c=0D M hw/pci-host/mv64361.c=0D M hw/ppc/pegasos2.c=0D M hw/ppc/ppc.c=0D M hw/ppc/ppc4xx_pci.c=0D M hw/ppc/spapr_softmmu.c=0D M include/hw/ppc/xive.h=0D M linux-user/elfload.c=0D M linux-user/ppc/signal.c=0D M target/ppc/cpu.c=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D M target/ppc/gdbstub.c=0D M target/ppc/helper_regs.c=0D M target/ppc/monitor.c=0D A target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D M target/ppc/translate.c=0D A tests/acceptance/ppc_405.py=0D A tests/acceptance/ppc_bamboo.py=0D M tests/tcg/ppc64/Makefile.target=0D M tests/tcg/ppc64le/Makefile.target=0D A tests/tcg/ppc64le/signal_save_restore_xer.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-6.2-20211021= ' into staging=0D =0D ppc patch queue 2021-10-21=0D =0D Here's the next batch of ppc target related patches for qemu-6.2.=0D Highlights are:=0D * Some fixes and minimal tests for old embedded ppc platforms=0D * The beginnings of PMU emulation in TCG from Daniel Barboza=0D * Some improvements to the pegasos2 platform=0D * A number of TCG bugfixes from the folks at the El Dorado Institute=0D * A few other assorted bugfixes and cleanups=0D =0D # gpg: Signature made Wed 20 Oct 2021 09:19:04 PM PDT=0D # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B= 392=0D # gpg: Good signature from "David Gibson " [= full]=0D # gpg: aka "David Gibson (kernel.org) " [= unknown]=0D # gpg: aka "David Gibson (Red Hat) " = [full]=0D # gpg: aka "David Gibson (ozlabs.org) " [full]=0D =0D * remotes/dgibson/tags/ppc-for-6.2-20211021: (25 commits)=0D hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels=0D= target/ppc: adding user read/write functions for PMCs=0D target/ppc: add user read/write functions for MMCR2=0D target/ppc: add user read/write functions for MMCR0=0D target/ppc: add MMCR0 PMCC bits to hflags=0D target/ppc: Filter mtmsr[d] input before setting MSR=0D tests/acceptance: Add a test for the bamboo ppc board=0D ppc/pegasos2: Implement power-off RTAS function with VOF=0D ppc/pegasos2: Add constants for PCI config addresses=0D ppc/pegasos2: Access MV64361 registers via their memory region=0D ppc/pegasos2: Implement get-time-of-day RTAS function with VOF=0D ppc/pegasos2: Warn when using VOF but no kernel is specified=0D ppc/pegasos2: Restrict memory to 2 gigabytes=0D target/ppc: Fix XER access in monitor=0D linux-user: Fix XER access in ppc version of elf_core_copy_regs=0D target/ppc: Fix XER access in gdbstub=0D linux-user/ppc: Fix XER access in save/restore_user_regs=0D tests/acceptance: Add tests for the ppc405 boards=0D hw/ppc: Fix iothread locking in the 405 code=0D spapr/xive: Use xive_esb_rw() to trigger interrupts=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/afc9fcde5529...e016b58f6ed2= =0D From MAILER-DAEMON Thu Oct 21 12:53:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdbJc-0001Ce-KI for mharc-qemu-commits@gnu.org; Thu, 21 Oct 2021 12:53:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbJV-00011T-Nk for qemu-commits@nongnu.org; Thu, 21 Oct 2021 12:53:09 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:48123 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbJQ-0003ZF-Sg for qemu-commits@nongnu.org; Thu, 21 Oct 2021 12:53:09 -0400 Received: from github.com (hubbernetes-node-7dc6fac.va3-iad.github.net [10.48.125.31]) by smtp.github.com (Postfix) with ESMTPA id DE9C4340210 for ; Thu, 21 Oct 2021 09:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634835183; bh=3YNDfCMsgziltBvj3nvg35wmdzBiRl32elwUVk8qIEc=; h=Date:From:To:Subject:From; b=zmzKvesDO+j4XpfpAMiRRdvqji96yK/N7p9oo2dNkxEQ3dQ+2GIy2ZjFX7Yx8bemX xgCDo+uA6/R9X8CJLCDeJf+GSwJHQyyx0haFE8IC0INQ+ET4ttUD5wzDStPVofi8AB P7302fV4dMp/YqHGfmzWXTIhNv/OQJbdwDztSUO4= Date: Thu, 21 Oct 2021 09:53:03 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 621f70: spapr/xive: Add source status helpers X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 16:53:10 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 621f70d21027a914eda1446134193a24e7a662d5=0D https://github.com/qemu/qemu/commit/621f70d21027a914eda1446134193a2= 4e7a662d5=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/spapr_xive.c=0D M hw/intc/spapr_xive_kvm.c=0D M hw/intc/xive.c=0D M include/hw/ppc/xive.h=0D =0D Log Message:=0D -----------=0D spapr/xive: Add source status helpers=0D =0D and use them to set and test the ASSERTED bit of LSI sources.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211004212141.432954-1-clg@kaod.org>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6f4912a4160f157217730b0affdcb6c92c24ca76=0D https://github.com/qemu/qemu/commit/6f4912a4160f157217730b0affdcb6c= 92c24ca76=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use tcg_constant_i32() in gen_setb()=0D =0D Avoid using TCG temporaries for the -1 and 8 constant values.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003141711.3673181-2-f4bug@amsat.org>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 491b3cca3653bf36db67f91be0e3db64682bef91=0D https://github.com/qemu/qemu/commit/491b3cca3653bf36db67f91be0e3db6= 4682bef91=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Use tcg_constant_i64() in gen_brh()=0D =0D The mask of the Byte-Reverse Halfword opcode is a read-only=0D constant. We can avoid using a TCG temporary by moving the=0D mask to the constant pool.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211003141711.3673181-3-f4bug@amsat.org>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: a8dcb8da8a95edde3d6d8bb6a0502d50ed632557=0D https://github.com/qemu/qemu/commit/a8dcb8da8a95edde3d6d8bb6a0502d5= 0ed632557=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix the test raising the decrementer exception=0D =0D Commit 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") introduced=0D new int64t variables and broke the test triggering the decrementer=0D exception. Revert partially the change to evaluate both clause of the=0D if statement.=0D =0D Reported-by: Coverity CID 1464061=0D Fixes: 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer")=0D Suggested-by: Peter Maydell =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211005053324.441132-1-clg@kaod.org>=0D Reviewed-by: Greg Kurz =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 3c706d02522fb031e79823fd14b121878dccbcc6=0D https://github.com/qemu/qemu/commit/3c706d02522fb031e79823fd14b1218= 78dccbcc6=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/spapr_softmmu.c=0D =0D Log Message:=0D -----------=0D hw/ppc/spapr_softmmu: Reduce include list=0D =0D Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu")=0D introduced a lot of unnecessary #include directives. Remove them.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211006170801.178023-1-philmd@redhat.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 644c68696e8335f80d4a9295db0445505e24d8e2=0D https://github.com/qemu/qemu/commit/644c68696e8335f80d4a9295db04455= 05e24d8e2=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/spapr_xive_kvm.c=0D =0D Log Message:=0D -----------=0D spapr/xive: Use xive_esb_rw() to trigger interrupts=0D =0D xive_esb_rw() is the common routine used for memory accesses on ESB=0D page. Use it for triggers also.=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Message-Id: <20211006210546.641102-1-clg@kaod.org>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 5ae3d2e8ba37def4b3ca38f220200bf5721317e0=0D https://github.com/qemu/qemu/commit/5ae3d2e8ba37def4b3ca38f220200bf= 5721317e0=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc.c=0D =0D Log Message:=0D -----------=0D hw/ppc: Fix iothread locking in the 405 code=0D =0D When using u-boot as firmware with the taihu board, QEMU aborts with=0D this assertion:=0D =0D ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion fa= iled:=0D (qemu_mutex_iothread_locked())=0D =0D Running QEMU with "-d in_asm" shows that the crash happens when writing=0D= to SPR 0x3f2, so we are missing to lock the iothread in the code path=0D here.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211006071140.565952-1-thuth@redhat.com>=0D Reviewed-by: C=C3=A9dric Le Goater =0D Tested-by: C=C3=A9dric Le Goater =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 252fcf36bba483493365e91c2f98569de29a43fd=0D https://github.com/qemu/qemu/commit/252fcf36bba483493365e91c2f98569= de29a43fd=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D A tests/acceptance/ppc_405.py=0D =0D Log Message:=0D -----------=0D tests/acceptance: Add tests for the ppc405 boards=0D =0D Using the U-Boot firmware, we can check that at least the serial console=0D= of the ppc405 boards is still usable.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211011125930.750217-1-thuth@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D [dwg: Added an extra tag at Philippe's suggestion]=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 66c6b40aba13807506f20c7522f4930c9ffc76ce=0D https://github.com/qemu/qemu/commit/66c6b40aba13807506f20c7522f4930= c9ffc76ce=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M linux-user/ppc/signal.c=0D M tests/tcg/ppc64/Makefile.target=0D M tests/tcg/ppc64le/Makefile.target=0D A tests/tcg/ppc64le/signal_save_restore_xer.c=0D =0D Log Message:=0D -----------=0D linux-user/ppc: Fix XER access in save/restore_user_regs=0D =0D We should use cpu_read_xer/cpu_write_xer to save/restore the complete=0D register since some of its bits are in other fields of CPUPPCState. A=0D test is added to prevent future regressions.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-2-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 7974dc5900f7c128232782b0b39ccd40001bdb08=0D https://github.com/qemu/qemu/commit/7974dc5900f7c128232782b0b39ccd4= 0001bdb08=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/gdbstub.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix XER access in gdbstub=0D =0D The value of XER is split in multiple fields of CPUPPCState, like=0D env->xer and env->so. To get/set the whole register from gdb, we should=0D= use cpu_read_xer/cpu_write_xer.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-3-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 10de0521889d36633450e35b22f6a45ef856226d=0D https://github.com/qemu/qemu/commit/10de0521889d36633450e35b22f6a45= ef856226d=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M target/ppc/cpu.c=0D M target/ppc/cpu.h=0D =0D Log Message:=0D -----------=0D linux-user: Fix XER access in ppc version of elf_core_copy_regs=0D =0D env->xer doesn't hold some bits of XER, like OV and CA. To write the=0D complete register in the core dump we should read XER value with=0D cpu_read_xer.=0D =0D Reported-by: Lucas Mateus Castro (alqotel) = =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-4-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 3938cacdb2367c203fd796af3f8c70cdb70c5007=0D https://github.com/qemu/qemu/commit/3938cacdb2367c203fd796af3f8c70c= db70c5007=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/monitor.c=0D =0D Log Message:=0D -----------=0D target/ppc: Fix XER access in monitor=0D =0D We can't read env->xer directly, as it does not contain some bits of=0D XER. Instead, we should have a callback that uses cpu_read_xer to read=0D= the complete register.=0D =0D Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")=0D= Signed-off-by: Matheus Ferst =0D Message-Id: <20211014223234.127012-5-matheus.ferst@eldorado.org.br>=0D Reviewed-by: Richard Henderson =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 239fec2497907f2adf7e6b9fdda4138e81bac619=0D https://github.com/qemu/qemu/commit/239fec2497907f2adf7e6b9fdda4138= e81bac619=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Restrict memory to 2 gigabytes=0D =0D The CHRP spec this board confirms to only allows 2 GiB of system=0D memory below 4 GiB as the high 2 GiB is allocated to IO and system=0D resources. To avoid problems with memory overlapping these areas=0D restrict RAM to 2 GiB similar to mac_newworld.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <54f58229a69c9c1cca21bcecad700b3d7052edd5.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 99173b679a346d6a92dbb685adecf5c419288c0c=0D https://github.com/qemu/qemu/commit/99173b679a346d6a92dbb685adecf5c= 419288c0c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Warn when using VOF but no kernel is specified=0D =0D Issue a warning when using VOF (which is the default) but no -kernel=0D option given to let users know that it will likely fail as the guest=0D has nothing to run. It is not a hard error because it may still be=0D useful to start the machine without further options for testing or=0D inspecting it from monitor without actually booting it.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 94cd1ffbe1a8b7f08df76e14d9226804cc21b56c=0D https://github.com/qemu/qemu/commit/94cd1ffbe1a8b7f08df76e14d922680= 4cc21b56c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Implement get-time-of-day RTAS function with VOF=0D =0D This is needed for Linux to access RTC time.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <6233eb07c680d6c74427e11b9641958f98d53378.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: bd20cde50bb1a3b47fcba02432edc6141d9fb1d0=0D https://github.com/qemu/qemu/commit/bd20cde50bb1a3b47fcba02432edc61= 41d9fb1d0=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/pci-host/mv64361.c=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Access MV64361 registers via their memory region=0D =0D Instead of relying on the mapped address of the MV64361 registers=0D access them via their memory region. This is not a problem at reset=0D time when these registers are mapped at the default address but the=0D guest could change this later and then the RTAS calls accessing PCI=0D config registers could fail. None of the guests actually do this so=0D this only avoids a theoretical problem not seen in practice.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: =0D Signed-off-by: David Gibson =0D =0D =0D Commit: d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d=0D https://github.com/qemu/qemu/commit/d200ea14b7ec5b9f0eaf1eee6e8fc47= c359ee40d=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Add constants for PCI config addresses=0D =0D Define a constant for PCI config addresses to make it clearer what=0D these numbers are.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 284c0486e7872243458b956b9a91bc757b59a44c=0D https://github.com/qemu/qemu/commit/284c0486e7872243458b956b9a91bc7= 57b59a44c=0D Author: BALATON Zoltan =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/pegasos2.c=0D =0D Log Message:=0D -----------=0D ppc/pegasos2: Implement power-off RTAS function with VOF=0D =0D This only helps Linux guests as only that seems to use it.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <1c1e030f2bbc86e950b3310fb5922facdc21ef86.1634241019.git.bala= ton@eik.bme.hu>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 5ff1dfdf66f99c5208187cc2716a3a974f22b7c7=0D https://github.com/qemu/qemu/commit/5ff1dfdf66f99c5208187cc2716a3a9= 74f22b7c7=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D A tests/acceptance/ppc_bamboo.py=0D =0D Log Message:=0D -----------=0D tests/acceptance: Add a test for the bamboo ppc board=0D =0D The kernel and initrd from the "Aboriginal Linux" project can be=0D used to run some tests on the bamboo ppc machine.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211015090008.1299609-1-thuth@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Tested-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6fa5726be6a52b246335cb86a3c118cdfd40c677=0D https://github.com/qemu/qemu/commit/6fa5726be6a52b246335cb86a3c118c= dfd40c677=0D Author: Matheus Ferst =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: Filter mtmsr[d] input before setting MSR=0D =0D PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or=0D= MSR[LE]", but the current code only filters the GPR-provided value if=0D L=3D1. This behavior caused some problems in FreeBSD, and a build option=0D= was added to work around the issue [1], but it seems that the bug was=0D not reported in launchpad/gitlab. This patch address the issue in qemu,=0D= so the option on FreeBSD should no longer be required.=0D =0D [1] https://cgit.freebsd.org/src/commit/?id=3D4efb1ca7d2a44cfb33d7f9e18bd= 92f8d68dcfee0=0D =0D Signed-off-by: Matheus Ferst =0D Message-Id: <20211015181940.197982-1-matheus.ferst@eldorado.org.br>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: f7460df27162d1643f74677d53fad4328142c6a9=0D https://github.com/qemu/qemu/commit/f7460df27162d1643f74677d53fad43= 28142c6a9=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/helper_regs.c=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: add MMCR0 PMCC bits to hflags=0D =0D We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+=0D= emulation and following PowerISA v3.1. This requires several PMU related=0D= registers to be exposed to userspace (problem state). PowerISA v3.1=0D dictates that the PMCC bits of the MMCR0 register controls the level of=0D= access of the PMU registers to problem state.=0D =0D This patch start things off by exposing both PMCC bits to hflags,=0D allowing us to access them via DisasContext in the read/write callbacks=0D= that we're going to add next.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-2-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 565cb1096733dae6d388244e03d60d680f6eca84=0D https://github.com/qemu/qemu/commit/565cb1096733dae6d388244e03d60d6= 80f6eca84=0D Author: Gustavo Romero =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D A target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D M target/ppc/translate.c=0D =0D Log Message:=0D -----------=0D target/ppc: add user read/write functions for MMCR0=0D =0D Userspace need access to PMU SPRs to be able to operate the PMU. One of=0D= such SPRs is MMCR0.=0D =0D MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU=0D register. This class of registers has common read/write rules that are=0D= governed by MMCR0 PMCC bits. MMCR0 is also not fully exposed to problem=0D= state: only MMCR0_FC, MMCR0_PMAO and MMCR0_PMAE bits are=0D readable/writable in this case.=0D =0D This patch exposes MMCR0 to userspace by doing the following:=0D =0D - two new callbacks, spr_read_MMCR0_ureg() and spr_write_MMCR0_ureg(),=0D= are added to be used as problem state read/write callbacks of UMMCR0.=0D Both callbacks filters the amount of bits userspace is able to=0D read/write by using a MMCR0_UREG_MASK;=0D =0D - problem state access control is done by the spr_groupA_read_allowed()=0D= and spr_groupA_write_allowed() helpers. These helpers will read the=0D current PMCC bits from DisasContext and check whether the read/write=0D MMCR0 operation is valid or noti;=0D =0D - to avoid putting exclusive PMU logic into the already loaded=0D translate.c file, let's create a new 'power8-pmu-regs.c.inc' file that=0D= will hold all the spr_read/spr_write functions of PMU registers.=0D =0D The 'power8' name of this new file intends to hint about the proven=0D support of the PMU logic to be added. The code has been tested with the=0D= IBM POWER chip family, POWER8 being the oldest version tested. This=0D doesn't mean that the PMU logic will break with any other PPC64 chip=0D that implements Book3s, but rather that we can't assert that it works=0D properly with any Book3s compliant chip.=0D =0D CC: Gustavo Romero =0D Signed-off-by: Gustavo Romero =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-3-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 7b3ecf16c81c16eb3cf171b0bd63c08f1a5dd942=0D https://github.com/qemu/qemu/commit/7b3ecf16c81c16eb3cf171b0bd63c08= f1a5dd942=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D M target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D =0D Log Message:=0D -----------=0D target/ppc: add user read/write functions for MMCR2=0D =0D Similar to the previous patch, let's add problem state read/write access = to=0D the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered=0D= to be read/written by userspace.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-4-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: cedf706956e7440653b18ac2c2a9452b8d710577=0D https://github.com/qemu/qemu/commit/cedf706956e7440653b18ac2c2a9452= b8d710577=0D Author: Daniel Henrique Barboza =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M target/ppc/cpu_init.c=0D M target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D =0D Log Message:=0D -----------=0D target/ppc: adding user read/write functions for PMCs=0D =0D Problem state needs to be able to read and write the PMU counters,=0D otherwise it won't be aware of any sampling result that the PMU produces=0D= after a Perf run.=0D =0D This patch does that in a similar fashion as already done in the=0D previous patches. PMCs 5 and 6 have a special condition, aside from the=0D= constraints that are common with PMCs 1-4, where they are not part of the= =0D PMU if MMCR0_PMCC is 0b11.=0D =0D Signed-off-by: Daniel Henrique Barboza =0D Message-Id: <20211018010133.315842-5-danielhb413@gmail.com>=0D Signed-off-by: David Gibson =0D =0D =0D Commit: 6f9e8515c106650fbba7222c8f66234c8546c025=0D https://github.com/qemu/qemu/commit/6f9e8515c106650fbba7222c8f66234= c8546c025=0D Author: Thomas Huth =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/ppc/ppc4xx_pci.c=0D =0D Log Message:=0D -----------=0D hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels=0D= =0D Recent Linux kernels are accessing the PCI device in slot 0 that=0D represents the PCI host bridge. This causes ppc4xx_pci_map_irq()=0D to return -1 which causes an assert() later:=0D =0D hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >=3D 0' f= ailed.=0D =0D Thus we should allocate an IRQ line for the device in slot 0, too.=0D To avoid changes to the outside of ppc4xx_pci.c, we map it to=0D the internal IRQ number 4 which will then happily be ignored since=0D ppc440_bamboo.c does not wire it up.=0D =0D With these changes it is now possible again to use recent Linux=0D kernels for the bamboo board.=0D =0D Signed-off-by: Thomas Huth =0D Message-Id: <20211019091817.469003-1-thuth@redhat.com>=0D Reviewed-by: C=C3=A9dric Le Goater =0D Tested-by: C=C3=A9dric Le Goater =0D Signed-off-by: David Gibson =0D =0D =0D Commit: e016b58f6ed2e07bde45da7d6792b6c93879a3cf=0D https://github.com/qemu/qemu/commit/e016b58f6ed2e07bde45da7d6792b6c= 93879a3cf=0D Author: Richard Henderson =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M hw/intc/spapr_xive.c=0D M hw/intc/spapr_xive_kvm.c=0D M hw/intc/xive.c=0D M hw/pci-host/mv64361.c=0D M hw/ppc/pegasos2.c=0D M hw/ppc/ppc.c=0D M hw/ppc/ppc4xx_pci.c=0D M hw/ppc/spapr_softmmu.c=0D M include/hw/ppc/xive.h=0D M linux-user/elfload.c=0D M linux-user/ppc/signal.c=0D M target/ppc/cpu.c=0D M target/ppc/cpu.h=0D M target/ppc/cpu_init.c=0D M target/ppc/gdbstub.c=0D M target/ppc/helper_regs.c=0D M target/ppc/monitor.c=0D A target/ppc/power8-pmu-regs.c.inc=0D M target/ppc/spr_tcg.h=0D M target/ppc/translate.c=0D A tests/acceptance/ppc_405.py=0D A tests/acceptance/ppc_bamboo.py=0D M tests/tcg/ppc64/Makefile.target=0D M tests/tcg/ppc64le/Makefile.target=0D A tests/tcg/ppc64le/signal_save_restore_xer.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-6.2-20211021= ' into staging=0D =0D ppc patch queue 2021-10-21=0D =0D Here's the next batch of ppc target related patches for qemu-6.2.=0D Highlights are:=0D * Some fixes and minimal tests for old embedded ppc platforms=0D * The beginnings of PMU emulation in TCG from Daniel Barboza=0D * Some improvements to the pegasos2 platform=0D * A number of TCG bugfixes from the folks at the El Dorado Institute=0D * A few other assorted bugfixes and cleanups=0D =0D # gpg: Signature made Wed 20 Oct 2021 09:19:04 PM PDT=0D # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B= 392=0D # gpg: Good signature from "David Gibson " [= full]=0D # gpg: aka "David Gibson (kernel.org) " [= unknown]=0D # gpg: aka "David Gibson (Red Hat) " = [full]=0D # gpg: aka "David Gibson (ozlabs.org) " [full]=0D =0D * remotes/dgibson/tags/ppc-for-6.2-20211021: (25 commits)=0D hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels=0D= target/ppc: adding user read/write functions for PMCs=0D target/ppc: add user read/write functions for MMCR2=0D target/ppc: add user read/write functions for MMCR0=0D target/ppc: add MMCR0 PMCC bits to hflags=0D target/ppc: Filter mtmsr[d] input before setting MSR=0D tests/acceptance: Add a test for the bamboo ppc board=0D ppc/pegasos2: Implement power-off RTAS function with VOF=0D ppc/pegasos2: Add constants for PCI config addresses=0D ppc/pegasos2: Access MV64361 registers via their memory region=0D ppc/pegasos2: Implement get-time-of-day RTAS function with VOF=0D ppc/pegasos2: Warn when using VOF but no kernel is specified=0D ppc/pegasos2: Restrict memory to 2 gigabytes=0D target/ppc: Fix XER access in monitor=0D linux-user: Fix XER access in ppc version of elf_core_copy_regs=0D target/ppc: Fix XER access in gdbstub=0D linux-user/ppc: Fix XER access in save/restore_user_regs=0D tests/acceptance: Add tests for the ppc405 boards=0D hw/ppc: Fix iothread locking in the 405 code=0D spapr/xive: Use xive_esb_rw() to trigger interrupts=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/afc9fcde5529...e016b58f6ed2= =0D From MAILER-DAEMON Thu Oct 21 12:59:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdbPN-0007tx-HM for mharc-qemu-commits@gnu.org; Thu, 21 Oct 2021 12:59:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbPL-0007qx-KD for qemu-commits@nongnu.org; Thu, 21 Oct 2021 12:59:11 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:41615 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbPH-0003oy-Iv for qemu-commits@nongnu.org; Thu, 21 Oct 2021 12:59:11 -0400 Received: from github.com (hubbernetes-node-ce32559.ash1-iad.github.net [10.56.117.66]) by smtp.github.com (Postfix) with ESMTPA id 5DEE2840682 for ; Thu, 21 Oct 2021 09:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634835546; bh=eiywYGWx3b+W29DbVcfLDf5OnqyZzEuGkQDmuuSmuwk=; h=Date:From:To:Subject:From; b=zmqZyuB620b0akLpyp/bvMw61cOWKx3baa5g5BrWTY7xTmkiyp8CywfzQJNsRaGDy 97S9hRTPhpCQo2AiTDN07qXfEJVWM9nMqJr096dSt0Q4B4yH6FQpZedceVP9D1fB2T i2f9W+GdDL82hr/+Ln0FQ8iU9jycwDfM7nPUHUPw= Date: Thu, 21 Oct 2021 09:59:06 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 5384ad: tests/acpi: Get prepared for IORT E.b revision upg... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 16:59:11 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 5384adef5d5ac27d57f684e3937592d2074ce8b9=0D https://github.com/qemu/qemu/commit/5384adef5d5ac27d57f684e3937592d= 2074ce8b9=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Get prepared for IORT E.b revision upgrade=0D =0D Ignore IORT till reference blob for E.b spec revision gets=0D added.=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-2-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1c2cb7e0b3e6743b449a4ad28d70b77d2290e817=0D https://github.com/qemu/qemu/commit/1c2cb7e0b3e6743b449a4ad28d70b77= d2290e817=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt-acpi-build: IORT upgrade up to revision E.b=0D =0D Upgrade the IORT table from B to E.b specification=0D revision (ARM DEN 0049E.b).=0D =0D The SMMUv3 and root complex node have additional=0D fields. Also unique IORT node identifiers are=0D introduced: they are generated in sequential order.=0D They are not cross-referenced though.=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-3-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 47432863ff1892870730e78630b5d0dbed7e72b2=0D https://github.com/qemu/qemu/commit/47432863ff1892870730e78630b5d0d= bed7e72b2=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/IORT=0D M tests/data/acpi/virt/IORT.memhp=0D M tests/data/acpi/virt/IORT.numamem=0D M tests/data/acpi/virt/IORT.pxb=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Generate reference blob for IORT rev E.b=0D =0D Re-generate reference blobs with rebuild-expected-aml.sh.=0D =0D Differences reported by "make check V=3D1" are listed below=0D (IORT.numamem). Differences for other variants are similar.=0D =0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20180629 (64-bit version)=0D * Copyright (c) 2000 - 2018 Intel Corporation=0D *=0D - * Disassembly of tests/data/acpi/virt/IORT.numamem, Thu Oct 14 06:13:19= 2021=0D + * Disassembly of /tmp/aml-K8L9A1, Thu Oct 14 06:13:19 2021=0D *=0D * ACPI Data Table [IORT]=0D *=0D * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue=0D= */=0D =0D [000h 0000 4] Signature : "IORT" [IO Remapping T= able]=0D -[004h 0004 4] Table Length : 0000007C=0D -[008h 0008 1] Revision : 00=0D -[009h 0009 1] Checksum : 07=0D +[004h 0004 4] Table Length : 00000080=0D +[008h 0008 1] Revision : 03=0D +[009h 0009 1] Checksum : B3=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 4] Node Count : 00000002=0D [028h 0040 4] Node Offset : 00000030=0D [02Ch 0044 4] Reserved : 00000000=0D =0D [030h 0048 1] Type : 00=0D [031h 0049 2] Length : 0018=0D -[033h 0051 1] Revision : 00=0D +[033h 0051 1] Revision : 01=0D [034h 0052 4] Reserved : 00000000=0D [038h 0056 4] Mapping Count : 00000000=0D [03Ch 0060 4] Mapping Offset : 00000000=0D =0D [040h 0064 4] ItsCount : 00000001=0D [044h 0068 4] Identifiers : 00000000=0D =0D [048h 0072 1] Type : 02=0D -[049h 0073 2] Length : 0034=0D -[04Bh 0075 1] Revision : 00=0D -[04Ch 0076 4] Reserved : 00000000=0D +[049h 0073 2] Length : 0038=0D +[04Bh 0075 1] Revision : 03=0D +[04Ch 0076 4] Reserved : 00000001=0D [050h 0080 4] Mapping Count : 00000001=0D -[054h 0084 4] Mapping Offset : 00000020=0D +[054h 0084 4] Mapping Offset : 00000024=0D =0D [058h 0088 8] Memory Properties : [IORT Memory Access Prope= rties]=0D [058h 0088 4] Cache Coherency : 00000001=0D [05Ch 0092 1] Hints (decoded below) : 00=0D Transient : 0=0D Write Allocate : 0=0D Read Allocate : 0=0D Override : 0=0D [05Dh 0093 2] Reserved : 0000=0D [05Fh 0095 1] Memory Flags (decoded below) : 03=0D Coherency : 1=0D Device Attribute : 1=0D [060h 0096 4] ATS Attribute : 00000000=0D [064h 0100 4] PCI Segment Number : 00000000=0D -[068h 0104 1] Memory Size Limit : 00=0D +[068h 0104 1] Memory Size Limit : 40=0D [069h 0105 3] Reserved : 000000=0D =0D -[068h 0104 4] Input base : 00000000=0D -[06Ch 0108 4] ID Count : 0000FFFF=0D -[070h 0112 4] Output Base : 00000000=0D -[074h 0116 4] Output Reference : 00000030=0D -[078h 0120 4] Flags (decoded below) : 00000000=0D +[06Ch 0108 4] Input base : 00000000=0D +[070h 0112 4] ID Count : 0000FFFF=0D +[074h 0116 4] Output Base : 00000000=0D +[078h 0120 4] Output Reference : 00000030=0D +[07Ch 0124 4] Flags (decoded below) : 00000000=0D Single Mapping : 0=0D =0D -Raw Table Data: Length 124 (0x7C)=0D +Raw Table Data: Length 128 (0x80)=0D =0D - 0000: 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.....= BOCHS=0D + 0000: 49 4F 52 54 80 00 00 00 03 B3 42 4F 43 48 53 20 // IORT......= BOCHS=0D 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ..= ..BXPC=0D 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0.= ......=0D - 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ..........= ......=0D - 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .........4= ......=0D - 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // .... .....= ......=0D - 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // ..........= ......=0D - 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0.....= ..=0D + 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ..........= ......=0D + 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8= ......=0D + 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$.....= ......=0D + 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@.= ......=0D + 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.= ......=0D **=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-4-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 99abb72520cb27f2318908831abc6915e286158b=0D https://github.com/qemu/qemu/commit/99abb72520cb27f2318908831abc691= 5e286158b=0D Author: Gavin Shan =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/boot.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Don't create device-tree node for empty NUMA node=0D =0D The empty NUMA node, where no memory resides, are allowed. For=0D example, the following command line specifies two empty NUMA nodes.=0D With this, QEMU fails to boot because of the conflicting device-tree=0D node names, as the following error message indicates.=0D =0D /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \=0D -accel kvm -machine virt,gic-version=3Dhost \=0D -cpu host -smp 4,sockets=3D2,cores=3D2,threads=3D1 \=0D -m 1024M,slots=3D16,maxmem=3D64G \=0D -object memory-backend-ram,id=3Dmem0,size=3D512M \=0D -object memory-backend-ram,id=3Dmem1,size=3D512M \=0D -numa node,nodeid=3D0,cpus=3D0-1,memdev=3Dmem0 \=0D -numa node,nodeid=3D1,cpus=3D2-3,memdev=3Dmem1 \=0D -numa node,nodeid=3D2 \=0D -numa node,nodeid=3D3=0D :=0D qemu-system-aarch64: FDT: Failed to create subnode /memory@80000000: FD= T_ERR_EXISTS=0D =0D As specified by linux device-tree binding document, the device-tree=0D nodes for these empty NUMA nodes shouldn't be generated. However,=0D the corresponding NUMA node IDs should be included in the distance=0D map. The memory hotplug through device-tree on ARM64 isn't existing=0D so far and it's not necessary to require the user to provide a distance=0D= map. Furthermore, the default distance map Linux generates may even be=0D= sufficient. So this simply skips populating the device-tree nodes for=0D these empty NUMA nodes to avoid the error, so that QEMU can be started=0D= successfully.=0D =0D Signed-off-by: Gavin Shan =0D Reviewed-by: Andrew Jones =0D Message-Id: <20211015124246.23073-1-gshan@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b152229697c8e3ef2655d29488eadacde6b2b309=0D https://github.com/qemu/qemu/commit/b152229697c8e3ef2655d29488eadac= de6b2b309=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M roms/Makefile=0D =0D Log Message:=0D -----------=0D roms/edk2: Only init brotli submodule to build BaseTools=0D =0D Since EDK2 BaseTools only require the brotli submodule,=0D we don't need to initialize other submodules to build it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Thomas Huth =0D Reviewed-by: Gerd Hoffmann =0D Message-Id: <20211018105816.2663195-2-philmd@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bd0da3a3d4f5e51856b5716508df9a4fdbbd416c=0D https://github.com/qemu/qemu/commit/bd0da3a3d4f5e51856b5716508df9a4= fdbbd416c=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/edk2.yml=0D M roms/Makefile.edk2=0D M scripts/make-release=0D =0D Log Message:=0D -----------=0D roms/edk2: Only initialize required submodules=0D =0D The EDK2 firmware images built to test QEMU do not require=0D the following submodules:=0D =0D - MdeModulePkg/Universal/RegularExpressionDxe/oniguruma=0D - UnitTestFrameworkPkg/Library/CmockaLib/cmocka=0D =0D The only submodules required are:=0D =0D - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3=0D - BaseTools/Source/C/BrotliCompress/brotli=0D - CryptoPkg/Library/OpensslLib/openssl=0D - MdeModulePkg/Library/BrotliCustomDecompressLib/brotli=0D =0D Adapt the buildsys machinery to only initialize the required=0D submodules.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Gerd Hoffmann =0D Message-Id: <20211018105816.2663195-3-philmd@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b84722cf4455b44a98b5a527067001dee58ace10=0D https://github.com/qemu/qemu/commit/b84722cf4455b44a98b5a527067001d= ee58ace10=0D Author: Shuuichirou Ishii =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/sbsa-ref.c=0D =0D Log Message:=0D -----------=0D hw/arm/sbsa-ref: Fixed cpu type error message typo.=0D =0D Signed-off-by: Shuuichirou Ishii =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Yanan Wang =0D Message-Id: <20211008063604.670699-1-ishii.shuuichir@fujitsu.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8975eb891fb6df56442763acf2bdb7c03b0933bf=0D https://github.com/qemu/qemu/commit/8975eb891fb6df56442763acf2bdb7c= 03b0933bf=0D Author: Luc Michel =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/core/loader.c=0D M include/hw/elf_ops.h=0D M include/hw/loader.h=0D =0D Log Message:=0D -----------=0D hw/elf_ops.h: switch to ssize_t for elf loader return type=0D =0D Until now, int was used as the return type for all the ELF=0D loader related functions. The returned value is the sum of all loaded=0D program headers "MemSize" fields.=0D =0D Because of the overflow check in elf_ops.h, trying to load an ELF bigger=0D= than INT_MAX will fail. Switch to ssize_t to remove this limitation.=0D =0D Signed-off-by: Luc Michel =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Stefano Garzarella =0D Message-Id: <20211014194325.19917-1-lmichel@kalray.eu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3cc322f437b027d95aa96dd140b2b4fa9a5b6dfb=0D https://github.com/qemu/qemu/commit/3cc322f437b027d95aa96dd140b2b4f= a9a5b6dfb=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/virt/DBG2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Add void table for virt/DBG2 bios-tables-test=0D =0D Add placeholders for DBG2 reference table for=0D virt tests and ignore till reference blob is added.=0D =0D Signed-off-by: Eric Auger =0D Acked-by: Igor Mammedov =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-2-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f0dc9a5d8d556a42a3e614d041effc8854eac71e=0D https://github.com/qemu/qemu/commit/f0dc9a5d8d556a42a3e614d041effc8= 854eac71e=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt_acpi_build: Generate DBG2 table=0D =0D ARM SBBR specification mandates DBG2 table (Debug Port Table 2)=0D since v1.0 (ARM DEN0044F 8.3.1.7 DBG2).=0D =0D The DBG2 table allows to describe one or more debug ports.=0D =0D Generate an DBG2 table featuring a single debug port, the PL011.=0D =0D The DBG2 specification can be found at=0D "Microsoft Debug Port Table 2 (DBG2)"=0D https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-de= bug-port-table?redirectedfrom=3DMSDN=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Igor Mammedov =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-3-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 98f5c60fbda773ba5620941adf1cb96b3b2ff758=0D https://github.com/qemu/qemu/commit/98f5c60fbda773ba5620941adf1cb96= b3b2ff758=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/DBG2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: Generate reference table for virt/DBG2=0D =0D Add the DBG2 table generated with=0D tests/data/acpi/rebuild-expected-aml.sh=0D =0D Signed-off-by: Eric Auger =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-4-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 31511b6fe0251806f425b5a671c6d211e030162d=0D https://github.com/qemu/qemu/commit/31511b6fe0251806f425b5a671c6d21= 1e030162d=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M include/hw/arm/virt.h=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Only describe cpu topology since virt-6.2=0D =0D On existing older machine types, without cpu topology described=0D in ACPI or DT, the guest will populate one by default. With the=0D topology described, it will read the information and set up its=0D topology as instructed, but that may not be the same as what was=0D getting used by default. It's possible that an user application=0D has a dependency on the default topology and if the default one=0D gets changed it will probably behave differently.=0D =0D Based on above consideration we'd better only describe topology=0D information to the guest on 6.2 and later machine types.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Message-Id: <20211020142125.7516-2-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b863f0b75852dfd62b3f31b08eeddd3b03694fc2=0D https://github.com/qemu/qemu/commit/b863f0b75852dfd62b3f31b08eeddd3= b03694fc2=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M include/sysemu/device_tree.h=0D M softmmu/device_tree.c=0D =0D Log Message:=0D -----------=0D device_tree: Add qemu_fdt_add_path=0D =0D qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it=0D also adds all missing subnodes from the given path. We'll use it=0D in a coming patch where we will add cpu-map to the device tree.=0D =0D And we also tweak an error message of qemu_fdt_add_subnode().=0D =0D Co-developed-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Reviewed-by: David Gibson =0D Reviewed-by: Andrew Jones =0D Cc: David Gibson =0D Cc: Alistair Francis =0D Message-Id: <20211020142125.7516-3-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 72b0527ff6ab09502e0b320050eb086fc4d61d26=0D https://github.com/qemu/qemu/commit/72b0527ff6ab09502e0b320050eb086= fc4d61d26=0D Author: Andrew Jones =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Add cpu-map to device tree=0D =0D Support device tree CPU topology descriptions.=0D =0D In accordance with the Devicetree Specification, the Linux Doc=0D "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are=0D present. And we have already met the requirement by generating=0D /cpus/cpu@* nodes for members within ms->smp.cpus. Accordingly,=0D we should also create subnodes in cpu-map for the present cpus,=0D each of which relates to an unique cpu node.=0D =0D The Linux Doc "cpu/cpu-topology.txt" states that the hierarchy=0D of CPUs in a SMP system is defined through four entities and=0D they are socket/cluster/core/thread. It is also required that=0D a socket node's child nodes must be one or more cluster nodes.=0D Given that currently we are only provided with information of=0D socket/core/thread, we assume there is one cluster child node=0D in each socket node when creating cpu-map.=0D =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Message-Id: <20211020142125.7516-4-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9de36ef87270b669219b973362a948347ab382f4=0D https://github.com/qemu/qemu/commit/9de36ef87270b669219b973362a9483= 47ab382f4=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D hw/acpi/aml-build: Add Processor hierarchy node structure=0D =0D Add a generic API to build Processor hierarchy node structure (Type 0),=0D= which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1.=0D =0D This function will be used to build ACPI PPTT table for cpu topology.=0D =0D Co-developed-by: Ying Fang =0D Co-developed-by: Henglong Fan =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Michael S. Tsirkin =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-5-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 099f2df2e6b0ec1b0f1d4e518f730594a66661a8=0D https://github.com/qemu/qemu/commit/099f2df2e6b0ec1b0f1d4e518f73059= 4a66661a8=0D Author: Andrew Jones =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D hw/acpi/aml-build: Add PPTT table=0D =0D Add the Processor Properties Topology Table (PPTT) used to=0D describe CPU topology information to ACPI guests.=0D =0D Note, a DT-boot Linux guest with a non-flat CPU topology will=0D see socket and core IDs being sequential integers starting=0D from zero, which is different from ACPI-boot Linux guest,=0D e.g. with -smp 4,sockets=3D2,cores=3D2,threads=3D1=0D =0D a DT boot produces:=0D =0D cpu: 0 package_id: 0 core_id: 0=0D cpu: 1 package_id: 0 core_id: 1=0D cpu: 2 package_id: 1 core_id: 0=0D cpu: 3 package_id: 1 core_id: 1=0D =0D an ACPI boot produces:=0D =0D cpu: 0 package_id: 36 core_id: 0=0D cpu: 1 package_id: 36 core_id: 1=0D cpu: 2 package_id: 96 core_id: 2=0D cpu: 3 package_id: 96 core_id: 3=0D =0D This is due to several reasons:=0D =0D 1) DT cpu nodes do not have an equivalent field to what the PPTT=0D ACPI Processor ID must be, i.e. something equal to the MADT CPU=0D UID or equal to the UID of an ACPI processor container. In both=0D ACPI cases those are platform dependant IDs assigned by the=0D vendor.=0D =0D 2) While QEMU is the vendor for a guest, if the topology specifies=0D SMT (> 1 thread), then, with ACPI, it is impossible to assign a=0D core-id the same value as a package-id, thus it is not possible=0D to have package-id=3D0 and core-id=3D0. This is because package and=0D= core containers must be in the same ACPI namespace and therefore=0D must have unique UIDs.=0D =0D 3) ACPI processor containers are not mandatorily required for PPTT=0D tables to be used and, due to the limitations of which IDs are=0D selected described above in (2), they are not helpful for QEMU,=0D so we don't build them with this patch. In the absence of them,=0D Linux assigns its own unique IDs. The maintainers have chosen not=0D to use counters from zero, but rather ACPI table offsets, which=0D explains why the numbers are so much larger than with DT.=0D =0D 4) When there is no SMT (threads=3D1) the core IDs for ACPI boot guests=0D= match the logical CPU IDs, because these IDs must be equal to the=0D MADT CPU UID (as no processor containers are present), and QEMU=0D uses the logical CPU ID for these MADT IDs.=0D =0D So in summary, with QEMU as the vendor for the guests, we simply=0D use sequential integers starting from zero for the non-leaf nodes=0D but with ID-valid flag unset, so that guest will ignore them and=0D use table offsets as unique container IDs. And we use logical CPU=0D IDs for the leaf nodes with the ID-valid flag set, which will be=0D consistent with MADT.=0D =0D Currently the implementation of PPTT generation complies with ACPI=0D specification 5.2.29 (Revision 6.3). The 6.3 spec can be found at:=0D https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf=0D =0D Reviewed-by: Eric Auger =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211020142125.7516-6-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4ebd52b92a560094f5127fa9478044084636cbdf=0D https://github.com/qemu/qemu/commit/4ebd52b92a560094f5127fa94780440= 84636cbdf=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/virt/PPTT=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/data/acpi/virt: Add an empty expected file for PPTT=0D =0D Add a generic empty binary file for the new introduced PPTT table=0D under tests/data/acpi/virt, and list it as files to be changed in=0D tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-7-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 70d23ed534efa038bb10af9f1c537d4eeb0db137=0D https://github.com/qemu/qemu/commit/70d23ed534efa038bb10af9f1c537d4= eeb0db137=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt-acpi-build: Generate PPTT table=0D =0D Generate the Processor Properties Topology Table (PPTT) for ARM=0D virt machines supporting it (>=3D 6.2).=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-8-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f801789ff00f457044dcd91323316dbde42578d1=0D https://github.com/qemu/qemu/commit/f801789ff00f457044dcd91323316db= de42578d1=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/PPTT=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/data/acpi/virt: Update the empty expected file for PPTT=0D =0D Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory=0D to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.=0D =0D Disassembled output of the updated new file:=0D =0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20180810 (64-bit version)=0D * Copyright (c) 2000 - 2018 Intel Corporation=0D *=0D * Disassembly of tests/data/acpi/virt/PPTT, Fri Oct 8 10:12:32 2021=0D *=0D * ACPI Data Table [PPTT]=0D *=0D * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue=0D= */=0D =0D [000h 0000 4] Signature : "PPTT" [Processor Prope= rties Topology Table]=0D [004h 0004 4] Table Length : 0000004C=0D [008h 0008 1] Revision : 02=0D [009h 0009 1] Checksum : A8=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 1] Subtable Type : 00 [Processor Hierarchy No= de]=0D [025h 0037 1] Length : 14=0D [026h 0038 2] Reserved : 0000=0D [028h 0040 4] Flags (decoded below) : 00000001=0D Physical package : 1=0D ACPI Processor ID valid : 0=0D [02Ch 0044 4] Parent : 00000000=0D [030h 0048 4] ACPI Processor ID : 00000000=0D [034h 0052 4] Private Resource Number : 00000000=0D =0D [038h 0056 1] Subtable Type : 00 [Processor Hierarchy No= de]=0D [039h 0057 1] Length : 14=0D [03Ah 0058 2] Reserved : 0000=0D [03Ch 0060 4] Flags (decoded below) : 0000000A=0D Physical package : 0=0D ACPI Processor ID valid : 1=0D [040h 0064 4] Parent : 00000024=0D [044h 0068 4] ACPI Processor ID : 00000000=0D [048h 0072 4] Private Resource Number : 00000000=0D =0D Raw Table Data: Length 76 (0x4C)=0D =0D 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....B= OCHS=0D 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ...= .BXPC=0D 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ...........= .....=0D 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ...........= .....=0D 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $..........= .=0D =0D Reviewed-by: Eric Auger =0D Signed-off-by: Yanan Wang =0D Message-Id: <20211020142125.7516-9-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0=0D https://github.com/qemu/qemu/commit/4c127fdbe81d66e7cafed90908d0fd1= f6f2a6cd0=0D Author: Richard Henderson =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/edk2.yml=0D M hw/acpi/aml-build.c=0D M hw/arm/boot.c=0D M hw/arm/sbsa-ref.c=0D M hw/arm/virt-acpi-build.c=0D M hw/arm/virt.c=0D M hw/core/loader.c=0D M include/hw/acpi/aml-build.h=0D M include/hw/arm/virt.h=0D M include/hw/elf_ops.h=0D M include/hw/loader.h=0D M include/sysemu/device_tree.h=0D M roms/Makefile=0D M roms/Makefile.edk2=0D M scripts/make-release=0D M softmmu/device_tree.c=0D A tests/data/acpi/virt/DBG2=0D M tests/data/acpi/virt/IORT=0D M tests/data/acpi/virt/IORT.memhp=0D M tests/data/acpi/virt/IORT.numamem=0D M tests/data/acpi/virt/IORT.pxb=0D A tests/data/acpi/virt/PPTT=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into = staging=0D =0D Introduce cpu topology support=0D Generate DBG2 table=0D Switch to ssize_t for elf loader return type=0D Fixed sbsa cpu type error message typo=0D Only initialize required submodules for edk2=0D Dont create device-tree node for empty NUMA node=0D =0D # gpg: Signature made Thu 21 Oct 2021 08:22:32 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-arm-20211021:=0D tests/data/acpi/virt: Update the empty expected file for PPTT=0D hw/arm/virt-acpi-build: Generate PPTT table=0D tests/data/acpi/virt: Add an empty expected file for PPTT=0D hw/acpi/aml-build: Add PPTT table=0D hw/acpi/aml-build: Add Processor hierarchy node structure=0D hw/arm/virt: Add cpu-map to device tree=0D device_tree: Add qemu_fdt_add_path=0D hw/arm/virt: Only describe cpu topology since virt-6.2=0D bios-tables-test: Generate reference table for virt/DBG2=0D hw/arm/virt_acpi_build: Generate DBG2 table=0D tests/acpi: Add void table for virt/DBG2 bios-tables-test=0D hw/elf_ops.h: switch to ssize_t for elf loader return type=0D hw/arm/sbsa-ref: Fixed cpu type error message typo.=0D roms/edk2: Only initialize required submodules=0D roms/edk2: Only init brotli submodule to build BaseTools=0D hw/arm/virt: Don't create device-tree node for empty NUMA node=0D tests/acpi: Generate reference blob for IORT rev E.b=0D hw/arm/virt-acpi-build: IORT upgrade up to revision E.b=0D tests/acpi: Get prepared for IORT E.b revision upgrade=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e016b58f6ed2...4c127fdbe81d= =0D From MAILER-DAEMON Thu Oct 21 15:19:43 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mddbK-0006gW-Ti for mharc-qemu-commits@gnu.org; Thu, 21 Oct 2021 15:19:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56652) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mddbJ-0006ej-U4 for qemu-commits@nongnu.org; Thu, 21 Oct 2021 15:19:41 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:56939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mddbF-00065S-TD for qemu-commits@nongnu.org; Thu, 21 Oct 2021 15:19:41 -0400 Received: from github.com (hubbernetes-node-07a07d5.ash1-iad.github.net [10.56.112.24]) by smtp.github.com (Postfix) with ESMTPA id 2352890085B for ; Thu, 21 Oct 2021 12:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634843977; bh=vEtmN/HrbovMkyli1RXn7iW8N8cG48aBFj9cEn0YSH8=; h=Date:From:To:Subject:From; b=YinB01ErBUA2N3MnCOzrpiWua5mxWoDxwVayyaW9Vh5TLezshlnXoABFQKVhKSUSA O53u2uMmAxpR5C04bJHeiPkEe/2UKUI/QkDrXqKDSvPU6d/MyiDbfW1HRmp9SBDviT dBy1oSFgGrb5GppFPOtHx6pZP3JE2iraCTiINLg4= Date: Thu, 21 Oct 2021 12:19:37 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 5384ad: tests/acpi: Get prepared for IORT E.b revision upg... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 19:19:42 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 5384adef5d5ac27d57f684e3937592d2074ce8b9=0D https://github.com/qemu/qemu/commit/5384adef5d5ac27d57f684e3937592d= 2074ce8b9=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Get prepared for IORT E.b revision upgrade=0D =0D Ignore IORT till reference blob for E.b spec revision gets=0D added.=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-2-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1c2cb7e0b3e6743b449a4ad28d70b77d2290e817=0D https://github.com/qemu/qemu/commit/1c2cb7e0b3e6743b449a4ad28d70b77= d2290e817=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt-acpi-build: IORT upgrade up to revision E.b=0D =0D Upgrade the IORT table from B to E.b specification=0D revision (ARM DEN 0049E.b).=0D =0D The SMMUv3 and root complex node have additional=0D fields. Also unique IORT node identifiers are=0D introduced: they are generated in sequential order.=0D They are not cross-referenced though.=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Jean-Philippe Brucker =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-3-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 47432863ff1892870730e78630b5d0dbed7e72b2=0D https://github.com/qemu/qemu/commit/47432863ff1892870730e78630b5d0d= bed7e72b2=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/IORT=0D M tests/data/acpi/virt/IORT.memhp=0D M tests/data/acpi/virt/IORT.numamem=0D M tests/data/acpi/virt/IORT.pxb=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Generate reference blob for IORT rev E.b=0D =0D Re-generate reference blobs with rebuild-expected-aml.sh.=0D =0D Differences reported by "make check V=3D1" are listed below=0D (IORT.numamem). Differences for other variants are similar.=0D =0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20180629 (64-bit version)=0D * Copyright (c) 2000 - 2018 Intel Corporation=0D *=0D - * Disassembly of tests/data/acpi/virt/IORT.numamem, Thu Oct 14 06:13:19= 2021=0D + * Disassembly of /tmp/aml-K8L9A1, Thu Oct 14 06:13:19 2021=0D *=0D * ACPI Data Table [IORT]=0D *=0D * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue=0D= */=0D =0D [000h 0000 4] Signature : "IORT" [IO Remapping T= able]=0D -[004h 0004 4] Table Length : 0000007C=0D -[008h 0008 1] Revision : 00=0D -[009h 0009 1] Checksum : 07=0D +[004h 0004 4] Table Length : 00000080=0D +[008h 0008 1] Revision : 03=0D +[009h 0009 1] Checksum : B3=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 4] Node Count : 00000002=0D [028h 0040 4] Node Offset : 00000030=0D [02Ch 0044 4] Reserved : 00000000=0D =0D [030h 0048 1] Type : 00=0D [031h 0049 2] Length : 0018=0D -[033h 0051 1] Revision : 00=0D +[033h 0051 1] Revision : 01=0D [034h 0052 4] Reserved : 00000000=0D [038h 0056 4] Mapping Count : 00000000=0D [03Ch 0060 4] Mapping Offset : 00000000=0D =0D [040h 0064 4] ItsCount : 00000001=0D [044h 0068 4] Identifiers : 00000000=0D =0D [048h 0072 1] Type : 02=0D -[049h 0073 2] Length : 0034=0D -[04Bh 0075 1] Revision : 00=0D -[04Ch 0076 4] Reserved : 00000000=0D +[049h 0073 2] Length : 0038=0D +[04Bh 0075 1] Revision : 03=0D +[04Ch 0076 4] Reserved : 00000001=0D [050h 0080 4] Mapping Count : 00000001=0D -[054h 0084 4] Mapping Offset : 00000020=0D +[054h 0084 4] Mapping Offset : 00000024=0D =0D [058h 0088 8] Memory Properties : [IORT Memory Access Prope= rties]=0D [058h 0088 4] Cache Coherency : 00000001=0D [05Ch 0092 1] Hints (decoded below) : 00=0D Transient : 0=0D Write Allocate : 0=0D Read Allocate : 0=0D Override : 0=0D [05Dh 0093 2] Reserved : 0000=0D [05Fh 0095 1] Memory Flags (decoded below) : 03=0D Coherency : 1=0D Device Attribute : 1=0D [060h 0096 4] ATS Attribute : 00000000=0D [064h 0100 4] PCI Segment Number : 00000000=0D -[068h 0104 1] Memory Size Limit : 00=0D +[068h 0104 1] Memory Size Limit : 40=0D [069h 0105 3] Reserved : 000000=0D =0D -[068h 0104 4] Input base : 00000000=0D -[06Ch 0108 4] ID Count : 0000FFFF=0D -[070h 0112 4] Output Base : 00000000=0D -[074h 0116 4] Output Reference : 00000030=0D -[078h 0120 4] Flags (decoded below) : 00000000=0D +[06Ch 0108 4] Input base : 00000000=0D +[070h 0112 4] ID Count : 0000FFFF=0D +[074h 0116 4] Output Base : 00000000=0D +[078h 0120 4] Output Reference : 00000030=0D +[07Ch 0124 4] Flags (decoded below) : 00000000=0D Single Mapping : 0=0D =0D -Raw Table Data: Length 124 (0x7C)=0D +Raw Table Data: Length 128 (0x80)=0D =0D - 0000: 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.....= BOCHS=0D + 0000: 49 4F 52 54 80 00 00 00 03 B3 42 4F 43 48 53 20 // IORT......= BOCHS=0D 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ..= ..BXPC=0D 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0.= ......=0D - 0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ..........= ......=0D - 0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .........4= ......=0D - 0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // .... .....= ......=0D - 0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // ..........= ......=0D - 0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0.....= ..=0D + 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ..........= ......=0D + 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8= ......=0D + 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$.....= ......=0D + 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@.= ......=0D + 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.= ......=0D **=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211014115643.756977-4-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 99abb72520cb27f2318908831abc6915e286158b=0D https://github.com/qemu/qemu/commit/99abb72520cb27f2318908831abc691= 5e286158b=0D Author: Gavin Shan =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/boot.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Don't create device-tree node for empty NUMA node=0D =0D The empty NUMA node, where no memory resides, are allowed. For=0D example, the following command line specifies two empty NUMA nodes.=0D With this, QEMU fails to boot because of the conflicting device-tree=0D node names, as the following error message indicates.=0D =0D /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \=0D -accel kvm -machine virt,gic-version=3Dhost \=0D -cpu host -smp 4,sockets=3D2,cores=3D2,threads=3D1 \=0D -m 1024M,slots=3D16,maxmem=3D64G \=0D -object memory-backend-ram,id=3Dmem0,size=3D512M \=0D -object memory-backend-ram,id=3Dmem1,size=3D512M \=0D -numa node,nodeid=3D0,cpus=3D0-1,memdev=3Dmem0 \=0D -numa node,nodeid=3D1,cpus=3D2-3,memdev=3Dmem1 \=0D -numa node,nodeid=3D2 \=0D -numa node,nodeid=3D3=0D :=0D qemu-system-aarch64: FDT: Failed to create subnode /memory@80000000: FD= T_ERR_EXISTS=0D =0D As specified by linux device-tree binding document, the device-tree=0D nodes for these empty NUMA nodes shouldn't be generated. However,=0D the corresponding NUMA node IDs should be included in the distance=0D map. The memory hotplug through device-tree on ARM64 isn't existing=0D so far and it's not necessary to require the user to provide a distance=0D= map. Furthermore, the default distance map Linux generates may even be=0D= sufficient. So this simply skips populating the device-tree nodes for=0D these empty NUMA nodes to avoid the error, so that QEMU can be started=0D= successfully.=0D =0D Signed-off-by: Gavin Shan =0D Reviewed-by: Andrew Jones =0D Message-Id: <20211015124246.23073-1-gshan@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b152229697c8e3ef2655d29488eadacde6b2b309=0D https://github.com/qemu/qemu/commit/b152229697c8e3ef2655d29488eadac= de6b2b309=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M roms/Makefile=0D =0D Log Message:=0D -----------=0D roms/edk2: Only init brotli submodule to build BaseTools=0D =0D Since EDK2 BaseTools only require the brotli submodule,=0D we don't need to initialize other submodules to build it.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Thomas Huth =0D Reviewed-by: Gerd Hoffmann =0D Message-Id: <20211018105816.2663195-2-philmd@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bd0da3a3d4f5e51856b5716508df9a4fdbbd416c=0D https://github.com/qemu/qemu/commit/bd0da3a3d4f5e51856b5716508df9a4= fdbbd416c=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/edk2.yml=0D M roms/Makefile.edk2=0D M scripts/make-release=0D =0D Log Message:=0D -----------=0D roms/edk2: Only initialize required submodules=0D =0D The EDK2 firmware images built to test QEMU do not require=0D the following submodules:=0D =0D - MdeModulePkg/Universal/RegularExpressionDxe/oniguruma=0D - UnitTestFrameworkPkg/Library/CmockaLib/cmocka=0D =0D The only submodules required are:=0D =0D - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3=0D - BaseTools/Source/C/BrotliCompress/brotli=0D - CryptoPkg/Library/OpensslLib/openssl=0D - MdeModulePkg/Library/BrotliCustomDecompressLib/brotli=0D =0D Adapt the buildsys machinery to only initialize the required=0D submodules.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Gerd Hoffmann =0D Message-Id: <20211018105816.2663195-3-philmd@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b84722cf4455b44a98b5a527067001dee58ace10=0D https://github.com/qemu/qemu/commit/b84722cf4455b44a98b5a527067001d= ee58ace10=0D Author: Shuuichirou Ishii =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/sbsa-ref.c=0D =0D Log Message:=0D -----------=0D hw/arm/sbsa-ref: Fixed cpu type error message typo.=0D =0D Signed-off-by: Shuuichirou Ishii =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Yanan Wang =0D Message-Id: <20211008063604.670699-1-ishii.shuuichir@fujitsu.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8975eb891fb6df56442763acf2bdb7c03b0933bf=0D https://github.com/qemu/qemu/commit/8975eb891fb6df56442763acf2bdb7c= 03b0933bf=0D Author: Luc Michel =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/core/loader.c=0D M include/hw/elf_ops.h=0D M include/hw/loader.h=0D =0D Log Message:=0D -----------=0D hw/elf_ops.h: switch to ssize_t for elf loader return type=0D =0D Until now, int was used as the return type for all the ELF=0D loader related functions. The returned value is the sum of all loaded=0D program headers "MemSize" fields.=0D =0D Because of the overflow check in elf_ops.h, trying to load an ELF bigger=0D= than INT_MAX will fail. Switch to ssize_t to remove this limitation.=0D =0D Signed-off-by: Luc Michel =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Stefano Garzarella =0D Message-Id: <20211014194325.19917-1-lmichel@kalray.eu>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3cc322f437b027d95aa96dd140b2b4fa9a5b6dfb=0D https://github.com/qemu/qemu/commit/3cc322f437b027d95aa96dd140b2b4f= a9a5b6dfb=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/virt/DBG2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/acpi: Add void table for virt/DBG2 bios-tables-test=0D =0D Add placeholders for DBG2 reference table for=0D virt tests and ignore till reference blob is added.=0D =0D Signed-off-by: Eric Auger =0D Acked-by: Igor Mammedov =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-2-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f0dc9a5d8d556a42a3e614d041effc8854eac71e=0D https://github.com/qemu/qemu/commit/f0dc9a5d8d556a42a3e614d041effc8= 854eac71e=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt_acpi_build: Generate DBG2 table=0D =0D ARM SBBR specification mandates DBG2 table (Debug Port Table 2)=0D since v1.0 (ARM DEN0044F 8.3.1.7 DBG2).=0D =0D The DBG2 table allows to describe one or more debug ports.=0D =0D Generate an DBG2 table featuring a single debug port, the PL011.=0D =0D The DBG2 specification can be found at=0D "Microsoft Debug Port Table 2 (DBG2)"=0D https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-de= bug-port-table?redirectedfrom=3DMSDN=0D =0D Signed-off-by: Eric Auger =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Igor Mammedov =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-3-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 98f5c60fbda773ba5620941adf1cb96b3b2ff758=0D https://github.com/qemu/qemu/commit/98f5c60fbda773ba5620941adf1cb96= b3b2ff758=0D Author: Eric Auger =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/DBG2=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D bios-tables-test: Generate reference table for virt/DBG2=0D =0D Add the DBG2 table generated with=0D tests/data/acpi/rebuild-expected-aml.sh=0D =0D Signed-off-by: Eric Auger =0D Acked-by: Michael S. Tsirkin =0D Message-Id: <20211019080037.930641-4-eric.auger@redhat.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 31511b6fe0251806f425b5a671c6d211e030162d=0D https://github.com/qemu/qemu/commit/31511b6fe0251806f425b5a671c6d21= 1e030162d=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D M include/hw/arm/virt.h=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Only describe cpu topology since virt-6.2=0D =0D On existing older machine types, without cpu topology described=0D in ACPI or DT, the guest will populate one by default. With the=0D topology described, it will read the information and set up its=0D topology as instructed, but that may not be the same as what was=0D getting used by default. It's possible that an user application=0D has a dependency on the default topology and if the default one=0D gets changed it will probably behave differently.=0D =0D Based on above consideration we'd better only describe topology=0D information to the guest on 6.2 and later machine types.=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Message-Id: <20211020142125.7516-2-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b863f0b75852dfd62b3f31b08eeddd3b03694fc2=0D https://github.com/qemu/qemu/commit/b863f0b75852dfd62b3f31b08eeddd3= b03694fc2=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M include/sysemu/device_tree.h=0D M softmmu/device_tree.c=0D =0D Log Message:=0D -----------=0D device_tree: Add qemu_fdt_add_path=0D =0D qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it=0D also adds all missing subnodes from the given path. We'll use it=0D in a coming patch where we will add cpu-map to the device tree.=0D =0D And we also tweak an error message of qemu_fdt_add_subnode().=0D =0D Co-developed-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Reviewed-by: David Gibson =0D Reviewed-by: Andrew Jones =0D Cc: David Gibson =0D Cc: Alistair Francis =0D Message-Id: <20211020142125.7516-3-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 72b0527ff6ab09502e0b320050eb086fc4d61d26=0D https://github.com/qemu/qemu/commit/72b0527ff6ab09502e0b320050eb086= fc4d61d26=0D Author: Andrew Jones =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt: Add cpu-map to device tree=0D =0D Support device tree CPU topology descriptions.=0D =0D In accordance with the Devicetree Specification, the Linux Doc=0D "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are=0D present. And we have already met the requirement by generating=0D /cpus/cpu@* nodes for members within ms->smp.cpus. Accordingly,=0D we should also create subnodes in cpu-map for the present cpus,=0D each of which relates to an unique cpu node.=0D =0D The Linux Doc "cpu/cpu-topology.txt" states that the hierarchy=0D of CPUs in a SMP system is defined through four entities and=0D they are socket/cluster/core/thread. It is also required that=0D a socket node's child nodes must be one or more cluster nodes.=0D Given that currently we are only provided with information of=0D socket/core/thread, we assume there is one cluster child node=0D in each socket node when creating cpu-map.=0D =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Message-Id: <20211020142125.7516-4-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9de36ef87270b669219b973362a948347ab382f4=0D https://github.com/qemu/qemu/commit/9de36ef87270b669219b973362a9483= 47ab382f4=0D Author: Yanan Wang =0D Date: 2021-10-20 (Wed, 20 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D =0D Log Message:=0D -----------=0D hw/acpi/aml-build: Add Processor hierarchy node structure=0D =0D Add a generic API to build Processor hierarchy node structure (Type 0),=0D= which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1.=0D =0D This function will be used to build ACPI PPTT table for cpu topology.=0D =0D Co-developed-by: Ying Fang =0D Co-developed-by: Henglong Fan =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Michael S. Tsirkin =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-5-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 099f2df2e6b0ec1b0f1d4e518f730594a66661a8=0D https://github.com/qemu/qemu/commit/099f2df2e6b0ec1b0f1d4e518f73059= 4a66661a8=0D Author: Andrew Jones =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/acpi/aml-build.c=0D M include/hw/acpi/aml-build.h=0D =0D Log Message:=0D -----------=0D hw/acpi/aml-build: Add PPTT table=0D =0D Add the Processor Properties Topology Table (PPTT) used to=0D describe CPU topology information to ACPI guests.=0D =0D Note, a DT-boot Linux guest with a non-flat CPU topology will=0D see socket and core IDs being sequential integers starting=0D from zero, which is different from ACPI-boot Linux guest,=0D e.g. with -smp 4,sockets=3D2,cores=3D2,threads=3D1=0D =0D a DT boot produces:=0D =0D cpu: 0 package_id: 0 core_id: 0=0D cpu: 1 package_id: 0 core_id: 1=0D cpu: 2 package_id: 1 core_id: 0=0D cpu: 3 package_id: 1 core_id: 1=0D =0D an ACPI boot produces:=0D =0D cpu: 0 package_id: 36 core_id: 0=0D cpu: 1 package_id: 36 core_id: 1=0D cpu: 2 package_id: 96 core_id: 2=0D cpu: 3 package_id: 96 core_id: 3=0D =0D This is due to several reasons:=0D =0D 1) DT cpu nodes do not have an equivalent field to what the PPTT=0D ACPI Processor ID must be, i.e. something equal to the MADT CPU=0D UID or equal to the UID of an ACPI processor container. In both=0D ACPI cases those are platform dependant IDs assigned by the=0D vendor.=0D =0D 2) While QEMU is the vendor for a guest, if the topology specifies=0D SMT (> 1 thread), then, with ACPI, it is impossible to assign a=0D core-id the same value as a package-id, thus it is not possible=0D to have package-id=3D0 and core-id=3D0. This is because package and=0D= core containers must be in the same ACPI namespace and therefore=0D must have unique UIDs.=0D =0D 3) ACPI processor containers are not mandatorily required for PPTT=0D tables to be used and, due to the limitations of which IDs are=0D selected described above in (2), they are not helpful for QEMU,=0D so we don't build them with this patch. In the absence of them,=0D Linux assigns its own unique IDs. The maintainers have chosen not=0D to use counters from zero, but rather ACPI table offsets, which=0D explains why the numbers are so much larger than with DT.=0D =0D 4) When there is no SMT (threads=3D1) the core IDs for ACPI boot guests=0D= match the logical CPU IDs, because these IDs must be equal to the=0D MADT CPU UID (as no processor containers are present), and QEMU=0D uses the logical CPU ID for these MADT IDs.=0D =0D So in summary, with QEMU as the vendor for the guests, we simply=0D use sequential integers starting from zero for the non-leaf nodes=0D but with ID-valid flag unset, so that guest will ignore them and=0D use table offsets as unique container IDs. And we use logical CPU=0D IDs for the leaf nodes with the ID-valid flag set, which will be=0D consistent with MADT.=0D =0D Currently the implementation of PPTT generation complies with ACPI=0D specification 5.2.29 (Revision 6.3). The 6.3 spec can be found at:=0D https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf=0D =0D Reviewed-by: Eric Auger =0D Co-developed-by: Yanan Wang =0D Signed-off-by: Andrew Jones =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Michael S. Tsirkin =0D Message-Id: <20211020142125.7516-6-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4ebd52b92a560094f5127fa9478044084636cbdf=0D https://github.com/qemu/qemu/commit/4ebd52b92a560094f5127fa94780440= 84636cbdf=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D A tests/data/acpi/virt/PPTT=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/data/acpi/virt: Add an empty expected file for PPTT=0D =0D Add a generic empty binary file for the new introduced PPTT table=0D under tests/data/acpi/virt, and list it as files to be changed in=0D tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-7-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 70d23ed534efa038bb10af9f1c537d4eeb0db137=0D https://github.com/qemu/qemu/commit/70d23ed534efa038bb10af9f1c537d4= eeb0db137=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/virt-acpi-build.c=0D =0D Log Message:=0D -----------=0D hw/arm/virt-acpi-build: Generate PPTT table=0D =0D Generate the Processor Properties Topology Table (PPTT) for ARM=0D virt machines supporting it (>=3D 6.2).=0D =0D Signed-off-by: Yanan Wang =0D Reviewed-by: Andrew Jones =0D Reviewed-by: Eric Auger =0D Message-Id: <20211020142125.7516-8-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: f801789ff00f457044dcd91323316dbde42578d1=0D https://github.com/qemu/qemu/commit/f801789ff00f457044dcd91323316db= de42578d1=0D Author: Yanan Wang =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M tests/data/acpi/virt/PPTT=0D M tests/qtest/bios-tables-test-allowed-diff.h=0D =0D Log Message:=0D -----------=0D tests/data/acpi/virt: Update the empty expected file for PPTT=0D =0D Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory=0D to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.=0D =0D Disassembled output of the updated new file:=0D =0D /*=0D * Intel ACPI Component Architecture=0D * AML/ASL+ Disassembler version 20180810 (64-bit version)=0D * Copyright (c) 2000 - 2018 Intel Corporation=0D *=0D * Disassembly of tests/data/acpi/virt/PPTT, Fri Oct 8 10:12:32 2021=0D *=0D * ACPI Data Table [PPTT]=0D *=0D * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue=0D= */=0D =0D [000h 0000 4] Signature : "PPTT" [Processor Prope= rties Topology Table]=0D [004h 0004 4] Table Length : 0000004C=0D [008h 0008 1] Revision : 02=0D [009h 0009 1] Checksum : A8=0D [00Ah 0010 6] Oem ID : "BOCHS "=0D [010h 0016 8] Oem Table ID : "BXPC "=0D [018h 0024 4] Oem Revision : 00000001=0D [01Ch 0028 4] Asl Compiler ID : "BXPC"=0D [020h 0032 4] Asl Compiler Revision : 00000001=0D =0D [024h 0036 1] Subtable Type : 00 [Processor Hierarchy No= de]=0D [025h 0037 1] Length : 14=0D [026h 0038 2] Reserved : 0000=0D [028h 0040 4] Flags (decoded below) : 00000001=0D Physical package : 1=0D ACPI Processor ID valid : 0=0D [02Ch 0044 4] Parent : 00000000=0D [030h 0048 4] ACPI Processor ID : 00000000=0D [034h 0052 4] Private Resource Number : 00000000=0D =0D [038h 0056 1] Subtable Type : 00 [Processor Hierarchy No= de]=0D [039h 0057 1] Length : 14=0D [03Ah 0058 2] Reserved : 0000=0D [03Ch 0060 4] Flags (decoded below) : 0000000A=0D Physical package : 0=0D ACPI Processor ID valid : 1=0D [040h 0064 4] Parent : 00000024=0D [044h 0068 4] ACPI Processor ID : 00000000=0D [048h 0072 4] Private Resource Number : 00000000=0D =0D Raw Table Data: Length 76 (0x4C)=0D =0D 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....B= OCHS=0D 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ...= .BXPC=0D 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ...........= .....=0D 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ...........= .....=0D 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $..........= .=0D =0D Reviewed-by: Eric Auger =0D Signed-off-by: Yanan Wang =0D Message-Id: <20211020142125.7516-9-wangyanan55@huawei.com>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0=0D https://github.com/qemu/qemu/commit/4c127fdbe81d66e7cafed90908d0fd1= f6f2a6cd0=0D Author: Richard Henderson =0D Date: 2021-10-21 (Thu, 21 Oct 2021)=0D =0D Changed paths:=0D M .gitlab-ci.d/edk2.yml=0D M hw/acpi/aml-build.c=0D M hw/arm/boot.c=0D M hw/arm/sbsa-ref.c=0D M hw/arm/virt-acpi-build.c=0D M hw/arm/virt.c=0D M hw/core/loader.c=0D M include/hw/acpi/aml-build.h=0D M include/hw/arm/virt.h=0D M include/hw/elf_ops.h=0D M include/hw/loader.h=0D M include/sysemu/device_tree.h=0D M roms/Makefile=0D M roms/Makefile.edk2=0D M scripts/make-release=0D M softmmu/device_tree.c=0D A tests/data/acpi/virt/DBG2=0D M tests/data/acpi/virt/IORT=0D M tests/data/acpi/virt/IORT.memhp=0D M tests/data/acpi/virt/IORT.numamem=0D M tests/data/acpi/virt/IORT.pxb=0D A tests/data/acpi/virt/PPTT=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into = staging=0D =0D Introduce cpu topology support=0D Generate DBG2 table=0D Switch to ssize_t for elf loader return type=0D Fixed sbsa cpu type error message typo=0D Only initialize required submodules for edk2=0D Dont create device-tree node for empty NUMA node=0D =0D # gpg: Signature made Thu 21 Oct 2021 08:22:32 AM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-arm-20211021:=0D tests/data/acpi/virt: Update the empty expected file for PPTT=0D hw/arm/virt-acpi-build: Generate PPTT table=0D tests/data/acpi/virt: Add an empty expected file for PPTT=0D hw/acpi/aml-build: Add PPTT table=0D hw/acpi/aml-build: Add Processor hierarchy node structure=0D hw/arm/virt: Add cpu-map to device tree=0D device_tree: Add qemu_fdt_add_path=0D hw/arm/virt: Only describe cpu topology since virt-6.2=0D bios-tables-test: Generate reference table for virt/DBG2=0D hw/arm/virt_acpi_build: Generate DBG2 table=0D tests/acpi: Add void table for virt/DBG2 bios-tables-test=0D hw/elf_ops.h: switch to ssize_t for elf loader return type=0D hw/arm/sbsa-ref: Fixed cpu type error message typo.=0D roms/edk2: Only initialize required submodules=0D roms/edk2: Only init brotli submodule to build BaseTools=0D hw/arm/virt: Don't create device-tree node for empty NUMA node=0D tests/acpi: Generate reference blob for IORT rev E.b=0D hw/arm/virt-acpi-build: IORT upgrade up to revision E.b=0D tests/acpi: Get prepared for IORT E.b revision upgrade=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/e016b58f6ed2...4c127fdbe81d= =0D From MAILER-DAEMON Thu Oct 21 15:26:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mddhh-0004ht-4X for mharc-qemu-commits@gnu.org; Thu, 21 Oct 2021 15:26:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mddhd-0004gN-Bb for qemu-commits@nongnu.org; Thu, 21 Oct 2021 15:26:15 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:48297) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mddhW-0006Pi-QC for qemu-commits@nongnu.org; Thu, 21 Oct 2021 15:26:12 -0400 Received: from github.com (hubbernetes-node-f040e1d.ac4-iad.github.net [10.52.201.73]) by smtp.github.com (Postfix) with ESMTPA id 35ADE60042E for ; Thu, 21 Oct 2021 12:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634844366; bh=CGIFfPCJREJgeepFezxQMXO+T/UlTieWtFllhD0cLIQ=; h=Date:From:To:Subject:From; b=cE7xrGvYEAPKo91aBxZNkA75NaT+Si+aOixUxMFj/fLTekw3BfihviB5sROG+GmjS KbRgZi4Se2Hv9qJC7bbhuQzmOgOvgKQ1SKPIZH2rmguyzU/WGzdUbHEW0UkmGAtOB8 4yYZGbePrFnkGvud6k+5D/LgqtiDbjkl7PGFmJPU= Date: Thu, 21 Oct 2021 12:26:06 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.207; envelope-from=noreply@github.com; helo=out-24.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 4b2b3d: coroutine: resize pool periodically instead of lim... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 19:26:15 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 4b2b3d2653f255ef4259a7689af1956536565901 https://github.com/qemu/qemu/commit/4b2b3d2653f255ef4259a7689af1956536565901 Author: Stefan Hajnoczi Date: 2021-10-21 (Thu, 21 Oct 2021) Changed paths: A include/qemu/coroutine-pool-timer.h M include/qemu/coroutine.h M iothread.c A util/coroutine-pool-timer.c M util/main-loop.c M util/meson.build M util/qemu-coroutine.c Log Message: ----------- coroutine: resize pool periodically instead of limiting size It was reported that enabling SafeStack reduces IOPS significantly (>25%) with the following fio benchmark on virtio-blk using a NVMe host block device: # fio --rw=randrw --bs=4k --iodepth=64 --runtime=1m --direct=1 \ --filename=/dev/vdb --name=job1 --ioengine=libaio --thread \ --group_reporting --numjobs=16 --time_based \ --output=/tmp/fio_result Serge Guelton and I found that SafeStack is not really at fault, it just increases the cost of coroutine creation. This fio workload exhausts the coroutine pool and coroutine creation becomes a bottleneck. Previous work by Honghao Wang also pointed to excessive coroutine creation. Creating new coroutines is expensive due to allocating new stacks with mmap(2) and mprotect(2). Currently there are thread-local and global pools that recycle old Coroutine objects and their stacks but the hardcoded size limit of 64 for thread-local pools and 128 for the global pool is insufficient for the fio benchmark shown above. This patch changes the coroutine pool algorithm to a simple thread-local pool without a maximum size limit. Threads periodically shrink the pool down to a size sufficient for the maximum observed number of coroutines. The global pool is removed by this patch. It can help to hide the fact that local pools are easily exhausted, but it's doesn't fix the root cause. I don't think there is a need for a global pool because QEMU's threads are long-lived, so let's keep things simple. Performance of the above fio benchmark is as follows: Before After IOPS 60k 97k Memory usage varies over time as needed by the workload: VSZ (KB) RSS (KB) Before fio 4705248 843128 During fio 5747668 (+ ~100 MB) 849280 After fio 4694996 (- ~100 MB) 845184 This confirms that coroutines are indeed being freed when no longer needed. Thanks to Serge Guelton for working on identifying the bottleneck with me! Reported-by: Tingting Mao Signed-off-by: Stefan Hajnoczi Message-id: 20210913153524.1190696-1-stefanha@redhat.com Cc: Serge Guelton Cc: Honghao Wang Cc: Paolo Bonzini Cc: Daniele Buono Signed-off-by: Stefan Hajnoczi [Moved atexit notifier to coroutine_delete() after GitLab CI reported a memory leak in tests/unit/test-aio-multithread because the Coroutine object was created in the main thread but runs in an IOThread (where it's also deleted). --Stefan] Commit: 78d98bfbd39d507ffb38f846f60ad63335cd9c83 https://github.com/qemu/qemu/commit/78d98bfbd39d507ffb38f846f60ad63335cd9c83 Author: Richard Henderson Date: 2021-10-21 (Thu, 21 Oct 2021) Changed paths: A include/qemu/coroutine-pool-timer.h M include/qemu/coroutine.h M iothread.c A util/coroutine-pool-timer.c M util/main-loop.c M util/meson.build M util/qemu-coroutine.c Log Message: ----------- Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging Pull request Performance optimization when guest applications submit a lot of parallel I/O. This has also been found to improve clang SafeStack performance. # gpg: Signature made Thu 21 Oct 2021 10:40:49 AM PDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi " [full] # gpg: aka "Stefan Hajnoczi " [full] * remotes/stefanha/tags/block-pull-request: coroutine: resize pool periodically instead of limiting size Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/4c127fdbe81d...78d98bfbd39d From MAILER-DAEMON Fri Oct 22 10:47:53 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdvpp-0001il-40 for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 10:47:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdvpo-0001i4-2X for qemu-commits@nongnu.org; Fri, 22 Oct 2021 10:47:52 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:49821 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdvpk-0000Wu-Q8 for qemu-commits@nongnu.org; Fri, 22 Oct 2021 10:47:50 -0400 Received: from github.com (hubbernetes-node-237a2a0.va3-iad.github.net [10.48.12.36]) by smtp.github.com (Postfix) with ESMTPA id C5C495C038C for ; Fri, 22 Oct 2021 07:47:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634914067; bh=zZjS0IeJN3CHFfJlBG9f3/nm1KHsWMxBHl9WnU9tJNA=; h=Date:From:To:Subject:From; b=ZbpmlhE74L31boz9pnVo9PKM4Ny5BrnbEkizCzFcOthVlUzUiIHPesPIy7KnofKwr DibVxB+nwZ06jvk3YTrj5keFBQ0wN+Io3eGdEFQnnzyMuZSfOCoGHROS8i+yU/NHCT KYJLXdCtDs7qTtQFSrtOqdr3DmCO1Xt3PVdA0oeo= Date: Fri, 22 Oct 2021 07:47:47 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e97645: mac_via: update comment for VIA1B_vMystery bit X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 14:47:52 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: e976459b3b127838befaef57f1587770452a0827 https://github.com/qemu/qemu/commit/e976459b3b127838befaef57f1587770452a0827 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/misc/mac_via.c Log Message: ----------- mac_via: update comment for VIA1B_vMystery bit According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't particularly descriptive, the patch leaves this to ensure that the constants in mac_via.c remain in sync with Linux's mac_via.h. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 39950b16ecc21bce3bbea3fddcdf1aaefa0d6cef https://github.com/qemu/qemu/commit/39950b16ecc21bce3bbea3fddcdf1aaefa0d6cef Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: move VIA1 IRQ from level 1 to level 6 On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6 to ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even though QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1 IRQ handler regardless of the value of via_alt_mapping which is why the kernel has been able to boot until now. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 91ff5e4dcd855c6f93b91ef8c5d43b18a1d080d0 https://github.com/qemu/qemu/commit/91ff5e4dcd855c6f93b91ef8c5d43b18a1d080d0 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs In order to allow dynamic routing of IRQs to different IRQ levels on the CPU depending upon port B bit 6, use GLUE IRQ numbers and map them to the the corresponding CPU IRQ level accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 291bc1809a0ec75f283717850003c08953d80e7c https://github.com/qemu/qemu/commit/291bc1809a0ec75f283717850003c08953d80e7c Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/misc/mac_via.c M hw/misc/trace-events M include/hw/misc/mac_via.h Log Message: ----------- mac_via: add GPIO for A/UX mode Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating whether the hardware is configured for A/UX mode. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: a85d18aabdd4632bb0eeb496c97472746ba35d3c https://github.com/qemu/qemu/commit/a85d18aabdd4632bb0eeb496c97472746ba35d3c Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: wire up auxmode GPIO to GLUE This enables the GLUE logic to change its CPU level IRQ routing depending upon whether the hardware has been configured for A/UX mode. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: f7c6e12e24a736f7f3f0bf2c4e34a598e3274130 https://github.com/qemu/qemu/commit/f7c6e12e24a736f7f3f0bf2c4e34a598e3274130 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ is routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not affect the framebuffer which although it exists in slot 9, has its own dedicated IRQ on the Quadra 800 hardware. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: c7710c1ebf0b316ac0ab517fa8ceaa2824904474 https://github.com/qemu/qemu/commit/c7710c1ebf0b316ac0ab517fa8ceaa2824904474 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: wire up remaining IRQs in classic mode Explicitly wire up the remaining IRQs in classic mode to enable the use of g_assert_not_reached() in the default case to detect any unexpected IRQs. Add a comment explaining the IRQ routing differences in A/UX mode based upon the comments in NetBSD (also noting that at least A/UX 3.0.1 still uses classic mode). Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 3ea74abe2ddfd0741d4aa75484c88b346b85fb26 https://github.com/qemu/qemu/commit/3ea74abe2ddfd0741d4aa75484c88b346b85fb26 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: add NMI handler This allows the programmer's switch to be triggered via the monitor for debugging purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to hold the NMI active for 100ms before releasing it again. Signed-off-by: Mark Cave-Ayland Reviewied-by: Laurent Vivier Message-Id: <20211020134131.4392-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: a56c12fb760a57c1419df4a34e930160f1d8d428 https://github.com/qemu/qemu/commit/a56c12fb760a57c1419df4a34e930160f1d8d428 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: drop 8-bit graphic_depth check for Apple 21 inch display The graphic_depth check is no longer required since commit df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") which introduced code in macfb_common_realize() to only allow the resolutions/depths provided in macfb_mode_table to be specified for each display type. Signed-off-by: Mark Cave-Ayland Fixes: df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") Message-Id: <20211020141810.7875-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 1dafe7656a9c2770065e91208edd4c073f5f98a9 https://github.com/qemu/qemu/commit/1dafe7656a9c2770065e91208edd4c073f5f98a9 Author: Richard Henderson Date: 2021-10-22 (Fri, 22 Oct 2021) Changed paths: M hw/m68k/q800.c M hw/misc/mac_via.c M hw/misc/trace-events M include/hw/misc/mac_via.h Log Message: ----------- Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' into staging Pull request Q800 20211022 GLUE updates for A/UX mode # gpg: Signature made Fri 22 Oct 2021 12:16:29 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier " [full] # gpg: aka "Laurent Vivier " [full] # gpg: aka "Laurent Vivier (Red Hat) " [full] * remotes/vivier-m68k/tags/q800-pull-request: q800: drop 8-bit graphic_depth check for Apple 21 inch display q800: add NMI handler q800: wire up remaining IRQs in classic mode q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode q800: wire up auxmode GPIO to GLUE mac_via: add GPIO for A/UX mode q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs q800: move VIA1 IRQ from level 1 to level 6 mac_via: update comment for VIA1B_vMystery bit Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/78d98bfbd39d...1dafe7656a9c From MAILER-DAEMON Fri Oct 22 12:02:06 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdwzd-0005BX-Vd for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 12:02:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdwzR-00058c-SZ for qemu-commits@nongnu.org; Fri, 22 Oct 2021 12:01:59 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:53179 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdwzN-0007yd-L9 for qemu-commits@nongnu.org; Fri, 22 Oct 2021 12:01:52 -0400 Received: from github.com (hubbernetes-node-7372fda.ac4-iad.github.net [10.52.202.40]) by smtp.github.com (Postfix) with ESMTPA id D4D1452038A for ; Fri, 22 Oct 2021 09:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634918506; bh=sMj1NMWzM0KF7uetqQtALrm4BXIcQdnfacmm21OVLF4=; h=Date:From:To:Subject:From; b=gWLAzV9pg4ipjhUXDU8pEuCJFjsykJDgEBmHjxUYCffUxOLaoN6SN623YULUAw0vQ e0FAlqwe5vAO72H+opi3oTln7g4MLpHNG11xtejZFkTbtgcbPUTgIZazEYrgfav6no dHggIgHUDjS7NMijzuuy7v86s6Q34qoHw99RuqR0= Date: Fri, 22 Oct 2021 09:01:46 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] e97645: mac_via: update comment for VIA1B_vMystery bit X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 16:02:01 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: e976459b3b127838befaef57f1587770452a0827 https://github.com/qemu/qemu/commit/e976459b3b127838befaef57f1587770452a0827 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/misc/mac_via.c Log Message: ----------- mac_via: update comment for VIA1B_vMystery bit According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't particularly descriptive, the patch leaves this to ensure that the constants in mac_via.c remain in sync with Linux's mac_via.h. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 39950b16ecc21bce3bbea3fddcdf1aaefa0d6cef https://github.com/qemu/qemu/commit/39950b16ecc21bce3bbea3fddcdf1aaefa0d6cef Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: move VIA1 IRQ from level 1 to level 6 On a Quadra 800 machine Linux sets via_alt_mapping to 1 and clears port B bit 6 to ensure that the VIA1 IRQ is delivered at level 6 rather than level 1. Even though QEMU doesn't yet emulate this behaviour, Linux still installs the VIA1 level 1 IRQ handler regardless of the value of via_alt_mapping which is why the kernel has been able to boot until now. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 91ff5e4dcd855c6f93b91ef8c5d43b18a1d080d0 https://github.com/qemu/qemu/commit/91ff5e4dcd855c6f93b91ef8c5d43b18a1d080d0 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs In order to allow dynamic routing of IRQs to different IRQ levels on the CPU depending upon port B bit 6, use GLUE IRQ numbers and map them to the the corresponding CPU IRQ level accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 291bc1809a0ec75f283717850003c08953d80e7c https://github.com/qemu/qemu/commit/291bc1809a0ec75f283717850003c08953d80e7c Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/misc/mac_via.c M hw/misc/trace-events M include/hw/misc/mac_via.h Log Message: ----------- mac_via: add GPIO for A/UX mode Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating whether the hardware is configured for A/UX mode. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: a85d18aabdd4632bb0eeb496c97472746ba35d3c https://github.com/qemu/qemu/commit/a85d18aabdd4632bb0eeb496c97472746ba35d3c Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: wire up auxmode GPIO to GLUE This enables the GLUE logic to change its CPU level IRQ routing depending upon whether the hardware has been configured for A/UX mode. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: f7c6e12e24a736f7f3f0bf2c4e34a598e3274130 https://github.com/qemu/qemu/commit/f7c6e12e24a736f7f3f0bf2c4e34a598e3274130 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode When the hardware is operating in classic mode the SONIC on-board Ethernet IRQ is routed to nubus IRQ 9 instead of directly to the CPU at level 3. This does not affect the framebuffer which although it exists in slot 9, has its own dedicated IRQ on the Quadra 800 hardware. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: c7710c1ebf0b316ac0ab517fa8ceaa2824904474 https://github.com/qemu/qemu/commit/c7710c1ebf0b316ac0ab517fa8ceaa2824904474 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: wire up remaining IRQs in classic mode Explicitly wire up the remaining IRQs in classic mode to enable the use of g_assert_not_reached() in the default case to detect any unexpected IRQs. Add a comment explaining the IRQ routing differences in A/UX mode based upon the comments in NetBSD (also noting that at least A/UX 3.0.1 still uses classic mode). Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-Id: <20211020134131.4392-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 3ea74abe2ddfd0741d4aa75484c88b346b85fb26 https://github.com/qemu/qemu/commit/3ea74abe2ddfd0741d4aa75484c88b346b85fb26 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: add NMI handler This allows the programmer's switch to be triggered via the monitor for debugging purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to hold the NMI active for 100ms before releasing it again. Signed-off-by: Mark Cave-Ayland Reviewied-by: Laurent Vivier Message-Id: <20211020134131.4392-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: a56c12fb760a57c1419df4a34e930160f1d8d428 https://github.com/qemu/qemu/commit/a56c12fb760a57c1419df4a34e930160f1d8d428 Author: Mark Cave-Ayland Date: 2021-10-20 (Wed, 20 Oct 2021) Changed paths: M hw/m68k/q800.c Log Message: ----------- q800: drop 8-bit graphic_depth check for Apple 21 inch display The graphic_depth check is no longer required since commit df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") which introduced code in macfb_common_realize() to only allow the resolutions/depths provided in macfb_mode_table to be specified for each display type. Signed-off-by: Mark Cave-Ayland Fixes: df8abbbadf ("macfb: add common monitor modes supported by the MacOS toolbox ROM") Message-Id: <20211020141810.7875-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier Commit: 1dafe7656a9c2770065e91208edd4c073f5f98a9 https://github.com/qemu/qemu/commit/1dafe7656a9c2770065e91208edd4c073f5f98a9 Author: Richard Henderson Date: 2021-10-22 (Fri, 22 Oct 2021) Changed paths: M hw/m68k/q800.c M hw/misc/mac_via.c M hw/misc/trace-events M include/hw/misc/mac_via.h Log Message: ----------- Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' into staging Pull request Q800 20211022 GLUE updates for A/UX mode # gpg: Signature made Fri 22 Oct 2021 12:16:29 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier " [full] # gpg: aka "Laurent Vivier " [full] # gpg: aka "Laurent Vivier (Red Hat) " [full] * remotes/vivier-m68k/tags/q800-pull-request: q800: drop 8-bit graphic_depth check for Apple 21 inch display q800: add NMI handler q800: wire up remaining IRQs in classic mode q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode q800: wire up auxmode GPIO to GLUE mac_via: add GPIO for A/UX mode q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs q800: move VIA1 IRQ from level 1 to level 6 mac_via: update comment for VIA1B_vMystery bit Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/4c127fdbe81d...1dafe7656a9c From MAILER-DAEMON Fri Oct 22 12:08:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdx6J-00050i-IL for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 12:08:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdx6H-0004uJ-FJ for qemu-commits@nongnu.org; Fri, 22 Oct 2021 12:08:57 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:41815 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdx62-00086v-4i for qemu-commits@nongnu.org; Fri, 22 Oct 2021 12:08:56 -0400 Received: from github.com (hubbernetes-node-ace26b3.va3-iad.github.net [10.48.209.66]) by smtp.github.com (Postfix) with ESMTPA id 1075E340B98 for ; Fri, 22 Oct 2021 09:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634918920; bh=++pWksxJiwcJ7UeF1gqvdqPjdLxR2aCuutR+/Z11fzk=; h=Date:From:To:Subject:From; b=a/YP0wydee45QmM4vzUYiTjWhK6KK1NGj0mrwZDa2zaH0Qcqc9GIrvYq12ucrdueX y4LrSKF0zG8lz4SJFV3GIBOxEoduohls8eEqBZx+7ZrHDCoOjWXwHZJ3R9nxi6WmqO CjwDndDMgV0boe7i7TPTFjPv7ThkeXNn0YPaHdfQ= Date: Fri, 22 Oct 2021 09:08:40 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 82b6a3: aspeed: Add support for the fp5280g2-bmc board X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 16:08:57 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 82b6a3f64d6d1ed0d5c455489a9294b59c8de65f=0D https://github.com/qemu/qemu/commit/82b6a3f64d6d1ed0d5c455489a9294b= 59c8de65f=0D Author: John Wang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D =0D Log Message:=0D -----------=0D aspeed: Add support for the fp5280g2-bmc board=0D =0D The fp5280g2-bmc is supported by OpenBMC, It's=0D based on the following device tree=0D =0D https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-b= mc-inspur-fp5280g2.dts=0D =0D Signed-off-by: John Wang =0D Reviewed-by: C=C3=A9dric Le Goater =0D Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: fc6642544eb86b520fed4e3b7792bd89e563de08=0D https://github.com/qemu/qemu/commit/fc6642544eb86b520fed4e3b7792bd8= 9e563de08=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Use a container for the flash mmio address space=0D =0D Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225=0D ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use=0D alias") introduced an alias for the flash mmio region.=0D =0D Using a container is cleaner.=0D =0D Cc: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Francisco Iglesias =0D Message-Id: <20211018132609.160008-5-clg@kaod.org>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: b12fa6118f4d838d19720ec6476a1666a1b43474=0D https://github.com/qemu/qemu/commit/b12fa6118f4d838d19720ec6476a166= 6a1b43474=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/sd/aspeed_sdhci.c=0D M hw/sd/trace-events=0D =0D Log Message:=0D -----------=0D speed/sdhci: Add trace events=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Francisco Iglesias =0D Message-Id: <20211018132609.160008-6-clg@kaod.org>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: eb8f1d57bd754b19da73bb316e80bbaf9b66103a=0D https://github.com/qemu/qemu/commit/eb8f1d57bd754b19da73bb316e80bba= f9b66103a=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M hw/sd/aspeed_sdhci.c=0D M hw/sd/trace-events=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' in= to staging=0D =0D Aspeed patches :=0D =0D * New fp5280g2-bmc board (John)=0D * Small cleanup in Aspeed SMC model (Cedric)=0D =0D # gpg: Signature made Fri 22 Oct 2021 12:55:18 AM PDT=0D # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBE= CA1=0D # gpg: Good signature from "C=C3=A9dric Le Goater " [margin= al]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB = ECA1=0D =0D * remotes/clg/tags/pull-aspeed-20211022:=0D speed/sdhci: Add trace events=0D aspeed/smc: Use a container for the flash mmio address space=0D aspeed: Add support for the fp5280g2-bmc board=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/1dafe7656a9c...eb8f1d57bd75= =0D From MAILER-DAEMON Fri Oct 22 13:36:10 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdySg-0006nY-Kc for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 13:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdySb-0006im-Rj for qemu-commits@nongnu.org; Fri, 22 Oct 2021 13:36:05 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:54409 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdySZ-0007gV-DZ for qemu-commits@nongnu.org; Fri, 22 Oct 2021 13:36:05 -0400 Received: from github.com (hubbernetes-node-11190e4.ac4-iad.github.net [10.52.202.80]) by smtp.github.com (Postfix) with ESMTPA id C1FAC520073 for ; Fri, 22 Oct 2021 10:36:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634924162; bh=56lBUcsRSkYuE6iMw9sJTMTmSR/5y4t0yXBEoKdRr0I=; h=Date:From:To:Subject:From; b=r23ilCQKGE7FdaVmyQ9RpVhv8qNag/DB2R9ZKQoBbICDqOdr1N/4gl4x5Bu6GdFG3 GkQU9bfXrmBjjIu86zv3SiPFzGRW2NiQD8j0TeQkkoRWzgM4m5PIe+asszHBPnB+Bh VDY2Xo9RUHFQIGFoADcL91+lEz1sYGSa/umoe/TE= Date: Fri, 22 Oct 2021 10:36:02 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 82b6a3: aspeed: Add support for the fp5280g2-bmc board X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 17:36:07 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 82b6a3f64d6d1ed0d5c455489a9294b59c8de65f=0D https://github.com/qemu/qemu/commit/82b6a3f64d6d1ed0d5c455489a9294b= 59c8de65f=0D Author: John Wang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D =0D Log Message:=0D -----------=0D aspeed: Add support for the fp5280g2-bmc board=0D =0D The fp5280g2-bmc is supported by OpenBMC, It's=0D based on the following device tree=0D =0D https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-b= mc-inspur-fp5280g2.dts=0D =0D Signed-off-by: John Wang =0D Reviewed-by: C=C3=A9dric Le Goater =0D Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: fc6642544eb86b520fed4e3b7792bd89e563de08=0D https://github.com/qemu/qemu/commit/fc6642544eb86b520fed4e3b7792bd8= 9e563de08=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D aspeed/smc: Use a container for the flash mmio address space=0D =0D Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225=0D ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use=0D alias") introduced an alias for the flash mmio region.=0D =0D Using a container is cleaner.=0D =0D Cc: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: C=C3=A9dric Le Goater =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Francisco Iglesias =0D Message-Id: <20211018132609.160008-5-clg@kaod.org>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: b12fa6118f4d838d19720ec6476a1666a1b43474=0D https://github.com/qemu/qemu/commit/b12fa6118f4d838d19720ec6476a166= 6a1b43474=0D Author: C=C3=A9dric Le Goater =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/sd/aspeed_sdhci.c=0D M hw/sd/trace-events=0D =0D Log Message:=0D -----------=0D speed/sdhci: Add trace events=0D =0D Signed-off-by: C=C3=A9dric Le Goater =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Francisco Iglesias =0D Message-Id: <20211018132609.160008-6-clg@kaod.org>=0D Signed-off-by: C=C3=A9dric Le Goater =0D =0D =0D Commit: eb8f1d57bd754b19da73bb316e80bbaf9b66103a=0D https://github.com/qemu/qemu/commit/eb8f1d57bd754b19da73bb316e80bba= f9b66103a=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/arm/aspeed.c=0D M hw/sd/aspeed_sdhci.c=0D M hw/sd/trace-events=0D M hw/ssi/aspeed_smc.c=0D M include/hw/ssi/aspeed_smc.h=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' in= to staging=0D =0D Aspeed patches :=0D =0D * New fp5280g2-bmc board (John)=0D * Small cleanup in Aspeed SMC model (Cedric)=0D =0D # gpg: Signature made Fri 22 Oct 2021 12:55:18 AM PDT=0D # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBE= CA1=0D # gpg: Good signature from "C=C3=A9dric Le Goater " [margin= al]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB = ECA1=0D =0D * remotes/clg/tags/pull-aspeed-20211022:=0D speed/sdhci: Add trace events=0D aspeed/smc: Use a container for the flash mmio address space=0D aspeed: Add support for the fp5280g2-bmc board=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/1dafe7656a9c...eb8f1d57bd75= =0D From MAILER-DAEMON Fri Oct 22 13:44:40 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdyat-0003nk-TL for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 13:44:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdyar-0003j7-TX for qemu-commits@nongnu.org; Fri, 22 Oct 2021 13:44:37 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:39665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdyal-00021y-Mn for qemu-commits@nongnu.org; Fri, 22 Oct 2021 13:44:36 -0400 Received: from github.com (hubbernetes-node-b1d0cbd.ac4-iad.github.net [10.52.202.70]) by smtp.github.com (Postfix) with ESMTPA id E47DF600A4C for ; Fri, 22 Oct 2021 10:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634924670; bh=I4sys6nq4AMOOQqmTiaJNKNNXmc0/hCPtcr85Hj9PtE=; h=Date:From:To:Subject:From; b=LVHeqVjQZ/cSpkgLEmt4RR+li0a5cL2ZGq99yiqXSaRZX3DhHh3imo6DH3xtjiCNe selXg6qPcWVOVxlMMZkZmbDq6D7EHTyARm+RP9rxcN9kjqQ+YVDJoviehn8VZ7l/RD 8rpTHUrToP3lBgiR+V9Qxyiqg90rtDoPMgVcQvxY= Date: Fri, 22 Oct 2021 10:44:30 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] b4b9a0: update seabios to master branch snapshot X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 17:44:38 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: b4b9a0e32f93c0700f46617524317b0580126592=0D https://github.com/qemu/qemu/commit/b4b9a0e32f93c0700f46617524317b0= 580126592=0D Author: Gerd Hoffmann =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M roms/seabios=0D =0D Log Message:=0D -----------=0D update seabios to master branch snapshot=0D =0D A new seabios release is planned for november.=0D =0D Update to a master branch snapshot, to=0D (a) increase test coverage of the changes.=0D (b) make the delta smaller when updating to the final=0D release during the qemu 6.2 freeze.=0D =0D Most noteworthy this fixes the nvme boot regression caused=0D by adding namespace support to the qemu nvme emulation.=0D =0D seabios shortlog=0D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D =0D Alex Martens via SeaBIOS (1):=0D nvme: fix missing newline on sq full print=0D =0D Alexander Graf (4):=0D nvme: Record maximum allowed request size=0D nvme: Allow to set PRP2=0D nvme: Pass large I/O requests as PRP lists=0D nvme: Split requests by maximum allowed size=0D =0D Daniel P. Berrang=C3=A9 (1):=0D smbios: avoid integer overflow when adding SMBIOS type 0 table=0D =0D David Woodhouse (1):=0D nvme: Clean up nvme_cmd_readwrite()=0D =0D Gerd Hoffmann (9):=0D output: add support for uppercase hex numbers=0D dsdt: add support for pnp ids as strings=0D usb: add boot prio support for mmio host adapters=0D usb/xhci: split xhci setup into generic and pci parts=0D usb/xhci: add support for mmio host adapters (via acpi).=0D usb boot: add xhci mmio example=0D nvme: improve namespace allocation=0D nvme: drive desc should not include the newline=0D Increase BUILD_MIN_BIOSTABLE for large roms=0D =0D Matt DeVillier (1):=0D usb.c: Fix devices using non-primary interface descriptor=0D =0D Mike Banon (1):=0D Support booting USB drives with a write protect switch enabled=0D =0D Sergei Trofimovich (1):=0D vgasrc: ignore .node.gnu.property (binutils-2.36 support)=0D =0D Stefan Berger (4):=0D tcgbios: Fix details in log entries=0D Add implementations for sha256, sha384, and sha512=0D tcgbios: Use The proper sha function for each PCR bank=0D tcgbios: Disable platform hierarchy in case of failure=0D =0D Stefan Ott via SeaBIOS (1):=0D usb-hid: Increase MAX_KBD_EVENT=0D =0D Volker R=C3=BCmelin (2):=0D stacks: call check_irqs() in run_thread()=0D stacks: call check_irqs() after switch_next()=0D =0D weitaowang-oc@zhaoxin.com (1):=0D USB:Fix xHCI initail fail by using longer reset and CNR clear timeo= ut value=0D =0D Signed-off-by: Gerd Hoffmann =0D =0D =0D Commit: 9fb3fcfce512da58cd048eaefd293e1d3f513de2=0D https://github.com/qemu/qemu/commit/9fb3fcfce512da58cd048eaefd293e1= d3f513de2=0D Author: Gerd Hoffmann =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M pc-bios/bios-256k.bin=0D M pc-bios/bios-microvm.bin=0D M pc-bios/bios.bin=0D M pc-bios/vgabios-ati.bin=0D M pc-bios/vgabios-bochs-display.bin=0D M pc-bios/vgabios-cirrus.bin=0D M pc-bios/vgabios-qxl.bin=0D M pc-bios/vgabios-ramfb.bin=0D M pc-bios/vgabios-stdvga.bin=0D M pc-bios/vgabios-virtio.bin=0D M pc-bios/vgabios-vmware.bin=0D M pc-bios/vgabios.bin=0D =0D Log Message:=0D -----------=0D update seabios binaries=0D =0D Signed-off-by: Gerd Hoffmann =0D =0D =0D Commit: 2c64ff92ecef4db0169f7238a26f1124268345c8=0D https://github.com/qemu/qemu/commit/2c64ff92ecef4db0169f7238a26f112= 4268345c8=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M pc-bios/bios-256k.bin=0D M pc-bios/bios-microvm.bin=0D M pc-bios/bios.bin=0D M pc-bios/vgabios-ati.bin=0D M pc-bios/vgabios-bochs-display.bin=0D M pc-bios/vgabios-cirrus.bin=0D M pc-bios/vgabios-qxl.bin=0D M pc-bios/vgabios-ramfb.bin=0D M pc-bios/vgabios-stdvga.bin=0D M pc-bios/vgabios-virtio.bin=0D M pc-bios/vgabios-vmware.bin=0D M pc-bios/vgabios.bin=0D M roms/seabios=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20211022-pull= -request' into staging=0D =0D seabios: update to master branch snapshot.=0D =0D # gpg: Signature made Fri 22 Oct 2021 05:14:00 AM PDT=0D # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87= 138=0D # gpg: Good signature from "Gerd Hoffmann (work) " [fu= ll]=0D # gpg: aka "Gerd Hoffmann " [full]=0D # gpg: aka "Gerd Hoffmann (private) " [= full]=0D =0D * remotes/kraxel/tags/seabios-20211022-pull-request:=0D update seabios binaries=0D update seabios to master branch snapshot=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/eb8f1d57bd75...2c64ff92ecef= =0D From MAILER-DAEMON Fri Oct 22 15:06:18 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdzru-0007Ek-BP for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 15:06:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdzrs-0007Du-Cx for qemu-commits@nongnu.org; Fri, 22 Oct 2021 15:06:16 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:59455) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdzrq-0004ue-HM for qemu-commits@nongnu.org; Fri, 22 Oct 2021 15:06:15 -0400 Received: from github.com (hubbernetes-node-249d1bb.ash1-iad.github.net [10.56.113.22]) by smtp.github.com (Postfix) with ESMTPA id D7C509011D6 for ; Fri, 22 Oct 2021 12:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634929573; bh=thsKhYIGa5QutGM+qpaZY/w2UL+hQ0LSO77Gdfy4qQs=; h=Date:From:To:Subject:From; b=XWwOLDXxYNmCyW9Lt81jHOtX66XuDuKUdX0D4ZeDbVmEsXRKhRL/+qvlLBQLE8Czz /E3bVotsiiMNxcMz9dQy9Rzmqu8HbAWUuxV+7OiYrQ1JWi3skC8FyCl0fxYw3GHDBT vRVHPap5CH1ibZdEZHA7g+TsrsLesUrwCoc016yw= Date: Fri, 22 Oct 2021 12:06:13 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] b4b9a0: update seabios to master branch snapshot X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 19:06:16 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: b4b9a0e32f93c0700f46617524317b0580126592=0D https://github.com/qemu/qemu/commit/b4b9a0e32f93c0700f46617524317b0= 580126592=0D Author: Gerd Hoffmann =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M roms/seabios=0D =0D Log Message:=0D -----------=0D update seabios to master branch snapshot=0D =0D A new seabios release is planned for november.=0D =0D Update to a master branch snapshot, to=0D (a) increase test coverage of the changes.=0D (b) make the delta smaller when updating to the final=0D release during the qemu 6.2 freeze.=0D =0D Most noteworthy this fixes the nvme boot regression caused=0D by adding namespace support to the qemu nvme emulation.=0D =0D seabios shortlog=0D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D =0D Alex Martens via SeaBIOS (1):=0D nvme: fix missing newline on sq full print=0D =0D Alexander Graf (4):=0D nvme: Record maximum allowed request size=0D nvme: Allow to set PRP2=0D nvme: Pass large I/O requests as PRP lists=0D nvme: Split requests by maximum allowed size=0D =0D Daniel P. Berrang=C3=A9 (1):=0D smbios: avoid integer overflow when adding SMBIOS type 0 table=0D =0D David Woodhouse (1):=0D nvme: Clean up nvme_cmd_readwrite()=0D =0D Gerd Hoffmann (9):=0D output: add support for uppercase hex numbers=0D dsdt: add support for pnp ids as strings=0D usb: add boot prio support for mmio host adapters=0D usb/xhci: split xhci setup into generic and pci parts=0D usb/xhci: add support for mmio host adapters (via acpi).=0D usb boot: add xhci mmio example=0D nvme: improve namespace allocation=0D nvme: drive desc should not include the newline=0D Increase BUILD_MIN_BIOSTABLE for large roms=0D =0D Matt DeVillier (1):=0D usb.c: Fix devices using non-primary interface descriptor=0D =0D Mike Banon (1):=0D Support booting USB drives with a write protect switch enabled=0D =0D Sergei Trofimovich (1):=0D vgasrc: ignore .node.gnu.property (binutils-2.36 support)=0D =0D Stefan Berger (4):=0D tcgbios: Fix details in log entries=0D Add implementations for sha256, sha384, and sha512=0D tcgbios: Use The proper sha function for each PCR bank=0D tcgbios: Disable platform hierarchy in case of failure=0D =0D Stefan Ott via SeaBIOS (1):=0D usb-hid: Increase MAX_KBD_EVENT=0D =0D Volker R=C3=BCmelin (2):=0D stacks: call check_irqs() in run_thread()=0D stacks: call check_irqs() after switch_next()=0D =0D weitaowang-oc@zhaoxin.com (1):=0D USB:Fix xHCI initail fail by using longer reset and CNR clear timeo= ut value=0D =0D Signed-off-by: Gerd Hoffmann =0D =0D =0D Commit: 9fb3fcfce512da58cd048eaefd293e1d3f513de2=0D https://github.com/qemu/qemu/commit/9fb3fcfce512da58cd048eaefd293e1= d3f513de2=0D Author: Gerd Hoffmann =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M pc-bios/bios-256k.bin=0D M pc-bios/bios-microvm.bin=0D M pc-bios/bios.bin=0D M pc-bios/vgabios-ati.bin=0D M pc-bios/vgabios-bochs-display.bin=0D M pc-bios/vgabios-cirrus.bin=0D M pc-bios/vgabios-qxl.bin=0D M pc-bios/vgabios-ramfb.bin=0D M pc-bios/vgabios-stdvga.bin=0D M pc-bios/vgabios-virtio.bin=0D M pc-bios/vgabios-vmware.bin=0D M pc-bios/vgabios.bin=0D =0D Log Message:=0D -----------=0D update seabios binaries=0D =0D Signed-off-by: Gerd Hoffmann =0D =0D =0D Commit: 2c64ff92ecef4db0169f7238a26f1124268345c8=0D https://github.com/qemu/qemu/commit/2c64ff92ecef4db0169f7238a26f112= 4268345c8=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M pc-bios/bios-256k.bin=0D M pc-bios/bios-microvm.bin=0D M pc-bios/bios.bin=0D M pc-bios/vgabios-ati.bin=0D M pc-bios/vgabios-bochs-display.bin=0D M pc-bios/vgabios-cirrus.bin=0D M pc-bios/vgabios-qxl.bin=0D M pc-bios/vgabios-ramfb.bin=0D M pc-bios/vgabios-stdvga.bin=0D M pc-bios/vgabios-virtio.bin=0D M pc-bios/vgabios-vmware.bin=0D M pc-bios/vgabios.bin=0D M roms/seabios=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20211022-pull= -request' into staging=0D =0D seabios: update to master branch snapshot.=0D =0D # gpg: Signature made Fri 22 Oct 2021 05:14:00 AM PDT=0D # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87= 138=0D # gpg: Good signature from "Gerd Hoffmann (work) " [fu= ll]=0D # gpg: aka "Gerd Hoffmann " [full]=0D # gpg: aka "Gerd Hoffmann (private) " [= full]=0D =0D * remotes/kraxel/tags/seabios-20211022-pull-request:=0D update seabios binaries=0D update seabios to master branch snapshot=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/eb8f1d57bd75...2c64ff92ecef= =0D From MAILER-DAEMON Fri Oct 22 15:15:02 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1me00M-0001KU-65 for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 15:15:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1me00K-0001Jq-Bf for qemu-commits@nongnu.org; Fri, 22 Oct 2021 15:15:00 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:45963 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1me00G-00033r-3N for qemu-commits@nongnu.org; Fri, 22 Oct 2021 15:14:59 -0400 Received: from github.com (hubbernetes-node-77c3ba1.ac4-iad.github.net [10.52.125.21]) by smtp.github.com (Postfix) with ESMTPA id D7EC7520A40 for ; Fri, 22 Oct 2021 12:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634930094; bh=1CjeEb6J4n7DO0jokHkMt52k0Aa+jMtactRv2LX/qE0=; h=Date:From:To:Subject:From; b=kDfny7cCEUYYPrrYzN5TVpcFoxvlzXDpNHk1sdWouky1hphdl5tMBUraaZA35r4ND pSME5beT6ecB5MojdBAKi/H+yz2/fZCpyQtXVwUy85l9dh/IbUlxaIKpNCi2TbHr+R KmBs1gDDsN2spNvvKRFSzJQJvZzYmUu6oufXAC/8= Date: Fri, 22 Oct 2021 12:14:54 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c672f1: target/riscv: Pass the same value to oprsz and max... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 19:15:00 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: c672f19f328922eff4963b0b61fbdcfa661e1c06=0D https://github.com/qemu/qemu/commit/c672f19f328922eff4963b0b61fbdcf= a661e1c06=0D Author: Frank Chang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v=0D =0D oprsz and maxsz are passed with the same value in commit: eee2d61e202.=0D= However, vmv.v.v was missed in that commit and should pass the same=0D value as well in its tcg_gen_gvec_2_ptr() call.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Message-id: 20211007081803.1705656-1-frank.chang@sifive.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e573a7f325e4d66d1005f7bb80d51ce95f307951=0D https://github.com/qemu/qemu/commit/e573a7f325e4d66d1005f7bb80d51ce= 95f307951=0D Author: Travis Geiselbrecht =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: line up all of the registers in the info register dump=0D= =0D Ensure the columns for all of the register names and values line up.=0D No functional change, just a minor tweak to the output.=0D =0D Signed-off-by: Travis Geiselbrecht =0D Reviewed-by: Alistair Francis =0D Message-id: 20211009055019.545153-1-travisg@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 54c17609372bb119575f3bb7309ea57fc1a58d1d=0D https://github.com/qemu/qemu/commit/54c17609372bb119575f3bb7309ea57= fc1a58d1d=0D Author: Philipp Tomsich =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Fix orc.b implementation=0D =0D The earlier implementation fell into a corner case for bytes that were=0D= 0x01, giving a wrong result (but not affecting our application test=0D cases for strings, as an ASCII value 0x01 is rare in those...).=0D =0D This changes the algorithm to:=0D 1. Mask out the high-bit of each bytes (so that each byte is <=3D 127).=0D= 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will ove= rflow=0D into the highest bit of each byte).=0D 3. Bitwise-or the original value back in (to cover those cases where the= =0D source byte was exactly 128) to saturate the high-bit.=0D 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB o= f=0D each byte into its LSB.=0D 5. Multiply with 0xff to fan out the LSB to all bits of each byte.=0D =0D Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing= gorc/gorci")=0D =0D Signed-off-by: Philipp Tomsich =0D Reported-by: Vincent Palatin =0D Tested-by: Vincent Palatin =0D Reviewed-by: Richard Henderson =0D Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 03fd0c5fe98f5617076527e9783d030294b64d6d=0D https://github.com/qemu/qemu/commit/03fd0c5fe98f5617076527e9783d030= 294b64d6d=0D Author: Mingwang Li =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Use machine->ram as the system memory=0D =0D If default main_mem is used to be registered as the system memory,=0D other memory cannot be initialized. Therefore, the system memory=0D should be initialized to the machine->ram, which consists of the=0D default main_mem and other possible memory required by applications,=0D such as shared hugepage memory in DPDK.=0D =0D Also, the mc->defaul_ram_id should be set to the default main_mem,=0D such as "riscv_virt_board.ram" for the virt machine.=0D =0D Signed-off-by: Mingwang Li =0D Signed-off-by: Yifei Jiang =0D Reviewed-by: Alistair Francis =0D Message-id: 20211016030908.40480-1-limingwang@huawei.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 61d56494884b0d4bbf78d0561258b3548dea3390=0D https://github.com/qemu/qemu/commit/61d56494884b0d4bbf78d0561258b35= 48dea3390=0D Author: Frank Chang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh=0D =0D TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in=0D commit: c445593, but other TB_FLAGS bits for rvv and rvh were=0D not shift as well so these bits may overlap with each other when=0D rvv is enabled.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 31dbcff713aa297033a008b5188fbb37abf85f36=0D https://github.com/qemu/qemu/commit/31dbcff713aa297033a008b5188fbb3= 7abf85f36=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Remove some unused macros=0D =0D Since commit 1a9540d1f1a=0D ("target/riscv: Drop support for ISA spec version 1.09.1")=0D these definitions are unused, remove them.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Frank Chang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 9d3d60b704f48217cf9b38b883cc15c40f76f286=0D https://github.com/qemu/qemu/commit/9d3d60b704f48217cf9b38b883cc15c= 40f76f286=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Organise the CPU properties=0D =0D Organise the CPU properties so that standard extensions come first=0D then followed by experimental extensions.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Frank Chang =0D Reviewed-by: Bin Meng =0D Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 53677acf25afa8e529d7f81a6ae9a03d15c72713=0D https://github.com/qemu/qemu/commit/53677acf25afa8e529d7f81a6ae9a03= d15c72713=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: Move cpu_get_tb_cpu_state out of line=0D =0D Move the function to cpu_helper.c, as it is large and growing.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-2-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 99bc874fb3a0709c36ae4e594a1262ce1660e698=0D https://github.com/qemu/qemu/commit/99bc874fb3a0709c36ae4e594a1262c= e1660e698=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Create RISCVMXL enumeration=0D =0D Move the MXL_RV* defines to enumerators.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-3-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e91a7227cb802ea62ffa14707ebc2f588b01213d=0D https://github.com/qemu/qemu/commit/e91a7227cb802ea62ffa14707ebc2f5= 88b01213d=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M linux-user/riscv/cpu_loop.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/machine.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Split misa.mxl and misa.ext=0D =0D The hw representation of misa.mxl is at the high bits of the=0D misa csr. Representing this in the same way inside QEMU=0D results in overly complex code trying to check that field.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-4-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: db23e5d981ab22da0bfe1150f4828d08484b1fba=0D https://github.com/qemu/qemu/commit/db23e5d981ab22da0bfe1150f4828d0= 8484b1fba=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/boot.c=0D M semihosting/arm-compat-semi.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/monitor.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl=0D =0D Shortly, the set of supported XL will not be just 32 and 64,=0D and representing that properly using the enumeration will be=0D imperative.=0D =0D Two places, booting and gdb, intentionally use misa_mxl_max=0D to emphasize the use of the reset value of misa.mxl, and not=0D the current cpu state.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-5-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 92371bd9033e5a50a7541d96ff8ad067930a4f93=0D https://github.com/qemu/qemu/commit/92371bd9033e5a50a7541d96ff8ad06= 7930a4f93=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add MXL/SXL/UXL to TB_FLAGS=0D =0D Begin adding support for switching XLEN at runtime. Extract the=0D effective XLEN from MISA and MSTATUS and store for use during translation= .=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-6-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fbb48032e46976cfc94a90a4233a2060fdc36a4e=0D https://github.com/qemu/qemu/commit/fbb48032e46976cfc94a90a4233a206= 0fdc36a4e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Use REQUIRE_64BIT in amo_check64=0D =0D Use the same REQUIRE_64BIT check that we use elsewhere,=0D rather than open-coding the use of is_32bit.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-7-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 4e97d459a0f2b92815c2c2c6eb96b75e2235b42e=0D https://github.com/qemu/qemu/commit/4e97d459a0f2b92815c2c2c6eb96b75= e2235b42e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Properly check SEW in amo_op=0D =0D We're currently assuming SEW <=3D 3, and the "else" from=0D the SEW =3D=3D 3 must be less. Use a switch and explicitly=0D bound both SEW and SEQ for all cases.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-8-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 905b9fcde1fb84d718d95369c5d886bc81bbdd8e=0D https://github.com/qemu/qemu/commit/905b9fcde1fb84d718d95369c5d886b= c81bbdd8e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace is_32bit with get_xl/get_xlen=0D =0D In preparation for RV128, replace a simple predicate=0D with a more versatile test.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-9-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 7667cafd5a0d173d1853b4d8414d4a98df1374dc=0D https://github.com/qemu/qemu/commit/7667cafd5a0d173d1853b4d8414d4a9= 8df1374dc=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace DisasContext.w with DisasContext.ol=0D =0D In preparation for RV128, consider more than just "w" for=0D operand size modification. This will be used for the "d"=0D insns from RV128 as well.=0D =0D Rename oper_len to get_olen to better match get_xlen.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-10-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 80347ae9f26dfafbd358d7d8d9ad175a2a624365=0D https://github.com/qemu/qemu/commit/80347ae9f26dfafbd358d7d8d9ad175= a2a624365=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_arith_per_ol for RVM=0D =0D The multiply high-part instructions require a separate=0D implementation for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-11-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 673be37163cb44d2e1699503ccd065e9d13d4db7=0D https://github.com/qemu/qemu/commit/673be37163cb44d2e1699503ccd065e= 9d13d4db7=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Adjust trans_rev8_32 for riscv64=0D =0D When target_long is 64-bit, we still want a 32-bit bswap for rev8.=0D Since this opcode is specific to RV32, we need not conditionalize.=0D =0D Acked-by: Alistair Francis =0D Reviewed-by: LIU Zhiwei =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-12-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fdab665f6e9d0919bbbab88b16ae2c4be1bf61c6=0D https://github.com/qemu/qemu/commit/fdab665f6e9d0919bbbab88b16ae2c4= be1bf61c6=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_unary_per_ol for RVB=0D =0D The count zeros instructions require a separate implementation=0D for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-13-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a0245d91dd1ca33ecde8c430ac6986dbd90a84db=0D https://github.com/qemu/qemu/commit/a0245d91dd1ca33ecde8c430ac6986d= bd90a84db=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_shift*_per_ol for RVB, RVI=0D =0D Most shift instructions require a separate implementation=0D for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-14-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 665b90d8a4aa7d90bbeee9ff279e37edcd573635=0D https://github.com/qemu/qemu/commit/665b90d8a4aa7d90bbeee9ff279e37e= dcd573635=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use riscv_csrrw_debug for cpu_dump=0D =0D Use the official debug read interface to the csrs,=0D rather than referencing the env slots directly.=0D Put the list of csrs to dump into a table.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-15-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b550f89457ef5022231f8255ae1a6ba496c492b1=0D https://github.com/qemu/qemu/commit/b550f89457ef5022231f8255ae1a6ba= 496c492b1=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Compute mstatus.sd on demand=0D =0D The position of this read-only field is dependent on the current xlen.=0D= Rather than having to compute that difference in many places, compute=0D it only on read.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-16-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: ef6310064820183cce7c5969cae293e680c57679=0D https://github.com/qemu/qemu/commit/ef6310064820183cce7c5969cae293e= 680c57679=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D M include/hw/riscv/opentitan.h=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Update to the latest build=0D =0D Update the OpenTitan machine model to match the latest OpenTitan FPGA=0D design.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 434e7e0217d73c20f60bd52437d0a0ba8a3c6247=0D https://github.com/qemu/qemu/commit/434e7e0217d73c20f60bd52437d0a0b= a8a3c6247=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D R hw/intc/ibex_plic.c=0D M hw/intc/meson.build=0D =0D Log Message:=0D -----------=0D hw/intc: Remove the Ibex PLIC=0D =0D The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and=0D instead use the SiFive PLIC.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d8c6590f183cd93956b7a458d212778a143b89c8=0D https://github.com/qemu/qemu/commit/d8c6590f183cd93956b7a458d212778= a143b89c8=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Move the properties=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d680ff664e1c7e097922f62fef824027b8fb711a=0D https://github.com/qemu/qemu/commit/d680ff664e1c7e097922f62fef82402= 7b8fb711a=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Cleanup the realize function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 8d3dae162e61e6c71bbd3d9878cd1768ae9dd989=0D https://github.com/qemu/qemu/commit/8d3dae162e61e6c71bbd3d9878cd176= 8ae9dd989=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Cleanup the irq_request function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d4c624f482778cfe91938996a588df2df0e70f20=0D https://github.com/qemu/qemu/commit/d4c624f482778cfe91938996a588df2= df0e70f20=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/microchip_pfsoc.c=0D =0D Log Message:=0D -----------=0D hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::defa= ult_ram_id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 91b1fbdc0cca11ac23ddc61ee3ea0e9706b645cf=0D https://github.com/qemu/qemu/commit/91b1fbdc0cca11ac23ddc61ee3ea0e9= 706b645cf=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ra= m_id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D While at it add check for user supplied RAM size and error out if it=0D mismatches board expected value.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 56917307f4780535d319dedc8973361a5da76f7b=0D https://github.com/qemu/qemu/commit/56917307f4780535d319dedc8973361= a5da76f7b=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/shakti_c.c=0D =0D Log Message:=0D -----------=0D hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e2b3ef75445fc2342b00680dad7af3618dc69deb=0D https://github.com/qemu/qemu/commit/e2b3ef75445fc2342b00680dad7af36= 18dc69deb=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_e.c=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D While at it add check for user supplied RAM size and error out if it=0D mismatches board expected value.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: c188a9c4f78e21f7f979ab7ef19c5bf21e9dcf08=0D https://github.com/qemu/qemu/commit/c188a9c4f78e21f7f979ab7ef19c5bf= 21e9dcf08=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_u.c=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 11ec06f9eaedc801ded34c79861367b76ab2b731=0D https://github.com/qemu/qemu/commit/11ec06f9eaedc801ded34c79861367b= 76ab2b731=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/spike.c=0D =0D Log Message:=0D -----------=0D hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id= =0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 660efed8b37aedec9b5fcc555da1f88f7d12c98a=0D https://github.com/qemu/qemu/commit/660efed8b37aedec9b5fcc555da1f88= f7d12c98a=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D R hw/intc/ibex_plic.c=0D M hw/intc/meson.build=0D M hw/intc/sifive_plic.c=0D M hw/riscv/boot.c=0D M hw/riscv/microchip_pfsoc.c=0D M hw/riscv/opentitan.c=0D M hw/riscv/shakti_c.c=0D M hw/riscv/sifive_e.c=0D M hw/riscv/sifive_u.c=0D M hw/riscv/spike.c=0D M hw/riscv/virt.c=0D M include/hw/riscv/opentitan.h=0D M linux-user/elfload.c=0D M linux-user/riscv/cpu_loop.c=0D M semihosting/arm-compat-semi.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/machine.c=0D M target/riscv/monitor.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211022-2' into staging=0D =0D Fourth RISC-V PR for QEMU 6.2=0D =0D - Vector extension bug fixes=0D - Bit manipulation extension bug fix=0D - Support vhost-user and numa mem options on all boards=0D - Rationalise XLEN and operand lengths=0D - Bump the OpenTitan FPGA support=0D - Remove the Ibex PLIC=0D - General code cleanup=0D =0D # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits)=0D= hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id= =0D hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ra= m_id=0D hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::defa= ult_ram_id=0D hw/intc: sifive_plic: Cleanup the irq_request function=0D hw/intc: sifive_plic: Cleanup the realize function=0D hw/intc: sifive_plic: Move the properties=0D hw/intc: Remove the Ibex PLIC=0D hw/riscv: opentitan: Update to the latest build=0D target/riscv: Compute mstatus.sd on demand=0D target/riscv: Use riscv_csrrw_debug for cpu_dump=0D target/riscv: Use gen_shift*_per_ol for RVB, RVI=0D target/riscv: Use gen_unary_per_ol for RVB=0D target/riscv: Adjust trans_rev8_32 for riscv64=0D target/riscv: Use gen_arith_per_ol for RVM=0D target/riscv: Replace DisasContext.w with DisasContext.ol=0D target/riscv: Replace is_32bit with get_xl/get_xlen=0D target/riscv: Properly check SEW in amo_op=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/2c64ff92ecef...660efed8b37a= =0D From MAILER-DAEMON Fri Oct 22 17:39:41 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1me2GK-0004Ci-C1 for mharc-qemu-commits@gnu.org; Fri, 22 Oct 2021 17:39:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1me2GG-0004BU-Tn for qemu-commits@nongnu.org; Fri, 22 Oct 2021 17:39:36 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:48441 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1me2GD-0002Tg-BZ for qemu-commits@nongnu.org; Fri, 22 Oct 2021 17:39:36 -0400 Received: from github.com (hubbernetes-node-1fbe417.ash1-iad.github.net [10.56.120.39]) by smtp.github.com (Postfix) with ESMTPA id B2D825E0948 for ; Fri, 22 Oct 2021 14:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1634938772; bh=Bn4zIWMCI3+ndau1LwNINIPEe7+vEzr5Ej7FFmqQTxc=; h=Date:From:To:Subject:From; b=OOU6Woq1ydGUWaSZWBF9JzpFpqdd7RY5730RgVVnTwryyDWvmNeV8WvJ65LpF+JWd lB6oIqbTe246SVm1sG6YaP3FwPy5PLz+31H7YOaBn6vaKZhTRFv2X4msvhYyyGWcpz 1ScvUSkx17lSswbY9tsIpFg6srqylLJ+mS0oL2Fo= Date: Fri, 22 Oct 2021 14:39:32 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c672f1: target/riscv: Pass the same value to oprsz and max... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Oct 2021 21:39:37 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: c672f19f328922eff4963b0b61fbdcfa661e1c06=0D https://github.com/qemu/qemu/commit/c672f19f328922eff4963b0b61fbdcf= a661e1c06=0D Author: Frank Chang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v=0D =0D oprsz and maxsz are passed with the same value in commit: eee2d61e202.=0D= However, vmv.v.v was missed in that commit and should pass the same=0D value as well in its tcg_gen_gvec_2_ptr() call.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Message-id: 20211007081803.1705656-1-frank.chang@sifive.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e573a7f325e4d66d1005f7bb80d51ce95f307951=0D https://github.com/qemu/qemu/commit/e573a7f325e4d66d1005f7bb80d51ce= 95f307951=0D Author: Travis Geiselbrecht =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: line up all of the registers in the info register dump=0D= =0D Ensure the columns for all of the register names and values line up.=0D No functional change, just a minor tweak to the output.=0D =0D Signed-off-by: Travis Geiselbrecht =0D Reviewed-by: Alistair Francis =0D Message-id: 20211009055019.545153-1-travisg@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 54c17609372bb119575f3bb7309ea57fc1a58d1d=0D https://github.com/qemu/qemu/commit/54c17609372bb119575f3bb7309ea57= fc1a58d1d=0D Author: Philipp Tomsich =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Fix orc.b implementation=0D =0D The earlier implementation fell into a corner case for bytes that were=0D= 0x01, giving a wrong result (but not affecting our application test=0D cases for strings, as an ASCII value 0x01 is rare in those...).=0D =0D This changes the algorithm to:=0D 1. Mask out the high-bit of each bytes (so that each byte is <=3D 127).=0D= 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will ove= rflow=0D into the highest bit of each byte).=0D 3. Bitwise-or the original value back in (to cover those cases where the= =0D source byte was exactly 128) to saturate the high-bit.=0D 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB o= f=0D each byte into its LSB.=0D 5. Multiply with 0xff to fan out the LSB to all bits of each byte.=0D =0D Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing= gorc/gorci")=0D =0D Signed-off-by: Philipp Tomsich =0D Reported-by: Vincent Palatin =0D Tested-by: Vincent Palatin =0D Reviewed-by: Richard Henderson =0D Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 03fd0c5fe98f5617076527e9783d030294b64d6d=0D https://github.com/qemu/qemu/commit/03fd0c5fe98f5617076527e9783d030= 294b64d6d=0D Author: Mingwang Li =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Use machine->ram as the system memory=0D =0D If default main_mem is used to be registered as the system memory,=0D other memory cannot be initialized. Therefore, the system memory=0D should be initialized to the machine->ram, which consists of the=0D default main_mem and other possible memory required by applications,=0D such as shared hugepage memory in DPDK.=0D =0D Also, the mc->defaul_ram_id should be set to the default main_mem,=0D such as "riscv_virt_board.ram" for the virt machine.=0D =0D Signed-off-by: Mingwang Li =0D Signed-off-by: Yifei Jiang =0D Reviewed-by: Alistair Francis =0D Message-id: 20211016030908.40480-1-limingwang@huawei.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 61d56494884b0d4bbf78d0561258b3548dea3390=0D https://github.com/qemu/qemu/commit/61d56494884b0d4bbf78d0561258b35= 48dea3390=0D Author: Frank Chang =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh=0D =0D TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in=0D commit: c445593, but other TB_FLAGS bits for rvv and rvh were=0D not shift as well so these bits may overlap with each other when=0D rvv is enabled.=0D =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 31dbcff713aa297033a008b5188fbb37abf85f36=0D https://github.com/qemu/qemu/commit/31dbcff713aa297033a008b5188fbb3= 7abf85f36=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Remove some unused macros=0D =0D Since commit 1a9540d1f1a=0D ("target/riscv: Drop support for ISA spec version 1.09.1")=0D these definitions are unused, remove them.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Frank Chang =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 9d3d60b704f48217cf9b38b883cc15c40f76f286=0D https://github.com/qemu/qemu/commit/9d3d60b704f48217cf9b38b883cc15c= 40f76f286=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Organise the CPU properties=0D =0D Organise the CPU properties so that standard extensions come first=0D then followed by experimental extensions.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Frank Chang =0D Reviewed-by: Bin Meng =0D Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 53677acf25afa8e529d7f81a6ae9a03d15c72713=0D https://github.com/qemu/qemu/commit/53677acf25afa8e529d7f81a6ae9a03= d15c72713=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: Move cpu_get_tb_cpu_state out of line=0D =0D Move the function to cpu_helper.c, as it is large and growing.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-2-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 99bc874fb3a0709c36ae4e594a1262ce1660e698=0D https://github.com/qemu/qemu/commit/99bc874fb3a0709c36ae4e594a1262c= e1660e698=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Create RISCVMXL enumeration=0D =0D Move the MXL_RV* defines to enumerators.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-3-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e91a7227cb802ea62ffa14707ebc2f588b01213d=0D https://github.com/qemu/qemu/commit/e91a7227cb802ea62ffa14707ebc2f5= 88b01213d=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M linux-user/elfload.c=0D M linux-user/riscv/cpu_loop.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/machine.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Split misa.mxl and misa.ext=0D =0D The hw representation of misa.mxl is at the high bits of the=0D misa csr. Representing this in the same way inside QEMU=0D results in overly complex code trying to check that field.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-4-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: db23e5d981ab22da0bfe1150f4828d08484b1fba=0D https://github.com/qemu/qemu/commit/db23e5d981ab22da0bfe1150f4828d0= 8484b1fba=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/boot.c=0D M semihosting/arm-compat-semi.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/monitor.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl=0D =0D Shortly, the set of supported XL will not be just 32 and 64,=0D and representing that properly using the enumeration will be=0D imperative.=0D =0D Two places, booting and gdb, intentionally use misa_mxl_max=0D to emphasize the use of the reset value of misa.mxl, and not=0D the current cpu state.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-5-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 92371bd9033e5a50a7541d96ff8ad067930a4f93=0D https://github.com/qemu/qemu/commit/92371bd9033e5a50a7541d96ff8ad06= 7930a4f93=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add MXL/SXL/UXL to TB_FLAGS=0D =0D Begin adding support for switching XLEN at runtime. Extract the=0D effective XLEN from MISA and MSTATUS and store for use during translation= .=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-6-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fbb48032e46976cfc94a90a4233a2060fdc36a4e=0D https://github.com/qemu/qemu/commit/fbb48032e46976cfc94a90a4233a206= 0fdc36a4e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Use REQUIRE_64BIT in amo_check64=0D =0D Use the same REQUIRE_64BIT check that we use elsewhere,=0D rather than open-coding the use of is_32bit.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-7-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 4e97d459a0f2b92815c2c2c6eb96b75e2235b42e=0D https://github.com/qemu/qemu/commit/4e97d459a0f2b92815c2c2c6eb96b75= e2235b42e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Properly check SEW in amo_op=0D =0D We're currently assuming SEW <=3D 3, and the "else" from=0D the SEW =3D=3D 3 must be less. Use a switch and explicitly=0D bound both SEW and SEQ for all cases.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-8-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 905b9fcde1fb84d718d95369c5d886bc81bbdd8e=0D https://github.com/qemu/qemu/commit/905b9fcde1fb84d718d95369c5d886b= c81bbdd8e=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace is_32bit with get_xl/get_xlen=0D =0D In preparation for RV128, replace a simple predicate=0D with a more versatile test.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-9-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 7667cafd5a0d173d1853b4d8414d4a98df1374dc=0D https://github.com/qemu/qemu/commit/7667cafd5a0d173d1853b4d8414d4a9= 8df1374dc=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Replace DisasContext.w with DisasContext.ol=0D =0D In preparation for RV128, consider more than just "w" for=0D operand size modification. This will be used for the "d"=0D insns from RV128 as well.=0D =0D Rename oper_len to get_olen to better match get_xlen.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-10-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 80347ae9f26dfafbd358d7d8d9ad175a2a624365=0D https://github.com/qemu/qemu/commit/80347ae9f26dfafbd358d7d8d9ad175= a2a624365=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_arith_per_ol for RVM=0D =0D The multiply high-part instructions require a separate=0D implementation for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-11-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 673be37163cb44d2e1699503ccd065e9d13d4db7=0D https://github.com/qemu/qemu/commit/673be37163cb44d2e1699503ccd065e= 9d13d4db7=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D =0D Log Message:=0D -----------=0D target/riscv: Adjust trans_rev8_32 for riscv64=0D =0D When target_long is 64-bit, we still want a 32-bit bswap for rev8.=0D Since this opcode is specific to RV32, we need not conditionalize.=0D =0D Acked-by: Alistair Francis =0D Reviewed-by: LIU Zhiwei =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-12-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: fdab665f6e9d0919bbbab88b16ae2c4be1bf61c6=0D https://github.com/qemu/qemu/commit/fdab665f6e9d0919bbbab88b16ae2c4= be1bf61c6=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_unary_per_ol for RVB=0D =0D The count zeros instructions require a separate implementation=0D for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-13-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: a0245d91dd1ca33ecde8c430ac6986dbd90a84db=0D https://github.com/qemu/qemu/commit/a0245d91dd1ca33ecde8c430ac6986d= bd90a84db=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use gen_shift*_per_ol for RVB, RVI=0D =0D Most shift instructions require a separate implementation=0D for RV32 when TARGET_LONG_BITS =3D=3D 64.=0D =0D Reviewed-by: LIU Zhiwei =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-14-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 665b90d8a4aa7d90bbeee9ff279e37edcd573635=0D https://github.com/qemu/qemu/commit/665b90d8a4aa7d90bbeee9ff279e37e= dcd573635=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Use riscv_csrrw_debug for cpu_dump=0D =0D Use the official debug read interface to the csrs,=0D rather than referencing the env slots directly.=0D Put the list of csrs to dump into a table.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-15-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b550f89457ef5022231f8255ae1a6ba496c492b1=0D https://github.com/qemu/qemu/commit/b550f89457ef5022231f8255ae1a6ba= 496c492b1=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Compute mstatus.sd on demand=0D =0D The position of this read-only field is dependent on the current xlen.=0D= Rather than having to compute that difference in many places, compute=0D it only on read.=0D =0D Reviewed-by: Alistair Francis =0D Signed-off-by: Richard Henderson =0D Message-id: 20211020031709.359469-16-richard.henderson@linaro.org=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: ef6310064820183cce7c5969cae293e680c57679=0D https://github.com/qemu/qemu/commit/ef6310064820183cce7c5969cae293e= 680c57679=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D M include/hw/riscv/opentitan.h=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Update to the latest build=0D =0D Update the OpenTitan machine model to match the latest OpenTitan FPGA=0D design.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 434e7e0217d73c20f60bd52437d0a0ba8a3c6247=0D https://github.com/qemu/qemu/commit/434e7e0217d73c20f60bd52437d0a0b= a8a3c6247=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D R hw/intc/ibex_plic.c=0D M hw/intc/meson.build=0D =0D Log Message:=0D -----------=0D hw/intc: Remove the Ibex PLIC=0D =0D The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and=0D instead use the SiFive PLIC.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d8c6590f183cd93956b7a458d212778a143b89c8=0D https://github.com/qemu/qemu/commit/d8c6590f183cd93956b7a458d212778= a143b89c8=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Move the properties=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d680ff664e1c7e097922f62fef824027b8fb711a=0D https://github.com/qemu/qemu/commit/d680ff664e1c7e097922f62fef82402= 7b8fb711a=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Cleanup the realize function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: 8d3dae162e61e6c71bbd3d9878cd1768ae9dd989=0D https://github.com/qemu/qemu/commit/8d3dae162e61e6c71bbd3d9878cd176= 8ae9dd989=0D Author: Alistair Francis =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sifive_plic.c=0D =0D Log Message:=0D -----------=0D hw/intc: sifive_plic: Cleanup the irq_request function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alist= air.francis@wdc.com=0D =0D =0D Commit: d4c624f482778cfe91938996a588df2df0e70f20=0D https://github.com/qemu/qemu/commit/d4c624f482778cfe91938996a588df2= df0e70f20=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/microchip_pfsoc.c=0D =0D Log Message:=0D -----------=0D hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::defa= ult_ram_id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 91b1fbdc0cca11ac23ddc61ee3ea0e9706b645cf=0D https://github.com/qemu/qemu/commit/91b1fbdc0cca11ac23ddc61ee3ea0e9= 706b645cf=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ra= m_id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D While at it add check for user supplied RAM size and error out if it=0D mismatches board expected value.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 56917307f4780535d319dedc8973361a5da76f7b=0D https://github.com/qemu/qemu/commit/56917307f4780535d319dedc8973361= a5da76f7b=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/shakti_c.c=0D =0D Log Message:=0D -----------=0D hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: e2b3ef75445fc2342b00680dad7af3618dc69deb=0D https://github.com/qemu/qemu/commit/e2b3ef75445fc2342b00680dad7af36= 18dc69deb=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_e.c=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D While at it add check for user supplied RAM size and error out if it=0D mismatches board expected value.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Igor Mammedov =0D Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: c188a9c4f78e21f7f979ab7ef19c5bf21e9dcf08=0D https://github.com/qemu/qemu/commit/c188a9c4f78e21f7f979ab7ef19c5bf= 21e9dcf08=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_u.c=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram= _id=0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 11ec06f9eaedc801ded34c79861367b76ab2b731=0D https://github.com/qemu/qemu/commit/11ec06f9eaedc801ded34c79861367b= 76ab2b731=0D Author: Bin Meng =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/spike.c=0D =0D Log Message:=0D -----------=0D hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id= =0D =0D Using memory_region_init_ram(), which can't possibly handle vhost-user,=0D= and can't work as expected with '-numa node,memdev' options.=0D =0D Use MachineState::ram instead of manually initializing RAM memory=0D region, as well as by providing MachineClass::default_ram_id to=0D opt in to memdev scheme.=0D =0D Signed-off-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Igor Mammedov =0D Reviewed-by: Alistair Francis =0D Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 660efed8b37aedec9b5fcc555da1f88f7d12c98a=0D https://github.com/qemu/qemu/commit/660efed8b37aedec9b5fcc555da1f88= f7d12c98a=0D Author: Richard Henderson =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D R hw/intc/ibex_plic.c=0D M hw/intc/meson.build=0D M hw/intc/sifive_plic.c=0D M hw/riscv/boot.c=0D M hw/riscv/microchip_pfsoc.c=0D M hw/riscv/opentitan.c=0D M hw/riscv/shakti_c.c=0D M hw/riscv/sifive_e.c=0D M hw/riscv/sifive_u.c=0D M hw/riscv/spike.c=0D M hw/riscv/virt.c=0D M include/hw/riscv/opentitan.h=0D M linux-user/elfload.c=0D M linux-user/riscv/cpu_loop.c=0D M semihosting/arm-compat-semi.c=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/gdbstub.c=0D M target/riscv/insn_trans/trans_rvb.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/insn_trans/trans_rvm.c.inc=0D M target/riscv/insn_trans/trans_rvv.c.inc=0D M target/riscv/machine.c=0D M target/riscv/monitor.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211022-2' into staging=0D =0D Fourth RISC-V PR for QEMU 6.2=0D =0D - Vector extension bug fixes=0D - Bit manipulation extension bug fix=0D - Support vhost-user and numa mem options on all boards=0D - Rationalise XLEN and operand lengths=0D - Bump the OpenTitan FPGA support=0D - Remove the Ibex PLIC=0D - General code cleanup=0D =0D # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits)=0D= hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id= =0D hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram= _id=0D hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ra= m_id=0D hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::defa= ult_ram_id=0D hw/intc: sifive_plic: Cleanup the irq_request function=0D hw/intc: sifive_plic: Cleanup the realize function=0D hw/intc: sifive_plic: Move the properties=0D hw/intc: Remove the Ibex PLIC=0D hw/riscv: opentitan: Update to the latest build=0D target/riscv: Compute mstatus.sd on demand=0D target/riscv: Use riscv_csrrw_debug for cpu_dump=0D target/riscv: Use gen_shift*_per_ol for RVB, RVI=0D target/riscv: Use gen_unary_per_ol for RVB=0D target/riscv: Adjust trans_rev8_32 for riscv64=0D target/riscv: Use gen_arith_per_ol for RVM=0D target/riscv: Replace DisasContext.w with DisasContext.ol=0D target/riscv: Replace is_32bit with get_xl/get_xlen=0D target/riscv: Properly check SEW in amo_op=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/2c64ff92ecef...660efed8b37a= =0D From MAILER-DAEMON Sat Oct 23 17:31:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1meObn-0001Fa-A3 for mharc-qemu-commits@gnu.org; Sat, 23 Oct 2021 17:31:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1meObm-0001Dv-4D for qemu-commits@nongnu.org; Sat, 23 Oct 2021 17:31:18 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:37019 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1meObj-0003vR-0j for qemu-commits@nongnu.org; Sat, 23 Oct 2021 17:31:17 -0400 Received: from github.com (hubbernetes-node-0704254.ac4-iad.github.net [10.52.201.68]) by smtp.github.com (Postfix) with ESMTPA id 3DDB152009A for ; Sat, 23 Oct 2021 14:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635024674; bh=z2tNBxvfuTLXooxWR09tscMeZ+636yz8s9z27vD9IB8=; h=Date:From:To:Subject:From; b=hxRPvxXgJpahk8ICqw+qvOQTgYUs8g2x91KFAsUEz9sGi0+r0uKiKHOecUug08QJQ rEPyeuQeIMsOu8X0hlAOe6MdCx0dhw64VLOLRpiLPGUnY7wCPHLnRxgraA/5s64p0S Xmr4X7aY6ORV899XkWG6Y/ucjvMyBYNuZL0Z5SII= Date: Sat, 23 Oct 2021 14:31:14 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HEXHASH_WORD=1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 764ecf: po: update turkish translation X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Oct 2021 21:31:18 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 764ecf77d03bb5fd42fac3d1042148da9130c552=0D https://github.com/qemu/qemu/commit/764ecf77d03bb5fd42fac3d1042148d= a9130c552=0D Author: O=C4=9Fuz Ersen =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M po/tr.po=0D =0D Log Message:=0D -----------=0D po: update turkish translation=0D =0D Message-Id: =0D Signed-off-by: O=C4=9Fuz Ersen =0D Reviewed-by: Laurent Vivier =0D [lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/]=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: ed899ac77d5c8b83797a001d33a1e57390181574=0D https://github.com/qemu/qemu/commit/ed899ac77d5c8b83797a001d33a1e57= 390181574=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M disas/nios2.c=0D =0D Log Message:=0D -----------=0D disas/nios2: Fix style in print_insn_nios2()=0D =0D We are going to modify this function, fix its style first.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Reviewed-by: Thomas Huth =0D Message-Id: <20210807110939.95853-2-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: dcc99bd833840c6c4e909d391df17b71e47dea62=0D https://github.com/qemu/qemu/commit/dcc99bd833840c6c4e909d391df17b7= 1e47dea62=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M disas/nios2.c=0D M include/disas/dis-asm.h=0D M target/nios2/cpu.c=0D =0D Log Message:=0D -----------=0D disas/nios2: Simplify endianess conversion=0D =0D Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization")=0D the disassemble_info->bfd_endian enum is set for all targets in=0D target_disas(). We can directly call print_insn_nios2() and simplify.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Reviewed-by: Thomas Huth =0D Message-Id: <20210807110939.95853-3-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3bc1bb80423b789cabedde2813630dd5092cb24a=0D https://github.com/qemu/qemu/commit/3bc1bb80423b789cabedde2813630dd= 5092cb24a=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Add myself as reviewer of 'Machine core' API=0D =0D In order to help Eduardo and Marcel with the machine=0D core API, add myself as reviewer. That will also help=0D me to learn more about this subsystem :)=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed by: Marcel Apfelbaum =0D Message-Id: <20211007093108.323223-1-philmd@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f18d403f15b92ded56362703067eb67161cfe2a9=0D https://github.com/qemu/qemu/commit/f18d403f15b92ded56362703067eb67= 161cfe2a9=0D Author: Greg Kurz =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu/physmem.c: Fix typo in comment=0D =0D Fix the comment to match what the code is doing, as explained in=0D the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09=0D that introduced the change:=0D =0D Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization= =0D of vCPU and migration operations through calling run_on_cpu operation= .=0D However, in replay mode this synchronization is unneeded, because=0D I/O and vCPU threads are already synchronized.=0D This patch disables such synchronization for record/replay mode.=0D =0D Signed-off-by: Greg Kurz =0D Reviewed-by: David Hildenbrand =0D Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguett= e>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c4e4d0d92b37430b74be3e9dab6066d2f4b69a95=0D https://github.com/qemu/qemu/commit/c4e4d0d92b37430b74be3e9dab6066d= 2f4b69a95=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-efuse.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx eFuse QOM=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-2-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 512a63b2b00ee0e7bf99bda2d8e6ce807dfa32c2=0D https://github.com/qemu/qemu/commit/512a63b2b00ee0e7bf99bda2d8e6ce8= 07dfa32c2=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-versal-efuse-ctrl.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-3-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e3f368e0b280315d5dd3bc26fb00b56587551d87=0D https://github.com/qemu/qemu/commit/e3f368e0b280315d5dd3bc26fb00b56= 587551d87=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-zynqmp-efuse.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-4-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 1c3515ad59878ad249a61a4a952f1820a12afb83=0D https://github.com/qemu/qemu/commit/1c3515ad59878ad249a61a4a952f182= 0a12afb83=0D Author: Greg Kurz =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M README.rst=0D =0D Log Message:=0D -----------=0D README: Fix some documentation URLs=0D =0D All of these pages live in the wiki, not in the main web site.=0D =0D Signed-off-by: Greg Kurz =0D Reviewed-by: Laurent Vivier =0D Tested-by: Laurent Vivier =0D Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguett= e>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f98d372aeff5109d2b5a3b858a51347e0ccd36b1=0D https://github.com/qemu/qemu/commit/f98d372aeff5109d2b5a3b858a51347= e0ccd36b1=0D Author: Laurent Vivier =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M scripts/analyze-migration.py=0D =0D Log Message:=0D -----------=0D analyze-migration.py: fix a long standing typo=0D =0D The parameters of '-d' can be either 'state' or 'desc', not 'dump'=0D as it is reported in the error message.=0D =0D Fixes: b17425701d66 ("Add migration stream analyzation script")=0D Signed-off-by: Laurent Vivier =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015131645.501281-2-lvivier@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa=0D https://github.com/qemu/qemu/commit/2c92be50bcfa8b7529a39fc99078ef1= 4dcfc71aa=0D Author: Laurent Vivier =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M scripts/analyze-migration.py=0D =0D Log Message:=0D -----------=0D analyze-migration.py: fix extract contents ('-x') errors=0D =0D When we try to use 'analyze-migration.py -x' with python3,=0D we have the following errors:=0D =0D Traceback (most recent call last):=0D File "scripts/analyze-migration.py", line 593, in =0D f.write(jsonenc.encode(dump.vmsd_desc))=0D TypeError: a bytes-like object is required, not 'str'=0D =0D Traceback (most recent call last):=0D File "scripts/analyze-migration.py", line 601, in =0D f.write(jsonenc.encode(dict))=0D TypeError: a bytes-like object is required, not 'str'=0D =0D This happens because the file 'f' is open in binary mode while=0D jsonenc.encode() returns a string.=0D =0D The results are human-readable files, 'desc.json' and 'state.json',=0D so there is no reason to use the binary mode.=0D =0D Signed-off-by: Laurent Vivier =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015131645.501281-3-lvivier@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c5b2f559814104f4145f8bc310f4d33c7ead8f49=0D https://github.com/qemu/qemu/commit/c5b2f559814104f4145f8bc310f4d33= c7ead8f49=0D Author: Richard Henderson =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M README.rst=0D M disas/nios2.c=0D M hw/nvram/xlnx-efuse.c=0D M hw/nvram/xlnx-versal-efuse-ctrl.c=0D M hw/nvram/xlnx-zynqmp-efuse.c=0D M include/disas/dis-asm.h=0D M po/tr.po=0D M scripts/analyze-migration.py=0D M softmmu/physmem.c=0D M target/nios2/cpu.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.= 2-pull-request' into staging=0D =0D Trivial patches pull request 20211023=0D =0D # gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/trivial-branch-for-6.2-pull-request:=0D analyze-migration.py: fix extract contents ('-x') errors=0D analyze-migration.py: fix a long standing typo=0D README: Fix some documentation URLs=0D hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device=0D hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device=0D hw/nvram: Fix Memory Leak in Xilinx eFuse QOM=0D softmmu/physmem.c: Fix typo in comment=0D MAINTAINERS: Add myself as reviewer of 'Machine core' API=0D disas/nios2: Simplify endianess conversion=0D disas/nios2: Fix style in print_insn_nios2()=0D po: update turkish translation=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/660efed8b37a...c5b2f5598141= =0D From MAILER-DAEMON Sat Oct 23 19:22:17 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1meQLB-0005yV-OO for mharc-qemu-commits@gnu.org; Sat, 23 Oct 2021 19:22:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1meQL9-0005yH-QE for qemu-commits@nongnu.org; Sat, 23 Oct 2021 19:22:15 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:41089 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1meQL7-0003Ru-9h for qemu-commits@nongnu.org; Sat, 23 Oct 2021 19:22:15 -0400 Received: from github.com (hubbernetes-node-ec8a6e4.va3-iad.github.net [10.48.206.52]) by smtp.github.com (Postfix) with ESMTPA id 97514340038 for ; Sat, 23 Oct 2021 16:22:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635031332; bh=Cw8hiZMUIeC0G+yFaaV8wMt9AgOE96+cVuw/8pGVQZM=; h=Date:From:To:Subject:From; b=V274GUs+l/KsDsTPdJlO9S8hc777D6oK/6PLZ8O+apTUsQgIzsecVcSEwSI+nmXnO YsiiIYyTIlu2lzLG+aXYAREI/yuHVuEMggfwsl1FK+yvHBSB61MfD2w9OQqluLR7/r zVompzGVJnubc7OYcqlJpVxas3m1NTqNcQ4c20OE= Date: Sat, 23 Oct 2021 16:22:12 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -60 X-Spam_score: -6.1 X-Spam_bar: ------ X-Spam_report: (-6.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HEXHASH_WORD=1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 764ecf: po: update turkish translation X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Oct 2021 23:22:16 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 764ecf77d03bb5fd42fac3d1042148da9130c552=0D https://github.com/qemu/qemu/commit/764ecf77d03bb5fd42fac3d1042148d= a9130c552=0D Author: O=C4=9Fuz Ersen =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M po/tr.po=0D =0D Log Message:=0D -----------=0D po: update turkish translation=0D =0D Message-Id: =0D Signed-off-by: O=C4=9Fuz Ersen =0D Reviewed-by: Laurent Vivier =0D [lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/]=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: ed899ac77d5c8b83797a001d33a1e57390181574=0D https://github.com/qemu/qemu/commit/ed899ac77d5c8b83797a001d33a1e57= 390181574=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M disas/nios2.c=0D =0D Log Message:=0D -----------=0D disas/nios2: Fix style in print_insn_nios2()=0D =0D We are going to modify this function, fix its style first.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Reviewed-by: Thomas Huth =0D Message-Id: <20210807110939.95853-2-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: dcc99bd833840c6c4e909d391df17b71e47dea62=0D https://github.com/qemu/qemu/commit/dcc99bd833840c6c4e909d391df17b7= 1e47dea62=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-22 (Fri, 22 Oct 2021)=0D =0D Changed paths:=0D M disas/nios2.c=0D M include/disas/dis-asm.h=0D M target/nios2/cpu.c=0D =0D Log Message:=0D -----------=0D disas/nios2: Simplify endianess conversion=0D =0D Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization")=0D the disassemble_info->bfd_endian enum is set for all targets in=0D target_disas(). We can directly call print_insn_nios2() and simplify.=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Laurent Vivier =0D Reviewed-by: Thomas Huth =0D Message-Id: <20210807110939.95853-3-f4bug@amsat.org>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 3bc1bb80423b789cabedde2813630dd5092cb24a=0D https://github.com/qemu/qemu/commit/3bc1bb80423b789cabedde2813630dd= 5092cb24a=0D Author: Philippe Mathieu-Daud=C3=A9 =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D =0D Log Message:=0D -----------=0D MAINTAINERS: Add myself as reviewer of 'Machine core' API=0D =0D In order to help Eduardo and Marcel with the machine=0D core API, add myself as reviewer. That will also help=0D me to learn more about this subsystem :)=0D =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed by: Marcel Apfelbaum =0D Message-Id: <20211007093108.323223-1-philmd@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f18d403f15b92ded56362703067eb67161cfe2a9=0D https://github.com/qemu/qemu/commit/f18d403f15b92ded56362703067eb67= 161cfe2a9=0D Author: Greg Kurz =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu/physmem.c: Fix typo in comment=0D =0D Fix the comment to match what the code is doing, as explained in=0D the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09=0D that introduced the change:=0D =0D Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization= =0D of vCPU and migration operations through calling run_on_cpu operation= .=0D However, in replay mode this synchronization is unneeded, because=0D I/O and vCPU threads are already synchronized.=0D This patch disables such synchronization for record/replay mode.=0D =0D Signed-off-by: Greg Kurz =0D Reviewed-by: David Hildenbrand =0D Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguett= e>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c4e4d0d92b37430b74be3e9dab6066d2f4b69a95=0D https://github.com/qemu/qemu/commit/c4e4d0d92b37430b74be3e9dab6066d= 2f4b69a95=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-efuse.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx eFuse QOM=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-2-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 512a63b2b00ee0e7bf99bda2d8e6ce807dfa32c2=0D https://github.com/qemu/qemu/commit/512a63b2b00ee0e7bf99bda2d8e6ce8= 07dfa32c2=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-versal-efuse-ctrl.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-3-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: e3f368e0b280315d5dd3bc26fb00b56587551d87=0D https://github.com/qemu/qemu/commit/e3f368e0b280315d5dd3bc26fb00b56= 587551d87=0D Author: Tong Ho =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M hw/nvram/xlnx-zynqmp-efuse.c=0D =0D Log Message:=0D -----------=0D hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device=0D =0D Signed-off-by: Tong Ho =0D Reviewed-by: Edgar E. Iglesias =0D Reviewed-by: Francisco Iglesias =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015203532.2463705-4-tong.ho@xilinx.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 1c3515ad59878ad249a61a4a952f1820a12afb83=0D https://github.com/qemu/qemu/commit/1c3515ad59878ad249a61a4a952f182= 0a12afb83=0D Author: Greg Kurz =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M README.rst=0D =0D Log Message:=0D -----------=0D README: Fix some documentation URLs=0D =0D All of these pages live in the wiki, not in the main web site.=0D =0D Signed-off-by: Greg Kurz =0D Reviewed-by: Laurent Vivier =0D Tested-by: Laurent Vivier =0D Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguett= e>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: f98d372aeff5109d2b5a3b858a51347e0ccd36b1=0D https://github.com/qemu/qemu/commit/f98d372aeff5109d2b5a3b858a51347= e0ccd36b1=0D Author: Laurent Vivier =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M scripts/analyze-migration.py=0D =0D Log Message:=0D -----------=0D analyze-migration.py: fix a long standing typo=0D =0D The parameters of '-d' can be either 'state' or 'desc', not 'dump'=0D as it is reported in the error message.=0D =0D Fixes: b17425701d66 ("Add migration stream analyzation script")=0D Signed-off-by: Laurent Vivier =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015131645.501281-2-lvivier@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa=0D https://github.com/qemu/qemu/commit/2c92be50bcfa8b7529a39fc99078ef1= 4dcfc71aa=0D Author: Laurent Vivier =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M scripts/analyze-migration.py=0D =0D Log Message:=0D -----------=0D analyze-migration.py: fix extract contents ('-x') errors=0D =0D When we try to use 'analyze-migration.py -x' with python3,=0D we have the following errors:=0D =0D Traceback (most recent call last):=0D File "scripts/analyze-migration.py", line 593, in =0D f.write(jsonenc.encode(dump.vmsd_desc))=0D TypeError: a bytes-like object is required, not 'str'=0D =0D Traceback (most recent call last):=0D File "scripts/analyze-migration.py", line 601, in =0D f.write(jsonenc.encode(dict))=0D TypeError: a bytes-like object is required, not 'str'=0D =0D This happens because the file 'f' is open in binary mode while=0D jsonenc.encode() returns a string.=0D =0D The results are human-readable files, 'desc.json' and 'state.json',=0D so there is no reason to use the binary mode.=0D =0D Signed-off-by: Laurent Vivier =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211015131645.501281-3-lvivier@redhat.com>=0D Signed-off-by: Laurent Vivier =0D =0D =0D Commit: c5b2f559814104f4145f8bc310f4d33c7ead8f49=0D https://github.com/qemu/qemu/commit/c5b2f559814104f4145f8bc310f4d33= c7ead8f49=0D Author: Richard Henderson =0D Date: 2021-10-23 (Sat, 23 Oct 2021)=0D =0D Changed paths:=0D M MAINTAINERS=0D M README.rst=0D M disas/nios2.c=0D M hw/nvram/xlnx-efuse.c=0D M hw/nvram/xlnx-versal-efuse-ctrl.c=0D M hw/nvram/xlnx-zynqmp-efuse.c=0D M include/disas/dis-asm.h=0D M po/tr.po=0D M scripts/analyze-migration.py=0D M softmmu/physmem.c=0D M target/nios2/cpu.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.= 2-pull-request' into staging=0D =0D Trivial patches pull request 20211023=0D =0D # gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT=0D # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FB= E3C=0D # gpg: issuer "laurent@vivier.eu"=0D # gpg: Good signature from "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier " [full]=0D= # gpg: aka "Laurent Vivier (Red Hat) = " [full]=0D =0D * remotes/vivier/tags/trivial-branch-for-6.2-pull-request:=0D analyze-migration.py: fix extract contents ('-x') errors=0D analyze-migration.py: fix a long standing typo=0D README: Fix some documentation URLs=0D hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device=0D hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device=0D hw/nvram: Fix Memory Leak in Xilinx eFuse QOM=0D softmmu/physmem.c: Fix typo in comment=0D MAINTAINERS: Add myself as reviewer of 'Machine core' API=0D disas/nios2: Simplify endianess conversion=0D disas/nios2: Fix style in print_insn_nios2()=0D po: update turkish translation=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/660efed8b37a...c5b2f5598141= =0D From MAILER-DAEMON Tue Oct 26 10:39:58 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfNcL-0007xm-W8 for mharc-qemu-commits@gnu.org; Tue, 26 Oct 2021 10:39:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfNcK-0007th-AC for qemu-commits@nongnu.org; Tue, 26 Oct 2021 10:39:56 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:46001 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfNcH-0005YF-Cr for qemu-commits@nongnu.org; Tue, 26 Oct 2021 10:39:55 -0400 Received: from github.com (hubbernetes-node-8a062b2.va3-iad.github.net [10.48.124.82]) by smtp.github.com (Postfix) with ESMTPA id AC20A5C05C1 for ; Tue, 26 Oct 2021 07:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635259192; bh=aPRpA16+00PSp9/tuxjaeDYr9laj+nZISOKMvJsNDi0=; h=Date:From:To:Subject:From; b=Z0oY7lDmYATd05XI4Oz2UndU23/dHa7AiXaC6ACFxmsoK4xvXatos4jxHXPFHWHYE plQbYAik4H8b0+NJz0IlS/Wv65HmfswJKH5z77VhmyWoKo5ei8AsDb0QON7A9v3pDl UBEy0AoRvZ+N30vknjJA64IZbNyW1j80MyOeIAkU= Date: Tue, 26 Oct 2021 07:39:52 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 5afc8d: virtiofsd: xattr mapping add a new type "unsupported" X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Oct 2021 14:39:56 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 5afc8df46cdf1a10fc44d43208cf449357009d2a https://github.com/qemu/qemu/commit/5afc8df46cdf1a10fc44d43208cf449357009d2a Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M docs/tools/virtiofsd.rst M tools/virtiofsd/passthrough_ll.c Log Message: ----------- virtiofsd: xattr mapping add a new type "unsupported" Right now for xattr remapping, we support types of "prefix", "ok" or "bad". Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For getxattr, mapping code returns -EPERM but getxattr code converts it to -ENODATA. I need a new semantics where if an xattr is unsupported, then getxattr()/setxattr() return -ENOTSUP and listxattr() should hide the xattr. This is needed to simulate that security.selinux is not supported by virtiofs filesystem and in that case client falls back to some default label specified by policy. So add a new type "unsupported" which returns -ENOTSUP on getxattr() and setxattr() and hides xattrs in listxattr(). For example, one can use following mapping rule to not support security.selinux xattr and allow others. "-o xattrmap=/unsupported/all/security.selinux/security.selinux//ok/all///" Suggested-by: "Dr. David Alan Gilbert" Signed-off-by: Vivek Goyal Message-Id: Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Dr. David Alan Gilbert Commit: a88abc6f841ea7f0a9c57d69ccf133e2c7d12348 https://github.com/qemu/qemu/commit/a88abc6f841ea7f0a9c57d69ccf133e2c7d12348 Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Remove unused virtio_fs_config definition "struct virtio_fs_config" definition seems to be unused in fuse_virtio.c. Remove it. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-4-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: c68276556a1e6e035f9a27d0dbb2f87b349f3aea https://github.com/qemu/qemu/commit/c68276556a1e6e035f9a27d0dbb2f87b349f3aea Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Add a helper to send element on virtqueue We have open coded logic to take locks and push element on virtqueue at three places. Add a helper and use it everywhere. Code is easier to read and less number of lines of code. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-5-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: 50cf6d6cb7b6b0e43f626da2a65d7277add21bd9 https://github.com/qemu/qemu/commit/50cf6d6cb7b6b0e43f626da2a65d7277add21bd9 Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Add a helper to stop all queues Use a helper to stop all the queues. Later in the patch series I am planning to use this helper at one more place later in the patch series. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-6-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: 555a76e5e5dc2cd3c84c5e1bc060be17d5b32584 https://github.com/qemu/qemu/commit/555a76e5e5dc2cd3c84c5e1bc060be17d5b32584 Author: Dr. David Alan Gilbert Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Error on bad socket group name Make the '--socket-group=' option fail if the group name is unknown: ./tools/virtiofsd/virtiofsd .... --socket-group=zaphod vhost socket: unable to find group 'zaphod' Reported-by: Xiaoling Gao Signed-off-by: Dr. David Alan Gilbert Message-Id: <20211014122554.34599-1-dgilbert@redhat.com> Reviewed-by: Vivek Goyal Signed-off-by: Dr. David Alan Gilbert Commit: 931ce30859176f0f7daac6bac255dae5eb21284e https://github.com/qemu/qemu/commit/931ce30859176f0f7daac6bac255dae5eb21284e Author: Richard Henderson Date: 2021-10-26 (Tue, 26 Oct 2021) Changed paths: M docs/tools/virtiofsd.rst M tools/virtiofsd/fuse_virtio.c M tools/virtiofsd/passthrough_ll.c Log Message: ----------- Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging Virtiofsd pull 2021-10-26 New 'unsupported' feature for xattr mapping Good for hiding selinux Plus some tidy ups and error handling. Signed-off-by: Dr. David Alan Gilbert # gpg: Signature made Tue 26 Oct 2021 03:28:44 AM PDT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) " [full] * remotes/dagrh/tags/pull-virtiofs-20211026: virtiofsd: Error on bad socket group name virtiofsd: Add a helper to stop all queues virtiofsd: Add a helper to send element on virtqueue virtiofsd: Remove unused virtio_fs_config definition virtiofsd: xattr mapping add a new type "unsupported" Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/c5b2f5598141...931ce3085917 From MAILER-DAEMON Tue Oct 26 13:12:09 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfPzc-0004vT-KA for mharc-qemu-commits@gnu.org; Tue, 26 Oct 2021 13:12:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfPzb-0004t6-6D for qemu-commits@nongnu.org; Tue, 26 Oct 2021 13:12:07 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:34151 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfPzY-0001zZ-05 for qemu-commits@nongnu.org; Tue, 26 Oct 2021 13:12:06 -0400 Received: from github.com (hubbernetes-node-d6ff2fa.va3-iad.github.net [10.48.124.46]) by smtp.github.com (Postfix) with ESMTPA id 37CB35C0CC2 for ; Tue, 26 Oct 2021 10:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635268323; bh=IsSvjv78Lew12fzuY6Wn8VTAbOfgMhMAml7MfaBDicQ=; h=Date:From:To:Subject:From; b=Nbsat6UnWWSwzz+OaYYe8B9sj+BYg78qLPXz6Q/u0UE2LNNzUrV2jdY/mnB5bPDWv HeV3BOjOdo604pFNIfOkyWiJu2jjt0AYpH/32YlZgwkxjME5dHumvXLTxNCntaBK3M lc23/WWKx49jekhLe9LneJKiuDjrTSuw4NAK/tMQ= Date: Tue, 26 Oct 2021 10:12:03 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 5afc8d: virtiofsd: xattr mapping add a new type "unsupported" X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Oct 2021 17:12:07 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: 5afc8df46cdf1a10fc44d43208cf449357009d2a https://github.com/qemu/qemu/commit/5afc8df46cdf1a10fc44d43208cf449357009d2a Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M docs/tools/virtiofsd.rst M tools/virtiofsd/passthrough_ll.c Log Message: ----------- virtiofsd: xattr mapping add a new type "unsupported" Right now for xattr remapping, we support types of "prefix", "ok" or "bad". Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For getxattr, mapping code returns -EPERM but getxattr code converts it to -ENODATA. I need a new semantics where if an xattr is unsupported, then getxattr()/setxattr() return -ENOTSUP and listxattr() should hide the xattr. This is needed to simulate that security.selinux is not supported by virtiofs filesystem and in that case client falls back to some default label specified by policy. So add a new type "unsupported" which returns -ENOTSUP on getxattr() and setxattr() and hides xattrs in listxattr(). For example, one can use following mapping rule to not support security.selinux xattr and allow others. "-o xattrmap=/unsupported/all/security.selinux/security.selinux//ok/all///" Suggested-by: "Dr. David Alan Gilbert" Signed-off-by: Vivek Goyal Message-Id: Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Dr. David Alan Gilbert Commit: a88abc6f841ea7f0a9c57d69ccf133e2c7d12348 https://github.com/qemu/qemu/commit/a88abc6f841ea7f0a9c57d69ccf133e2c7d12348 Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Remove unused virtio_fs_config definition "struct virtio_fs_config" definition seems to be unused in fuse_virtio.c. Remove it. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-4-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: c68276556a1e6e035f9a27d0dbb2f87b349f3aea https://github.com/qemu/qemu/commit/c68276556a1e6e035f9a27d0dbb2f87b349f3aea Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Add a helper to send element on virtqueue We have open coded logic to take locks and push element on virtqueue at three places. Add a helper and use it everywhere. Code is easier to read and less number of lines of code. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-5-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: 50cf6d6cb7b6b0e43f626da2a65d7277add21bd9 https://github.com/qemu/qemu/commit/50cf6d6cb7b6b0e43f626da2a65d7277add21bd9 Author: Vivek Goyal Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Add a helper to stop all queues Use a helper to stop all the queues. Later in the patch series I am planning to use this helper at one more place later in the patch series. Signed-off-by: Vivek Goyal Message-Id: <20210930153037.1194279-6-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Dr. David Alan Gilbert Commit: 555a76e5e5dc2cd3c84c5e1bc060be17d5b32584 https://github.com/qemu/qemu/commit/555a76e5e5dc2cd3c84c5e1bc060be17d5b32584 Author: Dr. David Alan Gilbert Date: 2021-10-25 (Mon, 25 Oct 2021) Changed paths: M tools/virtiofsd/fuse_virtio.c Log Message: ----------- virtiofsd: Error on bad socket group name Make the '--socket-group=' option fail if the group name is unknown: ./tools/virtiofsd/virtiofsd .... --socket-group=zaphod vhost socket: unable to find group 'zaphod' Reported-by: Xiaoling Gao Signed-off-by: Dr. David Alan Gilbert Message-Id: <20211014122554.34599-1-dgilbert@redhat.com> Reviewed-by: Vivek Goyal Signed-off-by: Dr. David Alan Gilbert Commit: 931ce30859176f0f7daac6bac255dae5eb21284e https://github.com/qemu/qemu/commit/931ce30859176f0f7daac6bac255dae5eb21284e Author: Richard Henderson Date: 2021-10-26 (Tue, 26 Oct 2021) Changed paths: M docs/tools/virtiofsd.rst M tools/virtiofsd/fuse_virtio.c M tools/virtiofsd/passthrough_ll.c Log Message: ----------- Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging Virtiofsd pull 2021-10-26 New 'unsupported' feature for xattr mapping Good for hiding selinux Plus some tidy ups and error handling. Signed-off-by: Dr. David Alan Gilbert # gpg: Signature made Tue 26 Oct 2021 03:28:44 AM PDT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) " [full] * remotes/dagrh/tags/pull-virtiofs-20211026: virtiofsd: Error on bad socket group name virtiofsd: Add a helper to stop all queues virtiofsd: Add a helper to send element on virtqueue virtiofsd: Remove unused virtio_fs_config definition virtiofsd: xattr mapping add a new type "unsupported" Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/c5b2f5598141...931ce3085917 From MAILER-DAEMON Wed Oct 27 10:58:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfkNw-00049j-1J for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 10:58:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfkNq-00045d-Pw for qemu-commits@nongnu.org; Wed, 27 Oct 2021 10:58:31 -0400 Received: from out-27.smtp.github.com ([192.30.252.210]:52093) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfkNn-0005FJ-Da for qemu-commits@nongnu.org; Wed, 27 Oct 2021 10:58:30 -0400 Received: from github.com (hubbernetes-node-69b5331.ash1-iad.github.net [10.56.113.46]) by smtp.github.com (Postfix) with ESMTPA id 98A5A901A73 for ; Wed, 27 Oct 2021 07:58:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635346706; bh=hvsb7OY3HL9DAxKjq69lYCp/QeznkjbnyHVbNbThyfA=; h=Date:From:To:Subject:From; b=FXx+oLIp7bgihoD9JsG8v7DpRd6XyYjYjhtq00dqb3nwRvI4vhELM2Gu0Bh2htEpd DcYB4mSPgIkhgLkSS4dPA1wDMwYijnXGQ2opBZMdKvOHrhZlTOQCD+EALDKI2ihDfd jGngd9X3kOwvHcQpO0Z5AFn1bodQDzrMpVfMluI4= Date: Wed, 27 Oct 2021 07:58:26 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.210; envelope-from=noreply@github.com; helo=out-27.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 669ced: 9pfs: fix wrong I/O block size in Rgetattr X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Oct 2021 14:58:32 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 669ced09b3b6070d478acce51810591b78ab0ccd=0D https://github.com/qemu/qemu/commit/669ced09b3b6070d478acce51810591= b78ab0ccd=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D When client sent a 9p Tgetattr request then the wrong I/O block=0D size value was returned by 9p server; instead of host file=0D system's I/O block size it should rather return an I/O block=0D size according to 9p session's 'msize' value, because the value=0D returned to client should be an "optimum" block size for I/O=0D (i.e. to maximize performance), it should not reflect the actual=0D physical block size of the underlying storage media.=0D =0D The I/O block size of a host filesystem is typically 4k, so the=0D value returned was far too low for good 9p I/O performance.=0D =0D This patch adds stat_to_iounit() with a similar approach as the=0D existing get_iounit() function.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: =0D =0D =0D Commit: b565bccb00afe8b73d529bbc3a38682996dac5c7=0D https://github.com/qemu/qemu/commit/b565bccb00afe8b73d529bbc3a38682= 996dac5c7=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: deduplicate iounit code=0D =0D Remove redundant code that translates host fileystem's block=0D size into 9p client (guest side) block size.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: <129bb71d5119e61d335f1e3107e472e4beea223a.1632758315.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 04a7f9e55e0930b87805f7c97851eea4610e78fc=0D https://github.com/qemu/qemu/commit/04a7f9e55e0930b87805f7c97851eea= 4610e78fc=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: simplify blksize_to_iounit()=0D =0D Use QEMU_ALIGN_DOWN() macro to reduce code and to make it=0D more human readable.=0D =0D Suggested-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D =0D =0D Commit: 30e702abf6fa8a7f1e6ad11a75d6f3ab6fcb2155=0D https://github.com/qemu/qemu/commit/30e702abf6fa8a7f1e6ad11a75d6f3a= b6fcb2155=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D A fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D 9pfs: introduce P9Array=0D =0D Implements deep auto free of arrays while retaining common C-style=0D squared bracket access. Main purpose of this API is to get rid of=0D error prone individual array deallocation pathes in user code, i.e.=0D turning something like this:=0D =0D void doSomething(size_t n) {=0D Foo *foos =3D malloc(n * sizeof(Foo));=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D goto out;=0D }=0D }=0D out:=0D if (...) {=0D for (...) {=0D /* deep deallocation */=0D free(foos[i].s);=0D }=0D /* array deallocation */=0D free(foos);=0D }=0D }=0D =0D into something more simple and safer like:=0D =0D void doSomething(size_t n) {=0D P9ARRAY_REF(Foo) foos =3D NULL;=0D P9ARRAY_NEW(Foo, foos, n);=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D return; /* array auto freed here */=0D }=0D }=0D /* array auto freed here */=0D }=0D =0D Unlike GArray, P9Array does not require special macros, function=0D calls or struct member dereferencing to access the individual array=0D elements:=0D =0D C-array =3D P9Array: vs. GArray:=0D =0D for (...) { | for (...) {=0D ... =3D arr[i].m; | ... =3D g_array_index(arr, Foo, i).m;=0D= arr[i].m =3D ... ; | g_array_index(arr, Foo, i).m =3D ... ;=0D= } | }=0D =0D So existing C-style array code can be retained with only very little=0D changes; basically limited to replacing array allocation call and of=0D course removing individual array deallocation pathes.=0D =0D In this initial version P9Array only supports the concept of unique=0D pointers, i.e. it does not support reference counting. The array (and=0D all dynamically allocated memory of individual array elements) is auto=0D= freed once execution leaves the scope of the reference variable (unique=0D= pointer) associated with the array.=0D =0D Internally a flex array struct is used in combination with macros=0D spanned over a continuous memory space for both the array's meta data=0D (private) and the actual C-array user data (public):=0D =0D struct P9Array##scalar_type {=0D size_t len; /* private, hidden from user code */=0D scalar_type first[]; /* public, directly exposed to user code */=0D= };=0D =0D Which has the advantage that the compiler automatically takes care=0D about correct padding, alignment and overall size for all scalar data=0D types on all systems and that the user space exposed pointer can=0D directly be translated back and forth between user space C-array=0D pointer and internal P9Array struct whenever needed, in a type-safe=0D manner.=0D =0D This header file is released under MIT license, to allow this file=0D being used in other C-projects as well. The common QEMU license=0D GPL2+ might have construed a conflict for other projects.=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: c0451f0bc4210d262268ff51c053a9277f20f862=0D https://github.com/qemu/qemu/commit/c0451f0bc4210d262268ff51c053a92= 77f20f862=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D =0D Make sure at compile time that the scalar type of the array=0D requested to be created via P9ARRAY_NEW() matches the scalar=0D type of the passed auto reference variable (unique pointer).=0D =0D Suggested-by: Richard Henderson =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: 42bdeb04b6a4bf3e54f4d7f87193803268ba8255=0D https://github.com/qemu/qemu/commit/42bdeb04b6a4bf3e54f4d7f87193803= 268ba8255=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsString usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: cc82fde9c7b4b598907914896ee6942fa866258c=0D https://github.com/qemu/qemu/commit/cc82fde9c7b4b598907914896ee6942= fa866258c=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/file-op-9p.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsPath usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <79a0ddf8375f6c95f0565ef155a1bf1e9387664f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 7e985780aaab93d2c5be9b62d8d386568dfb071e=0D https://github.com/qemu/qemu/commit/7e985780aaab93d2c5be9b62d8d3865= 68dfb071e=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: use P9Array in v9fs_walk()=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <90c65d1c1ca11c1b434bb981b1fc7966f7711c8f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 66b095c4fe18b50f73ceef40721d149d4d0cd307=0D https://github.com/qemu/qemu/commit/66b095c4fe18b50f73ceef40721d149= d4d0cd307=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D M fsdev/file-op-9p.h=0D A fsdev/p9array.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-2021102= 7' into staging=0D =0D 9pfs: performance fix and cleanup=0D =0D * First patch fixes suboptimal I/O performance on guest due to previously= =0D incorrect block size being transmitted to 9p client.=0D =0D * Subsequent patches are cleanup ones intended to reduce code complexity.= =0D =0D # gpg: Signature made Wed 27 Oct 2021 06:18:18 AM PDT=0D # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47= 395=0D # gpg: issuer "qemu_oss@crudebyte.com"=0D # gpg: Good signature from "Christian Schoenebeck " [unknown]=0D # gpg: WARNING: This key is not certified with a trusted signature!=0D # gpg: There is no indication that the signature belongs to the = owner.=0D # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 = D5F4=0D # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 = 7395=0D =0D * remotes/cschoenebeck/tags/pull-9p-20211027:=0D 9pfs: use P9Array in v9fs_walk()=0D 9pfs: make V9fsPath usable via P9Array API=0D 9pfs: make V9fsString usable via P9Array API=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D 9pfs: introduce P9Array=0D 9pfs: simplify blksize_to_iounit()=0D 9pfs: deduplicate iounit code=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/931ce3085917...66b095c4fe18= =0D From MAILER-DAEMON Wed Oct 27 12:43:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfm1h-00029P-KO for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 12:43:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfm1g-00022Q-9x for qemu-commits@nongnu.org; Wed, 27 Oct 2021 12:43:44 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:36961 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfm1d-0005YY-9Q for qemu-commits@nongnu.org; Wed, 27 Oct 2021 12:43:43 -0400 Received: from github.com (hubbernetes-node-79a227a.va3-iad.github.net [10.48.200.73]) by smtp.github.com (Postfix) with ESMTPA id A939234038C for ; Wed, 27 Oct 2021 09:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635353020; bh=NFrD3XHmI/4PO1JN9UhSIB5z98ZhGolahquT3UPimK8=; h=Date:From:To:Subject:From; b=1pO4eFdYuac5e+FljLr+G2pIq4K3KOpkxUrZz/0G+nstrPVbbTBv9i4YDKAs+rZim lQEgXAMZa0WZK8EFNNFfndO7WjSQ50JikpjNYONt3JIv82+2mkUo6EWDBfs0b/vKdK U/c+JT3/omnIzJQ8yihUzYFYgqJkwXlXpRyhy5oI= Date: Wed, 27 Oct 2021 09:43:40 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ea2933: qapi: Improve input_type_enum()'s error message X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Oct 2021 16:43:44 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: ea29331ba6c0e622e63424cc8495177ed7655a77=0D https://github.com/qemu/qemu/commit/ea29331ba6c0e622e63424cc8495177= ed7655a77=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M qapi/qapi-visit-core.c=0D M tests/qemu-iotests/049.out=0D M tests/qemu-iotests/206.out=0D M tests/qemu-iotests/237.out=0D M tests/qemu-iotests/245=0D M tests/qemu-iotests/287=0D M tests/qemu-iotests/308=0D M tests/unit/check-qom-proplist.c=0D =0D Log Message:=0D -----------=0D qapi: Improve input_type_enum()'s error message=0D =0D The error message claims the parameter is invalid:=0D =0D $ qemu-system-x86_64 -object qom-type=3Dnonexistent=0D qemu-system-x86_64: -object qom-type=3Dnonexistent: Invalid parameter= 'nonexistent'=0D =0D What's wrong is actually the *value* 'nonexistent'. Improve the=0D message to=0D =0D qemu-system-x86_64: -object qom-type=3Dnonexistent: Parameter 'qom-ty= pe' does not accept value 'nonexistent'=0D =0D Fixes: https://gitlab.com/qemu-project/qemu/-/issues/608=0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211020180231.434071-1-armbru@redhat.com>=0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 75ecee7262548d21a9e20c12f0b3b12f8a51d5c6=0D https://github.com/qemu/qemu/commit/75ecee7262548d21a9e20c12f0b3b12= f8a51d5c6=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/qapi-code-gen.rst=0D M qapi/introspect.json=0D M scripts/qapi/introspect.py=0D =0D Log Message:=0D -----------=0D qapi: Enable enum member introspection to show more than name=0D =0D The next commit will add feature flags to enum members. There's a=0D problem, though: query-qmp-schema shows an enum type's members as an=0D array of member names (SchemaInfoEnum member @values). If it showed=0D an array of objects with a name member, we could simply add more=0D members to these objects. Since it's just strings, we can't.=0D =0D I can see three ways to correct this design mistake:=0D =0D 1. Do it the way we should have done it, plus compatibility goo.=0D =0D We want a ['SchemaInfoEnumMember'] member in SchemaInfoEnum. Since=0D= changing @values would be a compatibility break, add a new member=0D @members instead.=0D =0D @values is now redundant. In my testing, output of=0D qemu-system-x86_64's query-qmp-schema grows by 11% (18.5KiB).=0D =0D We can deprecate @values now and drop it later. This will break=0D outmoded clients. Well-behaved clients such as libvirt are=0D expected to break cleanly.=0D =0D 2. Like 1, but omit "boring" elements of @member, and empty @member.=0D =0D @values does not become redundant. @members augments it. Somewhat=0D= cumbersome, but output of query-qmp-schema grows only as we make=0D enum members non-boring.=0D =0D There is nothing to deprecate here.=0D =0D 3. Versioned query-qmp-schema.=0D =0D query-qmp-schema provides either @values or @members. The QMP=0D client can select which version it wants. There is no redundant=0D output.=0D =0D We can deprecate old versions and eventually drop them. This will=0D break outmoded clients. Breaking cleanly is easier than for 1.=0D =0D While 1 and 2 operate within the common rules for compatible=0D evolution apply (section "Compatibility considerations" in=0D docs/devel/qapi-code-gen.rst), 3 bypasses them. Attractive when=0D operating within the rules is just too awkward. Not the case here.=0D= =0D This commit implements 1. Libvirt developers prefer it.=0D =0D Deprecate @values in favour of @members. Since query-qmp-schema=0D compatibility is pretty fundamental for management applications, an=0D extended grace period is advised.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Tested-by: Peter Krempa =0D Acked-by: Peter Krempa =0D Message-Id: <20211025042405.3762351-2-armbru@redhat.com>=0D Reviewed-by: John Snow =0D =0D =0D Commit: b6c18755e41f7b40aad4c2c8188fb1719535699d=0D https://github.com/qemu/qemu/commit/b6c18755e41f7b40aad4c2c8188fb17= 19535699d=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M qapi/compat.json=0D M qapi/introspect.json=0D M scripts/qapi/expr.py=0D M scripts/qapi/introspect.py=0D M scripts/qapi/schema.py=0D M tests/qapi-schema/doc-good.json=0D M tests/qapi-schema/doc-good.out=0D M tests/qapi-schema/doc-good.txt=0D M tests/qapi-schema/enum-dict-member-unknown.err=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D M tests/qapi-schema/test-qapi.py=0D =0D Log Message:=0D -----------=0D qapi: Add feature flags to enum members=0D =0D This is quite similar to commit 84ab008687 "qapi: Add feature flags to=0D= struct members", only for enums instead of structs.=0D =0D Special feature flag 'deprecated' is silently ignored there. This is=0D okay only because it will be implemented shortly.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Message-Id: <20211025042405.3762351-3-armbru@redhat.com>=0D Reviewed-by: John Snow =0D =0D =0D Commit: ed29bb28f8b0b17e965efcc2535fc32e101e3ceb=0D https://github.com/qemu/qemu/commit/ed29bb28f8b0b17e965efcc2535fc32= e101e3ceb=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qobject-input-visitor.h=0D M include/qapi/qobject-output-visitor.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D =0D Log Message:=0D -----------=0D qapi: Move compat policy from QObject to generic visitor=0D =0D The next commit needs to access compat policy from the generic visitor=0D= core. Move it there from qobject input and output visitor.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Message-Id: <20211025042405.3762351-4-armbru@redhat.com>=0D =0D =0D Commit: aa2370444b62f8f9a809c024d0c41cb40658a5c3=0D https://github.com/qemu/qemu/commit/aa2370444b62f8f9a809c024d0c41cb= 40658a5c3=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/compat.json=0D M qapi/qapi-visit-core.c=0D M scripts/qapi/types.py=0D =0D Log Message:=0D -----------=0D qapi: Implement deprecated-input=3D{reject,crash} for enum values=0D =0D This copies the code implementing the policy from qapi/qmp-dispatch.c=0D to qapi/qobject-input-visitor.c. Tolerable, but if we acquire more=0D copies, we should look into factoring them out.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Tested-by: Peter Krempa =0D Acked-by: Peter Krempa =0D Message-Id: <20211025042405.3762351-5-armbru@redhat.com>=0D =0D =0D Commit: 5c49c6c241e524b6ba7768de07cab6f2056feb90=0D https://github.com/qemu/qemu/commit/5c49c6c241e524b6ba7768de07cab6f= 2056feb90=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/qapi-code-gen.rst=0D M include/qapi/qobject-input-visitor.h=0D M include/qapi/qobject-output-visitor.h=0D M include/qapi/util.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/compat.json=0D M qapi/introspect.json=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M scripts/qapi/expr.py=0D M scripts/qapi/introspect.py=0D M scripts/qapi/schema.py=0D M scripts/qapi/types.py=0D M tests/qapi-schema/doc-good.json=0D M tests/qapi-schema/doc-good.out=0D M tests/qapi-schema/doc-good.txt=0D M tests/qapi-schema/enum-dict-member-unknown.err=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D M tests/qapi-schema/test-qapi.py=0D M tests/qemu-iotests/049.out=0D M tests/qemu-iotests/206.out=0D M tests/qemu-iotests/237.out=0D M tests/qemu-iotests/245=0D M tests/qemu-iotests/287=0D M tests/qemu-iotests/308=0D M tests/unit/check-qom-proplist.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-27'= into staging=0D =0D QAPI patches patches for 2021-10-27=0D =0D # gpg: Signature made Wed 27 Oct 2021 08:21:54 AM PDT=0D # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918= 653=0D # gpg: issuer "armbru@redhat.com"=0D # gpg: Good signature from "Markus Armbruster " [full]= =0D # gpg: aka "Markus Armbruster " [ful= l]=0D =0D * remotes/armbru/tags/pull-qapi-2021-10-27:=0D qapi: Implement deprecated-input=3D{reject,crash} for enum values=0D qapi: Move compat policy from QObject to generic visitor=0D qapi: Add feature flags to enum members=0D qapi: Enable enum member introspection to show more than name=0D qapi: Improve input_type_enum()'s error message=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/66b095c4fe18...5c49c6c241e5= =0D From MAILER-DAEMON Wed Oct 27 14:34:36 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfnkw-00077P-Dh for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 14:34:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfnkp-00074I-Mm for qemu-commits@nongnu.org; Wed, 27 Oct 2021 14:34:28 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:38683 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfnki-0007Ew-Ek for qemu-commits@nongnu.org; Wed, 27 Oct 2021 14:34:27 -0400 Received: from github.com (hubbernetes-node-7e7c924.ac4-iad.github.net [10.52.206.72]) by smtp.github.com (Postfix) with ESMTPA id 8BCEA560E32 for ; Wed, 27 Oct 2021 11:34:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635359659; bh=PkszAKVuuBNlfBjsNdk9edsrcjnNHCvnnB8DAKuWMgA=; h=Date:From:To:Subject:From; b=UTctKKof5uNdHJn2dA8cvh/AzlsTlm0FsEwwcoQmwbdWQTzAbbPzTLzPomVafOBAw AomkEHIYWv7HaRKELLkd5TSxMVpQYbsq+k9Qm1RxIr0xHz8mFIp/s0Hyb5nIpoY4Fs hIjvJAtqjVQxxUNND9eB9o0pmByuiBues24+iXUo= Date: Wed, 27 Oct 2021 11:34:19 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -66 X-Spam_score: -6.7 X-Spam_bar: ------ X-Spam_report: (-6.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] ea2933: qapi: Improve input_type_enum()'s error message X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Oct 2021 18:34:29 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: ea29331ba6c0e622e63424cc8495177ed7655a77=0D https://github.com/qemu/qemu/commit/ea29331ba6c0e622e63424cc8495177= ed7655a77=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M qapi/qapi-visit-core.c=0D M tests/qemu-iotests/049.out=0D M tests/qemu-iotests/206.out=0D M tests/qemu-iotests/237.out=0D M tests/qemu-iotests/245=0D M tests/qemu-iotests/287=0D M tests/qemu-iotests/308=0D M tests/unit/check-qom-proplist.c=0D =0D Log Message:=0D -----------=0D qapi: Improve input_type_enum()'s error message=0D =0D The error message claims the parameter is invalid:=0D =0D $ qemu-system-x86_64 -object qom-type=3Dnonexistent=0D qemu-system-x86_64: -object qom-type=3Dnonexistent: Invalid parameter= 'nonexistent'=0D =0D What's wrong is actually the *value* 'nonexistent'. Improve the=0D message to=0D =0D qemu-system-x86_64: -object qom-type=3Dnonexistent: Parameter 'qom-ty= pe' does not accept value 'nonexistent'=0D =0D Fixes: https://gitlab.com/qemu-project/qemu/-/issues/608=0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211020180231.434071-1-armbru@redhat.com>=0D Reviewed-by: Kevin Wolf =0D =0D =0D Commit: 75ecee7262548d21a9e20c12f0b3b12f8a51d5c6=0D https://github.com/qemu/qemu/commit/75ecee7262548d21a9e20c12f0b3b12= f8a51d5c6=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/qapi-code-gen.rst=0D M qapi/introspect.json=0D M scripts/qapi/introspect.py=0D =0D Log Message:=0D -----------=0D qapi: Enable enum member introspection to show more than name=0D =0D The next commit will add feature flags to enum members. There's a=0D problem, though: query-qmp-schema shows an enum type's members as an=0D array of member names (SchemaInfoEnum member @values). If it showed=0D an array of objects with a name member, we could simply add more=0D members to these objects. Since it's just strings, we can't.=0D =0D I can see three ways to correct this design mistake:=0D =0D 1. Do it the way we should have done it, plus compatibility goo.=0D =0D We want a ['SchemaInfoEnumMember'] member in SchemaInfoEnum. Since=0D= changing @values would be a compatibility break, add a new member=0D @members instead.=0D =0D @values is now redundant. In my testing, output of=0D qemu-system-x86_64's query-qmp-schema grows by 11% (18.5KiB).=0D =0D We can deprecate @values now and drop it later. This will break=0D outmoded clients. Well-behaved clients such as libvirt are=0D expected to break cleanly.=0D =0D 2. Like 1, but omit "boring" elements of @member, and empty @member.=0D =0D @values does not become redundant. @members augments it. Somewhat=0D= cumbersome, but output of query-qmp-schema grows only as we make=0D enum members non-boring.=0D =0D There is nothing to deprecate here.=0D =0D 3. Versioned query-qmp-schema.=0D =0D query-qmp-schema provides either @values or @members. The QMP=0D client can select which version it wants. There is no redundant=0D output.=0D =0D We can deprecate old versions and eventually drop them. This will=0D break outmoded clients. Breaking cleanly is easier than for 1.=0D =0D While 1 and 2 operate within the common rules for compatible=0D evolution apply (section "Compatibility considerations" in=0D docs/devel/qapi-code-gen.rst), 3 bypasses them. Attractive when=0D operating within the rules is just too awkward. Not the case here.=0D= =0D This commit implements 1. Libvirt developers prefer it.=0D =0D Deprecate @values in favour of @members. Since query-qmp-schema=0D compatibility is pretty fundamental for management applications, an=0D extended grace period is advised.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Tested-by: Peter Krempa =0D Acked-by: Peter Krempa =0D Message-Id: <20211025042405.3762351-2-armbru@redhat.com>=0D Reviewed-by: John Snow =0D =0D =0D Commit: b6c18755e41f7b40aad4c2c8188fb1719535699d=0D https://github.com/qemu/qemu/commit/b6c18755e41f7b40aad4c2c8188fb17= 19535699d=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M qapi/compat.json=0D M qapi/introspect.json=0D M scripts/qapi/expr.py=0D M scripts/qapi/introspect.py=0D M scripts/qapi/schema.py=0D M tests/qapi-schema/doc-good.json=0D M tests/qapi-schema/doc-good.out=0D M tests/qapi-schema/doc-good.txt=0D M tests/qapi-schema/enum-dict-member-unknown.err=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D M tests/qapi-schema/test-qapi.py=0D =0D Log Message:=0D -----------=0D qapi: Add feature flags to enum members=0D =0D This is quite similar to commit 84ab008687 "qapi: Add feature flags to=0D= struct members", only for enums instead of structs.=0D =0D Special feature flag 'deprecated' is silently ignored there. This is=0D okay only because it will be implemented shortly.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Message-Id: <20211025042405.3762351-3-armbru@redhat.com>=0D Reviewed-by: John Snow =0D =0D =0D Commit: ed29bb28f8b0b17e965efcc2535fc32e101e3ceb=0D https://github.com/qemu/qemu/commit/ed29bb28f8b0b17e965efcc2535fc32= e101e3ceb=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qobject-input-visitor.h=0D M include/qapi/qobject-output-visitor.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D =0D Log Message:=0D -----------=0D qapi: Move compat policy from QObject to generic visitor=0D =0D The next commit needs to access compat policy from the generic visitor=0D= core. Move it there from qobject input and output visitor.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Message-Id: <20211025042405.3762351-4-armbru@redhat.com>=0D =0D =0D Commit: aa2370444b62f8f9a809c024d0c41cb40658a5c3=0D https://github.com/qemu/qemu/commit/aa2370444b62f8f9a809c024d0c41cb= 40658a5c3=0D Author: Markus Armbruster =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/compat.json=0D M qapi/qapi-visit-core.c=0D M scripts/qapi/types.py=0D =0D Log Message:=0D -----------=0D qapi: Implement deprecated-input=3D{reject,crash} for enum values=0D =0D This copies the code implementing the policy from qapi/qmp-dispatch.c=0D to qapi/qobject-input-visitor.c. Tolerable, but if we acquire more=0D copies, we should look into factoring them out.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Eric Blake =0D Tested-by: Peter Krempa =0D Acked-by: Peter Krempa =0D Message-Id: <20211025042405.3762351-5-armbru@redhat.com>=0D =0D =0D Commit: 5c49c6c241e524b6ba7768de07cab6f2056feb90=0D https://github.com/qemu/qemu/commit/5c49c6c241e524b6ba7768de07cab6f= 2056feb90=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M docs/devel/qapi-code-gen.rst=0D M include/qapi/qobject-input-visitor.h=0D M include/qapi/qobject-output-visitor.h=0D M include/qapi/util.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/compat.json=0D M qapi/introspect.json=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M scripts/qapi/expr.py=0D M scripts/qapi/introspect.py=0D M scripts/qapi/schema.py=0D M scripts/qapi/types.py=0D M tests/qapi-schema/doc-good.json=0D M tests/qapi-schema/doc-good.out=0D M tests/qapi-schema/doc-good.txt=0D M tests/qapi-schema/enum-dict-member-unknown.err=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D M tests/qapi-schema/test-qapi.py=0D M tests/qemu-iotests/049.out=0D M tests/qemu-iotests/206.out=0D M tests/qemu-iotests/237.out=0D M tests/qemu-iotests/245=0D M tests/qemu-iotests/287=0D M tests/qemu-iotests/308=0D M tests/unit/check-qom-proplist.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-27'= into staging=0D =0D QAPI patches patches for 2021-10-27=0D =0D # gpg: Signature made Wed 27 Oct 2021 08:21:54 AM PDT=0D # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918= 653=0D # gpg: issuer "armbru@redhat.com"=0D # gpg: Good signature from "Markus Armbruster " [full]= =0D # gpg: aka "Markus Armbruster " [ful= l]=0D =0D * remotes/armbru/tags/pull-qapi-2021-10-27:=0D qapi: Implement deprecated-input=3D{reject,crash} for enum values=0D qapi: Move compat policy from QObject to generic visitor=0D qapi: Add feature flags to enum members=0D qapi: Enable enum member introspection to show more than name=0D qapi: Improve input_type_enum()'s error message=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/931ce3085917...5c49c6c241e5= =0D From MAILER-DAEMON Wed Oct 27 14:46:48 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfnwm-0005Do-68 for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 14:46:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfnwi-0005AI-EU for qemu-commits@nongnu.org; Wed, 27 Oct 2021 14:46:45 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:60489 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfnwg-0000pe-8S for qemu-commits@nongnu.org; Wed, 27 Oct 2021 14:46:44 -0400 Received: from github.com (hubbernetes-node-24be4a4.va3-iad.github.net [10.48.206.55]) by smtp.github.com (Postfix) with ESMTPA id A0F803403FF for ; Wed, 27 Oct 2021 11:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635360400; bh=kXI6NQK+XWQmXAsGtmiiknOnJ1PFek1KQJN+rhsxMs8=; h=Date:From:To:Subject:From; b=nfB6mGa2i1EM4ryKztKxLpc9Kuo6yWpZZ4u5yfsgAp9v/B3Bmy/R95W0R5aYuF7Vz g/+TN6JmDk4t/NDtzrQJpnMlR3NFO1xCAI3KhiiE6UbDyhtLd0Pr+8NX5l+WsCm591 lU2SVm+xu8m651KfUIKHnE1teybmRrAmhW7xu4Ic= Date: Wed, 27 Oct 2021 11:46:40 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 669ced: 9pfs: fix wrong I/O block size in Rgetattr X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Oct 2021 18:46:45 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 669ced09b3b6070d478acce51810591b78ab0ccd=0D https://github.com/qemu/qemu/commit/669ced09b3b6070d478acce51810591= b78ab0ccd=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D When client sent a 9p Tgetattr request then the wrong I/O block=0D size value was returned by 9p server; instead of host file=0D system's I/O block size it should rather return an I/O block=0D size according to 9p session's 'msize' value, because the value=0D returned to client should be an "optimum" block size for I/O=0D (i.e. to maximize performance), it should not reflect the actual=0D physical block size of the underlying storage media.=0D =0D The I/O block size of a host filesystem is typically 4k, so the=0D value returned was far too low for good 9p I/O performance.=0D =0D This patch adds stat_to_iounit() with a similar approach as the=0D existing get_iounit() function.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: =0D =0D =0D Commit: b565bccb00afe8b73d529bbc3a38682996dac5c7=0D https://github.com/qemu/qemu/commit/b565bccb00afe8b73d529bbc3a38682= 996dac5c7=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: deduplicate iounit code=0D =0D Remove redundant code that translates host fileystem's block=0D size into 9p client (guest side) block size.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: <129bb71d5119e61d335f1e3107e472e4beea223a.1632758315.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 04a7f9e55e0930b87805f7c97851eea4610e78fc=0D https://github.com/qemu/qemu/commit/04a7f9e55e0930b87805f7c97851eea= 4610e78fc=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: simplify blksize_to_iounit()=0D =0D Use QEMU_ALIGN_DOWN() macro to reduce code and to make it=0D more human readable.=0D =0D Suggested-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D =0D =0D Commit: 30e702abf6fa8a7f1e6ad11a75d6f3ab6fcb2155=0D https://github.com/qemu/qemu/commit/30e702abf6fa8a7f1e6ad11a75d6f3a= b6fcb2155=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D A fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D 9pfs: introduce P9Array=0D =0D Implements deep auto free of arrays while retaining common C-style=0D squared bracket access. Main purpose of this API is to get rid of=0D error prone individual array deallocation pathes in user code, i.e.=0D turning something like this:=0D =0D void doSomething(size_t n) {=0D Foo *foos =3D malloc(n * sizeof(Foo));=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D goto out;=0D }=0D }=0D out:=0D if (...) {=0D for (...) {=0D /* deep deallocation */=0D free(foos[i].s);=0D }=0D /* array deallocation */=0D free(foos);=0D }=0D }=0D =0D into something more simple and safer like:=0D =0D void doSomething(size_t n) {=0D P9ARRAY_REF(Foo) foos =3D NULL;=0D P9ARRAY_NEW(Foo, foos, n);=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D return; /* array auto freed here */=0D }=0D }=0D /* array auto freed here */=0D }=0D =0D Unlike GArray, P9Array does not require special macros, function=0D calls or struct member dereferencing to access the individual array=0D elements:=0D =0D C-array =3D P9Array: vs. GArray:=0D =0D for (...) { | for (...) {=0D ... =3D arr[i].m; | ... =3D g_array_index(arr, Foo, i).m;=0D= arr[i].m =3D ... ; | g_array_index(arr, Foo, i).m =3D ... ;=0D= } | }=0D =0D So existing C-style array code can be retained with only very little=0D changes; basically limited to replacing array allocation call and of=0D course removing individual array deallocation pathes.=0D =0D In this initial version P9Array only supports the concept of unique=0D pointers, i.e. it does not support reference counting. The array (and=0D all dynamically allocated memory of individual array elements) is auto=0D= freed once execution leaves the scope of the reference variable (unique=0D= pointer) associated with the array.=0D =0D Internally a flex array struct is used in combination with macros=0D spanned over a continuous memory space for both the array's meta data=0D (private) and the actual C-array user data (public):=0D =0D struct P9Array##scalar_type {=0D size_t len; /* private, hidden from user code */=0D scalar_type first[]; /* public, directly exposed to user code */=0D= };=0D =0D Which has the advantage that the compiler automatically takes care=0D about correct padding, alignment and overall size for all scalar data=0D types on all systems and that the user space exposed pointer can=0D directly be translated back and forth between user space C-array=0D pointer and internal P9Array struct whenever needed, in a type-safe=0D manner.=0D =0D This header file is released under MIT license, to allow this file=0D being used in other C-projects as well. The common QEMU license=0D GPL2+ might have construed a conflict for other projects.=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: c0451f0bc4210d262268ff51c053a9277f20f862=0D https://github.com/qemu/qemu/commit/c0451f0bc4210d262268ff51c053a92= 77f20f862=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D =0D Make sure at compile time that the scalar type of the array=0D requested to be created via P9ARRAY_NEW() matches the scalar=0D type of the passed auto reference variable (unique pointer).=0D =0D Suggested-by: Richard Henderson =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: 42bdeb04b6a4bf3e54f4d7f87193803268ba8255=0D https://github.com/qemu/qemu/commit/42bdeb04b6a4bf3e54f4d7f87193803= 268ba8255=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsString usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: cc82fde9c7b4b598907914896ee6942fa866258c=0D https://github.com/qemu/qemu/commit/cc82fde9c7b4b598907914896ee6942= fa866258c=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/file-op-9p.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsPath usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <79a0ddf8375f6c95f0565ef155a1bf1e9387664f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 7e985780aaab93d2c5be9b62d8d386568dfb071e=0D https://github.com/qemu/qemu/commit/7e985780aaab93d2c5be9b62d8d3865= 68dfb071e=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: use P9Array in v9fs_walk()=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <90c65d1c1ca11c1b434bb981b1fc7966f7711c8f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: c52d69e7dbaaed0ffdef8125e79218672c30161d=0D https://github.com/qemu/qemu/commit/c52d69e7dbaaed0ffdef8125e792186= 72c30161d=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D M fsdev/file-op-9p.h=0D A fsdev/p9array.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-2021102= 7' into staging=0D =0D 9pfs: performance fix and cleanup=0D =0D * First patch fixes suboptimal I/O performance on guest due to previously= =0D incorrect block size being transmitted to 9p client.=0D =0D * Subsequent patches are cleanup ones intended to reduce code complexity.= =0D =0D * remotes/cschoenebeck/tags/pull-9p-20211027:=0D 9pfs: use P9Array in v9fs_walk()=0D 9pfs: make V9fsPath usable via P9Array API=0D 9pfs: make V9fsString usable via P9Array API=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D 9pfs: introduce P9Array=0D 9pfs: simplify blksize_to_iounit()=0D 9pfs: deduplicate iounit code=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/5c49c6c241e5...c52d69e7dbaa= =0D From MAILER-DAEMON Wed Oct 27 17:03:15 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfq4p-0003wN-Kp for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 17:03:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfq4o-0003wE-Dv for qemu-commits@nongnu.org; Wed, 27 Oct 2021 17:03:14 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:49217 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfq4l-0005k3-4Y for qemu-commits@nongnu.org; Wed, 27 Oct 2021 17:03:13 -0400 Received: from github.com (hubbernetes-node-3f3c2be.ac4-iad.github.net [10.52.201.56]) by smtp.github.com (Postfix) with ESMTPA id 74DC7520763 for ; Wed, 27 Oct 2021 14:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635368590; bh=L/wAb4Boyf+AMu5Uf8GJgD/9Dtwvf44Zn4c3YhaaTk8=; h=Date:From:To:Subject:From; b=QOYQFGy7cbDak43Q1ILZqjBYw81qxaG/YZ9vZfo3HkGp8NSjGI4shXgpmdiGHjZxQ HIKoTAjZDMOCv/zmr8/bjV7toC/s/14SyvlNsnrTnWokFgqGpLHoeuZbKs7EXAHzpc tofl7Rpp0xXHOcbNAGjxjeZAY7GUM1UK5t2ps7WU= Date: Wed, 27 Oct 2021 14:03:10 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 669ced: 9pfs: fix wrong I/O block size in Rgetattr X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Oct 2021 21:03:14 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 669ced09b3b6070d478acce51810591b78ab0ccd=0D https://github.com/qemu/qemu/commit/669ced09b3b6070d478acce51810591= b78ab0ccd=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D When client sent a 9p Tgetattr request then the wrong I/O block=0D size value was returned by 9p server; instead of host file=0D system's I/O block size it should rather return an I/O block=0D size according to 9p session's 'msize' value, because the value=0D returned to client should be an "optimum" block size for I/O=0D (i.e. to maximize performance), it should not reflect the actual=0D physical block size of the underlying storage media.=0D =0D The I/O block size of a host filesystem is typically 4k, so the=0D value returned was far too low for good 9p I/O performance.=0D =0D This patch adds stat_to_iounit() with a similar approach as the=0D existing get_iounit() function.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: =0D =0D =0D Commit: b565bccb00afe8b73d529bbc3a38682996dac5c7=0D https://github.com/qemu/qemu/commit/b565bccb00afe8b73d529bbc3a38682= 996dac5c7=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: deduplicate iounit code=0D =0D Remove redundant code that translates host fileystem's block=0D size into 9p client (guest side) block size.=0D =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Message-Id: <129bb71d5119e61d335f1e3107e472e4beea223a.1632758315.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 04a7f9e55e0930b87805f7c97851eea4610e78fc=0D https://github.com/qemu/qemu/commit/04a7f9e55e0930b87805f7c97851eea= 4610e78fc=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: simplify blksize_to_iounit()=0D =0D Use QEMU_ALIGN_DOWN() macro to reduce code and to make it=0D more human readable.=0D =0D Suggested-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Christian Schoenebeck =0D Reviewed-by: Greg Kurz =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D =0D =0D Commit: 30e702abf6fa8a7f1e6ad11a75d6f3ab6fcb2155=0D https://github.com/qemu/qemu/commit/30e702abf6fa8a7f1e6ad11a75d6f3a= b6fcb2155=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D A fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D 9pfs: introduce P9Array=0D =0D Implements deep auto free of arrays while retaining common C-style=0D squared bracket access. Main purpose of this API is to get rid of=0D error prone individual array deallocation pathes in user code, i.e.=0D turning something like this:=0D =0D void doSomething(size_t n) {=0D Foo *foos =3D malloc(n * sizeof(Foo));=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D goto out;=0D }=0D }=0D out:=0D if (...) {=0D for (...) {=0D /* deep deallocation */=0D free(foos[i].s);=0D }=0D /* array deallocation */=0D free(foos);=0D }=0D }=0D =0D into something more simple and safer like:=0D =0D void doSomething(size_t n) {=0D P9ARRAY_REF(Foo) foos =3D NULL;=0D P9ARRAY_NEW(Foo, foos, n);=0D for (...) {=0D foos[i].s =3D malloc(...);=0D if (...) {=0D return; /* array auto freed here */=0D }=0D }=0D /* array auto freed here */=0D }=0D =0D Unlike GArray, P9Array does not require special macros, function=0D calls or struct member dereferencing to access the individual array=0D elements:=0D =0D C-array =3D P9Array: vs. GArray:=0D =0D for (...) { | for (...) {=0D ... =3D arr[i].m; | ... =3D g_array_index(arr, Foo, i).m;=0D= arr[i].m =3D ... ; | g_array_index(arr, Foo, i).m =3D ... ;=0D= } | }=0D =0D So existing C-style array code can be retained with only very little=0D changes; basically limited to replacing array allocation call and of=0D course removing individual array deallocation pathes.=0D =0D In this initial version P9Array only supports the concept of unique=0D pointers, i.e. it does not support reference counting. The array (and=0D all dynamically allocated memory of individual array elements) is auto=0D= freed once execution leaves the scope of the reference variable (unique=0D= pointer) associated with the array.=0D =0D Internally a flex array struct is used in combination with macros=0D spanned over a continuous memory space for both the array's meta data=0D (private) and the actual C-array user data (public):=0D =0D struct P9Array##scalar_type {=0D size_t len; /* private, hidden from user code */=0D scalar_type first[]; /* public, directly exposed to user code */=0D= };=0D =0D Which has the advantage that the compiler automatically takes care=0D about correct padding, alignment and overall size for all scalar data=0D types on all systems and that the user space exposed pointer can=0D directly be translated back and forth between user space C-array=0D pointer and internal P9Array struct whenever needed, in a type-safe=0D manner.=0D =0D This header file is released under MIT license, to allow this file=0D being used in other C-projects as well. The common QEMU license=0D GPL2+ might have construed a conflict for other projects.=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: c0451f0bc4210d262268ff51c053a9277f20f862=0D https://github.com/qemu/qemu/commit/c0451f0bc4210d262268ff51c053a92= 77f20f862=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/p9array.h=0D =0D Log Message:=0D -----------=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D =0D Make sure at compile time that the scalar type of the array=0D requested to be created via P9ARRAY_NEW() matches the scalar=0D type of the passed auto reference variable (unique pointer).=0D =0D Suggested-by: Richard Henderson =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: 42bdeb04b6a4bf3e54f4d7f87193803268ba8255=0D https://github.com/qemu/qemu/commit/42bdeb04b6a4bf3e54f4d7f87193803= 268ba8255=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsString usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: =0D =0D =0D Commit: cc82fde9c7b4b598907914896ee6942fa866258c=0D https://github.com/qemu/qemu/commit/cc82fde9c7b4b598907914896ee6942= fa866258c=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/file-op-9p.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: make V9fsPath usable via P9Array API=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <79a0ddf8375f6c95f0565ef155a1bf1e9387664f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: 7e985780aaab93d2c5be9b62d8d386568dfb071e=0D https://github.com/qemu/qemu/commit/7e985780aaab93d2c5be9b62d8d3865= 68dfb071e=0D Author: Christian Schoenebeck =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D 9pfs: use P9Array in v9fs_walk()=0D =0D Signed-off-by: Christian Schoenebeck =0D Message-Id: <90c65d1c1ca11c1b434bb981b1fc7966f7711c8f.1633097129.git.qemu= _oss@crudebyte.com>=0D =0D =0D Commit: c52d69e7dbaaed0ffdef8125e79218672c30161d=0D https://github.com/qemu/qemu/commit/c52d69e7dbaaed0ffdef8125e792186= 72c30161d=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M fsdev/9p-marshal.c=0D M fsdev/9p-marshal.h=0D M fsdev/file-op-9p.h=0D A fsdev/p9array.h=0D M hw/9pfs/9p.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-2021102= 7' into staging=0D =0D 9pfs: performance fix and cleanup=0D =0D * First patch fixes suboptimal I/O performance on guest due to previously= =0D incorrect block size being transmitted to 9p client.=0D =0D * Subsequent patches are cleanup ones intended to reduce code complexity.= =0D =0D * remotes/cschoenebeck/tags/pull-9p-20211027:=0D 9pfs: use P9Array in v9fs_walk()=0D 9pfs: make V9fsPath usable via P9Array API=0D 9pfs: make V9fsString usable via P9Array API=0D fsdev/p9array.h: check scalar type in P9ARRAY_NEW()=0D 9pfs: introduce P9Array=0D 9pfs: simplify blksize_to_iounit()=0D 9pfs: deduplicate iounit code=0D 9pfs: fix wrong I/O block size in Rgetattr=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/5c49c6c241e5...c52d69e7dbaa= =0D From MAILER-DAEMON Wed Oct 27 22:43:04 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mfvNg-0006Rx-CO for mharc-qemu-commits@gnu.org; Wed, 27 Oct 2021 22:43:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfvNZ-0006MU-N0 for qemu-commits@nongnu.org; Wed, 27 Oct 2021 22:42:57 -0400 Received: from out-18.smtp.github.com ([192.30.252.201]:34851 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfvNV-00049R-Aq for qemu-commits@nongnu.org; Wed, 27 Oct 2021 22:42:57 -0400 Received: from github.com (hubbernetes-node-a62d878.va3-iad.github.net [10.48.205.41]) by smtp.github.com (Postfix) with ESMTPA id 083EF340049 for ; Wed, 27 Oct 2021 19:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635388972; bh=nEUMrXjarPac3gDZ5l8BOEy39Z3mDc0uIYgDL6ZGD1o=; h=Date:From:To:Subject:From; b=af9nsM85FrnIA9bMVHQMRK2MPffXoeQANulQKq+LU/btHaC8Y1RoksBidJZarFdmw a1PTQMyQQ986pL5+Lrh3vMKXl1e58lo9P2hodVUKsJvXnquKiter3nwR7Oh8qfk8X2 /00zfzVBojzaIOVBRsULt4MbsBb6LlXVb/B33HMI= Date: Wed, 27 Oct 2021 19:42:52 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.201; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 1c4693: qemu/int128: Add int128_{not, xor} X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 02:42:57 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 1c46937358fc27a9e446d08c877389ee84d6767d=0D https://github.com/qemu/qemu/commit/1c46937358fc27a9e446d08c877389e= e84d6767d=0D Author: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qemu/int128.h=0D =0D Log Message:=0D -----------=0D qemu/int128: Add int128_{not,xor}=0D =0D Addition of not and xor on 128-bit integers.=0D =0D Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Co-authored-by: Fabien Portas =0D Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.= fr>=0D [rth: Split out logical operations.]=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9276a31c3484ff236a958a1e2a38beefb0eb7ebb=0D https://github.com/qemu/qemu/commit/9276a31c3484ff236a958a1e2a38bee= fb0eb7ebb=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: move checks out of divu128/divs128=0D =0D In preparation for changing the divu128/divs128 implementations=0D to allow for quotients larger than 64 bits, move the div-by-zero=0D and overflow checks to the callers.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8ac2d6c526d9ea0c89c8aa7046ca56e1b1b9d130=0D https://github.com/qemu/qemu/commit/8ac2d6c526d9ea0c89c8aa7046ca56e= 1b1b9d130=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/qemu/host-utils.h=0D =0D Log Message:=0D -----------=0D host-utils: move udiv_qrnnd() to host-utils=0D =0D Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,=0D so it can be reused by divu128().=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 40f3e79a862554553811d0681c05e00a4705e91c=0D https://github.com/qemu/qemu/commit/40f3e79a862554553811d0681c05e00= a4705e91c=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: add 128-bit quotient support to divu128/divs128=0D =0D These will be used to implement new decimal floating point=0D instructions from Power ISA 3.1.=0D =0D The remainder is now returned directly by divu128/divs128,=0D freeing up phigh to receive the high 64 bits of the quotient.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 023462978a1fb7b5a3f7ea74236a05d253d0b6e6=0D https://github.com/qemu/qemu/commit/023462978a1fb7b5a3f7ea74236a05d= 253d0b6e6=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D =0D Log Message:=0D -----------=0D host-utils: add unit tests for divu128/divs128=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-5-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b1fde411d0f3dd146ba9864f3a475e7100a14a3b=0D https://github.com/qemu/qemu/commit/b1fde411d0f3dd146ba9864f3a475e7= 100a14a3b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Rename "mask" to "z_mask"=0D =0D Prepare for tracking different masks by renaming this one.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3b3f847d754d7f243b2a04775f37c1b324ca1a12=0D https://github.com/qemu/qemu/commit/3b3f847d754d7f243b2a04775f37c1b= 324ca1a12=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out OptContext=0D =0D Provide what will become a larger context for splitting=0D the very large tcg_optimize function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b10f38339bda94bd960d6936ca6047b34be8eb31=0D https://github.com/qemu/qemu/commit/b10f38339bda94bd960d6936ca6047b= 34be8eb31=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Remove do_default label=0D =0D Break the final cleanup clause out of the main switch=0D statement. When fully folding an opcode to mov/movi,=0D use "continue" to process the next opcode, else break=0D to fall into the final cleanup.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dc84988a5f4147b8c1f90ed4cdcf5c57f06749cd=0D https://github.com/qemu/qemu/commit/dc84988a5f4147b8c1f90ed4cdcf5c5= 7f06749cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change tcg_opt_gen_{mov,movi} interface=0D =0D Adjust the interface to take the OptContext parameter instead=0D of TCGContext or both.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: d0ed5151b11b12e9e2ca3c9adde2fd4444588948=0D https://github.com/qemu/qemu/commit/d0ed5151b11b12e9e2ca3c9adde2fd4= 444588948=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Move prev_mb into OptContext=0D =0D This will expose the variable to subroutines that=0D will be broken out of tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e2577ea24f9974ab0fb2a2b255203bad0c878f91=0D https://github.com/qemu/qemu/commit/e2577ea24f9974ab0fb2a2b255203ba= d0c878f91=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out init_arguments=0D =0D There was no real reason for calls to have separate code here.=0D Unify init for calls vs non-calls using the call path, which=0D handles TCG_CALL_DUMMY_ARG.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8774dded029c96130aacf6e6bb71b70cf271b8df=0D https://github.com/qemu/qemu/commit/8774dded029c96130aacf6e6bb71b70= cf271b8df=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out copy_propagate=0D =0D Continue splitting tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5cf32be7d8f385d1599655fdb9de87996243f33b=0D https://github.com/qemu/qemu/commit/5cf32be7d8f385d1599655fdb9de879= 96243f33b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_call=0D =0D Calls are special in that they have a variable number=0D of arguments, and need to be able to clobber globals.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ec5d4cbeef2749c9137daeac1b7f67735510675b=0D https://github.com/qemu/qemu/commit/ec5d4cbeef2749c9137daeac1b7f677= 35510675b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Drop nb_oargs, nb_iargs locals=0D =0D Rather than try to keep these up-to-date across folding,=0D re-read nb_oargs at the end, after re-reading the opcode.=0D =0D A couple of asserts need dropping, but that will take care=0D of itself as we split the function further.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8d57bf1e82da9c1a71c16b12545a9e8d347690f3=0D https://github.com/qemu/qemu/commit/8d57bf1e82da9c1a71c16b12545a9e8= d347690f3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change fail return for do_constant_folding_cond*=0D =0D Return -1 instead of 2 for failure, so that we can=0D use comparisons against 0 for all cases.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b99d5bf388655b340e93412bf60f8bff90e5870=0D https://github.com/qemu/qemu/commit/6b99d5bf388655b340e93412bf60f8b= ff90e5870=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Return true from tcg_opt_gen_{mov,movi}=0D =0D This will allow callers to tail call to these functions=0D and return true indicating processing complete.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 137f1f4429965d9a702fae9fc89f2604449a24d3=0D https://github.com/qemu/qemu/commit/137f1f4429965d9a702fae9fc89f260= 4449a24d3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out finish_folding=0D =0D Copy z_mask into OptContext, for writeback to the=0D first output within the new function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 404a148d891bf18fc564fa94b00970bbc2c0feec=0D https://github.com/qemu/qemu/commit/404a148d891bf18fc564fa94b00970b= bc2c0feec=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use a boolean to avoid a mass of continues=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3eefdf2b5885dca36eefa200862c661654519162=0D https://github.com/qemu/qemu/commit/3eefdf2b5885dca36eefa200862c661= 654519162=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}=0D =0D This puts the separate mb optimization into the same framework=0D as the others. While fold_qemu_{ld,st} are currently identical,=0D that won't last as more code gets moved.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2f9f08ba43df3ea76124f66ae3fe99a96a0a072f=0D https://github.com/qemu/qemu/commit/2f9f08ba43df3ea76124f66ae3fe99a= 96a0a072f=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_const{1,2}=0D =0D Split out a whole bunch of placeholder functions, which are=0D currently identical. That won't last as more code gets moved.=0D =0D Use CASE_32_64_VEC for some logical operators that previously=0D missed the addition of vectors.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bc47b1aa5be9f90cdbf7fbb01717e4259f717bb9=0D https://github.com/qemu/qemu/commit/bc47b1aa5be9f90cdbf7fbb01717e42= 59f717bb9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 764d2aba08c35f2462371b01c27fb032447afcd8=0D https://github.com/qemu/qemu/commit/764d2aba08c35f2462371b01c27fb03= 2447afcd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 079b08040e0c4eed96b3c19fe37cf17a46294d2b=0D https://github.com/qemu/qemu/commit/079b08040e0c4eed96b3c19fe37cf17= a46294d2b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c63ff55cc5d27b81e6a0924bd1f9abea262069a9=0D https://github.com/qemu/qemu/commit/c63ff55cc5d27b81e6a0924bd1f9abe= a262069a9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b8ac0d1498cf6638e3d50c33e06e5b3b0e7a2d7=0D https://github.com/qemu/qemu/commit/6b8ac0d1498cf6638e3d50c33e06e5b= 3b0e7a2d7=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mulu2_i32=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e3f7dc216744aceb46fb67be1476b518bc48c5ff=0D https://github.com/qemu/qemu/commit/e3f7dc216744aceb46fb67be1476b51= 8bc48c5ff=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_addsub2_i32=0D =0D Add two additional helpers, fold_add2_i32 and fold_sub2_i32=0D which will not be simple wrappers forever.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0c310a3005b59a1e3667654b9c88ddaa32eaf166=0D https://github.com/qemu/qemu/commit/0c310a3005b59a1e3667654b9c88dda= a32eaf166=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_movcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dcd08996c9420a0d22399e0cc53117d2043a02bb=0D https://github.com/qemu/qemu/commit/dcd08996c9420a0d22399e0cc53117d= 2043a02bb=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6617c8821548350a490c14894a4fe0dba07fc73=0D https://github.com/qemu/qemu/commit/b6617c8821548350a490c14894a4fe0= dba07fc73=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract, fold_sextract=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1b1907b8460467743fd23cef918fac9dd7858441=0D https://github.com/qemu/qemu/commit/1b1907b8460467743fd23cef918fac9= dd7858441=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_deposit=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 30dd0bfeb5385342a7f216e661d9b69f6ec7182e=0D https://github.com/qemu/qemu/commit/30dd0bfeb5385342a7f216e661d9b69= f6ec7182e=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_count_zeros=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 09bacdc2632581cafd2878d91d62ba69dc7574f0=0D https://github.com/qemu/qemu/commit/09bacdc2632581cafd2878d91d62ba6= 9dc7574f0=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_bswap=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8cdb3fcb8e69502963ca4127fab656e5ffe2be93=0D https://github.com/qemu/qemu/commit/8cdb3fcb8e69502963ca4127fab656e= 5ffe2be93=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_dup, fold_dup2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2cfac7fa482e015310968ee68b001db94789d190=0D https://github.com/qemu/qemu/commit/2cfac7fa482e015310968ee68b001db= 94789d190=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mov=0D =0D This is the final entry in the main switch that was in a=0D different form. After this, we have the option to convert=0D the switch into a function dispatch table.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: cbe42fb2f22b9adb8b78374f6ff4ca5f58807208=0D https://github.com/qemu/qemu/commit/cbe42fb2f22b9adb8b78374f6ff4ca5= f58807208=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_i=0D =0D Pull the "op r, a, a =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ca7bb049a0250890afd4dd0e66f10b8a4d51715c=0D https://github.com/qemu/qemu/commit/ca7bb049a0250890afd4dd0e66f10b8= a4d51715c=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_x=0D =0D Pull the "op r, a, a =3D> mov r, a" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e8679955ec0791122a6c22d48ae760a215204f6a=0D https://github.com/qemu/qemu/commit/e8679955ec0791122a6c22d48ae760a= 215204f6a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_i=0D =0D Pull the "op r, a, 0 =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 67f84c962166093f26a1f2c66034a44cf294e809=0D https://github.com/qemu/qemu/commit/67f84c962166093f26a1f2c66034a44= cf294e809=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Add type to OptContext=0D =0D Compute the type of the operation early.=0D =0D There are at least 4 places that used a def->flags ladder=0D to determine the type of the operation being optimized.=0D =0D There were two places that assumed !TCG_OPF_64BIT means=0D TCG_TYPE_I32, and so could potentially compute incorrect=0D results for vector operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0e0a32bacb29c4313ef195d2ea18809fd25cf5e2=0D https://github.com/qemu/qemu/commit/0e0a32bacb29c4313ef195d2ea18809= fd25cf5e2=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_to_not=0D =0D Split out the conditional conversion from a more complex logical=0D operation to a simple NOT. Create a couple more helpers to make=0D this easy for the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9caca88a76a6b1e5203dd2470800941c2670a9cd=0D https://github.com/qemu/qemu/commit/9caca88a76a6b1e5203dd2470800941= c2670a9cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_sub_to_neg=0D =0D Even though there is only one user, place this more complex=0D conversion into its own helper.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a63ce0e9cb860439d4277bd6dca696bce1f1bb6b=0D https://github.com/qemu/qemu/commit/a63ce0e9cb860439d4277bd6dca696b= ce1f1bb6b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_x=0D =0D Pull the "op r, a, i =3D> mov r, a" optimization into a function,=0D and use them in the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: da48e2720227473041b7a14dd9f838577d36833a=0D https://github.com/qemu/qemu/commit/da48e2720227473041b7a14dd9f8385= 77d36833a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_ix_to_i=0D =0D Pull the "op r, 0, b =3D> movi r, 0" optimization into a function,=0D and use it in fold_shift.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fae450ba4764dcf8c7a131131639ac0969a8eae8=0D https://github.com/qemu/qemu/commit/fae450ba4764dcf8c7a131131639ac0= 969a8eae8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_masks=0D =0D Move all of the known-zero optimizations into the per-opcode=0D functions. Use fold_masks when there is a possibility of the=0D result being determined, and simply set ctx->z_mask otherwise.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 407112b03d7665a3cb7b3a21105e721a8a0c5fd8=0D https://github.com/qemu/qemu/commit/407112b03d7665a3cb7b3a21105e721= a8a0c5fd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D =0D Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,=0D and muls2_i64.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9531c078ff63783f2a21ba302827123e7b073304=0D https://github.com/qemu/qemu/commit/9531c078ff63783f2a21ba302827123= e7b073304=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D =0D Rename to fold_addsub2.=0D Use Int128 to implement the wider operation.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 7a2f70845255bd6a2ad6399d159c58a7e7b64b51=0D https://github.com/qemu/qemu/commit/7a2f70845255bd6a2ad6399d159c58a= 7e7b64b51=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D =0D Most of these are handled by creating a fold_const2_commutative=0D to handle all of the binary operators. The rest were already=0D handled on a case-by-case basis in the switch, and have their=0D own fold function in which to place the call.=0D =0D We now have only one major switch on TCGOpcode.=0D =0D Introduce NO_DEST and a block comment for swap_commutative in=0D order to make the handling of brcond and movcond opcodes cleaner.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 77babeedd41f7b890a32d0f6955d2a407c9aaab4=0D https://github.com/qemu/qemu/commit/77babeedd41f7b890a32d0f6955d2a4= 07c9aaab4=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D =0D This "garbage" setting pre-dates the addition of the type=0D changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,=0D and INDEX_op_extr{l,h}_i64_i32.=0D =0D So now we have a definitive points at which to adjust z_mask=0D to eliminate such bits from the 32-bit operands.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fbf16492dd0c0ae76ab040791d8a50c46a7f272b=0D https://github.com/qemu/qemu/commit/fbf16492dd0c0ae76ab040791d8a50c= 46a7f272b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for orc=0D =0D Recognize the constant function for or-complement.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6247051402da3bbfaec78006ec8a64362a9d97f=0D https://github.com/qemu/qemu/commit/b6247051402da3bbfaec78006ec8a64= 362a9d97f=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for mul=0D =0D Recognize the identity function for low-part multiply.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bc942d5c35f5ba613762545de624a47cc9fbf35f=0D https://github.com/qemu/qemu/commit/bc942d5c35f5ba613762545de624a47= cc9fbf35f=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for div=0D =0D Recognize the identity function for division.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1727897e1d22dad474b0c72e35e304d8894bc77d=0D https://github.com/qemu/qemu/commit/1727897e1d22dad474b0c72e35e304d= 8894bc77d=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for rem=0D =0D Recognize the constant function for remainder.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 76a95403bf8d7831be43255eaf871da9436786dd=0D https://github.com/qemu/qemu/commit/76a95403bf8d7831be43255eaf871da= 9436786dd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Optimize sign extensions=0D =0D Certain targets, like riscv, produce signed 32-bit results.=0D This can lead to lots of redundant extensions as values are=0D manipulated.=0D =0D Begin by tracking only the obvious sign-extensions, and=0D converting them to simple copies when possible.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a62b16e5c9c51514928fcf3ee6a4fab0dd6d2f37=0D https://github.com/qemu/qemu/commit/a62b16e5c9c51514928fcf3ee6a4fab= 0dd6d2f37=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for logical operations=0D =0D Sign repetitions are perforce all identical, whether they are 1 or 0.=0D Bitwise operations preserve the relative quantity of the repetitions.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6cf6408bb191953a0f160f47c937a45d4a6ddd3=0D https://github.com/qemu/qemu/commit/b6cf6408bb191953a0f160f47c937a4= 5d4a6ddd3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for setcond=0D =0D The result is either 0 or 1, which means that we have=0D a 2 bit signed result, and thus 62 bits of sign.=0D For clarity, use the smask_from_zmask function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 654011f5b3610a55da8ed4d680f4b25a63fdfba5=0D https://github.com/qemu/qemu/commit/654011f5b3610a55da8ed4d680f4b25= a63fdfba5=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for bit counting=0D =0D The results are generally 6 bit unsigned values, though=0D the count leading and trailing bits may produce any value=0D for a zero input.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 820c025f0dcacf2f3c12735b1f162893fbfa7bc6=0D https://github.com/qemu/qemu/commit/820c025f0dcacf2f3c12735b1f16289= 3fbfa7bc6=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for shifting=0D =0D For constant shifts, we can simply shift the s_mask.=0D =0D For variable shifts, we know that sar does not reduce=0D the s_mask, which helps for sequences like=0D =0D ext32s_i64 t, in=0D sar_i64 t, t, v=0D ext32s_i64 out, t=0D =0D allowing the final extend to be eliminated.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 80e9c5ade49e318f041abee291b47f281e20ee37=0D https://github.com/qemu/qemu/commit/80e9c5ade49e318f041abee291b47f2= 81e20ee37=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M include/qemu/int128.h=0D M target/ppc/int_helper.c=0D M tcg/optimize.c=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211027' into = staging=0D =0D Improvements to qemu/int128=0D Fixes for 128/64 division.=0D Cleanup tcg/optimize.c=0D Optimize redundant sign extensions=0D =0D # gpg: Signature made Wed 27 Oct 2021 07:40:01 PM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211027: (56 commits)=0D tcg/optimize: Propagate sign info for shifting=0D tcg/optimize: Propagate sign info for bit counting=0D tcg/optimize: Propagate sign info for setcond=0D tcg/optimize: Propagate sign info for logical operations=0D tcg/optimize: Optimize sign extensions=0D tcg/optimize: Use fold_xx_to_i for rem=0D tcg/optimize: Use fold_xi_to_x for div=0D tcg/optimize: Use fold_xi_to_x for mul=0D tcg/optimize: Use fold_xx_to_i for orc=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D tcg/optimize: Split out fold_masks=0D tcg/optimize: Split out fold_ix_to_i=0D tcg/optimize: Split out fold_xi_to_x=0D tcg/optimize: Split out fold_sub_to_neg=0D tcg/optimize: Split out fold_to_not=0D tcg/optimize: Add type to OptContext=0D tcg/optimize: Split out fold_xi_to_i=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c52d69e7dbaa...80e9c5ade49e= =0D From MAILER-DAEMON Thu Oct 28 10:53:19 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mg6mN-0005CD-Fw for mharc-qemu-commits@gnu.org; Thu, 28 Oct 2021 10:53:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mg6mL-00055T-RV for qemu-commits@nongnu.org; Thu, 28 Oct 2021 10:53:17 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:36499 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mg6mG-0004m0-Sb for qemu-commits@nongnu.org; Thu, 28 Oct 2021 10:53:17 -0400 Received: from github.com (hubbernetes-node-f46ca13.ash1-iad.github.net [10.56.120.53]) by smtp.github.com (Postfix) with ESMTPA id 11275840EA4 for ; Thu, 28 Oct 2021 07:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635432792; bh=pG69Eg57xUSyB1+cylgiYwWf4tJEXSp3qAWHcEslUXg=; h=Date:From:To:Subject:From; b=PbLxFphhYADtsEHm5ryFJRfzKImXrLiaoncuOVFmLSe9HraWQnX+6n9plW2dgSoJU Qr7Fo6fCxgCE2j2lj7dDcjrgjo5jI2OeSiBlmLeYaSSerbBbE8ewkr7swst4ZWB3/e +KHElJcIGkUh6BWyBsviJn0oZIDFZ4FOjBGulyVc= Date: Thu, 28 Oct 2021 07:53:12 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f9516e: monitor/hmp: add support for flag argument with value X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 14:53:18 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: f9516e380ec43707af14e712c09a586501baf33e=0D https://github.com/qemu/qemu/commit/f9516e380ec43707af14e712c09a586= 501baf33e=0D Author: Stefan Reiter =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M monitor/hmp.c=0D M monitor/monitor-internal.h=0D =0D Log Message:=0D -----------=0D monitor/hmp: add support for flag argument with value=0D =0D Adds support for the "-xV" parameter type, where "-x" denotes a flag=0D name and the "V" suffix indicates that this flag is supposed to take an=0D= arbitrary string parameter.=0D =0D These parameters are always optional, the entry in the qdict will be=0D omitted if the flag is not given.=0D =0D Signed-off-by: Stefan Reiter =0D Message-Id: <20211021100135.4146766-2-s.reiter@proxmox.com>=0D Reviewed-by: Dr. David Alan Gilbert =0D Acked-by: Gerd Hoffmann =0D Signed-off-by: Markus Armbruster =0D =0D =0D Commit: 9b8c77b167d9a5828d02302875906eb08a02baf0=0D https://github.com/qemu/qemu/commit/9b8c77b167d9a5828d02302875906eb= 08a02baf0=0D Author: Stefan Reiter =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M monitor/hmp-cmds.c=0D M monitor/qmp-cmds.c=0D M qapi/ui.json=0D =0D Log Message:=0D -----------=0D qapi/monitor: refactor set/expire_password with enums=0D =0D 'protocol' and 'connected' are better suited as enums than as strings,=0D= make use of that. No functional change intended.=0D =0D Suggested-by: Markus Armbruster =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: Stefan Reiter =0D Message-Id: <20211021100135.4146766-3-s.reiter@proxmox.com>=0D Acked-by: Gerd Hoffmann =0D Signed-off-by: Markus Armbruster =0D =0D =0D Commit: ddf513eaddc494e338a1db3da26050e798721267=0D https://github.com/qemu/qemu/commit/ddf513eaddc494e338a1db3da26050e= 798721267=0D Author: Stefan Reiter =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hmp-commands.hx=0D M monitor/hmp-cmds.c=0D M monitor/qmp-cmds.c=0D M qapi/ui.json=0D =0D Log Message:=0D -----------=0D qapi/monitor: allow VNC display id in set/expire_password=0D =0D It is possible to specify more than one VNC server on the command line,=0D= either with an explicit ID or the auto-generated ones =C3=A0 la "default"= ,=0D "vnc2", "vnc3", ...=0D =0D It is not possible to change the password on one of these extra VNC=0D displays though. Fix this by adding a "display" parameter to the=0D "set_password" and "expire_password" QMP and HMP commands.=0D =0D For HMP, the display is specified using the "-d" value flag.=0D =0D For QMP, the schema is updated to explicitly express the supported=0D variants of the commands with protocol-discriminated unions.=0D =0D Suggested-by: Markus Armbruster =0D Signed-off-by: Stefan Reiter =0D Message-Id: <20211021100135.4146766-4-s.reiter@proxmox.com>=0D Reviewed-by: Markus Armbruster =0D Acked-by: Gerd Hoffmann =0D Signed-off-by: Markus Armbruster =0D =0D =0D Commit: 47c849357b57c1fbd3d3355c586c4784c6f4188e=0D https://github.com/qemu/qemu/commit/47c849357b57c1fbd3d3355c586c478= 4c6f4188e=0D Author: Stefan Reiter =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M monitor/qmp-cmds.c=0D M qapi/ui.json=0D =0D Log Message:=0D -----------=0D qapi/monitor: only allow 'keep' SetPasswordAction for VNC and deprecate= =0D =0D VNC only supports 'keep' here, enforce this via a seperate=0D SetPasswordActionVnc enum and mark the option 'deprecated' (as it is=0D useless with only one value possible).=0D =0D Also add a deprecation note to docs.=0D =0D Suggested-by: Eric Blake =0D Reviewed-by: Markus Armbruster =0D Signed-off-by: Stefan Reiter =0D Message-Id: <20211021100135.4146766-5-s.reiter@proxmox.com>=0D Acked-by: Gerd Hoffmann =0D Signed-off-by: Markus Armbruster =0D =0D =0D Commit: 15525d3bc1fa810633ca2ea1d2bb55fddd8fb69d=0D https://github.com/qemu/qemu/commit/15525d3bc1fa810633ca2ea1d2bb55f= ddd8fb69d=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M docs/about/deprecated.rst=0D M hmp-commands.hx=0D M monitor/hmp-cmds.c=0D M monitor/hmp.c=0D M monitor/monitor-internal.h=0D M monitor/qmp-cmds.c=0D M qapi/ui.json=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2021-10-= 28' into staging=0D =0D Monitor patches patches for 2021-10-28=0D =0D # gpg: Signature made Wed 27 Oct 2021 10:25:51 PM PDT=0D # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918= 653=0D # gpg: issuer "armbru@redhat.com"=0D # gpg: Good signature from "Markus Armbruster " [full]= =0D # gpg: aka "Markus Armbruster " [ful= l]=0D =0D * remotes/armbru/tags/pull-monitor-2021-10-28:=0D qapi/monitor: only allow 'keep' SetPasswordAction for VNC and deprecate= =0D qapi/monitor: allow VNC display id in set/expire_password=0D qapi/monitor: refactor set/expire_password with enums=0D monitor/hmp: add support for flag argument with value=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/80e9c5ade49e...15525d3bc1fa= =0D From MAILER-DAEMON Thu Oct 28 17:46:16 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgDDz-00034Y-Oh for mharc-qemu-commits@gnu.org; Thu, 28 Oct 2021 17:46:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgDDu-0002zz-FF for qemu-commits@nongnu.org; Thu, 28 Oct 2021 17:46:10 -0400 Received: from out-19.smtp.github.com ([192.30.252.202]:47957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgDDp-0003HZ-3l for qemu-commits@nongnu.org; Thu, 28 Oct 2021 17:46:09 -0400 Received: from github.com (hubbernetes-node-1a1e0a1.va3-iad.github.net [10.48.209.95]) by smtp.github.com (Postfix) with ESMTPA id 1F1D1E08FD for ; Thu, 28 Oct 2021 14:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635457564; bh=+VkXShCOcbaKkGLSZgVTVX3fwIlgjNYBUtaNyEl33lk=; h=Date:From:To:Subject:From; b=iqFvMnBfjAgibJ8TW2vnm7QJ9Ei1X4iRAZ96WsTyIvcCaRdYyzpfn0DpEv9nrIbjm aygZTml3P7bkeTPrDcXeAdNZYZyiU+1gfJMcutd85XlfFff14GfwySgs2o74lCFwa/ F0rcbBSY2Ayc8RHCC6yWj6mV5EhIlvG8a+b/lfT8= Date: Thu, 28 Oct 2021 14:46:04 -0700 From: Jessica Clarke To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.202; envelope-from=noreply@github.com; helo=out-19.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] c18bc8: vhost-user: fix duplicated notifier MR init X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 21:46:11 -0000 Branch: refs/heads/stable-6.0-staging=0D Home: https://github.com/qemu/qemu=0D Commit: c18bc855ade093a1df850a01daf851c478a9cca7=0D https://github.com/qemu/qemu/commit/c18bc855ade093a1df850a01daf851c= 478a9cca7=0D Author: Xueming Li =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/virtio/vhost-user.c=0D =0D Log Message:=0D -----------=0D vhost-user: fix duplicated notifier MR init=0D =0D In case of device resume after suspend, VQ notifier MR still valid.=0D Duplicated registrations explode memory block list and slow down device=0D= resume.=0D =0D Fixes: 44866521bd6e ("vhost-user: support registering external host notif= iers")=0D Cc: tiwei.bie@intel.com=0D Cc: qemu-stable@nongnu.org=0D Cc: Yuwei Zhang =0D =0D Signed-off-by: Xueming Li =0D Message-Id: <20211008080215.590292-1-xuemingl@nvidia.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D (cherry picked from commit a1ed9ef1de87c3e86ff68589604298ec90875a14)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 487a0956a1b802d4db37afaeb4b8b8bb9fe1655f=0D https://github.com/qemu/qemu/commit/487a0956a1b802d4db37afaeb4b8b8b= b9fe1655f=0D Author: David Hildenbrand =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M subprojects/libvhost-user/libvhost-user.c=0D =0D Log Message:=0D -----------=0D libvhost-user: fix VHOST_USER_REM_MEM_REG skipping mmap_addr=0D =0D We end up not copying the mmap_addr of all existing regions, resulting=0D= in a SEGFAULT once we actually try to map/access anything within our=0D memory regions.=0D =0D Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user")=0D= Cc: qemu-stable@nongnu.org=0D Cc: Michael S. Tsirkin =0D Cc: Raphael Norwitz =0D Cc: "Marc-Andr=C3=A9 Lureau" =0D Cc: Stefan Hajnoczi =0D Cc: Paolo Bonzini =0D Cc: Coiby Xu =0D Signed-off-by: David Hildenbrand =0D Message-Id: <20211011201047.62587-1-david@redhat.com>=0D Reviewed-by: Michael S. Tsirkin =0D Signed-off-by: Michael S. Tsirkin =0D Reviewed-by: Raphael Norwitz =0D Reviewed-by: Stefan Hajnoczi =0D (cherry picked from commit 6889eb2d431ae962e3e083b57bff47cd573cb1c4)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: 62a012b0f40658fe6a5e75a7d6373080dcbcc5dd=0D https://github.com/qemu/qemu/commit/62a012b0f40658fe6a5e75a7d637308= 0dcbcc5dd=0D Author: Helge Deller =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M hw/display/artist.c=0D =0D Log Message:=0D -----------=0D hw/display/artist: Fix bug in coordinate extraction in artist_vram_read= () and artist_vram_write()=0D =0D The CDE desktop on HP-UX 10 shows wrongly rendered pixels when the local = screen=0D menu is closed. This bug was introduced by commit c7050f3f167b=0D ("hw/display/artist: Refactor x/y coordination extraction") which convert= ed the=0D coordinate extraction in artist_vram_read() and artist_vram_write() to us= e the=0D ADDR_TO_X and ADDR_TO_Y macros, but forgot to right-shift the address by = 2 as=0D it was done before.=0D =0D Signed-off-by: Helge Deller =0D Fixes: c7050f3f167b ("hw/display/artist: Refactor x/y coordination extrac= tion")=0D Cc: Philippe Mathieu-Daud=C3=A9 =0D Cc: Richard Henderson =0D Cc: Sven Schnelle =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Gerd Hoffmann =0D (cherry picked from commit 01f750f5fef1afd8f6abc0548910f87d473e26d5)=0D Signed-off-by: Michael Roth =0D =0D =0D Commit: db882c5c1871874d0b79dad380129479cb7b3c09=0D https://github.com/qemu/qemu/commit/db882c5c1871874d0b79dad38012947= 9cb7b3c09=0D Author: Jessica Clarke =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M configure=0D =0D Log Message:=0D -----------=0D Partially revert "build: -no-pie is no functional linker flag"=0D =0D This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.=0D= =0D This commit was misguided and broke using --disable-pie on any distro=0D that enables PIE by default in their compiler driver, including Debian=0D= and its derivatives. Whilst -no-pie is not a linker flag, it is a=0D compiler driver flag that ensures -pie is not automatically passed by it=0D= to the linker. Without it, all compile_prog checks will fail as any code=0D= built with the explicit -fno-pie will fail to link with the implicit=0D default -pie due to trying to use position-dependent relocations. The=0D only bug that needed fixing was LDFLAGS_NOPIE being used as a flag for=0D= the linker itself in pc-bios/optionrom/Makefile.=0D =0D Note this does not reinstate exporting LDFLAGS_NOPIE, as it is unused,=0D= since the only previous use was the one that should not have existed. I=0D= have also updated the comment for the -fno-pie and -no-pie checks to=0D reflect what they're actually needed for.=0D =0D Fixes: bbd2d5a8120771ec59b86a80a1f51884e0a26e53=0D Cc: Christian Ehrhardt =0D Cc: Paolo Bonzini =0D Cc: qemu-stable@nongnu.org=0D Signed-off-by: Jessica Clarke =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Michael Roth =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/27c6f20d9d87...db882c5c1871= =0D From MAILER-DAEMON Thu Oct 28 19:12:59 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgEZv-000618-E0 for mharc-qemu-commits@gnu.org; Thu, 28 Oct 2021 19:12:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEZu-00060v-F3 for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:12:58 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:35133 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEZs-0007FZ-ND for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:12:57 -0400 Received: from github.com (hubbernetes-node-85733df.ash1-iad.github.net [10.56.119.31]) by smtp.github.com (Postfix) with ESMTPA id B2A0A840674 for ; Thu, 28 Oct 2021 16:12:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635462775; bh=FaS1pX28ysdzZb5OoIL47WGKVs0XLOCTZHV+p4AD6mA=; h=Date:From:To:Subject:From; b=eNx6TY1kI1tFd1ZyBy7/Q0Mshy779JJp0rVTtT4qRAhOVVNx7RAcX6T1ZmjzhGkYq LFTrg4TdbCsbZvDkdSZ3SbpM70trSC8/+/UTVJSM5p6GLsRC4qym9fgzGF0sxLP+X6 SEIcltm6z2drt1rsrrq0JrLr7zbwNoVAa/hm4mtc= Date: Thu, 28 Oct 2021 16:12:55 -0700 From: Michael Roth To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 9654e5: Update version for 6.0.1 release X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 23:12:58 -0000 Branch: refs/heads/stable-6.0-staging Home: https://github.com/qemu/qemu Commit: 9654e55a747575e2dafbb235a15645c0a48b08c4 https://github.com/qemu/qemu/commit/9654e55a747575e2dafbb235a15645c0a48b08c4 Author: Michael Roth Date: 2021-10-28 (Thu, 28 Oct 2021) Changed paths: M VERSION Log Message: ----------- Update version for 6.0.1 release Signed-off-by: Michael Roth From MAILER-DAEMON Thu Oct 28 19:18:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgEez-0006nL-5l for mharc-qemu-commits@gnu.org; Thu, 28 Oct 2021 19:18:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEey-0006k8-81 for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:18:12 -0400 Received: from out-24.smtp.github.com ([192.30.252.207]:58759) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEev-0001dr-Ks for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:18:10 -0400 Received: from github.com (hubbernetes-node-d75d8b5.ac4-iad.github.net [10.52.211.42]) by smtp.github.com (Postfix) with ESMTPA id C3857600A49 for ; Thu, 28 Oct 2021 16:18:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; 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TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 23:18:12 -0000 Branch: refs/heads/stable-6.0 Home: https://github.com/qemu/qemu From MAILER-DAEMON Thu Oct 28 19:18:14 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgEf0-0006qH-I7 for mharc-qemu-commits@gnu.org; Thu, 28 Oct 2021 19:18:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEex-0006kk-Hq for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:18:11 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:51179 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgEew-0001dv-75 for qemu-commits@nongnu.org; Thu, 28 Oct 2021 19:18:11 -0400 Received: from github.com (hubbernetes-node-859ede5.ac4-iad.github.net [10.52.201.22]) by smtp.github.com (Postfix) with ESMTPA id 9662A56006E for ; Thu, 28 Oct 2021 16:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635463089; bh=9jlEPH93dQANBN1vJbagYiB33eVGQHsajqK/RglUAPs=; h=Date:From:To:Subject:From; b=e2c+IgvlT56P3XiVNuC5ETy+wNxnL5HMeqegX27R44KU8ugVdPzxsbVImuDviMMEo XqU8vnlY6UXrWNx4GN4kTB1aMyxpTJBh0mOvDPJZO2vfPxxfSLkbbBvT1JWj/gPq7k PHwUEo4SuqV+GsU51FsiVrHEeELYyH6VCXYFKzUY= Date: Thu, 28 Oct 2021 16:18:09 -0700 From: Paolo Bonzini To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PYZOR_CHECK=1.392, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Oct 2021 23:18:11 -0000 Branch: refs/tags/v6.0.1 Home: https://github.com/qemu/qemu From MAILER-DAEMON Fri Oct 29 00:44:54 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgJl8-0005F9-0o for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 00:44:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgJl4-00059s-PO for qemu-commits@nongnu.org; Fri, 29 Oct 2021 00:44:50 -0400 Received: from out-26.smtp.github.com ([192.30.252.209]:37051 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgJl1-0002tA-Ux for qemu-commits@nongnu.org; Fri, 29 Oct 2021 00:44:50 -0400 Received: from github.com (hubbernetes-node-ce32559.ash1-iad.github.net [10.56.117.66]) by smtp.github.com (Postfix) with ESMTPA id 5A9B55E0697 for ; Thu, 28 Oct 2021 21:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635482686; bh=sbWb9HWXr6Gg54V/UxYgsbRPBXbvT+FtgnUSqTkuQyo=; h=Date:From:To:Subject:From; b=JFwdBpVL7ZLH1ePjn9KxcOYVUJRx+nfYGWRaaJJIsz5Tx5mMuuvWG+d7nbhFzGZ7C lDtE2E7j+i5q1BoneY6wC/qeVduTIdsjcp2tL348nJEvq5dlCqhNIQ3zx7poVnJDsm uJNP5uGakbBrujDVm+rn8khD5IYlTv3RXpZFqnIg= Date: Thu, 28 Oct 2021 21:44:46 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.209; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f44839: Hexagon (target/hexagon) more tcg_constant_* X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 04:44:51 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: f448397a512189e726f5e8026c89ce7fc4392377=0D https://github.com/qemu/qemu/commit/f448397a512189e726f5e8026c89ce7= fc4392377=0D Author: Taylor Simpson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) more tcg_constant_*=0D =0D Change additional tcg_const_tl to tcg_constant_tl=0D =0D Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.=0D= However, it is not constant throughout, so we initialize it with=0D tcg_temp_new and replace the first use with the constant value.=0D =0D Inspired-by: Richard Henderson =0D Inspired-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Taylor Simpson =0D =0D =0D Commit: b9dd6ff91d29b9e38afd7facf1d683f34bd1ec10=0D https://github.com/qemu/qemu/commit/b9dd6ff91d29b9e38afd7facf1d683f= 34bd1ec10=0D Author: Taylor Simpson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/attribs_def.h.inc=0D M target/hexagon/hex_common.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/overflow.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) put writes to USR into temp until commit=0D =0D Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead=0D of hex_gpr[HEX_REG_USR].=0D =0D Then, we need code to mark the instructions that can set implicitly=0D set USR=0D - Macros added to hex_common.py=0D - A_FPOP added in translate.c=0D =0D Test case added in tests/tcg/hexagon/overflow.c=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Taylor Simpson =0D =0D =0D Commit: edf044c558acfcf9ccd45ebacb84542dcca2e813=0D https://github.com/qemu/qemu/commit/edf044c558acfcf9ccd45ebacb84542= dcca2e813=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/attribs_def.h.inc=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/hex_common.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/overflow.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211028' into= staging=0D =0D Followup to replace more tcg_const_* with tcg_constant_tl*=0D Fix bug to delay writes to USR until packet commit=0D =0D # gpg: Signature made Thu 28 Oct 2021 08:59:24 PM PDT=0D # gpg: using RSA key 7B0244FB12DE4422=0D # gpg: Good signature from "Taylor Simpson (Rock on) " [marginal]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE = 4422=0D =0D * remotes/quic/tags/pull-hex-20211028:=0D Hexagon (target/hexagon) put writes to USR into temp until commit=0D Hexagon (target/hexagon) more tcg_constant_*=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/15525d3bc1fa...edf044c558ac= =0D From MAILER-DAEMON Fri Oct 29 11:37:39 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgTwp-0002X2-GO for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 11:37:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgTwk-0002TG-Pz for qemu-commits@nongnu.org; Fri, 29 Oct 2021 11:37:34 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:37735 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgTwj-0003du-1i for qemu-commits@nongnu.org; Fri, 29 Oct 2021 11:37:34 -0400 Received: from github.com (hubbernetes-node-bd9a92d.ac4-iad.github.net [10.52.200.13]) by smtp.github.com (Postfix) with ESMTPA id 7229F520211 for ; Fri, 29 Oct 2021 08:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635521852; bh=tkwIEBD4DGNdjWvgjQbri/MYMoaP0UWjzXWqyyYQx1s=; h=Date:From:To:Subject:From; b=setb0L7s9c1y4lno9YUGda0RCbHua0R7gRCBkVhcJIcKoB/YIDkkO+EZQnMELZGD7 9T/cSyKY95mmcthj30h8BK7Ru/cX0QN5aQZ2BpwOsPRo5brcdr1JF1K6VM0Nq+TL+E Bp4Lb8xwR6ui3dFS/UcVXgl9pKt+T1t72K6Vwq9Y= Date: Fri, 29 Oct 2021 08:37:32 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] f44839: Hexagon (target/hexagon) more tcg_constant_* X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 15:37:35 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: f448397a512189e726f5e8026c89ce7fc4392377=0D https://github.com/qemu/qemu/commit/f448397a512189e726f5e8026c89ce7= fc4392377=0D Author: Taylor Simpson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) more tcg_constant_*=0D =0D Change additional tcg_const_tl to tcg_constant_tl=0D =0D Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.=0D= However, it is not constant throughout, so we initialize it with=0D tcg_temp_new and replace the first use with the constant value.=0D =0D Inspired-by: Richard Henderson =0D Inspired-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Taylor Simpson =0D =0D =0D Commit: b9dd6ff91d29b9e38afd7facf1d683f34bd1ec10=0D https://github.com/qemu/qemu/commit/b9dd6ff91d29b9e38afd7facf1d683f= 34bd1ec10=0D Author: Taylor Simpson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/attribs_def.h.inc=0D M target/hexagon/hex_common.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/overflow.c=0D =0D Log Message:=0D -----------=0D Hexagon (target/hexagon) put writes to USR into temp until commit=0D =0D Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead=0D of hex_gpr[HEX_REG_USR].=0D =0D Then, we need code to mark the instructions that can set implicitly=0D set USR=0D - Macros added to hex_common.py=0D - A_FPOP added in translate.c=0D =0D Test case added in tests/tcg/hexagon/overflow.c=0D =0D Reviewed-by: Richard Henderson =0D Signed-off-by: Taylor Simpson =0D =0D =0D Commit: edf044c558acfcf9ccd45ebacb84542dcca2e813=0D https://github.com/qemu/qemu/commit/edf044c558acfcf9ccd45ebacb84542= dcca2e813=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/hexagon/attribs_def.h.inc=0D M target/hexagon/gen_tcg.h=0D M target/hexagon/gen_tcg_funcs.py=0D M target/hexagon/hex_common.py=0D M target/hexagon/macros.h=0D M target/hexagon/translate.c=0D M tests/tcg/hexagon/Makefile.target=0D A tests/tcg/hexagon/overflow.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211028' into= staging=0D =0D Followup to replace more tcg_const_* with tcg_constant_tl*=0D Fix bug to delay writes to USR until packet commit=0D =0D # gpg: Signature made Thu 28 Oct 2021 08:59:24 PM PDT=0D # gpg: using RSA key 7B0244FB12DE4422=0D # gpg: Good signature from "Taylor Simpson (Rock on) " [marginal]=0D # gpg: WARNING: This key is not certified with sufficiently trusted signa= tures!=0D # gpg: It is not certain that the signature belongs to the owner= .=0D # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE = 4422=0D =0D * remotes/quic/tags/pull-hex-20211028:=0D Hexagon (target/hexagon) put writes to USR into temp until commit=0D Hexagon (target/hexagon) more tcg_constant_*=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/c52d69e7dbaa...edf044c558ac= =0D From MAILER-DAEMON Fri Oct 29 11:45:44 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgU4d-0006wk-5P for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 11:45:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgU4Z-0006vb-FD for qemu-commits@nongnu.org; Fri, 29 Oct 2021 11:45:39 -0400 Received: from out-25.smtp.github.com ([192.30.252.208]:54379 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgU4T-0007AJ-Fd for qemu-commits@nongnu.org; Fri, 29 Oct 2021 11:45:38 -0400 Received: from github.com (hubbernetes-node-37a3abe.ash1-iad.github.net [10.56.112.74]) by smtp.github.com (Postfix) with ESMTPA id 0D843840822 for ; Fri, 29 Oct 2021 08:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635522332; bh=9EmDB6QYpodfgEwWs/08WS9j3j/idIrv2aQ859Mzzlo=; h=Date:From:To:Subject:From; b=z0GVi2toOKoZ3NKQPXBLz44UZ1wbzofdM14UKcN9XNb78XaRdtwCUaK86XNXGF726 Zdzmp7yo8W/wgtj7W+jciedK3WGWDQGLi7ZtG8BduG5Hgp8xjA+3PeUc+711Wat7MQ Rdc2MPkRCV5c7HafkOrUDX3qV2q/u05QBjum9Rjs= Date: Fri, 29 Oct 2021 08:45:32 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.208; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 1c4693: qemu/int128: Add int128_{not, xor} X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 15:45:40 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 1c46937358fc27a9e446d08c877389ee84d6767d=0D https://github.com/qemu/qemu/commit/1c46937358fc27a9e446d08c877389e= e84d6767d=0D Author: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qemu/int128.h=0D =0D Log Message:=0D -----------=0D qemu/int128: Add int128_{not,xor}=0D =0D Addition of not and xor on 128-bit integers.=0D =0D Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Co-authored-by: Fabien Portas =0D Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.= fr>=0D [rth: Split out logical operations.]=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9276a31c3484ff236a958a1e2a38beefb0eb7ebb=0D https://github.com/qemu/qemu/commit/9276a31c3484ff236a958a1e2a38bee= fb0eb7ebb=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: move checks out of divu128/divs128=0D =0D In preparation for changing the divu128/divs128 implementations=0D to allow for quotients larger than 64 bits, move the div-by-zero=0D and overflow checks to the callers.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8ac2d6c526d9ea0c89c8aa7046ca56e1b1b9d130=0D https://github.com/qemu/qemu/commit/8ac2d6c526d9ea0c89c8aa7046ca56e= 1b1b9d130=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/qemu/host-utils.h=0D =0D Log Message:=0D -----------=0D host-utils: move udiv_qrnnd() to host-utils=0D =0D Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,=0D so it can be reused by divu128().=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 40f3e79a862554553811d0681c05e00a4705e91c=0D https://github.com/qemu/qemu/commit/40f3e79a862554553811d0681c05e00= a4705e91c=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: add 128-bit quotient support to divu128/divs128=0D =0D These will be used to implement new decimal floating point=0D instructions from Power ISA 3.1.=0D =0D The remainder is now returned directly by divu128/divs128,=0D freeing up phigh to receive the high 64 bits of the quotient.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 023462978a1fb7b5a3f7ea74236a05d253d0b6e6=0D https://github.com/qemu/qemu/commit/023462978a1fb7b5a3f7ea74236a05d= 253d0b6e6=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D =0D Log Message:=0D -----------=0D host-utils: add unit tests for divu128/divs128=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-5-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b1fde411d0f3dd146ba9864f3a475e7100a14a3b=0D https://github.com/qemu/qemu/commit/b1fde411d0f3dd146ba9864f3a475e7= 100a14a3b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Rename "mask" to "z_mask"=0D =0D Prepare for tracking different masks by renaming this one.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3b3f847d754d7f243b2a04775f37c1b324ca1a12=0D https://github.com/qemu/qemu/commit/3b3f847d754d7f243b2a04775f37c1b= 324ca1a12=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out OptContext=0D =0D Provide what will become a larger context for splitting=0D the very large tcg_optimize function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b10f38339bda94bd960d6936ca6047b34be8eb31=0D https://github.com/qemu/qemu/commit/b10f38339bda94bd960d6936ca6047b= 34be8eb31=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Remove do_default label=0D =0D Break the final cleanup clause out of the main switch=0D statement. When fully folding an opcode to mov/movi,=0D use "continue" to process the next opcode, else break=0D to fall into the final cleanup.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dc84988a5f4147b8c1f90ed4cdcf5c57f06749cd=0D https://github.com/qemu/qemu/commit/dc84988a5f4147b8c1f90ed4cdcf5c5= 7f06749cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change tcg_opt_gen_{mov,movi} interface=0D =0D Adjust the interface to take the OptContext parameter instead=0D of TCGContext or both.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: d0ed5151b11b12e9e2ca3c9adde2fd4444588948=0D https://github.com/qemu/qemu/commit/d0ed5151b11b12e9e2ca3c9adde2fd4= 444588948=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Move prev_mb into OptContext=0D =0D This will expose the variable to subroutines that=0D will be broken out of tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e2577ea24f9974ab0fb2a2b255203bad0c878f91=0D https://github.com/qemu/qemu/commit/e2577ea24f9974ab0fb2a2b255203ba= d0c878f91=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out init_arguments=0D =0D There was no real reason for calls to have separate code here.=0D Unify init for calls vs non-calls using the call path, which=0D handles TCG_CALL_DUMMY_ARG.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8774dded029c96130aacf6e6bb71b70cf271b8df=0D https://github.com/qemu/qemu/commit/8774dded029c96130aacf6e6bb71b70= cf271b8df=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out copy_propagate=0D =0D Continue splitting tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5cf32be7d8f385d1599655fdb9de87996243f33b=0D https://github.com/qemu/qemu/commit/5cf32be7d8f385d1599655fdb9de879= 96243f33b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_call=0D =0D Calls are special in that they have a variable number=0D of arguments, and need to be able to clobber globals.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ec5d4cbeef2749c9137daeac1b7f67735510675b=0D https://github.com/qemu/qemu/commit/ec5d4cbeef2749c9137daeac1b7f677= 35510675b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Drop nb_oargs, nb_iargs locals=0D =0D Rather than try to keep these up-to-date across folding,=0D re-read nb_oargs at the end, after re-reading the opcode.=0D =0D A couple of asserts need dropping, but that will take care=0D of itself as we split the function further.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8d57bf1e82da9c1a71c16b12545a9e8d347690f3=0D https://github.com/qemu/qemu/commit/8d57bf1e82da9c1a71c16b12545a9e8= d347690f3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change fail return for do_constant_folding_cond*=0D =0D Return -1 instead of 2 for failure, so that we can=0D use comparisons against 0 for all cases.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b99d5bf388655b340e93412bf60f8bff90e5870=0D https://github.com/qemu/qemu/commit/6b99d5bf388655b340e93412bf60f8b= ff90e5870=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Return true from tcg_opt_gen_{mov,movi}=0D =0D This will allow callers to tail call to these functions=0D and return true indicating processing complete.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 137f1f4429965d9a702fae9fc89f2604449a24d3=0D https://github.com/qemu/qemu/commit/137f1f4429965d9a702fae9fc89f260= 4449a24d3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out finish_folding=0D =0D Copy z_mask into OptContext, for writeback to the=0D first output within the new function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 404a148d891bf18fc564fa94b00970bbc2c0feec=0D https://github.com/qemu/qemu/commit/404a148d891bf18fc564fa94b00970b= bc2c0feec=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use a boolean to avoid a mass of continues=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3eefdf2b5885dca36eefa200862c661654519162=0D https://github.com/qemu/qemu/commit/3eefdf2b5885dca36eefa200862c661= 654519162=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}=0D =0D This puts the separate mb optimization into the same framework=0D as the others. While fold_qemu_{ld,st} are currently identical,=0D that won't last as more code gets moved.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2f9f08ba43df3ea76124f66ae3fe99a96a0a072f=0D https://github.com/qemu/qemu/commit/2f9f08ba43df3ea76124f66ae3fe99a= 96a0a072f=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_const{1,2}=0D =0D Split out a whole bunch of placeholder functions, which are=0D currently identical. That won't last as more code gets moved.=0D =0D Use CASE_32_64_VEC for some logical operators that previously=0D missed the addition of vectors.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bc47b1aa5be9f90cdbf7fbb01717e4259f717bb9=0D https://github.com/qemu/qemu/commit/bc47b1aa5be9f90cdbf7fbb01717e42= 59f717bb9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 764d2aba08c35f2462371b01c27fb032447afcd8=0D https://github.com/qemu/qemu/commit/764d2aba08c35f2462371b01c27fb03= 2447afcd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 079b08040e0c4eed96b3c19fe37cf17a46294d2b=0D https://github.com/qemu/qemu/commit/079b08040e0c4eed96b3c19fe37cf17= a46294d2b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c63ff55cc5d27b81e6a0924bd1f9abea262069a9=0D https://github.com/qemu/qemu/commit/c63ff55cc5d27b81e6a0924bd1f9abe= a262069a9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b8ac0d1498cf6638e3d50c33e06e5b3b0e7a2d7=0D https://github.com/qemu/qemu/commit/6b8ac0d1498cf6638e3d50c33e06e5b= 3b0e7a2d7=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mulu2_i32=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e3f7dc216744aceb46fb67be1476b518bc48c5ff=0D https://github.com/qemu/qemu/commit/e3f7dc216744aceb46fb67be1476b51= 8bc48c5ff=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_addsub2_i32=0D =0D Add two additional helpers, fold_add2_i32 and fold_sub2_i32=0D which will not be simple wrappers forever.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0c310a3005b59a1e3667654b9c88ddaa32eaf166=0D https://github.com/qemu/qemu/commit/0c310a3005b59a1e3667654b9c88dda= a32eaf166=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_movcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dcd08996c9420a0d22399e0cc53117d2043a02bb=0D https://github.com/qemu/qemu/commit/dcd08996c9420a0d22399e0cc53117d= 2043a02bb=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6617c8821548350a490c14894a4fe0dba07fc73=0D https://github.com/qemu/qemu/commit/b6617c8821548350a490c14894a4fe0= dba07fc73=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract, fold_sextract=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1b1907b8460467743fd23cef918fac9dd7858441=0D https://github.com/qemu/qemu/commit/1b1907b8460467743fd23cef918fac9= dd7858441=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_deposit=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 30dd0bfeb5385342a7f216e661d9b69f6ec7182e=0D https://github.com/qemu/qemu/commit/30dd0bfeb5385342a7f216e661d9b69= f6ec7182e=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_count_zeros=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 09bacdc2632581cafd2878d91d62ba69dc7574f0=0D https://github.com/qemu/qemu/commit/09bacdc2632581cafd2878d91d62ba6= 9dc7574f0=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_bswap=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8cdb3fcb8e69502963ca4127fab656e5ffe2be93=0D https://github.com/qemu/qemu/commit/8cdb3fcb8e69502963ca4127fab656e= 5ffe2be93=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_dup, fold_dup2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2cfac7fa482e015310968ee68b001db94789d190=0D https://github.com/qemu/qemu/commit/2cfac7fa482e015310968ee68b001db= 94789d190=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mov=0D =0D This is the final entry in the main switch that was in a=0D different form. After this, we have the option to convert=0D the switch into a function dispatch table.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: cbe42fb2f22b9adb8b78374f6ff4ca5f58807208=0D https://github.com/qemu/qemu/commit/cbe42fb2f22b9adb8b78374f6ff4ca5= f58807208=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_i=0D =0D Pull the "op r, a, a =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ca7bb049a0250890afd4dd0e66f10b8a4d51715c=0D https://github.com/qemu/qemu/commit/ca7bb049a0250890afd4dd0e66f10b8= a4d51715c=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_x=0D =0D Pull the "op r, a, a =3D> mov r, a" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e8679955ec0791122a6c22d48ae760a215204f6a=0D https://github.com/qemu/qemu/commit/e8679955ec0791122a6c22d48ae760a= 215204f6a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_i=0D =0D Pull the "op r, a, 0 =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 67f84c962166093f26a1f2c66034a44cf294e809=0D https://github.com/qemu/qemu/commit/67f84c962166093f26a1f2c66034a44= cf294e809=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Add type to OptContext=0D =0D Compute the type of the operation early.=0D =0D There are at least 4 places that used a def->flags ladder=0D to determine the type of the operation being optimized.=0D =0D There were two places that assumed !TCG_OPF_64BIT means=0D TCG_TYPE_I32, and so could potentially compute incorrect=0D results for vector operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0e0a32bacb29c4313ef195d2ea18809fd25cf5e2=0D https://github.com/qemu/qemu/commit/0e0a32bacb29c4313ef195d2ea18809= fd25cf5e2=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_to_not=0D =0D Split out the conditional conversion from a more complex logical=0D operation to a simple NOT. Create a couple more helpers to make=0D this easy for the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9caca88a76a6b1e5203dd2470800941c2670a9cd=0D https://github.com/qemu/qemu/commit/9caca88a76a6b1e5203dd2470800941= c2670a9cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_sub_to_neg=0D =0D Even though there is only one user, place this more complex=0D conversion into its own helper.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a63ce0e9cb860439d4277bd6dca696bce1f1bb6b=0D https://github.com/qemu/qemu/commit/a63ce0e9cb860439d4277bd6dca696b= ce1f1bb6b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_x=0D =0D Pull the "op r, a, i =3D> mov r, a" optimization into a function,=0D and use them in the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: da48e2720227473041b7a14dd9f838577d36833a=0D https://github.com/qemu/qemu/commit/da48e2720227473041b7a14dd9f8385= 77d36833a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_ix_to_i=0D =0D Pull the "op r, 0, b =3D> movi r, 0" optimization into a function,=0D and use it in fold_shift.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fae450ba4764dcf8c7a131131639ac0969a8eae8=0D https://github.com/qemu/qemu/commit/fae450ba4764dcf8c7a131131639ac0= 969a8eae8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_masks=0D =0D Move all of the known-zero optimizations into the per-opcode=0D functions. Use fold_masks when there is a possibility of the=0D result being determined, and simply set ctx->z_mask otherwise.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 407112b03d7665a3cb7b3a21105e721a8a0c5fd8=0D https://github.com/qemu/qemu/commit/407112b03d7665a3cb7b3a21105e721= a8a0c5fd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D =0D Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,=0D and muls2_i64.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9531c078ff63783f2a21ba302827123e7b073304=0D https://github.com/qemu/qemu/commit/9531c078ff63783f2a21ba302827123= e7b073304=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D =0D Rename to fold_addsub2.=0D Use Int128 to implement the wider operation.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 7a2f70845255bd6a2ad6399d159c58a7e7b64b51=0D https://github.com/qemu/qemu/commit/7a2f70845255bd6a2ad6399d159c58a= 7e7b64b51=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D =0D Most of these are handled by creating a fold_const2_commutative=0D to handle all of the binary operators. The rest were already=0D handled on a case-by-case basis in the switch, and have their=0D own fold function in which to place the call.=0D =0D We now have only one major switch on TCGOpcode.=0D =0D Introduce NO_DEST and a block comment for swap_commutative in=0D order to make the handling of brcond and movcond opcodes cleaner.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 18cf3d07a2556700895c626754937e90f8e972cf=0D https://github.com/qemu/qemu/commit/18cf3d07a2556700895c626754937e9= 0f8e972cf=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg.c=0D =0D Log Message:=0D -----------=0D tcg: Extend call args using the correct opcodes=0D =0D Pretending that the source is i64 when it is in fact i32 is=0D incorrect; we have type-changing opcodes that must be used.=0D This bug trips up the subsequent change to the optimizer.=0D =0D Fixes: 4f2331e5b67a=0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: faa2e10045ef82f4a1a24a7f69e285736143b469=0D https://github.com/qemu/qemu/commit/faa2e10045ef82f4a1a24a7f69e2857= 36143b469=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D =0D This "garbage" setting pre-dates the addition of the type=0D changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,=0D and INDEX_op_extr{l,h}_i64_i32.=0D =0D So now we have a definitive points at which to adjust z_mask=0D to eliminate such bits from the 32-bit operands.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4e858d96aa3997113014a31afabcf95fb36d2860=0D https://github.com/qemu/qemu/commit/4e858d96aa3997113014a31afabcf95= fb36d2860=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for orc=0D =0D Recognize the constant function for or-complement.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5b5cf47983c37d4c49eb2b8449bc62a7d3d76dbc=0D https://github.com/qemu/qemu/commit/5b5cf47983c37d4c49eb2b8449bc62a= 7d3d76dbc=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for mul=0D =0D Recognize the identity function for low-part multiply.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2f9d9a34221feb80d5b1fc6b584f910f8cee317a=0D https://github.com/qemu/qemu/commit/2f9d9a34221feb80d5b1fc6b584f910= f8cee317a=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for div=0D =0D Recognize the identity function for division.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 267c17e8252fd70b311871f3e936eb7cdf4abb51=0D https://github.com/qemu/qemu/commit/267c17e8252fd70b311871f3e936eb7= cdf4abb51=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for rem=0D =0D Recognize the constant function for remainder.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 57fe5c6df21c05af11435b2ed426a42ee3345298=0D https://github.com/qemu/qemu/commit/57fe5c6df21c05af11435b2ed426a42= ee3345298=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Optimize sign extensions=0D =0D Certain targets, like riscv, produce signed 32-bit results.=0D This can lead to lots of redundant extensions as values are=0D manipulated.=0D =0D Begin by tracking only the obvious sign-extensions, and=0D converting them to simple copies when possible.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3f2b1f8376c11327ca2ea54cdc1085d4d4c1d97c=0D https://github.com/qemu/qemu/commit/3f2b1f8376c11327ca2ea54cdc1085d= 4d4c1d97c=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for logical operations=0D =0D Sign repetitions are perforce all identical, whether they are 1 or 0.=0D Bitwise operations preserve the relative quantity of the repetitions.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 275d7d8e70ef8679e241ce78c83548067f403394=0D https://github.com/qemu/qemu/commit/275d7d8e70ef8679e241ce78c835480= 67f403394=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for setcond=0D =0D The result is either 0 or 1, which means that we have=0D a 2 bit signed result, and thus 62 bits of sign.=0D For clarity, use the smask_from_zmask function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2b9d0c59edec097c72ce9b917d3c08dc5d59cdda=0D https://github.com/qemu/qemu/commit/2b9d0c59edec097c72ce9b917d3c08d= c5d59cdda=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for bit counting=0D =0D The results are generally 6 bit unsigned values, though=0D the count leading and trailing bits may produce any value=0D for a zero input.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 93a967fbb571ae34857c769dbf0bcc08f2286328=0D https://github.com/qemu/qemu/commit/93a967fbb571ae34857c769dbf0bcc0= 8f2286328=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for shifting=0D =0D For constant shifts, we can simply shift the s_mask.=0D =0D For variable shifts, we know that sar does not reduce=0D the s_mask, which helps for sequences like=0D =0D ext32s_i64 t, in=0D sar_i64 t, t, v=0D ext32s_i64 out, t=0D =0D allowing the final extend to be eliminated.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9f660c077b53f58792b6fa6a45b2c3eb1e25b716=0D https://github.com/qemu/qemu/commit/9f660c077b53f58792b6fa6a45b2c3e= b1e25b716=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: fix watchpoint processing in icount mode=0D =0D Watchpoint processing code restores vCPU state twice:=0D in tb_check_watchpoint and in cpu_loop_exit_restore/cpu_restore_state.=0D= Normally it does not affect anything, but in icount mode instruction=0D counter is incremented twice and becomes incorrect.=0D This patch eliminates unneeded CPU state restore.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542168516.2127597.8781375223437124644.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1ab0ba8ab525046f4727c6e1b146e779db8b0489=0D https://github.com/qemu/qemu/commit/1ab0ba8ab525046f4727c6e1b146e77= 9db8b0489=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: remove useless condition in watchpoint check=0D =0D cpu_check_watchpoint function checks cpu->watchpoint_hit at the entry.=0D= But then it also does the same in the middle of the function,=0D while this field can't change.=0D That is why this patch removes this useless condition.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542169094.2127597.8801843697434113110.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: efd629fb21e2ff6a8f62642d9ed7a23dfee4d320=0D https://github.com/qemu/qemu/commit/efd629fb21e2ff6a8f62642d9ed7a23= dfee4d320=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: fix for "after access" watchpoints=0D =0D Watchpoints that should fire after the memory access=0D break an execution of the current block, try to=0D translate current instruction into the separate block,=0D which then causes debug interrupt.=0D But cpu_interrupt can't be called in such block when=0D icount is enabled, because interrupts muse be allowed=0D explicitly.=0D This patch sets CF_LAST_IO flag for retranslated block,=0D allowing interrupt request for the last instruction.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542169727.2127597.8141772572696627329.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a92cecba2791cd408d2bca04ce181dc2abaf9695=0D https://github.com/qemu/qemu/commit/a92cecba2791cd408d2bca04ce181dc= 2abaf9695=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M include/qemu/int128.h=0D M softmmu/physmem.c=0D M target/ppc/int_helper.c=0D M tcg/optimize.c=0D M tcg/tcg.c=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into = staging=0D =0D Improvements to qemu/int128=0D Fixes for 128/64 division.=0D Cleanup tcg/optimize.c=0D Optimize redundant sign extensions=0D =0D # gpg: Signature made Thu 28 Oct 2021 09:06:00 PM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211028: (60 commits)=0D softmmu: fix for "after access" watchpoints=0D softmmu: remove useless condition in watchpoint check=0D softmmu: fix watchpoint processing in icount mode=0D tcg/optimize: Propagate sign info for shifting=0D tcg/optimize: Propagate sign info for bit counting=0D tcg/optimize: Propagate sign info for setcond=0D tcg/optimize: Propagate sign info for logical operations=0D tcg/optimize: Optimize sign extensions=0D tcg/optimize: Use fold_xx_to_i for rem=0D tcg/optimize: Use fold_xi_to_x for div=0D tcg/optimize: Use fold_xi_to_x for mul=0D tcg/optimize: Use fold_xx_to_i for orc=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D tcg: Extend call args using the correct opcodes=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D tcg/optimize: Split out fold_masks=0D tcg/optimize: Split out fold_ix_to_i=0D tcg/optimize: Split out fold_xi_to_x=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/edf044c558ac...a92cecba2791= =0D From MAILER-DAEMON Fri Oct 29 13:58:46 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgW9O-0003bg-Fw for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 13:58:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgW9L-0003Sg-EP for qemu-commits@nongnu.org; Fri, 29 Oct 2021 13:58:43 -0400 Received: from out-22.smtp.github.com ([192.30.252.205]:42103 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgW9G-000085-Re for qemu-commits@nongnu.org; Fri, 29 Oct 2021 13:58:42 -0400 Received: from github.com (hubbernetes-node-fa5363c.ac4-iad.github.net [10.52.205.65]) by smtp.github.com (Postfix) with ESMTPA id 318B9560474 for ; Fri, 29 Oct 2021 10:58:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635530318; bh=4c4wqL7Z1hPMIt7Wx4/LAr5JOk6f/eFJN+7vbc1UtVQ=; h=Date:From:To:Subject:From; b=e0/sIVQPEoErCVqYn4DKbA+zhRFb1c+xstleB/sa0/rscGXH62L5xKY1DzuqsKqXe r0GRrMTmREotTRMi0pU0cWjeNUWANXKi04lGlIzT1+jOAV3VCyNGuVm+zDeRwbxVkA x2/0ic7XYaspUgI7zHZF1ua+18BKZkifXpZc76OI= Date: Fri, 29 Oct 2021 10:58:38 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.205; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 1c4693: qemu/int128: Add int128_{not, xor} X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 17:58:43 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 1c46937358fc27a9e446d08c877389ee84d6767d=0D https://github.com/qemu/qemu/commit/1c46937358fc27a9e446d08c877389e= e84d6767d=0D Author: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/qemu/int128.h=0D =0D Log Message:=0D -----------=0D qemu/int128: Add int128_{not,xor}=0D =0D Addition of not and xor on 128-bit integers.=0D =0D Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot =0D Co-authored-by: Fabien Portas =0D Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.= fr>=0D [rth: Split out logical operations.]=0D Reviewed-by: Richard Henderson =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9276a31c3484ff236a958a1e2a38beefb0eb7ebb=0D https://github.com/qemu/qemu/commit/9276a31c3484ff236a958a1e2a38bee= fb0eb7ebb=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: move checks out of divu128/divs128=0D =0D In preparation for changing the divu128/divs128 implementations=0D to allow for quotients larger than 64 bits, move the div-by-zero=0D and overflow checks to the callers.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8ac2d6c526d9ea0c89c8aa7046ca56e1b1b9d130=0D https://github.com/qemu/qemu/commit/8ac2d6c526d9ea0c89c8aa7046ca56e= 1b1b9d130=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/qemu/host-utils.h=0D =0D Log Message:=0D -----------=0D host-utils: move udiv_qrnnd() to host-utils=0D =0D Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils,=0D so it can be reused by divu128().=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 40f3e79a862554553811d0681c05e00a4705e91c=0D https://github.com/qemu/qemu/commit/40f3e79a862554553811d0681c05e00= a4705e91c=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M target/ppc/int_helper.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D host-utils: add 128-bit quotient support to divu128/divs128=0D =0D These will be used to implement new decimal floating point=0D instructions from Power ISA 3.1.=0D =0D The remainder is now returned directly by divu128/divs128,=0D freeing up phigh to receive the high 64 bits of the quotient.=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 023462978a1fb7b5a3f7ea74236a05d253d0b6e6=0D https://github.com/qemu/qemu/commit/023462978a1fb7b5a3f7ea74236a05d= 253d0b6e6=0D Author: Luis Pires =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D =0D Log Message:=0D -----------=0D host-utils: add unit tests for divu128/divs128=0D =0D Signed-off-by: Luis Pires =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211025191154.350831-5-luis.pires@eldorado.org.br>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b1fde411d0f3dd146ba9864f3a475e7100a14a3b=0D https://github.com/qemu/qemu/commit/b1fde411d0f3dd146ba9864f3a475e7= 100a14a3b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Rename "mask" to "z_mask"=0D =0D Prepare for tracking different masks by renaming this one.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3b3f847d754d7f243b2a04775f37c1b324ca1a12=0D https://github.com/qemu/qemu/commit/3b3f847d754d7f243b2a04775f37c1b= 324ca1a12=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out OptContext=0D =0D Provide what will become a larger context for splitting=0D the very large tcg_optimize function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b10f38339bda94bd960d6936ca6047b34be8eb31=0D https://github.com/qemu/qemu/commit/b10f38339bda94bd960d6936ca6047b= 34be8eb31=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Remove do_default label=0D =0D Break the final cleanup clause out of the main switch=0D statement. When fully folding an opcode to mov/movi,=0D use "continue" to process the next opcode, else break=0D to fall into the final cleanup.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dc84988a5f4147b8c1f90ed4cdcf5c57f06749cd=0D https://github.com/qemu/qemu/commit/dc84988a5f4147b8c1f90ed4cdcf5c5= 7f06749cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change tcg_opt_gen_{mov,movi} interface=0D =0D Adjust the interface to take the OptContext parameter instead=0D of TCGContext or both.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: d0ed5151b11b12e9e2ca3c9adde2fd4444588948=0D https://github.com/qemu/qemu/commit/d0ed5151b11b12e9e2ca3c9adde2fd4= 444588948=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Move prev_mb into OptContext=0D =0D This will expose the variable to subroutines that=0D will be broken out of tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e2577ea24f9974ab0fb2a2b255203bad0c878f91=0D https://github.com/qemu/qemu/commit/e2577ea24f9974ab0fb2a2b255203ba= d0c878f91=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out init_arguments=0D =0D There was no real reason for calls to have separate code here.=0D Unify init for calls vs non-calls using the call path, which=0D handles TCG_CALL_DUMMY_ARG.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8774dded029c96130aacf6e6bb71b70cf271b8df=0D https://github.com/qemu/qemu/commit/8774dded029c96130aacf6e6bb71b70= cf271b8df=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out copy_propagate=0D =0D Continue splitting tcg_optimize.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5cf32be7d8f385d1599655fdb9de87996243f33b=0D https://github.com/qemu/qemu/commit/5cf32be7d8f385d1599655fdb9de879= 96243f33b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_call=0D =0D Calls are special in that they have a variable number=0D of arguments, and need to be able to clobber globals.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ec5d4cbeef2749c9137daeac1b7f67735510675b=0D https://github.com/qemu/qemu/commit/ec5d4cbeef2749c9137daeac1b7f677= 35510675b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Drop nb_oargs, nb_iargs locals=0D =0D Rather than try to keep these up-to-date across folding,=0D re-read nb_oargs at the end, after re-reading the opcode.=0D =0D A couple of asserts need dropping, but that will take care=0D of itself as we split the function further.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8d57bf1e82da9c1a71c16b12545a9e8d347690f3=0D https://github.com/qemu/qemu/commit/8d57bf1e82da9c1a71c16b12545a9e8= d347690f3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Change fail return for do_constant_folding_cond*=0D =0D Return -1 instead of 2 for failure, so that we can=0D use comparisons against 0 for all cases.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b99d5bf388655b340e93412bf60f8bff90e5870=0D https://github.com/qemu/qemu/commit/6b99d5bf388655b340e93412bf60f8b= ff90e5870=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Return true from tcg_opt_gen_{mov,movi}=0D =0D This will allow callers to tail call to these functions=0D and return true indicating processing complete.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 137f1f4429965d9a702fae9fc89f2604449a24d3=0D https://github.com/qemu/qemu/commit/137f1f4429965d9a702fae9fc89f260= 4449a24d3=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out finish_folding=0D =0D Copy z_mask into OptContext, for writeback to the=0D first output within the new function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 404a148d891bf18fc564fa94b00970bbc2c0feec=0D https://github.com/qemu/qemu/commit/404a148d891bf18fc564fa94b00970b= bc2c0feec=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use a boolean to avoid a mass of continues=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3eefdf2b5885dca36eefa200862c661654519162=0D https://github.com/qemu/qemu/commit/3eefdf2b5885dca36eefa200862c661= 654519162=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mb, fold_qemu_{ld,st}=0D =0D This puts the separate mb optimization into the same framework=0D as the others. While fold_qemu_{ld,st} are currently identical,=0D that won't last as more code gets moved.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2f9f08ba43df3ea76124f66ae3fe99a96a0a072f=0D https://github.com/qemu/qemu/commit/2f9f08ba43df3ea76124f66ae3fe99a= 96a0a072f=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_const{1,2}=0D =0D Split out a whole bunch of placeholder functions, which are=0D currently identical. That won't last as more code gets moved.=0D =0D Use CASE_32_64_VEC for some logical operators that previously=0D missed the addition of vectors.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: bc47b1aa5be9f90cdbf7fbb01717e4259f717bb9=0D https://github.com/qemu/qemu/commit/bc47b1aa5be9f90cdbf7fbb01717e42= 59f717bb9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 764d2aba08c35f2462371b01c27fb032447afcd8=0D https://github.com/qemu/qemu/commit/764d2aba08c35f2462371b01c27fb03= 2447afcd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond2=0D =0D Reduce some code duplication by folding the NE and EQ cases.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 079b08040e0c4eed96b3c19fe37cf17a46294d2b=0D https://github.com/qemu/qemu/commit/079b08040e0c4eed96b3c19fe37cf17= a46294d2b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_brcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: c63ff55cc5d27b81e6a0924bd1f9abea262069a9=0D https://github.com/qemu/qemu/commit/c63ff55cc5d27b81e6a0924bd1f9abe= a262069a9=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_setcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 6b8ac0d1498cf6638e3d50c33e06e5b3b0e7a2d7=0D https://github.com/qemu/qemu/commit/6b8ac0d1498cf6638e3d50c33e06e5b= 3b0e7a2d7=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mulu2_i32=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e3f7dc216744aceb46fb67be1476b518bc48c5ff=0D https://github.com/qemu/qemu/commit/e3f7dc216744aceb46fb67be1476b51= 8bc48c5ff=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_addsub2_i32=0D =0D Add two additional helpers, fold_add2_i32 and fold_sub2_i32=0D which will not be simple wrappers forever.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0c310a3005b59a1e3667654b9c88ddaa32eaf166=0D https://github.com/qemu/qemu/commit/0c310a3005b59a1e3667654b9c88dda= a32eaf166=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_movcond=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: dcd08996c9420a0d22399e0cc53117d2043a02bb=0D https://github.com/qemu/qemu/commit/dcd08996c9420a0d22399e0cc53117d= 2043a02bb=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: b6617c8821548350a490c14894a4fe0dba07fc73=0D https://github.com/qemu/qemu/commit/b6617c8821548350a490c14894a4fe0= dba07fc73=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_extract, fold_sextract=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1b1907b8460467743fd23cef918fac9dd7858441=0D https://github.com/qemu/qemu/commit/1b1907b8460467743fd23cef918fac9= dd7858441=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_deposit=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 30dd0bfeb5385342a7f216e661d9b69f6ec7182e=0D https://github.com/qemu/qemu/commit/30dd0bfeb5385342a7f216e661d9b69= f6ec7182e=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_count_zeros=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 09bacdc2632581cafd2878d91d62ba69dc7574f0=0D https://github.com/qemu/qemu/commit/09bacdc2632581cafd2878d91d62ba6= 9dc7574f0=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_bswap=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 8cdb3fcb8e69502963ca4127fab656e5ffe2be93=0D https://github.com/qemu/qemu/commit/8cdb3fcb8e69502963ca4127fab656e= 5ffe2be93=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_dup, fold_dup2=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2cfac7fa482e015310968ee68b001db94789d190=0D https://github.com/qemu/qemu/commit/2cfac7fa482e015310968ee68b001db= 94789d190=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_mov=0D =0D This is the final entry in the main switch that was in a=0D different form. After this, we have the option to convert=0D the switch into a function dispatch table.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: cbe42fb2f22b9adb8b78374f6ff4ca5f58807208=0D https://github.com/qemu/qemu/commit/cbe42fb2f22b9adb8b78374f6ff4ca5= f58807208=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_i=0D =0D Pull the "op r, a, a =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: ca7bb049a0250890afd4dd0e66f10b8a4d51715c=0D https://github.com/qemu/qemu/commit/ca7bb049a0250890afd4dd0e66f10b8= a4d51715c=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xx_to_x=0D =0D Pull the "op r, a, a =3D> mov r, a" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: e8679955ec0791122a6c22d48ae760a215204f6a=0D https://github.com/qemu/qemu/commit/e8679955ec0791122a6c22d48ae760a= 215204f6a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_i=0D =0D Pull the "op r, a, 0 =3D> movi r, 0" optimization into a function,=0D and use it in the outer opcode fold functions.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 67f84c962166093f26a1f2c66034a44cf294e809=0D https://github.com/qemu/qemu/commit/67f84c962166093f26a1f2c66034a44= cf294e809=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Add type to OptContext=0D =0D Compute the type of the operation early.=0D =0D There are at least 4 places that used a def->flags ladder=0D to determine the type of the operation being optimized.=0D =0D There were two places that assumed !TCG_OPF_64BIT means=0D TCG_TYPE_I32, and so could potentially compute incorrect=0D results for vector operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 0e0a32bacb29c4313ef195d2ea18809fd25cf5e2=0D https://github.com/qemu/qemu/commit/0e0a32bacb29c4313ef195d2ea18809= fd25cf5e2=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_to_not=0D =0D Split out the conditional conversion from a more complex logical=0D operation to a simple NOT. Create a couple more helpers to make=0D this easy for the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9caca88a76a6b1e5203dd2470800941c2670a9cd=0D https://github.com/qemu/qemu/commit/9caca88a76a6b1e5203dd2470800941= c2670a9cd=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_sub_to_neg=0D =0D Even though there is only one user, place this more complex=0D conversion into its own helper.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a63ce0e9cb860439d4277bd6dca696bce1f1bb6b=0D https://github.com/qemu/qemu/commit/a63ce0e9cb860439d4277bd6dca696b= ce1f1bb6b=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_xi_to_x=0D =0D Pull the "op r, a, i =3D> mov r, a" optimization into a function,=0D and use them in the outer-most logical operations.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: da48e2720227473041b7a14dd9f838577d36833a=0D https://github.com/qemu/qemu/commit/da48e2720227473041b7a14dd9f8385= 77d36833a=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_ix_to_i=0D =0D Pull the "op r, 0, b =3D> movi r, 0" optimization into a function,=0D and use it in fold_shift.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: fae450ba4764dcf8c7a131131639ac0969a8eae8=0D https://github.com/qemu/qemu/commit/fae450ba4764dcf8c7a131131639ac0= 969a8eae8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Split out fold_masks=0D =0D Move all of the known-zero optimizations into the per-opcode=0D functions. Use fold_masks when there is a possibility of the=0D result being determined, and simply set ctx->z_mask otherwise.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 407112b03d7665a3cb7b3a21105e721a8a0c5fd8=0D https://github.com/qemu/qemu/commit/407112b03d7665a3cb7b3a21105e721= a8a0c5fd8=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D =0D Rename to fold_multiply2, and handle muls2_i32, mulu2_i64,=0D and muls2_i64.=0D =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9531c078ff63783f2a21ba302827123e7b073304=0D https://github.com/qemu/qemu/commit/9531c078ff63783f2a21ba302827123= e7b073304=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D =0D Rename to fold_addsub2.=0D Use Int128 to implement the wider operation.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 7a2f70845255bd6a2ad6399d159c58a7e7b64b51=0D https://github.com/qemu/qemu/commit/7a2f70845255bd6a2ad6399d159c58a= 7e7b64b51=0D Author: Richard Henderson =0D Date: 2021-10-27 (Wed, 27 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D =0D Most of these are handled by creating a fold_const2_commutative=0D to handle all of the binary operators. The rest were already=0D handled on a case-by-case basis in the switch, and have their=0D own fold function in which to place the call.=0D =0D We now have only one major switch on TCGOpcode.=0D =0D Introduce NO_DEST and a block comment for swap_commutative in=0D order to make the handling of brcond and movcond opcodes cleaner.=0D =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 18cf3d07a2556700895c626754937e90f8e972cf=0D https://github.com/qemu/qemu/commit/18cf3d07a2556700895c626754937e9= 0f8e972cf=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/tcg.c=0D =0D Log Message:=0D -----------=0D tcg: Extend call args using the correct opcodes=0D =0D Pretending that the source is i64 when it is in fact i32 is=0D incorrect; we have type-changing opcodes that must be used.=0D This bug trips up the subsequent change to the optimizer.=0D =0D Fixes: 4f2331e5b67a=0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: faa2e10045ef82f4a1a24a7f69e285736143b469=0D https://github.com/qemu/qemu/commit/faa2e10045ef82f4a1a24a7f69e2857= 36143b469=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D =0D This "garbage" setting pre-dates the addition of the type=0D changing opcodes INDEX_op_ext_i32_i64, INDEX_op_extu_i32_i64,=0D and INDEX_op_extr{l,h}_i64_i32.=0D =0D So now we have a definitive points at which to adjust z_mask=0D to eliminate such bits from the 32-bit operands.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 4e858d96aa3997113014a31afabcf95fb36d2860=0D https://github.com/qemu/qemu/commit/4e858d96aa3997113014a31afabcf95= fb36d2860=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for orc=0D =0D Recognize the constant function for or-complement.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 5b5cf47983c37d4c49eb2b8449bc62a7d3d76dbc=0D https://github.com/qemu/qemu/commit/5b5cf47983c37d4c49eb2b8449bc62a= 7d3d76dbc=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for mul=0D =0D Recognize the identity function for low-part multiply.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2f9d9a34221feb80d5b1fc6b584f910f8cee317a=0D https://github.com/qemu/qemu/commit/2f9d9a34221feb80d5b1fc6b584f910= f8cee317a=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xi_to_x for div=0D =0D Recognize the identity function for division.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 267c17e8252fd70b311871f3e936eb7cdf4abb51=0D https://github.com/qemu/qemu/commit/267c17e8252fd70b311871f3e936eb7= cdf4abb51=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Use fold_xx_to_i for rem=0D =0D Recognize the constant function for remainder.=0D =0D Suggested-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 57fe5c6df21c05af11435b2ed426a42ee3345298=0D https://github.com/qemu/qemu/commit/57fe5c6df21c05af11435b2ed426a42= ee3345298=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Optimize sign extensions=0D =0D Certain targets, like riscv, produce signed 32-bit results.=0D This can lead to lots of redundant extensions as values are=0D manipulated.=0D =0D Begin by tracking only the obvious sign-extensions, and=0D converting them to simple copies when possible.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 3f2b1f8376c11327ca2ea54cdc1085d4d4c1d97c=0D https://github.com/qemu/qemu/commit/3f2b1f8376c11327ca2ea54cdc1085d= 4d4c1d97c=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for logical operations=0D =0D Sign repetitions are perforce all identical, whether they are 1 or 0.=0D Bitwise operations preserve the relative quantity of the repetitions.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 275d7d8e70ef8679e241ce78c83548067f403394=0D https://github.com/qemu/qemu/commit/275d7d8e70ef8679e241ce78c835480= 67f403394=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for setcond=0D =0D The result is either 0 or 1, which means that we have=0D a 2 bit signed result, and thus 62 bits of sign.=0D For clarity, use the smask_from_zmask function.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 2b9d0c59edec097c72ce9b917d3c08dc5d59cdda=0D https://github.com/qemu/qemu/commit/2b9d0c59edec097c72ce9b917d3c08d= c5d59cdda=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for bit counting=0D =0D The results are generally 6 bit unsigned values, though=0D the count leading and trailing bits may produce any value=0D for a zero input.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 93a967fbb571ae34857c769dbf0bcc08f2286328=0D https://github.com/qemu/qemu/commit/93a967fbb571ae34857c769dbf0bcc0= 8f2286328=0D Author: Richard Henderson =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M tcg/optimize.c=0D =0D Log Message:=0D -----------=0D tcg/optimize: Propagate sign info for shifting=0D =0D For constant shifts, we can simply shift the s_mask.=0D =0D For variable shifts, we know that sar does not reduce=0D the s_mask, which helps for sequences like=0D =0D ext32s_i64 t, in=0D sar_i64 t, t, v=0D ext32s_i64 out, t=0D =0D allowing the final extend to be eliminated.=0D =0D Reviewed-by: Alex Benn=C3=A9e =0D Reviewed-by: Luis Pires =0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 9f660c077b53f58792b6fa6a45b2c3eb1e25b716=0D https://github.com/qemu/qemu/commit/9f660c077b53f58792b6fa6a45b2c3e= b1e25b716=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: fix watchpoint processing in icount mode=0D =0D Watchpoint processing code restores vCPU state twice:=0D in tb_check_watchpoint and in cpu_loop_exit_restore/cpu_restore_state.=0D= Normally it does not affect anything, but in icount mode instruction=0D counter is incremented twice and becomes incorrect.=0D This patch eliminates unneeded CPU state restore.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: David Hildenbrand =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542168516.2127597.8781375223437124644.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: 1ab0ba8ab525046f4727c6e1b146e779db8b0489=0D https://github.com/qemu/qemu/commit/1ab0ba8ab525046f4727c6e1b146e77= 9db8b0489=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: remove useless condition in watchpoint check=0D =0D cpu_check_watchpoint function checks cpu->watchpoint_hit at the entry.=0D= But then it also does the same in the middle of the function,=0D while this field can't change.=0D That is why this patch removes this useless condition.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542169094.2127597.8801843697434113110.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: efd629fb21e2ff6a8f62642d9ed7a23dfee4d320=0D https://github.com/qemu/qemu/commit/efd629fb21e2ff6a8f62642d9ed7a23= dfee4d320=0D Author: Pavel Dovgalyuk =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M softmmu/physmem.c=0D =0D Log Message:=0D -----------=0D softmmu: fix for "after access" watchpoints=0D =0D Watchpoints that should fire after the memory access=0D break an execution of the current block, try to=0D translate current instruction into the separate block,=0D which then causes debug interrupt.=0D But cpu_interrupt can't be called in such block when=0D icount is enabled, because interrupts muse be allowed=0D explicitly.=0D This patch sets CF_LAST_IO flag for retranslated block,=0D allowing interrupt request for the last instruction.=0D =0D Signed-off-by: Pavel Dovgalyuk =0D Reviewed-by: Richard Henderson =0D Message-Id: <163542169727.2127597.8141772572696627329.stgit@pasha-ThinkPa= d-X280>=0D Signed-off-by: Richard Henderson =0D =0D =0D Commit: a92cecba2791cd408d2bca04ce181dc2abaf9695=0D https://github.com/qemu/qemu/commit/a92cecba2791cd408d2bca04ce181dc= 2abaf9695=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/fpu/softfloat-macros.h=0D M include/hw/clock.h=0D M include/qemu/host-utils.h=0D M include/qemu/int128.h=0D M softmmu/physmem.c=0D M target/ppc/int_helper.c=0D M tcg/optimize.c=0D M tcg/tcg.c=0D M tests/unit/meson.build=0D A tests/unit/test-div128.c=0D M util/host-utils.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211028' into = staging=0D =0D Improvements to qemu/int128=0D Fixes for 128/64 division.=0D Cleanup tcg/optimize.c=0D Optimize redundant sign extensions=0D =0D # gpg: Signature made Thu 28 Oct 2021 09:06:00 PM PDT=0D # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E2= 15F=0D # gpg: issuer "richard.henderson@linaro.org"=0D # gpg: Good signature from "Richard Henderson " [ultimate]=0D =0D * remotes/rth/tags/pull-tcg-20211028: (60 commits)=0D softmmu: fix for "after access" watchpoints=0D softmmu: remove useless condition in watchpoint check=0D softmmu: fix watchpoint processing in icount mode=0D tcg/optimize: Propagate sign info for shifting=0D tcg/optimize: Propagate sign info for bit counting=0D tcg/optimize: Propagate sign info for setcond=0D tcg/optimize: Propagate sign info for logical operations=0D tcg/optimize: Optimize sign extensions=0D tcg/optimize: Use fold_xx_to_i for rem=0D tcg/optimize: Use fold_xi_to_x for div=0D tcg/optimize: Use fold_xi_to_x for mul=0D tcg/optimize: Use fold_xx_to_i for orc=0D tcg/optimize: Stop forcing z_mask to "garbage" for 32-bit values=0D tcg: Extend call args using the correct opcodes=0D tcg/optimize: Sink commutative operand swapping into fold functions=0D tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops=0D tcg/optimize: Expand fold_mulu2_i32 to all 4-arg multiplies=0D tcg/optimize: Split out fold_masks=0D tcg/optimize: Split out fold_ix_to_i=0D tcg/optimize: Split out fold_xi_to_x=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/edf044c558ac...a92cecba2791= =0D From MAILER-DAEMON Fri Oct 29 14:04:52 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgWFI-0001KX-IK for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 14:04:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgWFE-0001Fa-81 for qemu-commits@nongnu.org; Fri, 29 Oct 2021 14:04:50 -0400 Received: from out-28.smtp.github.com ([192.30.252.211]:33907) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgWFA-00011o-0B for qemu-commits@nongnu.org; Fri, 29 Oct 2021 14:04:47 -0400 Received: from github.com (hubbernetes-node-fb13474.ash1-iad.github.net [10.56.112.53]) by smtp.github.com (Postfix) with ESMTPA id 3B81B9004D9 for ; Fri, 29 Oct 2021 11:04:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635530683; bh=C3YSE/6Pg5hfCkQiw62O7a/OjJqjqlQLWCKbN2hvdxw=; h=Date:From:To:Subject:From; b=V5kHZJuql6Om7w1SoOebSSm6QXiR1ajFGx3cMSPg4OmnzhOQqQsZHsUSDWmMaFNyJ hCIek/moekBLaQsAEpQyVddTJuMbnk07TUmsh7LLWPA6jWBpKwgji5bhNQ/Q3yeccQ wnSI3+8JeMbPmCG/bE8yQdLg6ntyLcKAAHPIxdg8= Date: Fri, 29 Oct 2021 11:04:43 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.211; envelope-from=noreply@github.com; helo=out-28.smtp.github.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 9925c8: hw/riscv: virt: Don't use a macro for the PLIC con... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 18:04:50 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: 9925c8bb81d34339ea0433192fdb1d58c12b8edb=0D https://github.com/qemu/qemu/commit/9925c8bb81d34339ea0433192fdb1d5= 8c12b8edb=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D M include/hw/riscv/virt.h=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Don't use a macro for the PLIC configuration=0D =0D Using a macro for the PLIC configuration doesn't make the code any=0D easier to read. Instead it makes it harder to figure out what is going=0D= on, so let's remove it.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: bf357e1d72cd8b7b590518dacdf4b65beb2c61e2=0D https://github.com/qemu/qemu/commit/bf357e1d72cd8b7b590518dacdf4b65= beb2c61e2=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/boot.c=0D M include/hw/riscv/boot.h=0D =0D Log Message:=0D -----------=0D hw/riscv: boot: Add a PLIC config string function=0D =0D Add a generic function that can create the PLIC strings.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 4e8fb53c0b58cbb18cd243a5b067e4f26db83f77=0D https://github.com/qemu/qemu/commit/4e8fb53c0b58cbb18cd243a5b067e4f= 26db83f77=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_u.c=0D M include/hw/riscv/sifive_u.h=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_u: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 8486eb8cdcd336de8ae52d95da45af97f54db63e=0D https://github.com/qemu/qemu/commit/8486eb8cdcd336de8ae52d95da45af9= 7f54db63e=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/microchip_pfsoc.c=0D M include/hw/riscv/microchip_pfsoc.h=0D =0D Log Message:=0D -----------=0D hw/riscv: microchip_pfsoc: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713=0D https://github.com/qemu/qemu/commit/7d10ff8a4de7a9bff1e7b25011f5eb4= 3f24a6713=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662=0D https://github.com/qemu/qemu/commit/9b144ed444f1fb3149d9ec17f0c4a64= d4fd7d662=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Fixup the PLIC context addresses=0D =0D Fixup the PLIC context address to correctly support the threshold and=0D claim register.=0D =0D Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")=0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 53dcea58b8ab150ab034f9c19074c5f74d6ca41e=0D https://github.com/qemu/qemu/commit/53dcea58b8ab150ab034f9c19074c5f= 74d6ca41e=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add J-extension into RISC-V=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 138b5c5f8f5abec5acc18d2a256f0a082dc51ef5=0D https://github.com/qemu/qemu/commit/138b5c5f8f5abec5acc18d2a256f0a0= 82dc51ef5=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add CSR defines for RISC-V PM extension=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 4bbe8033fcd08769cef49f5149c5c165594ae10a=0D https://github.com/qemu/qemu/commit/4bbe8033fcd08769cef49f5149c5c16= 5594ae10a=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/csr.c=0D =0D Log Message:=0D -----------=0D target/riscv: Support CSRs required for RISC-V PM extension except for = the h-mode=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b1c279e135e0da33a06544919c2cb89b6988e874=0D https://github.com/qemu/qemu/commit/b1c279e135e0da33a06544919c2cb89= b6988e874=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/machine.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add J extension state description=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: bd5594ca2808b3e353d350a08d72f36cb8e01048=0D https://github.com/qemu/qemu/commit/bd5594ca2808b3e353d350a08d72f36= cb8e01048=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Print new PM CSRs in QEMU logs=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: c655df7fe00669ac9ac3b0614be6e4a6f5782737=0D https://github.com/qemu/qemu/commit/c655df7fe00669ac9ac3b0614be6e4a= 6f5782737=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rva.c.inc=0D M target/riscv/insn_trans/trans_rvd.c.inc=0D M target/riscv/insn_trans/trans_rvf.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of= instructions=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0774a7a1ff24d6b8c2f90b9c341f057914b18134=0D https://github.com/qemu/qemu/commit/0774a7a1ff24d6b8c2f90b9c341f057= 914b18134=0D Author: Anatoly Parshintsev =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Implement address masking functions required for RISC-V P= ointer Masking extension=0D =0D Signed-off-by: Anatoly Parshintsev =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0ee9a4e57e1cee4577cab22f6ced6c0c34fb2d94=0D https://github.com/qemu/qemu/commit/0ee9a4e57e1cee4577cab22f6ced6c0= c34fb2d94=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Allow experimental J-ext to be turned on=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 487a99551ae903fc83a878d4cbc6d853e17ad252=0D https://github.com/qemu/qemu/commit/487a99551ae903fc83a878d4cbc6d85= 3e17ad252=0D Author: Jose Martins =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: fix VS interrupts forwarding to HS=0D =0D VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when=0D not delegated in hideleg (which was not being taken into account). This=0D= was mainly because hs level sie was not always considered enabled when=0D= it should. The spec states that "Interrupts for higher-privilege modes,=0D= y>x, are always globally enabled regardless of the setting of the global=0D= yIE bit for the higher-privilege mode." and also "For purposes of=0D interrupt global enables, HS-mode is considered more privileged than=0D VS-mode, and VS-mode is considered more privileged than VU-mode". Also,=0D= vs-level interrupts were not being taken into account unless V=3D1, but=0D= should be unless delegated.=0D =0D Finally, there is no need for a special case for to handle vs interrupts=0D= as the current privilege level, the state of the global ie and of the=0D delegation registers should be enough to route all interrupts to the=0D appropriate privilege level in riscv_cpu_do_interrupt.=0D =0D Signed-off-by: Jose Martins =0D Reviewed-by: Alistair Francis =0D Message-id: 20211026145126.11025-2-josemartins90@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 50d160876414e91e51ac718ac6edea6dbadf4694=0D https://github.com/qemu/qemu/commit/50d160876414e91e51ac718ac6edea6= dbadf4694=0D Author: Jose Martins =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: remove force HS exception=0D =0D There is no need to "force an hs exception" as the current privilege=0D level, the state of the global ie and of the delegation registers should=0D= be enough to route the interrupt to the appropriate privilege level in=0D= riscv_cpu_do_interrupt. The is true for both asynchronous and=0D synchronous exceptions, specifically, guest page faults which must be=0D hardwired to zero hedeleg. As such the hs_force_except mechanism can be=0D= removed.=0D =0D Signed-off-by: Jose Martins =0D Reviewed-by: Alistair Francis =0D Message-id: 20211026145126.11025-3-josemartins90@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92=0D https://github.com/qemu/qemu/commit/0e9030376e1a8eb6d15cb5e69dffa09= a6ff16b92=0D Author: Chih-Min Chao =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M fpu/softfloat-parts.c.inc=0D M fpu/softfloat.c=0D M include/fpu/softfloat.h=0D =0D Log Message:=0D -----------=0D softfloat: add APIs to handle alternative sNaN propagation for fmax/fmi= n=0D =0D For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,=0D =0D The original logic:=0D Return NaN and set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNan= .=0D =0D The alternative path:=0D Set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNaN.=0D Return NaN only if ft1 =3D=3D NaN && ft2 =3D=3D NaN.=0D =0D The IEEE 754 spec allows both implementation and some architecture such=0D= as riscv choose different defintions in two spec versions.=0D (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to=0D alternative)=0D =0D Signed-off-by: Chih-Min Chao =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 15161e425ee1bb1180f9cec574cda44fb10c0931=0D https://github.com/qemu/qemu/commit/15161e425ee1bb1180f9cec574cda44= fb10c0931=0D Author: Chih-Min Chao =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/fpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: change the api for RVF/RVD fmin/fmax=0D =0D The sNaN propagation behavior has been changed since cd20cee7 in=0D https://github.com/riscv/riscv-isa-manual.=0D =0D In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with=0D= IEEE 754-2008 minNum and maxNum operations.=0D =0D In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to=0D implement IEEE 754-2019 minimumNumber and maximumNumber operations.=0D =0D Therefore, to prevent the risk of having too many version variables.=0D Instead of introducing an extra *fext_ver* variable, we tie RVF version=0D= to Priv version. Though it's not completely accurate but is close enough.= =0D =0D Signed-off-by: Chih-Min Chao =0D Signed-off-by: Frank Chang =0D Acked-by: Alistair Francis =0D Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 6450ce5634a57e57ee8bb790c080fc7636678f3d=0D https://github.com/qemu/qemu/commit/6450ce5634a57e57ee8bb790c080fc7= 636678f3d=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M fpu/softfloat-parts.c.inc=0D M fpu/softfloat.c=0D M hw/riscv/boot.c=0D M hw/riscv/microchip_pfsoc.c=0D M hw/riscv/opentitan.c=0D M hw/riscv/sifive_u.c=0D M hw/riscv/virt.c=0D M include/fpu/softfloat.h=0D M include/hw/riscv/boot.h=0D M include/hw/riscv/microchip_pfsoc.h=0D M include/hw/riscv/sifive_u.h=0D M include/hw/riscv/virt.h=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/fpu_helper.c=0D M target/riscv/insn_trans/trans_rva.c.inc=0D M target/riscv/insn_trans/trans_rvd.c.inc=0D M target/riscv/insn_trans/trans_rvf.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/machine.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211029-1' into staging=0D =0D Fifth RISC-V PR for QEMU 6.2=0D =0D - Use a shared PLIC config helper function=0D - Fixup the OpenTitan PLIC configuration=0D - Add support for the experimental J extension=0D - Update the fmin/fmax handling=0D - Fixup VS interrupt forwarding=0D =0D # gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211029-1:=0D target/riscv: change the api for RVF/RVD fmin/fmax=0D softfloat: add APIs to handle alternative sNaN propagation for fmax/fmi= n=0D target/riscv: remove force HS exception=0D target/riscv: fix VS interrupts forwarding to HS=0D target/riscv: Allow experimental J-ext to be turned on=0D target/riscv: Implement address masking functions required for RISC-V P= ointer Masking extension=0D target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of= instructions=0D target/riscv: Print new PM CSRs in QEMU logs=0D target/riscv: Add J extension state description=0D target/riscv: Support CSRs required for RISC-V PM extension except for = the h-mode=0D target/riscv: Add CSR defines for RISC-V PM extension=0D target/riscv: Add J-extension into RISC-V=0D hw/riscv: opentitan: Fixup the PLIC context addresses=0D hw/riscv: virt: Use the PLIC config helper function=0D hw/riscv: microchip_pfsoc: Use the PLIC config helper function=0D hw/riscv: sifive_u: Use the PLIC config helper function=0D hw/riscv: boot: Add a PLIC config string function=0D hw/riscv: virt: Don't use a macro for the PLIC configuration=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/a92cecba2791...6450ce5634a5= =0D From MAILER-DAEMON Fri Oct 29 16:53:23 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgYsN-0008Ji-Cn for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 16:53:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgYsL-0008F5-Lr for qemu-commits@nongnu.org; Fri, 29 Oct 2021 16:53:21 -0400 Received: from out-19.smtp.github.com ([192.30.252.202]:40247) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgYsJ-0002Sl-2G for qemu-commits@nongnu.org; Fri, 29 Oct 2021 16:53:21 -0400 Received: from github.com (hubbernetes-node-032c37e.va3-iad.github.net [10.48.124.23]) by smtp.github.com (Postfix) with ESMTPA id 4690DE09F4 for ; Fri, 29 Oct 2021 13:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635540798; bh=9G5+tx85fs8CWuXFRg1358GJeW6UJ5g6RJyGszjl6V0=; h=Date:From:To:Subject:From; b=OmKHVOQ+gmm0PrTD2loxCFzOtLMN3aKQKaYIoZW7l74JOnbCEk+4vSwFrmDW2aITu mdrgjMXY2AuJZGnGZNkuxHx9iNZf1MWFQ50toMYCKgaQUe7x7mg1NsqdcRXl1jj6Eo hZ1H83PB2QpBCSOw6yBlFn33RnGjipybZE4byG9M= Date: Fri, 29 Oct 2021 13:53:18 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.202; envelope-from=noreply@github.com; helo=out-19.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 9925c8: hw/riscv: virt: Don't use a macro for the PLIC con... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 20:53:21 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: 9925c8bb81d34339ea0433192fdb1d58c12b8edb=0D https://github.com/qemu/qemu/commit/9925c8bb81d34339ea0433192fdb1d5= 8c12b8edb=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D M include/hw/riscv/virt.h=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Don't use a macro for the PLIC configuration=0D =0D Using a macro for the PLIC configuration doesn't make the code any=0D easier to read. Instead it makes it harder to figure out what is going=0D= on, so let's remove it.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: bf357e1d72cd8b7b590518dacdf4b65beb2c61e2=0D https://github.com/qemu/qemu/commit/bf357e1d72cd8b7b590518dacdf4b65= beb2c61e2=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/boot.c=0D M include/hw/riscv/boot.h=0D =0D Log Message:=0D -----------=0D hw/riscv: boot: Add a PLIC config string function=0D =0D Add a generic function that can create the PLIC strings.=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 4e8fb53c0b58cbb18cd243a5b067e4f26db83f77=0D https://github.com/qemu/qemu/commit/4e8fb53c0b58cbb18cd243a5b067e4f= 26db83f77=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/sifive_u.c=0D M include/hw/riscv/sifive_u.h=0D =0D Log Message:=0D -----------=0D hw/riscv: sifive_u: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 8486eb8cdcd336de8ae52d95da45af97f54db63e=0D https://github.com/qemu/qemu/commit/8486eb8cdcd336de8ae52d95da45af9= 7f54db63e=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/microchip_pfsoc.c=0D M include/hw/riscv/microchip_pfsoc.h=0D =0D Log Message:=0D -----------=0D hw/riscv: microchip_pfsoc: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713=0D https://github.com/qemu/qemu/commit/7d10ff8a4de7a9bff1e7b25011f5eb4= 3f24a6713=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/virt.c=0D =0D Log Message:=0D -----------=0D hw/riscv: virt: Use the PLIC config helper function=0D =0D Signed-off-by: Alistair Francis =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Bin Meng =0D Tested-by: Bin Meng =0D Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662=0D https://github.com/qemu/qemu/commit/9b144ed444f1fb3149d9ec17f0c4a64= d4fd7d662=0D Author: Alistair Francis =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M hw/riscv/opentitan.c=0D =0D Log Message:=0D -----------=0D hw/riscv: opentitan: Fixup the PLIC context addresses=0D =0D Fixup the PLIC context address to correctly support the threshold and=0D claim register.=0D =0D Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")=0D Signed-off-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com=0D= =0D =0D Commit: 53dcea58b8ab150ab034f9c19074c5f74d6ca41e=0D https://github.com/qemu/qemu/commit/53dcea58b8ab150ab034f9c19074c5f= 74d6ca41e=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add J-extension into RISC-V=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 138b5c5f8f5abec5acc18d2a256f0a082dc51ef5=0D https://github.com/qemu/qemu/commit/138b5c5f8f5abec5acc18d2a256f0a0= 82dc51ef5=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_bits.h=0D =0D Log Message:=0D -----------=0D target/riscv: Add CSR defines for RISC-V PM extension=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 4bbe8033fcd08769cef49f5149c5c165594ae10a=0D https://github.com/qemu/qemu/commit/4bbe8033fcd08769cef49f5149c5c16= 5594ae10a=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/csr.c=0D =0D Log Message:=0D -----------=0D target/riscv: Support CSRs required for RISC-V PM extension except for = the h-mode=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: b1c279e135e0da33a06544919c2cb89b6988e874=0D https://github.com/qemu/qemu/commit/b1c279e135e0da33a06544919c2cb89= b6988e874=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/machine.c=0D =0D Log Message:=0D -----------=0D target/riscv: Add J extension state description=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: bd5594ca2808b3e353d350a08d72f36cb8e01048=0D https://github.com/qemu/qemu/commit/bd5594ca2808b3e353d350a08d72f36= cb8e01048=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Print new PM CSRs in QEMU logs=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: c655df7fe00669ac9ac3b0614be6e4a6f5782737=0D https://github.com/qemu/qemu/commit/c655df7fe00669ac9ac3b0614be6e4a= 6f5782737=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/insn_trans/trans_rva.c.inc=0D M target/riscv/insn_trans/trans_rvd.c.inc=0D M target/riscv/insn_trans/trans_rvf.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of= instructions=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0774a7a1ff24d6b8c2f90b9c341f057914b18134=0D https://github.com/qemu/qemu/commit/0774a7a1ff24d6b8c2f90b9c341f057= 914b18134=0D Author: Anatoly Parshintsev =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D target/riscv: Implement address masking functions required for RISC-V P= ointer Masking extension=0D =0D Signed-off-by: Anatoly Parshintsev =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Alistair Francis =0D Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0ee9a4e57e1cee4577cab22f6ced6c0c34fb2d94=0D https://github.com/qemu/qemu/commit/0ee9a4e57e1cee4577cab22f6ced6c0= c34fb2d94=0D Author: Alexey Baturo =0D Date: 2021-10-28 (Thu, 28 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.c=0D =0D Log Message:=0D -----------=0D target/riscv: Allow experimental J-ext to be turned on=0D =0D Signed-off-by: Alexey Baturo =0D Reviewed-by: Alistair Francis =0D Reviewed-by: Bin Meng =0D Reviewed-by: Richard Henderson =0D Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 487a99551ae903fc83a878d4cbc6d853e17ad252=0D https://github.com/qemu/qemu/commit/487a99551ae903fc83a878d4cbc6d85= 3e17ad252=0D Author: Jose Martins =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: fix VS interrupts forwarding to HS=0D =0D VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when=0D not delegated in hideleg (which was not being taken into account). This=0D= was mainly because hs level sie was not always considered enabled when=0D= it should. The spec states that "Interrupts for higher-privilege modes,=0D= y>x, are always globally enabled regardless of the setting of the global=0D= yIE bit for the higher-privilege mode." and also "For purposes of=0D interrupt global enables, HS-mode is considered more privileged than=0D VS-mode, and VS-mode is considered more privileged than VU-mode". Also,=0D= vs-level interrupts were not being taken into account unless V=3D1, but=0D= should be unless delegated.=0D =0D Finally, there is no need for a special case for to handle vs interrupts=0D= as the current privilege level, the state of the global ie and of the=0D delegation registers should be enough to route all interrupts to the=0D appropriate privilege level in riscv_cpu_do_interrupt.=0D =0D Signed-off-by: Jose Martins =0D Reviewed-by: Alistair Francis =0D Message-id: 20211026145126.11025-2-josemartins90@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 50d160876414e91e51ac718ac6edea6dbadf4694=0D https://github.com/qemu/qemu/commit/50d160876414e91e51ac718ac6edea6= dbadf4694=0D Author: Jose Martins =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: remove force HS exception=0D =0D There is no need to "force an hs exception" as the current privilege=0D level, the state of the global ie and of the delegation registers should=0D= be enough to route the interrupt to the appropriate privilege level in=0D= riscv_cpu_do_interrupt. The is true for both asynchronous and=0D synchronous exceptions, specifically, guest page faults which must be=0D hardwired to zero hedeleg. As such the hs_force_except mechanism can be=0D= removed.=0D =0D Signed-off-by: Jose Martins =0D Reviewed-by: Alistair Francis =0D Message-id: 20211026145126.11025-3-josemartins90@gmail.com=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92=0D https://github.com/qemu/qemu/commit/0e9030376e1a8eb6d15cb5e69dffa09= a6ff16b92=0D Author: Chih-Min Chao =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M fpu/softfloat-parts.c.inc=0D M fpu/softfloat.c=0D M include/fpu/softfloat.h=0D =0D Log Message:=0D -----------=0D softfloat: add APIs to handle alternative sNaN propagation for fmax/fmi= n=0D =0D For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,=0D =0D The original logic:=0D Return NaN and set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNan= .=0D =0D The alternative path:=0D Set invalid flag if ft1 =3D=3D sNaN || ft2 =3D=3D sNaN.=0D Return NaN only if ft1 =3D=3D NaN && ft2 =3D=3D NaN.=0D =0D The IEEE 754 spec allows both implementation and some architecture such=0D= as riscv choose different defintions in two spec versions.=0D (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to=0D alternative)=0D =0D Signed-off-by: Chih-Min Chao =0D Signed-off-by: Frank Chang =0D Reviewed-by: Richard Henderson =0D Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 15161e425ee1bb1180f9cec574cda44fb10c0931=0D https://github.com/qemu/qemu/commit/15161e425ee1bb1180f9cec574cda44= fb10c0931=0D Author: Chih-Min Chao =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M target/riscv/fpu_helper.c=0D =0D Log Message:=0D -----------=0D target/riscv: change the api for RVF/RVD fmin/fmax=0D =0D The sNaN propagation behavior has been changed since cd20cee7 in=0D https://github.com/riscv/riscv-isa-manual.=0D =0D In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with=0D= IEEE 754-2008 minNum and maxNum operations.=0D =0D In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to=0D implement IEEE 754-2019 minimumNumber and maximumNumber operations.=0D =0D Therefore, to prevent the risk of having too many version variables.=0D Instead of introducing an extra *fext_ver* variable, we tie RVF version=0D= to Priv version. Though it's not completely accurate but is close enough.= =0D =0D Signed-off-by: Chih-Min Chao =0D Signed-off-by: Frank Chang =0D Acked-by: Alistair Francis =0D Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>=0D Signed-off-by: Alistair Francis =0D =0D =0D Commit: 6450ce5634a57e57ee8bb790c080fc7636678f3d=0D https://github.com/qemu/qemu/commit/6450ce5634a57e57ee8bb790c080fc7= 636678f3d=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M fpu/softfloat-parts.c.inc=0D M fpu/softfloat.c=0D M hw/riscv/boot.c=0D M hw/riscv/microchip_pfsoc.c=0D M hw/riscv/opentitan.c=0D M hw/riscv/sifive_u.c=0D M hw/riscv/virt.c=0D M include/fpu/softfloat.h=0D M include/hw/riscv/boot.h=0D M include/hw/riscv/microchip_pfsoc.h=0D M include/hw/riscv/sifive_u.h=0D M include/hw/riscv/virt.h=0D M target/riscv/cpu.c=0D M target/riscv/cpu.h=0D M target/riscv/cpu_bits.h=0D M target/riscv/cpu_helper.c=0D M target/riscv/csr.c=0D M target/riscv/fpu_helper.c=0D M target/riscv/insn_trans/trans_rva.c.inc=0D M target/riscv/insn_trans/trans_rvd.c.inc=0D M target/riscv/insn_trans/trans_rvf.c.inc=0D M target/riscv/insn_trans/trans_rvi.c.inc=0D M target/riscv/machine.c=0D M target/riscv/translate.c=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-app= ly-20211029-1' into staging=0D =0D Fifth RISC-V PR for QEMU 6.2=0D =0D - Use a shared PLIC config helper function=0D - Fixup the OpenTitan PLIC configuration=0D - Add support for the experimental J extension=0D - Update the fmin/fmax handling=0D - Fixup VS interrupt forwarding=0D =0D # gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT=0D # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977= 054=0D # gpg: Good signature from "Alistair Francis " [f= ull]=0D =0D * remotes/alistair23/tags/pull-riscv-to-apply-20211029-1:=0D target/riscv: change the api for RVF/RVD fmin/fmax=0D softfloat: add APIs to handle alternative sNaN propagation for fmax/fmi= n=0D target/riscv: remove force HS exception=0D target/riscv: fix VS interrupts forwarding to HS=0D target/riscv: Allow experimental J-ext to be turned on=0D target/riscv: Implement address masking functions required for RISC-V P= ointer Masking extension=0D target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of= instructions=0D target/riscv: Print new PM CSRs in QEMU logs=0D target/riscv: Add J extension state description=0D target/riscv: Support CSRs required for RISC-V PM extension except for = the h-mode=0D target/riscv: Add CSR defines for RISC-V PM extension=0D target/riscv: Add J-extension into RISC-V=0D hw/riscv: opentitan: Fixup the PLIC context addresses=0D hw/riscv: virt: Use the PLIC config helper function=0D hw/riscv: microchip_pfsoc: Use the PLIC config helper function=0D hw/riscv: sifive_u: Use the PLIC config helper function=0D hw/riscv: boot: Add a PLIC config string function=0D hw/riscv: virt: Don't use a macro for the PLIC configuration=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/a92cecba2791...6450ce5634a5= =0D From MAILER-DAEMON Fri Oct 29 17:00:05 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgYyr-00021g-GM for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 17:00:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgYyp-0001x2-CJ for qemu-commits@nongnu.org; Fri, 29 Oct 2021 17:00:03 -0400 Received: from out-21.smtp.github.com ([192.30.252.204]:37227 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgYyn-0003wb-6w for qemu-commits@nongnu.org; Fri, 29 Oct 2021 17:00:03 -0400 Received: from github.com (hubbernetes-node-b1ab623.ac4-iad.github.net [10.52.205.21]) by smtp.github.com (Postfix) with ESMTPA id 51E865208E5 for ; Fri, 29 Oct 2021 14:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635541200; bh=6pbydoiFKsHCVnMxtrtsz7lXOcbALrIGASvqxqNNndU=; h=Date:From:To:Subject:From; b=XqvKPRfQxU1rob17BOy1kig/x85N/7FpX1kcd2F3oy2pUYkvPJloITLGcs2JWOUPN eP7doyqWywCJ0gHLrCAYdimx8FPEG2k/IUnifj9OxZEgaFsXX4U02wYZq2kopdavF2 3bAeHHzlbWpXeDGbfb7UD/87Fpj/kPDQUslYBmq4= Date: Fri, 29 Oct 2021 14:00:00 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.204; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 07db29: target/i386: Remove core-capability in Snowridge C... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Oct 2021 21:00:03 -0000 Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 07db29f20a9a845c8408df11936889e5411ff44f https://github.com/qemu/qemu/commit/07db29f20a9a845c8408df11936889e5411ff44f Author: Chenyi Qiang Date: 2021-10-29 (Fri, 29 Oct 2021) Changed paths: M target/i386/cpu.c Log Message: ----------- target/i386: Remove core-capability in Snowridge CPU model Because core-capability releated features are model-specific and KVM won't support it, remove the core-capability in CPU model to avoid the warning message. Signed-off-by: Chenyi Qiang Message-Id: <20210827064818.4698-3-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost Commit: a856cce31b48ef1b04ea80893458766ec16e7194 https://github.com/qemu/qemu/commit/a856cce31b48ef1b04ea80893458766ec16e7194 Author: Richard Henderson Date: 2021-10-29 (Fri, 29 Oct 2021) Changed paths: M target/i386/cpu.c Log Message: ----------- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2021-10-29 Bug fixes: * Remove core-capability in Snowridge CPU model # gpg: Signature made Fri 29 Oct 2021 12:05:14 PM PDT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost " [full] * remotes/ehabkost/tags/x86-next-pull-request: target/i386: Remove core-capability in Snowridge CPU model Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/6450ce5634a5...a856cce31b48 From MAILER-DAEMON Fri Oct 29 22:42:12 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgeJw-00077p-Pf for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 22:42:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgeJv-00077g-9i for qemu-commits@nongnu.org; Fri, 29 Oct 2021 22:42:11 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:52217) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgeJs-0004Xs-Hr for qemu-commits@nongnu.org; Fri, 29 Oct 2021 22:42:10 -0400 Received: from github.com (hubbernetes-node-706e292.ac4-iad.github.net [10.52.125.27]) by smtp.github.com (Postfix) with ESMTPA id 746DA60013A for ; Fri, 29 Oct 2021 19:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635561727; bh=ku67pjifbU3wfY6BCMHJUXgkKIUhHwWSPyRlHh0BILg=; h=Date:From:To:Subject:From; b=1voNDvuf1ppF+YbmQGD0yya/h/cNkYJEW5+EVGVnrxlevKFHXd+CbjLZdMXHSqOmA LBcKjX1Fg1Fu4q/LIjbCzo6sPdKJfnOlYZmKNO4aqHnlQtJc2ccUiOuIFOEN/BfJ3d MJIFc3oiYtxkEWu3Kl/gmUB0Oi+TpLNUoIxPW9cU= Date: Fri, 29 Oct 2021 19:42:07 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] 07db29: target/i386: Remove core-capability in Snowridge C... X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Oct 2021 02:42:11 -0000 Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: 07db29f20a9a845c8408df11936889e5411ff44f https://github.com/qemu/qemu/commit/07db29f20a9a845c8408df11936889e5411ff44f Author: Chenyi Qiang Date: 2021-10-29 (Fri, 29 Oct 2021) Changed paths: M target/i386/cpu.c Log Message: ----------- target/i386: Remove core-capability in Snowridge CPU model Because core-capability releated features are model-specific and KVM won't support it, remove the core-capability in CPU model to avoid the warning message. Signed-off-by: Chenyi Qiang Message-Id: <20210827064818.4698-3-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost Commit: a856cce31b48ef1b04ea80893458766ec16e7194 https://github.com/qemu/qemu/commit/a856cce31b48ef1b04ea80893458766ec16e7194 Author: Richard Henderson Date: 2021-10-29 (Fri, 29 Oct 2021) Changed paths: M target/i386/cpu.c Log Message: ----------- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2021-10-29 Bug fixes: * Remove core-capability in Snowridge CPU model # gpg: Signature made Fri 29 Oct 2021 12:05:14 PM PDT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost " [full] * remotes/ehabkost/tags/x86-next-pull-request: target/i386: Remove core-capability in Snowridge CPU model Signed-off-by: Richard Henderson Compare: https://github.com/qemu/qemu/compare/6450ce5634a5...a856cce31b48 From MAILER-DAEMON Fri Oct 29 22:48:13 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgePk-0002zS-T8 for mharc-qemu-commits@gnu.org; Fri, 29 Oct 2021 22:48:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgePi-0002w2-SJ for qemu-commits@nongnu.org; Fri, 29 Oct 2021 22:48:10 -0400 Received: from out-23.smtp.github.com ([192.30.252.206]:38569) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgePg-0006U6-Gm for qemu-commits@nongnu.org; Fri, 29 Oct 2021 22:48:10 -0400 Received: from github.com (hubbernetes-node-76eefbb.ac4-iad.github.net [10.52.207.52]) by smtp.github.com (Postfix) with ESMTPA id 93B5560015D for ; Fri, 29 Oct 2021 19:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635562087; bh=XaNVh25jnY65TwIdeZxHe76UUOpj9uwsag9PnWZ5Ky4=; h=Date:From:To:Subject:From; b=e8yMM4TqPREWWRW/OKluHX/7SjaGlQUcKxpphJr0QiyrCYXx1je549dBC3MrvGCRd veyjFswxmDEH/hWoOULL29iUzs8CZaJj2Sw2oXixumVcFCbEkamOZ35UrizmWrFrRC Sp87Pk+NTvP3Ktmj5K9EJGoEheHXs9jrHBywf6k8= Date: Fri, 29 Oct 2021 19:48:07 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.206; envelope-from=noreply@github.com; helo=out-23.smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] a3c45b: qapi: New special feature flag "unstable" X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Oct 2021 02:48:11 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: a3c45b3e62962f99338716b1347cfb0d427cea44=0D https://github.com/qemu/qemu/commit/a3c45b3e62962f99338716b1347cfb0= d427cea44=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D =0D Log Message:=0D -----------=0D qapi: New special feature flag "unstable"=0D =0D By convention, names starting with "x-" are experimental. The parts=0D of external interfaces so named may be withdrawn or changed=0D incompatibly in future releases.=0D =0D The naming convention makes unstable interfaces easy to recognize.=0D Promoting something from experimental to stable involves a name=0D change. Client code needs to be updated. Occasionally bothersome.=0D =0D Worse, the convention is not universally observed:=0D =0D * QOM type "input-barrier" has properties "x-origin", "y-origin".=0D Looks accidental, but it's ABI since 4.2.=0D =0D * QOM types "memory-backend-file", "memory-backend-memfd",=0D "memory-backend-ram", and "memory-backend-epc" have a property=0D "x-use-canonical-path-for-ramblock-id" that is documented to be=0D stable despite its name.=0D =0D We could document these exceptions, but documentation helps only=0D humans. We want to recognize "unstable" in code, like "deprecated".=0D =0D So support recognizing it the same way: introduce new special feature=0D flag "unstable". It will be treated specially by the QAPI generator,=0D like the existing feature flag "deprecated", and unlike regular=0D feature flags.=0D =0D This commit updates documentation and prepares tests. The next commit=0D= updates the QAPI schema. The remaining patches update the QAPI=0D generator and wire up -compat policy checking.=0D =0D Management applications can then use query-qmp-schema and -compat to=0D manage or guard against use of unstable interfaces the same way as for=0D= deprecated interfaces.=0D =0D docs/devel/qapi-code-gen.txt no longer mandates the naming convention.=0D= Using it anyway might help writers of programs that aren't=0D full-fledged management applications. Not using it can save us=0D bothersome renames. We'll see how that shakes out.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-2-armbru@redhat.com>=0D =0D =0D Commit: 9fb49daabfb0052f05981e5a484cd0d3bf283fc6=0D https://github.com/qemu/qemu/commit/9fb49daabfb0052f05981e5a484cd0d= 3bf283fc6=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M qapi/block-core.json=0D M qapi/migration.json=0D M qapi/misc.json=0D M qapi/qom.json=0D =0D Log Message:=0D -----------=0D qapi: Mark unstable QMP parts with feature 'unstable'=0D =0D Add special feature 'unstable' everywhere the name starts with 'x-',=0D except for InputBarrierProperties member x-origin and=0D MemoryBackendProperties member x-use-canonical-path-for-ramblock-id,=0D because these two are actually stable.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-3-armbru@redhat.com>=0D =0D =0D Commit: 9bafe07bc8b00ce9ba5ea6f4c590239c579d83ee=0D https://github.com/qemu/qemu/commit/9bafe07bc8b00ce9ba5ea6f4c590239= c579d83ee=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qmp/dispatch.h=0D M monitor/misc.c=0D M scripts/qapi/commands.py=0D =0D Log Message:=0D -----------=0D qapi: Eliminate QCO_NO_OPTIONS for a slight simplification=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-4-armbru@redhat.com>=0D =0D =0D Commit: c67db1ed16ff5a7c1b186caa754e0c738aa945b8=0D https://github.com/qemu/qemu/commit/c67db1ed16ff5a7c1b186caa754e0c7= 38aa945b8=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M scripts/qapi/gen.py=0D M scripts/qapi/schema.py=0D =0D Log Message:=0D -----------=0D qapi: Tools for sets of special feature flags in generated code=0D =0D New enum QapiSpecialFeature enumerates the special feature flags.=0D =0D New helper gen_special_features() returns code to represent a=0D collection of special feature flags as a bitset.=0D =0D The next few commits will put them to use.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-5-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: a130728554d0cc19ef0ed4c1c824305c1682e64b=0D https://github.com/qemu/qemu/commit/a130728554d0cc19ef0ed4c1c824305= c1682e64b=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/qapi-forward-visitor.c=0D M qapi/qapi-visit-core.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M qapi/trace-events=0D M scripts/qapi/visit.py=0D =0D Log Message:=0D -----------=0D qapi: Generalize struct member policy checking=0D =0D The generated visitor functions call visit_deprecated_accept() and=0D visit_deprecated() when visiting a struct member with special feature=0D flag 'deprecated'. This makes the feature flag visible to the actual=0D visitors. I want to make feature flag 'unstable' visible there as=0D well, so I can add policy for it.=0D =0D To let me make it visible, replace these functions by=0D visit_policy_reject() and visit_policy_skip(), which take the member's=0D= special features as an argument. Note that the new functions have the=0D= opposite sense, i.e. the return value flips.=0D =0D Signed-off-by: Markus Armbruster =0D Message-Id: <20211028102520.747396-6-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [Unbreak forward visitor]=0D =0D =0D Commit: 6604e4757a1fc5832f87b5f9244efccabb49be8e=0D https://github.com/qemu/qemu/commit/6604e4757a1fc5832f87b5f9244efcc= abb49be8e=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qmp/dispatch.h=0D M monitor/misc.c=0D M qapi/qmp-dispatch.c=0D M qapi/qmp-registry.c=0D M scripts/qapi/commands.py=0D M storage-daemon/qemu-storage-daemon.c=0D =0D Log Message:=0D -----------=0D qapi: Generalize command policy checking=0D =0D The code to check command policy can see special feature flag=0D 'deprecated' as command flag QCO_DEPRECATED. I want to make feature=0D flag 'unstable' visible there as well, so I can add policy for it.=0D =0D To let me make it visible, add member @special_features (a bitset of=0D QapiSpecialFeature) to QmpCommand, and adjust the generator to pass it=0D= through qmp_register_command(). Then replace "QCO_DEPRECATED in=0D @flags" by QAPI_DEPRECATED in @special_features", and drop=0D QCO_DEPRECATED.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-7-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Eric Blake =0D =0D =0D Commit: c8688760437aaf4bfa9012ff5aef8ab1c92a38e1=0D https://github.com/qemu/qemu/commit/c8688760437aaf4bfa9012ff5aef8ab= 1c92a38e1=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/qapi-visit-core.c=0D M scripts/qapi/types.py=0D =0D Log Message:=0D -----------=0D qapi: Generalize enum member policy checking=0D =0D The code to check enumeration value policy can see special feature=0D flag 'deprecated' in QEnumLookup member flags[value]. I want to make=0D feature flag 'unstable' visible there as well, so I can add policy for=0D= it.=0D =0D Instead of extending flags[], replace it by @special_features (a=0D bitset of QapiSpecialFeature), because that's how special features get=0D= passed around elsewhere.=0D =0D Signed-off-by: Markus Armbruster =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-8-armbru@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 7ce5fc63c75d0ac756fd0b4d0472774de17f8fec=0D https://github.com/qemu/qemu/commit/7ce5fc63c75d0ac756fd0b4d0472774= de17f8fec=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/compat-policy.h=0D M qapi/qapi-util.c=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D =0D Log Message:=0D -----------=0D qapi: Factor out compat_policy_input_ok()=0D =0D The code to check policy for handling deprecated input is triplicated.=0D= Factor it out into compat_policy_input_ok() before I mess with it in=0D the next commit.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211028102520.747396-9-armbru@redhat.com>=0D [Policy code moved from qmp-dispatch.c to qapi-util.c to make visitors=0D= link without qmp-dispatch.o]=0D =0D =0D Commit: 57df0dff1a1f4c846aa74a082bfd595a8a990015=0D https://github.com/qemu/qemu/commit/57df0dff1a1f4c846aa74a082bfd595= a8a990015=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/compat.json=0D M qapi/qapi-util.c=0D M qapi/qobject-output-visitor.c=0D M qemu-options.hx=0D M scripts/qapi/events.py=0D M scripts/qapi/schema.py=0D =0D Log Message:=0D -----------=0D qapi: Extend -compat to set policy for unstable interfaces=0D =0D New option parameters unstable-input and unstable-output set policy=0D for unstable interfaces just like deprecated-input and=0D deprecated-output set policy for deprecated interfaces (see commit=0D 6dd75472d5 "qemu-options: New -compat to set policy for deprecated=0D interfaces"). This is intended for testing users of the management=0D interfaces. It is experimental.=0D =0D For now, this covers only syntactic aspects of QMP, i.e. stuff tagged=0D with feature 'unstable'. We may want to extend it to cover semantic=0D aspects, or the command line.=0D =0D Note that there is no good way for management application to detect=0D presence of these new option parameters: they are not visible output=0D of query-qmp-schema or query-command-line-options. Tolerable, because=0D= it's meant for testing. If running with -compat fails, skip the test.=0D= =0D Signed-off-by: Markus Armbruster =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-10-armbru@redhat.com>=0D Reviewed-by: Eric Blake =0D [Doc comments fixed up]=0D =0D =0D Commit: dd61b91c080cdfba1360a5ea1e4693fffb3445b0=0D https://github.com/qemu/qemu/commit/dd61b91c080cdfba1360a5ea1e4693f= ffb3445b0=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M include/qapi/compat-policy.h=0D M include/qapi/qmp/dispatch.h=0D M include/qapi/util.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M monitor/misc.c=0D M qapi/block-core.json=0D M qapi/compat.json=0D M qapi/migration.json=0D M qapi/misc.json=0D M qapi/qapi-forward-visitor.c=0D M qapi/qapi-util.c=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qmp-registry.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M qapi/qom.json=0D M qapi/trace-events=0D M qemu-options.hx=0D M scripts/qapi/commands.py=0D M scripts/qapi/events.py=0D M scripts/qapi/gen.py=0D M scripts/qapi/schema.py=0D M scripts/qapi/types.py=0D M scripts/qapi/visit.py=0D M storage-daemon/qemu-storage-daemon.c=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29'= into staging=0D =0D QAPI patches patches for 2021-10-29=0D =0D # gpg: Signature made Fri 29 Oct 2021 12:28:53 PM PDT=0D # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918= 653=0D # gpg: issuer "armbru@redhat.com"=0D # gpg: Good signature from "Markus Armbruster " [full]= =0D # gpg: aka "Markus Armbruster " [ful= l]=0D =0D * remotes/armbru/tags/pull-qapi-2021-10-29:=0D qapi: Extend -compat to set policy for unstable interfaces=0D qapi: Factor out compat_policy_input_ok()=0D qapi: Generalize enum member policy checking=0D qapi: Generalize command policy checking=0D qapi: Generalize struct member policy checking=0D qapi: Tools for sets of special feature flags in generated code=0D qapi: Eliminate QCO_NO_OPTIONS for a slight simplification=0D qapi: Mark unstable QMP parts with feature 'unstable'=0D qapi: New special feature flag "unstable"=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/a856cce31b48...dd61b91c080c= =0D From MAILER-DAEMON Sat Oct 30 00:44:37 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mggEO-0006ti-Sb for mharc-qemu-commits@gnu.org; Sat, 30 Oct 2021 00:44:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mggEM-0006sg-JB for qemu-commits@nongnu.org; Sat, 30 Oct 2021 00:44:34 -0400 Received: from out-17.smtp.github.com ([192.30.252.200]:53033 helo=smtp.github.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mggEJ-00072f-VH for qemu-commits@nongnu.org; Sat, 30 Oct 2021 00:44:34 -0400 Received: from github.com (hubbernetes-node-597131f.va3-iad.github.net [10.48.209.97]) by smtp.github.com (Postfix) with ESMTPA id B22D05C0537 for ; Fri, 29 Oct 2021 21:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635569070; bh=R9Mvc4At9B+nHiArbYvlOU6mAtSjN8jPS2AK6PD5qeM=; h=Date:From:To:Subject:From; b=JGjIfTRW3LWd+s5qjITntgwEBY+D+RpXP5wU5dh+jscvRG6YvcRDIrnz4Ny1Zqibr 7sFvkUd5dfYAf10yN+a0qlcYC93WCrE6mlfK2kyyxA87TwZq3i1GX27czHEX6Mk9ie CKYRdtyOiWzvvlvjeXz8gje91cyEl+bkXo5PZCnc= Date: Fri, 29 Oct 2021 21:44:30 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.200; envelope-from=noreply@github.com; helo=smtp.github.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] a3c45b: qapi: New special feature flag "unstable" X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Oct 2021 04:44:34 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: a3c45b3e62962f99338716b1347cfb0d427cea44=0D https://github.com/qemu/qemu/commit/a3c45b3e62962f99338716b1347cfb0= d427cea44=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D =0D Log Message:=0D -----------=0D qapi: New special feature flag "unstable"=0D =0D By convention, names starting with "x-" are experimental. The parts=0D of external interfaces so named may be withdrawn or changed=0D incompatibly in future releases.=0D =0D The naming convention makes unstable interfaces easy to recognize.=0D Promoting something from experimental to stable involves a name=0D change. Client code needs to be updated. Occasionally bothersome.=0D =0D Worse, the convention is not universally observed:=0D =0D * QOM type "input-barrier" has properties "x-origin", "y-origin".=0D Looks accidental, but it's ABI since 4.2.=0D =0D * QOM types "memory-backend-file", "memory-backend-memfd",=0D "memory-backend-ram", and "memory-backend-epc" have a property=0D "x-use-canonical-path-for-ramblock-id" that is documented to be=0D stable despite its name.=0D =0D We could document these exceptions, but documentation helps only=0D humans. We want to recognize "unstable" in code, like "deprecated".=0D =0D So support recognizing it the same way: introduce new special feature=0D flag "unstable". It will be treated specially by the QAPI generator,=0D like the existing feature flag "deprecated", and unlike regular=0D feature flags.=0D =0D This commit updates documentation and prepares tests. The next commit=0D= updates the QAPI schema. The remaining patches update the QAPI=0D generator and wire up -compat policy checking.=0D =0D Management applications can then use query-qmp-schema and -compat to=0D manage or guard against use of unstable interfaces the same way as for=0D= deprecated interfaces.=0D =0D docs/devel/qapi-code-gen.txt no longer mandates the naming convention.=0D= Using it anyway might help writers of programs that aren't=0D full-fledged management applications. Not using it can save us=0D bothersome renames. We'll see how that shakes out.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-2-armbru@redhat.com>=0D =0D =0D Commit: 9fb49daabfb0052f05981e5a484cd0d3bf283fc6=0D https://github.com/qemu/qemu/commit/9fb49daabfb0052f05981e5a484cd0d= 3bf283fc6=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M qapi/block-core.json=0D M qapi/migration.json=0D M qapi/misc.json=0D M qapi/qom.json=0D =0D Log Message:=0D -----------=0D qapi: Mark unstable QMP parts with feature 'unstable'=0D =0D Add special feature 'unstable' everywhere the name starts with 'x-',=0D except for InputBarrierProperties member x-origin and=0D MemoryBackendProperties member x-use-canonical-path-for-ramblock-id,=0D because these two are actually stable.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-3-armbru@redhat.com>=0D =0D =0D Commit: 9bafe07bc8b00ce9ba5ea6f4c590239c579d83ee=0D https://github.com/qemu/qemu/commit/9bafe07bc8b00ce9ba5ea6f4c590239= c579d83ee=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qmp/dispatch.h=0D M monitor/misc.c=0D M scripts/qapi/commands.py=0D =0D Log Message:=0D -----------=0D qapi: Eliminate QCO_NO_OPTIONS for a slight simplification=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Juan Quintela =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-4-armbru@redhat.com>=0D =0D =0D Commit: c67db1ed16ff5a7c1b186caa754e0c738aa945b8=0D https://github.com/qemu/qemu/commit/c67db1ed16ff5a7c1b186caa754e0c7= 38aa945b8=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M scripts/qapi/gen.py=0D M scripts/qapi/schema.py=0D =0D Log Message:=0D -----------=0D qapi: Tools for sets of special feature flags in generated code=0D =0D New enum QapiSpecialFeature enumerates the special feature flags.=0D =0D New helper gen_special_features() returns code to represent a=0D collection of special feature flags as a bitset.=0D =0D The next few commits will put them to use.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: John Snow =0D Message-Id: <20211028102520.747396-5-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: a130728554d0cc19ef0ed4c1c824305c1682e64b=0D https://github.com/qemu/qemu/commit/a130728554d0cc19ef0ed4c1c824305= c1682e64b=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M qapi/qapi-forward-visitor.c=0D M qapi/qapi-visit-core.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M qapi/trace-events=0D M scripts/qapi/visit.py=0D =0D Log Message:=0D -----------=0D qapi: Generalize struct member policy checking=0D =0D The generated visitor functions call visit_deprecated_accept() and=0D visit_deprecated() when visiting a struct member with special feature=0D flag 'deprecated'. This makes the feature flag visible to the actual=0D visitors. I want to make feature flag 'unstable' visible there as=0D well, so I can add policy for it.=0D =0D To let me make it visible, replace these functions by=0D visit_policy_reject() and visit_policy_skip(), which take the member's=0D= special features as an argument. Note that the new functions have the=0D= opposite sense, i.e. the return value flips.=0D =0D Signed-off-by: Markus Armbruster =0D Message-Id: <20211028102520.747396-6-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D [Unbreak forward visitor]=0D =0D =0D Commit: 6604e4757a1fc5832f87b5f9244efccabb49be8e=0D https://github.com/qemu/qemu/commit/6604e4757a1fc5832f87b5f9244efcc= abb49be8e=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/qmp/dispatch.h=0D M monitor/misc.c=0D M qapi/qmp-dispatch.c=0D M qapi/qmp-registry.c=0D M scripts/qapi/commands.py=0D M storage-daemon/qemu-storage-daemon.c=0D =0D Log Message:=0D -----------=0D qapi: Generalize command policy checking=0D =0D The code to check command policy can see special feature flag=0D 'deprecated' as command flag QCO_DEPRECATED. I want to make feature=0D flag 'unstable' visible there as well, so I can add policy for it.=0D =0D To let me make it visible, add member @special_features (a bitset of=0D QapiSpecialFeature) to QmpCommand, and adjust the generator to pass it=0D= through qmp_register_command(). Then replace "QCO_DEPRECATED in=0D @flags" by QAPI_DEPRECATED in @special_features", and drop=0D QCO_DEPRECATED.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-7-armbru@redhat.com>=0D Reviewed-by: Juan Quintela =0D Reviewed-by: Eric Blake =0D =0D =0D Commit: c8688760437aaf4bfa9012ff5aef8ab1c92a38e1=0D https://github.com/qemu/qemu/commit/c8688760437aaf4bfa9012ff5aef8ab= 1c92a38e1=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/qapi-visit-core.c=0D M scripts/qapi/types.py=0D =0D Log Message:=0D -----------=0D qapi: Generalize enum member policy checking=0D =0D The code to check enumeration value policy can see special feature=0D flag 'deprecated' in QEnumLookup member flags[value]. I want to make=0D feature flag 'unstable' visible there as well, so I can add policy for=0D= it.=0D =0D Instead of extending flags[], replace it by @special_features (a=0D bitset of QapiSpecialFeature), because that's how special features get=0D= passed around elsewhere.=0D =0D Signed-off-by: Markus Armbruster =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-8-armbru@redhat.com>=0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 7ce5fc63c75d0ac756fd0b4d0472774de17f8fec=0D https://github.com/qemu/qemu/commit/7ce5fc63c75d0ac756fd0b4d0472774= de17f8fec=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/compat-policy.h=0D M qapi/qapi-util.c=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qobject-input-visitor.c=0D =0D Log Message:=0D -----------=0D qapi: Factor out compat_policy_input_ok()=0D =0D The code to check policy for handling deprecated input is triplicated.=0D= Factor it out into compat_policy_input_ok() before I mess with it in=0D the next commit.=0D =0D Signed-off-by: Markus Armbruster =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <20211028102520.747396-9-armbru@redhat.com>=0D [Policy code moved from qmp-dispatch.c to qapi-util.c to make visitors=0D= link without qmp-dispatch.o]=0D =0D =0D Commit: 57df0dff1a1f4c846aa74a082bfd595a8a990015=0D https://github.com/qemu/qemu/commit/57df0dff1a1f4c846aa74a082bfd595= a8a990015=0D Author: Markus Armbruster =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M include/qapi/util.h=0D M qapi/compat.json=0D M qapi/qapi-util.c=0D M qapi/qobject-output-visitor.c=0D M qemu-options.hx=0D M scripts/qapi/events.py=0D M scripts/qapi/schema.py=0D =0D Log Message:=0D -----------=0D qapi: Extend -compat to set policy for unstable interfaces=0D =0D New option parameters unstable-input and unstable-output set policy=0D for unstable interfaces just like deprecated-input and=0D deprecated-output set policy for deprecated interfaces (see commit=0D 6dd75472d5 "qemu-options: New -compat to set policy for deprecated=0D interfaces"). This is intended for testing users of the management=0D interfaces. It is experimental.=0D =0D For now, this covers only syntactic aspects of QMP, i.e. stuff tagged=0D with feature 'unstable'. We may want to extend it to cover semantic=0D aspects, or the command line.=0D =0D Note that there is no good way for management application to detect=0D presence of these new option parameters: they are not visible output=0D of query-qmp-schema or query-command-line-options. Tolerable, because=0D= it's meant for testing. If running with -compat fails, skip the test.=0D= =0D Signed-off-by: Markus Armbruster =0D Acked-by: John Snow =0D Message-Id: <20211028102520.747396-10-armbru@redhat.com>=0D Reviewed-by: Eric Blake =0D [Doc comments fixed up]=0D =0D =0D Commit: dd61b91c080cdfba1360a5ea1e4693fffb3445b0=0D https://github.com/qemu/qemu/commit/dd61b91c080cdfba1360a5ea1e4693f= ffb3445b0=0D Author: Richard Henderson =0D Date: 2021-10-29 (Fri, 29 Oct 2021)=0D =0D Changed paths:=0D M docs/devel/qapi-code-gen.rst=0D M include/qapi/compat-policy.h=0D M include/qapi/qmp/dispatch.h=0D M include/qapi/util.h=0D M include/qapi/visitor-impl.h=0D M include/qapi/visitor.h=0D M monitor/misc.c=0D M qapi/block-core.json=0D M qapi/compat.json=0D M qapi/migration.json=0D M qapi/misc.json=0D M qapi/qapi-forward-visitor.c=0D M qapi/qapi-util.c=0D M qapi/qapi-visit-core.c=0D M qapi/qmp-dispatch.c=0D M qapi/qmp-registry.c=0D M qapi/qobject-input-visitor.c=0D M qapi/qobject-output-visitor.c=0D M qapi/qom.json=0D M qapi/trace-events=0D M qemu-options.hx=0D M scripts/qapi/commands.py=0D M scripts/qapi/events.py=0D M scripts/qapi/gen.py=0D M scripts/qapi/schema.py=0D M scripts/qapi/types.py=0D M scripts/qapi/visit.py=0D M storage-daemon/qemu-storage-daemon.c=0D M tests/qapi-schema/qapi-schema-test.json=0D M tests/qapi-schema/qapi-schema-test.out=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-10-29'= into staging=0D =0D QAPI patches patches for 2021-10-29=0D =0D # gpg: Signature made Fri 29 Oct 2021 12:28:53 PM PDT=0D # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918= 653=0D # gpg: issuer "armbru@redhat.com"=0D # gpg: Good signature from "Markus Armbruster " [full]= =0D # gpg: aka "Markus Armbruster " [ful= l]=0D =0D * remotes/armbru/tags/pull-qapi-2021-10-29:=0D qapi: Extend -compat to set policy for unstable interfaces=0D qapi: Factor out compat_policy_input_ok()=0D qapi: Generalize enum member policy checking=0D qapi: Generalize command policy checking=0D qapi: Generalize struct member policy checking=0D qapi: Tools for sets of special feature flags in generated code=0D qapi: Eliminate QCO_NO_OPTIONS for a slight simplification=0D qapi: Mark unstable QMP parts with feature 'unstable'=0D qapi: New special feature flag "unstable"=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/a856cce31b48...dd61b91c080c= =0D From MAILER-DAEMON Sat Oct 30 14:32:49 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mgt9t-0007Nd-Gi for mharc-qemu-commits@gnu.org; Sat, 30 Oct 2021 14:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgt9k-0007Kq-4z for qemu-commits@nongnu.org; Sat, 30 Oct 2021 14:32:45 -0400 Received: from out-28.smtp.github.com ([192.30.252.211]:45099) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgt9g-0001zD-Eh for qemu-commits@nongnu.org; Sat, 30 Oct 2021 14:32:39 -0400 Received: from github.com (hubbernetes-node-71c7075.ash1-iad.github.net [10.56.112.69]) by smtp.github.com (Postfix) with ESMTPA id 8D1849008E4 for ; Sat, 30 Oct 2021 11:32:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635618755; bh=QTG7CLVExSEV58XYvzaGOCXNYGy41ra7BaVBNKznfdg=; h=Date:From:To:Subject:From; b=E0yszVXU6TfJEWYYWU8X8QLN0XsyIgW/Xg8Al7kAWH0aEigfX+lFUu4sRaLIwaxCV Gl2TM8ORaNgKAJ0pJj3/MbtB6X6CluTH+JgUjwshtI86QGoo1edtjpwHs8WzF0AbnG 7qQuv+81AT5Do3ZFt66WK3a8WaNpytwN8A81A8HM= Date: Sat, 30 Oct 2021 11:32:35 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.211; envelope-from=noreply@github.com; helo=out-28.smtp.github.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] b3793b: hw/sh4: Coding style: Remove tabs X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Oct 2021 18:32:48 -0000 Branch: refs/heads/staging=0D Home: https://github.com/qemu/qemu=0D Commit: b3793b8a9183d6019f557263bbddd647e1918394=0D https://github.com/qemu/qemu/commit/b3793b8a9183d6019f557263bbddd64= 7e1918394=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Remove tabs=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <2d9b2c470ec022cc85a25b3e5de337b5e794f7f6.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 221389657aa77ced7a17936747f288193e321d3f=0D https://github.com/qemu/qemu/commit/221389657aa77ced7a17936747f2881= 93e321d3f=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Fix multi-line comments=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <3f192c699f4e5949ec0fcc436e5610f50afe2dbf.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: f94bff1337ff525e2ff458b8e4cd57f9561acde3=0D https://github.com/qemu/qemu/commit/f94bff1337ff525e2ff458b8e4cd57f= 9561acde3=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/pci-host/sh_pci.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D M hw/timer/sh_timer.c=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: White space fixes=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: ac3c9e74c1ee1071e5be692a611c5ee261b9b581=0D https://github.com/qemu/qemu/commit/ac3c9e74c1ee1071e5be692a611c5ee= 261b9b581=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Add missing braces=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 373b96b9c6d77a54a52239b422a44958d9dcc67e=0D https://github.com/qemu/qemu/commit/373b96b9c6d77a54a52239b422a4495= 8d9dcc67e=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Remove unnecessary casts=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <6cb1bcf24572ad8465c20b64fec81157f34bcbe9.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3b885dabd09f449143adbfc0595896b47648673d=0D https://github.com/qemu/qemu/commit/3b885dabd09f449143adbfc0595896b= 47648673d=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Fix typos in a comment=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: ad52cfc13750662fd003565e8035bb8ffbd4f0ef=0D https://github.com/qemu/qemu/commit/ad52cfc13750662fd003565e8035bb8= ffbd4f0ef=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D M hw/intc/sh_intc.c=0D M hw/intc/trace-events=0D M hw/sh4/sh7750.c=0D A hw/sh4/trace-events=0D A hw/sh4/trace.h=0D M hw/timer/sh_timer.c=0D M hw/timer/trace-events=0D M meson.build=0D =0D Log Message:=0D -----------=0D hw/sh4: Change debug printfs to traces=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D [PMD: Fixed format strings for 32-bit hosts]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 6e5dd76f213afc3fdf07ddebe3fed3980228f71b=0D https://github.com/qemu/qemu/commit/6e5dd76f213afc3fdf07ddebe3fed39= 80228f71b=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/sh4/r2d.c=0D =0D Log Message:=0D -----------=0D hw/sh4/r2d: Use error_report instead of fprintf to stderr=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <7f320ab72f3d4d43cd62925230a9f83583413f67.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3cf7ce4337aebf8f9148ee53033710b4c4b00f01=0D https://github.com/qemu/qemu/commit/3cf7ce4337aebf8f9148ee53033710b= 4c4b00f01=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Do not abort on invalid access=0D =0D Replace fprintf with qemu_log_mask LOG_GUEST_ERROR as the intention is=0D= to handle valid accesses in these functions so if we get to these=0D errors then it's an invalid access. Do not abort as that would allow=0D the guest to crash QEMU and the practice in other devices is to not do=0D= that just log and ignore the invalid access. While at it also simplify=0D= the complex bit ops to check if a return value was set which can be=0D done much simpler and clearer.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <6b46045141d6d9cc32e17c223896fa1116384796.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 2f6df13748a7de19ab150a52af846f70303746e5=0D https://github.com/qemu/qemu/commit/2f6df13748a7de19ab150a52af846f7= 0303746e5=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Rename type sh_serial_state to SHSerialState=0D =0D Coding style says types should be camel case.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <0f185653528c99eeeb2b4e4afb8b818d93298c20.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 5b344b02e1813c6823e76ea981a56e7b432985a4=0D https://github.com/qemu/qemu/commit/5b344b02e1813c6823e76ea981a56e7= b432985a4=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Embed QEMUTimer in state struct=0D =0D Instead of allocating timer with timer_new store it directly in the=0D state struct. This makes it simpler to free it together with the device.=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 017f77bbf75ef6c9b69188a150020013e6d5d8ad=0D https://github.com/qemu/qemu/commit/017f77bbf75ef6c9b69188a15002001= 3e6d5d8ad=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Split off sh_serial_reset() from sh_serial_init()=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: beeb520925d54f5c69c66656a96dc68de0eec9a4=0D https://github.com/qemu/qemu/commit/beeb520925d54f5c69c66656a96dc68= de0eec9a4=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/sh4/sh7750.c=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: QOM-ify=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <92902ba34fdf2c8c62232365fbb6531b1036d557.1635541329.git.bala= ton@eik.bme.hu>=0D [PMD: Use g_strdup() to initialize DeviceState::id]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 44ae04f0328d0726c1b1666600d0aa8da604a341=0D https://github.com/qemu/qemu/commit/44ae04f0328d0726c1b1666600d0aa8= da604a341=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Add device id to trace output=0D =0D Normally there are at least two sh_serial instances. Add device id to=0D trace messages to make it clear which instance they belong to=0D otherwise its not possible to tell which serial device is accessed.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: cfaf2806e87b0eb962866e041a0fd75a524394d8=0D https://github.com/qemu/qemu/commit/cfaf2806e87b0eb962866e041a0fd75= a524394d8=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Use existing macro instead of local one=0D =0D The INTC_A7 local macro does the same as the A7ADDR from=0D include/sh/sh.h so use the latter and drop the local macro definition.=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <53f033477c73b7c9b021d36033c590416d6199c7.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: dc6f1734b704e5563e4c512393e2629799093681=0D https://github.com/qemu/qemu/commit/dc6f1734b704e5563e4c512393e2629= 799093681=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Turn some defines into an enum=0D =0D Turn the INTC_MODE defines into an enum and clean up the function=0D returning these to make it clearer by removing nested ifs and=0D superfluous parenthesis. The one remaining #define is a flag which is=0D moved further apart by changing its value from 8 to 0x80 to leave some=0D= spare bits as this is or-ed with the enum value at some places.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <4adf4e1ac9d2e728e5a536c69e310d77f0c4455a.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 81d18cd48a87205bed159586fd3ca524a36bd49a=0D https://github.com/qemu/qemu/commit/81d18cd48a87205bed159586fd3ca52= 4a36bd49a=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Rename iomem region=0D =0D Rename the iomem region to "intc" from "interrupt-controller" which=0D makes the info mtree output less wide as it is already too wide=0D because of all the aliases. Also drop the format macro which was only=0D used twice in close proximity so we can just use the literal string=0D instead without a macro definition.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 92d1d3ada11dfb338bb96b6405d6938901182488=0D https://github.com/qemu/qemu/commit/92d1d3ada11dfb338bb96b6405d6938= 901182488=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Drop another useless macro=0D =0D The INT_REG_PARAMS macro was only used a few times within one function=0D= on adjacent lines and is actually more complex than writing out the=0D parameters so simplify it by expanding the macro at call sites and=0D dropping the #define.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 51cb902baca1ccfba270fa5a1f230d85301a68e6=0D https://github.com/qemu/qemu/commit/51cb902baca1ccfba270fa5a1f230d8= 5301a68e6=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Move sh_intc_register() closer to its only user=0D =0D The sh_intc_register() function is only used at one place. Move them=0D together so it's easier to see what's going on.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <49f2742bc67cba7164385fafad204ab1e1bd3a0b.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 46ea1f8236ffdf80c52dad79ee7d2dc18ed5eda1=0D https://github.com/qemu/qemu/commit/46ea1f8236ffdf80c52dad79ee7d2dc= 18ed5eda1=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Remove excessive parenthesis=0D =0D Drop unneded parenthesis and split up one complex expression to write=0D it with less brackets so it's easier to follow.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 12201fe38a592695eea647c9600d08a4622c1431=0D https://github.com/qemu/qemu/commit/12201fe38a592695eea647c9600d08a= 4622c1431=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Use array index instead of pointer arithmetics=0D =0D Address of element i is one word thus clearer than array + i.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 9b12fb10b731d8d9cbb6cc0bf200d1c48de7f20d=0D https://github.com/qemu/qemu/commit/9b12fb10b731d8d9cbb6cc0bf200d1c= 48de7f20d=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D M hw/sh4/sh7750.c=0D M include/hw/sh4/sh_intc.h=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Inline and drop sh_intc_source() function=0D =0D This function is very simple and provides no advantage. Call sites=0D become simpler without it so just write it in line and drop the=0D separate function.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 85208f7a9756948ed16ef09d7982584528904430=0D https://github.com/qemu/qemu/commit/85208f7a9756948ed16ef09d7982584= 528904430=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Replace abort() with g_assert_not_reached()=0D =0D All the places that call abort should not happen which is better=0D marked by g_assert_not_reached.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <039e6a784532f2af27f8adeafdb8e0391722f567.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 418a221c2b8a97838980e61cdfef356ec6976e4b=0D https://github.com/qemu/qemu/commit/418a221c2b8a97838980e61cdfef356= ec6976e4b=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Avoid using continue in loops=0D =0D Instead of if !expr continue else do something it is more straight=0D forward to say if expr then do something, especially if the action is=0D just a few lines. Remove such uses of continue to make the code easier=0D= to follow.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Message-Id: <0efaa5e7a1a3ee11f82b3bb1942c287576c67f8b.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 36cf5ee8852a3aac56be160ad87cc49974278c46=0D https://github.com/qemu/qemu/commit/36cf5ee8852a3aac56be160ad87cc49= 974278c46=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Simplify allocating sources array=0D =0D Use g_new0 instead of g_malloc0 and avoid some unneeded temporary=0D variable assignments.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <72efc4f2c4ff8b96848d03dca08e4541ee4076f6.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 32331787896104022deb024906f1cca9606cfdc6=0D https://github.com/qemu/qemu/commit/32331787896104022deb024906f1cca= 9606cfdc6=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Remove unneeded local variable initialisers=0D =0D The sh_intc_locate function will either init these or not return so no=0D= need to initialise them.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <15e04aa665c68ab5df47bbf505346d413be2fc1c.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 5d9b737e5144baff1c3a4205ff57d974a347c204=0D https://github.com/qemu/qemu/commit/5d9b737e5144baff1c3a4205ff57d97= 4a347c204=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Rename sh_timer_state to SHTimerState=0D =0D According to coding style types should be camel case, also remove=0D unneded casts from void *.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: f64ccec414e72754921c25de6395d7e3b10a0c9e=0D https://github.com/qemu/qemu/commit/f64ccec414e72754921c25de6395d7e= 3b10a0c9e=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Do not wrap lines that are not too long=0D =0D It's more readable to keep things on one line if it fits the length limit= .=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <97bc2a38991f33fd0c8cc2e4d0a3a29b20c47d1f.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 65307c7792a50bffe036423ec21107f4fb9c74e3=0D https://github.com/qemu/qemu/commit/65307c7792a50bffe036423ec21107f= 4fb9c74e3=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Fix timer memory region size=0D =0D The timer unit only has registers that fit in a region 0x30 bytes=0D long. No need to have the timer region larger than that.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 46e44759fc24a05e338cd37a735b4aad5422e717=0D https://github.com/qemu/qemu/commit/46e44759fc24a05e338cd37a735b4aa= d5422e717=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Remove use of hw_error=0D =0D The hw_error function calls abort and is not meant to be used by=0D devices. Use qemu_log_mask instead to log and ignore invalid accesses.=0D= Also fix format strings to allow dropping type casts of hwaddr and use=0D= __func__ instead of hard coding function name in the message which=0D were wrong in two cases.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: af531756d25541a1b3b3d9a14e72e7fedd941a2e=0D https://github.com/qemu/qemu/commit/af531756d25541a1b3b3d9a14e72e7f= edd941a2e=0D Author: Richard Henderson =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D M hw/intc/sh_intc.c=0D M hw/intc/trace-events=0D M hw/pci-host/sh_pci.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D A hw/sh4/trace-events=0D A hw/sh4/trace.h=0D M hw/timer/sh_timer.c=0D M hw/timer/trace-events=0D M include/hw/sh4/sh.h=0D M include/hw/sh4/sh_intc.h=0D M meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' int= o staging=0D =0D Renesas SH-4 patches queue=0D =0D Patches from Zoltan:=0D - Various clean up to align the code style with the rest of the code base= =0D - QOM'ify the SH_SERIAL device=0D - Modify few memory region size to better match the hardware manual=0D =0D # gpg: Signature made Sat 30 Oct 2021 10:05:03 AM PDT=0D # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC= 0DE=0D # gpg: Good signature from "Philippe Mathieu-Daud=C3=A9 (F4BUG) " [full]=0D =0D * remotes/philmd/tags/renesas-20211030: (30 commits)=0D hw/timer/sh_timer: Remove use of hw_error=0D hw/timer/sh_timer: Fix timer memory region size=0D hw/timer/sh_timer: Do not wrap lines that are not too long=0D hw/timer/sh_timer: Rename sh_timer_state to SHTimerState=0D hw/intc/sh_intc: Remove unneeded local variable initialisers=0D hw/intc/sh_intc: Simplify allocating sources array=0D hw/intc/sh_intc: Avoid using continue in loops=0D hw/intc/sh_intc: Replace abort() with g_assert_not_reached()=0D hw/intc/sh_intc: Inline and drop sh_intc_source() function=0D hw/intc/sh_intc: Use array index instead of pointer arithmetics=0D hw/intc/sh_intc: Remove excessive parenthesis=0D hw/intc/sh_intc: Move sh_intc_register() closer to its only user=0D hw/intc/sh_intc: Drop another useless macro=0D hw/intc/sh_intc: Rename iomem region=0D hw/intc/sh_intc: Turn some defines into an enum=0D hw/intc/sh_intc: Use existing macro instead of local one=0D hw/char/sh_serial: Add device id to trace output=0D hw/char/sh_serial: QOM-ify=0D hw/char/sh_serial: Split off sh_serial_reset() from sh_serial_init()=0D= hw/char/sh_serial: Embed QEMUTimer in state struct=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/dd61b91c080c...af531756d255= =0D From MAILER-DAEMON Sat Oct 30 16:13:01 2021 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mguir-0006ui-5l for mharc-qemu-commits@gnu.org; Sat, 30 Oct 2021 16:13:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mguio-0006tx-Nr for qemu-commits@nongnu.org; Sat, 30 Oct 2021 16:12:58 -0400 Received: from out-28.smtp.github.com ([192.30.252.211]:59027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mguil-0001Ro-Ke for qemu-commits@nongnu.org; Sat, 30 Oct 2021 16:12:58 -0400 Received: from github.com (hubbernetes-node-338fd2c.ash1-iad.github.net [10.56.121.25]) by smtp.github.com (Postfix) with ESMTPA id CF6EF900235 for ; Sat, 30 Oct 2021 13:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=github.com; s=pf2014; t=1635624774; bh=I3bqZpNMx3ZA4DGOk5KB9pXpq377ldr2sDBEtW0lfM8=; h=Date:From:To:Subject:From; b=zLAiyUjV6UR7XawBRJuvZA95FosuRQtG7a6Z9QgyhuUCfHy/lMAjVmwrlgmETJCe7 5Kc6GrKuLxswEwKi16xxKB2F2Mbv+0PUPNNvNOb14n2soeCMlUZZ5wxCEi5yOGV4Vt DB4WsHv6i6lIgGlnJBaSlFPeXHbxXXOBBCyVuUIA= Date: Sat, 30 Oct 2021 13:12:54 -0700 From: Richard Henderson To: qemu-commits@nongnu.org Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GitHub-Recipient-Address: qemu-commits@nongnu.org X-Auto-Response-Suppress: All Received-SPF: pass client-ip=192.30.252.211; envelope-from=noreply@github.com; helo=out-28.smtp.github.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Subject: [Qemu-commits] [qemu/qemu] b3793b: hw/sh4: Coding style: Remove tabs X-BeenThere: qemu-commits@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Oct 2021 20:12:59 -0000 Branch: refs/heads/master=0D Home: https://github.com/qemu/qemu=0D Commit: b3793b8a9183d6019f557263bbddd647e1918394=0D https://github.com/qemu/qemu/commit/b3793b8a9183d6019f557263bbddd64= 7e1918394=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Remove tabs=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <2d9b2c470ec022cc85a25b3e5de337b5e794f7f6.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 221389657aa77ced7a17936747f288193e321d3f=0D https://github.com/qemu/qemu/commit/221389657aa77ced7a17936747f2881= 93e321d3f=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Fix multi-line comments=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <3f192c699f4e5949ec0fcc436e5610f50afe2dbf.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: f94bff1337ff525e2ff458b8e4cd57f9561acde3=0D https://github.com/qemu/qemu/commit/f94bff1337ff525e2ff458b8e4cd57f= 9561acde3=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/pci-host/sh_pci.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D M hw/timer/sh_timer.c=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: White space fixes=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: ac3c9e74c1ee1071e5be692a611c5ee261b9b581=0D https://github.com/qemu/qemu/commit/ac3c9e74c1ee1071e5be692a611c5ee= 261b9b581=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/intc/sh_intc.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Add missing braces=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 373b96b9c6d77a54a52239b422a44958d9dcc67e=0D https://github.com/qemu/qemu/commit/373b96b9c6d77a54a52239b422a4495= 8d9dcc67e=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Coding style: Remove unnecessary casts=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Yoshinori Sato =0D Message-Id: <6cb1bcf24572ad8465c20b64fec81157f34bcbe9.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3b885dabd09f449143adbfc0595896b47648673d=0D https://github.com/qemu/qemu/commit/3b885dabd09f449143adbfc0595896b= 47648673d=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/sh4: Fix typos in a comment=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: ad52cfc13750662fd003565e8035bb8ffbd4f0ef=0D https://github.com/qemu/qemu/commit/ad52cfc13750662fd003565e8035bb8= ffbd4f0ef=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D M hw/intc/sh_intc.c=0D M hw/intc/trace-events=0D M hw/sh4/sh7750.c=0D A hw/sh4/trace-events=0D A hw/sh4/trace.h=0D M hw/timer/sh_timer.c=0D M hw/timer/trace-events=0D M meson.build=0D =0D Log Message:=0D -----------=0D hw/sh4: Change debug printfs to traces=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D [PMD: Fixed format strings for 32-bit hosts]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 6e5dd76f213afc3fdf07ddebe3fed3980228f71b=0D https://github.com/qemu/qemu/commit/6e5dd76f213afc3fdf07ddebe3fed39= 80228f71b=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/sh4/r2d.c=0D =0D Log Message:=0D -----------=0D hw/sh4/r2d: Use error_report instead of fprintf to stderr=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <7f320ab72f3d4d43cd62925230a9f83583413f67.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 3cf7ce4337aebf8f9148ee53033710b4c4b00f01=0D https://github.com/qemu/qemu/commit/3cf7ce4337aebf8f9148ee53033710b= 4c4b00f01=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Do not abort on invalid access=0D =0D Replace fprintf with qemu_log_mask LOG_GUEST_ERROR as the intention is=0D= to handle valid accesses in these functions so if we get to these=0D errors then it's an invalid access. Do not abort as that would allow=0D the guest to crash QEMU and the practice in other devices is to not do=0D= that just log and ignore the invalid access. While at it also simplify=0D= the complex bit ops to check if a return value was set which can be=0D done much simpler and clearer.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <6b46045141d6d9cc32e17c223896fa1116384796.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 2f6df13748a7de19ab150a52af846f70303746e5=0D https://github.com/qemu/qemu/commit/2f6df13748a7de19ab150a52af846f7= 0303746e5=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Rename type sh_serial_state to SHSerialState=0D =0D Coding style says types should be camel case.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <0f185653528c99eeeb2b4e4afb8b818d93298c20.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 5b344b02e1813c6823e76ea981a56e7b432985a4=0D https://github.com/qemu/qemu/commit/5b344b02e1813c6823e76ea981a56e7= b432985a4=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Embed QEMUTimer in state struct=0D =0D Instead of allocating timer with timer_new store it directly in the=0D state struct. This makes it simpler to free it together with the device.=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 017f77bbf75ef6c9b69188a150020013e6d5d8ad=0D https://github.com/qemu/qemu/commit/017f77bbf75ef6c9b69188a15002001= 3e6d5d8ad=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Split off sh_serial_reset() from sh_serial_init()=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: beeb520925d54f5c69c66656a96dc68de0eec9a4=0D https://github.com/qemu/qemu/commit/beeb520925d54f5c69c66656a96dc68= de0eec9a4=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/sh4/sh7750.c=0D M include/hw/sh4/sh.h=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: QOM-ify=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <92902ba34fdf2c8c62232365fbb6531b1036d557.1635541329.git.bala= ton@eik.bme.hu>=0D [PMD: Use g_strdup() to initialize DeviceState::id]=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 44ae04f0328d0726c1b1666600d0aa8da604a341=0D https://github.com/qemu/qemu/commit/44ae04f0328d0726c1b1666600d0aa8= da604a341=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D =0D Log Message:=0D -----------=0D hw/char/sh_serial: Add device id to trace output=0D =0D Normally there are at least two sh_serial instances. Add device id to=0D trace messages to make it clear which instance they belong to=0D otherwise its not possible to tell which serial device is accessed.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: cfaf2806e87b0eb962866e041a0fd75a524394d8=0D https://github.com/qemu/qemu/commit/cfaf2806e87b0eb962866e041a0fd75= a524394d8=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Use existing macro instead of local one=0D =0D The INTC_A7 local macro does the same as the A7ADDR from=0D include/sh/sh.h so use the latter and drop the local macro definition.=0D= =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: <53f033477c73b7c9b021d36033c590416d6199c7.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: dc6f1734b704e5563e4c512393e2629799093681=0D https://github.com/qemu/qemu/commit/dc6f1734b704e5563e4c512393e2629= 799093681=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Turn some defines into an enum=0D =0D Turn the INTC_MODE defines into an enum and clean up the function=0D returning these to make it clearer by removing nested ifs and=0D superfluous parenthesis. The one remaining #define is a flag which is=0D moved further apart by changing its value from 8 to 0x80 to leave some=0D= spare bits as this is or-ed with the enum value at some places.=0D =0D Signed-off-by: BALATON Zoltan =0D Message-Id: <4adf4e1ac9d2e728e5a536c69e310d77f0c4455a.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 81d18cd48a87205bed159586fd3ca524a36bd49a=0D https://github.com/qemu/qemu/commit/81d18cd48a87205bed159586fd3ca52= 4a36bd49a=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Rename iomem region=0D =0D Rename the iomem region to "intc" from "interrupt-controller" which=0D makes the info mtree output less wide as it is already too wide=0D because of all the aliases. Also drop the format macro which was only=0D used twice in close proximity so we can just use the literal string=0D instead without a macro definition.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 92d1d3ada11dfb338bb96b6405d6938901182488=0D https://github.com/qemu/qemu/commit/92d1d3ada11dfb338bb96b6405d6938= 901182488=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Drop another useless macro=0D =0D The INT_REG_PARAMS macro was only used a few times within one function=0D= on adjacent lines and is actually more complex than writing out the=0D parameters so simplify it by expanding the macro at call sites and=0D dropping the #define.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Reviewed-by: Richard Henderson =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 51cb902baca1ccfba270fa5a1f230d85301a68e6=0D https://github.com/qemu/qemu/commit/51cb902baca1ccfba270fa5a1f230d8= 5301a68e6=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Move sh_intc_register() closer to its only user=0D =0D The sh_intc_register() function is only used at one place. Move them=0D together so it's easier to see what's going on.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <49f2742bc67cba7164385fafad204ab1e1bd3a0b.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 46ea1f8236ffdf80c52dad79ee7d2dc18ed5eda1=0D https://github.com/qemu/qemu/commit/46ea1f8236ffdf80c52dad79ee7d2dc= 18ed5eda1=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Remove excessive parenthesis=0D =0D Drop unneded parenthesis and split up one complex expression to write=0D it with less brackets so it's easier to follow.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 12201fe38a592695eea647c9600d08a4622c1431=0D https://github.com/qemu/qemu/commit/12201fe38a592695eea647c9600d08a= 4622c1431=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Use array index instead of pointer arithmetics=0D =0D Address of element i is one word thus clearer than array + i.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 9b12fb10b731d8d9cbb6cc0bf200d1c48de7f20d=0D https://github.com/qemu/qemu/commit/9b12fb10b731d8d9cbb6cc0bf200d1c= 48de7f20d=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D M hw/sh4/sh7750.c=0D M include/hw/sh4/sh_intc.h=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Inline and drop sh_intc_source() function=0D =0D This function is very simple and provides no advantage. Call sites=0D become simpler without it so just write it in line and drop the=0D separate function.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 85208f7a9756948ed16ef09d7982584528904430=0D https://github.com/qemu/qemu/commit/85208f7a9756948ed16ef09d7982584= 528904430=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Replace abort() with g_assert_not_reached()=0D =0D All the places that call abort should not happen which is better=0D marked by g_assert_not_reached.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <039e6a784532f2af27f8adeafdb8e0391722f567.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 418a221c2b8a97838980e61cdfef356ec6976e4b=0D https://github.com/qemu/qemu/commit/418a221c2b8a97838980e61cdfef356= ec6976e4b=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Avoid using continue in loops=0D =0D Instead of if !expr continue else do something it is more straight=0D forward to say if expr then do something, especially if the action is=0D just a few lines. Remove such uses of continue to make the code easier=0D= to follow.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Richard Henderson =0D Message-Id: <0efaa5e7a1a3ee11f82b3bb1942c287576c67f8b.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 36cf5ee8852a3aac56be160ad87cc49974278c46=0D https://github.com/qemu/qemu/commit/36cf5ee8852a3aac56be160ad87cc49= 974278c46=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Simplify allocating sources array=0D =0D Use g_new0 instead of g_malloc0 and avoid some unneeded temporary=0D variable assignments.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <72efc4f2c4ff8b96848d03dca08e4541ee4076f6.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 32331787896104022deb024906f1cca9606cfdc6=0D https://github.com/qemu/qemu/commit/32331787896104022deb024906f1cca= 9606cfdc6=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/intc/sh_intc.c=0D =0D Log Message:=0D -----------=0D hw/intc/sh_intc: Remove unneeded local variable initialisers=0D =0D The sh_intc_locate function will either init these or not return so no=0D= need to initialise them.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <15e04aa665c68ab5df47bbf505346d413be2fc1c.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 5d9b737e5144baff1c3a4205ff57d974a347c204=0D https://github.com/qemu/qemu/commit/5d9b737e5144baff1c3a4205ff57d97= 4a347c204=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Rename sh_timer_state to SHTimerState=0D =0D According to coding style types should be camel case, also remove=0D unneded casts from void *.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: f64ccec414e72754921c25de6395d7e3b10a0c9e=0D https://github.com/qemu/qemu/commit/f64ccec414e72754921c25de6395d7e= 3b10a0c9e=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Do not wrap lines that are not too long=0D =0D It's more readable to keep things on one line if it fits the length limit= .=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: <97bc2a38991f33fd0c8cc2e4d0a3a29b20c47d1f.1635541329.git.bala= ton@eik.bme.hu>=0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 65307c7792a50bffe036423ec21107f4fb9c74e3=0D https://github.com/qemu/qemu/commit/65307c7792a50bffe036423ec21107f= 4fb9c74e3=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Fix timer memory region size=0D =0D The timer unit only has registers that fit in a region 0x30 bytes=0D long. No need to have the timer region larger than that.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: 46e44759fc24a05e338cd37a735b4aad5422e717=0D https://github.com/qemu/qemu/commit/46e44759fc24a05e338cd37a735b4aa= d5422e717=0D Author: BALATON Zoltan =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/timer/sh_timer.c=0D =0D Log Message:=0D -----------=0D hw/timer/sh_timer: Remove use of hw_error=0D =0D The hw_error function calls abort and is not meant to be used by=0D devices. Use qemu_log_mask instead to log and ignore invalid accesses.=0D= Also fix format strings to allow dropping type casts of hwaddr and use=0D= __func__ instead of hard coding function name in the message which=0D were wrong in two cases.=0D =0D Signed-off-by: BALATON Zoltan =0D Reviewed-by: Philippe Mathieu-Daud=C3=A9 =0D Message-Id: =0D Signed-off-by: Philippe Mathieu-Daud=C3=A9 =0D =0D =0D Commit: af531756d25541a1b3b3d9a14e72e7fedd941a2e=0D https://github.com/qemu/qemu/commit/af531756d25541a1b3b3d9a14e72e7f= edd941a2e=0D Author: Richard Henderson =0D Date: 2021-10-30 (Sat, 30 Oct 2021)=0D =0D Changed paths:=0D M hw/char/sh_serial.c=0D M hw/char/trace-events=0D M hw/intc/sh_intc.c=0D M hw/intc/trace-events=0D M hw/pci-host/sh_pci.c=0D M hw/sh4/r2d.c=0D M hw/sh4/sh7750.c=0D M hw/sh4/sh7750_regnames.c=0D M hw/sh4/sh7750_regs.h=0D M hw/sh4/shix.c=0D A hw/sh4/trace-events=0D A hw/sh4/trace.h=0D M hw/timer/sh_timer.c=0D M hw/timer/trace-events=0D M include/hw/sh4/sh.h=0D M include/hw/sh4/sh_intc.h=0D M meson.build=0D =0D Log Message:=0D -----------=0D Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' int= o staging=0D =0D Renesas SH-4 patches queue=0D =0D Patches from Zoltan:=0D - Various clean up to align the code style with the rest of the code base= =0D - QOM'ify the SH_SERIAL device=0D - Modify few memory region size to better match the hardware manual=0D =0D # gpg: Signature made Sat 30 Oct 2021 10:05:03 AM PDT=0D # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC= 0DE=0D # gpg: Good signature from "Philippe Mathieu-Daud=C3=A9 (F4BUG) " [full]=0D =0D * remotes/philmd/tags/renesas-20211030: (30 commits)=0D hw/timer/sh_timer: Remove use of hw_error=0D hw/timer/sh_timer: Fix timer memory region size=0D hw/timer/sh_timer: Do not wrap lines that are not too long=0D hw/timer/sh_timer: Rename sh_timer_state to SHTimerState=0D hw/intc/sh_intc: Remove unneeded local variable initialisers=0D hw/intc/sh_intc: Simplify allocating sources array=0D hw/intc/sh_intc: Avoid using continue in loops=0D hw/intc/sh_intc: Replace abort() with g_assert_not_reached()=0D hw/intc/sh_intc: Inline and drop sh_intc_source() function=0D hw/intc/sh_intc: Use array index instead of pointer arithmetics=0D hw/intc/sh_intc: Remove excessive parenthesis=0D hw/intc/sh_intc: Move sh_intc_register() closer to its only user=0D hw/intc/sh_intc: Drop another useless macro=0D hw/intc/sh_intc: Rename iomem region=0D hw/intc/sh_intc: Turn some defines into an enum=0D hw/intc/sh_intc: Use existing macro instead of local one=0D hw/char/sh_serial: Add device id to trace output=0D hw/char/sh_serial: QOM-ify=0D hw/char/sh_serial: Split off sh_serial_reset() from sh_serial_init()=0D= hw/char/sh_serial: Embed QEMUTimer in state struct=0D ...=0D =0D Signed-off-by: Richard Henderson =0D =0D =0D Compare: https://github.com/qemu/qemu/compare/dd61b91c080c...af531756d255= =0D